1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_H_
35 #define _I40E_ADMINQ_H_
37 #include "i40e_osdep.h"
38 #include "i40e_status.h"
39 #include "i40e_adminq_cmd.h"
41 #define I40E_ADMINQ_DESC(R, i) \
42 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
44 #define I40E_ADMINQ_DESC_ALIGNMENT 4096
46 struct i40e_adminq_ring {
47 struct i40e_virt_mem dma_head; /* space for dma structures */
48 struct i40e_dma_mem desc_buf; /* descriptor ring memory */
49 struct i40e_virt_mem cmd_buf; /* command buffer memory */
52 struct i40e_dma_mem *asq_bi;
53 struct i40e_dma_mem *arq_bi;
56 u16 count; /* Number of descriptors */
57 u16 rx_buf_len; /* Admin Receive Queue buffer length */
59 /* used for interrupt processing */
63 /* used for queue tracking */
71 /* ASQ transaction details */
72 struct i40e_asq_cmd_details {
73 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
81 #define I40E_ADMINQ_DETAILS(R, i) \
82 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
84 /* ARQ event information */
85 struct i40e_arq_event_info {
86 struct i40e_aq_desc desc;
92 /* Admin Queue information */
93 struct i40e_adminq_info {
94 struct i40e_adminq_ring arq; /* receive queue */
95 struct i40e_adminq_ring asq; /* send queue */
96 u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
97 u16 num_arq_entries; /* receive queue depth */
98 u16 num_asq_entries; /* send queue depth */
99 u16 arq_buf_size; /* receive queue buffer size */
100 u16 asq_buf_size; /* send queue buffer size */
101 u16 fw_maj_ver; /* firmware major version */
102 u16 fw_min_ver; /* firmware minor version */
103 u32 fw_build; /* firmware build number */
104 u16 api_maj_ver; /* api major version */
105 u16 api_min_ver; /* api minor version */
106 bool nvm_release_on_done;
108 struct i40e_spinlock asq_spinlock; /* Send queue spinlock */
109 struct i40e_spinlock arq_spinlock; /* Receive queue spinlock */
111 /* last status values on send and receive queues */
112 enum i40e_admin_queue_err asq_last_status;
113 enum i40e_admin_queue_err arq_last_status;
117 * i40e_aq_rc_to_posix - convert errors to user-land codes
118 * aq_rc: AdminQ error code to convert
120 STATIC inline int i40e_aq_rc_to_posix(int aq_ret, u16 aq_rc)
122 int aq_to_posix[] = {
123 0, /* I40E_AQ_RC_OK */
124 -EPERM, /* I40E_AQ_RC_EPERM */
125 -ENOENT, /* I40E_AQ_RC_ENOENT */
126 -ESRCH, /* I40E_AQ_RC_ESRCH */
127 -EINTR, /* I40E_AQ_RC_EINTR */
128 -EIO, /* I40E_AQ_RC_EIO */
129 -ENXIO, /* I40E_AQ_RC_ENXIO */
130 -E2BIG, /* I40E_AQ_RC_E2BIG */
131 -EAGAIN, /* I40E_AQ_RC_EAGAIN */
132 -ENOMEM, /* I40E_AQ_RC_ENOMEM */
133 -EACCES, /* I40E_AQ_RC_EACCES */
134 -EFAULT, /* I40E_AQ_RC_EFAULT */
135 -EBUSY, /* I40E_AQ_RC_EBUSY */
136 -EEXIST, /* I40E_AQ_RC_EEXIST */
137 -EINVAL, /* I40E_AQ_RC_EINVAL */
138 -ENOTTY, /* I40E_AQ_RC_ENOTTY */
139 -ENOSPC, /* I40E_AQ_RC_ENOSPC */
140 -ENOSYS, /* I40E_AQ_RC_ENOSYS */
141 -ERANGE, /* I40E_AQ_RC_ERANGE */
142 -EPIPE, /* I40E_AQ_RC_EFLUSHED */
143 -ESPIPE, /* I40E_AQ_RC_BAD_ADDR */
144 -EROFS, /* I40E_AQ_RC_EMODE */
145 -EFBIG, /* I40E_AQ_RC_EFBIG */
148 /* aq_rc is invalid if AQ timed out */
149 if (aq_ret == I40E_ERR_ADMIN_QUEUE_TIMEOUT)
152 if (aq_rc >= (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0])))
154 return aq_to_posix[aq_rc];
157 /* general information */
158 #define I40E_AQ_LARGE_BUF 512
159 #define I40E_ASQ_CMD_TIMEOUT 250 /* msecs */
161 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
164 #endif /* _I40E_ADMINQ_H_ */