1 /*******************************************************************************
3 Copyright (c) 2013 - 2014, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_H_
35 #define _I40E_ADMINQ_H_
37 #include "i40e_osdep.h"
38 #include "i40e_adminq_cmd.h"
40 #define I40E_ADMINQ_DESC(R, i) \
41 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
43 #define I40E_ADMINQ_DESC_ALIGNMENT 4096
45 struct i40e_adminq_ring {
46 struct i40e_virt_mem dma_head; /* space for dma structures */
47 struct i40e_dma_mem desc_buf; /* descriptor ring memory */
48 struct i40e_virt_mem cmd_buf; /* command buffer memory */
51 struct i40e_dma_mem *asq_bi;
52 struct i40e_dma_mem *arq_bi;
55 u16 count; /* Number of descriptors */
56 u16 rx_buf_len; /* Admin Receive Queue buffer length */
58 /* used for interrupt processing */
62 /* used for queue tracking */
70 /* ASQ transaction details */
71 struct i40e_asq_cmd_details {
72 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
80 #define I40E_ADMINQ_DETAILS(R, i) \
81 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
83 /* ARQ event information */
84 struct i40e_arq_event_info {
85 struct i40e_aq_desc desc;
91 /* Admin Queue information */
92 struct i40e_adminq_info {
93 struct i40e_adminq_ring arq; /* receive queue */
94 struct i40e_adminq_ring asq; /* send queue */
95 u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
96 u16 num_arq_entries; /* receive queue depth */
97 u16 num_asq_entries; /* send queue depth */
98 u16 arq_buf_size; /* receive queue buffer size */
99 u16 asq_buf_size; /* send queue buffer size */
100 u16 fw_maj_ver; /* firmware major version */
101 u16 fw_min_ver; /* firmware minor version */
102 u16 api_maj_ver; /* api major version */
103 u16 api_min_ver; /* api minor version */
105 bool nvm_release_on_done;
107 struct i40e_spinlock asq_spinlock; /* Send queue spinlock */
108 struct i40e_spinlock arq_spinlock; /* Receive queue spinlock */
110 /* last status values on send and receive queues */
111 enum i40e_admin_queue_err asq_last_status;
112 enum i40e_admin_queue_err arq_last_status;
116 * i40e_aq_rc_to_posix - convert errors to user-land codes
117 * aq_rc: AdminQ error code to convert
119 STATIC inline int i40e_aq_rc_to_posix(u16 aq_rc)
121 int aq_to_posix[] = {
122 0, /* I40E_AQ_RC_OK */
123 -EPERM, /* I40E_AQ_RC_EPERM */
124 -ENOENT, /* I40E_AQ_RC_ENOENT */
125 -ESRCH, /* I40E_AQ_RC_ESRCH */
126 -EINTR, /* I40E_AQ_RC_EINTR */
127 -EIO, /* I40E_AQ_RC_EIO */
128 -ENXIO, /* I40E_AQ_RC_ENXIO */
129 -E2BIG, /* I40E_AQ_RC_E2BIG */
130 -EAGAIN, /* I40E_AQ_RC_EAGAIN */
131 -ENOMEM, /* I40E_AQ_RC_ENOMEM */
132 -EACCES, /* I40E_AQ_RC_EACCES */
133 -EFAULT, /* I40E_AQ_RC_EFAULT */
134 -EBUSY, /* I40E_AQ_RC_EBUSY */
135 -EEXIST, /* I40E_AQ_RC_EEXIST */
136 -EINVAL, /* I40E_AQ_RC_EINVAL */
137 -ENOTTY, /* I40E_AQ_RC_ENOTTY */
138 -ENOSPC, /* I40E_AQ_RC_ENOSPC */
139 -ENOSYS, /* I40E_AQ_RC_ENOSYS */
140 -ERANGE, /* I40E_AQ_RC_ERANGE */
141 -EPIPE, /* I40E_AQ_RC_EFLUSHED */
142 -ESPIPE, /* I40E_AQ_RC_BAD_ADDR */
143 -EROFS, /* I40E_AQ_RC_EMODE */
144 -EFBIG, /* I40E_AQ_RC_EFBIG */
147 return aq_to_posix[aq_rc];
150 /* general information */
151 #define I40E_AQ_LARGE_BUF 512
152 #define I40E_ASQ_CMD_TIMEOUT 100 /* msecs */
154 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
157 #endif /* _I40E_ADMINQ_H_ */