1 /*******************************************************************************
3 Copyright (c) 2013 - 2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 hw->mac.type = I40E_MAC_XL710;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
87 * @hw: debug mask related to admin queue
89 * @desc: pointer to admin queue descriptor
90 * @buffer: pointer to command buffer
92 * Dumps debug log about adminq command with descriptor contents.
94 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
98 u8 *aq_buffer = (u8 *)buffer;
102 if ((!(mask & hw->debug_mask)) || (desc == NULL))
106 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
107 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
109 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
110 aq_desc->cookie_high, aq_desc->cookie_low);
111 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
112 aq_desc->params.internal.param0,
113 aq_desc->params.internal.param1);
114 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
115 aq_desc->params.external.addr_high,
116 aq_desc->params.external.addr_low);
118 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
119 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
120 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
121 for (i = 0; i < LE16_TO_CPU(aq_desc->datalen); i++) {
122 data[((i % 16) / 4)] |=
123 ((u32)aq_buffer[i]) << (8 * (i % 4));
124 if ((i % 16) == 15) {
126 "\t0x%04X %08X %08X %08X %08X\n",
127 i - 15, data[0], data[1], data[2],
129 i40e_memset(data, 0, sizeof(data),
134 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
135 i - (i % 16), data[0], data[1], data[2],
141 * i40e_check_asq_alive
142 * @hw: pointer to the hw struct
144 * Returns true if Queue is enabled else false.
146 bool i40e_check_asq_alive(struct i40e_hw *hw)
149 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
155 * i40e_aq_queue_shutdown
156 * @hw: pointer to the hw struct
157 * @unloading: is the driver unloading itself
159 * Tell the Firmware that we're shutting down the AdminQ and whether
160 * or not the driver is unloading as well.
162 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
165 struct i40e_aq_desc desc;
166 struct i40e_aqc_queue_shutdown *cmd =
167 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
168 enum i40e_status_code status;
170 i40e_fill_default_direct_cmd_desc(&desc,
171 i40e_aqc_opc_queue_shutdown);
174 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
175 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
180 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
181 * hardware to a bit-field that can be used by SW to more easily determine the
184 * Macros are used to shorten the table lines and make this table human
187 * We store the PTYPE in the top byte of the bit field - this is just so that
188 * we can check that the table doesn't have a row missing, as the index into
189 * the table should be the PTYPE.
193 * IF NOT i40e_ptype_lookup[ptype].known
196 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
197 * Use the rest of the fields to look at the tunnels, inner protocols, etc
199 * Use the enum i40e_rx_l2_ptype to decode the packet type
203 /* macro to make the table lines short */
204 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
207 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
208 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
209 I40E_RX_PTYPE_##OUTER_FRAG, \
210 I40E_RX_PTYPE_TUNNEL_##T, \
211 I40E_RX_PTYPE_TUNNEL_END_##TE, \
212 I40E_RX_PTYPE_##TEF, \
213 I40E_RX_PTYPE_INNER_PROT_##I, \
214 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
216 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
217 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
219 /* shorter macros makes the table fit but are terse */
220 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
221 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
222 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
224 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
225 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
226 /* L2 Packet types */
227 I40E_PTT_UNUSED_ENTRY(0),
228 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
229 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
230 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
231 I40E_PTT_UNUSED_ENTRY(4),
232 I40E_PTT_UNUSED_ENTRY(5),
233 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
235 I40E_PTT_UNUSED_ENTRY(8),
236 I40E_PTT_UNUSED_ENTRY(9),
237 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
239 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 /* Non Tunneled IPv4 */
251 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
254 I40E_PTT_UNUSED_ENTRY(25),
255 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
256 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
257 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
260 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
261 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
262 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(32),
264 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
265 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
266 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
269 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
270 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
271 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(39),
273 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
274 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
275 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
277 /* IPv4 --> GRE/NAT */
278 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
280 /* IPv4 --> GRE/NAT --> IPv4 */
281 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
282 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
283 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
284 I40E_PTT_UNUSED_ENTRY(47),
285 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
286 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
287 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
289 /* IPv4 --> GRE/NAT --> IPv6 */
290 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
291 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
292 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(54),
294 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
295 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
296 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> MAC */
299 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
301 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
302 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
303 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
304 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
305 I40E_PTT_UNUSED_ENTRY(62),
306 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
307 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
308 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
310 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
311 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
312 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
313 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(69),
315 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
316 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
317 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT --> MAC/VLAN */
320 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
322 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
323 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
324 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
325 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
326 I40E_PTT_UNUSED_ENTRY(77),
327 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
328 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
329 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
331 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
332 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
333 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
334 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(84),
336 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
337 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
338 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
340 /* Non Tunneled IPv6 */
341 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
342 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
343 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
344 I40E_PTT_UNUSED_ENTRY(91),
345 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
346 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
347 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
350 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
351 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
352 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
353 I40E_PTT_UNUSED_ENTRY(98),
354 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
355 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
356 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
359 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
360 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
361 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(105),
363 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
364 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
365 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
367 /* IPv6 --> GRE/NAT */
368 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
370 /* IPv6 --> GRE/NAT -> IPv4 */
371 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
372 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
373 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
374 I40E_PTT_UNUSED_ENTRY(113),
375 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
376 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
377 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
379 /* IPv6 --> GRE/NAT -> IPv6 */
380 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
381 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
382 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(120),
384 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
385 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
386 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> MAC */
389 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
391 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
392 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
393 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
394 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
395 I40E_PTT_UNUSED_ENTRY(128),
396 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
397 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
398 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
401 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
402 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
403 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(135),
405 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
406 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
407 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC/VLAN */
410 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
413 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
414 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
415 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
416 I40E_PTT_UNUSED_ENTRY(143),
417 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
418 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
419 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
422 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
423 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
424 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(150),
426 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
427 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
428 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
431 I40E_PTT_UNUSED_ENTRY(154),
432 I40E_PTT_UNUSED_ENTRY(155),
433 I40E_PTT_UNUSED_ENTRY(156),
434 I40E_PTT_UNUSED_ENTRY(157),
435 I40E_PTT_UNUSED_ENTRY(158),
436 I40E_PTT_UNUSED_ENTRY(159),
438 I40E_PTT_UNUSED_ENTRY(160),
439 I40E_PTT_UNUSED_ENTRY(161),
440 I40E_PTT_UNUSED_ENTRY(162),
441 I40E_PTT_UNUSED_ENTRY(163),
442 I40E_PTT_UNUSED_ENTRY(164),
443 I40E_PTT_UNUSED_ENTRY(165),
444 I40E_PTT_UNUSED_ENTRY(166),
445 I40E_PTT_UNUSED_ENTRY(167),
446 I40E_PTT_UNUSED_ENTRY(168),
447 I40E_PTT_UNUSED_ENTRY(169),
449 I40E_PTT_UNUSED_ENTRY(170),
450 I40E_PTT_UNUSED_ENTRY(171),
451 I40E_PTT_UNUSED_ENTRY(172),
452 I40E_PTT_UNUSED_ENTRY(173),
453 I40E_PTT_UNUSED_ENTRY(174),
454 I40E_PTT_UNUSED_ENTRY(175),
455 I40E_PTT_UNUSED_ENTRY(176),
456 I40E_PTT_UNUSED_ENTRY(177),
457 I40E_PTT_UNUSED_ENTRY(178),
458 I40E_PTT_UNUSED_ENTRY(179),
460 I40E_PTT_UNUSED_ENTRY(180),
461 I40E_PTT_UNUSED_ENTRY(181),
462 I40E_PTT_UNUSED_ENTRY(182),
463 I40E_PTT_UNUSED_ENTRY(183),
464 I40E_PTT_UNUSED_ENTRY(184),
465 I40E_PTT_UNUSED_ENTRY(185),
466 I40E_PTT_UNUSED_ENTRY(186),
467 I40E_PTT_UNUSED_ENTRY(187),
468 I40E_PTT_UNUSED_ENTRY(188),
469 I40E_PTT_UNUSED_ENTRY(189),
471 I40E_PTT_UNUSED_ENTRY(190),
472 I40E_PTT_UNUSED_ENTRY(191),
473 I40E_PTT_UNUSED_ENTRY(192),
474 I40E_PTT_UNUSED_ENTRY(193),
475 I40E_PTT_UNUSED_ENTRY(194),
476 I40E_PTT_UNUSED_ENTRY(195),
477 I40E_PTT_UNUSED_ENTRY(196),
478 I40E_PTT_UNUSED_ENTRY(197),
479 I40E_PTT_UNUSED_ENTRY(198),
480 I40E_PTT_UNUSED_ENTRY(199),
482 I40E_PTT_UNUSED_ENTRY(200),
483 I40E_PTT_UNUSED_ENTRY(201),
484 I40E_PTT_UNUSED_ENTRY(202),
485 I40E_PTT_UNUSED_ENTRY(203),
486 I40E_PTT_UNUSED_ENTRY(204),
487 I40E_PTT_UNUSED_ENTRY(205),
488 I40E_PTT_UNUSED_ENTRY(206),
489 I40E_PTT_UNUSED_ENTRY(207),
490 I40E_PTT_UNUSED_ENTRY(208),
491 I40E_PTT_UNUSED_ENTRY(209),
493 I40E_PTT_UNUSED_ENTRY(210),
494 I40E_PTT_UNUSED_ENTRY(211),
495 I40E_PTT_UNUSED_ENTRY(212),
496 I40E_PTT_UNUSED_ENTRY(213),
497 I40E_PTT_UNUSED_ENTRY(214),
498 I40E_PTT_UNUSED_ENTRY(215),
499 I40E_PTT_UNUSED_ENTRY(216),
500 I40E_PTT_UNUSED_ENTRY(217),
501 I40E_PTT_UNUSED_ENTRY(218),
502 I40E_PTT_UNUSED_ENTRY(219),
504 I40E_PTT_UNUSED_ENTRY(220),
505 I40E_PTT_UNUSED_ENTRY(221),
506 I40E_PTT_UNUSED_ENTRY(222),
507 I40E_PTT_UNUSED_ENTRY(223),
508 I40E_PTT_UNUSED_ENTRY(224),
509 I40E_PTT_UNUSED_ENTRY(225),
510 I40E_PTT_UNUSED_ENTRY(226),
511 I40E_PTT_UNUSED_ENTRY(227),
512 I40E_PTT_UNUSED_ENTRY(228),
513 I40E_PTT_UNUSED_ENTRY(229),
515 I40E_PTT_UNUSED_ENTRY(230),
516 I40E_PTT_UNUSED_ENTRY(231),
517 I40E_PTT_UNUSED_ENTRY(232),
518 I40E_PTT_UNUSED_ENTRY(233),
519 I40E_PTT_UNUSED_ENTRY(234),
520 I40E_PTT_UNUSED_ENTRY(235),
521 I40E_PTT_UNUSED_ENTRY(236),
522 I40E_PTT_UNUSED_ENTRY(237),
523 I40E_PTT_UNUSED_ENTRY(238),
524 I40E_PTT_UNUSED_ENTRY(239),
526 I40E_PTT_UNUSED_ENTRY(240),
527 I40E_PTT_UNUSED_ENTRY(241),
528 I40E_PTT_UNUSED_ENTRY(242),
529 I40E_PTT_UNUSED_ENTRY(243),
530 I40E_PTT_UNUSED_ENTRY(244),
531 I40E_PTT_UNUSED_ENTRY(245),
532 I40E_PTT_UNUSED_ENTRY(246),
533 I40E_PTT_UNUSED_ENTRY(247),
534 I40E_PTT_UNUSED_ENTRY(248),
535 I40E_PTT_UNUSED_ENTRY(249),
537 I40E_PTT_UNUSED_ENTRY(250),
538 I40E_PTT_UNUSED_ENTRY(251),
539 I40E_PTT_UNUSED_ENTRY(252),
540 I40E_PTT_UNUSED_ENTRY(253),
541 I40E_PTT_UNUSED_ENTRY(254),
542 I40E_PTT_UNUSED_ENTRY(255)
548 * i40e_init_shared_code - Initialize the shared code
549 * @hw: pointer to hardware structure
551 * This assigns the MAC type and PHY code and inits the NVM.
552 * Does not touch the hardware. This function must be called prior to any
553 * other function in the shared code. The i40e_hw structure should be
554 * memset to 0 prior to calling this function. The following fields in
555 * hw structure should be filled in prior to calling this function:
556 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
557 * subsystem_vendor_id, and revision_id
559 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
561 enum i40e_status_code status = I40E_SUCCESS;
564 DEBUGFUNC("i40e_init_shared_code");
566 i40e_set_mac_type(hw);
568 switch (hw->mac.type) {
572 return I40E_ERR_DEVICE_NOT_SUPPORTED;
575 hw->phy.get_link_info = true;
577 /* Determine port number */
578 reg = rd32(hw, I40E_PFGEN_PORTNUM);
579 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
580 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
583 /* Determine the PF number based on the PCI fn */
584 reg = rd32(hw, I40E_GLPCI_CAPSUP);
585 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
586 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
588 hw->pf_id = (u8)hw->bus.func;
590 status = i40e_init_nvm(hw);
595 * i40e_aq_mac_address_read - Retrieve the MAC addresses
596 * @hw: pointer to the hw struct
597 * @flags: a return indicator of what addresses were added to the addr store
598 * @addrs: the requestor's mac addr store
599 * @cmd_details: pointer to command details structure or NULL
601 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
603 struct i40e_aqc_mac_address_read_data *addrs,
604 struct i40e_asq_cmd_details *cmd_details)
606 struct i40e_aq_desc desc;
607 struct i40e_aqc_mac_address_read *cmd_data =
608 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
609 enum i40e_status_code status;
611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
612 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
614 status = i40e_asq_send_command(hw, &desc, addrs,
615 sizeof(*addrs), cmd_details);
616 *flags = LE16_TO_CPU(cmd_data->command_flags);
622 * i40e_aq_mac_address_write - Change the MAC addresses
623 * @hw: pointer to the hw struct
624 * @flags: indicates which MAC to be written
625 * @mac_addr: address to write
626 * @cmd_details: pointer to command details structure or NULL
628 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
629 u16 flags, u8 *mac_addr,
630 struct i40e_asq_cmd_details *cmd_details)
632 struct i40e_aq_desc desc;
633 struct i40e_aqc_mac_address_write *cmd_data =
634 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
635 enum i40e_status_code status;
637 i40e_fill_default_direct_cmd_desc(&desc,
638 i40e_aqc_opc_mac_address_write);
639 cmd_data->command_flags = CPU_TO_LE16(flags);
640 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
641 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
642 ((u32)mac_addr[3] << 16) |
643 ((u32)mac_addr[4] << 8) |
646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
652 * i40e_get_mac_addr - get MAC address
653 * @hw: pointer to the HW structure
654 * @mac_addr: pointer to MAC address
656 * Reads the adapter's MAC address from register
658 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
660 struct i40e_aqc_mac_address_read_data addrs;
661 enum i40e_status_code status;
664 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
666 if (flags & I40E_AQC_LAN_ADDR_VALID)
667 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
673 * i40e_get_port_mac_addr - get Port MAC address
674 * @hw: pointer to the HW structure
675 * @mac_addr: pointer to Port MAC address
677 * Reads the adapter's Port MAC address
679 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
681 struct i40e_aqc_mac_address_read_data addrs;
682 enum i40e_status_code status;
685 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
689 if (flags & I40E_AQC_PORT_ADDR_VALID)
690 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
692 status = I40E_ERR_INVALID_MAC_ADDR;
698 * i40e_pre_tx_queue_cfg - pre tx queue configure
699 * @hw: pointer to the HW structure
700 * @queue: target pf queue index
701 * @enable: state change request
703 * Handles hw requirement to indicate intention to enable
704 * or disable target queue.
706 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
708 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
712 if (abs_queue_idx >= 128) {
713 reg_block = abs_queue_idx / 128;
714 abs_queue_idx %= 128;
717 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
718 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
719 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
722 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
724 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
726 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
730 * i40e_validate_mac_addr - Validate unicast MAC address
731 * @mac_addr: pointer to MAC address
733 * Tests a MAC address to ensure it is a valid Individual Address
735 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
737 enum i40e_status_code status = I40E_SUCCESS;
739 DEBUGFUNC("i40e_validate_mac_addr");
741 /* Broadcast addresses ARE multicast addresses
742 * Make sure it is not a multicast address
743 * Reject the zero address
745 if (I40E_IS_MULTICAST(mac_addr) ||
746 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
747 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
748 status = I40E_ERR_INVALID_MAC_ADDR;
754 * i40e_get_media_type - Gets media type
755 * @hw: pointer to the hardware structure
757 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
759 enum i40e_media_type media;
761 switch (hw->phy.link_info.phy_type) {
762 case I40E_PHY_TYPE_10GBASE_SR:
763 case I40E_PHY_TYPE_10GBASE_LR:
764 case I40E_PHY_TYPE_40GBASE_SR4:
765 case I40E_PHY_TYPE_40GBASE_LR4:
766 media = I40E_MEDIA_TYPE_FIBER;
768 case I40E_PHY_TYPE_100BASE_TX:
769 case I40E_PHY_TYPE_1000BASE_T:
770 case I40E_PHY_TYPE_10GBASE_T:
771 media = I40E_MEDIA_TYPE_BASET;
773 case I40E_PHY_TYPE_10GBASE_CR1_CU:
774 case I40E_PHY_TYPE_40GBASE_CR4_CU:
775 case I40E_PHY_TYPE_10GBASE_CR1:
776 case I40E_PHY_TYPE_40GBASE_CR4:
777 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
778 media = I40E_MEDIA_TYPE_DA;
780 case I40E_PHY_TYPE_1000BASE_KX:
781 case I40E_PHY_TYPE_10GBASE_KX4:
782 case I40E_PHY_TYPE_10GBASE_KR:
783 case I40E_PHY_TYPE_40GBASE_KR4:
784 media = I40E_MEDIA_TYPE_BACKPLANE;
786 case I40E_PHY_TYPE_SGMII:
787 case I40E_PHY_TYPE_XAUI:
788 case I40E_PHY_TYPE_XFI:
789 case I40E_PHY_TYPE_XLAUI:
790 case I40E_PHY_TYPE_XLPPI:
792 media = I40E_MEDIA_TYPE_UNKNOWN;
799 #define I40E_PF_RESET_WAIT_COUNT 100
801 * i40e_pf_reset - Reset the PF
802 * @hw: pointer to the hardware structure
804 * Assuming someone else has triggered a global reset,
805 * assure the global reset is complete and then reset the PF
807 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
814 /* Poll for Global Reset steady state in case of recent GRST.
815 * The grst delay value is in 100ms units, and we'll wait a
816 * couple counts longer to be sure we don't just miss the end.
818 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
819 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
820 for (cnt = 0; cnt < grst_del + 2; cnt++) {
821 reg = rd32(hw, I40E_GLGEN_RSTAT);
822 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
824 i40e_msec_delay(100);
826 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
827 DEBUGOUT("Global reset polling failed to complete.\n");
828 return I40E_ERR_RESET_FAILED;
831 /* Now Wait for the FW to be ready */
832 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
833 reg = rd32(hw, I40E_GLNVM_ULD);
834 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
835 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
836 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
837 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
838 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
843 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
844 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
845 DEBUGOUT("wait for FW Reset complete timedout\n");
846 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
847 return I40E_ERR_RESET_FAILED;
850 /* If there was a Global Reset in progress when we got here,
851 * we don't need to do the PF Reset
854 reg = rd32(hw, I40E_PFGEN_CTRL);
855 wr32(hw, I40E_PFGEN_CTRL,
856 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
857 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
858 reg = rd32(hw, I40E_PFGEN_CTRL);
859 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
863 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
864 DEBUGOUT("PF reset polling failed to complete.\n");
865 return I40E_ERR_RESET_FAILED;
869 i40e_clear_pxe_mode(hw);
876 * i40e_clear_hw - clear out any left over hw state
877 * @hw: pointer to the hw struct
879 * Clear queues and interrupts, typically called at init time,
880 * but after the capabilities have been found so we know how many
881 * queues and msix vectors have been allocated.
883 void i40e_clear_hw(struct i40e_hw *hw)
885 u32 num_queues, base_queue;
893 /* get number of interrupts, queues, and vfs */
894 val = rd32(hw, I40E_GLPCI_CNF2);
895 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
896 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
897 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
898 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
900 val = rd32(hw, I40E_PFLAN_QALLOC);
901 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
902 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
903 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
904 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
905 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
906 num_queues = (j - base_queue) + 1;
910 val = rd32(hw, I40E_PF_VT_PFALLOC);
911 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
912 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
913 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
914 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
915 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
916 num_vfs = (j - i) + 1;
920 /* stop all the interrupts */
921 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
922 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
923 for (i = 0; i < num_pf_int - 2; i++)
924 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
926 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
927 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
928 wr32(hw, I40E_PFINT_LNKLST0, val);
929 for (i = 0; i < num_pf_int - 2; i++)
930 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
931 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
932 for (i = 0; i < num_vfs; i++)
933 wr32(hw, I40E_VPINT_LNKLST0(i), val);
934 for (i = 0; i < num_vf_int - 2; i++)
935 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
937 /* warn the HW of the coming Tx disables */
938 for (i = 0; i < num_queues; i++) {
939 u32 abs_queue_idx = base_queue + i;
942 if (abs_queue_idx >= 128) {
943 reg_block = abs_queue_idx / 128;
944 abs_queue_idx %= 128;
947 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
948 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
949 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
950 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
952 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
954 i40e_usec_delay(400);
956 /* stop all the queues */
957 for (i = 0; i < num_queues; i++) {
958 wr32(hw, I40E_QINT_TQCTL(i), 0);
959 wr32(hw, I40E_QTX_ENA(i), 0);
960 wr32(hw, I40E_QINT_RQCTL(i), 0);
961 wr32(hw, I40E_QRX_ENA(i), 0);
964 /* short wait for all queue disables to settle */
969 * i40e_clear_pxe_mode - clear pxe operations mode
970 * @hw: pointer to the hw struct
972 * Make sure all PXE mode settings are cleared, including things
973 * like descriptor fetch/write-back mode.
975 void i40e_clear_pxe_mode(struct i40e_hw *hw)
977 if (i40e_check_asq_alive(hw))
978 i40e_aq_clear_pxe_mode(hw, NULL);
982 * i40e_led_is_mine - helper to find matching led
983 * @hw: pointer to the hw struct
984 * @idx: index into GPIO registers
986 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
988 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
993 if (!hw->func_caps.led[idx])
996 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
997 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
998 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1000 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1001 * if it is not our port then ignore
1003 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1010 #define I40E_LED0 22
1011 #define I40E_LINK_ACTIVITY 0xC
1014 * i40e_led_get - return current on/off mode
1015 * @hw: pointer to the hw struct
1017 * The value returned is the 'mode' field as defined in the
1018 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1019 * values are variations of possible behaviors relating to
1020 * blink, link, and wire.
1022 u32 i40e_led_get(struct i40e_hw *hw)
1027 /* as per the documentation GPIO 22-29 are the LED
1028 * GPIO pins named LED0..LED7
1030 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1031 u32 gpio_val = i40e_led_is_mine(hw, i);
1036 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1037 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1045 * i40e_led_set - set new on/off mode
1046 * @hw: pointer to the hw struct
1047 * @mode: 0=off, 0xf=on (else see manual for mode details)
1048 * @blink: true if the LED should blink when on, false if steady
1050 * if this function is used to turn on the blink it should
1051 * be used to disable the blink when restoring the original state.
1053 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1057 if (mode & 0xfffffff0)
1058 DEBUGOUT1("invalid mode passed in %X\n", mode);
1060 /* as per the documentation GPIO 22-29 are the LED
1061 * GPIO pins named LED0..LED7
1063 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1064 u32 gpio_val = i40e_led_is_mine(hw, i);
1069 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1070 /* this & is a bit of paranoia, but serves as a range check */
1071 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1072 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1074 if (mode == I40E_LINK_ACTIVITY)
1077 gpio_val |= (blink ? 1 : 0) <<
1078 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1080 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1085 /* Admin command wrappers */
1088 * i40e_aq_get_phy_capabilities
1089 * @hw: pointer to the hw struct
1090 * @abilities: structure for PHY capabilities to be filled
1091 * @qualified_modules: report Qualified Modules
1092 * @report_init: report init capabilities (active are default)
1093 * @cmd_details: pointer to command details structure or NULL
1095 * Returns the various PHY abilities supported on the Port.
1097 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1098 bool qualified_modules, bool report_init,
1099 struct i40e_aq_get_phy_abilities_resp *abilities,
1100 struct i40e_asq_cmd_details *cmd_details)
1102 struct i40e_aq_desc desc;
1103 enum i40e_status_code status;
1104 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1107 return I40E_ERR_PARAM;
1109 i40e_fill_default_direct_cmd_desc(&desc,
1110 i40e_aqc_opc_get_phy_abilities);
1112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1113 if (abilities_size > I40E_AQ_LARGE_BUF)
1114 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1116 if (qualified_modules)
1117 desc.params.external.param0 |=
1118 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1121 desc.params.external.param0 |=
1122 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1124 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1127 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1128 status = I40E_ERR_UNKNOWN_PHY;
1134 * i40e_aq_set_phy_config
1135 * @hw: pointer to the hw struct
1136 * @config: structure with PHY configuration to be set
1137 * @cmd_details: pointer to command details structure or NULL
1139 * Set the various PHY configuration parameters
1140 * supported on the Port.One or more of the Set PHY config parameters may be
1141 * ignored in an MFP mode as the PF may not have the privilege to set some
1142 * of the PHY Config parameters. This status will be indicated by the
1145 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1146 struct i40e_aq_set_phy_config *config,
1147 struct i40e_asq_cmd_details *cmd_details)
1149 struct i40e_aq_desc desc;
1150 struct i40e_aq_set_phy_config *cmd =
1151 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1152 enum i40e_status_code status;
1155 return I40E_ERR_PARAM;
1157 i40e_fill_default_direct_cmd_desc(&desc,
1158 i40e_aqc_opc_set_phy_config);
1162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1169 * @hw: pointer to the hw struct
1171 * Set the requested flow control mode using set_phy_config.
1173 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1174 bool atomic_restart)
1176 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1177 struct i40e_aq_get_phy_abilities_resp abilities;
1178 struct i40e_aq_set_phy_config config;
1179 enum i40e_status_code status;
1180 u8 pause_mask = 0x0;
1186 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1187 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1189 case I40E_FC_RX_PAUSE:
1190 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1192 case I40E_FC_TX_PAUSE:
1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1199 /* Get the current phy config */
1200 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1203 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1207 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1208 /* clear the old pause settings */
1209 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1210 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1211 /* set the new abilities */
1212 config.abilities |= pause_mask;
1213 /* If the abilities have changed, then set the new config */
1214 if (config.abilities != abilities.abilities) {
1215 /* Auto restart link so settings take effect */
1217 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1218 /* Copy over all the old settings */
1219 config.phy_type = abilities.phy_type;
1220 config.link_speed = abilities.link_speed;
1221 config.eee_capability = abilities.eee_capability;
1222 config.eeer = abilities.eeer_val;
1223 config.low_power_ctrl = abilities.d3_lpan;
1224 status = i40e_aq_set_phy_config(hw, &config, NULL);
1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1229 /* Update the link info */
1230 status = i40e_update_link_info(hw, true);
1232 /* Wait a little bit (on 40G cards it sometimes takes a really
1233 * long time for link to come back from the atomic reset)
1236 i40e_msec_delay(1000);
1237 status = i40e_update_link_info(hw, true);
1240 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1246 * i40e_aq_set_mac_config
1247 * @hw: pointer to the hw struct
1248 * @max_frame_size: Maximum Frame Size to be supported by the port
1249 * @crc_en: Tell HW to append a CRC to outgoing frames
1250 * @pacing: Pacing configurations
1251 * @cmd_details: pointer to command details structure or NULL
1253 * Configure MAC settings for frame size, jumbo frame support and the
1254 * addition of a CRC by the hardware.
1256 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1258 bool crc_en, u16 pacing,
1259 struct i40e_asq_cmd_details *cmd_details)
1261 struct i40e_aq_desc desc;
1262 struct i40e_aq_set_mac_config *cmd =
1263 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1264 enum i40e_status_code status;
1266 if (max_frame_size == 0)
1267 return I40E_ERR_PARAM;
1269 i40e_fill_default_direct_cmd_desc(&desc,
1270 i40e_aqc_opc_set_mac_config);
1272 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1273 cmd->params = ((u8)pacing & 0x0F) << 3;
1275 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1277 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1283 * i40e_aq_clear_pxe_mode
1284 * @hw: pointer to the hw struct
1285 * @cmd_details: pointer to command details structure or NULL
1287 * Tell the firmware that the driver is taking over from PXE
1289 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1290 struct i40e_asq_cmd_details *cmd_details)
1292 enum i40e_status_code status;
1293 struct i40e_aq_desc desc;
1294 struct i40e_aqc_clear_pxe *cmd =
1295 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1297 i40e_fill_default_direct_cmd_desc(&desc,
1298 i40e_aqc_opc_clear_pxe_mode);
1302 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1304 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1310 * i40e_aq_set_link_restart_an
1311 * @hw: pointer to the hw struct
1312 * @enable_link: if true: enable link, if false: disable link
1313 * @cmd_details: pointer to command details structure or NULL
1315 * Sets up the link and restarts the Auto-Negotiation over the link.
1317 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1318 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1320 struct i40e_aq_desc desc;
1321 struct i40e_aqc_set_link_restart_an *cmd =
1322 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1323 enum i40e_status_code status;
1325 i40e_fill_default_direct_cmd_desc(&desc,
1326 i40e_aqc_opc_set_link_restart_an);
1328 cmd->command = I40E_AQ_PHY_RESTART_AN;
1330 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1332 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1334 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1340 * i40e_aq_get_link_info
1341 * @hw: pointer to the hw struct
1342 * @enable_lse: enable/disable LinkStatusEvent reporting
1343 * @link: pointer to link status structure - optional
1344 * @cmd_details: pointer to command details structure or NULL
1346 * Returns the link status of the adapter.
1348 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1349 bool enable_lse, struct i40e_link_status *link,
1350 struct i40e_asq_cmd_details *cmd_details)
1352 struct i40e_aq_desc desc;
1353 struct i40e_aqc_get_link_status *resp =
1354 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1355 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1356 enum i40e_status_code status;
1357 bool tx_pause, rx_pause;
1360 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1363 command_flags = I40E_AQ_LSE_ENABLE;
1365 command_flags = I40E_AQ_LSE_DISABLE;
1366 resp->command_flags = CPU_TO_LE16(command_flags);
1368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1370 if (status != I40E_SUCCESS)
1371 goto aq_get_link_info_exit;
1373 /* save off old link status information */
1374 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1375 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1377 /* update link status */
1378 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1379 hw->phy.media_type = i40e_get_media_type(hw);
1380 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1381 hw_link_info->link_info = resp->link_info;
1382 hw_link_info->an_info = resp->an_info;
1383 hw_link_info->ext_info = resp->ext_info;
1384 hw_link_info->loopback = resp->loopback;
1385 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1386 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1388 /* update fc info */
1389 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1390 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1391 if (tx_pause & rx_pause)
1392 hw->fc.current_mode = I40E_FC_FULL;
1394 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1396 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1398 hw->fc.current_mode = I40E_FC_NONE;
1400 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1401 hw_link_info->crc_enable = true;
1403 hw_link_info->crc_enable = false;
1405 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1406 hw_link_info->lse_enable = true;
1408 hw_link_info->lse_enable = false;
1410 /* save link status information */
1412 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1413 I40E_NONDMA_TO_NONDMA);
1415 /* flag cleared so helper functions don't call AQ again */
1416 hw->phy.get_link_info = false;
1418 aq_get_link_info_exit:
1423 * i40e_update_link_info
1424 * @hw: pointer to the hw struct
1425 * @enable_lse: enable/disable LinkStatusEvent reporting
1427 * Returns the link status of the adapter
1429 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1432 struct i40e_aq_get_phy_abilities_resp abilities;
1433 enum i40e_status_code status;
1435 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1439 status = i40e_aq_get_phy_capabilities(hw, false, false,
1444 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1445 hw->phy.link_info.an_enabled = true;
1447 hw->phy.link_info.an_enabled = false;
1453 * i40e_aq_set_phy_int_mask
1454 * @hw: pointer to the hw struct
1455 * @mask: interrupt mask to be set
1456 * @cmd_details: pointer to command details structure or NULL
1458 * Set link interrupt mask.
1460 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1462 struct i40e_asq_cmd_details *cmd_details)
1464 struct i40e_aq_desc desc;
1465 struct i40e_aqc_set_phy_int_mask *cmd =
1466 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1467 enum i40e_status_code status;
1469 i40e_fill_default_direct_cmd_desc(&desc,
1470 i40e_aqc_opc_set_phy_int_mask);
1472 cmd->event_mask = CPU_TO_LE16(mask);
1474 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1480 * i40e_aq_get_local_advt_reg
1481 * @hw: pointer to the hw struct
1482 * @advt_reg: local AN advertisement register value
1483 * @cmd_details: pointer to command details structure or NULL
1485 * Get the Local AN advertisement register value.
1487 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1489 struct i40e_asq_cmd_details *cmd_details)
1491 struct i40e_aq_desc desc;
1492 struct i40e_aqc_an_advt_reg *resp =
1493 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1494 enum i40e_status_code status;
1496 i40e_fill_default_direct_cmd_desc(&desc,
1497 i40e_aqc_opc_get_local_advt_reg);
1499 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1501 if (status != I40E_SUCCESS)
1502 goto aq_get_local_advt_reg_exit;
1504 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1505 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1507 aq_get_local_advt_reg_exit:
1512 * i40e_aq_set_local_advt_reg
1513 * @hw: pointer to the hw struct
1514 * @advt_reg: local AN advertisement register value
1515 * @cmd_details: pointer to command details structure or NULL
1517 * Get the Local AN advertisement register value.
1519 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1521 struct i40e_asq_cmd_details *cmd_details)
1523 struct i40e_aq_desc desc;
1524 struct i40e_aqc_an_advt_reg *cmd =
1525 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1526 enum i40e_status_code status;
1528 i40e_fill_default_direct_cmd_desc(&desc,
1529 i40e_aqc_opc_get_local_advt_reg);
1531 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1532 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1540 * i40e_aq_get_partner_advt
1541 * @hw: pointer to the hw struct
1542 * @advt_reg: AN partner advertisement register value
1543 * @cmd_details: pointer to command details structure or NULL
1545 * Get the link partner AN advertisement register value.
1547 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1549 struct i40e_asq_cmd_details *cmd_details)
1551 struct i40e_aq_desc desc;
1552 struct i40e_aqc_an_advt_reg *resp =
1553 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1554 enum i40e_status_code status;
1556 i40e_fill_default_direct_cmd_desc(&desc,
1557 i40e_aqc_opc_get_partner_advt);
1559 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1561 if (status != I40E_SUCCESS)
1562 goto aq_get_partner_advt_exit;
1564 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1565 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1567 aq_get_partner_advt_exit:
1572 * i40e_aq_set_lb_modes
1573 * @hw: pointer to the hw struct
1574 * @lb_modes: loopback mode to be set
1575 * @cmd_details: pointer to command details structure or NULL
1577 * Sets loopback modes.
1579 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1581 struct i40e_asq_cmd_details *cmd_details)
1583 struct i40e_aq_desc desc;
1584 struct i40e_aqc_set_lb_mode *cmd =
1585 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1586 enum i40e_status_code status;
1588 i40e_fill_default_direct_cmd_desc(&desc,
1589 i40e_aqc_opc_set_lb_modes);
1591 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1593 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1599 * i40e_aq_set_phy_debug
1600 * @hw: pointer to the hw struct
1601 * @cmd_flags: debug command flags
1602 * @cmd_details: pointer to command details structure or NULL
1604 * Reset the external PHY.
1606 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1607 struct i40e_asq_cmd_details *cmd_details)
1609 struct i40e_aq_desc desc;
1610 struct i40e_aqc_set_phy_debug *cmd =
1611 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1612 enum i40e_status_code status;
1614 i40e_fill_default_direct_cmd_desc(&desc,
1615 i40e_aqc_opc_set_phy_debug);
1617 cmd->command_flags = cmd_flags;
1619 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1626 * @hw: pointer to the hw struct
1627 * @vsi_ctx: pointer to a vsi context struct
1628 * @cmd_details: pointer to command details structure or NULL
1630 * Add a VSI context to the hardware.
1632 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1633 struct i40e_vsi_context *vsi_ctx,
1634 struct i40e_asq_cmd_details *cmd_details)
1636 struct i40e_aq_desc desc;
1637 struct i40e_aqc_add_get_update_vsi *cmd =
1638 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1639 struct i40e_aqc_add_get_update_vsi_completion *resp =
1640 (struct i40e_aqc_add_get_update_vsi_completion *)
1642 enum i40e_status_code status;
1644 i40e_fill_default_direct_cmd_desc(&desc,
1645 i40e_aqc_opc_add_vsi);
1647 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1648 cmd->connection_type = vsi_ctx->connection_type;
1649 cmd->vf_id = vsi_ctx->vf_num;
1650 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1652 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1654 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1655 sizeof(vsi_ctx->info), cmd_details);
1657 if (status != I40E_SUCCESS)
1658 goto aq_add_vsi_exit;
1660 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1661 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1662 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1663 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1670 * i40e_aq_set_default_vsi
1671 * @hw: pointer to the hw struct
1673 * @cmd_details: pointer to command details structure or NULL
1675 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1677 struct i40e_asq_cmd_details *cmd_details)
1679 struct i40e_aq_desc desc;
1680 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1681 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1683 enum i40e_status_code status;
1685 i40e_fill_default_direct_cmd_desc(&desc,
1686 i40e_aqc_opc_set_vsi_promiscuous_modes);
1688 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1689 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1690 cmd->seid = CPU_TO_LE16(seid);
1692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1698 * i40e_aq_set_vsi_unicast_promiscuous
1699 * @hw: pointer to the hw struct
1701 * @set: set unicast promiscuous enable/disable
1702 * @cmd_details: pointer to command details structure or NULL
1704 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1706 struct i40e_asq_cmd_details *cmd_details)
1708 struct i40e_aq_desc desc;
1709 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1710 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1711 enum i40e_status_code status;
1714 i40e_fill_default_direct_cmd_desc(&desc,
1715 i40e_aqc_opc_set_vsi_promiscuous_modes);
1718 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1720 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1722 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1724 cmd->seid = CPU_TO_LE16(seid);
1725 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1731 * i40e_aq_set_vsi_multicast_promiscuous
1732 * @hw: pointer to the hw struct
1734 * @set: set multicast promiscuous enable/disable
1735 * @cmd_details: pointer to command details structure or NULL
1737 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1738 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1740 struct i40e_aq_desc desc;
1741 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1742 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1743 enum i40e_status_code status;
1746 i40e_fill_default_direct_cmd_desc(&desc,
1747 i40e_aqc_opc_set_vsi_promiscuous_modes);
1750 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1752 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1754 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1756 cmd->seid = CPU_TO_LE16(seid);
1757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1763 * i40e_aq_set_vsi_broadcast
1764 * @hw: pointer to the hw struct
1766 * @set_filter: true to set filter, false to clear filter
1767 * @cmd_details: pointer to command details structure or NULL
1769 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1771 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1772 u16 seid, bool set_filter,
1773 struct i40e_asq_cmd_details *cmd_details)
1775 struct i40e_aq_desc desc;
1776 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1777 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1778 enum i40e_status_code status;
1780 i40e_fill_default_direct_cmd_desc(&desc,
1781 i40e_aqc_opc_set_vsi_promiscuous_modes);
1784 cmd->promiscuous_flags
1785 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1787 cmd->promiscuous_flags
1788 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1790 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1791 cmd->seid = CPU_TO_LE16(seid);
1792 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1798 * i40e_get_vsi_params - get VSI configuration info
1799 * @hw: pointer to the hw struct
1800 * @vsi_ctx: pointer to a vsi context struct
1801 * @cmd_details: pointer to command details structure or NULL
1803 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1804 struct i40e_vsi_context *vsi_ctx,
1805 struct i40e_asq_cmd_details *cmd_details)
1807 struct i40e_aq_desc desc;
1808 struct i40e_aqc_add_get_update_vsi *cmd =
1809 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1810 struct i40e_aqc_add_get_update_vsi_completion *resp =
1811 (struct i40e_aqc_add_get_update_vsi_completion *)
1813 enum i40e_status_code status;
1815 UNREFERENCED_1PARAMETER(cmd_details);
1816 i40e_fill_default_direct_cmd_desc(&desc,
1817 i40e_aqc_opc_get_vsi_parameters);
1819 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1821 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1823 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1824 sizeof(vsi_ctx->info), NULL);
1826 if (status != I40E_SUCCESS)
1827 goto aq_get_vsi_params_exit;
1829 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1830 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1831 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1832 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1834 aq_get_vsi_params_exit:
1839 * i40e_aq_update_vsi_params
1840 * @hw: pointer to the hw struct
1841 * @vsi_ctx: pointer to a vsi context struct
1842 * @cmd_details: pointer to command details structure or NULL
1844 * Update a VSI context.
1846 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1847 struct i40e_vsi_context *vsi_ctx,
1848 struct i40e_asq_cmd_details *cmd_details)
1850 struct i40e_aq_desc desc;
1851 struct i40e_aqc_add_get_update_vsi *cmd =
1852 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1853 enum i40e_status_code status;
1855 i40e_fill_default_direct_cmd_desc(&desc,
1856 i40e_aqc_opc_update_vsi_parameters);
1857 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1859 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1861 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1862 sizeof(vsi_ctx->info), cmd_details);
1868 * i40e_aq_get_switch_config
1869 * @hw: pointer to the hardware structure
1870 * @buf: pointer to the result buffer
1871 * @buf_size: length of input buffer
1872 * @start_seid: seid to start for the report, 0 == beginning
1873 * @cmd_details: pointer to command details structure or NULL
1875 * Fill the buf with switch configuration returned from AdminQ command
1877 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1878 struct i40e_aqc_get_switch_config_resp *buf,
1879 u16 buf_size, u16 *start_seid,
1880 struct i40e_asq_cmd_details *cmd_details)
1882 struct i40e_aq_desc desc;
1883 struct i40e_aqc_switch_seid *scfg =
1884 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1885 enum i40e_status_code status;
1887 i40e_fill_default_direct_cmd_desc(&desc,
1888 i40e_aqc_opc_get_switch_config);
1889 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1890 if (buf_size > I40E_AQ_LARGE_BUF)
1891 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1892 scfg->seid = CPU_TO_LE16(*start_seid);
1894 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1895 *start_seid = LE16_TO_CPU(scfg->seid);
1901 * i40e_aq_get_firmware_version
1902 * @hw: pointer to the hw struct
1903 * @fw_major_version: firmware major version
1904 * @fw_minor_version: firmware minor version
1905 * @api_major_version: major queue version
1906 * @api_minor_version: minor queue version
1907 * @cmd_details: pointer to command details structure or NULL
1909 * Get the firmware version from the admin queue commands
1911 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1912 u16 *fw_major_version, u16 *fw_minor_version,
1913 u16 *api_major_version, u16 *api_minor_version,
1914 struct i40e_asq_cmd_details *cmd_details)
1916 struct i40e_aq_desc desc;
1917 struct i40e_aqc_get_version *resp =
1918 (struct i40e_aqc_get_version *)&desc.params.raw;
1919 enum i40e_status_code status;
1921 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1925 if (status == I40E_SUCCESS) {
1926 if (fw_major_version != NULL)
1927 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1928 if (fw_minor_version != NULL)
1929 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1930 if (api_major_version != NULL)
1931 *api_major_version = LE16_TO_CPU(resp->api_major);
1932 if (api_minor_version != NULL)
1933 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1935 /* A workaround to fix the API version in SW */
1936 if (api_major_version && api_minor_version &&
1937 fw_major_version && fw_minor_version &&
1938 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1939 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1940 (*fw_major_version > 4)))
1941 *api_minor_version = 2;
1948 * i40e_aq_send_driver_version
1949 * @hw: pointer to the hw struct
1950 * @dv: driver's major, minor version
1951 * @cmd_details: pointer to command details structure or NULL
1953 * Send the driver version to the firmware
1955 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1956 struct i40e_driver_version *dv,
1957 struct i40e_asq_cmd_details *cmd_details)
1959 struct i40e_aq_desc desc;
1960 struct i40e_aqc_driver_version *cmd =
1961 (struct i40e_aqc_driver_version *)&desc.params.raw;
1962 enum i40e_status_code status;
1966 return I40E_ERR_PARAM;
1968 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1970 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI);
1971 cmd->driver_major_ver = dv->major_version;
1972 cmd->driver_minor_ver = dv->minor_version;
1973 cmd->driver_build_ver = dv->build_version;
1974 cmd->driver_subbuild_ver = dv->subbuild_version;
1977 while (len < sizeof(dv->driver_string) &&
1978 (dv->driver_string[len] < 0x80) &&
1979 dv->driver_string[len])
1981 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1988 * i40e_get_link_status - get status of the HW network link
1989 * @hw: pointer to the hw struct
1991 * Returns true if link is up, false if link is down.
1993 * Side effect: LinkStatusEvent reporting becomes enabled
1995 bool i40e_get_link_status(struct i40e_hw *hw)
1997 enum i40e_status_code status = I40E_SUCCESS;
1998 bool link_status = false;
2000 if (hw->phy.get_link_info) {
2001 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2003 if (status != I40E_SUCCESS)
2004 goto i40e_get_link_status_exit;
2007 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2009 i40e_get_link_status_exit:
2014 * i40e_get_link_speed
2015 * @hw: pointer to the hw struct
2017 * Returns the link speed of the adapter.
2019 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2021 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2022 enum i40e_status_code status = I40E_SUCCESS;
2024 if (hw->phy.get_link_info) {
2025 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2027 if (status != I40E_SUCCESS)
2028 goto i40e_link_speed_exit;
2031 speed = hw->phy.link_info.link_speed;
2033 i40e_link_speed_exit:
2038 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2039 * @hw: pointer to the hw struct
2040 * @uplink_seid: the MAC or other gizmo SEID
2041 * @downlink_seid: the VSI SEID
2042 * @enabled_tc: bitmap of TCs to be enabled
2043 * @default_port: true for default port VSI, false for control port
2044 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2045 * @veb_seid: pointer to where to put the resulting VEB SEID
2046 * @cmd_details: pointer to command details structure or NULL
2048 * This asks the FW to add a VEB between the uplink and downlink
2049 * elements. If the uplink SEID is 0, this will be a floating VEB.
2051 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2052 u16 downlink_seid, u8 enabled_tc,
2053 bool default_port, bool enable_l2_filtering,
2055 struct i40e_asq_cmd_details *cmd_details)
2057 struct i40e_aq_desc desc;
2058 struct i40e_aqc_add_veb *cmd =
2059 (struct i40e_aqc_add_veb *)&desc.params.raw;
2060 struct i40e_aqc_add_veb_completion *resp =
2061 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2062 enum i40e_status_code status;
2065 /* SEIDs need to either both be set or both be 0 for floating VEB */
2066 if (!!uplink_seid != !!downlink_seid)
2067 return I40E_ERR_PARAM;
2069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2071 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2072 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2073 cmd->enable_tcs = enabled_tc;
2075 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2077 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2079 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2081 if (enable_l2_filtering)
2082 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2084 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2086 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2088 if (!status && veb_seid)
2089 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2095 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2096 * @hw: pointer to the hw struct
2097 * @veb_seid: the SEID of the VEB to query
2098 * @switch_id: the uplink switch id
2099 * @floating: set to true if the VEB is floating
2100 * @statistic_index: index of the stats counter block for this VEB
2101 * @vebs_used: number of VEB's used by function
2102 * @vebs_free: total VEB's not reserved by any function
2103 * @cmd_details: pointer to command details structure or NULL
2105 * This retrieves the parameters for a particular VEB, specified by
2106 * uplink_seid, and returns them to the caller.
2108 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2109 u16 veb_seid, u16 *switch_id,
2110 bool *floating, u16 *statistic_index,
2111 u16 *vebs_used, u16 *vebs_free,
2112 struct i40e_asq_cmd_details *cmd_details)
2114 struct i40e_aq_desc desc;
2115 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2116 (struct i40e_aqc_get_veb_parameters_completion *)
2118 enum i40e_status_code status;
2121 return I40E_ERR_PARAM;
2123 i40e_fill_default_direct_cmd_desc(&desc,
2124 i40e_aqc_opc_get_veb_parameters);
2125 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2127 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2132 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2133 if (statistic_index)
2134 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2136 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2138 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2140 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2141 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2152 * i40e_aq_add_macvlan
2153 * @hw: pointer to the hw struct
2154 * @seid: VSI for the mac address
2155 * @mv_list: list of macvlans to be added
2156 * @count: length of the list
2157 * @cmd_details: pointer to command details structure or NULL
2159 * Add MAC/VLAN addresses to the HW filtering
2161 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2162 struct i40e_aqc_add_macvlan_element_data *mv_list,
2163 u16 count, struct i40e_asq_cmd_details *cmd_details)
2165 struct i40e_aq_desc desc;
2166 struct i40e_aqc_macvlan *cmd =
2167 (struct i40e_aqc_macvlan *)&desc.params.raw;
2168 enum i40e_status_code status;
2171 if (count == 0 || !mv_list || !hw)
2172 return I40E_ERR_PARAM;
2174 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2176 /* prep the rest of the request */
2177 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2178 cmd->num_addresses = CPU_TO_LE16(count);
2179 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2183 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2184 if (buf_size > I40E_AQ_LARGE_BUF)
2185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2187 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2194 * i40e_aq_remove_macvlan
2195 * @hw: pointer to the hw struct
2196 * @seid: VSI for the mac address
2197 * @mv_list: list of macvlans to be removed
2198 * @count: length of the list
2199 * @cmd_details: pointer to command details structure or NULL
2201 * Remove MAC/VLAN addresses from the HW filtering
2203 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2204 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2205 u16 count, struct i40e_asq_cmd_details *cmd_details)
2207 struct i40e_aq_desc desc;
2208 struct i40e_aqc_macvlan *cmd =
2209 (struct i40e_aqc_macvlan *)&desc.params.raw;
2210 enum i40e_status_code status;
2213 if (count == 0 || !mv_list || !hw)
2214 return I40E_ERR_PARAM;
2216 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2218 /* prep the rest of the request */
2219 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2220 cmd->num_addresses = CPU_TO_LE16(count);
2221 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2225 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2226 if (buf_size > I40E_AQ_LARGE_BUF)
2227 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2229 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2236 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2237 * @hw: pointer to the hw struct
2238 * @seid: VSI for the vlan filters
2239 * @v_list: list of vlan filters to be added
2240 * @count: length of the list
2241 * @cmd_details: pointer to command details structure or NULL
2243 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2244 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2245 u8 count, struct i40e_asq_cmd_details *cmd_details)
2247 struct i40e_aq_desc desc;
2248 struct i40e_aqc_macvlan *cmd =
2249 (struct i40e_aqc_macvlan *)&desc.params.raw;
2250 enum i40e_status_code status;
2253 if (count == 0 || !v_list || !hw)
2254 return I40E_ERR_PARAM;
2256 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2258 /* prep the rest of the request */
2259 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2260 cmd->num_addresses = CPU_TO_LE16(count);
2261 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2265 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2266 if (buf_size > I40E_AQ_LARGE_BUF)
2267 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2269 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2276 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2277 * @hw: pointer to the hw struct
2278 * @seid: VSI for the vlan filters
2279 * @v_list: list of macvlans to be removed
2280 * @count: length of the list
2281 * @cmd_details: pointer to command details structure or NULL
2283 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2284 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2285 u8 count, struct i40e_asq_cmd_details *cmd_details)
2287 struct i40e_aq_desc desc;
2288 struct i40e_aqc_macvlan *cmd =
2289 (struct i40e_aqc_macvlan *)&desc.params.raw;
2290 enum i40e_status_code status;
2293 if (count == 0 || !v_list || !hw)
2294 return I40E_ERR_PARAM;
2296 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2298 /* prep the rest of the request */
2299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2300 cmd->num_addresses = CPU_TO_LE16(count);
2301 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2305 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2306 if (buf_size > I40E_AQ_LARGE_BUF)
2307 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2309 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2316 * i40e_aq_send_msg_to_vf
2317 * @hw: pointer to the hardware structure
2318 * @vfid: vf id to send msg
2319 * @v_opcode: opcodes for VF-PF communication
2320 * @v_retval: return error code
2321 * @msg: pointer to the msg buffer
2322 * @msglen: msg length
2323 * @cmd_details: pointer to command details
2327 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2328 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2329 struct i40e_asq_cmd_details *cmd_details)
2331 struct i40e_aq_desc desc;
2332 struct i40e_aqc_pf_vf_message *cmd =
2333 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2334 enum i40e_status_code status;
2336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2337 cmd->id = CPU_TO_LE32(vfid);
2338 desc.cookie_high = CPU_TO_LE32(v_opcode);
2339 desc.cookie_low = CPU_TO_LE32(v_retval);
2340 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2342 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2344 if (msglen > I40E_AQ_LARGE_BUF)
2345 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2346 desc.datalen = CPU_TO_LE16(msglen);
2348 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2354 * i40e_aq_get_hmc_resource_profile
2355 * @hw: pointer to the hw struct
2356 * @profile: type of profile the HMC is to be set as
2357 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2358 * @cmd_details: pointer to command details structure or NULL
2360 * query the HMC profile of the device.
2362 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2363 enum i40e_aq_hmc_profile *profile,
2364 u8 *pe_vf_enabled_count,
2365 struct i40e_asq_cmd_details *cmd_details)
2367 struct i40e_aq_desc desc;
2368 struct i40e_aq_get_set_hmc_resource_profile *resp =
2369 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2370 enum i40e_status_code status;
2372 i40e_fill_default_direct_cmd_desc(&desc,
2373 i40e_aqc_opc_query_hmc_resource_profile);
2374 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2376 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2377 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2378 *pe_vf_enabled_count = resp->pe_vf_enabled &
2379 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2385 * i40e_aq_set_hmc_resource_profile
2386 * @hw: pointer to the hw struct
2387 * @profile: type of profile the HMC is to be set as
2388 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2389 * @cmd_details: pointer to command details structure or NULL
2391 * set the HMC profile of the device.
2393 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2394 enum i40e_aq_hmc_profile profile,
2395 u8 pe_vf_enabled_count,
2396 struct i40e_asq_cmd_details *cmd_details)
2398 struct i40e_aq_desc desc;
2399 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2400 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2401 enum i40e_status_code status;
2403 i40e_fill_default_direct_cmd_desc(&desc,
2404 i40e_aqc_opc_set_hmc_resource_profile);
2406 cmd->pm_profile = (u8)profile;
2407 cmd->pe_vf_enabled = pe_vf_enabled_count;
2409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2415 * i40e_aq_request_resource
2416 * @hw: pointer to the hw struct
2417 * @resource: resource id
2418 * @access: access type
2419 * @sdp_number: resource number
2420 * @timeout: the maximum time in ms that the driver may hold the resource
2421 * @cmd_details: pointer to command details structure or NULL
2423 * requests common resource using the admin queue commands
2425 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2426 enum i40e_aq_resources_ids resource,
2427 enum i40e_aq_resource_access_type access,
2428 u8 sdp_number, u64 *timeout,
2429 struct i40e_asq_cmd_details *cmd_details)
2431 struct i40e_aq_desc desc;
2432 struct i40e_aqc_request_resource *cmd_resp =
2433 (struct i40e_aqc_request_resource *)&desc.params.raw;
2434 enum i40e_status_code status;
2436 DEBUGFUNC("i40e_aq_request_resource");
2438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2440 cmd_resp->resource_id = CPU_TO_LE16(resource);
2441 cmd_resp->access_type = CPU_TO_LE16(access);
2442 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2445 /* The completion specifies the maximum time in ms that the driver
2446 * may hold the resource in the Timeout field.
2447 * If the resource is held by someone else, the command completes with
2448 * busy return value and the timeout field indicates the maximum time
2449 * the current owner of the resource has to free it.
2451 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2452 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2458 * i40e_aq_release_resource
2459 * @hw: pointer to the hw struct
2460 * @resource: resource id
2461 * @sdp_number: resource number
2462 * @cmd_details: pointer to command details structure or NULL
2464 * release common resource using the admin queue commands
2466 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2467 enum i40e_aq_resources_ids resource,
2469 struct i40e_asq_cmd_details *cmd_details)
2471 struct i40e_aq_desc desc;
2472 struct i40e_aqc_request_resource *cmd =
2473 (struct i40e_aqc_request_resource *)&desc.params.raw;
2474 enum i40e_status_code status;
2476 DEBUGFUNC("i40e_aq_release_resource");
2478 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2480 cmd->resource_id = CPU_TO_LE16(resource);
2481 cmd->resource_number = CPU_TO_LE32(sdp_number);
2483 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2490 * @hw: pointer to the hw struct
2491 * @module_pointer: module pointer location in words from the NVM beginning
2492 * @offset: byte offset from the module beginning
2493 * @length: length of the section to be read (in bytes from the offset)
2494 * @data: command buffer (size [bytes] = length)
2495 * @last_command: tells if this is the last command in a series
2496 * @cmd_details: pointer to command details structure or NULL
2498 * Read the NVM using the admin queue commands
2500 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2501 u32 offset, u16 length, void *data,
2503 struct i40e_asq_cmd_details *cmd_details)
2505 struct i40e_aq_desc desc;
2506 struct i40e_aqc_nvm_update *cmd =
2507 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2508 enum i40e_status_code status;
2510 DEBUGFUNC("i40e_aq_read_nvm");
2512 /* In offset the highest byte must be zeroed. */
2513 if (offset & 0xFF000000) {
2514 status = I40E_ERR_PARAM;
2515 goto i40e_aq_read_nvm_exit;
2518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2520 /* If this is the last command in a series, set the proper flag. */
2522 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2523 cmd->module_pointer = module_pointer;
2524 cmd->offset = CPU_TO_LE32(offset);
2525 cmd->length = CPU_TO_LE16(length);
2527 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2528 if (length > I40E_AQ_LARGE_BUF)
2529 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2531 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2533 i40e_aq_read_nvm_exit:
2539 * @hw: pointer to the hw struct
2540 * @module_pointer: module pointer location in words from the NVM beginning
2541 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2542 * @length: length of the section to be erased (expressed in 4 KB)
2543 * @last_command: tells if this is the last command in a series
2544 * @cmd_details: pointer to command details structure or NULL
2546 * Erase the NVM sector using the admin queue commands
2548 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2549 u32 offset, u16 length, bool last_command,
2550 struct i40e_asq_cmd_details *cmd_details)
2552 struct i40e_aq_desc desc;
2553 struct i40e_aqc_nvm_update *cmd =
2554 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2555 enum i40e_status_code status;
2557 DEBUGFUNC("i40e_aq_erase_nvm");
2559 /* In offset the highest byte must be zeroed. */
2560 if (offset & 0xFF000000) {
2561 status = I40E_ERR_PARAM;
2562 goto i40e_aq_erase_nvm_exit;
2565 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2567 /* If this is the last command in a series, set the proper flag. */
2569 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2570 cmd->module_pointer = module_pointer;
2571 cmd->offset = CPU_TO_LE32(offset);
2572 cmd->length = CPU_TO_LE16(length);
2574 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2576 i40e_aq_erase_nvm_exit:
2580 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2581 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2582 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2583 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2584 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2585 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2586 #define I40E_DEV_FUNC_CAP_VF 0x13
2587 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2588 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2589 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2590 #define I40E_DEV_FUNC_CAP_VSI 0x17
2591 #define I40E_DEV_FUNC_CAP_DCB 0x18
2592 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2593 #define I40E_DEV_FUNC_CAP_RSS 0x40
2594 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2595 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2596 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2597 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2598 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2599 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2600 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2601 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2602 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2603 #define I40E_DEV_FUNC_CAP_LED 0x61
2604 #define I40E_DEV_FUNC_CAP_SDP 0x62
2605 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2608 * i40e_parse_discover_capabilities
2609 * @hw: pointer to the hw struct
2610 * @buff: pointer to a buffer containing device/function capability records
2611 * @cap_count: number of capability records in the list
2612 * @list_type_opc: type of capabilities list to parse
2614 * Parse the device/function capabilities list.
2616 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2618 enum i40e_admin_queue_opc list_type_opc)
2620 struct i40e_aqc_list_capabilities_element_resp *cap;
2621 u32 number, logical_id, phys_id;
2622 struct i40e_hw_capabilities *p;
2626 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2628 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2629 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2630 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2631 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2635 for (i = 0; i < cap_count; i++, cap++) {
2636 id = LE16_TO_CPU(cap->id);
2637 number = LE32_TO_CPU(cap->number);
2638 logical_id = LE32_TO_CPU(cap->logical_id);
2639 phys_id = LE32_TO_CPU(cap->phys_id);
2642 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2643 p->switch_mode = number;
2645 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2646 p->management_mode = number;
2648 case I40E_DEV_FUNC_CAP_NPAR:
2649 p->npar_enable = number;
2651 case I40E_DEV_FUNC_CAP_OS2BMC:
2654 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2655 p->valid_functions = number;
2657 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2659 p->sr_iov_1_1 = true;
2661 case I40E_DEV_FUNC_CAP_VF:
2662 p->num_vfs = number;
2663 p->vf_base_id = logical_id;
2665 case I40E_DEV_FUNC_CAP_VMDQ:
2669 case I40E_DEV_FUNC_CAP_802_1_QBG:
2671 p->evb_802_1_qbg = true;
2673 case I40E_DEV_FUNC_CAP_802_1_QBH:
2675 p->evb_802_1_qbh = true;
2677 case I40E_DEV_FUNC_CAP_VSI:
2678 p->num_vsis = number;
2680 case I40E_DEV_FUNC_CAP_DCB:
2683 p->enabled_tcmap = logical_id;
2687 case I40E_DEV_FUNC_CAP_FCOE:
2691 case I40E_DEV_FUNC_CAP_RSS:
2693 p->rss_table_size = number;
2694 p->rss_table_entry_width = logical_id;
2696 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2697 p->num_rx_qp = number;
2698 p->base_queue = phys_id;
2700 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2701 p->num_tx_qp = number;
2702 p->base_queue = phys_id;
2704 case I40E_DEV_FUNC_CAP_MSIX:
2705 p->num_msix_vectors = number;
2707 case I40E_DEV_FUNC_CAP_MSIX_VF:
2708 p->num_msix_vectors_vf = number;
2710 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2712 p->mfp_mode_1 = true;
2714 case I40E_DEV_FUNC_CAP_CEM:
2718 case I40E_DEV_FUNC_CAP_IWARP:
2722 case I40E_DEV_FUNC_CAP_LED:
2723 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2724 p->led[phys_id] = true;
2726 case I40E_DEV_FUNC_CAP_SDP:
2727 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2728 p->sdp[phys_id] = true;
2730 case I40E_DEV_FUNC_CAP_MDIO:
2732 p->mdio_port_num = phys_id;
2733 p->mdio_port_mode = logical_id;
2736 case I40E_DEV_FUNC_CAP_IEEE_1588:
2738 p->ieee_1588 = true;
2740 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2742 p->fd_filters_guaranteed = number;
2743 p->fd_filters_best_effort = logical_id;
2750 /* Software override ensuring FCoE is disabled if npar or mfp
2751 * mode because it is not supported in these modes.
2753 if (p->npar_enable || p->mfp_mode_1)
2756 /* additional HW specific goodies that might
2757 * someday be HW version specific
2759 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2763 * i40e_aq_discover_capabilities
2764 * @hw: pointer to the hw struct
2765 * @buff: a virtual buffer to hold the capabilities
2766 * @buff_size: Size of the virtual buffer
2767 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2768 * @list_type_opc: capabilities type to discover - pass in the command opcode
2769 * @cmd_details: pointer to command details structure or NULL
2771 * Get the device capabilities descriptions from the firmware
2773 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2774 void *buff, u16 buff_size, u16 *data_size,
2775 enum i40e_admin_queue_opc list_type_opc,
2776 struct i40e_asq_cmd_details *cmd_details)
2778 struct i40e_aqc_list_capabilites *cmd;
2779 struct i40e_aq_desc desc;
2780 enum i40e_status_code status = I40E_SUCCESS;
2782 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2784 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2785 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2786 status = I40E_ERR_PARAM;
2790 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2792 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2793 if (buff_size > I40E_AQ_LARGE_BUF)
2794 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2796 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2797 *data_size = LE16_TO_CPU(desc.datalen);
2802 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2810 * i40e_aq_update_nvm
2811 * @hw: pointer to the hw struct
2812 * @module_pointer: module pointer location in words from the NVM beginning
2813 * @offset: byte offset from the module beginning
2814 * @length: length of the section to be written (in bytes from the offset)
2815 * @data: command buffer (size [bytes] = length)
2816 * @last_command: tells if this is the last command in a series
2817 * @cmd_details: pointer to command details structure or NULL
2819 * Update the NVM using the admin queue commands
2821 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2822 u32 offset, u16 length, void *data,
2824 struct i40e_asq_cmd_details *cmd_details)
2826 struct i40e_aq_desc desc;
2827 struct i40e_aqc_nvm_update *cmd =
2828 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2829 enum i40e_status_code status;
2831 DEBUGFUNC("i40e_aq_update_nvm");
2833 /* In offset the highest byte must be zeroed. */
2834 if (offset & 0xFF000000) {
2835 status = I40E_ERR_PARAM;
2836 goto i40e_aq_update_nvm_exit;
2839 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2841 /* If this is the last command in a series, set the proper flag. */
2843 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2844 cmd->module_pointer = module_pointer;
2845 cmd->offset = CPU_TO_LE32(offset);
2846 cmd->length = CPU_TO_LE16(length);
2848 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2849 if (length > I40E_AQ_LARGE_BUF)
2850 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2852 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2854 i40e_aq_update_nvm_exit:
2859 * i40e_aq_get_lldp_mib
2860 * @hw: pointer to the hw struct
2861 * @bridge_type: type of bridge requested
2862 * @mib_type: Local, Remote or both Local and Remote MIBs
2863 * @buff: pointer to a user supplied buffer to store the MIB block
2864 * @buff_size: size of the buffer (in bytes)
2865 * @local_len : length of the returned Local LLDP MIB
2866 * @remote_len: length of the returned Remote LLDP MIB
2867 * @cmd_details: pointer to command details structure or NULL
2869 * Requests the complete LLDP MIB (entire packet).
2871 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2872 u8 mib_type, void *buff, u16 buff_size,
2873 u16 *local_len, u16 *remote_len,
2874 struct i40e_asq_cmd_details *cmd_details)
2876 struct i40e_aq_desc desc;
2877 struct i40e_aqc_lldp_get_mib *cmd =
2878 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2879 struct i40e_aqc_lldp_get_mib *resp =
2880 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2881 enum i40e_status_code status;
2883 if (buff_size == 0 || !buff)
2884 return I40E_ERR_PARAM;
2886 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2887 /* Indirect Command */
2888 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2890 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2891 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2892 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2894 desc.datalen = CPU_TO_LE16(buff_size);
2896 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2897 if (buff_size > I40E_AQ_LARGE_BUF)
2898 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2900 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2902 if (local_len != NULL)
2903 *local_len = LE16_TO_CPU(resp->local_len);
2904 if (remote_len != NULL)
2905 *remote_len = LE16_TO_CPU(resp->remote_len);
2912 * i40e_aq_cfg_lldp_mib_change_event
2913 * @hw: pointer to the hw struct
2914 * @enable_update: Enable or Disable event posting
2915 * @cmd_details: pointer to command details structure or NULL
2917 * Enable or Disable posting of an event on ARQ when LLDP MIB
2918 * associated with the interface changes
2920 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2922 struct i40e_asq_cmd_details *cmd_details)
2924 struct i40e_aq_desc desc;
2925 struct i40e_aqc_lldp_update_mib *cmd =
2926 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2927 enum i40e_status_code status;
2929 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2932 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2940 * i40e_aq_add_lldp_tlv
2941 * @hw: pointer to the hw struct
2942 * @bridge_type: type of bridge
2943 * @buff: buffer with TLV to add
2944 * @buff_size: length of the buffer
2945 * @tlv_len: length of the TLV to be added
2946 * @mib_len: length of the LLDP MIB returned in response
2947 * @cmd_details: pointer to command details structure or NULL
2949 * Add the specified TLV to LLDP Local MIB for the given bridge type,
2950 * it is responsibility of the caller to make sure that the TLV is not
2951 * already present in the LLDPDU.
2952 * In return firmware will write the complete LLDP MIB with the newly
2953 * added TLV in the response buffer.
2955 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
2956 void *buff, u16 buff_size, u16 tlv_len,
2958 struct i40e_asq_cmd_details *cmd_details)
2960 struct i40e_aq_desc desc;
2961 struct i40e_aqc_lldp_add_tlv *cmd =
2962 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
2963 enum i40e_status_code status;
2965 if (buff_size == 0 || !buff || tlv_len == 0)
2966 return I40E_ERR_PARAM;
2968 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
2970 /* Indirect Command */
2971 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2972 if (buff_size > I40E_AQ_LARGE_BUF)
2973 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2974 desc.datalen = CPU_TO_LE16(buff_size);
2976 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2977 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2978 cmd->len = CPU_TO_LE16(tlv_len);
2980 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2982 if (mib_len != NULL)
2983 *mib_len = LE16_TO_CPU(desc.datalen);
2990 * i40e_aq_update_lldp_tlv
2991 * @hw: pointer to the hw struct
2992 * @bridge_type: type of bridge
2993 * @buff: buffer with TLV to update
2994 * @buff_size: size of the buffer holding original and updated TLVs
2995 * @old_len: Length of the Original TLV
2996 * @new_len: Length of the Updated TLV
2997 * @offset: offset of the updated TLV in the buff
2998 * @mib_len: length of the returned LLDP MIB
2999 * @cmd_details: pointer to command details structure or NULL
3001 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3002 * Firmware will place the complete LLDP MIB in response buffer with the
3005 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3006 u8 bridge_type, void *buff, u16 buff_size,
3007 u16 old_len, u16 new_len, u16 offset,
3009 struct i40e_asq_cmd_details *cmd_details)
3011 struct i40e_aq_desc desc;
3012 struct i40e_aqc_lldp_update_tlv *cmd =
3013 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3014 enum i40e_status_code status;
3016 if (buff_size == 0 || !buff || offset == 0 ||
3017 old_len == 0 || new_len == 0)
3018 return I40E_ERR_PARAM;
3020 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3022 /* Indirect Command */
3023 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3024 if (buff_size > I40E_AQ_LARGE_BUF)
3025 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3026 desc.datalen = CPU_TO_LE16(buff_size);
3028 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3029 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3030 cmd->old_len = CPU_TO_LE16(old_len);
3031 cmd->new_offset = CPU_TO_LE16(offset);
3032 cmd->new_len = CPU_TO_LE16(new_len);
3034 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3036 if (mib_len != NULL)
3037 *mib_len = LE16_TO_CPU(desc.datalen);
3044 * i40e_aq_delete_lldp_tlv
3045 * @hw: pointer to the hw struct
3046 * @bridge_type: type of bridge
3047 * @buff: pointer to a user supplied buffer that has the TLV
3048 * @buff_size: length of the buffer
3049 * @tlv_len: length of the TLV to be deleted
3050 * @mib_len: length of the returned LLDP MIB
3051 * @cmd_details: pointer to command details structure or NULL
3053 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3054 * The firmware places the entire LLDP MIB in the response buffer.
3056 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3057 u8 bridge_type, void *buff, u16 buff_size,
3058 u16 tlv_len, u16 *mib_len,
3059 struct i40e_asq_cmd_details *cmd_details)
3061 struct i40e_aq_desc desc;
3062 struct i40e_aqc_lldp_add_tlv *cmd =
3063 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3064 enum i40e_status_code status;
3066 if (buff_size == 0 || !buff)
3067 return I40E_ERR_PARAM;
3069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3071 /* Indirect Command */
3072 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3073 if (buff_size > I40E_AQ_LARGE_BUF)
3074 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3075 desc.datalen = CPU_TO_LE16(buff_size);
3076 cmd->len = CPU_TO_LE16(tlv_len);
3077 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3078 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3080 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3082 if (mib_len != NULL)
3083 *mib_len = LE16_TO_CPU(desc.datalen);
3091 * @hw: pointer to the hw struct
3092 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3093 * @cmd_details: pointer to command details structure or NULL
3095 * Stop or Shutdown the embedded LLDP Agent
3097 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3098 struct i40e_asq_cmd_details *cmd_details)
3100 struct i40e_aq_desc desc;
3101 struct i40e_aqc_lldp_stop *cmd =
3102 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3103 enum i40e_status_code status;
3105 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3108 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3116 * i40e_aq_start_lldp
3117 * @hw: pointer to the hw struct
3118 * @cmd_details: pointer to command details structure or NULL
3120 * Start the embedded LLDP Agent on all ports.
3122 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3123 struct i40e_asq_cmd_details *cmd_details)
3125 struct i40e_aq_desc desc;
3126 struct i40e_aqc_lldp_start *cmd =
3127 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3128 enum i40e_status_code status;
3130 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3132 cmd->command = I40E_AQ_LLDP_AGENT_START;
3134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3140 * i40e_aq_add_udp_tunnel
3141 * @hw: pointer to the hw struct
3142 * @udp_port: the UDP port to add
3143 * @header_len: length of the tunneling header length in DWords
3144 * @protocol_index: protocol index type
3145 * @filter_index: pointer to filter index
3146 * @cmd_details: pointer to command details structure or NULL
3148 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3149 u16 udp_port, u8 protocol_index,
3151 struct i40e_asq_cmd_details *cmd_details)
3153 struct i40e_aq_desc desc;
3154 struct i40e_aqc_add_udp_tunnel *cmd =
3155 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3156 struct i40e_aqc_del_udp_tunnel_completion *resp =
3157 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3158 enum i40e_status_code status;
3160 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3162 cmd->udp_port = CPU_TO_LE16(udp_port);
3163 cmd->protocol_type = protocol_index;
3165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3168 *filter_index = resp->index;
3174 * i40e_aq_del_udp_tunnel
3175 * @hw: pointer to the hw struct
3176 * @index: filter index
3177 * @cmd_details: pointer to command details structure or NULL
3179 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3180 struct i40e_asq_cmd_details *cmd_details)
3182 struct i40e_aq_desc desc;
3183 struct i40e_aqc_remove_udp_tunnel *cmd =
3184 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3185 enum i40e_status_code status;
3187 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3191 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3197 * i40e_aq_get_switch_resource_alloc (0x0204)
3198 * @hw: pointer to the hw struct
3199 * @num_entries: pointer to u8 to store the number of resource entries returned
3200 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3201 * to store the resource information for all resource types. Each
3202 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3203 * @count: size, in bytes, of the buffer provided
3204 * @cmd_details: pointer to command details structure or NULL
3206 * Query the resources allocated to a function.
3208 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3210 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3212 struct i40e_asq_cmd_details *cmd_details)
3214 struct i40e_aq_desc desc;
3215 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3216 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3217 enum i40e_status_code status;
3219 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3221 i40e_fill_default_direct_cmd_desc(&desc,
3222 i40e_aqc_opc_get_switch_resource_alloc);
3224 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3225 if (length > I40E_AQ_LARGE_BUF)
3226 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3228 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3231 *num_entries = cmd_resp->num_entries;
3237 * i40e_aq_delete_element - Delete switch element
3238 * @hw: pointer to the hw struct
3239 * @seid: the SEID to delete from the switch
3240 * @cmd_details: pointer to command details structure or NULL
3242 * This deletes a switch element from the switch.
3244 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3245 struct i40e_asq_cmd_details *cmd_details)
3247 struct i40e_aq_desc desc;
3248 struct i40e_aqc_switch_seid *cmd =
3249 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3250 enum i40e_status_code status;
3253 return I40E_ERR_PARAM;
3255 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3257 cmd->seid = CPU_TO_LE16(seid);
3259 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3265 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3266 * @hw: pointer to the hw struct
3267 * @flags: component flags
3268 * @mac_seid: uplink seid (MAC SEID)
3269 * @vsi_seid: connected vsi seid
3270 * @ret_seid: seid of create pv component
3272 * This instantiates an i40e port virtualizer with specified flags.
3273 * Depending on specified flags the port virtualizer can act as a
3274 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3276 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3277 u16 mac_seid, u16 vsi_seid,
3280 struct i40e_aq_desc desc;
3281 struct i40e_aqc_add_update_pv *cmd =
3282 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3283 struct i40e_aqc_add_update_pv_completion *resp =
3284 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3285 enum i40e_status_code status;
3288 return I40E_ERR_PARAM;
3290 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3291 cmd->command_flags = CPU_TO_LE16(flags);
3292 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3293 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3295 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3296 if (!status && ret_seid)
3297 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3303 * i40e_aq_add_tag - Add an S/E-tag
3304 * @hw: pointer to the hw struct
3305 * @direct_to_queue: should s-tag direct flow to a specific queue
3306 * @vsi_seid: VSI SEID to use this tag
3307 * @tag: value of the tag
3308 * @queue_num: queue number, only valid is direct_to_queue is true
3309 * @tags_used: return value, number of tags in use by this PF
3310 * @tags_free: return value, number of unallocated tags
3311 * @cmd_details: pointer to command details structure or NULL
3313 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3314 * the number of tags allocated by the PF, and the number of unallocated
3317 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3318 u16 vsi_seid, u16 tag, u16 queue_num,
3319 u16 *tags_used, u16 *tags_free,
3320 struct i40e_asq_cmd_details *cmd_details)
3322 struct i40e_aq_desc desc;
3323 struct i40e_aqc_add_tag *cmd =
3324 (struct i40e_aqc_add_tag *)&desc.params.raw;
3325 struct i40e_aqc_add_remove_tag_completion *resp =
3326 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3327 enum i40e_status_code status;
3330 return I40E_ERR_PARAM;
3332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3334 cmd->seid = CPU_TO_LE16(vsi_seid);
3335 cmd->tag = CPU_TO_LE16(tag);
3336 if (direct_to_queue) {
3337 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3338 cmd->queue_number = CPU_TO_LE16(queue_num);
3341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3344 if (tags_used != NULL)
3345 *tags_used = LE16_TO_CPU(resp->tags_used);
3346 if (tags_free != NULL)
3347 *tags_free = LE16_TO_CPU(resp->tags_free);
3354 * i40e_aq_remove_tag - Remove an S- or E-tag
3355 * @hw: pointer to the hw struct
3356 * @vsi_seid: VSI SEID this tag is associated with
3357 * @tag: value of the S-tag to delete
3358 * @tags_used: return value, number of tags in use by this PF
3359 * @tags_free: return value, number of unallocated tags
3360 * @cmd_details: pointer to command details structure or NULL
3362 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3363 * the number of tags allocated by the PF, and the number of unallocated
3366 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3367 u16 tag, u16 *tags_used, u16 *tags_free,
3368 struct i40e_asq_cmd_details *cmd_details)
3370 struct i40e_aq_desc desc;
3371 struct i40e_aqc_remove_tag *cmd =
3372 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3373 struct i40e_aqc_add_remove_tag_completion *resp =
3374 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3375 enum i40e_status_code status;
3378 return I40E_ERR_PARAM;
3380 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3382 cmd->seid = CPU_TO_LE16(vsi_seid);
3383 cmd->tag = CPU_TO_LE16(tag);
3385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3388 if (tags_used != NULL)
3389 *tags_used = LE16_TO_CPU(resp->tags_used);
3390 if (tags_free != NULL)
3391 *tags_free = LE16_TO_CPU(resp->tags_free);
3398 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3399 * @hw: pointer to the hw struct
3400 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3401 * @etag: value of E-tag to add
3402 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3403 * @buf: address of indirect buffer
3404 * @tags_used: return value, number of E-tags in use by this port
3405 * @tags_free: return value, number of unallocated M-tags
3406 * @cmd_details: pointer to command details structure or NULL
3408 * This associates a multicast E-tag to a port virtualizer. It will return
3409 * the number of tags allocated by the PF, and the number of unallocated
3412 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3413 * num_tags_in_buf long.
3415 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3416 u16 etag, u8 num_tags_in_buf, void *buf,
3417 u16 *tags_used, u16 *tags_free,
3418 struct i40e_asq_cmd_details *cmd_details)
3420 struct i40e_aq_desc desc;
3421 struct i40e_aqc_add_remove_mcast_etag *cmd =
3422 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3423 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3424 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3425 enum i40e_status_code status;
3426 u16 length = sizeof(u16) * num_tags_in_buf;
3428 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3429 return I40E_ERR_PARAM;
3431 i40e_fill_default_direct_cmd_desc(&desc,
3432 i40e_aqc_opc_add_multicast_etag);
3434 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3435 cmd->etag = CPU_TO_LE16(etag);
3436 cmd->num_unicast_etags = num_tags_in_buf;
3438 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3439 if (length > I40E_AQ_LARGE_BUF)
3440 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3442 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3445 if (tags_used != NULL)
3446 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3447 if (tags_free != NULL)
3448 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3455 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3456 * @hw: pointer to the hw struct
3457 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3458 * @etag: value of the E-tag to remove
3459 * @tags_used: return value, number of tags in use by this port
3460 * @tags_free: return value, number of unallocated tags
3461 * @cmd_details: pointer to command details structure or NULL
3463 * This deletes an E-tag from the port virtualizer. It will return
3464 * the number of tags allocated by the port, and the number of unallocated
3467 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3468 u16 etag, u16 *tags_used, u16 *tags_free,
3469 struct i40e_asq_cmd_details *cmd_details)
3471 struct i40e_aq_desc desc;
3472 struct i40e_aqc_add_remove_mcast_etag *cmd =
3473 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3474 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3475 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3476 enum i40e_status_code status;
3480 return I40E_ERR_PARAM;
3482 i40e_fill_default_direct_cmd_desc(&desc,
3483 i40e_aqc_opc_remove_multicast_etag);
3485 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3486 cmd->etag = CPU_TO_LE16(etag);
3488 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3491 if (tags_used != NULL)
3492 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3493 if (tags_free != NULL)
3494 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3501 * i40e_aq_update_tag - Update an S/E-tag
3502 * @hw: pointer to the hw struct
3503 * @vsi_seid: VSI SEID using this S-tag
3504 * @old_tag: old tag value
3505 * @new_tag: new tag value
3506 * @tags_used: return value, number of tags in use by this PF
3507 * @tags_free: return value, number of unallocated tags
3508 * @cmd_details: pointer to command details structure or NULL
3510 * This updates the value of the tag currently attached to this VSI
3511 * in the switch complex. It will return the number of tags allocated
3512 * by the PF, and the number of unallocated tags available.
3514 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3515 u16 old_tag, u16 new_tag, u16 *tags_used,
3517 struct i40e_asq_cmd_details *cmd_details)
3519 struct i40e_aq_desc desc;
3520 struct i40e_aqc_update_tag *cmd =
3521 (struct i40e_aqc_update_tag *)&desc.params.raw;
3522 struct i40e_aqc_update_tag_completion *resp =
3523 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3524 enum i40e_status_code status;
3527 return I40E_ERR_PARAM;
3529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3531 cmd->seid = CPU_TO_LE16(vsi_seid);
3532 cmd->old_tag = CPU_TO_LE16(old_tag);
3533 cmd->new_tag = CPU_TO_LE16(new_tag);
3535 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3538 if (tags_used != NULL)
3539 *tags_used = LE16_TO_CPU(resp->tags_used);
3540 if (tags_free != NULL)
3541 *tags_free = LE16_TO_CPU(resp->tags_free);
3548 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3549 * @hw: pointer to the hw struct
3550 * @tcmap: TC map for request/release any ignore PFC condition
3551 * @request: request or release ignore PFC condition
3552 * @tcmap_ret: return TCs for which PFC is currently ignored
3553 * @cmd_details: pointer to command details structure or NULL
3555 * This sends out request/release to ignore PFC condition for a TC.
3556 * It will return the TCs for which PFC is currently ignored.
3558 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3559 bool request, u8 *tcmap_ret,
3560 struct i40e_asq_cmd_details *cmd_details)
3562 struct i40e_aq_desc desc;
3563 struct i40e_aqc_pfc_ignore *cmd_resp =
3564 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3565 enum i40e_status_code status;
3567 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3570 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3572 cmd_resp->tc_bitmap = tcmap;
3574 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3577 if (tcmap_ret != NULL)
3578 *tcmap_ret = cmd_resp->tc_bitmap;
3585 * i40e_aq_dcb_updated - DCB Updated Command
3586 * @hw: pointer to the hw struct
3587 * @cmd_details: pointer to command details structure or NULL
3589 * When LLDP is handled in PF this command is used by the PF
3590 * to notify EMP that a DCB setting is modified.
3591 * When LLDP is handled in EMP this command is used by the PF
3592 * to notify EMP whenever one of the following parameters get
3594 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3595 * - PCIRTT in PRTDCB_GENC.PCIRTT
3596 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3597 * EMP will return when the shared RPB settings have been
3598 * recomputed and modified. The retval field in the descriptor
3599 * will be set to 0 when RPB is modified.
3601 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3602 struct i40e_asq_cmd_details *cmd_details)
3604 struct i40e_aq_desc desc;
3605 enum i40e_status_code status;
3607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3615 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3616 * @hw: pointer to the hw struct
3617 * @seid: defines the SEID of the switch for which the stats are requested
3618 * @vlan_id: the VLAN ID for which the statistics are requested
3619 * @stat_index: index of the statistics counters block assigned to this VLAN
3620 * @cmd_details: pointer to command details structure or NULL
3622 * XL710 supports 128 smonVlanStats counters.This command is used to
3623 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3626 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3627 u16 vlan_id, u16 *stat_index,
3628 struct i40e_asq_cmd_details *cmd_details)
3630 struct i40e_aq_desc desc;
3631 struct i40e_aqc_add_remove_statistics *cmd_resp =
3632 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3633 enum i40e_status_code status;
3635 if ((seid == 0) || (stat_index == NULL))
3636 return I40E_ERR_PARAM;
3638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3640 cmd_resp->seid = CPU_TO_LE16(seid);
3641 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3646 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3652 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3653 * @hw: pointer to the hw struct
3654 * @seid: defines the SEID of the switch for which the stats are requested
3655 * @vlan_id: the VLAN ID for which the statistics are requested
3656 * @stat_index: index of the statistics counters block assigned to this VLAN
3657 * @cmd_details: pointer to command details structure or NULL
3659 * XL710 supports 128 smonVlanStats counters.This command is used to
3660 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3663 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3664 u16 vlan_id, u16 stat_index,
3665 struct i40e_asq_cmd_details *cmd_details)
3667 struct i40e_aq_desc desc;
3668 struct i40e_aqc_add_remove_statistics *cmd =
3669 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3670 enum i40e_status_code status;
3673 return I40E_ERR_PARAM;
3675 i40e_fill_default_direct_cmd_desc(&desc,
3676 i40e_aqc_opc_remove_statistics);
3678 cmd->seid = CPU_TO_LE16(seid);
3679 cmd->vlan = CPU_TO_LE16(vlan_id);
3680 cmd->stat_index = CPU_TO_LE16(stat_index);
3682 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3688 * i40e_aq_set_port_parameters - set physical port parameters.
3689 * @hw: pointer to the hw struct
3690 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3691 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3692 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3693 * @double_vlan: if set double VLAN is enabled
3694 * @cmd_details: pointer to command details structure or NULL
3696 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3697 u16 bad_frame_vsi, bool save_bad_pac,
3698 bool pad_short_pac, bool double_vlan,
3699 struct i40e_asq_cmd_details *cmd_details)
3701 struct i40e_aqc_set_port_parameters *cmd;
3702 enum i40e_status_code status;
3703 struct i40e_aq_desc desc;
3704 u16 command_flags = 0;
3706 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3708 i40e_fill_default_direct_cmd_desc(&desc,
3709 i40e_aqc_opc_set_port_parameters);
3711 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3713 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3715 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3717 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3718 cmd->command_flags = CPU_TO_LE16(command_flags);
3720 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3726 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3727 * @hw: pointer to the hw struct
3728 * @seid: seid for the physical port/switching component/vsi
3729 * @buff: Indirect buffer to hold data parameters and response
3730 * @buff_size: Indirect buffer size
3731 * @opcode: Tx scheduler AQ command opcode
3732 * @cmd_details: pointer to command details structure or NULL
3734 * Generic command handler for Tx scheduler AQ commands
3736 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3737 void *buff, u16 buff_size,
3738 enum i40e_admin_queue_opc opcode,
3739 struct i40e_asq_cmd_details *cmd_details)
3741 struct i40e_aq_desc desc;
3742 struct i40e_aqc_tx_sched_ind *cmd =
3743 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3744 enum i40e_status_code status;
3745 bool cmd_param_flag = false;
3748 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3749 case i40e_aqc_opc_configure_vsi_tc_bw:
3750 case i40e_aqc_opc_enable_switching_comp_ets:
3751 case i40e_aqc_opc_modify_switching_comp_ets:
3752 case i40e_aqc_opc_disable_switching_comp_ets:
3753 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3754 case i40e_aqc_opc_configure_switching_comp_bw_config:
3755 cmd_param_flag = true;
3757 case i40e_aqc_opc_query_vsi_bw_config:
3758 case i40e_aqc_opc_query_vsi_ets_sla_config:
3759 case i40e_aqc_opc_query_switching_comp_ets_config:
3760 case i40e_aqc_opc_query_port_ets_config:
3761 case i40e_aqc_opc_query_switching_comp_bw_config:
3762 cmd_param_flag = false;
3765 return I40E_ERR_PARAM;
3768 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3770 /* Indirect command */
3771 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3773 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3774 if (buff_size > I40E_AQ_LARGE_BUF)
3775 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3777 desc.datalen = CPU_TO_LE16(buff_size);
3779 cmd->vsi_seid = CPU_TO_LE16(seid);
3781 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3787 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3788 * @hw: pointer to the hw struct
3790 * @credit: BW limit credits (0 = disabled)
3791 * @max_credit: Max BW limit credits
3792 * @cmd_details: pointer to command details structure or NULL
3794 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3795 u16 seid, u16 credit, u8 max_credit,
3796 struct i40e_asq_cmd_details *cmd_details)
3798 struct i40e_aq_desc desc;
3799 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3800 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3801 enum i40e_status_code status;
3803 i40e_fill_default_direct_cmd_desc(&desc,
3804 i40e_aqc_opc_configure_vsi_bw_limit);
3806 cmd->vsi_seid = CPU_TO_LE16(seid);
3807 cmd->credit = CPU_TO_LE16(credit);
3808 cmd->max_credit = max_credit;
3810 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3816 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3817 * @hw: pointer to the hw struct
3818 * @seid: switching component seid
3819 * @credit: BW limit credits (0 = disabled)
3820 * @max_bw: Max BW limit credits
3821 * @cmd_details: pointer to command details structure or NULL
3823 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3824 u16 seid, u16 credit, u8 max_bw,
3825 struct i40e_asq_cmd_details *cmd_details)
3827 struct i40e_aq_desc desc;
3828 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3829 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3830 enum i40e_status_code status;
3832 i40e_fill_default_direct_cmd_desc(&desc,
3833 i40e_aqc_opc_configure_switching_comp_bw_limit);
3835 cmd->seid = CPU_TO_LE16(seid);
3836 cmd->credit = CPU_TO_LE16(credit);
3837 cmd->max_bw = max_bw;
3839 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3845 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3846 * @hw: pointer to the hw struct
3848 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3849 * @cmd_details: pointer to command details structure or NULL
3851 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3853 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3854 struct i40e_asq_cmd_details *cmd_details)
3856 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3857 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3862 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3863 * @hw: pointer to the hw struct
3865 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3866 * @cmd_details: pointer to command details structure or NULL
3868 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3870 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3871 struct i40e_asq_cmd_details *cmd_details)
3873 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3874 i40e_aqc_opc_configure_vsi_tc_bw,
3879 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
3880 * @hw: pointer to the hw struct
3881 * @seid: seid of the switching component
3882 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3883 * @cmd_details: pointer to command details structure or NULL
3885 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
3886 struct i40e_hw *hw, u16 seid,
3887 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
3888 struct i40e_asq_cmd_details *cmd_details)
3890 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3891 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
3896 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3897 * @hw: pointer to the hw struct
3898 * @seid: seid of the VSI
3899 * @bw_data: Buffer to hold VSI BW configuration
3900 * @cmd_details: pointer to command details structure or NULL
3902 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3904 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3905 struct i40e_asq_cmd_details *cmd_details)
3907 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3908 i40e_aqc_opc_query_vsi_bw_config,
3913 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3914 * @hw: pointer to the hw struct
3915 * @seid: seid of the VSI
3916 * @bw_data: Buffer to hold VSI BW configuration per TC
3917 * @cmd_details: pointer to command details structure or NULL
3919 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3921 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3922 struct i40e_asq_cmd_details *cmd_details)
3924 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3925 i40e_aqc_opc_query_vsi_ets_sla_config,
3930 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3931 * @hw: pointer to the hw struct
3932 * @seid: seid of the switching component
3933 * @bw_data: Buffer to hold switching component's per TC BW config
3934 * @cmd_details: pointer to command details structure or NULL
3936 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3938 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3939 struct i40e_asq_cmd_details *cmd_details)
3941 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3942 i40e_aqc_opc_query_switching_comp_ets_config,
3947 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3948 * @hw: pointer to the hw struct
3949 * @seid: seid of the VSI or switching component connected to Physical Port
3950 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3951 * @cmd_details: pointer to command details structure or NULL
3953 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3955 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3956 struct i40e_asq_cmd_details *cmd_details)
3958 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3959 i40e_aqc_opc_query_port_ets_config,
3964 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3965 * @hw: pointer to the hw struct
3966 * @seid: seid of the switching component
3967 * @bw_data: Buffer to hold switching component's BW configuration
3968 * @cmd_details: pointer to command details structure or NULL
3970 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3972 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3973 struct i40e_asq_cmd_details *cmd_details)
3975 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3976 i40e_aqc_opc_query_switching_comp_bw_config,
3981 * i40e_validate_filter_settings
3982 * @hw: pointer to the hardware structure
3983 * @settings: Filter control settings
3985 * Check and validate the filter control settings passed.
3986 * The function checks for the valid filter/context sizes being
3987 * passed for FCoE and PE.
3989 * Returns I40E_SUCCESS if the values passed are valid and within
3990 * range else returns an error.
3992 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
3993 struct i40e_filter_control_settings *settings)
3995 u32 fcoe_cntx_size, fcoe_filt_size;
3996 u32 pe_cntx_size, pe_filt_size;
4001 /* Validate FCoE settings passed */
4002 switch (settings->fcoe_filt_num) {
4003 case I40E_HASH_FILTER_SIZE_1K:
4004 case I40E_HASH_FILTER_SIZE_2K:
4005 case I40E_HASH_FILTER_SIZE_4K:
4006 case I40E_HASH_FILTER_SIZE_8K:
4007 case I40E_HASH_FILTER_SIZE_16K:
4008 case I40E_HASH_FILTER_SIZE_32K:
4009 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4010 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4013 return I40E_ERR_PARAM;
4016 switch (settings->fcoe_cntx_num) {
4017 case I40E_DMA_CNTX_SIZE_512:
4018 case I40E_DMA_CNTX_SIZE_1K:
4019 case I40E_DMA_CNTX_SIZE_2K:
4020 case I40E_DMA_CNTX_SIZE_4K:
4021 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4022 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4025 return I40E_ERR_PARAM;
4028 /* Validate PE settings passed */
4029 switch (settings->pe_filt_num) {
4030 case I40E_HASH_FILTER_SIZE_1K:
4031 case I40E_HASH_FILTER_SIZE_2K:
4032 case I40E_HASH_FILTER_SIZE_4K:
4033 case I40E_HASH_FILTER_SIZE_8K:
4034 case I40E_HASH_FILTER_SIZE_16K:
4035 case I40E_HASH_FILTER_SIZE_32K:
4036 case I40E_HASH_FILTER_SIZE_64K:
4037 case I40E_HASH_FILTER_SIZE_128K:
4038 case I40E_HASH_FILTER_SIZE_256K:
4039 case I40E_HASH_FILTER_SIZE_512K:
4040 case I40E_HASH_FILTER_SIZE_1M:
4041 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4042 pe_filt_size <<= (u32)settings->pe_filt_num;
4045 return I40E_ERR_PARAM;
4048 switch (settings->pe_cntx_num) {
4049 case I40E_DMA_CNTX_SIZE_512:
4050 case I40E_DMA_CNTX_SIZE_1K:
4051 case I40E_DMA_CNTX_SIZE_2K:
4052 case I40E_DMA_CNTX_SIZE_4K:
4053 case I40E_DMA_CNTX_SIZE_8K:
4054 case I40E_DMA_CNTX_SIZE_16K:
4055 case I40E_DMA_CNTX_SIZE_32K:
4056 case I40E_DMA_CNTX_SIZE_64K:
4057 case I40E_DMA_CNTX_SIZE_128K:
4058 case I40E_DMA_CNTX_SIZE_256K:
4059 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4060 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4063 return I40E_ERR_PARAM;
4066 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4067 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4068 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4069 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4070 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4071 return I40E_ERR_INVALID_SIZE;
4073 return I40E_SUCCESS;
4077 * i40e_set_filter_control
4078 * @hw: pointer to the hardware structure
4079 * @settings: Filter control settings
4081 * Set the Queue Filters for PE/FCoE and enable filters required
4082 * for a single PF. It is expected that these settings are programmed
4083 * at the driver initialization time.
4085 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4086 struct i40e_filter_control_settings *settings)
4088 enum i40e_status_code ret = I40E_SUCCESS;
4089 u32 hash_lut_size = 0;
4093 return I40E_ERR_PARAM;
4095 /* Validate the input settings */
4096 ret = i40e_validate_filter_settings(hw, settings);
4100 /* Read the PF Queue Filter control register */
4101 val = rd32(hw, I40E_PFQF_CTL_0);
4103 /* Program required PE hash buckets for the PF */
4104 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4105 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4106 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4107 /* Program required PE contexts for the PF */
4108 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4109 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4110 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4112 /* Program required FCoE hash buckets for the PF */
4113 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4114 val |= ((u32)settings->fcoe_filt_num <<
4115 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4116 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4117 /* Program required FCoE DDP contexts for the PF */
4118 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4119 val |= ((u32)settings->fcoe_cntx_num <<
4120 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4121 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4123 /* Program Hash LUT size for the PF */
4124 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4125 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4127 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4128 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4130 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4131 if (settings->enable_fdir)
4132 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4133 if (settings->enable_ethtype)
4134 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4135 if (settings->enable_macvlan)
4136 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4138 wr32(hw, I40E_PFQF_CTL_0, val);
4140 return I40E_SUCCESS;
4144 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4145 * @hw: pointer to the hw struct
4146 * @mac_addr: MAC address to use in the filter
4147 * @ethtype: Ethertype to use in the filter
4148 * @flags: Flags that needs to be applied to the filter
4149 * @vsi_seid: seid of the control VSI
4150 * @queue: VSI queue number to send the packet to
4151 * @is_add: Add control packet filter if True else remove
4152 * @stats: Structure to hold information on control filter counts
4153 * @cmd_details: pointer to command details structure or NULL
4155 * This command will Add or Remove control packet filter for a control VSI.
4156 * In return it will update the total number of perfect filter count in
4159 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4160 u8 *mac_addr, u16 ethtype, u16 flags,
4161 u16 vsi_seid, u16 queue, bool is_add,
4162 struct i40e_control_filter_stats *stats,
4163 struct i40e_asq_cmd_details *cmd_details)
4165 struct i40e_aq_desc desc;
4166 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4167 (struct i40e_aqc_add_remove_control_packet_filter *)
4169 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4170 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4172 enum i40e_status_code status;
4175 return I40E_ERR_PARAM;
4178 i40e_fill_default_direct_cmd_desc(&desc,
4179 i40e_aqc_opc_add_control_packet_filter);
4180 cmd->queue = CPU_TO_LE16(queue);
4182 i40e_fill_default_direct_cmd_desc(&desc,
4183 i40e_aqc_opc_remove_control_packet_filter);
4187 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4188 I40E_NONDMA_TO_NONDMA);
4190 cmd->etype = CPU_TO_LE16(ethtype);
4191 cmd->flags = CPU_TO_LE16(flags);
4192 cmd->seid = CPU_TO_LE16(vsi_seid);
4194 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4196 if (!status && stats) {
4197 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4198 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4199 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4200 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4207 * i40e_aq_add_cloud_filters
4208 * @hw: pointer to the hardware structure
4209 * @seid: VSI seid to add cloud filters from
4210 * @filters: Buffer which contains the filters to be added
4211 * @filter_count: number of filters contained in the buffer
4213 * Set the cloud filters for a given VSI. The contents of the
4214 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4215 * in by the caller of the function.
4218 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4220 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4223 struct i40e_aq_desc desc;
4224 struct i40e_aqc_add_remove_cloud_filters *cmd =
4225 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4227 enum i40e_status_code status;
4229 i40e_fill_default_direct_cmd_desc(&desc,
4230 i40e_aqc_opc_add_cloud_filters);
4232 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4234 desc.datalen = CPU_TO_LE16(buff_len);
4235 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4236 cmd->num_filters = filter_count;
4237 cmd->seid = CPU_TO_LE16(seid);
4239 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4245 * i40e_aq_remove_cloud_filters
4246 * @hw: pointer to the hardware structure
4247 * @seid: VSI seid to remove cloud filters from
4248 * @filters: Buffer which contains the filters to be removed
4249 * @filter_count: number of filters contained in the buffer
4251 * Remove the cloud filters for a given VSI. The contents of the
4252 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4253 * in by the caller of the function.
4256 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4258 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4261 struct i40e_aq_desc desc;
4262 struct i40e_aqc_add_remove_cloud_filters *cmd =
4263 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4264 enum i40e_status_code status;
4267 i40e_fill_default_direct_cmd_desc(&desc,
4268 i40e_aqc_opc_remove_cloud_filters);
4270 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4272 desc.datalen = CPU_TO_LE16(buff_len);
4273 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4274 cmd->num_filters = filter_count;
4275 cmd->seid = CPU_TO_LE16(seid);
4277 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4283 * i40e_aq_alternate_write
4284 * @hw: pointer to the hardware structure
4285 * @reg_addr0: address of first dword to be read
4286 * @reg_val0: value to be written under 'reg_addr0'
4287 * @reg_addr1: address of second dword to be read
4288 * @reg_val1: value to be written under 'reg_addr1'
4290 * Write one or two dwords to alternate structure. Fields are indicated
4291 * by 'reg_addr0' and 'reg_addr1' register numbers.
4294 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4295 u32 reg_addr0, u32 reg_val0,
4296 u32 reg_addr1, u32 reg_val1)
4298 struct i40e_aq_desc desc;
4299 struct i40e_aqc_alternate_write *cmd_resp =
4300 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4301 enum i40e_status_code status;
4303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4304 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4305 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4306 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4307 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4309 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4315 * i40e_aq_alternate_write_indirect
4316 * @hw: pointer to the hardware structure
4317 * @addr: address of a first register to be modified
4318 * @dw_count: number of alternate structure fields to write
4319 * @buffer: pointer to the command buffer
4321 * Write 'dw_count' dwords from 'buffer' to alternate structure
4322 * starting at 'addr'.
4325 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4326 u32 addr, u32 dw_count, void *buffer)
4328 struct i40e_aq_desc desc;
4329 struct i40e_aqc_alternate_ind_write *cmd_resp =
4330 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4331 enum i40e_status_code status;
4334 return I40E_ERR_PARAM;
4336 /* Indirect command */
4337 i40e_fill_default_direct_cmd_desc(&desc,
4338 i40e_aqc_opc_alternate_write_indirect);
4340 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4341 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4342 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4343 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4345 cmd_resp->address = CPU_TO_LE32(addr);
4346 cmd_resp->length = CPU_TO_LE32(dw_count);
4347 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4348 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4350 status = i40e_asq_send_command(hw, &desc, buffer,
4351 I40E_LO_DWORD(4*dw_count), NULL);
4357 * i40e_aq_alternate_read
4358 * @hw: pointer to the hardware structure
4359 * @reg_addr0: address of first dword to be read
4360 * @reg_val0: pointer for data read from 'reg_addr0'
4361 * @reg_addr1: address of second dword to be read
4362 * @reg_val1: pointer for data read from 'reg_addr1'
4364 * Read one or two dwords from alternate structure. Fields are indicated
4365 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4366 * is not passed then only register at 'reg_addr0' is read.
4369 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4370 u32 reg_addr0, u32 *reg_val0,
4371 u32 reg_addr1, u32 *reg_val1)
4373 struct i40e_aq_desc desc;
4374 struct i40e_aqc_alternate_write *cmd_resp =
4375 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4376 enum i40e_status_code status;
4378 if (reg_val0 == NULL)
4379 return I40E_ERR_PARAM;
4381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4382 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4383 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4385 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4387 if (status == I40E_SUCCESS) {
4388 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4390 if (reg_val1 != NULL)
4391 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4398 * i40e_aq_alternate_read_indirect
4399 * @hw: pointer to the hardware structure
4400 * @addr: address of the alternate structure field
4401 * @dw_count: number of alternate structure fields to read
4402 * @buffer: pointer to the command buffer
4404 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4405 * place them in 'buffer'. The buffer should be allocated by caller.
4408 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4409 u32 addr, u32 dw_count, void *buffer)
4411 struct i40e_aq_desc desc;
4412 struct i40e_aqc_alternate_ind_write *cmd_resp =
4413 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4414 enum i40e_status_code status;
4417 return I40E_ERR_PARAM;
4419 /* Indirect command */
4420 i40e_fill_default_direct_cmd_desc(&desc,
4421 i40e_aqc_opc_alternate_read_indirect);
4423 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4424 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4425 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4426 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4428 cmd_resp->address = CPU_TO_LE32(addr);
4429 cmd_resp->length = CPU_TO_LE32(dw_count);
4430 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4431 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4433 status = i40e_asq_send_command(hw, &desc, buffer,
4434 I40E_LO_DWORD(4*dw_count), NULL);
4440 * i40e_aq_alternate_clear
4441 * @hw: pointer to the HW structure.
4443 * Clear the alternate structures of the port from which the function
4447 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4449 struct i40e_aq_desc desc;
4450 enum i40e_status_code status;
4452 i40e_fill_default_direct_cmd_desc(&desc,
4453 i40e_aqc_opc_alternate_clear_port);
4455 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4461 * i40e_aq_alternate_write_done
4462 * @hw: pointer to the HW structure.
4463 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4464 * @reset_needed: indicates the SW should trigger GLOBAL reset
4466 * Indicates to the FW that alternate structures have been changed.
4469 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4470 u8 bios_mode, bool *reset_needed)
4472 struct i40e_aq_desc desc;
4473 struct i40e_aqc_alternate_write_done *cmd =
4474 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4475 enum i40e_status_code status;
4477 if (reset_needed == NULL)
4478 return I40E_ERR_PARAM;
4480 i40e_fill_default_direct_cmd_desc(&desc,
4481 i40e_aqc_opc_alternate_write_done);
4483 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4485 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4487 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4488 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4494 * i40e_aq_set_oem_mode
4495 * @hw: pointer to the HW structure.
4496 * @oem_mode: the OEM mode to be used
4498 * Sets the device to a specific operating mode. Currently the only supported
4499 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4502 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4505 struct i40e_aq_desc desc;
4506 struct i40e_aqc_alternate_write_done *cmd =
4507 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4508 enum i40e_status_code status;
4510 i40e_fill_default_direct_cmd_desc(&desc,
4511 i40e_aqc_opc_alternate_set_mode);
4513 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4515 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4521 * i40e_aq_resume_port_tx
4522 * @hw: pointer to the hardware structure
4523 * @cmd_details: pointer to command details structure or NULL
4525 * Resume port's Tx traffic
4527 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4528 struct i40e_asq_cmd_details *cmd_details)
4530 struct i40e_aq_desc desc;
4531 enum i40e_status_code status;
4533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4535 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4541 * i40e_set_pci_config_data - store PCI bus info
4542 * @hw: pointer to hardware structure
4543 * @link_status: the link status word from PCI config space
4545 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4547 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4549 hw->bus.type = i40e_bus_type_pci_express;
4551 switch (link_status & I40E_PCI_LINK_WIDTH) {
4552 case I40E_PCI_LINK_WIDTH_1:
4553 hw->bus.width = i40e_bus_width_pcie_x1;
4555 case I40E_PCI_LINK_WIDTH_2:
4556 hw->bus.width = i40e_bus_width_pcie_x2;
4558 case I40E_PCI_LINK_WIDTH_4:
4559 hw->bus.width = i40e_bus_width_pcie_x4;
4561 case I40E_PCI_LINK_WIDTH_8:
4562 hw->bus.width = i40e_bus_width_pcie_x8;
4565 hw->bus.width = i40e_bus_width_unknown;
4569 switch (link_status & I40E_PCI_LINK_SPEED) {
4570 case I40E_PCI_LINK_SPEED_2500:
4571 hw->bus.speed = i40e_bus_speed_2500;
4573 case I40E_PCI_LINK_SPEED_5000:
4574 hw->bus.speed = i40e_bus_speed_5000;
4576 case I40E_PCI_LINK_SPEED_8000:
4577 hw->bus.speed = i40e_bus_speed_8000;
4580 hw->bus.speed = i40e_bus_speed_unknown;
4586 * i40e_read_bw_from_alt_ram
4587 * @hw: pointer to the hardware structure
4588 * @max_bw: pointer for max_bw read
4589 * @min_bw: pointer for min_bw read
4590 * @min_valid: pointer for bool that is true if min_bw is a valid value
4591 * @max_valid: pointer for bool that is true if max_bw is a valid value
4593 * Read bw from the alternate ram for the given pf
4595 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4596 u32 *max_bw, u32 *min_bw,
4597 bool *min_valid, bool *max_valid)
4599 enum i40e_status_code status;
4600 u32 max_bw_addr, min_bw_addr;
4602 /* Calculate the address of the min/max bw registers */
4603 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4604 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4605 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4606 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4607 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4608 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4610 /* Read the bandwidths from alt ram */
4611 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4612 min_bw_addr, min_bw);
4614 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4619 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4628 * i40e_aq_configure_partition_bw
4629 * @hw: pointer to the hardware structure
4630 * @bw_data: Buffer holding valid pfs and bw limits
4631 * @cmd_details: pointer to command details
4633 * Configure partitions guaranteed/max bw
4635 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4636 struct i40e_aqc_configure_partition_bw_data *bw_data,
4637 struct i40e_asq_cmd_details *cmd_details)
4639 enum i40e_status_code status;
4640 struct i40e_aq_desc desc;
4641 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4643 i40e_fill_default_direct_cmd_desc(&desc,
4644 i40e_aqc_opc_configure_partition_bw);
4646 /* Indirect command */
4647 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4648 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4650 if (bwd_size > I40E_AQ_LARGE_BUF)
4651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4653 desc.datalen = CPU_TO_LE16(bwd_size);
4655 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4661 * i40e_aq_send_msg_to_pf
4662 * @hw: pointer to the hardware structure
4663 * @v_opcode: opcodes for VF-PF communication
4664 * @v_retval: return error code
4665 * @msg: pointer to the msg buffer
4666 * @msglen: msg length
4667 * @cmd_details: pointer to command details
4669 * Send message to PF driver using admin queue. By default, this message
4670 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4671 * completion before returning.
4673 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4674 enum i40e_virtchnl_ops v_opcode,
4675 enum i40e_status_code v_retval,
4676 u8 *msg, u16 msglen,
4677 struct i40e_asq_cmd_details *cmd_details)
4679 struct i40e_aq_desc desc;
4680 struct i40e_asq_cmd_details details;
4681 enum i40e_status_code status;
4683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4684 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4685 desc.cookie_high = CPU_TO_LE32(v_opcode);
4686 desc.cookie_low = CPU_TO_LE32(v_retval);
4688 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4689 | I40E_AQ_FLAG_RD));
4690 if (msglen > I40E_AQ_LARGE_BUF)
4691 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4692 desc.datalen = CPU_TO_LE16(msglen);
4695 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4696 details.async = true;
4697 cmd_details = &details;
4699 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4700 msglen, cmd_details);
4705 * i40e_vf_parse_hw_config
4706 * @hw: pointer to the hardware structure
4707 * @msg: pointer to the virtual channel VF resource structure
4709 * Given a VF resource message from the PF, populate the hw struct
4710 * with appropriate information.
4712 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4713 struct i40e_virtchnl_vf_resource *msg)
4715 struct i40e_virtchnl_vsi_resource *vsi_res;
4718 vsi_res = &msg->vsi_res[0];
4720 hw->dev_caps.num_vsis = msg->num_vsis;
4721 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4722 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4723 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4724 hw->dev_caps.dcb = msg->vf_offload_flags &
4725 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4726 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4727 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4728 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4729 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4730 for (i = 0; i < msg->num_vsis; i++) {
4731 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4732 i40e_memcpy(hw->mac.perm_addr,
4733 vsi_res->default_mac_addr,
4734 I40E_ETH_LENGTH_OF_ADDRESS,
4735 I40E_NONDMA_TO_NONDMA);
4736 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4737 I40E_ETH_LENGTH_OF_ADDRESS,
4738 I40E_NONDMA_TO_NONDMA);
4746 * @hw: pointer to the hardware structure
4748 * Send a VF_RESET message to the PF. Does not wait for response from PF
4749 * as none will be forthcoming. Immediately after calling this function,
4750 * the admin queue should be shut down and (optionally) reinitialized.
4752 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4754 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4755 I40E_SUCCESS, NULL, 0, NULL);
4757 #endif /* VF_DRIVER */