1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *buf = (u8 *)buffer;
104 if ((!(mask & hw->debug_mask)) || (desc == NULL))
108 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
109 LE16_TO_CPU(aq_desc->opcode),
110 LE16_TO_CPU(aq_desc->flags),
111 LE16_TO_CPU(aq_desc->datalen),
112 LE16_TO_CPU(aq_desc->retval));
113 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
114 LE32_TO_CPU(aq_desc->cookie_high),
115 LE32_TO_CPU(aq_desc->cookie_low));
116 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
117 LE32_TO_CPU(aq_desc->params.internal.param0),
118 LE32_TO_CPU(aq_desc->params.internal.param1));
119 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
120 LE32_TO_CPU(aq_desc->params.external.addr_high),
121 LE32_TO_CPU(aq_desc->params.external.addr_low));
123 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
124 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
127 /* write the full 16-byte chunks */
128 for (i = 0; i < (len - 16); i += 16)
130 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
131 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
132 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
133 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
134 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
135 /* write whatever's left over without overrunning the buffer */
140 memset(d_buf, 0, sizeof(d_buf));
141 j += sprintf(d_buf, "\t0x%04X ", i);
143 j += sprintf(&d_buf[j], " %02X", buf[i++]);
144 i40e_debug(hw, mask, "%s\n", d_buf);
150 * i40e_check_asq_alive
151 * @hw: pointer to the hw struct
153 * Returns true if Queue is enabled else false.
155 bool i40e_check_asq_alive(struct i40e_hw *hw)
158 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
164 * i40e_aq_queue_shutdown
165 * @hw: pointer to the hw struct
166 * @unloading: is the driver unloading itself
168 * Tell the Firmware that we're shutting down the AdminQ and whether
169 * or not the driver is unloading as well.
171 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
174 struct i40e_aq_desc desc;
175 struct i40e_aqc_queue_shutdown *cmd =
176 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
177 enum i40e_status_code status;
179 i40e_fill_default_direct_cmd_desc(&desc,
180 i40e_aqc_opc_queue_shutdown);
183 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
189 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
190 * hardware to a bit-field that can be used by SW to more easily determine the
193 * Macros are used to shorten the table lines and make this table human
196 * We store the PTYPE in the top byte of the bit field - this is just so that
197 * we can check that the table doesn't have a row missing, as the index into
198 * the table should be the PTYPE.
202 * IF NOT i40e_ptype_lookup[ptype].known
205 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
206 * Use the rest of the fields to look at the tunnels, inner protocols, etc
208 * Use the enum i40e_rx_l2_ptype to decode the packet type
212 /* macro to make the table lines short */
213 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
216 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
217 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
218 I40E_RX_PTYPE_##OUTER_FRAG, \
219 I40E_RX_PTYPE_TUNNEL_##T, \
220 I40E_RX_PTYPE_TUNNEL_END_##TE, \
221 I40E_RX_PTYPE_##TEF, \
222 I40E_RX_PTYPE_INNER_PROT_##I, \
223 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
225 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
226 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
228 /* shorter macros makes the table fit but are terse */
229 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
230 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
231 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
233 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
234 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
235 /* L2 Packet types */
236 I40E_PTT_UNUSED_ENTRY(0),
237 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
239 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(4),
241 I40E_PTT_UNUSED_ENTRY(5),
242 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(8),
245 I40E_PTT_UNUSED_ENTRY(9),
246 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
248 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 /* Non Tunneled IPv4 */
260 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(25),
264 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
265 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
266 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
269 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
270 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
271 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(32),
273 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
274 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
275 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
278 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
279 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
280 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
281 I40E_PTT_UNUSED_ENTRY(39),
282 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
283 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
284 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
286 /* IPv4 --> GRE/NAT */
287 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
289 /* IPv4 --> GRE/NAT --> IPv4 */
290 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
291 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
292 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(47),
294 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
295 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
296 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> IPv6 */
299 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
300 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
301 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
302 I40E_PTT_UNUSED_ENTRY(54),
303 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
304 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
305 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
307 /* IPv4 --> GRE/NAT --> MAC */
308 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
310 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
311 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
312 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
313 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(62),
315 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
316 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
317 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
320 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
321 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
322 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
323 I40E_PTT_UNUSED_ENTRY(69),
324 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
325 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
326 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
328 /* IPv4 --> GRE/NAT --> MAC/VLAN */
329 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
331 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
332 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
333 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
334 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(77),
336 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
337 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
338 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
340 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
341 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
342 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
343 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(84),
345 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
346 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
347 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
349 /* Non Tunneled IPv6 */
350 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
353 I40E_PTT_UNUSED_ENTRY(91),
354 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
355 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
356 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
359 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
360 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
361 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(98),
363 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
364 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
365 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
368 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
369 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
370 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
371 I40E_PTT_UNUSED_ENTRY(105),
372 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
373 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
374 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
376 /* IPv6 --> GRE/NAT */
377 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
379 /* IPv6 --> GRE/NAT -> IPv4 */
380 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
381 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
382 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(113),
384 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
385 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
386 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> IPv6 */
389 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
390 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
391 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
392 I40E_PTT_UNUSED_ENTRY(120),
393 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
394 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
395 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
397 /* IPv6 --> GRE/NAT -> MAC */
398 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
401 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
402 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
403 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(128),
405 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
406 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
407 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
410 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
411 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
412 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
413 I40E_PTT_UNUSED_ENTRY(135),
414 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
415 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
416 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
418 /* IPv6 --> GRE/NAT -> MAC/VLAN */
419 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
422 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
423 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
424 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(143),
426 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
427 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
428 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
430 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
431 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
432 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
433 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
434 I40E_PTT_UNUSED_ENTRY(150),
435 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
436 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
437 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
440 I40E_PTT_UNUSED_ENTRY(154),
441 I40E_PTT_UNUSED_ENTRY(155),
442 I40E_PTT_UNUSED_ENTRY(156),
443 I40E_PTT_UNUSED_ENTRY(157),
444 I40E_PTT_UNUSED_ENTRY(158),
445 I40E_PTT_UNUSED_ENTRY(159),
447 I40E_PTT_UNUSED_ENTRY(160),
448 I40E_PTT_UNUSED_ENTRY(161),
449 I40E_PTT_UNUSED_ENTRY(162),
450 I40E_PTT_UNUSED_ENTRY(163),
451 I40E_PTT_UNUSED_ENTRY(164),
452 I40E_PTT_UNUSED_ENTRY(165),
453 I40E_PTT_UNUSED_ENTRY(166),
454 I40E_PTT_UNUSED_ENTRY(167),
455 I40E_PTT_UNUSED_ENTRY(168),
456 I40E_PTT_UNUSED_ENTRY(169),
458 I40E_PTT_UNUSED_ENTRY(170),
459 I40E_PTT_UNUSED_ENTRY(171),
460 I40E_PTT_UNUSED_ENTRY(172),
461 I40E_PTT_UNUSED_ENTRY(173),
462 I40E_PTT_UNUSED_ENTRY(174),
463 I40E_PTT_UNUSED_ENTRY(175),
464 I40E_PTT_UNUSED_ENTRY(176),
465 I40E_PTT_UNUSED_ENTRY(177),
466 I40E_PTT_UNUSED_ENTRY(178),
467 I40E_PTT_UNUSED_ENTRY(179),
469 I40E_PTT_UNUSED_ENTRY(180),
470 I40E_PTT_UNUSED_ENTRY(181),
471 I40E_PTT_UNUSED_ENTRY(182),
472 I40E_PTT_UNUSED_ENTRY(183),
473 I40E_PTT_UNUSED_ENTRY(184),
474 I40E_PTT_UNUSED_ENTRY(185),
475 I40E_PTT_UNUSED_ENTRY(186),
476 I40E_PTT_UNUSED_ENTRY(187),
477 I40E_PTT_UNUSED_ENTRY(188),
478 I40E_PTT_UNUSED_ENTRY(189),
480 I40E_PTT_UNUSED_ENTRY(190),
481 I40E_PTT_UNUSED_ENTRY(191),
482 I40E_PTT_UNUSED_ENTRY(192),
483 I40E_PTT_UNUSED_ENTRY(193),
484 I40E_PTT_UNUSED_ENTRY(194),
485 I40E_PTT_UNUSED_ENTRY(195),
486 I40E_PTT_UNUSED_ENTRY(196),
487 I40E_PTT_UNUSED_ENTRY(197),
488 I40E_PTT_UNUSED_ENTRY(198),
489 I40E_PTT_UNUSED_ENTRY(199),
491 I40E_PTT_UNUSED_ENTRY(200),
492 I40E_PTT_UNUSED_ENTRY(201),
493 I40E_PTT_UNUSED_ENTRY(202),
494 I40E_PTT_UNUSED_ENTRY(203),
495 I40E_PTT_UNUSED_ENTRY(204),
496 I40E_PTT_UNUSED_ENTRY(205),
497 I40E_PTT_UNUSED_ENTRY(206),
498 I40E_PTT_UNUSED_ENTRY(207),
499 I40E_PTT_UNUSED_ENTRY(208),
500 I40E_PTT_UNUSED_ENTRY(209),
502 I40E_PTT_UNUSED_ENTRY(210),
503 I40E_PTT_UNUSED_ENTRY(211),
504 I40E_PTT_UNUSED_ENTRY(212),
505 I40E_PTT_UNUSED_ENTRY(213),
506 I40E_PTT_UNUSED_ENTRY(214),
507 I40E_PTT_UNUSED_ENTRY(215),
508 I40E_PTT_UNUSED_ENTRY(216),
509 I40E_PTT_UNUSED_ENTRY(217),
510 I40E_PTT_UNUSED_ENTRY(218),
511 I40E_PTT_UNUSED_ENTRY(219),
513 I40E_PTT_UNUSED_ENTRY(220),
514 I40E_PTT_UNUSED_ENTRY(221),
515 I40E_PTT_UNUSED_ENTRY(222),
516 I40E_PTT_UNUSED_ENTRY(223),
517 I40E_PTT_UNUSED_ENTRY(224),
518 I40E_PTT_UNUSED_ENTRY(225),
519 I40E_PTT_UNUSED_ENTRY(226),
520 I40E_PTT_UNUSED_ENTRY(227),
521 I40E_PTT_UNUSED_ENTRY(228),
522 I40E_PTT_UNUSED_ENTRY(229),
524 I40E_PTT_UNUSED_ENTRY(230),
525 I40E_PTT_UNUSED_ENTRY(231),
526 I40E_PTT_UNUSED_ENTRY(232),
527 I40E_PTT_UNUSED_ENTRY(233),
528 I40E_PTT_UNUSED_ENTRY(234),
529 I40E_PTT_UNUSED_ENTRY(235),
530 I40E_PTT_UNUSED_ENTRY(236),
531 I40E_PTT_UNUSED_ENTRY(237),
532 I40E_PTT_UNUSED_ENTRY(238),
533 I40E_PTT_UNUSED_ENTRY(239),
535 I40E_PTT_UNUSED_ENTRY(240),
536 I40E_PTT_UNUSED_ENTRY(241),
537 I40E_PTT_UNUSED_ENTRY(242),
538 I40E_PTT_UNUSED_ENTRY(243),
539 I40E_PTT_UNUSED_ENTRY(244),
540 I40E_PTT_UNUSED_ENTRY(245),
541 I40E_PTT_UNUSED_ENTRY(246),
542 I40E_PTT_UNUSED_ENTRY(247),
543 I40E_PTT_UNUSED_ENTRY(248),
544 I40E_PTT_UNUSED_ENTRY(249),
546 I40E_PTT_UNUSED_ENTRY(250),
547 I40E_PTT_UNUSED_ENTRY(251),
548 I40E_PTT_UNUSED_ENTRY(252),
549 I40E_PTT_UNUSED_ENTRY(253),
550 I40E_PTT_UNUSED_ENTRY(254),
551 I40E_PTT_UNUSED_ENTRY(255)
557 * i40e_init_shared_code - Initialize the shared code
558 * @hw: pointer to hardware structure
560 * This assigns the MAC type and PHY code and inits the NVM.
561 * Does not touch the hardware. This function must be called prior to any
562 * other function in the shared code. The i40e_hw structure should be
563 * memset to 0 prior to calling this function. The following fields in
564 * hw structure should be filled in prior to calling this function:
565 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
566 * subsystem_vendor_id, and revision_id
568 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
570 enum i40e_status_code status = I40E_SUCCESS;
573 DEBUGFUNC("i40e_init_shared_code");
575 i40e_set_mac_type(hw);
577 switch (hw->mac.type) {
581 return I40E_ERR_DEVICE_NOT_SUPPORTED;
584 hw->phy.get_link_info = true;
586 /* Determine port number */
587 reg = rd32(hw, I40E_PFGEN_PORTNUM);
588 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
589 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
592 /* Determine the PF number based on the PCI fn */
593 reg = rd32(hw, I40E_GLPCI_CAPSUP);
594 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
595 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
597 hw->pf_id = (u8)hw->bus.func;
599 status = i40e_init_nvm(hw);
604 * i40e_aq_mac_address_read - Retrieve the MAC addresses
605 * @hw: pointer to the hw struct
606 * @flags: a return indicator of what addresses were added to the addr store
607 * @addrs: the requestor's mac addr store
608 * @cmd_details: pointer to command details structure or NULL
610 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
612 struct i40e_aqc_mac_address_read_data *addrs,
613 struct i40e_asq_cmd_details *cmd_details)
615 struct i40e_aq_desc desc;
616 struct i40e_aqc_mac_address_read *cmd_data =
617 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
618 enum i40e_status_code status;
620 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
621 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
623 status = i40e_asq_send_command(hw, &desc, addrs,
624 sizeof(*addrs), cmd_details);
625 *flags = LE16_TO_CPU(cmd_data->command_flags);
631 * i40e_aq_mac_address_write - Change the MAC addresses
632 * @hw: pointer to the hw struct
633 * @flags: indicates which MAC to be written
634 * @mac_addr: address to write
635 * @cmd_details: pointer to command details structure or NULL
637 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
638 u16 flags, u8 *mac_addr,
639 struct i40e_asq_cmd_details *cmd_details)
641 struct i40e_aq_desc desc;
642 struct i40e_aqc_mac_address_write *cmd_data =
643 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
644 enum i40e_status_code status;
646 i40e_fill_default_direct_cmd_desc(&desc,
647 i40e_aqc_opc_mac_address_write);
648 cmd_data->command_flags = CPU_TO_LE16(flags);
649 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
650 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
651 ((u32)mac_addr[3] << 16) |
652 ((u32)mac_addr[4] << 8) |
655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
661 * i40e_get_mac_addr - get MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to MAC address
665 * Reads the adapter's MAC address from register
667 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
669 struct i40e_aqc_mac_address_read_data addrs;
670 enum i40e_status_code status;
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
675 if (flags & I40E_AQC_LAN_ADDR_VALID)
676 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
682 * i40e_get_port_mac_addr - get Port MAC address
683 * @hw: pointer to the HW structure
684 * @mac_addr: pointer to Port MAC address
686 * Reads the adapter's Port MAC address
688 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
690 struct i40e_aqc_mac_address_read_data addrs;
691 enum i40e_status_code status;
694 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
698 if (flags & I40E_AQC_PORT_ADDR_VALID)
699 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
701 status = I40E_ERR_INVALID_MAC_ADDR;
707 * i40e_pre_tx_queue_cfg - pre tx queue configure
708 * @hw: pointer to the HW structure
709 * @queue: target pf queue index
710 * @enable: state change request
712 * Handles hw requirement to indicate intention to enable
713 * or disable target queue.
715 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
717 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
721 if (abs_queue_idx >= 128) {
722 reg_block = abs_queue_idx / 128;
723 abs_queue_idx %= 128;
726 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
727 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
728 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
731 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
733 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
735 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
739 * i40e_validate_mac_addr - Validate unicast MAC address
740 * @mac_addr: pointer to MAC address
742 * Tests a MAC address to ensure it is a valid Individual Address
744 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
746 enum i40e_status_code status = I40E_SUCCESS;
748 DEBUGFUNC("i40e_validate_mac_addr");
750 /* Broadcast addresses ARE multicast addresses
751 * Make sure it is not a multicast address
752 * Reject the zero address
754 if (I40E_IS_MULTICAST(mac_addr) ||
755 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
756 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
757 status = I40E_ERR_INVALID_MAC_ADDR;
763 * i40e_get_media_type - Gets media type
764 * @hw: pointer to the hardware structure
766 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
768 enum i40e_media_type media;
770 switch (hw->phy.link_info.phy_type) {
771 case I40E_PHY_TYPE_10GBASE_SR:
772 case I40E_PHY_TYPE_10GBASE_LR:
773 case I40E_PHY_TYPE_1000BASE_SX:
774 case I40E_PHY_TYPE_1000BASE_LX:
775 case I40E_PHY_TYPE_40GBASE_SR4:
776 case I40E_PHY_TYPE_40GBASE_LR4:
777 media = I40E_MEDIA_TYPE_FIBER;
779 case I40E_PHY_TYPE_100BASE_TX:
780 case I40E_PHY_TYPE_1000BASE_T:
781 case I40E_PHY_TYPE_10GBASE_T:
782 media = I40E_MEDIA_TYPE_BASET;
784 case I40E_PHY_TYPE_10GBASE_CR1_CU:
785 case I40E_PHY_TYPE_40GBASE_CR4_CU:
786 case I40E_PHY_TYPE_10GBASE_CR1:
787 case I40E_PHY_TYPE_40GBASE_CR4:
788 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
789 media = I40E_MEDIA_TYPE_DA;
791 case I40E_PHY_TYPE_1000BASE_KX:
792 case I40E_PHY_TYPE_10GBASE_KX4:
793 case I40E_PHY_TYPE_10GBASE_KR:
794 case I40E_PHY_TYPE_40GBASE_KR4:
795 media = I40E_MEDIA_TYPE_BACKPLANE;
797 case I40E_PHY_TYPE_SGMII:
798 case I40E_PHY_TYPE_XAUI:
799 case I40E_PHY_TYPE_XFI:
800 case I40E_PHY_TYPE_XLAUI:
801 case I40E_PHY_TYPE_XLPPI:
803 media = I40E_MEDIA_TYPE_UNKNOWN;
810 #define I40E_PF_RESET_WAIT_COUNT 100
812 * i40e_pf_reset - Reset the PF
813 * @hw: pointer to the hardware structure
815 * Assuming someone else has triggered a global reset,
816 * assure the global reset is complete and then reset the PF
818 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
825 /* Poll for Global Reset steady state in case of recent GRST.
826 * The grst delay value is in 100ms units, and we'll wait a
827 * couple counts longer to be sure we don't just miss the end.
829 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
830 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
831 for (cnt = 0; cnt < grst_del + 2; cnt++) {
832 reg = rd32(hw, I40E_GLGEN_RSTAT);
833 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
835 i40e_msec_delay(100);
837 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
838 DEBUGOUT("Global reset polling failed to complete.\n");
839 return I40E_ERR_RESET_FAILED;
842 /* Now Wait for the FW to be ready */
843 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
844 reg = rd32(hw, I40E_GLNVM_ULD);
845 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
846 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
847 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
848 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
849 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
854 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
855 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
856 DEBUGOUT("wait for FW Reset complete timedout\n");
857 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
858 return I40E_ERR_RESET_FAILED;
861 /* If there was a Global Reset in progress when we got here,
862 * we don't need to do the PF Reset
865 reg = rd32(hw, I40E_PFGEN_CTRL);
866 wr32(hw, I40E_PFGEN_CTRL,
867 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
868 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
869 reg = rd32(hw, I40E_PFGEN_CTRL);
870 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
874 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
875 DEBUGOUT("PF reset polling failed to complete.\n");
876 return I40E_ERR_RESET_FAILED;
880 i40e_clear_pxe_mode(hw);
887 * i40e_clear_hw - clear out any left over hw state
888 * @hw: pointer to the hw struct
890 * Clear queues and interrupts, typically called at init time,
891 * but after the capabilities have been found so we know how many
892 * queues and msix vectors have been allocated.
894 void i40e_clear_hw(struct i40e_hw *hw)
896 u32 num_queues, base_queue;
904 /* get number of interrupts, queues, and vfs */
905 val = rd32(hw, I40E_GLPCI_CNF2);
906 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
907 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
908 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
909 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
911 val = rd32(hw, I40E_PFLAN_QALLOC);
912 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
913 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
914 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
915 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
916 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
917 num_queues = (j - base_queue) + 1;
921 val = rd32(hw, I40E_PF_VT_PFALLOC);
922 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
923 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
924 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
925 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
926 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
927 num_vfs = (j - i) + 1;
931 /* stop all the interrupts */
932 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
933 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
934 for (i = 0; i < num_pf_int - 2; i++)
935 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
937 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
938 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
939 wr32(hw, I40E_PFINT_LNKLST0, val);
940 for (i = 0; i < num_pf_int - 2; i++)
941 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
942 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
943 for (i = 0; i < num_vfs; i++)
944 wr32(hw, I40E_VPINT_LNKLST0(i), val);
945 for (i = 0; i < num_vf_int - 2; i++)
946 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
948 /* warn the HW of the coming Tx disables */
949 for (i = 0; i < num_queues; i++) {
950 u32 abs_queue_idx = base_queue + i;
953 if (abs_queue_idx >= 128) {
954 reg_block = abs_queue_idx / 128;
955 abs_queue_idx %= 128;
958 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
959 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
960 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
961 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
963 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
965 i40e_usec_delay(400);
967 /* stop all the queues */
968 for (i = 0; i < num_queues; i++) {
969 wr32(hw, I40E_QINT_TQCTL(i), 0);
970 wr32(hw, I40E_QTX_ENA(i), 0);
971 wr32(hw, I40E_QINT_RQCTL(i), 0);
972 wr32(hw, I40E_QRX_ENA(i), 0);
975 /* short wait for all queue disables to settle */
980 * i40e_clear_pxe_mode - clear pxe operations mode
981 * @hw: pointer to the hw struct
983 * Make sure all PXE mode settings are cleared, including things
984 * like descriptor fetch/write-back mode.
986 void i40e_clear_pxe_mode(struct i40e_hw *hw)
988 if (i40e_check_asq_alive(hw))
989 i40e_aq_clear_pxe_mode(hw, NULL);
993 * i40e_led_is_mine - helper to find matching led
994 * @hw: pointer to the hw struct
995 * @idx: index into GPIO registers
997 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
999 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1004 if (!hw->func_caps.led[idx])
1007 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1008 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1009 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1011 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1012 * if it is not our port then ignore
1014 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1021 #define I40E_COMBINED_ACTIVITY 0xA
1022 #define I40E_FILTER_ACTIVITY 0xE
1023 #define I40E_LINK_ACTIVITY 0xC
1024 #define I40E_MAC_ACTIVITY 0xD
1025 #define I40E_LED0 22
1028 * i40e_led_get - return current on/off mode
1029 * @hw: pointer to the hw struct
1031 * The value returned is the 'mode' field as defined in the
1032 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1033 * values are variations of possible behaviors relating to
1034 * blink, link, and wire.
1036 u32 i40e_led_get(struct i40e_hw *hw)
1038 u32 current_mode = 0;
1042 /* as per the documentation GPIO 22-29 are the LED
1043 * GPIO pins named LED0..LED7
1045 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1046 u32 gpio_val = i40e_led_is_mine(hw, i);
1051 /* ignore gpio LED src mode entries related to the activity LEDs */
1052 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1053 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1054 switch (current_mode) {
1055 case I40E_COMBINED_ACTIVITY:
1056 case I40E_FILTER_ACTIVITY:
1057 case I40E_MAC_ACTIVITY:
1063 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1064 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1072 * i40e_led_set - set new on/off mode
1073 * @hw: pointer to the hw struct
1074 * @mode: 0=off, 0xf=on (else see manual for mode details)
1075 * @blink: true if the LED should blink when on, false if steady
1077 * if this function is used to turn on the blink it should
1078 * be used to disable the blink when restoring the original state.
1080 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1082 u32 current_mode = 0;
1085 if (mode & 0xfffffff0)
1086 DEBUGOUT1("invalid mode passed in %X\n", mode);
1088 /* as per the documentation GPIO 22-29 are the LED
1089 * GPIO pins named LED0..LED7
1091 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1092 u32 gpio_val = i40e_led_is_mine(hw, i);
1097 /* ignore gpio LED src mode entries related to the activity LEDs */
1098 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1099 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1100 switch (current_mode) {
1101 case I40E_COMBINED_ACTIVITY:
1102 case I40E_FILTER_ACTIVITY:
1103 case I40E_MAC_ACTIVITY:
1109 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1110 /* this & is a bit of paranoia, but serves as a range check */
1111 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1112 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1114 if (mode == I40E_LINK_ACTIVITY)
1118 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1120 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1122 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1127 /* Admin command wrappers */
1130 * i40e_aq_get_phy_capabilities
1131 * @hw: pointer to the hw struct
1132 * @abilities: structure for PHY capabilities to be filled
1133 * @qualified_modules: report Qualified Modules
1134 * @report_init: report init capabilities (active are default)
1135 * @cmd_details: pointer to command details structure or NULL
1137 * Returns the various PHY abilities supported on the Port.
1139 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1140 bool qualified_modules, bool report_init,
1141 struct i40e_aq_get_phy_abilities_resp *abilities,
1142 struct i40e_asq_cmd_details *cmd_details)
1144 struct i40e_aq_desc desc;
1145 enum i40e_status_code status;
1146 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1149 return I40E_ERR_PARAM;
1151 i40e_fill_default_direct_cmd_desc(&desc,
1152 i40e_aqc_opc_get_phy_abilities);
1154 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1155 if (abilities_size > I40E_AQ_LARGE_BUF)
1156 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1158 if (qualified_modules)
1159 desc.params.external.param0 |=
1160 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1163 desc.params.external.param0 |=
1164 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1166 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1169 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1170 status = I40E_ERR_UNKNOWN_PHY;
1176 * i40e_aq_set_phy_config
1177 * @hw: pointer to the hw struct
1178 * @config: structure with PHY configuration to be set
1179 * @cmd_details: pointer to command details structure or NULL
1181 * Set the various PHY configuration parameters
1182 * supported on the Port.One or more of the Set PHY config parameters may be
1183 * ignored in an MFP mode as the PF may not have the privilege to set some
1184 * of the PHY Config parameters. This status will be indicated by the
1187 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1188 struct i40e_aq_set_phy_config *config,
1189 struct i40e_asq_cmd_details *cmd_details)
1191 struct i40e_aq_desc desc;
1192 struct i40e_aq_set_phy_config *cmd =
1193 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1194 enum i40e_status_code status;
1197 return I40E_ERR_PARAM;
1199 i40e_fill_default_direct_cmd_desc(&desc,
1200 i40e_aqc_opc_set_phy_config);
1204 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1211 * @hw: pointer to the hw struct
1213 * Set the requested flow control mode using set_phy_config.
1215 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1216 bool atomic_restart)
1218 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1219 struct i40e_aq_get_phy_abilities_resp abilities;
1220 struct i40e_aq_set_phy_config config;
1221 enum i40e_status_code status;
1222 u8 pause_mask = 0x0;
1228 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1229 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1231 case I40E_FC_RX_PAUSE:
1232 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1234 case I40E_FC_TX_PAUSE:
1235 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1241 /* Get the current phy config */
1242 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1245 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1249 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1250 /* clear the old pause settings */
1251 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1252 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1253 /* set the new abilities */
1254 config.abilities |= pause_mask;
1255 /* If the abilities have changed, then set the new config */
1256 if (config.abilities != abilities.abilities) {
1257 /* Auto restart link so settings take effect */
1259 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1260 /* Copy over all the old settings */
1261 config.phy_type = abilities.phy_type;
1262 config.link_speed = abilities.link_speed;
1263 config.eee_capability = abilities.eee_capability;
1264 config.eeer = abilities.eeer_val;
1265 config.low_power_ctrl = abilities.d3_lpan;
1266 status = i40e_aq_set_phy_config(hw, &config, NULL);
1269 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1271 /* Update the link info */
1272 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1274 /* Wait a little bit (on 40G cards it sometimes takes a really
1275 * long time for link to come back from the atomic reset)
1278 i40e_msec_delay(1000);
1279 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1282 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1288 * i40e_aq_set_mac_config
1289 * @hw: pointer to the hw struct
1290 * @max_frame_size: Maximum Frame Size to be supported by the port
1291 * @crc_en: Tell HW to append a CRC to outgoing frames
1292 * @pacing: Pacing configurations
1293 * @cmd_details: pointer to command details structure or NULL
1295 * Configure MAC settings for frame size, jumbo frame support and the
1296 * addition of a CRC by the hardware.
1298 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1300 bool crc_en, u16 pacing,
1301 struct i40e_asq_cmd_details *cmd_details)
1303 struct i40e_aq_desc desc;
1304 struct i40e_aq_set_mac_config *cmd =
1305 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1306 enum i40e_status_code status;
1308 if (max_frame_size == 0)
1309 return I40E_ERR_PARAM;
1311 i40e_fill_default_direct_cmd_desc(&desc,
1312 i40e_aqc_opc_set_mac_config);
1314 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1315 cmd->params = ((u8)pacing & 0x0F) << 3;
1317 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1319 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1325 * i40e_aq_clear_pxe_mode
1326 * @hw: pointer to the hw struct
1327 * @cmd_details: pointer to command details structure or NULL
1329 * Tell the firmware that the driver is taking over from PXE
1331 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1332 struct i40e_asq_cmd_details *cmd_details)
1334 enum i40e_status_code status;
1335 struct i40e_aq_desc desc;
1336 struct i40e_aqc_clear_pxe *cmd =
1337 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1339 i40e_fill_default_direct_cmd_desc(&desc,
1340 i40e_aqc_opc_clear_pxe_mode);
1344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1346 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1352 * i40e_aq_set_link_restart_an
1353 * @hw: pointer to the hw struct
1354 * @enable_link: if true: enable link, if false: disable link
1355 * @cmd_details: pointer to command details structure or NULL
1357 * Sets up the link and restarts the Auto-Negotiation over the link.
1359 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1360 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1362 struct i40e_aq_desc desc;
1363 struct i40e_aqc_set_link_restart_an *cmd =
1364 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1365 enum i40e_status_code status;
1367 i40e_fill_default_direct_cmd_desc(&desc,
1368 i40e_aqc_opc_set_link_restart_an);
1370 cmd->command = I40E_AQ_PHY_RESTART_AN;
1372 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1374 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1376 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1382 * i40e_aq_get_link_info
1383 * @hw: pointer to the hw struct
1384 * @enable_lse: enable/disable LinkStatusEvent reporting
1385 * @link: pointer to link status structure - optional
1386 * @cmd_details: pointer to command details structure or NULL
1388 * Returns the link status of the adapter.
1390 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1391 bool enable_lse, struct i40e_link_status *link,
1392 struct i40e_asq_cmd_details *cmd_details)
1394 struct i40e_aq_desc desc;
1395 struct i40e_aqc_get_link_status *resp =
1396 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1397 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1398 enum i40e_status_code status;
1399 bool tx_pause, rx_pause;
1402 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1405 command_flags = I40E_AQ_LSE_ENABLE;
1407 command_flags = I40E_AQ_LSE_DISABLE;
1408 resp->command_flags = CPU_TO_LE16(command_flags);
1410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1412 if (status != I40E_SUCCESS)
1413 goto aq_get_link_info_exit;
1415 /* save off old link status information */
1416 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1417 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1419 /* update link status */
1420 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1421 hw->phy.media_type = i40e_get_media_type(hw);
1422 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1423 hw_link_info->link_info = resp->link_info;
1424 hw_link_info->an_info = resp->an_info;
1425 hw_link_info->ext_info = resp->ext_info;
1426 hw_link_info->loopback = resp->loopback;
1427 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1428 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1430 /* update fc info */
1431 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1432 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1433 if (tx_pause & rx_pause)
1434 hw->fc.current_mode = I40E_FC_FULL;
1436 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1438 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1440 hw->fc.current_mode = I40E_FC_NONE;
1442 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1443 hw_link_info->crc_enable = true;
1445 hw_link_info->crc_enable = false;
1447 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1448 hw_link_info->lse_enable = true;
1450 hw_link_info->lse_enable = false;
1452 /* save link status information */
1454 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1455 I40E_NONDMA_TO_NONDMA);
1457 /* flag cleared so helper functions don't call AQ again */
1458 hw->phy.get_link_info = false;
1460 aq_get_link_info_exit:
1465 * i40e_aq_set_phy_int_mask
1466 * @hw: pointer to the hw struct
1467 * @mask: interrupt mask to be set
1468 * @cmd_details: pointer to command details structure or NULL
1470 * Set link interrupt mask.
1472 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1474 struct i40e_asq_cmd_details *cmd_details)
1476 struct i40e_aq_desc desc;
1477 struct i40e_aqc_set_phy_int_mask *cmd =
1478 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1479 enum i40e_status_code status;
1481 i40e_fill_default_direct_cmd_desc(&desc,
1482 i40e_aqc_opc_set_phy_int_mask);
1484 cmd->event_mask = CPU_TO_LE16(mask);
1486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1492 * i40e_aq_get_local_advt_reg
1493 * @hw: pointer to the hw struct
1494 * @advt_reg: local AN advertisement register value
1495 * @cmd_details: pointer to command details structure or NULL
1497 * Get the Local AN advertisement register value.
1499 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1501 struct i40e_asq_cmd_details *cmd_details)
1503 struct i40e_aq_desc desc;
1504 struct i40e_aqc_an_advt_reg *resp =
1505 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1506 enum i40e_status_code status;
1508 i40e_fill_default_direct_cmd_desc(&desc,
1509 i40e_aqc_opc_get_local_advt_reg);
1511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1513 if (status != I40E_SUCCESS)
1514 goto aq_get_local_advt_reg_exit;
1516 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1517 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1519 aq_get_local_advt_reg_exit:
1524 * i40e_aq_set_local_advt_reg
1525 * @hw: pointer to the hw struct
1526 * @advt_reg: local AN advertisement register value
1527 * @cmd_details: pointer to command details structure or NULL
1529 * Get the Local AN advertisement register value.
1531 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1533 struct i40e_asq_cmd_details *cmd_details)
1535 struct i40e_aq_desc desc;
1536 struct i40e_aqc_an_advt_reg *cmd =
1537 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1538 enum i40e_status_code status;
1540 i40e_fill_default_direct_cmd_desc(&desc,
1541 i40e_aqc_opc_get_local_advt_reg);
1543 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1544 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1546 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1552 * i40e_aq_get_partner_advt
1553 * @hw: pointer to the hw struct
1554 * @advt_reg: AN partner advertisement register value
1555 * @cmd_details: pointer to command details structure or NULL
1557 * Get the link partner AN advertisement register value.
1559 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1561 struct i40e_asq_cmd_details *cmd_details)
1563 struct i40e_aq_desc desc;
1564 struct i40e_aqc_an_advt_reg *resp =
1565 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1566 enum i40e_status_code status;
1568 i40e_fill_default_direct_cmd_desc(&desc,
1569 i40e_aqc_opc_get_partner_advt);
1571 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1573 if (status != I40E_SUCCESS)
1574 goto aq_get_partner_advt_exit;
1576 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1577 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1579 aq_get_partner_advt_exit:
1584 * i40e_aq_set_lb_modes
1585 * @hw: pointer to the hw struct
1586 * @lb_modes: loopback mode to be set
1587 * @cmd_details: pointer to command details structure or NULL
1589 * Sets loopback modes.
1591 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1593 struct i40e_asq_cmd_details *cmd_details)
1595 struct i40e_aq_desc desc;
1596 struct i40e_aqc_set_lb_mode *cmd =
1597 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1598 enum i40e_status_code status;
1600 i40e_fill_default_direct_cmd_desc(&desc,
1601 i40e_aqc_opc_set_lb_modes);
1603 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1611 * i40e_aq_set_phy_debug
1612 * @hw: pointer to the hw struct
1613 * @cmd_flags: debug command flags
1614 * @cmd_details: pointer to command details structure or NULL
1616 * Reset the external PHY.
1618 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1619 struct i40e_asq_cmd_details *cmd_details)
1621 struct i40e_aq_desc desc;
1622 struct i40e_aqc_set_phy_debug *cmd =
1623 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1624 enum i40e_status_code status;
1626 i40e_fill_default_direct_cmd_desc(&desc,
1627 i40e_aqc_opc_set_phy_debug);
1629 cmd->command_flags = cmd_flags;
1631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1638 * @hw: pointer to the hw struct
1639 * @vsi_ctx: pointer to a vsi context struct
1640 * @cmd_details: pointer to command details structure or NULL
1642 * Add a VSI context to the hardware.
1644 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1645 struct i40e_vsi_context *vsi_ctx,
1646 struct i40e_asq_cmd_details *cmd_details)
1648 struct i40e_aq_desc desc;
1649 struct i40e_aqc_add_get_update_vsi *cmd =
1650 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1651 struct i40e_aqc_add_get_update_vsi_completion *resp =
1652 (struct i40e_aqc_add_get_update_vsi_completion *)
1654 enum i40e_status_code status;
1656 i40e_fill_default_direct_cmd_desc(&desc,
1657 i40e_aqc_opc_add_vsi);
1659 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1660 cmd->connection_type = vsi_ctx->connection_type;
1661 cmd->vf_id = vsi_ctx->vf_num;
1662 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1664 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1666 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1667 sizeof(vsi_ctx->info), cmd_details);
1669 if (status != I40E_SUCCESS)
1670 goto aq_add_vsi_exit;
1672 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1673 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1674 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1675 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1682 * i40e_aq_set_default_vsi
1683 * @hw: pointer to the hw struct
1685 * @cmd_details: pointer to command details structure or NULL
1687 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1689 struct i40e_asq_cmd_details *cmd_details)
1691 struct i40e_aq_desc desc;
1692 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1693 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1695 enum i40e_status_code status;
1697 i40e_fill_default_direct_cmd_desc(&desc,
1698 i40e_aqc_opc_set_vsi_promiscuous_modes);
1700 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1701 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1702 cmd->seid = CPU_TO_LE16(seid);
1704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1710 * i40e_aq_set_vsi_unicast_promiscuous
1711 * @hw: pointer to the hw struct
1713 * @set: set unicast promiscuous enable/disable
1714 * @cmd_details: pointer to command details structure or NULL
1716 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1718 struct i40e_asq_cmd_details *cmd_details)
1720 struct i40e_aq_desc desc;
1721 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1722 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1723 enum i40e_status_code status;
1726 i40e_fill_default_direct_cmd_desc(&desc,
1727 i40e_aqc_opc_set_vsi_promiscuous_modes);
1730 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1732 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1734 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1736 cmd->seid = CPU_TO_LE16(seid);
1737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1743 * i40e_aq_set_vsi_multicast_promiscuous
1744 * @hw: pointer to the hw struct
1746 * @set: set multicast promiscuous enable/disable
1747 * @cmd_details: pointer to command details structure or NULL
1749 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1750 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1752 struct i40e_aq_desc desc;
1753 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1754 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1755 enum i40e_status_code status;
1758 i40e_fill_default_direct_cmd_desc(&desc,
1759 i40e_aqc_opc_set_vsi_promiscuous_modes);
1762 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1764 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1766 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1768 cmd->seid = CPU_TO_LE16(seid);
1769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1775 * i40e_aq_set_vsi_broadcast
1776 * @hw: pointer to the hw struct
1778 * @set_filter: true to set filter, false to clear filter
1779 * @cmd_details: pointer to command details structure or NULL
1781 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1783 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1784 u16 seid, bool set_filter,
1785 struct i40e_asq_cmd_details *cmd_details)
1787 struct i40e_aq_desc desc;
1788 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1789 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1790 enum i40e_status_code status;
1792 i40e_fill_default_direct_cmd_desc(&desc,
1793 i40e_aqc_opc_set_vsi_promiscuous_modes);
1796 cmd->promiscuous_flags
1797 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1799 cmd->promiscuous_flags
1800 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1802 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1803 cmd->seid = CPU_TO_LE16(seid);
1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1810 * i40e_get_vsi_params - get VSI configuration info
1811 * @hw: pointer to the hw struct
1812 * @vsi_ctx: pointer to a vsi context struct
1813 * @cmd_details: pointer to command details structure or NULL
1815 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1816 struct i40e_vsi_context *vsi_ctx,
1817 struct i40e_asq_cmd_details *cmd_details)
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_add_get_update_vsi *cmd =
1821 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1822 struct i40e_aqc_add_get_update_vsi_completion *resp =
1823 (struct i40e_aqc_add_get_update_vsi_completion *)
1825 enum i40e_status_code status;
1827 UNREFERENCED_1PARAMETER(cmd_details);
1828 i40e_fill_default_direct_cmd_desc(&desc,
1829 i40e_aqc_opc_get_vsi_parameters);
1831 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1833 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1835 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1836 sizeof(vsi_ctx->info), NULL);
1838 if (status != I40E_SUCCESS)
1839 goto aq_get_vsi_params_exit;
1841 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1842 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1843 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1844 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1846 aq_get_vsi_params_exit:
1851 * i40e_aq_update_vsi_params
1852 * @hw: pointer to the hw struct
1853 * @vsi_ctx: pointer to a vsi context struct
1854 * @cmd_details: pointer to command details structure or NULL
1856 * Update a VSI context.
1858 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1859 struct i40e_vsi_context *vsi_ctx,
1860 struct i40e_asq_cmd_details *cmd_details)
1862 struct i40e_aq_desc desc;
1863 struct i40e_aqc_add_get_update_vsi *cmd =
1864 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1865 enum i40e_status_code status;
1867 i40e_fill_default_direct_cmd_desc(&desc,
1868 i40e_aqc_opc_update_vsi_parameters);
1869 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1871 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1873 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1874 sizeof(vsi_ctx->info), cmd_details);
1880 * i40e_aq_get_switch_config
1881 * @hw: pointer to the hardware structure
1882 * @buf: pointer to the result buffer
1883 * @buf_size: length of input buffer
1884 * @start_seid: seid to start for the report, 0 == beginning
1885 * @cmd_details: pointer to command details structure or NULL
1887 * Fill the buf with switch configuration returned from AdminQ command
1889 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1890 struct i40e_aqc_get_switch_config_resp *buf,
1891 u16 buf_size, u16 *start_seid,
1892 struct i40e_asq_cmd_details *cmd_details)
1894 struct i40e_aq_desc desc;
1895 struct i40e_aqc_switch_seid *scfg =
1896 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1897 enum i40e_status_code status;
1899 i40e_fill_default_direct_cmd_desc(&desc,
1900 i40e_aqc_opc_get_switch_config);
1901 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1902 if (buf_size > I40E_AQ_LARGE_BUF)
1903 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1904 scfg->seid = CPU_TO_LE16(*start_seid);
1906 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1907 *start_seid = LE16_TO_CPU(scfg->seid);
1913 * i40e_aq_get_firmware_version
1914 * @hw: pointer to the hw struct
1915 * @fw_major_version: firmware major version
1916 * @fw_minor_version: firmware minor version
1917 * @fw_build: firmware build number
1918 * @api_major_version: major queue version
1919 * @api_minor_version: minor queue version
1920 * @cmd_details: pointer to command details structure or NULL
1922 * Get the firmware version from the admin queue commands
1924 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1925 u16 *fw_major_version, u16 *fw_minor_version,
1927 u16 *api_major_version, u16 *api_minor_version,
1928 struct i40e_asq_cmd_details *cmd_details)
1930 struct i40e_aq_desc desc;
1931 struct i40e_aqc_get_version *resp =
1932 (struct i40e_aqc_get_version *)&desc.params.raw;
1933 enum i40e_status_code status;
1935 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1937 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1939 if (status == I40E_SUCCESS) {
1940 if (fw_major_version != NULL)
1941 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1942 if (fw_minor_version != NULL)
1943 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1944 if (fw_build != NULL)
1945 *fw_build = LE32_TO_CPU(resp->fw_build);
1946 if (api_major_version != NULL)
1947 *api_major_version = LE16_TO_CPU(resp->api_major);
1948 if (api_minor_version != NULL)
1949 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1951 /* A workaround to fix the API version in SW */
1952 if (api_major_version && api_minor_version &&
1953 fw_major_version && fw_minor_version &&
1954 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1955 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1956 (*fw_major_version > 4)))
1957 *api_minor_version = 2;
1964 * i40e_aq_send_driver_version
1965 * @hw: pointer to the hw struct
1966 * @dv: driver's major, minor version
1967 * @cmd_details: pointer to command details structure or NULL
1969 * Send the driver version to the firmware
1971 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1972 struct i40e_driver_version *dv,
1973 struct i40e_asq_cmd_details *cmd_details)
1975 struct i40e_aq_desc desc;
1976 struct i40e_aqc_driver_version *cmd =
1977 (struct i40e_aqc_driver_version *)&desc.params.raw;
1978 enum i40e_status_code status;
1982 return I40E_ERR_PARAM;
1984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1986 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1987 cmd->driver_major_ver = dv->major_version;
1988 cmd->driver_minor_ver = dv->minor_version;
1989 cmd->driver_build_ver = dv->build_version;
1990 cmd->driver_subbuild_ver = dv->subbuild_version;
1993 while (len < sizeof(dv->driver_string) &&
1994 (dv->driver_string[len] < 0x80) &&
1995 dv->driver_string[len])
1997 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2004 * i40e_get_link_status - get status of the HW network link
2005 * @hw: pointer to the hw struct
2007 * Returns true if link is up, false if link is down.
2009 * Side effect: LinkStatusEvent reporting becomes enabled
2011 bool i40e_get_link_status(struct i40e_hw *hw)
2013 enum i40e_status_code status = I40E_SUCCESS;
2014 bool link_status = false;
2016 if (hw->phy.get_link_info) {
2017 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2019 if (status != I40E_SUCCESS)
2020 goto i40e_get_link_status_exit;
2023 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2025 i40e_get_link_status_exit:
2030 * i40e_get_link_speed
2031 * @hw: pointer to the hw struct
2033 * Returns the link speed of the adapter.
2035 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2037 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2038 enum i40e_status_code status = I40E_SUCCESS;
2040 if (hw->phy.get_link_info) {
2041 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2043 if (status != I40E_SUCCESS)
2044 goto i40e_link_speed_exit;
2047 speed = hw->phy.link_info.link_speed;
2049 i40e_link_speed_exit:
2054 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2055 * @hw: pointer to the hw struct
2056 * @uplink_seid: the MAC or other gizmo SEID
2057 * @downlink_seid: the VSI SEID
2058 * @enabled_tc: bitmap of TCs to be enabled
2059 * @default_port: true for default port VSI, false for control port
2060 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2061 * @veb_seid: pointer to where to put the resulting VEB SEID
2062 * @cmd_details: pointer to command details structure or NULL
2064 * This asks the FW to add a VEB between the uplink and downlink
2065 * elements. If the uplink SEID is 0, this will be a floating VEB.
2067 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2068 u16 downlink_seid, u8 enabled_tc,
2069 bool default_port, bool enable_l2_filtering,
2071 struct i40e_asq_cmd_details *cmd_details)
2073 struct i40e_aq_desc desc;
2074 struct i40e_aqc_add_veb *cmd =
2075 (struct i40e_aqc_add_veb *)&desc.params.raw;
2076 struct i40e_aqc_add_veb_completion *resp =
2077 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2078 enum i40e_status_code status;
2081 /* SEIDs need to either both be set or both be 0 for floating VEB */
2082 if (!!uplink_seid != !!downlink_seid)
2083 return I40E_ERR_PARAM;
2085 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2087 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2088 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2089 cmd->enable_tcs = enabled_tc;
2091 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2093 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2095 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2097 if (enable_l2_filtering)
2098 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2100 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2102 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2104 if (!status && veb_seid)
2105 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2111 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2112 * @hw: pointer to the hw struct
2113 * @veb_seid: the SEID of the VEB to query
2114 * @switch_id: the uplink switch id
2115 * @floating: set to true if the VEB is floating
2116 * @statistic_index: index of the stats counter block for this VEB
2117 * @vebs_used: number of VEB's used by function
2118 * @vebs_free: total VEB's not reserved by any function
2119 * @cmd_details: pointer to command details structure or NULL
2121 * This retrieves the parameters for a particular VEB, specified by
2122 * uplink_seid, and returns them to the caller.
2124 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2125 u16 veb_seid, u16 *switch_id,
2126 bool *floating, u16 *statistic_index,
2127 u16 *vebs_used, u16 *vebs_free,
2128 struct i40e_asq_cmd_details *cmd_details)
2130 struct i40e_aq_desc desc;
2131 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2132 (struct i40e_aqc_get_veb_parameters_completion *)
2134 enum i40e_status_code status;
2137 return I40E_ERR_PARAM;
2139 i40e_fill_default_direct_cmd_desc(&desc,
2140 i40e_aqc_opc_get_veb_parameters);
2141 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2148 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2149 if (statistic_index)
2150 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2152 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2154 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2156 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2157 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2168 * i40e_aq_add_macvlan
2169 * @hw: pointer to the hw struct
2170 * @seid: VSI for the mac address
2171 * @mv_list: list of macvlans to be added
2172 * @count: length of the list
2173 * @cmd_details: pointer to command details structure or NULL
2175 * Add MAC/VLAN addresses to the HW filtering
2177 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2178 struct i40e_aqc_add_macvlan_element_data *mv_list,
2179 u16 count, struct i40e_asq_cmd_details *cmd_details)
2181 struct i40e_aq_desc desc;
2182 struct i40e_aqc_macvlan *cmd =
2183 (struct i40e_aqc_macvlan *)&desc.params.raw;
2184 enum i40e_status_code status;
2187 if (count == 0 || !mv_list || !hw)
2188 return I40E_ERR_PARAM;
2190 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2192 /* prep the rest of the request */
2193 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2194 cmd->num_addresses = CPU_TO_LE16(count);
2195 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2199 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2200 if (buf_size > I40E_AQ_LARGE_BUF)
2201 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2203 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2210 * i40e_aq_remove_macvlan
2211 * @hw: pointer to the hw struct
2212 * @seid: VSI for the mac address
2213 * @mv_list: list of macvlans to be removed
2214 * @count: length of the list
2215 * @cmd_details: pointer to command details structure or NULL
2217 * Remove MAC/VLAN addresses from the HW filtering
2219 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2220 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2221 u16 count, struct i40e_asq_cmd_details *cmd_details)
2223 struct i40e_aq_desc desc;
2224 struct i40e_aqc_macvlan *cmd =
2225 (struct i40e_aqc_macvlan *)&desc.params.raw;
2226 enum i40e_status_code status;
2229 if (count == 0 || !mv_list || !hw)
2230 return I40E_ERR_PARAM;
2232 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2234 /* prep the rest of the request */
2235 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2236 cmd->num_addresses = CPU_TO_LE16(count);
2237 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2241 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2242 if (buf_size > I40E_AQ_LARGE_BUF)
2243 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2245 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2252 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2253 * @hw: pointer to the hw struct
2254 * @seid: VSI for the vlan filters
2255 * @v_list: list of vlan filters to be added
2256 * @count: length of the list
2257 * @cmd_details: pointer to command details structure or NULL
2259 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2260 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2261 u8 count, struct i40e_asq_cmd_details *cmd_details)
2263 struct i40e_aq_desc desc;
2264 struct i40e_aqc_macvlan *cmd =
2265 (struct i40e_aqc_macvlan *)&desc.params.raw;
2266 enum i40e_status_code status;
2269 if (count == 0 || !v_list || !hw)
2270 return I40E_ERR_PARAM;
2272 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2274 /* prep the rest of the request */
2275 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2276 cmd->num_addresses = CPU_TO_LE16(count);
2277 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2281 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2282 if (buf_size > I40E_AQ_LARGE_BUF)
2283 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2285 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2292 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2293 * @hw: pointer to the hw struct
2294 * @seid: VSI for the vlan filters
2295 * @v_list: list of macvlans to be removed
2296 * @count: length of the list
2297 * @cmd_details: pointer to command details structure or NULL
2299 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2300 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2301 u8 count, struct i40e_asq_cmd_details *cmd_details)
2303 struct i40e_aq_desc desc;
2304 struct i40e_aqc_macvlan *cmd =
2305 (struct i40e_aqc_macvlan *)&desc.params.raw;
2306 enum i40e_status_code status;
2309 if (count == 0 || !v_list || !hw)
2310 return I40E_ERR_PARAM;
2312 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2314 /* prep the rest of the request */
2315 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2316 cmd->num_addresses = CPU_TO_LE16(count);
2317 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2321 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2322 if (buf_size > I40E_AQ_LARGE_BUF)
2323 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2325 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2332 * i40e_aq_send_msg_to_vf
2333 * @hw: pointer to the hardware structure
2334 * @vfid: vf id to send msg
2335 * @v_opcode: opcodes for VF-PF communication
2336 * @v_retval: return error code
2337 * @msg: pointer to the msg buffer
2338 * @msglen: msg length
2339 * @cmd_details: pointer to command details
2343 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2344 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2345 struct i40e_asq_cmd_details *cmd_details)
2347 struct i40e_aq_desc desc;
2348 struct i40e_aqc_pf_vf_message *cmd =
2349 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2350 enum i40e_status_code status;
2352 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2353 cmd->id = CPU_TO_LE32(vfid);
2354 desc.cookie_high = CPU_TO_LE32(v_opcode);
2355 desc.cookie_low = CPU_TO_LE32(v_retval);
2356 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2358 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2360 if (msglen > I40E_AQ_LARGE_BUF)
2361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2362 desc.datalen = CPU_TO_LE16(msglen);
2364 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2370 * i40e_aq_debug_read_register
2371 * @hw: pointer to the hw struct
2372 * @reg_addr: register address
2373 * @reg_val: register value
2374 * @cmd_details: pointer to command details structure or NULL
2376 * Read the register using the admin queue commands
2378 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2379 u32 reg_addr, u64 *reg_val,
2380 struct i40e_asq_cmd_details *cmd_details)
2382 struct i40e_aq_desc desc;
2383 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2384 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2385 enum i40e_status_code status;
2387 if (reg_val == NULL)
2388 return I40E_ERR_PARAM;
2390 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2392 cmd_resp->address = CPU_TO_LE32(reg_addr);
2394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2396 if (status == I40E_SUCCESS) {
2397 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2398 (u64)LE32_TO_CPU(cmd_resp->value_low);
2405 * i40e_aq_debug_write_register
2406 * @hw: pointer to the hw struct
2407 * @reg_addr: register address
2408 * @reg_val: register value
2409 * @cmd_details: pointer to command details structure or NULL
2411 * Write to a register using the admin queue commands
2413 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2414 u32 reg_addr, u64 reg_val,
2415 struct i40e_asq_cmd_details *cmd_details)
2417 struct i40e_aq_desc desc;
2418 struct i40e_aqc_debug_reg_read_write *cmd =
2419 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2420 enum i40e_status_code status;
2422 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2424 cmd->address = CPU_TO_LE32(reg_addr);
2425 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2426 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2434 * i40e_aq_get_hmc_resource_profile
2435 * @hw: pointer to the hw struct
2436 * @profile: type of profile the HMC is to be set as
2437 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2438 * @cmd_details: pointer to command details structure or NULL
2440 * query the HMC profile of the device.
2442 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2443 enum i40e_aq_hmc_profile *profile,
2444 u8 *pe_vf_enabled_count,
2445 struct i40e_asq_cmd_details *cmd_details)
2447 struct i40e_aq_desc desc;
2448 struct i40e_aq_get_set_hmc_resource_profile *resp =
2449 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2450 enum i40e_status_code status;
2452 i40e_fill_default_direct_cmd_desc(&desc,
2453 i40e_aqc_opc_query_hmc_resource_profile);
2454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2457 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2458 *pe_vf_enabled_count = resp->pe_vf_enabled &
2459 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2465 * i40e_aq_set_hmc_resource_profile
2466 * @hw: pointer to the hw struct
2467 * @profile: type of profile the HMC is to be set as
2468 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2469 * @cmd_details: pointer to command details structure or NULL
2471 * set the HMC profile of the device.
2473 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2474 enum i40e_aq_hmc_profile profile,
2475 u8 pe_vf_enabled_count,
2476 struct i40e_asq_cmd_details *cmd_details)
2478 struct i40e_aq_desc desc;
2479 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2480 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2481 enum i40e_status_code status;
2483 i40e_fill_default_direct_cmd_desc(&desc,
2484 i40e_aqc_opc_set_hmc_resource_profile);
2486 cmd->pm_profile = (u8)profile;
2487 cmd->pe_vf_enabled = pe_vf_enabled_count;
2489 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2495 * i40e_aq_request_resource
2496 * @hw: pointer to the hw struct
2497 * @resource: resource id
2498 * @access: access type
2499 * @sdp_number: resource number
2500 * @timeout: the maximum time in ms that the driver may hold the resource
2501 * @cmd_details: pointer to command details structure or NULL
2503 * requests common resource using the admin queue commands
2505 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2506 enum i40e_aq_resources_ids resource,
2507 enum i40e_aq_resource_access_type access,
2508 u8 sdp_number, u64 *timeout,
2509 struct i40e_asq_cmd_details *cmd_details)
2511 struct i40e_aq_desc desc;
2512 struct i40e_aqc_request_resource *cmd_resp =
2513 (struct i40e_aqc_request_resource *)&desc.params.raw;
2514 enum i40e_status_code status;
2516 DEBUGFUNC("i40e_aq_request_resource");
2518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2520 cmd_resp->resource_id = CPU_TO_LE16(resource);
2521 cmd_resp->access_type = CPU_TO_LE16(access);
2522 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2524 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2525 /* The completion specifies the maximum time in ms that the driver
2526 * may hold the resource in the Timeout field.
2527 * If the resource is held by someone else, the command completes with
2528 * busy return value and the timeout field indicates the maximum time
2529 * the current owner of the resource has to free it.
2531 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2532 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2538 * i40e_aq_release_resource
2539 * @hw: pointer to the hw struct
2540 * @resource: resource id
2541 * @sdp_number: resource number
2542 * @cmd_details: pointer to command details structure or NULL
2544 * release common resource using the admin queue commands
2546 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2547 enum i40e_aq_resources_ids resource,
2549 struct i40e_asq_cmd_details *cmd_details)
2551 struct i40e_aq_desc desc;
2552 struct i40e_aqc_request_resource *cmd =
2553 (struct i40e_aqc_request_resource *)&desc.params.raw;
2554 enum i40e_status_code status;
2556 DEBUGFUNC("i40e_aq_release_resource");
2558 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2560 cmd->resource_id = CPU_TO_LE16(resource);
2561 cmd->resource_number = CPU_TO_LE32(sdp_number);
2563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2570 * @hw: pointer to the hw struct
2571 * @module_pointer: module pointer location in words from the NVM beginning
2572 * @offset: byte offset from the module beginning
2573 * @length: length of the section to be read (in bytes from the offset)
2574 * @data: command buffer (size [bytes] = length)
2575 * @last_command: tells if this is the last command in a series
2576 * @cmd_details: pointer to command details structure or NULL
2578 * Read the NVM using the admin queue commands
2580 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2581 u32 offset, u16 length, void *data,
2583 struct i40e_asq_cmd_details *cmd_details)
2585 struct i40e_aq_desc desc;
2586 struct i40e_aqc_nvm_update *cmd =
2587 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2588 enum i40e_status_code status;
2590 DEBUGFUNC("i40e_aq_read_nvm");
2592 /* In offset the highest byte must be zeroed. */
2593 if (offset & 0xFF000000) {
2594 status = I40E_ERR_PARAM;
2595 goto i40e_aq_read_nvm_exit;
2598 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2600 /* If this is the last command in a series, set the proper flag. */
2602 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2603 cmd->module_pointer = module_pointer;
2604 cmd->offset = CPU_TO_LE32(offset);
2605 cmd->length = CPU_TO_LE16(length);
2607 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2608 if (length > I40E_AQ_LARGE_BUF)
2609 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2611 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2613 i40e_aq_read_nvm_exit:
2619 * @hw: pointer to the hw struct
2620 * @module_pointer: module pointer location in words from the NVM beginning
2621 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2622 * @length: length of the section to be erased (expressed in 4 KB)
2623 * @last_command: tells if this is the last command in a series
2624 * @cmd_details: pointer to command details structure or NULL
2626 * Erase the NVM sector using the admin queue commands
2628 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2629 u32 offset, u16 length, bool last_command,
2630 struct i40e_asq_cmd_details *cmd_details)
2632 struct i40e_aq_desc desc;
2633 struct i40e_aqc_nvm_update *cmd =
2634 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2635 enum i40e_status_code status;
2637 DEBUGFUNC("i40e_aq_erase_nvm");
2639 /* In offset the highest byte must be zeroed. */
2640 if (offset & 0xFF000000) {
2641 status = I40E_ERR_PARAM;
2642 goto i40e_aq_erase_nvm_exit;
2645 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2647 /* If this is the last command in a series, set the proper flag. */
2649 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2650 cmd->module_pointer = module_pointer;
2651 cmd->offset = CPU_TO_LE32(offset);
2652 cmd->length = CPU_TO_LE16(length);
2654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2656 i40e_aq_erase_nvm_exit:
2660 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2661 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2662 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2663 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2664 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2665 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2666 #define I40E_DEV_FUNC_CAP_VF 0x13
2667 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2668 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2669 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2670 #define I40E_DEV_FUNC_CAP_VSI 0x17
2671 #define I40E_DEV_FUNC_CAP_DCB 0x18
2672 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2673 #define I40E_DEV_FUNC_CAP_RSS 0x40
2674 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2675 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2676 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2677 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2678 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2679 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2680 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2681 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2682 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2683 #define I40E_DEV_FUNC_CAP_LED 0x61
2684 #define I40E_DEV_FUNC_CAP_SDP 0x62
2685 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2688 * i40e_parse_discover_capabilities
2689 * @hw: pointer to the hw struct
2690 * @buff: pointer to a buffer containing device/function capability records
2691 * @cap_count: number of capability records in the list
2692 * @list_type_opc: type of capabilities list to parse
2694 * Parse the device/function capabilities list.
2696 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2698 enum i40e_admin_queue_opc list_type_opc)
2700 struct i40e_aqc_list_capabilities_element_resp *cap;
2701 u32 number, logical_id, phys_id;
2702 struct i40e_hw_capabilities *p;
2706 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2708 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2709 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2710 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2711 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2715 for (i = 0; i < cap_count; i++, cap++) {
2716 id = LE16_TO_CPU(cap->id);
2717 number = LE32_TO_CPU(cap->number);
2718 logical_id = LE32_TO_CPU(cap->logical_id);
2719 phys_id = LE32_TO_CPU(cap->phys_id);
2722 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2723 p->switch_mode = number;
2725 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2726 p->management_mode = number;
2728 case I40E_DEV_FUNC_CAP_NPAR:
2729 p->npar_enable = number;
2731 case I40E_DEV_FUNC_CAP_OS2BMC:
2734 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2735 p->valid_functions = number;
2737 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2739 p->sr_iov_1_1 = true;
2741 case I40E_DEV_FUNC_CAP_VF:
2742 p->num_vfs = number;
2743 p->vf_base_id = logical_id;
2745 case I40E_DEV_FUNC_CAP_VMDQ:
2749 case I40E_DEV_FUNC_CAP_802_1_QBG:
2751 p->evb_802_1_qbg = true;
2753 case I40E_DEV_FUNC_CAP_802_1_QBH:
2755 p->evb_802_1_qbh = true;
2757 case I40E_DEV_FUNC_CAP_VSI:
2758 p->num_vsis = number;
2760 case I40E_DEV_FUNC_CAP_DCB:
2763 p->enabled_tcmap = logical_id;
2767 case I40E_DEV_FUNC_CAP_FCOE:
2771 case I40E_DEV_FUNC_CAP_RSS:
2773 p->rss_table_size = number;
2774 p->rss_table_entry_width = logical_id;
2776 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2777 p->num_rx_qp = number;
2778 p->base_queue = phys_id;
2780 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2781 p->num_tx_qp = number;
2782 p->base_queue = phys_id;
2784 case I40E_DEV_FUNC_CAP_MSIX:
2785 p->num_msix_vectors = number;
2787 case I40E_DEV_FUNC_CAP_MSIX_VF:
2788 p->num_msix_vectors_vf = number;
2790 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2792 p->mfp_mode_1 = true;
2794 case I40E_DEV_FUNC_CAP_CEM:
2798 case I40E_DEV_FUNC_CAP_IWARP:
2802 case I40E_DEV_FUNC_CAP_LED:
2803 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2804 p->led[phys_id] = true;
2806 case I40E_DEV_FUNC_CAP_SDP:
2807 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2808 p->sdp[phys_id] = true;
2810 case I40E_DEV_FUNC_CAP_MDIO:
2812 p->mdio_port_num = phys_id;
2813 p->mdio_port_mode = logical_id;
2816 case I40E_DEV_FUNC_CAP_IEEE_1588:
2818 p->ieee_1588 = true;
2820 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2822 p->fd_filters_guaranteed = number;
2823 p->fd_filters_best_effort = logical_id;
2830 /* Software override ensuring FCoE is disabled if npar or mfp
2831 * mode because it is not supported in these modes.
2833 if (p->npar_enable || p->mfp_mode_1)
2836 /* additional HW specific goodies that might
2837 * someday be HW version specific
2839 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2843 * i40e_aq_discover_capabilities
2844 * @hw: pointer to the hw struct
2845 * @buff: a virtual buffer to hold the capabilities
2846 * @buff_size: Size of the virtual buffer
2847 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2848 * @list_type_opc: capabilities type to discover - pass in the command opcode
2849 * @cmd_details: pointer to command details structure or NULL
2851 * Get the device capabilities descriptions from the firmware
2853 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2854 void *buff, u16 buff_size, u16 *data_size,
2855 enum i40e_admin_queue_opc list_type_opc,
2856 struct i40e_asq_cmd_details *cmd_details)
2858 struct i40e_aqc_list_capabilites *cmd;
2859 struct i40e_aq_desc desc;
2860 enum i40e_status_code status = I40E_SUCCESS;
2862 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2864 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2865 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2866 status = I40E_ERR_PARAM;
2870 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2872 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2873 if (buff_size > I40E_AQ_LARGE_BUF)
2874 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2876 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2877 *data_size = LE16_TO_CPU(desc.datalen);
2882 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2890 * i40e_aq_update_nvm
2891 * @hw: pointer to the hw struct
2892 * @module_pointer: module pointer location in words from the NVM beginning
2893 * @offset: byte offset from the module beginning
2894 * @length: length of the section to be written (in bytes from the offset)
2895 * @data: command buffer (size [bytes] = length)
2896 * @last_command: tells if this is the last command in a series
2897 * @cmd_details: pointer to command details structure or NULL
2899 * Update the NVM using the admin queue commands
2901 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2902 u32 offset, u16 length, void *data,
2904 struct i40e_asq_cmd_details *cmd_details)
2906 struct i40e_aq_desc desc;
2907 struct i40e_aqc_nvm_update *cmd =
2908 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2909 enum i40e_status_code status;
2911 DEBUGFUNC("i40e_aq_update_nvm");
2913 /* In offset the highest byte must be zeroed. */
2914 if (offset & 0xFF000000) {
2915 status = I40E_ERR_PARAM;
2916 goto i40e_aq_update_nvm_exit;
2919 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2921 /* If this is the last command in a series, set the proper flag. */
2923 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2924 cmd->module_pointer = module_pointer;
2925 cmd->offset = CPU_TO_LE32(offset);
2926 cmd->length = CPU_TO_LE16(length);
2928 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2929 if (length > I40E_AQ_LARGE_BUF)
2930 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2932 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2934 i40e_aq_update_nvm_exit:
2939 * i40e_aq_get_lldp_mib
2940 * @hw: pointer to the hw struct
2941 * @bridge_type: type of bridge requested
2942 * @mib_type: Local, Remote or both Local and Remote MIBs
2943 * @buff: pointer to a user supplied buffer to store the MIB block
2944 * @buff_size: size of the buffer (in bytes)
2945 * @local_len : length of the returned Local LLDP MIB
2946 * @remote_len: length of the returned Remote LLDP MIB
2947 * @cmd_details: pointer to command details structure or NULL
2949 * Requests the complete LLDP MIB (entire packet).
2951 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2952 u8 mib_type, void *buff, u16 buff_size,
2953 u16 *local_len, u16 *remote_len,
2954 struct i40e_asq_cmd_details *cmd_details)
2956 struct i40e_aq_desc desc;
2957 struct i40e_aqc_lldp_get_mib *cmd =
2958 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2959 struct i40e_aqc_lldp_get_mib *resp =
2960 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2961 enum i40e_status_code status;
2963 if (buff_size == 0 || !buff)
2964 return I40E_ERR_PARAM;
2966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2967 /* Indirect Command */
2968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2970 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2971 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2972 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2974 desc.datalen = CPU_TO_LE16(buff_size);
2976 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2977 if (buff_size > I40E_AQ_LARGE_BUF)
2978 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2980 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2982 if (local_len != NULL)
2983 *local_len = LE16_TO_CPU(resp->local_len);
2984 if (remote_len != NULL)
2985 *remote_len = LE16_TO_CPU(resp->remote_len);
2992 * i40e_aq_cfg_lldp_mib_change_event
2993 * @hw: pointer to the hw struct
2994 * @enable_update: Enable or Disable event posting
2995 * @cmd_details: pointer to command details structure or NULL
2997 * Enable or Disable posting of an event on ARQ when LLDP MIB
2998 * associated with the interface changes
3000 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3002 struct i40e_asq_cmd_details *cmd_details)
3004 struct i40e_aq_desc desc;
3005 struct i40e_aqc_lldp_update_mib *cmd =
3006 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3007 enum i40e_status_code status;
3009 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3012 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3020 * i40e_aq_add_lldp_tlv
3021 * @hw: pointer to the hw struct
3022 * @bridge_type: type of bridge
3023 * @buff: buffer with TLV to add
3024 * @buff_size: length of the buffer
3025 * @tlv_len: length of the TLV to be added
3026 * @mib_len: length of the LLDP MIB returned in response
3027 * @cmd_details: pointer to command details structure or NULL
3029 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3030 * it is responsibility of the caller to make sure that the TLV is not
3031 * already present in the LLDPDU.
3032 * In return firmware will write the complete LLDP MIB with the newly
3033 * added TLV in the response buffer.
3035 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3036 void *buff, u16 buff_size, u16 tlv_len,
3038 struct i40e_asq_cmd_details *cmd_details)
3040 struct i40e_aq_desc desc;
3041 struct i40e_aqc_lldp_add_tlv *cmd =
3042 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3043 enum i40e_status_code status;
3045 if (buff_size == 0 || !buff || tlv_len == 0)
3046 return I40E_ERR_PARAM;
3048 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3050 /* Indirect Command */
3051 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3052 if (buff_size > I40E_AQ_LARGE_BUF)
3053 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3054 desc.datalen = CPU_TO_LE16(buff_size);
3056 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3057 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3058 cmd->len = CPU_TO_LE16(tlv_len);
3060 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3062 if (mib_len != NULL)
3063 *mib_len = LE16_TO_CPU(desc.datalen);
3070 * i40e_aq_update_lldp_tlv
3071 * @hw: pointer to the hw struct
3072 * @bridge_type: type of bridge
3073 * @buff: buffer with TLV to update
3074 * @buff_size: size of the buffer holding original and updated TLVs
3075 * @old_len: Length of the Original TLV
3076 * @new_len: Length of the Updated TLV
3077 * @offset: offset of the updated TLV in the buff
3078 * @mib_len: length of the returned LLDP MIB
3079 * @cmd_details: pointer to command details structure or NULL
3081 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3082 * Firmware will place the complete LLDP MIB in response buffer with the
3085 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3086 u8 bridge_type, void *buff, u16 buff_size,
3087 u16 old_len, u16 new_len, u16 offset,
3089 struct i40e_asq_cmd_details *cmd_details)
3091 struct i40e_aq_desc desc;
3092 struct i40e_aqc_lldp_update_tlv *cmd =
3093 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3094 enum i40e_status_code status;
3096 if (buff_size == 0 || !buff || offset == 0 ||
3097 old_len == 0 || new_len == 0)
3098 return I40E_ERR_PARAM;
3100 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3102 /* Indirect Command */
3103 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3104 if (buff_size > I40E_AQ_LARGE_BUF)
3105 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3106 desc.datalen = CPU_TO_LE16(buff_size);
3108 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3109 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3110 cmd->old_len = CPU_TO_LE16(old_len);
3111 cmd->new_offset = CPU_TO_LE16(offset);
3112 cmd->new_len = CPU_TO_LE16(new_len);
3114 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3116 if (mib_len != NULL)
3117 *mib_len = LE16_TO_CPU(desc.datalen);
3124 * i40e_aq_delete_lldp_tlv
3125 * @hw: pointer to the hw struct
3126 * @bridge_type: type of bridge
3127 * @buff: pointer to a user supplied buffer that has the TLV
3128 * @buff_size: length of the buffer
3129 * @tlv_len: length of the TLV to be deleted
3130 * @mib_len: length of the returned LLDP MIB
3131 * @cmd_details: pointer to command details structure or NULL
3133 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3134 * The firmware places the entire LLDP MIB in the response buffer.
3136 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3137 u8 bridge_type, void *buff, u16 buff_size,
3138 u16 tlv_len, u16 *mib_len,
3139 struct i40e_asq_cmd_details *cmd_details)
3141 struct i40e_aq_desc desc;
3142 struct i40e_aqc_lldp_add_tlv *cmd =
3143 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3144 enum i40e_status_code status;
3146 if (buff_size == 0 || !buff)
3147 return I40E_ERR_PARAM;
3149 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3151 /* Indirect Command */
3152 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3153 if (buff_size > I40E_AQ_LARGE_BUF)
3154 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3155 desc.datalen = CPU_TO_LE16(buff_size);
3156 cmd->len = CPU_TO_LE16(tlv_len);
3157 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3158 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3160 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3162 if (mib_len != NULL)
3163 *mib_len = LE16_TO_CPU(desc.datalen);
3171 * @hw: pointer to the hw struct
3172 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3173 * @cmd_details: pointer to command details structure or NULL
3175 * Stop or Shutdown the embedded LLDP Agent
3177 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3178 struct i40e_asq_cmd_details *cmd_details)
3180 struct i40e_aq_desc desc;
3181 struct i40e_aqc_lldp_stop *cmd =
3182 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3183 enum i40e_status_code status;
3185 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3188 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3196 * i40e_aq_start_lldp
3197 * @hw: pointer to the hw struct
3198 * @cmd_details: pointer to command details structure or NULL
3200 * Start the embedded LLDP Agent on all ports.
3202 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3203 struct i40e_asq_cmd_details *cmd_details)
3205 struct i40e_aq_desc desc;
3206 struct i40e_aqc_lldp_start *cmd =
3207 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3208 enum i40e_status_code status;
3210 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3212 cmd->command = I40E_AQ_LLDP_AGENT_START;
3214 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3220 * i40e_aq_get_cee_dcb_config
3221 * @hw: pointer to the hw struct
3222 * @buff: response buffer that stores CEE operational configuration
3223 * @buff_size: size of the buffer passed
3224 * @cmd_details: pointer to command details structure or NULL
3226 * Get CEE DCBX mode operational configuration from firmware
3228 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3229 void *buff, u16 buff_size,
3230 struct i40e_asq_cmd_details *cmd_details)
3232 struct i40e_aq_desc desc;
3233 enum i40e_status_code status;
3235 if (buff_size == 0 || !buff)
3236 return I40E_ERR_PARAM;
3238 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3240 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3241 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3248 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3249 * @hw: pointer to the hw struct
3250 * @start_agent: True if DCBx Agent needs to be Started
3251 * False if DCBx Agent needs to be Stopped
3252 * @cmd_details: pointer to command details structure or NULL
3254 * Start/Stop the embedded dcbx Agent
3256 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3258 struct i40e_asq_cmd_details *cmd_details)
3260 struct i40e_aq_desc desc;
3261 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3262 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3264 enum i40e_status_code status;
3266 i40e_fill_default_direct_cmd_desc(&desc,
3267 i40e_aqc_opc_lldp_stop_start_spec_agent);
3270 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3278 * i40e_aq_add_udp_tunnel
3279 * @hw: pointer to the hw struct
3280 * @udp_port: the UDP port to add
3281 * @header_len: length of the tunneling header length in DWords
3282 * @protocol_index: protocol index type
3283 * @filter_index: pointer to filter index
3284 * @cmd_details: pointer to command details structure or NULL
3286 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3287 u16 udp_port, u8 protocol_index,
3289 struct i40e_asq_cmd_details *cmd_details)
3291 struct i40e_aq_desc desc;
3292 struct i40e_aqc_add_udp_tunnel *cmd =
3293 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3294 struct i40e_aqc_del_udp_tunnel_completion *resp =
3295 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3296 enum i40e_status_code status;
3298 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3300 cmd->udp_port = CPU_TO_LE16(udp_port);
3301 cmd->protocol_type = protocol_index;
3303 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3306 *filter_index = resp->index;
3312 * i40e_aq_del_udp_tunnel
3313 * @hw: pointer to the hw struct
3314 * @index: filter index
3315 * @cmd_details: pointer to command details structure or NULL
3317 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3318 struct i40e_asq_cmd_details *cmd_details)
3320 struct i40e_aq_desc desc;
3321 struct i40e_aqc_remove_udp_tunnel *cmd =
3322 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3323 enum i40e_status_code status;
3325 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3329 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3335 * i40e_aq_get_switch_resource_alloc (0x0204)
3336 * @hw: pointer to the hw struct
3337 * @num_entries: pointer to u8 to store the number of resource entries returned
3338 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3339 * to store the resource information for all resource types. Each
3340 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3341 * @count: size, in bytes, of the buffer provided
3342 * @cmd_details: pointer to command details structure or NULL
3344 * Query the resources allocated to a function.
3346 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3348 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3350 struct i40e_asq_cmd_details *cmd_details)
3352 struct i40e_aq_desc desc;
3353 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3354 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3355 enum i40e_status_code status;
3357 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3359 i40e_fill_default_direct_cmd_desc(&desc,
3360 i40e_aqc_opc_get_switch_resource_alloc);
3362 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3363 if (length > I40E_AQ_LARGE_BUF)
3364 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3366 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3369 *num_entries = cmd_resp->num_entries;
3375 * i40e_aq_delete_element - Delete switch element
3376 * @hw: pointer to the hw struct
3377 * @seid: the SEID to delete from the switch
3378 * @cmd_details: pointer to command details structure or NULL
3380 * This deletes a switch element from the switch.
3382 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3383 struct i40e_asq_cmd_details *cmd_details)
3385 struct i40e_aq_desc desc;
3386 struct i40e_aqc_switch_seid *cmd =
3387 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3388 enum i40e_status_code status;
3391 return I40E_ERR_PARAM;
3393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3395 cmd->seid = CPU_TO_LE16(seid);
3397 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3403 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3404 * @hw: pointer to the hw struct
3405 * @flags: component flags
3406 * @mac_seid: uplink seid (MAC SEID)
3407 * @vsi_seid: connected vsi seid
3408 * @ret_seid: seid of create pv component
3410 * This instantiates an i40e port virtualizer with specified flags.
3411 * Depending on specified flags the port virtualizer can act as a
3412 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3414 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3415 u16 mac_seid, u16 vsi_seid,
3418 struct i40e_aq_desc desc;
3419 struct i40e_aqc_add_update_pv *cmd =
3420 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3421 struct i40e_aqc_add_update_pv_completion *resp =
3422 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3423 enum i40e_status_code status;
3426 return I40E_ERR_PARAM;
3428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3429 cmd->command_flags = CPU_TO_LE16(flags);
3430 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3431 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3433 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3434 if (!status && ret_seid)
3435 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3441 * i40e_aq_add_tag - Add an S/E-tag
3442 * @hw: pointer to the hw struct
3443 * @direct_to_queue: should s-tag direct flow to a specific queue
3444 * @vsi_seid: VSI SEID to use this tag
3445 * @tag: value of the tag
3446 * @queue_num: queue number, only valid is direct_to_queue is true
3447 * @tags_used: return value, number of tags in use by this PF
3448 * @tags_free: return value, number of unallocated tags
3449 * @cmd_details: pointer to command details structure or NULL
3451 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3452 * the number of tags allocated by the PF, and the number of unallocated
3455 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3456 u16 vsi_seid, u16 tag, u16 queue_num,
3457 u16 *tags_used, u16 *tags_free,
3458 struct i40e_asq_cmd_details *cmd_details)
3460 struct i40e_aq_desc desc;
3461 struct i40e_aqc_add_tag *cmd =
3462 (struct i40e_aqc_add_tag *)&desc.params.raw;
3463 struct i40e_aqc_add_remove_tag_completion *resp =
3464 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3465 enum i40e_status_code status;
3468 return I40E_ERR_PARAM;
3470 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3472 cmd->seid = CPU_TO_LE16(vsi_seid);
3473 cmd->tag = CPU_TO_LE16(tag);
3474 if (direct_to_queue) {
3475 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3476 cmd->queue_number = CPU_TO_LE16(queue_num);
3479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3482 if (tags_used != NULL)
3483 *tags_used = LE16_TO_CPU(resp->tags_used);
3484 if (tags_free != NULL)
3485 *tags_free = LE16_TO_CPU(resp->tags_free);
3492 * i40e_aq_remove_tag - Remove an S- or E-tag
3493 * @hw: pointer to the hw struct
3494 * @vsi_seid: VSI SEID this tag is associated with
3495 * @tag: value of the S-tag to delete
3496 * @tags_used: return value, number of tags in use by this PF
3497 * @tags_free: return value, number of unallocated tags
3498 * @cmd_details: pointer to command details structure or NULL
3500 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3501 * the number of tags allocated by the PF, and the number of unallocated
3504 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3505 u16 tag, u16 *tags_used, u16 *tags_free,
3506 struct i40e_asq_cmd_details *cmd_details)
3508 struct i40e_aq_desc desc;
3509 struct i40e_aqc_remove_tag *cmd =
3510 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3511 struct i40e_aqc_add_remove_tag_completion *resp =
3512 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3513 enum i40e_status_code status;
3516 return I40E_ERR_PARAM;
3518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3520 cmd->seid = CPU_TO_LE16(vsi_seid);
3521 cmd->tag = CPU_TO_LE16(tag);
3523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3526 if (tags_used != NULL)
3527 *tags_used = LE16_TO_CPU(resp->tags_used);
3528 if (tags_free != NULL)
3529 *tags_free = LE16_TO_CPU(resp->tags_free);
3536 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3537 * @hw: pointer to the hw struct
3538 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3539 * @etag: value of E-tag to add
3540 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3541 * @buf: address of indirect buffer
3542 * @tags_used: return value, number of E-tags in use by this port
3543 * @tags_free: return value, number of unallocated M-tags
3544 * @cmd_details: pointer to command details structure or NULL
3546 * This associates a multicast E-tag to a port virtualizer. It will return
3547 * the number of tags allocated by the PF, and the number of unallocated
3550 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3551 * num_tags_in_buf long.
3553 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3554 u16 etag, u8 num_tags_in_buf, void *buf,
3555 u16 *tags_used, u16 *tags_free,
3556 struct i40e_asq_cmd_details *cmd_details)
3558 struct i40e_aq_desc desc;
3559 struct i40e_aqc_add_remove_mcast_etag *cmd =
3560 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3561 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3562 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3563 enum i40e_status_code status;
3564 u16 length = sizeof(u16) * num_tags_in_buf;
3566 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3567 return I40E_ERR_PARAM;
3569 i40e_fill_default_direct_cmd_desc(&desc,
3570 i40e_aqc_opc_add_multicast_etag);
3572 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3573 cmd->etag = CPU_TO_LE16(etag);
3574 cmd->num_unicast_etags = num_tags_in_buf;
3576 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3577 if (length > I40E_AQ_LARGE_BUF)
3578 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3580 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3583 if (tags_used != NULL)
3584 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3585 if (tags_free != NULL)
3586 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3593 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3594 * @hw: pointer to the hw struct
3595 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3596 * @etag: value of the E-tag to remove
3597 * @tags_used: return value, number of tags in use by this port
3598 * @tags_free: return value, number of unallocated tags
3599 * @cmd_details: pointer to command details structure or NULL
3601 * This deletes an E-tag from the port virtualizer. It will return
3602 * the number of tags allocated by the port, and the number of unallocated
3605 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3606 u16 etag, u16 *tags_used, u16 *tags_free,
3607 struct i40e_asq_cmd_details *cmd_details)
3609 struct i40e_aq_desc desc;
3610 struct i40e_aqc_add_remove_mcast_etag *cmd =
3611 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3612 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3613 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3614 enum i40e_status_code status;
3618 return I40E_ERR_PARAM;
3620 i40e_fill_default_direct_cmd_desc(&desc,
3621 i40e_aqc_opc_remove_multicast_etag);
3623 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3624 cmd->etag = CPU_TO_LE16(etag);
3626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3629 if (tags_used != NULL)
3630 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3631 if (tags_free != NULL)
3632 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3639 * i40e_aq_update_tag - Update an S/E-tag
3640 * @hw: pointer to the hw struct
3641 * @vsi_seid: VSI SEID using this S-tag
3642 * @old_tag: old tag value
3643 * @new_tag: new tag value
3644 * @tags_used: return value, number of tags in use by this PF
3645 * @tags_free: return value, number of unallocated tags
3646 * @cmd_details: pointer to command details structure or NULL
3648 * This updates the value of the tag currently attached to this VSI
3649 * in the switch complex. It will return the number of tags allocated
3650 * by the PF, and the number of unallocated tags available.
3652 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3653 u16 old_tag, u16 new_tag, u16 *tags_used,
3655 struct i40e_asq_cmd_details *cmd_details)
3657 struct i40e_aq_desc desc;
3658 struct i40e_aqc_update_tag *cmd =
3659 (struct i40e_aqc_update_tag *)&desc.params.raw;
3660 struct i40e_aqc_update_tag_completion *resp =
3661 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3662 enum i40e_status_code status;
3665 return I40E_ERR_PARAM;
3667 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3669 cmd->seid = CPU_TO_LE16(vsi_seid);
3670 cmd->old_tag = CPU_TO_LE16(old_tag);
3671 cmd->new_tag = CPU_TO_LE16(new_tag);
3673 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3676 if (tags_used != NULL)
3677 *tags_used = LE16_TO_CPU(resp->tags_used);
3678 if (tags_free != NULL)
3679 *tags_free = LE16_TO_CPU(resp->tags_free);
3686 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3687 * @hw: pointer to the hw struct
3688 * @tcmap: TC map for request/release any ignore PFC condition
3689 * @request: request or release ignore PFC condition
3690 * @tcmap_ret: return TCs for which PFC is currently ignored
3691 * @cmd_details: pointer to command details structure or NULL
3693 * This sends out request/release to ignore PFC condition for a TC.
3694 * It will return the TCs for which PFC is currently ignored.
3696 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3697 bool request, u8 *tcmap_ret,
3698 struct i40e_asq_cmd_details *cmd_details)
3700 struct i40e_aq_desc desc;
3701 struct i40e_aqc_pfc_ignore *cmd_resp =
3702 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3703 enum i40e_status_code status;
3705 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3708 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3710 cmd_resp->tc_bitmap = tcmap;
3712 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3715 if (tcmap_ret != NULL)
3716 *tcmap_ret = cmd_resp->tc_bitmap;
3723 * i40e_aq_dcb_updated - DCB Updated Command
3724 * @hw: pointer to the hw struct
3725 * @cmd_details: pointer to command details structure or NULL
3727 * When LLDP is handled in PF this command is used by the PF
3728 * to notify EMP that a DCB setting is modified.
3729 * When LLDP is handled in EMP this command is used by the PF
3730 * to notify EMP whenever one of the following parameters get
3732 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3733 * - PCIRTT in PRTDCB_GENC.PCIRTT
3734 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3735 * EMP will return when the shared RPB settings have been
3736 * recomputed and modified. The retval field in the descriptor
3737 * will be set to 0 when RPB is modified.
3739 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3740 struct i40e_asq_cmd_details *cmd_details)
3742 struct i40e_aq_desc desc;
3743 enum i40e_status_code status;
3745 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3747 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3753 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3754 * @hw: pointer to the hw struct
3755 * @seid: defines the SEID of the switch for which the stats are requested
3756 * @vlan_id: the VLAN ID for which the statistics are requested
3757 * @stat_index: index of the statistics counters block assigned to this VLAN
3758 * @cmd_details: pointer to command details structure or NULL
3760 * XL710 supports 128 smonVlanStats counters.This command is used to
3761 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3764 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3765 u16 vlan_id, u16 *stat_index,
3766 struct i40e_asq_cmd_details *cmd_details)
3768 struct i40e_aq_desc desc;
3769 struct i40e_aqc_add_remove_statistics *cmd_resp =
3770 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3771 enum i40e_status_code status;
3773 if ((seid == 0) || (stat_index == NULL))
3774 return I40E_ERR_PARAM;
3776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3778 cmd_resp->seid = CPU_TO_LE16(seid);
3779 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3784 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3790 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3791 * @hw: pointer to the hw struct
3792 * @seid: defines the SEID of the switch for which the stats are requested
3793 * @vlan_id: the VLAN ID for which the statistics are requested
3794 * @stat_index: index of the statistics counters block assigned to this VLAN
3795 * @cmd_details: pointer to command details structure or NULL
3797 * XL710 supports 128 smonVlanStats counters.This command is used to
3798 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3801 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3802 u16 vlan_id, u16 stat_index,
3803 struct i40e_asq_cmd_details *cmd_details)
3805 struct i40e_aq_desc desc;
3806 struct i40e_aqc_add_remove_statistics *cmd =
3807 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3808 enum i40e_status_code status;
3811 return I40E_ERR_PARAM;
3813 i40e_fill_default_direct_cmd_desc(&desc,
3814 i40e_aqc_opc_remove_statistics);
3816 cmd->seid = CPU_TO_LE16(seid);
3817 cmd->vlan = CPU_TO_LE16(vlan_id);
3818 cmd->stat_index = CPU_TO_LE16(stat_index);
3820 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3826 * i40e_aq_set_port_parameters - set physical port parameters.
3827 * @hw: pointer to the hw struct
3828 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3829 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3830 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3831 * @double_vlan: if set double VLAN is enabled
3832 * @cmd_details: pointer to command details structure or NULL
3834 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3835 u16 bad_frame_vsi, bool save_bad_pac,
3836 bool pad_short_pac, bool double_vlan,
3837 struct i40e_asq_cmd_details *cmd_details)
3839 struct i40e_aqc_set_port_parameters *cmd;
3840 enum i40e_status_code status;
3841 struct i40e_aq_desc desc;
3842 u16 command_flags = 0;
3844 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3846 i40e_fill_default_direct_cmd_desc(&desc,
3847 i40e_aqc_opc_set_port_parameters);
3849 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3851 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3853 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3855 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3856 cmd->command_flags = CPU_TO_LE16(command_flags);
3858 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3864 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3865 * @hw: pointer to the hw struct
3866 * @seid: seid for the physical port/switching component/vsi
3867 * @buff: Indirect buffer to hold data parameters and response
3868 * @buff_size: Indirect buffer size
3869 * @opcode: Tx scheduler AQ command opcode
3870 * @cmd_details: pointer to command details structure or NULL
3872 * Generic command handler for Tx scheduler AQ commands
3874 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3875 void *buff, u16 buff_size,
3876 enum i40e_admin_queue_opc opcode,
3877 struct i40e_asq_cmd_details *cmd_details)
3879 struct i40e_aq_desc desc;
3880 struct i40e_aqc_tx_sched_ind *cmd =
3881 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3882 enum i40e_status_code status;
3883 bool cmd_param_flag = false;
3886 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3887 case i40e_aqc_opc_configure_vsi_tc_bw:
3888 case i40e_aqc_opc_enable_switching_comp_ets:
3889 case i40e_aqc_opc_modify_switching_comp_ets:
3890 case i40e_aqc_opc_disable_switching_comp_ets:
3891 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3892 case i40e_aqc_opc_configure_switching_comp_bw_config:
3893 cmd_param_flag = true;
3895 case i40e_aqc_opc_query_vsi_bw_config:
3896 case i40e_aqc_opc_query_vsi_ets_sla_config:
3897 case i40e_aqc_opc_query_switching_comp_ets_config:
3898 case i40e_aqc_opc_query_port_ets_config:
3899 case i40e_aqc_opc_query_switching_comp_bw_config:
3900 cmd_param_flag = false;
3903 return I40E_ERR_PARAM;
3906 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3908 /* Indirect command */
3909 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3911 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3912 if (buff_size > I40E_AQ_LARGE_BUF)
3913 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3915 desc.datalen = CPU_TO_LE16(buff_size);
3917 cmd->vsi_seid = CPU_TO_LE16(seid);
3919 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3925 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3926 * @hw: pointer to the hw struct
3928 * @credit: BW limit credits (0 = disabled)
3929 * @max_credit: Max BW limit credits
3930 * @cmd_details: pointer to command details structure or NULL
3932 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3933 u16 seid, u16 credit, u8 max_credit,
3934 struct i40e_asq_cmd_details *cmd_details)
3936 struct i40e_aq_desc desc;
3937 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3938 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3939 enum i40e_status_code status;
3941 i40e_fill_default_direct_cmd_desc(&desc,
3942 i40e_aqc_opc_configure_vsi_bw_limit);
3944 cmd->vsi_seid = CPU_TO_LE16(seid);
3945 cmd->credit = CPU_TO_LE16(credit);
3946 cmd->max_credit = max_credit;
3948 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3954 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3955 * @hw: pointer to the hw struct
3956 * @seid: switching component seid
3957 * @credit: BW limit credits (0 = disabled)
3958 * @max_bw: Max BW limit credits
3959 * @cmd_details: pointer to command details structure or NULL
3961 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3962 u16 seid, u16 credit, u8 max_bw,
3963 struct i40e_asq_cmd_details *cmd_details)
3965 struct i40e_aq_desc desc;
3966 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3967 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3968 enum i40e_status_code status;
3970 i40e_fill_default_direct_cmd_desc(&desc,
3971 i40e_aqc_opc_configure_switching_comp_bw_limit);
3973 cmd->seid = CPU_TO_LE16(seid);
3974 cmd->credit = CPU_TO_LE16(credit);
3975 cmd->max_bw = max_bw;
3977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3983 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3984 * @hw: pointer to the hw struct
3986 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3987 * @cmd_details: pointer to command details structure or NULL
3989 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3991 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3992 struct i40e_asq_cmd_details *cmd_details)
3994 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3995 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4000 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4001 * @hw: pointer to the hw struct
4003 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4004 * @cmd_details: pointer to command details structure or NULL
4006 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4008 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4009 struct i40e_asq_cmd_details *cmd_details)
4011 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4012 i40e_aqc_opc_configure_vsi_tc_bw,
4017 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4018 * @hw: pointer to the hw struct
4019 * @seid: seid of the switching component
4020 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4021 * @cmd_details: pointer to command details structure or NULL
4023 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4024 struct i40e_hw *hw, u16 seid,
4025 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4026 struct i40e_asq_cmd_details *cmd_details)
4028 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4029 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4034 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4035 * @hw: pointer to the hw struct
4036 * @seid: seid of the VSI
4037 * @bw_data: Buffer to hold VSI BW configuration
4038 * @cmd_details: pointer to command details structure or NULL
4040 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4042 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4043 struct i40e_asq_cmd_details *cmd_details)
4045 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4046 i40e_aqc_opc_query_vsi_bw_config,
4051 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4052 * @hw: pointer to the hw struct
4053 * @seid: seid of the VSI
4054 * @bw_data: Buffer to hold VSI BW configuration per TC
4055 * @cmd_details: pointer to command details structure or NULL
4057 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4059 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4060 struct i40e_asq_cmd_details *cmd_details)
4062 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4063 i40e_aqc_opc_query_vsi_ets_sla_config,
4068 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4069 * @hw: pointer to the hw struct
4070 * @seid: seid of the switching component
4071 * @bw_data: Buffer to hold switching component's per TC BW config
4072 * @cmd_details: pointer to command details structure or NULL
4074 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4076 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4077 struct i40e_asq_cmd_details *cmd_details)
4079 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4080 i40e_aqc_opc_query_switching_comp_ets_config,
4085 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4086 * @hw: pointer to the hw struct
4087 * @seid: seid of the VSI or switching component connected to Physical Port
4088 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4089 * @cmd_details: pointer to command details structure or NULL
4091 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4093 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4094 struct i40e_asq_cmd_details *cmd_details)
4096 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4097 i40e_aqc_opc_query_port_ets_config,
4102 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4103 * @hw: pointer to the hw struct
4104 * @seid: seid of the switching component
4105 * @bw_data: Buffer to hold switching component's BW configuration
4106 * @cmd_details: pointer to command details structure or NULL
4108 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4110 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4111 struct i40e_asq_cmd_details *cmd_details)
4113 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4114 i40e_aqc_opc_query_switching_comp_bw_config,
4119 * i40e_validate_filter_settings
4120 * @hw: pointer to the hardware structure
4121 * @settings: Filter control settings
4123 * Check and validate the filter control settings passed.
4124 * The function checks for the valid filter/context sizes being
4125 * passed for FCoE and PE.
4127 * Returns I40E_SUCCESS if the values passed are valid and within
4128 * range else returns an error.
4130 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4131 struct i40e_filter_control_settings *settings)
4133 u32 fcoe_cntx_size, fcoe_filt_size;
4134 u32 pe_cntx_size, pe_filt_size;
4139 /* Validate FCoE settings passed */
4140 switch (settings->fcoe_filt_num) {
4141 case I40E_HASH_FILTER_SIZE_1K:
4142 case I40E_HASH_FILTER_SIZE_2K:
4143 case I40E_HASH_FILTER_SIZE_4K:
4144 case I40E_HASH_FILTER_SIZE_8K:
4145 case I40E_HASH_FILTER_SIZE_16K:
4146 case I40E_HASH_FILTER_SIZE_32K:
4147 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4148 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4151 return I40E_ERR_PARAM;
4154 switch (settings->fcoe_cntx_num) {
4155 case I40E_DMA_CNTX_SIZE_512:
4156 case I40E_DMA_CNTX_SIZE_1K:
4157 case I40E_DMA_CNTX_SIZE_2K:
4158 case I40E_DMA_CNTX_SIZE_4K:
4159 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4160 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4163 return I40E_ERR_PARAM;
4166 /* Validate PE settings passed */
4167 switch (settings->pe_filt_num) {
4168 case I40E_HASH_FILTER_SIZE_1K:
4169 case I40E_HASH_FILTER_SIZE_2K:
4170 case I40E_HASH_FILTER_SIZE_4K:
4171 case I40E_HASH_FILTER_SIZE_8K:
4172 case I40E_HASH_FILTER_SIZE_16K:
4173 case I40E_HASH_FILTER_SIZE_32K:
4174 case I40E_HASH_FILTER_SIZE_64K:
4175 case I40E_HASH_FILTER_SIZE_128K:
4176 case I40E_HASH_FILTER_SIZE_256K:
4177 case I40E_HASH_FILTER_SIZE_512K:
4178 case I40E_HASH_FILTER_SIZE_1M:
4179 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4180 pe_filt_size <<= (u32)settings->pe_filt_num;
4183 return I40E_ERR_PARAM;
4186 switch (settings->pe_cntx_num) {
4187 case I40E_DMA_CNTX_SIZE_512:
4188 case I40E_DMA_CNTX_SIZE_1K:
4189 case I40E_DMA_CNTX_SIZE_2K:
4190 case I40E_DMA_CNTX_SIZE_4K:
4191 case I40E_DMA_CNTX_SIZE_8K:
4192 case I40E_DMA_CNTX_SIZE_16K:
4193 case I40E_DMA_CNTX_SIZE_32K:
4194 case I40E_DMA_CNTX_SIZE_64K:
4195 case I40E_DMA_CNTX_SIZE_128K:
4196 case I40E_DMA_CNTX_SIZE_256K:
4197 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4198 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4201 return I40E_ERR_PARAM;
4204 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4205 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4206 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4207 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4208 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4209 return I40E_ERR_INVALID_SIZE;
4211 return I40E_SUCCESS;
4215 * i40e_set_filter_control
4216 * @hw: pointer to the hardware structure
4217 * @settings: Filter control settings
4219 * Set the Queue Filters for PE/FCoE and enable filters required
4220 * for a single PF. It is expected that these settings are programmed
4221 * at the driver initialization time.
4223 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4224 struct i40e_filter_control_settings *settings)
4226 enum i40e_status_code ret = I40E_SUCCESS;
4227 u32 hash_lut_size = 0;
4231 return I40E_ERR_PARAM;
4233 /* Validate the input settings */
4234 ret = i40e_validate_filter_settings(hw, settings);
4238 /* Read the PF Queue Filter control register */
4239 val = rd32(hw, I40E_PFQF_CTL_0);
4241 /* Program required PE hash buckets for the PF */
4242 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4243 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4244 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4245 /* Program required PE contexts for the PF */
4246 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4247 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4248 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4250 /* Program required FCoE hash buckets for the PF */
4251 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4252 val |= ((u32)settings->fcoe_filt_num <<
4253 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4254 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4255 /* Program required FCoE DDP contexts for the PF */
4256 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4257 val |= ((u32)settings->fcoe_cntx_num <<
4258 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4259 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4261 /* Program Hash LUT size for the PF */
4262 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4263 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4265 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4266 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4268 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4269 if (settings->enable_fdir)
4270 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4271 if (settings->enable_ethtype)
4272 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4273 if (settings->enable_macvlan)
4274 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4276 wr32(hw, I40E_PFQF_CTL_0, val);
4278 return I40E_SUCCESS;
4282 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4283 * @hw: pointer to the hw struct
4284 * @mac_addr: MAC address to use in the filter
4285 * @ethtype: Ethertype to use in the filter
4286 * @flags: Flags that needs to be applied to the filter
4287 * @vsi_seid: seid of the control VSI
4288 * @queue: VSI queue number to send the packet to
4289 * @is_add: Add control packet filter if True else remove
4290 * @stats: Structure to hold information on control filter counts
4291 * @cmd_details: pointer to command details structure or NULL
4293 * This command will Add or Remove control packet filter for a control VSI.
4294 * In return it will update the total number of perfect filter count in
4297 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4298 u8 *mac_addr, u16 ethtype, u16 flags,
4299 u16 vsi_seid, u16 queue, bool is_add,
4300 struct i40e_control_filter_stats *stats,
4301 struct i40e_asq_cmd_details *cmd_details)
4303 struct i40e_aq_desc desc;
4304 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4305 (struct i40e_aqc_add_remove_control_packet_filter *)
4307 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4308 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4310 enum i40e_status_code status;
4313 return I40E_ERR_PARAM;
4316 i40e_fill_default_direct_cmd_desc(&desc,
4317 i40e_aqc_opc_add_control_packet_filter);
4318 cmd->queue = CPU_TO_LE16(queue);
4320 i40e_fill_default_direct_cmd_desc(&desc,
4321 i40e_aqc_opc_remove_control_packet_filter);
4325 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4326 I40E_NONDMA_TO_NONDMA);
4328 cmd->etype = CPU_TO_LE16(ethtype);
4329 cmd->flags = CPU_TO_LE16(flags);
4330 cmd->seid = CPU_TO_LE16(vsi_seid);
4332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4334 if (!status && stats) {
4335 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4336 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4337 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4338 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4345 * i40e_aq_add_cloud_filters
4346 * @hw: pointer to the hardware structure
4347 * @seid: VSI seid to add cloud filters from
4348 * @filters: Buffer which contains the filters to be added
4349 * @filter_count: number of filters contained in the buffer
4351 * Set the cloud filters for a given VSI. The contents of the
4352 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4353 * in by the caller of the function.
4356 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4358 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4361 struct i40e_aq_desc desc;
4362 struct i40e_aqc_add_remove_cloud_filters *cmd =
4363 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4365 enum i40e_status_code status;
4367 i40e_fill_default_direct_cmd_desc(&desc,
4368 i40e_aqc_opc_add_cloud_filters);
4370 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4372 desc.datalen = CPU_TO_LE16(buff_len);
4373 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4374 cmd->num_filters = filter_count;
4375 cmd->seid = CPU_TO_LE16(seid);
4377 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4383 * i40e_aq_remove_cloud_filters
4384 * @hw: pointer to the hardware structure
4385 * @seid: VSI seid to remove cloud filters from
4386 * @filters: Buffer which contains the filters to be removed
4387 * @filter_count: number of filters contained in the buffer
4389 * Remove the cloud filters for a given VSI. The contents of the
4390 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4391 * in by the caller of the function.
4394 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4396 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4399 struct i40e_aq_desc desc;
4400 struct i40e_aqc_add_remove_cloud_filters *cmd =
4401 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4402 enum i40e_status_code status;
4405 i40e_fill_default_direct_cmd_desc(&desc,
4406 i40e_aqc_opc_remove_cloud_filters);
4408 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4410 desc.datalen = CPU_TO_LE16(buff_len);
4411 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4412 cmd->num_filters = filter_count;
4413 cmd->seid = CPU_TO_LE16(seid);
4415 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4421 * i40e_aq_alternate_write
4422 * @hw: pointer to the hardware structure
4423 * @reg_addr0: address of first dword to be read
4424 * @reg_val0: value to be written under 'reg_addr0'
4425 * @reg_addr1: address of second dword to be read
4426 * @reg_val1: value to be written under 'reg_addr1'
4428 * Write one or two dwords to alternate structure. Fields are indicated
4429 * by 'reg_addr0' and 'reg_addr1' register numbers.
4432 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4433 u32 reg_addr0, u32 reg_val0,
4434 u32 reg_addr1, u32 reg_val1)
4436 struct i40e_aq_desc desc;
4437 struct i40e_aqc_alternate_write *cmd_resp =
4438 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4439 enum i40e_status_code status;
4441 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4442 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4443 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4444 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4445 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4447 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4453 * i40e_aq_alternate_write_indirect
4454 * @hw: pointer to the hardware structure
4455 * @addr: address of a first register to be modified
4456 * @dw_count: number of alternate structure fields to write
4457 * @buffer: pointer to the command buffer
4459 * Write 'dw_count' dwords from 'buffer' to alternate structure
4460 * starting at 'addr'.
4463 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4464 u32 addr, u32 dw_count, void *buffer)
4466 struct i40e_aq_desc desc;
4467 struct i40e_aqc_alternate_ind_write *cmd_resp =
4468 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4469 enum i40e_status_code status;
4472 return I40E_ERR_PARAM;
4474 /* Indirect command */
4475 i40e_fill_default_direct_cmd_desc(&desc,
4476 i40e_aqc_opc_alternate_write_indirect);
4478 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4479 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4480 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4483 cmd_resp->address = CPU_TO_LE32(addr);
4484 cmd_resp->length = CPU_TO_LE32(dw_count);
4485 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4486 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4488 status = i40e_asq_send_command(hw, &desc, buffer,
4489 I40E_LO_DWORD(4*dw_count), NULL);
4495 * i40e_aq_alternate_read
4496 * @hw: pointer to the hardware structure
4497 * @reg_addr0: address of first dword to be read
4498 * @reg_val0: pointer for data read from 'reg_addr0'
4499 * @reg_addr1: address of second dword to be read
4500 * @reg_val1: pointer for data read from 'reg_addr1'
4502 * Read one or two dwords from alternate structure. Fields are indicated
4503 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4504 * is not passed then only register at 'reg_addr0' is read.
4507 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4508 u32 reg_addr0, u32 *reg_val0,
4509 u32 reg_addr1, u32 *reg_val1)
4511 struct i40e_aq_desc desc;
4512 struct i40e_aqc_alternate_write *cmd_resp =
4513 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4514 enum i40e_status_code status;
4516 if (reg_val0 == NULL)
4517 return I40E_ERR_PARAM;
4519 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4520 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4521 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4523 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4525 if (status == I40E_SUCCESS) {
4526 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4528 if (reg_val1 != NULL)
4529 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4536 * i40e_aq_alternate_read_indirect
4537 * @hw: pointer to the hardware structure
4538 * @addr: address of the alternate structure field
4539 * @dw_count: number of alternate structure fields to read
4540 * @buffer: pointer to the command buffer
4542 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4543 * place them in 'buffer'. The buffer should be allocated by caller.
4546 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4547 u32 addr, u32 dw_count, void *buffer)
4549 struct i40e_aq_desc desc;
4550 struct i40e_aqc_alternate_ind_write *cmd_resp =
4551 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4552 enum i40e_status_code status;
4555 return I40E_ERR_PARAM;
4557 /* Indirect command */
4558 i40e_fill_default_direct_cmd_desc(&desc,
4559 i40e_aqc_opc_alternate_read_indirect);
4561 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4562 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4563 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4564 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4566 cmd_resp->address = CPU_TO_LE32(addr);
4567 cmd_resp->length = CPU_TO_LE32(dw_count);
4568 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4569 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4571 status = i40e_asq_send_command(hw, &desc, buffer,
4572 I40E_LO_DWORD(4*dw_count), NULL);
4578 * i40e_aq_alternate_clear
4579 * @hw: pointer to the HW structure.
4581 * Clear the alternate structures of the port from which the function
4585 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4587 struct i40e_aq_desc desc;
4588 enum i40e_status_code status;
4590 i40e_fill_default_direct_cmd_desc(&desc,
4591 i40e_aqc_opc_alternate_clear_port);
4593 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4599 * i40e_aq_alternate_write_done
4600 * @hw: pointer to the HW structure.
4601 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4602 * @reset_needed: indicates the SW should trigger GLOBAL reset
4604 * Indicates to the FW that alternate structures have been changed.
4607 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4608 u8 bios_mode, bool *reset_needed)
4610 struct i40e_aq_desc desc;
4611 struct i40e_aqc_alternate_write_done *cmd =
4612 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4613 enum i40e_status_code status;
4615 if (reset_needed == NULL)
4616 return I40E_ERR_PARAM;
4618 i40e_fill_default_direct_cmd_desc(&desc,
4619 i40e_aqc_opc_alternate_write_done);
4621 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4623 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4625 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4626 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4632 * i40e_aq_set_oem_mode
4633 * @hw: pointer to the HW structure.
4634 * @oem_mode: the OEM mode to be used
4636 * Sets the device to a specific operating mode. Currently the only supported
4637 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4640 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4643 struct i40e_aq_desc desc;
4644 struct i40e_aqc_alternate_write_done *cmd =
4645 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4646 enum i40e_status_code status;
4648 i40e_fill_default_direct_cmd_desc(&desc,
4649 i40e_aqc_opc_alternate_set_mode);
4651 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4653 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4659 * i40e_aq_resume_port_tx
4660 * @hw: pointer to the hardware structure
4661 * @cmd_details: pointer to command details structure or NULL
4663 * Resume port's Tx traffic
4665 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4666 struct i40e_asq_cmd_details *cmd_details)
4668 struct i40e_aq_desc desc;
4669 enum i40e_status_code status;
4671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4673 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4679 * i40e_set_pci_config_data - store PCI bus info
4680 * @hw: pointer to hardware structure
4681 * @link_status: the link status word from PCI config space
4683 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4685 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4687 hw->bus.type = i40e_bus_type_pci_express;
4689 switch (link_status & I40E_PCI_LINK_WIDTH) {
4690 case I40E_PCI_LINK_WIDTH_1:
4691 hw->bus.width = i40e_bus_width_pcie_x1;
4693 case I40E_PCI_LINK_WIDTH_2:
4694 hw->bus.width = i40e_bus_width_pcie_x2;
4696 case I40E_PCI_LINK_WIDTH_4:
4697 hw->bus.width = i40e_bus_width_pcie_x4;
4699 case I40E_PCI_LINK_WIDTH_8:
4700 hw->bus.width = i40e_bus_width_pcie_x8;
4703 hw->bus.width = i40e_bus_width_unknown;
4707 switch (link_status & I40E_PCI_LINK_SPEED) {
4708 case I40E_PCI_LINK_SPEED_2500:
4709 hw->bus.speed = i40e_bus_speed_2500;
4711 case I40E_PCI_LINK_SPEED_5000:
4712 hw->bus.speed = i40e_bus_speed_5000;
4714 case I40E_PCI_LINK_SPEED_8000:
4715 hw->bus.speed = i40e_bus_speed_8000;
4718 hw->bus.speed = i40e_bus_speed_unknown;
4724 * i40e_read_bw_from_alt_ram
4725 * @hw: pointer to the hardware structure
4726 * @max_bw: pointer for max_bw read
4727 * @min_bw: pointer for min_bw read
4728 * @min_valid: pointer for bool that is true if min_bw is a valid value
4729 * @max_valid: pointer for bool that is true if max_bw is a valid value
4731 * Read bw from the alternate ram for the given pf
4733 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4734 u32 *max_bw, u32 *min_bw,
4735 bool *min_valid, bool *max_valid)
4737 enum i40e_status_code status;
4738 u32 max_bw_addr, min_bw_addr;
4740 /* Calculate the address of the min/max bw registers */
4741 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4742 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4743 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4744 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4745 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4746 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4748 /* Read the bandwidths from alt ram */
4749 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4750 min_bw_addr, min_bw);
4752 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4757 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4766 * i40e_aq_configure_partition_bw
4767 * @hw: pointer to the hardware structure
4768 * @bw_data: Buffer holding valid pfs and bw limits
4769 * @cmd_details: pointer to command details
4771 * Configure partitions guaranteed/max bw
4773 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4774 struct i40e_aqc_configure_partition_bw_data *bw_data,
4775 struct i40e_asq_cmd_details *cmd_details)
4777 enum i40e_status_code status;
4778 struct i40e_aq_desc desc;
4779 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4781 i40e_fill_default_direct_cmd_desc(&desc,
4782 i40e_aqc_opc_configure_partition_bw);
4784 /* Indirect command */
4785 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4786 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4788 if (bwd_size > I40E_AQ_LARGE_BUF)
4789 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4791 desc.datalen = CPU_TO_LE16(bwd_size);
4793 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4797 #endif /* PF_DRIVER */
4801 * i40e_aq_send_msg_to_pf
4802 * @hw: pointer to the hardware structure
4803 * @v_opcode: opcodes for VF-PF communication
4804 * @v_retval: return error code
4805 * @msg: pointer to the msg buffer
4806 * @msglen: msg length
4807 * @cmd_details: pointer to command details
4809 * Send message to PF driver using admin queue. By default, this message
4810 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4811 * completion before returning.
4813 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4814 enum i40e_virtchnl_ops v_opcode,
4815 enum i40e_status_code v_retval,
4816 u8 *msg, u16 msglen,
4817 struct i40e_asq_cmd_details *cmd_details)
4819 struct i40e_aq_desc desc;
4820 struct i40e_asq_cmd_details details;
4821 enum i40e_status_code status;
4823 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4824 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4825 desc.cookie_high = CPU_TO_LE32(v_opcode);
4826 desc.cookie_low = CPU_TO_LE32(v_retval);
4828 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4829 | I40E_AQ_FLAG_RD));
4830 if (msglen > I40E_AQ_LARGE_BUF)
4831 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4832 desc.datalen = CPU_TO_LE16(msglen);
4835 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4836 details.async = true;
4837 cmd_details = &details;
4839 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4840 msglen, cmd_details);
4845 * i40e_vf_parse_hw_config
4846 * @hw: pointer to the hardware structure
4847 * @msg: pointer to the virtual channel VF resource structure
4849 * Given a VF resource message from the PF, populate the hw struct
4850 * with appropriate information.
4852 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4853 struct i40e_virtchnl_vf_resource *msg)
4855 struct i40e_virtchnl_vsi_resource *vsi_res;
4858 vsi_res = &msg->vsi_res[0];
4860 hw->dev_caps.num_vsis = msg->num_vsis;
4861 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4862 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4863 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4864 hw->dev_caps.dcb = msg->vf_offload_flags &
4865 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4866 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4867 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4868 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4869 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4870 for (i = 0; i < msg->num_vsis; i++) {
4871 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4872 i40e_memcpy(hw->mac.perm_addr,
4873 vsi_res->default_mac_addr,
4874 I40E_ETH_LENGTH_OF_ADDRESS,
4875 I40E_NONDMA_TO_NONDMA);
4876 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4877 I40E_ETH_LENGTH_OF_ADDRESS,
4878 I40E_NONDMA_TO_NONDMA);
4886 * @hw: pointer to the hardware structure
4888 * Send a VF_RESET message to the PF. Does not wait for response from PF
4889 * as none will be forthcoming. Immediately after calling this function,
4890 * the admin queue should be shut down and (optionally) reinitialized.
4892 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4894 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4895 I40E_SUCCESS, NULL, 0, NULL);
4897 #endif /* VF_DRIVER */