1 /*******************************************************************************
3 Copyright (c) 2013 - 2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 hw->mac.type = I40E_MAC_XL710;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
87 * @hw: debug mask related to admin queue
89 * @desc: pointer to admin queue descriptor
90 * @buffer: pointer to command buffer
92 * Dumps debug log about adminq command with descriptor contents.
94 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
98 u8 *aq_buffer = (u8 *)buffer;
102 if ((!(mask & hw->debug_mask)) || (desc == NULL))
106 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
107 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
109 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
110 aq_desc->cookie_high, aq_desc->cookie_low);
111 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
112 aq_desc->params.internal.param0,
113 aq_desc->params.internal.param1);
114 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
115 aq_desc->params.external.addr_high,
116 aq_desc->params.external.addr_low);
118 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
119 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
120 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
121 for (i = 0; i < LE16_TO_CPU(aq_desc->datalen); i++) {
122 data[((i % 16) / 4)] |=
123 ((u32)aq_buffer[i]) << (8 * (i % 4));
124 if ((i % 16) == 15) {
126 "\t0x%04X %08X %08X %08X %08X\n",
127 i - 15, data[0], data[1], data[2],
129 i40e_memset(data, 0, sizeof(data),
134 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
135 i - (i % 16), data[0], data[1], data[2],
141 * i40e_check_asq_alive
142 * @hw: pointer to the hw struct
144 * Returns true if Queue is enabled else false.
146 bool i40e_check_asq_alive(struct i40e_hw *hw)
149 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
155 * i40e_aq_queue_shutdown
156 * @hw: pointer to the hw struct
157 * @unloading: is the driver unloading itself
159 * Tell the Firmware that we're shutting down the AdminQ and whether
160 * or not the driver is unloading as well.
162 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
165 struct i40e_aq_desc desc;
166 struct i40e_aqc_queue_shutdown *cmd =
167 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
168 enum i40e_status_code status;
170 i40e_fill_default_direct_cmd_desc(&desc,
171 i40e_aqc_opc_queue_shutdown);
174 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
175 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
180 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
181 * hardware to a bit-field that can be used by SW to more easily determine the
184 * Macros are used to shorten the table lines and make this table human
187 * We store the PTYPE in the top byte of the bit field - this is just so that
188 * we can check that the table doesn't have a row missing, as the index into
189 * the table should be the PTYPE.
193 * IF NOT i40e_ptype_lookup[ptype].known
196 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
197 * Use the rest of the fields to look at the tunnels, inner protocols, etc
199 * Use the enum i40e_rx_l2_ptype to decode the packet type
203 /* macro to make the table lines short */
204 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
207 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
208 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
209 I40E_RX_PTYPE_##OUTER_FRAG, \
210 I40E_RX_PTYPE_TUNNEL_##T, \
211 I40E_RX_PTYPE_TUNNEL_END_##TE, \
212 I40E_RX_PTYPE_##TEF, \
213 I40E_RX_PTYPE_INNER_PROT_##I, \
214 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
216 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
217 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
219 /* shorter macros makes the table fit but are terse */
220 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
221 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
222 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
224 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
225 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
226 /* L2 Packet types */
227 I40E_PTT_UNUSED_ENTRY(0),
228 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
229 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
230 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
231 I40E_PTT_UNUSED_ENTRY(4),
232 I40E_PTT_UNUSED_ENTRY(5),
233 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
235 I40E_PTT_UNUSED_ENTRY(8),
236 I40E_PTT_UNUSED_ENTRY(9),
237 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
239 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 /* Non Tunneled IPv4 */
251 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
254 I40E_PTT_UNUSED_ENTRY(25),
255 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
256 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
257 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
260 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
261 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
262 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(32),
264 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
265 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
266 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
269 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
270 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
271 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(39),
273 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
274 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
275 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
277 /* IPv4 --> GRE/NAT */
278 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
280 /* IPv4 --> GRE/NAT --> IPv4 */
281 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
282 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
283 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
284 I40E_PTT_UNUSED_ENTRY(47),
285 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
286 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
287 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
289 /* IPv4 --> GRE/NAT --> IPv6 */
290 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
291 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
292 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(54),
294 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
295 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
296 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> MAC */
299 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
301 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
302 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
303 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
304 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
305 I40E_PTT_UNUSED_ENTRY(62),
306 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
307 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
308 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
310 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
311 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
312 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
313 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(69),
315 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
316 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
317 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT --> MAC/VLAN */
320 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
322 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
323 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
324 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
325 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
326 I40E_PTT_UNUSED_ENTRY(77),
327 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
328 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
329 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
331 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
332 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
333 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
334 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(84),
336 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
337 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
338 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
340 /* Non Tunneled IPv6 */
341 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
342 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
343 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
344 I40E_PTT_UNUSED_ENTRY(91),
345 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
346 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
347 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
350 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
351 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
352 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
353 I40E_PTT_UNUSED_ENTRY(98),
354 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
355 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
356 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
359 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
360 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
361 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(105),
363 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
364 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
365 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
367 /* IPv6 --> GRE/NAT */
368 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
370 /* IPv6 --> GRE/NAT -> IPv4 */
371 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
372 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
373 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
374 I40E_PTT_UNUSED_ENTRY(113),
375 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
376 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
377 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
379 /* IPv6 --> GRE/NAT -> IPv6 */
380 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
381 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
382 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(120),
384 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
385 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
386 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> MAC */
389 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
391 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
392 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
393 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
394 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
395 I40E_PTT_UNUSED_ENTRY(128),
396 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
397 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
398 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
401 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
402 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
403 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(135),
405 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
406 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
407 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC/VLAN */
410 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
413 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
414 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
415 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
416 I40E_PTT_UNUSED_ENTRY(143),
417 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
418 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
419 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
422 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
423 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
424 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(150),
426 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
427 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
428 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
431 I40E_PTT_UNUSED_ENTRY(154),
432 I40E_PTT_UNUSED_ENTRY(155),
433 I40E_PTT_UNUSED_ENTRY(156),
434 I40E_PTT_UNUSED_ENTRY(157),
435 I40E_PTT_UNUSED_ENTRY(158),
436 I40E_PTT_UNUSED_ENTRY(159),
438 I40E_PTT_UNUSED_ENTRY(160),
439 I40E_PTT_UNUSED_ENTRY(161),
440 I40E_PTT_UNUSED_ENTRY(162),
441 I40E_PTT_UNUSED_ENTRY(163),
442 I40E_PTT_UNUSED_ENTRY(164),
443 I40E_PTT_UNUSED_ENTRY(165),
444 I40E_PTT_UNUSED_ENTRY(166),
445 I40E_PTT_UNUSED_ENTRY(167),
446 I40E_PTT_UNUSED_ENTRY(168),
447 I40E_PTT_UNUSED_ENTRY(169),
449 I40E_PTT_UNUSED_ENTRY(170),
450 I40E_PTT_UNUSED_ENTRY(171),
451 I40E_PTT_UNUSED_ENTRY(172),
452 I40E_PTT_UNUSED_ENTRY(173),
453 I40E_PTT_UNUSED_ENTRY(174),
454 I40E_PTT_UNUSED_ENTRY(175),
455 I40E_PTT_UNUSED_ENTRY(176),
456 I40E_PTT_UNUSED_ENTRY(177),
457 I40E_PTT_UNUSED_ENTRY(178),
458 I40E_PTT_UNUSED_ENTRY(179),
460 I40E_PTT_UNUSED_ENTRY(180),
461 I40E_PTT_UNUSED_ENTRY(181),
462 I40E_PTT_UNUSED_ENTRY(182),
463 I40E_PTT_UNUSED_ENTRY(183),
464 I40E_PTT_UNUSED_ENTRY(184),
465 I40E_PTT_UNUSED_ENTRY(185),
466 I40E_PTT_UNUSED_ENTRY(186),
467 I40E_PTT_UNUSED_ENTRY(187),
468 I40E_PTT_UNUSED_ENTRY(188),
469 I40E_PTT_UNUSED_ENTRY(189),
471 I40E_PTT_UNUSED_ENTRY(190),
472 I40E_PTT_UNUSED_ENTRY(191),
473 I40E_PTT_UNUSED_ENTRY(192),
474 I40E_PTT_UNUSED_ENTRY(193),
475 I40E_PTT_UNUSED_ENTRY(194),
476 I40E_PTT_UNUSED_ENTRY(195),
477 I40E_PTT_UNUSED_ENTRY(196),
478 I40E_PTT_UNUSED_ENTRY(197),
479 I40E_PTT_UNUSED_ENTRY(198),
480 I40E_PTT_UNUSED_ENTRY(199),
482 I40E_PTT_UNUSED_ENTRY(200),
483 I40E_PTT_UNUSED_ENTRY(201),
484 I40E_PTT_UNUSED_ENTRY(202),
485 I40E_PTT_UNUSED_ENTRY(203),
486 I40E_PTT_UNUSED_ENTRY(204),
487 I40E_PTT_UNUSED_ENTRY(205),
488 I40E_PTT_UNUSED_ENTRY(206),
489 I40E_PTT_UNUSED_ENTRY(207),
490 I40E_PTT_UNUSED_ENTRY(208),
491 I40E_PTT_UNUSED_ENTRY(209),
493 I40E_PTT_UNUSED_ENTRY(210),
494 I40E_PTT_UNUSED_ENTRY(211),
495 I40E_PTT_UNUSED_ENTRY(212),
496 I40E_PTT_UNUSED_ENTRY(213),
497 I40E_PTT_UNUSED_ENTRY(214),
498 I40E_PTT_UNUSED_ENTRY(215),
499 I40E_PTT_UNUSED_ENTRY(216),
500 I40E_PTT_UNUSED_ENTRY(217),
501 I40E_PTT_UNUSED_ENTRY(218),
502 I40E_PTT_UNUSED_ENTRY(219),
504 I40E_PTT_UNUSED_ENTRY(220),
505 I40E_PTT_UNUSED_ENTRY(221),
506 I40E_PTT_UNUSED_ENTRY(222),
507 I40E_PTT_UNUSED_ENTRY(223),
508 I40E_PTT_UNUSED_ENTRY(224),
509 I40E_PTT_UNUSED_ENTRY(225),
510 I40E_PTT_UNUSED_ENTRY(226),
511 I40E_PTT_UNUSED_ENTRY(227),
512 I40E_PTT_UNUSED_ENTRY(228),
513 I40E_PTT_UNUSED_ENTRY(229),
515 I40E_PTT_UNUSED_ENTRY(230),
516 I40E_PTT_UNUSED_ENTRY(231),
517 I40E_PTT_UNUSED_ENTRY(232),
518 I40E_PTT_UNUSED_ENTRY(233),
519 I40E_PTT_UNUSED_ENTRY(234),
520 I40E_PTT_UNUSED_ENTRY(235),
521 I40E_PTT_UNUSED_ENTRY(236),
522 I40E_PTT_UNUSED_ENTRY(237),
523 I40E_PTT_UNUSED_ENTRY(238),
524 I40E_PTT_UNUSED_ENTRY(239),
526 I40E_PTT_UNUSED_ENTRY(240),
527 I40E_PTT_UNUSED_ENTRY(241),
528 I40E_PTT_UNUSED_ENTRY(242),
529 I40E_PTT_UNUSED_ENTRY(243),
530 I40E_PTT_UNUSED_ENTRY(244),
531 I40E_PTT_UNUSED_ENTRY(245),
532 I40E_PTT_UNUSED_ENTRY(246),
533 I40E_PTT_UNUSED_ENTRY(247),
534 I40E_PTT_UNUSED_ENTRY(248),
535 I40E_PTT_UNUSED_ENTRY(249),
537 I40E_PTT_UNUSED_ENTRY(250),
538 I40E_PTT_UNUSED_ENTRY(251),
539 I40E_PTT_UNUSED_ENTRY(252),
540 I40E_PTT_UNUSED_ENTRY(253),
541 I40E_PTT_UNUSED_ENTRY(254),
542 I40E_PTT_UNUSED_ENTRY(255)
545 #ifdef I40E_TPH_SUPPORT
549 * @hw: pointer to the hw struct
551 * Check to see if TPH capability is present.
553 bool i40e_tph_present(struct i40e_hw *hw)
555 u32 capsup = rd32(hw, I40E_GLPCI_CAPSUP);
557 return capsup & I40E_GLPCI_CAPSUP_TPH_EN_MASK;
562 * @hw: pointer to the hw struct
563 * @tph_control: contents of TPH Requester Control Register
565 * Check to see if TPH can be enabled; if so, enable it.
567 bool i40e_enable_tph(struct i40e_hw *hw, u32 tph_control)
569 u32 gltph, st_mode, permit;
571 /* check that TPH is permitted */
572 permit = (tph_control & I40E_TPH_REQ_ENA_MASK)
573 >> I40E_TPH_REQ_ENA_SHIFT;
574 if (!(permit & I40E_TPH_REQ_PERMIT))
577 /* check for valid ST mode */
578 st_mode = tph_control & I40E_TPH_ST_MODE_MASK;
579 if ((st_mode != I40E_TPH_MODE_NOTABLE) &&
580 (st_mode != I40E_TPH_MODE_DEVSPEC))
583 /* TPH may be enabled */
584 gltph = rd32(hw, I40E_GLTPH_CTRL);
586 /* turn off device-specific */
587 if (st_mode != I40E_TPH_MODE_DEVSPEC)
588 gltph &= ~I40E_GLTPH_CTRL_TPH_DEVSPEC_MASK;
590 /* This enables TPH for all queues for the given types of operation.
591 * Additional enabling is done per-queue in setup of the queue contexts.
593 gltph |= I40E_GLTPH_CTRL_DESC_PH_MASK; /* descriptor reads/writes */
594 gltph |= I40E_GLTPH_CTRL_DATA_PH_MASK; /* data reads/writes */
595 wr32(hw, I40E_GLTPH_CTRL, gltph);
599 #endif /* I40E_TPH_SUPPORT */
603 * i40e_init_shared_code - Initialize the shared code
604 * @hw: pointer to hardware structure
606 * This assigns the MAC type and PHY code and inits the NVM.
607 * Does not touch the hardware. This function must be called prior to any
608 * other function in the shared code. The i40e_hw structure should be
609 * memset to 0 prior to calling this function. The following fields in
610 * hw structure should be filled in prior to calling this function:
611 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
612 * subsystem_vendor_id, and revision_id
614 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
616 enum i40e_status_code status = I40E_SUCCESS;
619 DEBUGFUNC("i40e_init_shared_code");
621 i40e_set_mac_type(hw);
623 switch (hw->mac.type) {
627 return I40E_ERR_DEVICE_NOT_SUPPORTED;
631 hw->phy.get_link_info = true;
633 /* Determine port number */
634 reg = rd32(hw, I40E_PFGEN_PORTNUM);
635 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
636 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
639 /* Determine the PF number based on the PCI fn */
640 reg = rd32(hw, I40E_GLPCI_CAPSUP);
641 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
642 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
644 hw->pf_id = (u8)hw->bus.func;
646 status = i40e_init_nvm(hw);
651 * i40e_aq_mac_address_read - Retrieve the MAC addresses
652 * @hw: pointer to the hw struct
653 * @flags: a return indicator of what addresses were added to the addr store
654 * @addrs: the requestor's mac addr store
655 * @cmd_details: pointer to command details structure or NULL
657 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
659 struct i40e_aqc_mac_address_read_data *addrs,
660 struct i40e_asq_cmd_details *cmd_details)
662 struct i40e_aq_desc desc;
663 struct i40e_aqc_mac_address_read *cmd_data =
664 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
665 enum i40e_status_code status;
667 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
668 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
670 status = i40e_asq_send_command(hw, &desc, addrs,
671 sizeof(*addrs), cmd_details);
672 *flags = LE16_TO_CPU(cmd_data->command_flags);
678 * i40e_aq_mac_address_write - Change the MAC addresses
679 * @hw: pointer to the hw struct
680 * @flags: indicates which MAC to be written
681 * @mac_addr: address to write
682 * @cmd_details: pointer to command details structure or NULL
684 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
685 u16 flags, u8 *mac_addr,
686 struct i40e_asq_cmd_details *cmd_details)
688 struct i40e_aq_desc desc;
689 struct i40e_aqc_mac_address_write *cmd_data =
690 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
691 enum i40e_status_code status;
693 i40e_fill_default_direct_cmd_desc(&desc,
694 i40e_aqc_opc_mac_address_write);
695 cmd_data->command_flags = CPU_TO_LE16(flags);
696 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
697 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
698 ((u32)mac_addr[3] << 16) |
699 ((u32)mac_addr[4] << 8) |
702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
708 * i40e_get_mac_addr - get MAC address
709 * @hw: pointer to the HW structure
710 * @mac_addr: pointer to MAC address
712 * Reads the adapter's MAC address from register
714 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
716 struct i40e_aqc_mac_address_read_data addrs;
717 enum i40e_status_code status;
720 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
722 if (flags & I40E_AQC_LAN_ADDR_VALID)
723 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
729 * i40e_get_port_mac_addr - get Port MAC address
730 * @hw: pointer to the HW structure
731 * @mac_addr: pointer to Port MAC address
733 * Reads the adapter's Port MAC address
735 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
737 struct i40e_aqc_mac_address_read_data addrs;
738 enum i40e_status_code status;
741 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
745 if (flags & I40E_AQC_PORT_ADDR_VALID)
746 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
748 status = I40E_ERR_INVALID_MAC_ADDR;
754 * i40e_pre_tx_queue_cfg - pre tx queue configure
755 * @hw: pointer to the HW structure
756 * @queue: target pf queue index
757 * @enable: state change request
759 * Handles hw requirement to indicate intention to enable
760 * or disable target queue.
762 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
764 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
768 if (abs_queue_idx >= 128) {
769 reg_block = abs_queue_idx / 128;
770 abs_queue_idx %= 128;
773 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
774 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
775 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
778 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
780 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
782 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
786 * i40e_validate_mac_addr - Validate unicast MAC address
787 * @mac_addr: pointer to MAC address
789 * Tests a MAC address to ensure it is a valid Individual Address
791 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
793 enum i40e_status_code status = I40E_SUCCESS;
795 DEBUGFUNC("i40e_validate_mac_addr");
797 /* Broadcast addresses ARE multicast addresses
798 * Make sure it is not a multicast address
799 * Reject the zero address
801 if (I40E_IS_MULTICAST(mac_addr) ||
802 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
803 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
804 status = I40E_ERR_INVALID_MAC_ADDR;
810 * i40e_get_media_type - Gets media type
811 * @hw: pointer to the hardware structure
813 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
815 enum i40e_media_type media;
817 switch (hw->phy.link_info.phy_type) {
818 case I40E_PHY_TYPE_10GBASE_SR:
819 case I40E_PHY_TYPE_10GBASE_LR:
820 case I40E_PHY_TYPE_40GBASE_SR4:
821 case I40E_PHY_TYPE_40GBASE_LR4:
822 media = I40E_MEDIA_TYPE_FIBER;
824 case I40E_PHY_TYPE_100BASE_TX:
825 case I40E_PHY_TYPE_1000BASE_T:
826 case I40E_PHY_TYPE_10GBASE_T:
827 media = I40E_MEDIA_TYPE_BASET;
829 case I40E_PHY_TYPE_10GBASE_CR1_CU:
830 case I40E_PHY_TYPE_40GBASE_CR4_CU:
831 case I40E_PHY_TYPE_10GBASE_CR1:
832 case I40E_PHY_TYPE_40GBASE_CR4:
833 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
834 media = I40E_MEDIA_TYPE_DA;
836 case I40E_PHY_TYPE_1000BASE_KX:
837 case I40E_PHY_TYPE_10GBASE_KX4:
838 case I40E_PHY_TYPE_10GBASE_KR:
839 case I40E_PHY_TYPE_40GBASE_KR4:
840 media = I40E_MEDIA_TYPE_BACKPLANE;
842 case I40E_PHY_TYPE_SGMII:
843 case I40E_PHY_TYPE_XAUI:
844 case I40E_PHY_TYPE_XFI:
845 case I40E_PHY_TYPE_XLAUI:
846 case I40E_PHY_TYPE_XLPPI:
848 media = I40E_MEDIA_TYPE_UNKNOWN;
855 #define I40E_PF_RESET_WAIT_COUNT 100
857 * i40e_pf_reset - Reset the PF
858 * @hw: pointer to the hardware structure
860 * Assuming someone else has triggered a global reset,
861 * assure the global reset is complete and then reset the PF
863 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
870 /* Poll for Global Reset steady state in case of recent GRST.
871 * The grst delay value is in 100ms units, and we'll wait a
872 * couple counts longer to be sure we don't just miss the end.
874 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
875 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
876 for (cnt = 0; cnt < grst_del + 2; cnt++) {
877 reg = rd32(hw, I40E_GLGEN_RSTAT);
878 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
880 i40e_msec_delay(100);
882 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
883 DEBUGOUT("Global reset polling failed to complete.\n");
884 return I40E_ERR_RESET_FAILED;
887 /* Now Wait for the FW to be ready */
888 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
889 reg = rd32(hw, I40E_GLNVM_ULD);
890 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
891 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
892 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
893 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
894 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
899 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
900 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
901 DEBUGOUT("wait for FW Reset complete timedout\n");
902 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
903 return I40E_ERR_RESET_FAILED;
906 /* If there was a Global Reset in progress when we got here,
907 * we don't need to do the PF Reset
910 reg = rd32(hw, I40E_PFGEN_CTRL);
911 wr32(hw, I40E_PFGEN_CTRL,
912 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
913 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
914 reg = rd32(hw, I40E_PFGEN_CTRL);
915 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
919 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
920 DEBUGOUT("PF reset polling failed to complete.\n");
921 return I40E_ERR_RESET_FAILED;
925 i40e_clear_pxe_mode(hw);
931 * i40e_clear_hw - clear out any left over hw state
932 * @hw: pointer to the hw struct
934 * Clear queues and interrupts, typically called at init time,
935 * but after the capabilities have been found so we know how many
936 * queues and msix vectors have been allocated.
938 void i40e_clear_hw(struct i40e_hw *hw)
940 u32 num_queues, base_queue;
948 /* get number of interrupts, queues, and vfs */
949 val = rd32(hw, I40E_GLPCI_CNF2);
950 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
951 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
952 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
953 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
955 val = rd32(hw, I40E_PFLAN_QALLOC);
956 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
957 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
958 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
959 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
960 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
961 num_queues = (j - base_queue) + 1;
965 val = rd32(hw, I40E_PF_VT_PFALLOC);
966 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
967 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
968 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
969 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
970 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
971 num_vfs = (j - i) + 1;
975 /* stop all the interrupts */
976 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
977 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
978 for (i = 0; i < num_pf_int - 2; i++)
979 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
981 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
982 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
983 wr32(hw, I40E_PFINT_LNKLST0, val);
984 for (i = 0; i < num_pf_int - 2; i++)
985 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
986 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
987 for (i = 0; i < num_vfs; i++)
988 wr32(hw, I40E_VPINT_LNKLST0(i), val);
989 for (i = 0; i < num_vf_int - 2; i++)
990 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
992 /* warn the HW of the coming Tx disables */
993 for (i = 0; i < num_queues; i++) {
994 u32 abs_queue_idx = base_queue + i;
997 if (abs_queue_idx >= 128) {
998 reg_block = abs_queue_idx / 128;
999 abs_queue_idx %= 128;
1002 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1003 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1004 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1005 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1007 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1009 i40e_usec_delay(400);
1011 /* stop all the queues */
1012 for (i = 0; i < num_queues; i++) {
1013 wr32(hw, I40E_QINT_TQCTL(i), 0);
1014 wr32(hw, I40E_QTX_ENA(i), 0);
1015 wr32(hw, I40E_QINT_RQCTL(i), 0);
1016 wr32(hw, I40E_QRX_ENA(i), 0);
1019 /* short wait for all queue disables to settle */
1020 i40e_usec_delay(50);
1024 * i40e_clear_pxe_mode - clear pxe operations mode
1025 * @hw: pointer to the hw struct
1027 * Make sure all PXE mode settings are cleared, including things
1028 * like descriptor fetch/write-back mode.
1030 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1032 if (i40e_check_asq_alive(hw))
1033 i40e_aq_clear_pxe_mode(hw, NULL);
1037 * i40e_led_is_mine - helper to find matching led
1038 * @hw: pointer to the hw struct
1039 * @idx: index into GPIO registers
1041 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1043 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1048 if (!hw->func_caps.led[idx])
1051 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1052 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1053 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1055 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1056 * if it is not our port then ignore
1058 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1065 #define I40E_LED0 22
1066 #define I40E_LINK_ACTIVITY 0xC
1069 * i40e_led_get - return current on/off mode
1070 * @hw: pointer to the hw struct
1072 * The value returned is the 'mode' field as defined in the
1073 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1074 * values are variations of possible behaviors relating to
1075 * blink, link, and wire.
1077 u32 i40e_led_get(struct i40e_hw *hw)
1082 /* as per the documentation GPIO 22-29 are the LED
1083 * GPIO pins named LED0..LED7
1085 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1086 u32 gpio_val = i40e_led_is_mine(hw, i);
1091 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1092 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1100 * i40e_led_set - set new on/off mode
1101 * @hw: pointer to the hw struct
1102 * @mode: 0=off, 0xf=on (else see manual for mode details)
1103 * @blink: true if the LED should blink when on, false if steady
1105 * if this function is used to turn on the blink it should
1106 * be used to disable the blink when restoring the original state.
1108 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1112 if (mode & 0xfffffff0)
1113 DEBUGOUT1("invalid mode passed in %X\n", mode);
1115 /* as per the documentation GPIO 22-29 are the LED
1116 * GPIO pins named LED0..LED7
1118 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1119 u32 gpio_val = i40e_led_is_mine(hw, i);
1124 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1125 /* this & is a bit of paranoia, but serves as a range check */
1126 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1127 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1129 if (mode == I40E_LINK_ACTIVITY)
1132 gpio_val |= (blink ? 1 : 0) <<
1133 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1135 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1140 /* Admin command wrappers */
1143 * i40e_aq_get_phy_capabilities
1144 * @hw: pointer to the hw struct
1145 * @abilities: structure for PHY capabilities to be filled
1146 * @qualified_modules: report Qualified Modules
1147 * @report_init: report init capabilities (active are default)
1148 * @cmd_details: pointer to command details structure or NULL
1150 * Returns the various PHY abilities supported on the Port.
1152 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1153 bool qualified_modules, bool report_init,
1154 struct i40e_aq_get_phy_abilities_resp *abilities,
1155 struct i40e_asq_cmd_details *cmd_details)
1157 struct i40e_aq_desc desc;
1158 enum i40e_status_code status;
1159 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1162 return I40E_ERR_PARAM;
1164 i40e_fill_default_direct_cmd_desc(&desc,
1165 i40e_aqc_opc_get_phy_abilities);
1167 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1168 if (abilities_size > I40E_AQ_LARGE_BUF)
1169 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1171 if (qualified_modules)
1172 desc.params.external.param0 |=
1173 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1176 desc.params.external.param0 |=
1177 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1179 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1182 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1183 status = I40E_ERR_UNKNOWN_PHY;
1189 * i40e_aq_set_phy_config
1190 * @hw: pointer to the hw struct
1191 * @config: structure with PHY configuration to be set
1192 * @cmd_details: pointer to command details structure or NULL
1194 * Set the various PHY configuration parameters
1195 * supported on the Port.One or more of the Set PHY config parameters may be
1196 * ignored in an MFP mode as the PF may not have the privilege to set some
1197 * of the PHY Config parameters. This status will be indicated by the
1200 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1201 struct i40e_aq_set_phy_config *config,
1202 struct i40e_asq_cmd_details *cmd_details)
1204 struct i40e_aq_desc desc;
1205 struct i40e_aq_set_phy_config *cmd =
1206 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1207 enum i40e_status_code status;
1210 return I40E_ERR_PARAM;
1212 i40e_fill_default_direct_cmd_desc(&desc,
1213 i40e_aqc_opc_set_phy_config);
1217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1224 * @hw: pointer to the hw struct
1226 * Set the requested flow control mode using set_phy_config.
1228 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1229 bool atomic_restart)
1231 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1232 struct i40e_aq_get_phy_abilities_resp abilities;
1233 struct i40e_aq_set_phy_config config;
1234 enum i40e_status_code status;
1235 u8 pause_mask = 0x0;
1241 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1242 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1244 case I40E_FC_RX_PAUSE:
1245 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1247 case I40E_FC_TX_PAUSE:
1248 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1254 /* Get the current phy config */
1255 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1258 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET1;
1262 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1263 /* clear the old pause settings */
1264 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1265 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1266 /* set the new abilities */
1267 config.abilities |= pause_mask;
1268 /* If the abilities have changed, then set the new config */
1269 if (config.abilities != abilities.abilities) {
1270 /* Auto restart link so settings take effect */
1272 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1273 /* Copy over all the old settings */
1274 config.phy_type = abilities.phy_type;
1275 config.link_speed = abilities.link_speed;
1276 config.eee_capability = abilities.eee_capability;
1277 config.eeer = abilities.eeer_val;
1278 config.low_power_ctrl = abilities.d3_lpan;
1279 status = i40e_aq_set_phy_config(hw, &config, NULL);
1282 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1284 /* Get the abilities to set hw->fc.current_mode correctly */
1285 status = i40e_aq_get_phy_capabilities(hw, false, false,
1288 /* Wait a little bit and try once more */
1289 i40e_msec_delay(1000);
1290 status = i40e_aq_get_phy_capabilities(hw, false, false,
1294 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET2;
1298 /* Copy the what was returned from get capabilities into fc */
1299 if ((abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX) &&
1300 (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX))
1301 hw->fc.current_mode = I40E_FC_FULL;
1302 else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX)
1303 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1304 else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX)
1305 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1307 hw->fc.current_mode = I40E_FC_NONE;
1313 * i40e_aq_set_mac_config
1314 * @hw: pointer to the hw struct
1315 * @max_frame_size: Maximum Frame Size to be supported by the port
1316 * @crc_en: Tell HW to append a CRC to outgoing frames
1317 * @pacing: Pacing configurations
1318 * @cmd_details: pointer to command details structure or NULL
1320 * Configure MAC settings for frame size, jumbo frame support and the
1321 * addition of a CRC by the hardware.
1323 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1325 bool crc_en, u16 pacing,
1326 struct i40e_asq_cmd_details *cmd_details)
1328 struct i40e_aq_desc desc;
1329 struct i40e_aq_set_mac_config *cmd =
1330 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1331 enum i40e_status_code status;
1333 if (max_frame_size == 0)
1334 return I40E_ERR_PARAM;
1336 i40e_fill_default_direct_cmd_desc(&desc,
1337 i40e_aqc_opc_set_mac_config);
1339 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1340 cmd->params = ((u8)pacing & 0x0F) << 3;
1342 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1350 * i40e_aq_clear_pxe_mode
1351 * @hw: pointer to the hw struct
1352 * @cmd_details: pointer to command details structure or NULL
1354 * Tell the firmware that the driver is taking over from PXE
1356 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1357 struct i40e_asq_cmd_details *cmd_details)
1359 enum i40e_status_code status;
1360 struct i40e_aq_desc desc;
1361 struct i40e_aqc_clear_pxe *cmd =
1362 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1364 i40e_fill_default_direct_cmd_desc(&desc,
1365 i40e_aqc_opc_clear_pxe_mode);
1369 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1371 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1377 * i40e_aq_set_link_restart_an
1378 * @hw: pointer to the hw struct
1379 * @enable_link: if true: enable link, if false: disable link
1380 * @cmd_details: pointer to command details structure or NULL
1382 * Sets up the link and restarts the Auto-Negotiation over the link.
1384 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1385 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1387 struct i40e_aq_desc desc;
1388 struct i40e_aqc_set_link_restart_an *cmd =
1389 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1390 enum i40e_status_code status;
1392 i40e_fill_default_direct_cmd_desc(&desc,
1393 i40e_aqc_opc_set_link_restart_an);
1395 cmd->command = I40E_AQ_PHY_RESTART_AN;
1397 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1399 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1401 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1407 * i40e_aq_get_link_info
1408 * @hw: pointer to the hw struct
1409 * @enable_lse: enable/disable LinkStatusEvent reporting
1410 * @link: pointer to link status structure - optional
1411 * @cmd_details: pointer to command details structure or NULL
1413 * Returns the link status of the adapter.
1415 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1416 bool enable_lse, struct i40e_link_status *link,
1417 struct i40e_asq_cmd_details *cmd_details)
1419 struct i40e_aq_desc desc;
1420 struct i40e_aqc_get_link_status *resp =
1421 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1422 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1423 enum i40e_status_code status;
1424 bool tx_pause, rx_pause;
1427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1430 command_flags = I40E_AQ_LSE_ENABLE;
1432 command_flags = I40E_AQ_LSE_DISABLE;
1433 resp->command_flags = CPU_TO_LE16(command_flags);
1435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1437 if (status != I40E_SUCCESS)
1438 goto aq_get_link_info_exit;
1440 /* save off old link status information */
1441 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1442 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1444 /* update link status */
1445 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1446 hw->phy.media_type = i40e_get_media_type(hw);
1447 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1448 hw_link_info->link_info = resp->link_info;
1449 hw_link_info->an_info = resp->an_info;
1450 hw_link_info->ext_info = resp->ext_info;
1451 hw_link_info->loopback = resp->loopback;
1452 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1453 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1455 /* update fc info */
1456 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1457 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1458 if (tx_pause & rx_pause)
1459 hw->fc.current_mode = I40E_FC_FULL;
1461 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1463 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1465 hw->fc.current_mode = I40E_FC_NONE;
1467 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1468 hw_link_info->crc_enable = true;
1470 hw_link_info->crc_enable = false;
1472 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1473 hw_link_info->lse_enable = true;
1475 hw_link_info->lse_enable = false;
1477 /* save link status information */
1479 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1480 I40E_NONDMA_TO_NONDMA);
1482 /* flag cleared so helper functions don't call AQ again */
1483 hw->phy.get_link_info = false;
1485 aq_get_link_info_exit:
1490 * i40e_update_link_info
1491 * @hw: pointer to the hw struct
1492 * @enable_lse: enable/disable LinkStatusEvent reporting
1494 * Returns the link status of the adapter
1496 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1499 struct i40e_aq_get_phy_abilities_resp abilities;
1500 enum i40e_status_code status;
1502 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1506 status = i40e_aq_get_phy_capabilities(hw, false, false,
1511 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1512 hw->phy.link_info.an_enabled = true;
1514 hw->phy.link_info.an_enabled = false;
1520 * i40e_aq_set_phy_int_mask
1521 * @hw: pointer to the hw struct
1522 * @mask: interrupt mask to be set
1523 * @cmd_details: pointer to command details structure or NULL
1525 * Set link interrupt mask.
1527 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1529 struct i40e_asq_cmd_details *cmd_details)
1531 struct i40e_aq_desc desc;
1532 struct i40e_aqc_set_phy_int_mask *cmd =
1533 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1534 enum i40e_status_code status;
1536 i40e_fill_default_direct_cmd_desc(&desc,
1537 i40e_aqc_opc_set_phy_int_mask);
1539 cmd->event_mask = CPU_TO_LE16(mask);
1541 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1547 * i40e_aq_get_local_advt_reg
1548 * @hw: pointer to the hw struct
1549 * @advt_reg: local AN advertisement register value
1550 * @cmd_details: pointer to command details structure or NULL
1552 * Get the Local AN advertisement register value.
1554 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1556 struct i40e_asq_cmd_details *cmd_details)
1558 struct i40e_aq_desc desc;
1559 struct i40e_aqc_an_advt_reg *resp =
1560 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1561 enum i40e_status_code status;
1563 i40e_fill_default_direct_cmd_desc(&desc,
1564 i40e_aqc_opc_get_local_advt_reg);
1566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1568 if (status != I40E_SUCCESS)
1569 goto aq_get_local_advt_reg_exit;
1571 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1572 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1574 aq_get_local_advt_reg_exit:
1579 * i40e_aq_set_local_advt_reg
1580 * @hw: pointer to the hw struct
1581 * @advt_reg: local AN advertisement register value
1582 * @cmd_details: pointer to command details structure or NULL
1584 * Get the Local AN advertisement register value.
1586 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1588 struct i40e_asq_cmd_details *cmd_details)
1590 struct i40e_aq_desc desc;
1591 struct i40e_aqc_an_advt_reg *cmd =
1592 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1593 enum i40e_status_code status;
1595 i40e_fill_default_direct_cmd_desc(&desc,
1596 i40e_aqc_opc_get_local_advt_reg);
1598 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1599 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1607 * i40e_aq_get_partner_advt
1608 * @hw: pointer to the hw struct
1609 * @advt_reg: AN partner advertisement register value
1610 * @cmd_details: pointer to command details structure or NULL
1612 * Get the link partner AN advertisement register value.
1614 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1616 struct i40e_asq_cmd_details *cmd_details)
1618 struct i40e_aq_desc desc;
1619 struct i40e_aqc_an_advt_reg *resp =
1620 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1621 enum i40e_status_code status;
1623 i40e_fill_default_direct_cmd_desc(&desc,
1624 i40e_aqc_opc_get_partner_advt);
1626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1628 if (status != I40E_SUCCESS)
1629 goto aq_get_partner_advt_exit;
1631 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1632 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1634 aq_get_partner_advt_exit:
1639 * i40e_aq_set_lb_modes
1640 * @hw: pointer to the hw struct
1641 * @lb_modes: loopback mode to be set
1642 * @cmd_details: pointer to command details structure or NULL
1644 * Sets loopback modes.
1646 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1648 struct i40e_asq_cmd_details *cmd_details)
1650 struct i40e_aq_desc desc;
1651 struct i40e_aqc_set_lb_mode *cmd =
1652 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1653 enum i40e_status_code status;
1655 i40e_fill_default_direct_cmd_desc(&desc,
1656 i40e_aqc_opc_set_lb_modes);
1658 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1666 * i40e_aq_set_phy_debug
1667 * @hw: pointer to the hw struct
1668 * @cmd_flags: debug command flags
1669 * @cmd_details: pointer to command details structure or NULL
1671 * Reset the external PHY.
1673 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1674 struct i40e_asq_cmd_details *cmd_details)
1676 struct i40e_aq_desc desc;
1677 struct i40e_aqc_set_phy_debug *cmd =
1678 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1679 enum i40e_status_code status;
1681 i40e_fill_default_direct_cmd_desc(&desc,
1682 i40e_aqc_opc_set_phy_debug);
1684 cmd->command_flags = cmd_flags;
1686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1693 * @hw: pointer to the hw struct
1694 * @vsi_ctx: pointer to a vsi context struct
1695 * @cmd_details: pointer to command details structure or NULL
1697 * Add a VSI context to the hardware.
1699 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1700 struct i40e_vsi_context *vsi_ctx,
1701 struct i40e_asq_cmd_details *cmd_details)
1703 struct i40e_aq_desc desc;
1704 struct i40e_aqc_add_get_update_vsi *cmd =
1705 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1706 struct i40e_aqc_add_get_update_vsi_completion *resp =
1707 (struct i40e_aqc_add_get_update_vsi_completion *)
1709 enum i40e_status_code status;
1711 i40e_fill_default_direct_cmd_desc(&desc,
1712 i40e_aqc_opc_add_vsi);
1714 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1715 cmd->connection_type = vsi_ctx->connection_type;
1716 cmd->vf_id = vsi_ctx->vf_num;
1717 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1719 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1721 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1722 sizeof(vsi_ctx->info), cmd_details);
1724 if (status != I40E_SUCCESS)
1725 goto aq_add_vsi_exit;
1727 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1728 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1729 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1730 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1737 * i40e_aq_set_default_vsi
1738 * @hw: pointer to the hw struct
1740 * @cmd_details: pointer to command details structure or NULL
1742 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1744 struct i40e_asq_cmd_details *cmd_details)
1746 struct i40e_aq_desc desc;
1747 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1748 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1750 enum i40e_status_code status;
1752 i40e_fill_default_direct_cmd_desc(&desc,
1753 i40e_aqc_opc_set_vsi_promiscuous_modes);
1755 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1756 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1757 cmd->seid = CPU_TO_LE16(seid);
1759 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1765 * i40e_aq_set_vsi_unicast_promiscuous
1766 * @hw: pointer to the hw struct
1768 * @set: set unicast promiscuous enable/disable
1769 * @cmd_details: pointer to command details structure or NULL
1771 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1773 struct i40e_asq_cmd_details *cmd_details)
1775 struct i40e_aq_desc desc;
1776 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1777 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1778 enum i40e_status_code status;
1781 i40e_fill_default_direct_cmd_desc(&desc,
1782 i40e_aqc_opc_set_vsi_promiscuous_modes);
1785 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1787 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1789 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1791 cmd->seid = CPU_TO_LE16(seid);
1792 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1798 * i40e_aq_set_vsi_multicast_promiscuous
1799 * @hw: pointer to the hw struct
1801 * @set: set multicast promiscuous enable/disable
1802 * @cmd_details: pointer to command details structure or NULL
1804 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1805 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1807 struct i40e_aq_desc desc;
1808 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1809 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1810 enum i40e_status_code status;
1813 i40e_fill_default_direct_cmd_desc(&desc,
1814 i40e_aqc_opc_set_vsi_promiscuous_modes);
1817 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1819 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1821 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1823 cmd->seid = CPU_TO_LE16(seid);
1824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1830 * i40e_aq_set_vsi_broadcast
1831 * @hw: pointer to the hw struct
1833 * @set_filter: true to set filter, false to clear filter
1834 * @cmd_details: pointer to command details structure or NULL
1836 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1838 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1839 u16 seid, bool set_filter,
1840 struct i40e_asq_cmd_details *cmd_details)
1842 struct i40e_aq_desc desc;
1843 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1844 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1845 enum i40e_status_code status;
1847 i40e_fill_default_direct_cmd_desc(&desc,
1848 i40e_aqc_opc_set_vsi_promiscuous_modes);
1851 cmd->promiscuous_flags
1852 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1854 cmd->promiscuous_flags
1855 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1857 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1858 cmd->seid = CPU_TO_LE16(seid);
1859 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1865 * i40e_get_vsi_params - get VSI configuration info
1866 * @hw: pointer to the hw struct
1867 * @vsi_ctx: pointer to a vsi context struct
1868 * @cmd_details: pointer to command details structure or NULL
1870 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1871 struct i40e_vsi_context *vsi_ctx,
1872 struct i40e_asq_cmd_details *cmd_details)
1874 struct i40e_aq_desc desc;
1875 struct i40e_aqc_add_get_update_vsi *cmd =
1876 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1877 struct i40e_aqc_add_get_update_vsi_completion *resp =
1878 (struct i40e_aqc_add_get_update_vsi_completion *)
1880 enum i40e_status_code status;
1882 UNREFERENCED_1PARAMETER(cmd_details);
1883 i40e_fill_default_direct_cmd_desc(&desc,
1884 i40e_aqc_opc_get_vsi_parameters);
1886 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1888 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1890 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1891 sizeof(vsi_ctx->info), NULL);
1893 if (status != I40E_SUCCESS)
1894 goto aq_get_vsi_params_exit;
1896 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1897 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1898 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1899 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1901 aq_get_vsi_params_exit:
1906 * i40e_aq_update_vsi_params
1907 * @hw: pointer to the hw struct
1908 * @vsi_ctx: pointer to a vsi context struct
1909 * @cmd_details: pointer to command details structure or NULL
1911 * Update a VSI context.
1913 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1914 struct i40e_vsi_context *vsi_ctx,
1915 struct i40e_asq_cmd_details *cmd_details)
1917 struct i40e_aq_desc desc;
1918 struct i40e_aqc_add_get_update_vsi *cmd =
1919 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1920 enum i40e_status_code status;
1922 i40e_fill_default_direct_cmd_desc(&desc,
1923 i40e_aqc_opc_update_vsi_parameters);
1924 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1926 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1928 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1929 sizeof(vsi_ctx->info), cmd_details);
1935 * i40e_aq_get_switch_config
1936 * @hw: pointer to the hardware structure
1937 * @buf: pointer to the result buffer
1938 * @buf_size: length of input buffer
1939 * @start_seid: seid to start for the report, 0 == beginning
1940 * @cmd_details: pointer to command details structure or NULL
1942 * Fill the buf with switch configuration returned from AdminQ command
1944 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1945 struct i40e_aqc_get_switch_config_resp *buf,
1946 u16 buf_size, u16 *start_seid,
1947 struct i40e_asq_cmd_details *cmd_details)
1949 struct i40e_aq_desc desc;
1950 struct i40e_aqc_switch_seid *scfg =
1951 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1952 enum i40e_status_code status;
1954 i40e_fill_default_direct_cmd_desc(&desc,
1955 i40e_aqc_opc_get_switch_config);
1956 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1957 if (buf_size > I40E_AQ_LARGE_BUF)
1958 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1959 scfg->seid = CPU_TO_LE16(*start_seid);
1961 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1962 *start_seid = LE16_TO_CPU(scfg->seid);
1968 * i40e_aq_get_firmware_version
1969 * @hw: pointer to the hw struct
1970 * @fw_major_version: firmware major version
1971 * @fw_minor_version: firmware minor version
1972 * @api_major_version: major queue version
1973 * @api_minor_version: minor queue version
1974 * @cmd_details: pointer to command details structure or NULL
1976 * Get the firmware version from the admin queue commands
1978 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1979 u16 *fw_major_version, u16 *fw_minor_version,
1980 u16 *api_major_version, u16 *api_minor_version,
1981 struct i40e_asq_cmd_details *cmd_details)
1983 struct i40e_aq_desc desc;
1984 struct i40e_aqc_get_version *resp =
1985 (struct i40e_aqc_get_version *)&desc.params.raw;
1986 enum i40e_status_code status;
1988 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1990 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1992 if (status == I40E_SUCCESS) {
1993 if (fw_major_version != NULL)
1994 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1995 if (fw_minor_version != NULL)
1996 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1997 if (api_major_version != NULL)
1998 *api_major_version = LE16_TO_CPU(resp->api_major);
1999 if (api_minor_version != NULL)
2000 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2007 * i40e_aq_send_driver_version
2008 * @hw: pointer to the hw struct
2009 * @dv: driver's major, minor version
2010 * @cmd_details: pointer to command details structure or NULL
2012 * Send the driver version to the firmware
2014 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2015 struct i40e_driver_version *dv,
2016 struct i40e_asq_cmd_details *cmd_details)
2018 struct i40e_aq_desc desc;
2019 struct i40e_aqc_driver_version *cmd =
2020 (struct i40e_aqc_driver_version *)&desc.params.raw;
2021 enum i40e_status_code status;
2025 return I40E_ERR_PARAM;
2027 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2029 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI);
2030 cmd->driver_major_ver = dv->major_version;
2031 cmd->driver_minor_ver = dv->minor_version;
2032 cmd->driver_build_ver = dv->build_version;
2033 cmd->driver_subbuild_ver = dv->subbuild_version;
2036 while (len < sizeof(dv->driver_string) &&
2037 (dv->driver_string[len] < 0x80) &&
2038 dv->driver_string[len])
2040 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2047 * i40e_get_link_status - get status of the HW network link
2048 * @hw: pointer to the hw struct
2050 * Returns true if link is up, false if link is down.
2052 * Side effect: LinkStatusEvent reporting becomes enabled
2054 bool i40e_get_link_status(struct i40e_hw *hw)
2056 enum i40e_status_code status = I40E_SUCCESS;
2057 bool link_status = false;
2059 if (hw->phy.get_link_info) {
2060 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2062 if (status != I40E_SUCCESS)
2063 goto i40e_get_link_status_exit;
2066 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2068 i40e_get_link_status_exit:
2073 * i40e_get_link_speed
2074 * @hw: pointer to the hw struct
2076 * Returns the link speed of the adapter.
2078 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2080 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2081 enum i40e_status_code status = I40E_SUCCESS;
2083 if (hw->phy.get_link_info) {
2084 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2086 if (status != I40E_SUCCESS)
2087 goto i40e_link_speed_exit;
2090 speed = hw->phy.link_info.link_speed;
2092 i40e_link_speed_exit:
2097 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2098 * @hw: pointer to the hw struct
2099 * @uplink_seid: the MAC or other gizmo SEID
2100 * @downlink_seid: the VSI SEID
2101 * @enabled_tc: bitmap of TCs to be enabled
2102 * @default_port: true for default port VSI, false for control port
2103 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2104 * @veb_seid: pointer to where to put the resulting VEB SEID
2105 * @cmd_details: pointer to command details structure or NULL
2107 * This asks the FW to add a VEB between the uplink and downlink
2108 * elements. If the uplink SEID is 0, this will be a floating VEB.
2110 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2111 u16 downlink_seid, u8 enabled_tc,
2112 bool default_port, bool enable_l2_filtering,
2114 struct i40e_asq_cmd_details *cmd_details)
2116 struct i40e_aq_desc desc;
2117 struct i40e_aqc_add_veb *cmd =
2118 (struct i40e_aqc_add_veb *)&desc.params.raw;
2119 struct i40e_aqc_add_veb_completion *resp =
2120 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2121 enum i40e_status_code status;
2124 /* SEIDs need to either both be set or both be 0 for floating VEB */
2125 if (!!uplink_seid != !!downlink_seid)
2126 return I40E_ERR_PARAM;
2128 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2130 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2131 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2132 cmd->enable_tcs = enabled_tc;
2134 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2136 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2138 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2140 if (enable_l2_filtering)
2141 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2143 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2145 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2147 if (!status && veb_seid)
2148 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2154 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2155 * @hw: pointer to the hw struct
2156 * @veb_seid: the SEID of the VEB to query
2157 * @switch_id: the uplink switch id
2158 * @floating: set to true if the VEB is floating
2159 * @statistic_index: index of the stats counter block for this VEB
2160 * @vebs_used: number of VEB's used by function
2161 * @vebs_free: total VEB's not reserved by any function
2162 * @cmd_details: pointer to command details structure or NULL
2164 * This retrieves the parameters for a particular VEB, specified by
2165 * uplink_seid, and returns them to the caller.
2167 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2168 u16 veb_seid, u16 *switch_id,
2169 bool *floating, u16 *statistic_index,
2170 u16 *vebs_used, u16 *vebs_free,
2171 struct i40e_asq_cmd_details *cmd_details)
2173 struct i40e_aq_desc desc;
2174 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2175 (struct i40e_aqc_get_veb_parameters_completion *)
2177 enum i40e_status_code status;
2180 return I40E_ERR_PARAM;
2182 i40e_fill_default_direct_cmd_desc(&desc,
2183 i40e_aqc_opc_get_veb_parameters);
2184 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2191 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2192 if (statistic_index)
2193 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2195 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2197 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2199 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2200 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2211 * i40e_aq_add_macvlan
2212 * @hw: pointer to the hw struct
2213 * @seid: VSI for the mac address
2214 * @mv_list: list of macvlans to be added
2215 * @count: length of the list
2216 * @cmd_details: pointer to command details structure or NULL
2218 * Add MAC/VLAN addresses to the HW filtering
2220 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2221 struct i40e_aqc_add_macvlan_element_data *mv_list,
2222 u16 count, struct i40e_asq_cmd_details *cmd_details)
2224 struct i40e_aq_desc desc;
2225 struct i40e_aqc_macvlan *cmd =
2226 (struct i40e_aqc_macvlan *)&desc.params.raw;
2227 enum i40e_status_code status;
2230 if (count == 0 || !mv_list || !hw)
2231 return I40E_ERR_PARAM;
2233 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2235 /* prep the rest of the request */
2236 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2237 cmd->num_addresses = CPU_TO_LE16(count);
2238 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2242 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2243 if (buf_size > I40E_AQ_LARGE_BUF)
2244 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2246 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2253 * i40e_aq_remove_macvlan
2254 * @hw: pointer to the hw struct
2255 * @seid: VSI for the mac address
2256 * @mv_list: list of macvlans to be removed
2257 * @count: length of the list
2258 * @cmd_details: pointer to command details structure or NULL
2260 * Remove MAC/VLAN addresses from the HW filtering
2262 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2263 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2264 u16 count, struct i40e_asq_cmd_details *cmd_details)
2266 struct i40e_aq_desc desc;
2267 struct i40e_aqc_macvlan *cmd =
2268 (struct i40e_aqc_macvlan *)&desc.params.raw;
2269 enum i40e_status_code status;
2272 if (count == 0 || !mv_list || !hw)
2273 return I40E_ERR_PARAM;
2275 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2277 /* prep the rest of the request */
2278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2279 cmd->num_addresses = CPU_TO_LE16(count);
2280 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2284 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2285 if (buf_size > I40E_AQ_LARGE_BUF)
2286 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2288 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2295 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2296 * @hw: pointer to the hw struct
2297 * @seid: VSI for the vlan filters
2298 * @v_list: list of vlan filters to be added
2299 * @count: length of the list
2300 * @cmd_details: pointer to command details structure or NULL
2302 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2303 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2304 u8 count, struct i40e_asq_cmd_details *cmd_details)
2306 struct i40e_aq_desc desc;
2307 struct i40e_aqc_macvlan *cmd =
2308 (struct i40e_aqc_macvlan *)&desc.params.raw;
2309 enum i40e_status_code status;
2312 if (count == 0 || !v_list || !hw)
2313 return I40E_ERR_PARAM;
2315 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2317 /* prep the rest of the request */
2318 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2319 cmd->num_addresses = CPU_TO_LE16(count);
2320 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2324 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2325 if (buf_size > I40E_AQ_LARGE_BUF)
2326 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2328 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2335 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2336 * @hw: pointer to the hw struct
2337 * @seid: VSI for the vlan filters
2338 * @v_list: list of macvlans to be removed
2339 * @count: length of the list
2340 * @cmd_details: pointer to command details structure or NULL
2342 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2343 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2344 u8 count, struct i40e_asq_cmd_details *cmd_details)
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_macvlan *cmd =
2348 (struct i40e_aqc_macvlan *)&desc.params.raw;
2349 enum i40e_status_code status;
2352 if (count == 0 || !v_list || !hw)
2353 return I40E_ERR_PARAM;
2355 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2357 /* prep the rest of the request */
2358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2359 cmd->num_addresses = CPU_TO_LE16(count);
2360 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2364 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2365 if (buf_size > I40E_AQ_LARGE_BUF)
2366 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2368 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2375 * i40e_aq_send_msg_to_vf
2376 * @hw: pointer to the hardware structure
2377 * @vfid: vf id to send msg
2378 * @v_opcode: opcodes for VF-PF communication
2379 * @v_retval: return error code
2380 * @msg: pointer to the msg buffer
2381 * @msglen: msg length
2382 * @cmd_details: pointer to command details
2386 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2387 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2388 struct i40e_asq_cmd_details *cmd_details)
2390 struct i40e_aq_desc desc;
2391 struct i40e_aqc_pf_vf_message *cmd =
2392 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2393 enum i40e_status_code status;
2395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2396 cmd->id = CPU_TO_LE32(vfid);
2397 desc.cookie_high = CPU_TO_LE32(v_opcode);
2398 desc.cookie_low = CPU_TO_LE32(v_retval);
2399 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2401 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2403 if (msglen > I40E_AQ_LARGE_BUF)
2404 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2405 desc.datalen = CPU_TO_LE16(msglen);
2407 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2413 * i40e_aq_get_hmc_resource_profile
2414 * @hw: pointer to the hw struct
2415 * @profile: type of profile the HMC is to be set as
2416 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2417 * @cmd_details: pointer to command details structure or NULL
2419 * query the HMC profile of the device.
2421 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2422 enum i40e_aq_hmc_profile *profile,
2423 u8 *pe_vf_enabled_count,
2424 struct i40e_asq_cmd_details *cmd_details)
2426 struct i40e_aq_desc desc;
2427 struct i40e_aq_get_set_hmc_resource_profile *resp =
2428 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2429 enum i40e_status_code status;
2431 i40e_fill_default_direct_cmd_desc(&desc,
2432 i40e_aqc_opc_query_hmc_resource_profile);
2433 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2435 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2436 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2437 *pe_vf_enabled_count = resp->pe_vf_enabled &
2438 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2444 * i40e_aq_set_hmc_resource_profile
2445 * @hw: pointer to the hw struct
2446 * @profile: type of profile the HMC is to be set as
2447 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2448 * @cmd_details: pointer to command details structure or NULL
2450 * set the HMC profile of the device.
2452 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2453 enum i40e_aq_hmc_profile profile,
2454 u8 pe_vf_enabled_count,
2455 struct i40e_asq_cmd_details *cmd_details)
2457 struct i40e_aq_desc desc;
2458 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2459 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2460 enum i40e_status_code status;
2462 i40e_fill_default_direct_cmd_desc(&desc,
2463 i40e_aqc_opc_set_hmc_resource_profile);
2465 cmd->pm_profile = (u8)profile;
2466 cmd->pe_vf_enabled = pe_vf_enabled_count;
2468 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2474 * i40e_aq_request_resource
2475 * @hw: pointer to the hw struct
2476 * @resource: resource id
2477 * @access: access type
2478 * @sdp_number: resource number
2479 * @timeout: the maximum time in ms that the driver may hold the resource
2480 * @cmd_details: pointer to command details structure or NULL
2482 * requests common resource using the admin queue commands
2484 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2485 enum i40e_aq_resources_ids resource,
2486 enum i40e_aq_resource_access_type access,
2487 u8 sdp_number, u64 *timeout,
2488 struct i40e_asq_cmd_details *cmd_details)
2490 struct i40e_aq_desc desc;
2491 struct i40e_aqc_request_resource *cmd_resp =
2492 (struct i40e_aqc_request_resource *)&desc.params.raw;
2493 enum i40e_status_code status;
2495 DEBUGFUNC("i40e_aq_request_resource");
2497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2499 cmd_resp->resource_id = CPU_TO_LE16(resource);
2500 cmd_resp->access_type = CPU_TO_LE16(access);
2501 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2503 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2504 /* The completion specifies the maximum time in ms that the driver
2505 * may hold the resource in the Timeout field.
2506 * If the resource is held by someone else, the command completes with
2507 * busy return value and the timeout field indicates the maximum time
2508 * the current owner of the resource has to free it.
2510 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2511 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2517 * i40e_aq_release_resource
2518 * @hw: pointer to the hw struct
2519 * @resource: resource id
2520 * @sdp_number: resource number
2521 * @cmd_details: pointer to command details structure or NULL
2523 * release common resource using the admin queue commands
2525 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2526 enum i40e_aq_resources_ids resource,
2528 struct i40e_asq_cmd_details *cmd_details)
2530 struct i40e_aq_desc desc;
2531 struct i40e_aqc_request_resource *cmd =
2532 (struct i40e_aqc_request_resource *)&desc.params.raw;
2533 enum i40e_status_code status;
2535 DEBUGFUNC("i40e_aq_release_resource");
2537 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2539 cmd->resource_id = CPU_TO_LE16(resource);
2540 cmd->resource_number = CPU_TO_LE32(sdp_number);
2542 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2549 * @hw: pointer to the hw struct
2550 * @module_pointer: module pointer location in words from the NVM beginning
2551 * @offset: byte offset from the module beginning
2552 * @length: length of the section to be read (in bytes from the offset)
2553 * @data: command buffer (size [bytes] = length)
2554 * @last_command: tells if this is the last command in a series
2555 * @cmd_details: pointer to command details structure or NULL
2557 * Read the NVM using the admin queue commands
2559 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2560 u32 offset, u16 length, void *data,
2562 struct i40e_asq_cmd_details *cmd_details)
2564 struct i40e_aq_desc desc;
2565 struct i40e_aqc_nvm_update *cmd =
2566 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2567 enum i40e_status_code status;
2569 DEBUGFUNC("i40e_aq_read_nvm");
2571 /* In offset the highest byte must be zeroed. */
2572 if (offset & 0xFF000000) {
2573 status = I40E_ERR_PARAM;
2574 goto i40e_aq_read_nvm_exit;
2577 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2579 /* If this is the last command in a series, set the proper flag. */
2581 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2582 cmd->module_pointer = module_pointer;
2583 cmd->offset = CPU_TO_LE32(offset);
2584 cmd->length = CPU_TO_LE16(length);
2586 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2587 if (length > I40E_AQ_LARGE_BUF)
2588 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2590 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2592 i40e_aq_read_nvm_exit:
2598 * @hw: pointer to the hw struct
2599 * @module_pointer: module pointer location in words from the NVM beginning
2600 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2601 * @length: length of the section to be erased (expressed in 4 KB)
2602 * @last_command: tells if this is the last command in a series
2603 * @cmd_details: pointer to command details structure or NULL
2605 * Erase the NVM sector using the admin queue commands
2607 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2608 u32 offset, u16 length, bool last_command,
2609 struct i40e_asq_cmd_details *cmd_details)
2611 struct i40e_aq_desc desc;
2612 struct i40e_aqc_nvm_update *cmd =
2613 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2614 enum i40e_status_code status;
2616 DEBUGFUNC("i40e_aq_erase_nvm");
2618 /* In offset the highest byte must be zeroed. */
2619 if (offset & 0xFF000000) {
2620 status = I40E_ERR_PARAM;
2621 goto i40e_aq_erase_nvm_exit;
2624 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2626 /* If this is the last command in a series, set the proper flag. */
2628 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2629 cmd->module_pointer = module_pointer;
2630 cmd->offset = CPU_TO_LE32(offset);
2631 cmd->length = CPU_TO_LE16(length);
2633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2635 i40e_aq_erase_nvm_exit:
2639 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2640 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2641 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2642 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2643 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2644 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2645 #define I40E_DEV_FUNC_CAP_VF 0x13
2646 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2647 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2648 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2649 #define I40E_DEV_FUNC_CAP_VSI 0x17
2650 #define I40E_DEV_FUNC_CAP_DCB 0x18
2651 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2652 #define I40E_DEV_FUNC_CAP_RSS 0x40
2653 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2654 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2655 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2656 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2657 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2658 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2659 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2660 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2661 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2662 #define I40E_DEV_FUNC_CAP_LED 0x61
2663 #define I40E_DEV_FUNC_CAP_SDP 0x62
2664 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2667 * i40e_parse_discover_capabilities
2668 * @hw: pointer to the hw struct
2669 * @buff: pointer to a buffer containing device/function capability records
2670 * @cap_count: number of capability records in the list
2671 * @list_type_opc: type of capabilities list to parse
2673 * Parse the device/function capabilities list.
2675 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2677 enum i40e_admin_queue_opc list_type_opc)
2679 struct i40e_aqc_list_capabilities_element_resp *cap;
2680 u32 number, logical_id, phys_id;
2681 struct i40e_hw_capabilities *p;
2685 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2687 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2688 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2689 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2690 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2694 for (i = 0; i < cap_count; i++, cap++) {
2695 id = LE16_TO_CPU(cap->id);
2696 number = LE32_TO_CPU(cap->number);
2697 logical_id = LE32_TO_CPU(cap->logical_id);
2698 phys_id = LE32_TO_CPU(cap->phys_id);
2701 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2702 p->switch_mode = number;
2704 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2705 p->management_mode = number;
2707 case I40E_DEV_FUNC_CAP_NPAR:
2708 p->npar_enable = number;
2710 case I40E_DEV_FUNC_CAP_OS2BMC:
2713 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2714 p->valid_functions = number;
2716 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2718 p->sr_iov_1_1 = true;
2720 case I40E_DEV_FUNC_CAP_VF:
2721 p->num_vfs = number;
2722 p->vf_base_id = logical_id;
2724 case I40E_DEV_FUNC_CAP_VMDQ:
2728 case I40E_DEV_FUNC_CAP_802_1_QBG:
2730 p->evb_802_1_qbg = true;
2732 case I40E_DEV_FUNC_CAP_802_1_QBH:
2734 p->evb_802_1_qbh = true;
2736 case I40E_DEV_FUNC_CAP_VSI:
2737 p->num_vsis = number;
2739 case I40E_DEV_FUNC_CAP_DCB:
2742 p->enabled_tcmap = logical_id;
2746 case I40E_DEV_FUNC_CAP_FCOE:
2750 case I40E_DEV_FUNC_CAP_RSS:
2752 p->rss_table_size = number;
2753 p->rss_table_entry_width = logical_id;
2755 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2756 p->num_rx_qp = number;
2757 p->base_queue = phys_id;
2759 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2760 p->num_tx_qp = number;
2761 p->base_queue = phys_id;
2763 case I40E_DEV_FUNC_CAP_MSIX:
2764 p->num_msix_vectors = number;
2766 case I40E_DEV_FUNC_CAP_MSIX_VF:
2767 p->num_msix_vectors_vf = number;
2769 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2771 p->mfp_mode_1 = true;
2773 case I40E_DEV_FUNC_CAP_CEM:
2777 case I40E_DEV_FUNC_CAP_IWARP:
2781 case I40E_DEV_FUNC_CAP_LED:
2782 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2783 p->led[phys_id] = true;
2785 case I40E_DEV_FUNC_CAP_SDP:
2786 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2787 p->sdp[phys_id] = true;
2789 case I40E_DEV_FUNC_CAP_MDIO:
2791 p->mdio_port_num = phys_id;
2792 p->mdio_port_mode = logical_id;
2795 case I40E_DEV_FUNC_CAP_IEEE_1588:
2797 p->ieee_1588 = true;
2799 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2801 p->fd_filters_guaranteed = number;
2802 p->fd_filters_best_effort = logical_id;
2809 /* Software override ensuring FCoE is disabled if npar or mfp
2810 * mode because it is not supported in these modes.
2812 if (p->npar_enable || p->mfp_mode_1)
2815 /* additional HW specific goodies that might
2816 * someday be HW version specific
2818 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2822 * i40e_aq_discover_capabilities
2823 * @hw: pointer to the hw struct
2824 * @buff: a virtual buffer to hold the capabilities
2825 * @buff_size: Size of the virtual buffer
2826 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2827 * @list_type_opc: capabilities type to discover - pass in the command opcode
2828 * @cmd_details: pointer to command details structure or NULL
2830 * Get the device capabilities descriptions from the firmware
2832 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2833 void *buff, u16 buff_size, u16 *data_size,
2834 enum i40e_admin_queue_opc list_type_opc,
2835 struct i40e_asq_cmd_details *cmd_details)
2837 struct i40e_aqc_list_capabilites *cmd;
2838 struct i40e_aq_desc desc;
2839 enum i40e_status_code status = I40E_SUCCESS;
2841 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2843 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2844 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2845 status = I40E_ERR_PARAM;
2849 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2851 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2852 if (buff_size > I40E_AQ_LARGE_BUF)
2853 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2855 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2856 *data_size = LE16_TO_CPU(desc.datalen);
2861 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2869 * i40e_aq_update_nvm
2870 * @hw: pointer to the hw struct
2871 * @module_pointer: module pointer location in words from the NVM beginning
2872 * @offset: byte offset from the module beginning
2873 * @length: length of the section to be written (in bytes from the offset)
2874 * @data: command buffer (size [bytes] = length)
2875 * @last_command: tells if this is the last command in a series
2876 * @cmd_details: pointer to command details structure or NULL
2878 * Update the NVM using the admin queue commands
2880 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2881 u32 offset, u16 length, void *data,
2883 struct i40e_asq_cmd_details *cmd_details)
2885 struct i40e_aq_desc desc;
2886 struct i40e_aqc_nvm_update *cmd =
2887 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2888 enum i40e_status_code status;
2890 DEBUGFUNC("i40e_aq_update_nvm");
2892 /* In offset the highest byte must be zeroed. */
2893 if (offset & 0xFF000000) {
2894 status = I40E_ERR_PARAM;
2895 goto i40e_aq_update_nvm_exit;
2898 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2900 /* If this is the last command in a series, set the proper flag. */
2902 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2903 cmd->module_pointer = module_pointer;
2904 cmd->offset = CPU_TO_LE32(offset);
2905 cmd->length = CPU_TO_LE16(length);
2907 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2908 if (length > I40E_AQ_LARGE_BUF)
2909 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2911 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2913 i40e_aq_update_nvm_exit:
2918 * i40e_aq_get_lldp_mib
2919 * @hw: pointer to the hw struct
2920 * @bridge_type: type of bridge requested
2921 * @mib_type: Local, Remote or both Local and Remote MIBs
2922 * @buff: pointer to a user supplied buffer to store the MIB block
2923 * @buff_size: size of the buffer (in bytes)
2924 * @local_len : length of the returned Local LLDP MIB
2925 * @remote_len: length of the returned Remote LLDP MIB
2926 * @cmd_details: pointer to command details structure or NULL
2928 * Requests the complete LLDP MIB (entire packet).
2930 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2931 u8 mib_type, void *buff, u16 buff_size,
2932 u16 *local_len, u16 *remote_len,
2933 struct i40e_asq_cmd_details *cmd_details)
2935 struct i40e_aq_desc desc;
2936 struct i40e_aqc_lldp_get_mib *cmd =
2937 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2938 struct i40e_aqc_lldp_get_mib *resp =
2939 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2940 enum i40e_status_code status;
2942 if (buff_size == 0 || !buff)
2943 return I40E_ERR_PARAM;
2945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2946 /* Indirect Command */
2947 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2949 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2950 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2951 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2953 desc.datalen = CPU_TO_LE16(buff_size);
2955 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2956 if (buff_size > I40E_AQ_LARGE_BUF)
2957 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2959 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2961 if (local_len != NULL)
2962 *local_len = LE16_TO_CPU(resp->local_len);
2963 if (remote_len != NULL)
2964 *remote_len = LE16_TO_CPU(resp->remote_len);
2971 * i40e_aq_cfg_lldp_mib_change_event
2972 * @hw: pointer to the hw struct
2973 * @enable_update: Enable or Disable event posting
2974 * @cmd_details: pointer to command details structure or NULL
2976 * Enable or Disable posting of an event on ARQ when LLDP MIB
2977 * associated with the interface changes
2979 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2981 struct i40e_asq_cmd_details *cmd_details)
2983 struct i40e_aq_desc desc;
2984 struct i40e_aqc_lldp_update_mib *cmd =
2985 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2986 enum i40e_status_code status;
2988 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2991 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2993 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2999 * i40e_aq_add_lldp_tlv
3000 * @hw: pointer to the hw struct
3001 * @bridge_type: type of bridge
3002 * @buff: buffer with TLV to add
3003 * @buff_size: length of the buffer
3004 * @tlv_len: length of the TLV to be added
3005 * @mib_len: length of the LLDP MIB returned in response
3006 * @cmd_details: pointer to command details structure or NULL
3008 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3009 * it is responsibility of the caller to make sure that the TLV is not
3010 * already present in the LLDPDU.
3011 * In return firmware will write the complete LLDP MIB with the newly
3012 * added TLV in the response buffer.
3014 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3015 void *buff, u16 buff_size, u16 tlv_len,
3017 struct i40e_asq_cmd_details *cmd_details)
3019 struct i40e_aq_desc desc;
3020 struct i40e_aqc_lldp_add_tlv *cmd =
3021 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3022 enum i40e_status_code status;
3024 if (buff_size == 0 || !buff || tlv_len == 0)
3025 return I40E_ERR_PARAM;
3027 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3029 /* Indirect Command */
3030 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3031 if (buff_size > I40E_AQ_LARGE_BUF)
3032 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3033 desc.datalen = CPU_TO_LE16(buff_size);
3035 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3036 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3037 cmd->len = CPU_TO_LE16(tlv_len);
3039 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3041 if (mib_len != NULL)
3042 *mib_len = LE16_TO_CPU(desc.datalen);
3049 * i40e_aq_update_lldp_tlv
3050 * @hw: pointer to the hw struct
3051 * @bridge_type: type of bridge
3052 * @buff: buffer with TLV to update
3053 * @buff_size: size of the buffer holding original and updated TLVs
3054 * @old_len: Length of the Original TLV
3055 * @new_len: Length of the Updated TLV
3056 * @offset: offset of the updated TLV in the buff
3057 * @mib_len: length of the returned LLDP MIB
3058 * @cmd_details: pointer to command details structure or NULL
3060 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3061 * Firmware will place the complete LLDP MIB in response buffer with the
3064 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3065 u8 bridge_type, void *buff, u16 buff_size,
3066 u16 old_len, u16 new_len, u16 offset,
3068 struct i40e_asq_cmd_details *cmd_details)
3070 struct i40e_aq_desc desc;
3071 struct i40e_aqc_lldp_update_tlv *cmd =
3072 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3073 enum i40e_status_code status;
3075 if (buff_size == 0 || !buff || offset == 0 ||
3076 old_len == 0 || new_len == 0)
3077 return I40E_ERR_PARAM;
3079 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3081 /* Indirect Command */
3082 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3083 if (buff_size > I40E_AQ_LARGE_BUF)
3084 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3085 desc.datalen = CPU_TO_LE16(buff_size);
3087 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3088 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3089 cmd->old_len = CPU_TO_LE16(old_len);
3090 cmd->new_offset = CPU_TO_LE16(offset);
3091 cmd->new_len = CPU_TO_LE16(new_len);
3093 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3095 if (mib_len != NULL)
3096 *mib_len = LE16_TO_CPU(desc.datalen);
3103 * i40e_aq_delete_lldp_tlv
3104 * @hw: pointer to the hw struct
3105 * @bridge_type: type of bridge
3106 * @buff: pointer to a user supplied buffer that has the TLV
3107 * @buff_size: length of the buffer
3108 * @tlv_len: length of the TLV to be deleted
3109 * @mib_len: length of the returned LLDP MIB
3110 * @cmd_details: pointer to command details structure or NULL
3112 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3113 * The firmware places the entire LLDP MIB in the response buffer.
3115 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3116 u8 bridge_type, void *buff, u16 buff_size,
3117 u16 tlv_len, u16 *mib_len,
3118 struct i40e_asq_cmd_details *cmd_details)
3120 struct i40e_aq_desc desc;
3121 struct i40e_aqc_lldp_add_tlv *cmd =
3122 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3123 enum i40e_status_code status;
3125 if (buff_size == 0 || !buff)
3126 return I40E_ERR_PARAM;
3128 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3130 /* Indirect Command */
3131 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3132 if (buff_size > I40E_AQ_LARGE_BUF)
3133 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3134 desc.datalen = CPU_TO_LE16(buff_size);
3135 cmd->len = CPU_TO_LE16(tlv_len);
3136 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3137 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3139 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3141 if (mib_len != NULL)
3142 *mib_len = LE16_TO_CPU(desc.datalen);
3150 * @hw: pointer to the hw struct
3151 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3152 * @cmd_details: pointer to command details structure or NULL
3154 * Stop or Shutdown the embedded LLDP Agent
3156 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3157 struct i40e_asq_cmd_details *cmd_details)
3159 struct i40e_aq_desc desc;
3160 struct i40e_aqc_lldp_stop *cmd =
3161 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3162 enum i40e_status_code status;
3164 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3167 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3175 * i40e_aq_start_lldp
3176 * @hw: pointer to the hw struct
3177 * @cmd_details: pointer to command details structure or NULL
3179 * Start the embedded LLDP Agent on all ports.
3181 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3182 struct i40e_asq_cmd_details *cmd_details)
3184 struct i40e_aq_desc desc;
3185 struct i40e_aqc_lldp_start *cmd =
3186 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3187 enum i40e_status_code status;
3189 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3191 cmd->command = I40E_AQ_LLDP_AGENT_START;
3193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3199 * i40e_aq_add_udp_tunnel
3200 * @hw: pointer to the hw struct
3201 * @udp_port: the UDP port to add
3202 * @header_len: length of the tunneling header length in DWords
3203 * @protocol_index: protocol index type
3204 * @filter_index: pointer to filter index
3205 * @cmd_details: pointer to command details structure or NULL
3207 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3208 u16 udp_port, u8 protocol_index,
3210 struct i40e_asq_cmd_details *cmd_details)
3212 struct i40e_aq_desc desc;
3213 struct i40e_aqc_add_udp_tunnel *cmd =
3214 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3215 struct i40e_aqc_del_udp_tunnel_completion *resp =
3216 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3217 enum i40e_status_code status;
3219 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3221 cmd->udp_port = CPU_TO_LE16(udp_port);
3222 cmd->protocol_type = protocol_index;
3224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3227 *filter_index = resp->index;
3233 * i40e_aq_del_udp_tunnel
3234 * @hw: pointer to the hw struct
3235 * @index: filter index
3236 * @cmd_details: pointer to command details structure or NULL
3238 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3239 struct i40e_asq_cmd_details *cmd_details)
3241 struct i40e_aq_desc desc;
3242 struct i40e_aqc_remove_udp_tunnel *cmd =
3243 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3244 enum i40e_status_code status;
3246 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3250 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3256 * i40e_aq_get_switch_resource_alloc (0x0204)
3257 * @hw: pointer to the hw struct
3258 * @num_entries: pointer to u8 to store the number of resource entries returned
3259 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3260 * to store the resource information for all resource types. Each
3261 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3262 * @count: size, in bytes, of the buffer provided
3263 * @cmd_details: pointer to command details structure or NULL
3265 * Query the resources allocated to a function.
3267 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3269 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3271 struct i40e_asq_cmd_details *cmd_details)
3273 struct i40e_aq_desc desc;
3274 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3275 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3276 enum i40e_status_code status;
3278 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3280 i40e_fill_default_direct_cmd_desc(&desc,
3281 i40e_aqc_opc_get_switch_resource_alloc);
3283 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3284 if (length > I40E_AQ_LARGE_BUF)
3285 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3287 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3290 *num_entries = cmd_resp->num_entries;
3296 * i40e_aq_delete_element - Delete switch element
3297 * @hw: pointer to the hw struct
3298 * @seid: the SEID to delete from the switch
3299 * @cmd_details: pointer to command details structure or NULL
3301 * This deletes a switch element from the switch.
3303 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3304 struct i40e_asq_cmd_details *cmd_details)
3306 struct i40e_aq_desc desc;
3307 struct i40e_aqc_switch_seid *cmd =
3308 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3309 enum i40e_status_code status;
3312 return I40E_ERR_PARAM;
3314 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3316 cmd->seid = CPU_TO_LE16(seid);
3318 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3324 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3325 * @hw: pointer to the hw struct
3326 * @flags: component flags
3327 * @mac_seid: uplink seid (MAC SEID)
3328 * @vsi_seid: connected vsi seid
3329 * @ret_seid: seid of create pv component
3331 * This instantiates an i40e port virtualizer with specified flags.
3332 * Depending on specified flags the port virtualizer can act as a
3333 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3335 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3336 u16 mac_seid, u16 vsi_seid,
3339 struct i40e_aq_desc desc;
3340 struct i40e_aqc_add_update_pv *cmd =
3341 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3342 struct i40e_aqc_add_update_pv_completion *resp =
3343 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3344 enum i40e_status_code status;
3347 return I40E_ERR_PARAM;
3349 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3350 cmd->command_flags = CPU_TO_LE16(flags);
3351 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3352 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3354 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3355 if (!status && ret_seid)
3356 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3362 * i40e_aq_add_tag - Add an S/E-tag
3363 * @hw: pointer to the hw struct
3364 * @direct_to_queue: should s-tag direct flow to a specific queue
3365 * @vsi_seid: VSI SEID to use this tag
3366 * @tag: value of the tag
3367 * @queue_num: queue number, only valid is direct_to_queue is true
3368 * @tags_used: return value, number of tags in use by this PF
3369 * @tags_free: return value, number of unallocated tags
3370 * @cmd_details: pointer to command details structure or NULL
3372 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3373 * the number of tags allocated by the PF, and the number of unallocated
3376 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3377 u16 vsi_seid, u16 tag, u16 queue_num,
3378 u16 *tags_used, u16 *tags_free,
3379 struct i40e_asq_cmd_details *cmd_details)
3381 struct i40e_aq_desc desc;
3382 struct i40e_aqc_add_tag *cmd =
3383 (struct i40e_aqc_add_tag *)&desc.params.raw;
3384 struct i40e_aqc_add_remove_tag_completion *resp =
3385 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3386 enum i40e_status_code status;
3389 return I40E_ERR_PARAM;
3391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3393 cmd->seid = CPU_TO_LE16(vsi_seid);
3394 cmd->tag = CPU_TO_LE16(tag);
3395 if (direct_to_queue) {
3396 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3397 cmd->queue_number = CPU_TO_LE16(queue_num);
3400 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3403 if (tags_used != NULL)
3404 *tags_used = LE16_TO_CPU(resp->tags_used);
3405 if (tags_free != NULL)
3406 *tags_free = LE16_TO_CPU(resp->tags_free);
3413 * i40e_aq_remove_tag - Remove an S- or E-tag
3414 * @hw: pointer to the hw struct
3415 * @vsi_seid: VSI SEID this tag is associated with
3416 * @tag: value of the S-tag to delete
3417 * @tags_used: return value, number of tags in use by this PF
3418 * @tags_free: return value, number of unallocated tags
3419 * @cmd_details: pointer to command details structure or NULL
3421 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3422 * the number of tags allocated by the PF, and the number of unallocated
3425 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3426 u16 tag, u16 *tags_used, u16 *tags_free,
3427 struct i40e_asq_cmd_details *cmd_details)
3429 struct i40e_aq_desc desc;
3430 struct i40e_aqc_remove_tag *cmd =
3431 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3432 struct i40e_aqc_add_remove_tag_completion *resp =
3433 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3434 enum i40e_status_code status;
3437 return I40E_ERR_PARAM;
3439 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3441 cmd->seid = CPU_TO_LE16(vsi_seid);
3442 cmd->tag = CPU_TO_LE16(tag);
3444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3447 if (tags_used != NULL)
3448 *tags_used = LE16_TO_CPU(resp->tags_used);
3449 if (tags_free != NULL)
3450 *tags_free = LE16_TO_CPU(resp->tags_free);
3457 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3458 * @hw: pointer to the hw struct
3459 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3460 * @etag: value of E-tag to add
3461 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3462 * @buf: address of indirect buffer
3463 * @tags_used: return value, number of E-tags in use by this port
3464 * @tags_free: return value, number of unallocated M-tags
3465 * @cmd_details: pointer to command details structure or NULL
3467 * This associates a multicast E-tag to a port virtualizer. It will return
3468 * the number of tags allocated by the PF, and the number of unallocated
3471 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3472 * num_tags_in_buf long.
3474 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3475 u16 etag, u8 num_tags_in_buf, void *buf,
3476 u16 *tags_used, u16 *tags_free,
3477 struct i40e_asq_cmd_details *cmd_details)
3479 struct i40e_aq_desc desc;
3480 struct i40e_aqc_add_remove_mcast_etag *cmd =
3481 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3482 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3483 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3484 enum i40e_status_code status;
3485 u16 length = sizeof(u16) * num_tags_in_buf;
3487 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3488 return I40E_ERR_PARAM;
3490 i40e_fill_default_direct_cmd_desc(&desc,
3491 i40e_aqc_opc_add_multicast_etag);
3493 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3494 cmd->etag = CPU_TO_LE16(etag);
3495 cmd->num_unicast_etags = num_tags_in_buf;
3497 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3498 if (length > I40E_AQ_LARGE_BUF)
3499 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3501 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3504 if (tags_used != NULL)
3505 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3506 if (tags_free != NULL)
3507 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3514 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3515 * @hw: pointer to the hw struct
3516 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3517 * @etag: value of the E-tag to remove
3518 * @tags_used: return value, number of tags in use by this port
3519 * @tags_free: return value, number of unallocated tags
3520 * @cmd_details: pointer to command details structure or NULL
3522 * This deletes an E-tag from the port virtualizer. It will return
3523 * the number of tags allocated by the port, and the number of unallocated
3526 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3527 u16 etag, u16 *tags_used, u16 *tags_free,
3528 struct i40e_asq_cmd_details *cmd_details)
3530 struct i40e_aq_desc desc;
3531 struct i40e_aqc_add_remove_mcast_etag *cmd =
3532 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3533 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3534 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3535 enum i40e_status_code status;
3539 return I40E_ERR_PARAM;
3541 i40e_fill_default_direct_cmd_desc(&desc,
3542 i40e_aqc_opc_remove_multicast_etag);
3544 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3545 cmd->etag = CPU_TO_LE16(etag);
3547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3550 if (tags_used != NULL)
3551 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3552 if (tags_free != NULL)
3553 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3560 * i40e_aq_update_tag - Update an S/E-tag
3561 * @hw: pointer to the hw struct
3562 * @vsi_seid: VSI SEID using this S-tag
3563 * @old_tag: old tag value
3564 * @new_tag: new tag value
3565 * @tags_used: return value, number of tags in use by this PF
3566 * @tags_free: return value, number of unallocated tags
3567 * @cmd_details: pointer to command details structure or NULL
3569 * This updates the value of the tag currently attached to this VSI
3570 * in the switch complex. It will return the number of tags allocated
3571 * by the PF, and the number of unallocated tags available.
3573 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3574 u16 old_tag, u16 new_tag, u16 *tags_used,
3576 struct i40e_asq_cmd_details *cmd_details)
3578 struct i40e_aq_desc desc;
3579 struct i40e_aqc_update_tag *cmd =
3580 (struct i40e_aqc_update_tag *)&desc.params.raw;
3581 struct i40e_aqc_update_tag_completion *resp =
3582 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3583 enum i40e_status_code status;
3586 return I40E_ERR_PARAM;
3588 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3590 cmd->seid = CPU_TO_LE16(vsi_seid);
3591 cmd->old_tag = CPU_TO_LE16(old_tag);
3592 cmd->new_tag = CPU_TO_LE16(new_tag);
3594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3597 if (tags_used != NULL)
3598 *tags_used = LE16_TO_CPU(resp->tags_used);
3599 if (tags_free != NULL)
3600 *tags_free = LE16_TO_CPU(resp->tags_free);
3607 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3608 * @hw: pointer to the hw struct
3609 * @tcmap: TC map for request/release any ignore PFC condition
3610 * @request: request or release ignore PFC condition
3611 * @tcmap_ret: return TCs for which PFC is currently ignored
3612 * @cmd_details: pointer to command details structure or NULL
3614 * This sends out request/release to ignore PFC condition for a TC.
3615 * It will return the TCs for which PFC is currently ignored.
3617 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3618 bool request, u8 *tcmap_ret,
3619 struct i40e_asq_cmd_details *cmd_details)
3621 struct i40e_aq_desc desc;
3622 struct i40e_aqc_pfc_ignore *cmd_resp =
3623 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3624 enum i40e_status_code status;
3626 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3629 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3631 cmd_resp->tc_bitmap = tcmap;
3633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3636 if (tcmap_ret != NULL)
3637 *tcmap_ret = cmd_resp->tc_bitmap;
3644 * i40e_aq_dcb_updated - DCB Updated Command
3645 * @hw: pointer to the hw struct
3646 * @cmd_details: pointer to command details structure or NULL
3648 * When LLDP is handled in PF this command is used by the PF
3649 * to notify EMP that a DCB setting is modified.
3650 * When LLDP is handled in EMP this command is used by the PF
3651 * to notify EMP whenever one of the following parameters get
3653 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3654 * - PCIRTT in PRTDCB_GENC.PCIRTT
3655 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3656 * EMP will return when the shared RPB settings have been
3657 * recomputed and modified. The retval field in the descriptor
3658 * will be set to 0 when RPB is modified.
3660 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3661 struct i40e_asq_cmd_details *cmd_details)
3663 struct i40e_aq_desc desc;
3664 enum i40e_status_code status;
3666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3668 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3674 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3675 * @hw: pointer to the hw struct
3676 * @seid: defines the SEID of the switch for which the stats are requested
3677 * @vlan_id: the VLAN ID for which the statistics are requested
3678 * @stat_index: index of the statistics counters block assigned to this VLAN
3679 * @cmd_details: pointer to command details structure or NULL
3681 * XL710 supports 128 smonVlanStats counters.This command is used to
3682 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3685 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3686 u16 vlan_id, u16 *stat_index,
3687 struct i40e_asq_cmd_details *cmd_details)
3689 struct i40e_aq_desc desc;
3690 struct i40e_aqc_add_remove_statistics *cmd_resp =
3691 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3692 enum i40e_status_code status;
3694 if ((seid == 0) || (stat_index == NULL))
3695 return I40E_ERR_PARAM;
3697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3699 cmd_resp->seid = CPU_TO_LE16(seid);
3700 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3705 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3711 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3712 * @hw: pointer to the hw struct
3713 * @seid: defines the SEID of the switch for which the stats are requested
3714 * @vlan_id: the VLAN ID for which the statistics are requested
3715 * @stat_index: index of the statistics counters block assigned to this VLAN
3716 * @cmd_details: pointer to command details structure or NULL
3718 * XL710 supports 128 smonVlanStats counters.This command is used to
3719 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3722 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3723 u16 vlan_id, u16 stat_index,
3724 struct i40e_asq_cmd_details *cmd_details)
3726 struct i40e_aq_desc desc;
3727 struct i40e_aqc_add_remove_statistics *cmd =
3728 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3729 enum i40e_status_code status;
3732 return I40E_ERR_PARAM;
3734 i40e_fill_default_direct_cmd_desc(&desc,
3735 i40e_aqc_opc_remove_statistics);
3737 cmd->seid = CPU_TO_LE16(seid);
3738 cmd->vlan = CPU_TO_LE16(vlan_id);
3739 cmd->stat_index = CPU_TO_LE16(stat_index);
3741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3747 * i40e_aq_set_port_parameters - set physical port parameters.
3748 * @hw: pointer to the hw struct
3749 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3750 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3751 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3752 * @double_vlan: if set double VLAN is enabled
3753 * @cmd_details: pointer to command details structure or NULL
3755 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3756 u16 bad_frame_vsi, bool save_bad_pac,
3757 bool pad_short_pac, bool double_vlan,
3758 struct i40e_asq_cmd_details *cmd_details)
3760 struct i40e_aqc_set_port_parameters *cmd;
3761 enum i40e_status_code status;
3762 struct i40e_aq_desc desc;
3763 u16 command_flags = 0;
3765 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3767 i40e_fill_default_direct_cmd_desc(&desc,
3768 i40e_aqc_opc_set_port_parameters);
3770 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3772 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3774 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3776 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3777 cmd->command_flags = CPU_TO_LE16(command_flags);
3779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3785 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3786 * @hw: pointer to the hw struct
3787 * @seid: seid for the physical port/switching component/vsi
3788 * @buff: Indirect buffer to hold data parameters and response
3789 * @buff_size: Indirect buffer size
3790 * @opcode: Tx scheduler AQ command opcode
3791 * @cmd_details: pointer to command details structure or NULL
3793 * Generic command handler for Tx scheduler AQ commands
3795 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3796 void *buff, u16 buff_size,
3797 enum i40e_admin_queue_opc opcode,
3798 struct i40e_asq_cmd_details *cmd_details)
3800 struct i40e_aq_desc desc;
3801 struct i40e_aqc_tx_sched_ind *cmd =
3802 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3803 enum i40e_status_code status;
3804 bool cmd_param_flag = false;
3807 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3808 case i40e_aqc_opc_configure_vsi_tc_bw:
3809 case i40e_aqc_opc_enable_switching_comp_ets:
3810 case i40e_aqc_opc_modify_switching_comp_ets:
3811 case i40e_aqc_opc_disable_switching_comp_ets:
3812 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3813 case i40e_aqc_opc_configure_switching_comp_bw_config:
3814 cmd_param_flag = true;
3816 case i40e_aqc_opc_query_vsi_bw_config:
3817 case i40e_aqc_opc_query_vsi_ets_sla_config:
3818 case i40e_aqc_opc_query_switching_comp_ets_config:
3819 case i40e_aqc_opc_query_port_ets_config:
3820 case i40e_aqc_opc_query_switching_comp_bw_config:
3821 cmd_param_flag = false;
3824 return I40E_ERR_PARAM;
3827 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3829 /* Indirect command */
3830 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3832 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3833 if (buff_size > I40E_AQ_LARGE_BUF)
3834 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3836 desc.datalen = CPU_TO_LE16(buff_size);
3838 cmd->vsi_seid = CPU_TO_LE16(seid);
3840 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3846 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3847 * @hw: pointer to the hw struct
3849 * @credit: BW limit credits (0 = disabled)
3850 * @max_credit: Max BW limit credits
3851 * @cmd_details: pointer to command details structure or NULL
3853 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3854 u16 seid, u16 credit, u8 max_credit,
3855 struct i40e_asq_cmd_details *cmd_details)
3857 struct i40e_aq_desc desc;
3858 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3859 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3860 enum i40e_status_code status;
3862 i40e_fill_default_direct_cmd_desc(&desc,
3863 i40e_aqc_opc_configure_vsi_bw_limit);
3865 cmd->vsi_seid = CPU_TO_LE16(seid);
3866 cmd->credit = CPU_TO_LE16(credit);
3867 cmd->max_credit = max_credit;
3869 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3875 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3876 * @hw: pointer to the hw struct
3877 * @seid: switching component seid
3878 * @credit: BW limit credits (0 = disabled)
3879 * @max_bw: Max BW limit credits
3880 * @cmd_details: pointer to command details structure or NULL
3882 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3883 u16 seid, u16 credit, u8 max_bw,
3884 struct i40e_asq_cmd_details *cmd_details)
3886 struct i40e_aq_desc desc;
3887 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3888 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3889 enum i40e_status_code status;
3891 i40e_fill_default_direct_cmd_desc(&desc,
3892 i40e_aqc_opc_configure_switching_comp_bw_limit);
3894 cmd->seid = CPU_TO_LE16(seid);
3895 cmd->credit = CPU_TO_LE16(credit);
3896 cmd->max_bw = max_bw;
3898 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3904 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3905 * @hw: pointer to the hw struct
3907 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3908 * @cmd_details: pointer to command details structure or NULL
3910 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3912 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3913 struct i40e_asq_cmd_details *cmd_details)
3915 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3916 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3921 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3922 * @hw: pointer to the hw struct
3924 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3925 * @cmd_details: pointer to command details structure or NULL
3927 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3929 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3930 struct i40e_asq_cmd_details *cmd_details)
3932 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3933 i40e_aqc_opc_configure_vsi_tc_bw,
3938 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
3939 * @hw: pointer to the hw struct
3940 * @seid: seid of the switching component
3941 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3942 * @cmd_details: pointer to command details structure or NULL
3944 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
3945 struct i40e_hw *hw, u16 seid,
3946 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
3947 struct i40e_asq_cmd_details *cmd_details)
3949 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3950 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
3955 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3956 * @hw: pointer to the hw struct
3957 * @seid: seid of the VSI
3958 * @bw_data: Buffer to hold VSI BW configuration
3959 * @cmd_details: pointer to command details structure or NULL
3961 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3963 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3964 struct i40e_asq_cmd_details *cmd_details)
3966 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3967 i40e_aqc_opc_query_vsi_bw_config,
3972 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3973 * @hw: pointer to the hw struct
3974 * @seid: seid of the VSI
3975 * @bw_data: Buffer to hold VSI BW configuration per TC
3976 * @cmd_details: pointer to command details structure or NULL
3978 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3980 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3981 struct i40e_asq_cmd_details *cmd_details)
3983 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3984 i40e_aqc_opc_query_vsi_ets_sla_config,
3989 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3990 * @hw: pointer to the hw struct
3991 * @seid: seid of the switching component
3992 * @bw_data: Buffer to hold switching component's per TC BW config
3993 * @cmd_details: pointer to command details structure or NULL
3995 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3997 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3998 struct i40e_asq_cmd_details *cmd_details)
4000 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4001 i40e_aqc_opc_query_switching_comp_ets_config,
4006 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4007 * @hw: pointer to the hw struct
4008 * @seid: seid of the VSI or switching component connected to Physical Port
4009 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4010 * @cmd_details: pointer to command details structure or NULL
4012 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4014 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4015 struct i40e_asq_cmd_details *cmd_details)
4017 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4018 i40e_aqc_opc_query_port_ets_config,
4023 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4024 * @hw: pointer to the hw struct
4025 * @seid: seid of the switching component
4026 * @bw_data: Buffer to hold switching component's BW configuration
4027 * @cmd_details: pointer to command details structure or NULL
4029 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4031 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4032 struct i40e_asq_cmd_details *cmd_details)
4034 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4035 i40e_aqc_opc_query_switching_comp_bw_config,
4040 * i40e_validate_filter_settings
4041 * @hw: pointer to the hardware structure
4042 * @settings: Filter control settings
4044 * Check and validate the filter control settings passed.
4045 * The function checks for the valid filter/context sizes being
4046 * passed for FCoE and PE.
4048 * Returns I40E_SUCCESS if the values passed are valid and within
4049 * range else returns an error.
4051 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4052 struct i40e_filter_control_settings *settings)
4054 u32 fcoe_cntx_size, fcoe_filt_size;
4055 u32 pe_cntx_size, pe_filt_size;
4060 /* Validate FCoE settings passed */
4061 switch (settings->fcoe_filt_num) {
4062 case I40E_HASH_FILTER_SIZE_1K:
4063 case I40E_HASH_FILTER_SIZE_2K:
4064 case I40E_HASH_FILTER_SIZE_4K:
4065 case I40E_HASH_FILTER_SIZE_8K:
4066 case I40E_HASH_FILTER_SIZE_16K:
4067 case I40E_HASH_FILTER_SIZE_32K:
4068 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4069 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4072 return I40E_ERR_PARAM;
4075 switch (settings->fcoe_cntx_num) {
4076 case I40E_DMA_CNTX_SIZE_512:
4077 case I40E_DMA_CNTX_SIZE_1K:
4078 case I40E_DMA_CNTX_SIZE_2K:
4079 case I40E_DMA_CNTX_SIZE_4K:
4080 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4081 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4084 return I40E_ERR_PARAM;
4087 /* Validate PE settings passed */
4088 switch (settings->pe_filt_num) {
4089 case I40E_HASH_FILTER_SIZE_1K:
4090 case I40E_HASH_FILTER_SIZE_2K:
4091 case I40E_HASH_FILTER_SIZE_4K:
4092 case I40E_HASH_FILTER_SIZE_8K:
4093 case I40E_HASH_FILTER_SIZE_16K:
4094 case I40E_HASH_FILTER_SIZE_32K:
4095 case I40E_HASH_FILTER_SIZE_64K:
4096 case I40E_HASH_FILTER_SIZE_128K:
4097 case I40E_HASH_FILTER_SIZE_256K:
4098 case I40E_HASH_FILTER_SIZE_512K:
4099 case I40E_HASH_FILTER_SIZE_1M:
4100 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4101 pe_filt_size <<= (u32)settings->pe_filt_num;
4104 return I40E_ERR_PARAM;
4107 switch (settings->pe_cntx_num) {
4108 case I40E_DMA_CNTX_SIZE_512:
4109 case I40E_DMA_CNTX_SIZE_1K:
4110 case I40E_DMA_CNTX_SIZE_2K:
4111 case I40E_DMA_CNTX_SIZE_4K:
4112 case I40E_DMA_CNTX_SIZE_8K:
4113 case I40E_DMA_CNTX_SIZE_16K:
4114 case I40E_DMA_CNTX_SIZE_32K:
4115 case I40E_DMA_CNTX_SIZE_64K:
4116 case I40E_DMA_CNTX_SIZE_128K:
4117 case I40E_DMA_CNTX_SIZE_256K:
4118 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4119 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4122 return I40E_ERR_PARAM;
4125 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4126 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4127 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4128 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4129 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4130 return I40E_ERR_INVALID_SIZE;
4132 return I40E_SUCCESS;
4136 * i40e_set_filter_control
4137 * @hw: pointer to the hardware structure
4138 * @settings: Filter control settings
4140 * Set the Queue Filters for PE/FCoE and enable filters required
4141 * for a single PF. It is expected that these settings are programmed
4142 * at the driver initialization time.
4144 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4145 struct i40e_filter_control_settings *settings)
4147 enum i40e_status_code ret = I40E_SUCCESS;
4148 u32 hash_lut_size = 0;
4152 return I40E_ERR_PARAM;
4154 /* Validate the input settings */
4155 ret = i40e_validate_filter_settings(hw, settings);
4159 /* Read the PF Queue Filter control register */
4160 val = rd32(hw, I40E_PFQF_CTL_0);
4162 /* Program required PE hash buckets for the PF */
4163 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4164 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4165 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4166 /* Program required PE contexts for the PF */
4167 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4168 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4169 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4171 /* Program required FCoE hash buckets for the PF */
4172 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4173 val |= ((u32)settings->fcoe_filt_num <<
4174 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4175 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4176 /* Program required FCoE DDP contexts for the PF */
4177 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4178 val |= ((u32)settings->fcoe_cntx_num <<
4179 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4180 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4182 /* Program Hash LUT size for the PF */
4183 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4184 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4186 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4187 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4189 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4190 if (settings->enable_fdir)
4191 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4192 if (settings->enable_ethtype)
4193 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4194 if (settings->enable_macvlan)
4195 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4197 wr32(hw, I40E_PFQF_CTL_0, val);
4199 return I40E_SUCCESS;
4203 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4204 * @hw: pointer to the hw struct
4205 * @mac_addr: MAC address to use in the filter
4206 * @ethtype: Ethertype to use in the filter
4207 * @flags: Flags that needs to be applied to the filter
4208 * @vsi_seid: seid of the control VSI
4209 * @queue: VSI queue number to send the packet to
4210 * @is_add: Add control packet filter if True else remove
4211 * @stats: Structure to hold information on control filter counts
4212 * @cmd_details: pointer to command details structure or NULL
4214 * This command will Add or Remove control packet filter for a control VSI.
4215 * In return it will update the total number of perfect filter count in
4218 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4219 u8 *mac_addr, u16 ethtype, u16 flags,
4220 u16 vsi_seid, u16 queue, bool is_add,
4221 struct i40e_control_filter_stats *stats,
4222 struct i40e_asq_cmd_details *cmd_details)
4224 struct i40e_aq_desc desc;
4225 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4226 (struct i40e_aqc_add_remove_control_packet_filter *)
4228 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4229 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4231 enum i40e_status_code status;
4234 return I40E_ERR_PARAM;
4237 i40e_fill_default_direct_cmd_desc(&desc,
4238 i40e_aqc_opc_add_control_packet_filter);
4239 cmd->queue = CPU_TO_LE16(queue);
4241 i40e_fill_default_direct_cmd_desc(&desc,
4242 i40e_aqc_opc_remove_control_packet_filter);
4246 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4247 I40E_NONDMA_TO_NONDMA);
4249 cmd->etype = CPU_TO_LE16(ethtype);
4250 cmd->flags = CPU_TO_LE16(flags);
4251 cmd->seid = CPU_TO_LE16(vsi_seid);
4253 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4255 if (!status && stats) {
4256 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4257 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4258 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4259 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4266 * i40e_aq_add_cloud_filters
4267 * @hw: pointer to the hardware structure
4268 * @seid: VSI seid to add cloud filters from
4269 * @filters: Buffer which contains the filters to be added
4270 * @filter_count: number of filters contained in the buffer
4272 * Set the cloud filters for a given VSI. The contents of the
4273 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4274 * in by the caller of the function.
4277 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4279 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4282 struct i40e_aq_desc desc;
4283 struct i40e_aqc_add_remove_cloud_filters *cmd =
4284 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4286 enum i40e_status_code status;
4288 i40e_fill_default_direct_cmd_desc(&desc,
4289 i40e_aqc_opc_add_cloud_filters);
4291 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4293 desc.datalen = CPU_TO_LE16(buff_len);
4294 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4295 cmd->num_filters = filter_count;
4296 cmd->seid = CPU_TO_LE16(seid);
4298 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4304 * i40e_aq_remove_cloud_filters
4305 * @hw: pointer to the hardware structure
4306 * @seid: VSI seid to remove cloud filters from
4307 * @filters: Buffer which contains the filters to be removed
4308 * @filter_count: number of filters contained in the buffer
4310 * Remove the cloud filters for a given VSI. The contents of the
4311 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4312 * in by the caller of the function.
4315 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4317 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4320 struct i40e_aq_desc desc;
4321 struct i40e_aqc_add_remove_cloud_filters *cmd =
4322 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4323 enum i40e_status_code status;
4326 i40e_fill_default_direct_cmd_desc(&desc,
4327 i40e_aqc_opc_remove_cloud_filters);
4329 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4331 desc.datalen = CPU_TO_LE16(buff_len);
4332 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4333 cmd->num_filters = filter_count;
4334 cmd->seid = CPU_TO_LE16(seid);
4336 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4342 * i40e_aq_alternate_write
4343 * @hw: pointer to the hardware structure
4344 * @reg_addr0: address of first dword to be read
4345 * @reg_val0: value to be written under 'reg_addr0'
4346 * @reg_addr1: address of second dword to be read
4347 * @reg_val1: value to be written under 'reg_addr1'
4349 * Write one or two dwords to alternate structure. Fields are indicated
4350 * by 'reg_addr0' and 'reg_addr1' register numbers.
4353 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4354 u32 reg_addr0, u32 reg_val0,
4355 u32 reg_addr1, u32 reg_val1)
4357 struct i40e_aq_desc desc;
4358 struct i40e_aqc_alternate_write *cmd_resp =
4359 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4360 enum i40e_status_code status;
4362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4363 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4364 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4365 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4366 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4368 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4374 * i40e_aq_alternate_write_indirect
4375 * @hw: pointer to the hardware structure
4376 * @addr: address of a first register to be modified
4377 * @dw_count: number of alternate structure fields to write
4378 * @buffer: pointer to the command buffer
4380 * Write 'dw_count' dwords from 'buffer' to alternate structure
4381 * starting at 'addr'.
4384 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4385 u32 addr, u32 dw_count, void *buffer)
4387 struct i40e_aq_desc desc;
4388 struct i40e_aqc_alternate_ind_write *cmd_resp =
4389 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4390 enum i40e_status_code status;
4393 return I40E_ERR_PARAM;
4395 /* Indirect command */
4396 i40e_fill_default_direct_cmd_desc(&desc,
4397 i40e_aqc_opc_alternate_write_indirect);
4399 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4400 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4401 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4402 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4404 cmd_resp->address = CPU_TO_LE32(addr);
4405 cmd_resp->length = CPU_TO_LE32(dw_count);
4406 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4407 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4409 status = i40e_asq_send_command(hw, &desc, buffer,
4410 I40E_LO_DWORD(4*dw_count), NULL);
4416 * i40e_aq_alternate_read
4417 * @hw: pointer to the hardware structure
4418 * @reg_addr0: address of first dword to be read
4419 * @reg_val0: pointer for data read from 'reg_addr0'
4420 * @reg_addr1: address of second dword to be read
4421 * @reg_val1: pointer for data read from 'reg_addr1'
4423 * Read one or two dwords from alternate structure. Fields are indicated
4424 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4425 * is not passed then only register at 'reg_addr0' is read.
4428 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4429 u32 reg_addr0, u32 *reg_val0,
4430 u32 reg_addr1, u32 *reg_val1)
4432 struct i40e_aq_desc desc;
4433 struct i40e_aqc_alternate_write *cmd_resp =
4434 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4435 enum i40e_status_code status;
4437 if (reg_val0 == NULL)
4438 return I40E_ERR_PARAM;
4440 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4441 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4442 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4444 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4446 if (status == I40E_SUCCESS) {
4447 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4449 if (reg_val1 != NULL)
4450 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4457 * i40e_aq_alternate_read_indirect
4458 * @hw: pointer to the hardware structure
4459 * @addr: address of the alternate structure field
4460 * @dw_count: number of alternate structure fields to read
4461 * @buffer: pointer to the command buffer
4463 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4464 * place them in 'buffer'. The buffer should be allocated by caller.
4467 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4468 u32 addr, u32 dw_count, void *buffer)
4470 struct i40e_aq_desc desc;
4471 struct i40e_aqc_alternate_ind_write *cmd_resp =
4472 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4473 enum i40e_status_code status;
4476 return I40E_ERR_PARAM;
4478 /* Indirect command */
4479 i40e_fill_default_direct_cmd_desc(&desc,
4480 i40e_aqc_opc_alternate_read_indirect);
4482 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4483 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4484 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4485 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4487 cmd_resp->address = CPU_TO_LE32(addr);
4488 cmd_resp->length = CPU_TO_LE32(dw_count);
4489 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4490 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4492 status = i40e_asq_send_command(hw, &desc, buffer,
4493 I40E_LO_DWORD(4*dw_count), NULL);
4499 * i40e_aq_alternate_clear
4500 * @hw: pointer to the HW structure.
4502 * Clear the alternate structures of the port from which the function
4506 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4508 struct i40e_aq_desc desc;
4509 enum i40e_status_code status;
4511 i40e_fill_default_direct_cmd_desc(&desc,
4512 i40e_aqc_opc_alternate_clear_port);
4514 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4520 * i40e_aq_alternate_write_done
4521 * @hw: pointer to the HW structure.
4522 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4523 * @reset_needed: indicates the SW should trigger GLOBAL reset
4525 * Indicates to the FW that alternate structures have been changed.
4528 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4529 u8 bios_mode, bool *reset_needed)
4531 struct i40e_aq_desc desc;
4532 struct i40e_aqc_alternate_write_done *cmd =
4533 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4534 enum i40e_status_code status;
4536 if (reset_needed == NULL)
4537 return I40E_ERR_PARAM;
4539 i40e_fill_default_direct_cmd_desc(&desc,
4540 i40e_aqc_opc_alternate_write_done);
4542 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4544 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4546 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4547 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4553 * i40e_aq_set_oem_mode
4554 * @hw: pointer to the HW structure.
4555 * @oem_mode: the OEM mode to be used
4557 * Sets the device to a specific operating mode. Currently the only supported
4558 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4561 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4564 struct i40e_aq_desc desc;
4565 struct i40e_aqc_alternate_write_done *cmd =
4566 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4567 enum i40e_status_code status;
4569 i40e_fill_default_direct_cmd_desc(&desc,
4570 i40e_aqc_opc_alternate_set_mode);
4572 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4574 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4581 * i40e_aq_suspend_port_tx
4582 * @hw: pointer to the hardware structure
4584 * @cmd_details: pointer to command details structure or NULL
4586 * Suspend port's Tx traffic
4588 enum i40e_status_code i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4589 struct i40e_asq_cmd_details *cmd_details)
4591 struct i40e_aq_desc desc;
4592 enum i40e_status_code status;
4593 struct i40e_aqc_tx_sched_ind *cmd =
4594 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4598 cmd->vsi_seid = CPU_TO_LE16(seid);
4600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4604 #endif /* I40E_DCB_SW */
4607 * i40e_aq_resume_port_tx
4608 * @hw: pointer to the hardware structure
4609 * @cmd_details: pointer to command details structure or NULL
4611 * Resume port's Tx traffic
4613 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4614 struct i40e_asq_cmd_details *cmd_details)
4616 struct i40e_aq_desc desc;
4617 enum i40e_status_code status;
4619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4627 * i40e_set_pci_config_data - store PCI bus info
4628 * @hw: pointer to hardware structure
4629 * @link_status: the link status word from PCI config space
4631 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4633 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4635 hw->bus.type = i40e_bus_type_pci_express;
4637 switch (link_status & I40E_PCI_LINK_WIDTH) {
4638 case I40E_PCI_LINK_WIDTH_1:
4639 hw->bus.width = i40e_bus_width_pcie_x1;
4641 case I40E_PCI_LINK_WIDTH_2:
4642 hw->bus.width = i40e_bus_width_pcie_x2;
4644 case I40E_PCI_LINK_WIDTH_4:
4645 hw->bus.width = i40e_bus_width_pcie_x4;
4647 case I40E_PCI_LINK_WIDTH_8:
4648 hw->bus.width = i40e_bus_width_pcie_x8;
4651 hw->bus.width = i40e_bus_width_unknown;
4655 switch (link_status & I40E_PCI_LINK_SPEED) {
4656 case I40E_PCI_LINK_SPEED_2500:
4657 hw->bus.speed = i40e_bus_speed_2500;
4659 case I40E_PCI_LINK_SPEED_5000:
4660 hw->bus.speed = i40e_bus_speed_5000;
4662 case I40E_PCI_LINK_SPEED_8000:
4663 hw->bus.speed = i40e_bus_speed_8000;
4666 hw->bus.speed = i40e_bus_speed_unknown;
4672 * i40e_read_bw_from_alt_ram
4673 * @hw: pointer to the hardware structure
4674 * @max_bw: pointer for max_bw read
4675 * @min_bw: pointer for min_bw read
4676 * @min_valid: pointer for bool that is true if min_bw is a valid value
4677 * @max_valid: pointer for bool that is true if max_bw is a valid value
4679 * Read bw from the alternate ram for the given pf
4681 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4682 u32 *max_bw, u32 *min_bw,
4683 bool *min_valid, bool *max_valid)
4685 enum i40e_status_code status;
4686 u32 max_bw_addr, min_bw_addr;
4688 /* Calculate the address of the min/max bw registers */
4689 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4690 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4691 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4692 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4693 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4694 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4696 /* Read the bandwidths from alt ram */
4697 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4698 min_bw_addr, min_bw);
4700 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4705 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4714 * i40e_aq_configure_partition_bw
4715 * @hw: pointer to the hardware structure
4716 * @bw_data: Buffer holding valid pfs and bw limits
4717 * @cmd_details: pointer to command details
4719 * Configure partitions guaranteed/max bw
4721 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4722 struct i40e_aqc_configure_partition_bw_data *bw_data,
4723 struct i40e_asq_cmd_details *cmd_details)
4725 enum i40e_status_code status;
4726 struct i40e_aq_desc desc;
4727 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4729 i40e_fill_default_direct_cmd_desc(&desc,
4730 i40e_aqc_opc_configure_partition_bw);
4732 /* Indirect command */
4733 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4734 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4736 if (bwd_size > I40E_AQ_LARGE_BUF)
4737 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4739 desc.datalen = CPU_TO_LE16(bwd_size);
4741 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4747 * i40e_aq_send_msg_to_pf
4748 * @hw: pointer to the hardware structure
4749 * @v_opcode: opcodes for VF-PF communication
4750 * @v_retval: return error code
4751 * @msg: pointer to the msg buffer
4752 * @msglen: msg length
4753 * @cmd_details: pointer to command details
4755 * Send message to PF driver using admin queue. By default, this message
4756 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4757 * completion before returning.
4759 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4760 enum i40e_virtchnl_ops v_opcode,
4761 enum i40e_status_code v_retval,
4762 u8 *msg, u16 msglen,
4763 struct i40e_asq_cmd_details *cmd_details)
4765 struct i40e_aq_desc desc;
4766 enum i40e_status_code status;
4768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4769 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4770 desc.cookie_high = CPU_TO_LE32(v_opcode);
4771 desc.cookie_low = CPU_TO_LE32(v_retval);
4773 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4774 | I40E_AQ_FLAG_RD));
4775 if (msglen > I40E_AQ_LARGE_BUF)
4776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4777 desc.datalen = CPU_TO_LE16(msglen);
4780 struct i40e_asq_cmd_details details;
4781 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4782 details.async = true;
4783 cmd_details = &details;
4785 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4786 msglen, cmd_details);
4791 * i40e_vf_parse_hw_config
4792 * @hw: pointer to the hardware structure
4793 * @msg: pointer to the virtual channel VF resource structure
4795 * Given a VF resource message from the PF, populate the hw struct
4796 * with appropriate information.
4798 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4799 struct i40e_virtchnl_vf_resource *msg)
4801 struct i40e_virtchnl_vsi_resource *vsi_res;
4804 vsi_res = &msg->vsi_res[0];
4806 hw->dev_caps.num_vsis = msg->num_vsis;
4807 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4808 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4809 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4810 hw->dev_caps.dcb = msg->vf_offload_flags &
4811 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4812 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4813 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4814 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4815 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4816 for (i = 0; i < msg->num_vsis; i++) {
4817 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4818 i40e_memcpy(hw->mac.perm_addr,
4819 vsi_res->default_mac_addr,
4820 I40E_ETH_LENGTH_OF_ADDRESS,
4821 I40E_NONDMA_TO_NONDMA);
4822 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4823 I40E_ETH_LENGTH_OF_ADDRESS,
4824 I40E_NONDMA_TO_NONDMA);
4832 * @hw: pointer to the hardware structure
4834 * Send a VF_RESET message to the PF. Does not wait for response from PF
4835 * as none will be forthcoming. Immediately after calling this function,
4836 * the admin queue should be shut down and (optionally) reinitialized.
4838 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4840 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4841 I40E_SUCCESS, NULL, 0, NULL);
4843 #endif /* VF_DRIVER */