1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *buf = (u8 *)buffer;
104 if ((!(mask & hw->debug_mask)) || (desc == NULL))
108 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
109 LE16_TO_CPU(aq_desc->opcode),
110 LE16_TO_CPU(aq_desc->flags),
111 LE16_TO_CPU(aq_desc->datalen),
112 LE16_TO_CPU(aq_desc->retval));
113 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
114 LE32_TO_CPU(aq_desc->cookie_high),
115 LE32_TO_CPU(aq_desc->cookie_low));
116 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
117 LE32_TO_CPU(aq_desc->params.internal.param0),
118 LE32_TO_CPU(aq_desc->params.internal.param1));
119 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
120 LE32_TO_CPU(aq_desc->params.external.addr_high),
121 LE32_TO_CPU(aq_desc->params.external.addr_low));
123 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
124 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
127 /* write the full 16-byte chunks */
128 for (i = 0; i < (len - 16); i += 16)
130 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
131 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
132 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
133 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
134 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
135 /* write whatever's left over without overrunning the buffer */
140 memset(d_buf, 0, sizeof(d_buf));
141 j += sprintf(d_buf, "\t0x%04X ", i);
143 j += sprintf(&d_buf[j], " %02X", buf[i++]);
144 i40e_debug(hw, mask, "%s\n", d_buf);
150 * i40e_check_asq_alive
151 * @hw: pointer to the hw struct
153 * Returns true if Queue is enabled else false.
155 bool i40e_check_asq_alive(struct i40e_hw *hw)
158 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
164 * i40e_aq_queue_shutdown
165 * @hw: pointer to the hw struct
166 * @unloading: is the driver unloading itself
168 * Tell the Firmware that we're shutting down the AdminQ and whether
169 * or not the driver is unloading as well.
171 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
174 struct i40e_aq_desc desc;
175 struct i40e_aqc_queue_shutdown *cmd =
176 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
177 enum i40e_status_code status;
179 i40e_fill_default_direct_cmd_desc(&desc,
180 i40e_aqc_opc_queue_shutdown);
183 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
189 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
190 * hardware to a bit-field that can be used by SW to more easily determine the
193 * Macros are used to shorten the table lines and make this table human
196 * We store the PTYPE in the top byte of the bit field - this is just so that
197 * we can check that the table doesn't have a row missing, as the index into
198 * the table should be the PTYPE.
202 * IF NOT i40e_ptype_lookup[ptype].known
205 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
206 * Use the rest of the fields to look at the tunnels, inner protocols, etc
208 * Use the enum i40e_rx_l2_ptype to decode the packet type
212 /* macro to make the table lines short */
213 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
216 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
217 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
218 I40E_RX_PTYPE_##OUTER_FRAG, \
219 I40E_RX_PTYPE_TUNNEL_##T, \
220 I40E_RX_PTYPE_TUNNEL_END_##TE, \
221 I40E_RX_PTYPE_##TEF, \
222 I40E_RX_PTYPE_INNER_PROT_##I, \
223 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
225 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
226 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
228 /* shorter macros makes the table fit but are terse */
229 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
230 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
231 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
233 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
234 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
235 /* L2 Packet types */
236 I40E_PTT_UNUSED_ENTRY(0),
237 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
239 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(4),
241 I40E_PTT_UNUSED_ENTRY(5),
242 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(8),
245 I40E_PTT_UNUSED_ENTRY(9),
246 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
248 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 /* Non Tunneled IPv4 */
260 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(25),
264 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
265 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
266 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
269 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
270 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
271 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(32),
273 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
274 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
275 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
278 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
279 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
280 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
281 I40E_PTT_UNUSED_ENTRY(39),
282 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
283 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
284 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
286 /* IPv4 --> GRE/NAT */
287 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
289 /* IPv4 --> GRE/NAT --> IPv4 */
290 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
291 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
292 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(47),
294 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
295 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
296 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> IPv6 */
299 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
300 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
301 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
302 I40E_PTT_UNUSED_ENTRY(54),
303 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
304 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
305 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
307 /* IPv4 --> GRE/NAT --> MAC */
308 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
310 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
311 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
312 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
313 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(62),
315 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
316 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
317 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
320 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
321 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
322 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
323 I40E_PTT_UNUSED_ENTRY(69),
324 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
325 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
326 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
328 /* IPv4 --> GRE/NAT --> MAC/VLAN */
329 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
331 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
332 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
333 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
334 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(77),
336 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
337 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
338 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
340 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
341 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
342 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
343 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(84),
345 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
346 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
347 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
349 /* Non Tunneled IPv6 */
350 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
353 I40E_PTT_UNUSED_ENTRY(91),
354 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
355 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
356 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
359 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
360 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
361 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(98),
363 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
364 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
365 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
368 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
369 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
370 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
371 I40E_PTT_UNUSED_ENTRY(105),
372 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
373 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
374 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
376 /* IPv6 --> GRE/NAT */
377 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
379 /* IPv6 --> GRE/NAT -> IPv4 */
380 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
381 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
382 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(113),
384 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
385 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
386 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> IPv6 */
389 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
390 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
391 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
392 I40E_PTT_UNUSED_ENTRY(120),
393 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
394 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
395 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
397 /* IPv6 --> GRE/NAT -> MAC */
398 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
401 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
402 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
403 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(128),
405 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
406 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
407 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
410 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
411 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
412 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
413 I40E_PTT_UNUSED_ENTRY(135),
414 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
415 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
416 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
418 /* IPv6 --> GRE/NAT -> MAC/VLAN */
419 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
422 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
423 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
424 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(143),
426 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
427 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
428 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
430 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
431 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
432 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
433 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
434 I40E_PTT_UNUSED_ENTRY(150),
435 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
436 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
437 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
440 I40E_PTT_UNUSED_ENTRY(154),
441 I40E_PTT_UNUSED_ENTRY(155),
442 I40E_PTT_UNUSED_ENTRY(156),
443 I40E_PTT_UNUSED_ENTRY(157),
444 I40E_PTT_UNUSED_ENTRY(158),
445 I40E_PTT_UNUSED_ENTRY(159),
447 I40E_PTT_UNUSED_ENTRY(160),
448 I40E_PTT_UNUSED_ENTRY(161),
449 I40E_PTT_UNUSED_ENTRY(162),
450 I40E_PTT_UNUSED_ENTRY(163),
451 I40E_PTT_UNUSED_ENTRY(164),
452 I40E_PTT_UNUSED_ENTRY(165),
453 I40E_PTT_UNUSED_ENTRY(166),
454 I40E_PTT_UNUSED_ENTRY(167),
455 I40E_PTT_UNUSED_ENTRY(168),
456 I40E_PTT_UNUSED_ENTRY(169),
458 I40E_PTT_UNUSED_ENTRY(170),
459 I40E_PTT_UNUSED_ENTRY(171),
460 I40E_PTT_UNUSED_ENTRY(172),
461 I40E_PTT_UNUSED_ENTRY(173),
462 I40E_PTT_UNUSED_ENTRY(174),
463 I40E_PTT_UNUSED_ENTRY(175),
464 I40E_PTT_UNUSED_ENTRY(176),
465 I40E_PTT_UNUSED_ENTRY(177),
466 I40E_PTT_UNUSED_ENTRY(178),
467 I40E_PTT_UNUSED_ENTRY(179),
469 I40E_PTT_UNUSED_ENTRY(180),
470 I40E_PTT_UNUSED_ENTRY(181),
471 I40E_PTT_UNUSED_ENTRY(182),
472 I40E_PTT_UNUSED_ENTRY(183),
473 I40E_PTT_UNUSED_ENTRY(184),
474 I40E_PTT_UNUSED_ENTRY(185),
475 I40E_PTT_UNUSED_ENTRY(186),
476 I40E_PTT_UNUSED_ENTRY(187),
477 I40E_PTT_UNUSED_ENTRY(188),
478 I40E_PTT_UNUSED_ENTRY(189),
480 I40E_PTT_UNUSED_ENTRY(190),
481 I40E_PTT_UNUSED_ENTRY(191),
482 I40E_PTT_UNUSED_ENTRY(192),
483 I40E_PTT_UNUSED_ENTRY(193),
484 I40E_PTT_UNUSED_ENTRY(194),
485 I40E_PTT_UNUSED_ENTRY(195),
486 I40E_PTT_UNUSED_ENTRY(196),
487 I40E_PTT_UNUSED_ENTRY(197),
488 I40E_PTT_UNUSED_ENTRY(198),
489 I40E_PTT_UNUSED_ENTRY(199),
491 I40E_PTT_UNUSED_ENTRY(200),
492 I40E_PTT_UNUSED_ENTRY(201),
493 I40E_PTT_UNUSED_ENTRY(202),
494 I40E_PTT_UNUSED_ENTRY(203),
495 I40E_PTT_UNUSED_ENTRY(204),
496 I40E_PTT_UNUSED_ENTRY(205),
497 I40E_PTT_UNUSED_ENTRY(206),
498 I40E_PTT_UNUSED_ENTRY(207),
499 I40E_PTT_UNUSED_ENTRY(208),
500 I40E_PTT_UNUSED_ENTRY(209),
502 I40E_PTT_UNUSED_ENTRY(210),
503 I40E_PTT_UNUSED_ENTRY(211),
504 I40E_PTT_UNUSED_ENTRY(212),
505 I40E_PTT_UNUSED_ENTRY(213),
506 I40E_PTT_UNUSED_ENTRY(214),
507 I40E_PTT_UNUSED_ENTRY(215),
508 I40E_PTT_UNUSED_ENTRY(216),
509 I40E_PTT_UNUSED_ENTRY(217),
510 I40E_PTT_UNUSED_ENTRY(218),
511 I40E_PTT_UNUSED_ENTRY(219),
513 I40E_PTT_UNUSED_ENTRY(220),
514 I40E_PTT_UNUSED_ENTRY(221),
515 I40E_PTT_UNUSED_ENTRY(222),
516 I40E_PTT_UNUSED_ENTRY(223),
517 I40E_PTT_UNUSED_ENTRY(224),
518 I40E_PTT_UNUSED_ENTRY(225),
519 I40E_PTT_UNUSED_ENTRY(226),
520 I40E_PTT_UNUSED_ENTRY(227),
521 I40E_PTT_UNUSED_ENTRY(228),
522 I40E_PTT_UNUSED_ENTRY(229),
524 I40E_PTT_UNUSED_ENTRY(230),
525 I40E_PTT_UNUSED_ENTRY(231),
526 I40E_PTT_UNUSED_ENTRY(232),
527 I40E_PTT_UNUSED_ENTRY(233),
528 I40E_PTT_UNUSED_ENTRY(234),
529 I40E_PTT_UNUSED_ENTRY(235),
530 I40E_PTT_UNUSED_ENTRY(236),
531 I40E_PTT_UNUSED_ENTRY(237),
532 I40E_PTT_UNUSED_ENTRY(238),
533 I40E_PTT_UNUSED_ENTRY(239),
535 I40E_PTT_UNUSED_ENTRY(240),
536 I40E_PTT_UNUSED_ENTRY(241),
537 I40E_PTT_UNUSED_ENTRY(242),
538 I40E_PTT_UNUSED_ENTRY(243),
539 I40E_PTT_UNUSED_ENTRY(244),
540 I40E_PTT_UNUSED_ENTRY(245),
541 I40E_PTT_UNUSED_ENTRY(246),
542 I40E_PTT_UNUSED_ENTRY(247),
543 I40E_PTT_UNUSED_ENTRY(248),
544 I40E_PTT_UNUSED_ENTRY(249),
546 I40E_PTT_UNUSED_ENTRY(250),
547 I40E_PTT_UNUSED_ENTRY(251),
548 I40E_PTT_UNUSED_ENTRY(252),
549 I40E_PTT_UNUSED_ENTRY(253),
550 I40E_PTT_UNUSED_ENTRY(254),
551 I40E_PTT_UNUSED_ENTRY(255)
556 * i40e_validate_mac_addr - Validate unicast MAC address
557 * @mac_addr: pointer to MAC address
559 * Tests a MAC address to ensure it is a valid Individual Address
561 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
563 enum i40e_status_code status = I40E_SUCCESS;
565 DEBUGFUNC("i40e_validate_mac_addr");
567 /* Broadcast addresses ARE multicast addresses
568 * Make sure it is not a multicast address
569 * Reject the zero address
571 if (I40E_IS_MULTICAST(mac_addr) ||
572 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
573 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
574 status = I40E_ERR_INVALID_MAC_ADDR;
581 * i40e_init_shared_code - Initialize the shared code
582 * @hw: pointer to hardware structure
584 * This assigns the MAC type and PHY code and inits the NVM.
585 * Does not touch the hardware. This function must be called prior to any
586 * other function in the shared code. The i40e_hw structure should be
587 * memset to 0 prior to calling this function. The following fields in
588 * hw structure should be filled in prior to calling this function:
589 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
590 * subsystem_vendor_id, and revision_id
592 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
594 enum i40e_status_code status = I40E_SUCCESS;
595 u32 port, ari, func_rid;
597 DEBUGFUNC("i40e_init_shared_code");
599 i40e_set_mac_type(hw);
601 switch (hw->mac.type) {
605 return I40E_ERR_DEVICE_NOT_SUPPORTED;
608 hw->phy.get_link_info = true;
610 /* Determine port number and PF number*/
611 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
612 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
614 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
615 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
616 func_rid = rd32(hw, I40E_PF_FUNC_RID);
618 hw->pf_id = (u8)(func_rid & 0xff);
620 hw->pf_id = (u8)(func_rid & 0x7);
622 status = i40e_init_nvm(hw);
627 * i40e_aq_mac_address_read - Retrieve the MAC addresses
628 * @hw: pointer to the hw struct
629 * @flags: a return indicator of what addresses were added to the addr store
630 * @addrs: the requestor's mac addr store
631 * @cmd_details: pointer to command details structure or NULL
633 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
635 struct i40e_aqc_mac_address_read_data *addrs,
636 struct i40e_asq_cmd_details *cmd_details)
638 struct i40e_aq_desc desc;
639 struct i40e_aqc_mac_address_read *cmd_data =
640 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
641 enum i40e_status_code status;
643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
644 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
646 status = i40e_asq_send_command(hw, &desc, addrs,
647 sizeof(*addrs), cmd_details);
648 *flags = LE16_TO_CPU(cmd_data->command_flags);
654 * i40e_aq_mac_address_write - Change the MAC addresses
655 * @hw: pointer to the hw struct
656 * @flags: indicates which MAC to be written
657 * @mac_addr: address to write
658 * @cmd_details: pointer to command details structure or NULL
660 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
661 u16 flags, u8 *mac_addr,
662 struct i40e_asq_cmd_details *cmd_details)
664 struct i40e_aq_desc desc;
665 struct i40e_aqc_mac_address_write *cmd_data =
666 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
667 enum i40e_status_code status;
669 i40e_fill_default_direct_cmd_desc(&desc,
670 i40e_aqc_opc_mac_address_write);
671 cmd_data->command_flags = CPU_TO_LE16(flags);
672 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
673 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
674 ((u32)mac_addr[3] << 16) |
675 ((u32)mac_addr[4] << 8) |
678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
684 * i40e_get_mac_addr - get MAC address
685 * @hw: pointer to the HW structure
686 * @mac_addr: pointer to MAC address
688 * Reads the adapter's MAC address from register
690 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
692 struct i40e_aqc_mac_address_read_data addrs;
693 enum i40e_status_code status;
696 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
698 if (flags & I40E_AQC_LAN_ADDR_VALID)
699 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
705 * i40e_get_port_mac_addr - get Port MAC address
706 * @hw: pointer to the HW structure
707 * @mac_addr: pointer to Port MAC address
709 * Reads the adapter's Port MAC address
711 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
713 struct i40e_aqc_mac_address_read_data addrs;
714 enum i40e_status_code status;
717 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
721 if (flags & I40E_AQC_PORT_ADDR_VALID)
722 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
724 status = I40E_ERR_INVALID_MAC_ADDR;
730 * i40e_pre_tx_queue_cfg - pre tx queue configure
731 * @hw: pointer to the HW structure
732 * @queue: target pf queue index
733 * @enable: state change request
735 * Handles hw requirement to indicate intention to enable
736 * or disable target queue.
738 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
740 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
744 if (abs_queue_idx >= 128) {
745 reg_block = abs_queue_idx / 128;
746 abs_queue_idx %= 128;
749 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
750 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
751 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
754 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
756 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
758 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
762 * i40e_read_pba_string - Reads part number string from EEPROM
763 * @hw: pointer to hardware structure
764 * @pba_num: stores the part number string from the EEPROM
765 * @pba_num_size: part number string buffer length
767 * Reads the part number string from the EEPROM.
769 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
772 enum i40e_status_code status = I40E_SUCCESS;
778 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
779 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
780 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
784 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
785 if (status != I40E_SUCCESS) {
786 DEBUGOUT("Failed to read PBA Block pointer.\n");
790 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
791 if (status != I40E_SUCCESS) {
792 DEBUGOUT("Failed to read PBA Block size.\n");
796 /* Subtract one to get PBA word count (PBA Size word is included in
800 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
801 DEBUGOUT("Buffer to small for PBA data.\n");
802 return I40E_ERR_PARAM;
805 for (i = 0; i < pba_size; i++) {
806 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
807 if (status != I40E_SUCCESS) {
808 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
812 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
813 pba_num[(i * 2) + 1] = pba_word & 0xFF;
815 pba_num[(pba_size * 2)] = '\0';
821 * i40e_get_media_type - Gets media type
822 * @hw: pointer to the hardware structure
824 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
826 enum i40e_media_type media;
828 switch (hw->phy.link_info.phy_type) {
829 case I40E_PHY_TYPE_10GBASE_SR:
830 case I40E_PHY_TYPE_10GBASE_LR:
831 case I40E_PHY_TYPE_1000BASE_SX:
832 case I40E_PHY_TYPE_1000BASE_LX:
833 case I40E_PHY_TYPE_40GBASE_SR4:
834 case I40E_PHY_TYPE_40GBASE_LR4:
835 media = I40E_MEDIA_TYPE_FIBER;
837 case I40E_PHY_TYPE_100BASE_TX:
838 case I40E_PHY_TYPE_1000BASE_T:
839 case I40E_PHY_TYPE_10GBASE_T:
840 media = I40E_MEDIA_TYPE_BASET;
842 case I40E_PHY_TYPE_10GBASE_CR1_CU:
843 case I40E_PHY_TYPE_40GBASE_CR4_CU:
844 case I40E_PHY_TYPE_10GBASE_CR1:
845 case I40E_PHY_TYPE_40GBASE_CR4:
846 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
847 case I40E_PHY_TYPE_40GBASE_AOC:
848 case I40E_PHY_TYPE_10GBASE_AOC:
849 media = I40E_MEDIA_TYPE_DA;
851 case I40E_PHY_TYPE_1000BASE_KX:
852 case I40E_PHY_TYPE_10GBASE_KX4:
853 case I40E_PHY_TYPE_10GBASE_KR:
854 case I40E_PHY_TYPE_40GBASE_KR4:
855 media = I40E_MEDIA_TYPE_BACKPLANE;
857 case I40E_PHY_TYPE_SGMII:
858 case I40E_PHY_TYPE_XAUI:
859 case I40E_PHY_TYPE_XFI:
860 case I40E_PHY_TYPE_XLAUI:
861 case I40E_PHY_TYPE_XLPPI:
863 media = I40E_MEDIA_TYPE_UNKNOWN;
870 #define I40E_PF_RESET_WAIT_COUNT 100
872 * i40e_pf_reset - Reset the PF
873 * @hw: pointer to the hardware structure
875 * Assuming someone else has triggered a global reset,
876 * assure the global reset is complete and then reset the PF
878 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
885 /* Poll for Global Reset steady state in case of recent GRST.
886 * The grst delay value is in 100ms units, and we'll wait a
887 * couple counts longer to be sure we don't just miss the end.
889 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
890 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
891 for (cnt = 0; cnt < grst_del + 2; cnt++) {
892 reg = rd32(hw, I40E_GLGEN_RSTAT);
893 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
895 i40e_msec_delay(100);
897 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
898 DEBUGOUT("Global reset polling failed to complete.\n");
899 return I40E_ERR_RESET_FAILED;
902 /* Now Wait for the FW to be ready */
903 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
904 reg = rd32(hw, I40E_GLNVM_ULD);
905 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
906 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
907 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
908 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
909 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
914 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
915 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
916 DEBUGOUT("wait for FW Reset complete timedout\n");
917 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
918 return I40E_ERR_RESET_FAILED;
921 /* If there was a Global Reset in progress when we got here,
922 * we don't need to do the PF Reset
925 reg = rd32(hw, I40E_PFGEN_CTRL);
926 wr32(hw, I40E_PFGEN_CTRL,
927 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
928 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
929 reg = rd32(hw, I40E_PFGEN_CTRL);
930 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
934 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
935 DEBUGOUT("PF reset polling failed to complete.\n");
936 return I40E_ERR_RESET_FAILED;
940 i40e_clear_pxe_mode(hw);
947 * i40e_clear_hw - clear out any left over hw state
948 * @hw: pointer to the hw struct
950 * Clear queues and interrupts, typically called at init time,
951 * but after the capabilities have been found so we know how many
952 * queues and msix vectors have been allocated.
954 void i40e_clear_hw(struct i40e_hw *hw)
956 u32 num_queues, base_queue;
964 /* get number of interrupts, queues, and vfs */
965 val = rd32(hw, I40E_GLPCI_CNF2);
966 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
967 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
968 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
969 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
971 val = rd32(hw, I40E_PFLAN_QALLOC);
972 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
973 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
974 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
975 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
976 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
977 num_queues = (j - base_queue) + 1;
981 val = rd32(hw, I40E_PF_VT_PFALLOC);
982 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
983 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
984 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
985 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
986 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
987 num_vfs = (j - i) + 1;
991 /* stop all the interrupts */
992 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
993 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
994 for (i = 0; i < num_pf_int - 2; i++)
995 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
997 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
998 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
999 wr32(hw, I40E_PFINT_LNKLST0, val);
1000 for (i = 0; i < num_pf_int - 2; i++)
1001 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1002 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1003 for (i = 0; i < num_vfs; i++)
1004 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1005 for (i = 0; i < num_vf_int - 2; i++)
1006 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1008 /* warn the HW of the coming Tx disables */
1009 for (i = 0; i < num_queues; i++) {
1010 u32 abs_queue_idx = base_queue + i;
1013 if (abs_queue_idx >= 128) {
1014 reg_block = abs_queue_idx / 128;
1015 abs_queue_idx %= 128;
1018 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1019 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1020 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1021 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1023 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1025 i40e_usec_delay(400);
1027 /* stop all the queues */
1028 for (i = 0; i < num_queues; i++) {
1029 wr32(hw, I40E_QINT_TQCTL(i), 0);
1030 wr32(hw, I40E_QTX_ENA(i), 0);
1031 wr32(hw, I40E_QINT_RQCTL(i), 0);
1032 wr32(hw, I40E_QRX_ENA(i), 0);
1035 /* short wait for all queue disables to settle */
1036 i40e_usec_delay(50);
1040 * i40e_clear_pxe_mode - clear pxe operations mode
1041 * @hw: pointer to the hw struct
1043 * Make sure all PXE mode settings are cleared, including things
1044 * like descriptor fetch/write-back mode.
1046 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1048 if (i40e_check_asq_alive(hw))
1049 i40e_aq_clear_pxe_mode(hw, NULL);
1053 * i40e_led_is_mine - helper to find matching led
1054 * @hw: pointer to the hw struct
1055 * @idx: index into GPIO registers
1057 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1059 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1064 if (!hw->func_caps.led[idx])
1067 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1068 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1069 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1071 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1072 * if it is not our port then ignore
1074 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1081 #define I40E_COMBINED_ACTIVITY 0xA
1082 #define I40E_FILTER_ACTIVITY 0xE
1083 #define I40E_LINK_ACTIVITY 0xC
1084 #define I40E_MAC_ACTIVITY 0xD
1085 #define I40E_LED0 22
1088 * i40e_led_get - return current on/off mode
1089 * @hw: pointer to the hw struct
1091 * The value returned is the 'mode' field as defined in the
1092 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1093 * values are variations of possible behaviors relating to
1094 * blink, link, and wire.
1096 u32 i40e_led_get(struct i40e_hw *hw)
1098 u32 current_mode = 0;
1102 /* as per the documentation GPIO 22-29 are the LED
1103 * GPIO pins named LED0..LED7
1105 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1106 u32 gpio_val = i40e_led_is_mine(hw, i);
1111 /* ignore gpio LED src mode entries related to the activity LEDs */
1112 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1113 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1114 switch (current_mode) {
1115 case I40E_COMBINED_ACTIVITY:
1116 case I40E_FILTER_ACTIVITY:
1117 case I40E_MAC_ACTIVITY:
1123 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1124 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1132 * i40e_led_set - set new on/off mode
1133 * @hw: pointer to the hw struct
1134 * @mode: 0=off, 0xf=on (else see manual for mode details)
1135 * @blink: true if the LED should blink when on, false if steady
1137 * if this function is used to turn on the blink it should
1138 * be used to disable the blink when restoring the original state.
1140 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1142 u32 current_mode = 0;
1145 if (mode & 0xfffffff0)
1146 DEBUGOUT1("invalid mode passed in %X\n", mode);
1148 /* as per the documentation GPIO 22-29 are the LED
1149 * GPIO pins named LED0..LED7
1151 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1152 u32 gpio_val = i40e_led_is_mine(hw, i);
1157 /* ignore gpio LED src mode entries related to the activity LEDs */
1158 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1159 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1160 switch (current_mode) {
1161 case I40E_COMBINED_ACTIVITY:
1162 case I40E_FILTER_ACTIVITY:
1163 case I40E_MAC_ACTIVITY:
1169 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1170 /* this & is a bit of paranoia, but serves as a range check */
1171 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1172 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1174 if (mode == I40E_LINK_ACTIVITY)
1178 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1180 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1182 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1187 /* Admin command wrappers */
1190 * i40e_aq_get_phy_capabilities
1191 * @hw: pointer to the hw struct
1192 * @abilities: structure for PHY capabilities to be filled
1193 * @qualified_modules: report Qualified Modules
1194 * @report_init: report init capabilities (active are default)
1195 * @cmd_details: pointer to command details structure or NULL
1197 * Returns the various PHY abilities supported on the Port.
1199 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1200 bool qualified_modules, bool report_init,
1201 struct i40e_aq_get_phy_abilities_resp *abilities,
1202 struct i40e_asq_cmd_details *cmd_details)
1204 struct i40e_aq_desc desc;
1205 enum i40e_status_code status;
1206 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1209 return I40E_ERR_PARAM;
1211 i40e_fill_default_direct_cmd_desc(&desc,
1212 i40e_aqc_opc_get_phy_abilities);
1214 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1215 if (abilities_size > I40E_AQ_LARGE_BUF)
1216 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1218 if (qualified_modules)
1219 desc.params.external.param0 |=
1220 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1223 desc.params.external.param0 |=
1224 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1226 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1229 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1230 status = I40E_ERR_UNKNOWN_PHY;
1236 * i40e_aq_set_phy_config
1237 * @hw: pointer to the hw struct
1238 * @config: structure with PHY configuration to be set
1239 * @cmd_details: pointer to command details structure or NULL
1241 * Set the various PHY configuration parameters
1242 * supported on the Port.One or more of the Set PHY config parameters may be
1243 * ignored in an MFP mode as the PF may not have the privilege to set some
1244 * of the PHY Config parameters. This status will be indicated by the
1247 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1248 struct i40e_aq_set_phy_config *config,
1249 struct i40e_asq_cmd_details *cmd_details)
1251 struct i40e_aq_desc desc;
1252 struct i40e_aq_set_phy_config *cmd =
1253 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1254 enum i40e_status_code status;
1257 return I40E_ERR_PARAM;
1259 i40e_fill_default_direct_cmd_desc(&desc,
1260 i40e_aqc_opc_set_phy_config);
1264 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1271 * @hw: pointer to the hw struct
1273 * Set the requested flow control mode using set_phy_config.
1275 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1276 bool atomic_restart)
1278 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1279 struct i40e_aq_get_phy_abilities_resp abilities;
1280 struct i40e_aq_set_phy_config config;
1281 enum i40e_status_code status;
1282 u8 pause_mask = 0x0;
1288 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1289 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1291 case I40E_FC_RX_PAUSE:
1292 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1294 case I40E_FC_TX_PAUSE:
1295 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1301 /* Get the current phy config */
1302 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1305 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1309 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1310 /* clear the old pause settings */
1311 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1312 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1313 /* set the new abilities */
1314 config.abilities |= pause_mask;
1315 /* If the abilities have changed, then set the new config */
1316 if (config.abilities != abilities.abilities) {
1317 /* Auto restart link so settings take effect */
1319 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1320 /* Copy over all the old settings */
1321 config.phy_type = abilities.phy_type;
1322 config.link_speed = abilities.link_speed;
1323 config.eee_capability = abilities.eee_capability;
1324 config.eeer = abilities.eeer_val;
1325 config.low_power_ctrl = abilities.d3_lpan;
1326 status = i40e_aq_set_phy_config(hw, &config, NULL);
1329 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1331 /* Update the link info */
1332 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1334 /* Wait a little bit (on 40G cards it sometimes takes a really
1335 * long time for link to come back from the atomic reset)
1338 i40e_msec_delay(1000);
1339 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1342 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1348 * i40e_aq_set_mac_config
1349 * @hw: pointer to the hw struct
1350 * @max_frame_size: Maximum Frame Size to be supported by the port
1351 * @crc_en: Tell HW to append a CRC to outgoing frames
1352 * @pacing: Pacing configurations
1353 * @cmd_details: pointer to command details structure or NULL
1355 * Configure MAC settings for frame size, jumbo frame support and the
1356 * addition of a CRC by the hardware.
1358 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1360 bool crc_en, u16 pacing,
1361 struct i40e_asq_cmd_details *cmd_details)
1363 struct i40e_aq_desc desc;
1364 struct i40e_aq_set_mac_config *cmd =
1365 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1366 enum i40e_status_code status;
1368 if (max_frame_size == 0)
1369 return I40E_ERR_PARAM;
1371 i40e_fill_default_direct_cmd_desc(&desc,
1372 i40e_aqc_opc_set_mac_config);
1374 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1375 cmd->params = ((u8)pacing & 0x0F) << 3;
1377 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1385 * i40e_aq_clear_pxe_mode
1386 * @hw: pointer to the hw struct
1387 * @cmd_details: pointer to command details structure or NULL
1389 * Tell the firmware that the driver is taking over from PXE
1391 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1392 struct i40e_asq_cmd_details *cmd_details)
1394 enum i40e_status_code status;
1395 struct i40e_aq_desc desc;
1396 struct i40e_aqc_clear_pxe *cmd =
1397 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1399 i40e_fill_default_direct_cmd_desc(&desc,
1400 i40e_aqc_opc_clear_pxe_mode);
1404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1406 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1412 * i40e_aq_set_link_restart_an
1413 * @hw: pointer to the hw struct
1414 * @enable_link: if true: enable link, if false: disable link
1415 * @cmd_details: pointer to command details structure or NULL
1417 * Sets up the link and restarts the Auto-Negotiation over the link.
1419 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1420 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1422 struct i40e_aq_desc desc;
1423 struct i40e_aqc_set_link_restart_an *cmd =
1424 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1425 enum i40e_status_code status;
1427 i40e_fill_default_direct_cmd_desc(&desc,
1428 i40e_aqc_opc_set_link_restart_an);
1430 cmd->command = I40E_AQ_PHY_RESTART_AN;
1432 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1434 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1436 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1442 * i40e_aq_get_link_info
1443 * @hw: pointer to the hw struct
1444 * @enable_lse: enable/disable LinkStatusEvent reporting
1445 * @link: pointer to link status structure - optional
1446 * @cmd_details: pointer to command details structure or NULL
1448 * Returns the link status of the adapter.
1450 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1451 bool enable_lse, struct i40e_link_status *link,
1452 struct i40e_asq_cmd_details *cmd_details)
1454 struct i40e_aq_desc desc;
1455 struct i40e_aqc_get_link_status *resp =
1456 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1457 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1458 enum i40e_status_code status;
1459 bool tx_pause, rx_pause;
1462 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1465 command_flags = I40E_AQ_LSE_ENABLE;
1467 command_flags = I40E_AQ_LSE_DISABLE;
1468 resp->command_flags = CPU_TO_LE16(command_flags);
1470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1472 if (status != I40E_SUCCESS)
1473 goto aq_get_link_info_exit;
1475 /* save off old link status information */
1476 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1477 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1479 /* update link status */
1480 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1481 hw->phy.media_type = i40e_get_media_type(hw);
1482 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1483 hw_link_info->link_info = resp->link_info;
1484 hw_link_info->an_info = resp->an_info;
1485 hw_link_info->ext_info = resp->ext_info;
1486 hw_link_info->loopback = resp->loopback;
1487 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1488 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1490 /* update fc info */
1491 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1492 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1493 if (tx_pause & rx_pause)
1494 hw->fc.current_mode = I40E_FC_FULL;
1496 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1498 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1500 hw->fc.current_mode = I40E_FC_NONE;
1502 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1503 hw_link_info->crc_enable = true;
1505 hw_link_info->crc_enable = false;
1507 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1508 hw_link_info->lse_enable = true;
1510 hw_link_info->lse_enable = false;
1512 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1513 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1514 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1516 /* save link status information */
1518 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1519 I40E_NONDMA_TO_NONDMA);
1521 /* flag cleared so helper functions don't call AQ again */
1522 hw->phy.get_link_info = false;
1524 aq_get_link_info_exit:
1529 * i40e_aq_set_phy_int_mask
1530 * @hw: pointer to the hw struct
1531 * @mask: interrupt mask to be set
1532 * @cmd_details: pointer to command details structure or NULL
1534 * Set link interrupt mask.
1536 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1538 struct i40e_asq_cmd_details *cmd_details)
1540 struct i40e_aq_desc desc;
1541 struct i40e_aqc_set_phy_int_mask *cmd =
1542 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1543 enum i40e_status_code status;
1545 i40e_fill_default_direct_cmd_desc(&desc,
1546 i40e_aqc_opc_set_phy_int_mask);
1548 cmd->event_mask = CPU_TO_LE16(mask);
1550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1556 * i40e_aq_get_local_advt_reg
1557 * @hw: pointer to the hw struct
1558 * @advt_reg: local AN advertisement register value
1559 * @cmd_details: pointer to command details structure or NULL
1561 * Get the Local AN advertisement register value.
1563 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1565 struct i40e_asq_cmd_details *cmd_details)
1567 struct i40e_aq_desc desc;
1568 struct i40e_aqc_an_advt_reg *resp =
1569 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1570 enum i40e_status_code status;
1572 i40e_fill_default_direct_cmd_desc(&desc,
1573 i40e_aqc_opc_get_local_advt_reg);
1575 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1577 if (status != I40E_SUCCESS)
1578 goto aq_get_local_advt_reg_exit;
1580 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1581 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1583 aq_get_local_advt_reg_exit:
1588 * i40e_aq_set_local_advt_reg
1589 * @hw: pointer to the hw struct
1590 * @advt_reg: local AN advertisement register value
1591 * @cmd_details: pointer to command details structure or NULL
1593 * Get the Local AN advertisement register value.
1595 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1597 struct i40e_asq_cmd_details *cmd_details)
1599 struct i40e_aq_desc desc;
1600 struct i40e_aqc_an_advt_reg *cmd =
1601 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1602 enum i40e_status_code status;
1604 i40e_fill_default_direct_cmd_desc(&desc,
1605 i40e_aqc_opc_get_local_advt_reg);
1607 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1608 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1610 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1616 * i40e_aq_get_partner_advt
1617 * @hw: pointer to the hw struct
1618 * @advt_reg: AN partner advertisement register value
1619 * @cmd_details: pointer to command details structure or NULL
1621 * Get the link partner AN advertisement register value.
1623 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1625 struct i40e_asq_cmd_details *cmd_details)
1627 struct i40e_aq_desc desc;
1628 struct i40e_aqc_an_advt_reg *resp =
1629 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1630 enum i40e_status_code status;
1632 i40e_fill_default_direct_cmd_desc(&desc,
1633 i40e_aqc_opc_get_partner_advt);
1635 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1637 if (status != I40E_SUCCESS)
1638 goto aq_get_partner_advt_exit;
1640 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1641 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1643 aq_get_partner_advt_exit:
1648 * i40e_aq_set_lb_modes
1649 * @hw: pointer to the hw struct
1650 * @lb_modes: loopback mode to be set
1651 * @cmd_details: pointer to command details structure or NULL
1653 * Sets loopback modes.
1655 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1657 struct i40e_asq_cmd_details *cmd_details)
1659 struct i40e_aq_desc desc;
1660 struct i40e_aqc_set_lb_mode *cmd =
1661 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1662 enum i40e_status_code status;
1664 i40e_fill_default_direct_cmd_desc(&desc,
1665 i40e_aqc_opc_set_lb_modes);
1667 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1669 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1675 * i40e_aq_set_phy_debug
1676 * @hw: pointer to the hw struct
1677 * @cmd_flags: debug command flags
1678 * @cmd_details: pointer to command details structure or NULL
1680 * Reset the external PHY.
1682 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1683 struct i40e_asq_cmd_details *cmd_details)
1685 struct i40e_aq_desc desc;
1686 struct i40e_aqc_set_phy_debug *cmd =
1687 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1688 enum i40e_status_code status;
1690 i40e_fill_default_direct_cmd_desc(&desc,
1691 i40e_aqc_opc_set_phy_debug);
1693 cmd->command_flags = cmd_flags;
1695 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1702 * @hw: pointer to the hw struct
1703 * @vsi_ctx: pointer to a vsi context struct
1704 * @cmd_details: pointer to command details structure or NULL
1706 * Add a VSI context to the hardware.
1708 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1709 struct i40e_vsi_context *vsi_ctx,
1710 struct i40e_asq_cmd_details *cmd_details)
1712 struct i40e_aq_desc desc;
1713 struct i40e_aqc_add_get_update_vsi *cmd =
1714 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1715 struct i40e_aqc_add_get_update_vsi_completion *resp =
1716 (struct i40e_aqc_add_get_update_vsi_completion *)
1718 enum i40e_status_code status;
1720 i40e_fill_default_direct_cmd_desc(&desc,
1721 i40e_aqc_opc_add_vsi);
1723 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1724 cmd->connection_type = vsi_ctx->connection_type;
1725 cmd->vf_id = vsi_ctx->vf_num;
1726 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1728 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1730 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1731 sizeof(vsi_ctx->info), cmd_details);
1733 if (status != I40E_SUCCESS)
1734 goto aq_add_vsi_exit;
1736 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1737 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1738 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1739 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1746 * i40e_aq_set_default_vsi
1747 * @hw: pointer to the hw struct
1749 * @cmd_details: pointer to command details structure or NULL
1751 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1753 struct i40e_asq_cmd_details *cmd_details)
1755 struct i40e_aq_desc desc;
1756 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1757 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1759 enum i40e_status_code status;
1761 i40e_fill_default_direct_cmd_desc(&desc,
1762 i40e_aqc_opc_set_vsi_promiscuous_modes);
1764 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1765 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1766 cmd->seid = CPU_TO_LE16(seid);
1768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1774 * i40e_aq_set_vsi_unicast_promiscuous
1775 * @hw: pointer to the hw struct
1777 * @set: set unicast promiscuous enable/disable
1778 * @cmd_details: pointer to command details structure or NULL
1780 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1782 struct i40e_asq_cmd_details *cmd_details)
1784 struct i40e_aq_desc desc;
1785 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1786 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1787 enum i40e_status_code status;
1790 i40e_fill_default_direct_cmd_desc(&desc,
1791 i40e_aqc_opc_set_vsi_promiscuous_modes);
1794 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1796 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1798 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1800 cmd->seid = CPU_TO_LE16(seid);
1801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1807 * i40e_aq_set_vsi_multicast_promiscuous
1808 * @hw: pointer to the hw struct
1810 * @set: set multicast promiscuous enable/disable
1811 * @cmd_details: pointer to command details structure or NULL
1813 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1814 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1816 struct i40e_aq_desc desc;
1817 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1818 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1819 enum i40e_status_code status;
1822 i40e_fill_default_direct_cmd_desc(&desc,
1823 i40e_aqc_opc_set_vsi_promiscuous_modes);
1826 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1828 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1830 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1832 cmd->seid = CPU_TO_LE16(seid);
1833 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1839 * i40e_aq_set_vsi_broadcast
1840 * @hw: pointer to the hw struct
1842 * @set_filter: true to set filter, false to clear filter
1843 * @cmd_details: pointer to command details structure or NULL
1845 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1847 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1848 u16 seid, bool set_filter,
1849 struct i40e_asq_cmd_details *cmd_details)
1851 struct i40e_aq_desc desc;
1852 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1853 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1854 enum i40e_status_code status;
1856 i40e_fill_default_direct_cmd_desc(&desc,
1857 i40e_aqc_opc_set_vsi_promiscuous_modes);
1860 cmd->promiscuous_flags
1861 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1863 cmd->promiscuous_flags
1864 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1866 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1867 cmd->seid = CPU_TO_LE16(seid);
1868 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1874 * i40e_get_vsi_params - get VSI configuration info
1875 * @hw: pointer to the hw struct
1876 * @vsi_ctx: pointer to a vsi context struct
1877 * @cmd_details: pointer to command details structure or NULL
1879 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1880 struct i40e_vsi_context *vsi_ctx,
1881 struct i40e_asq_cmd_details *cmd_details)
1883 struct i40e_aq_desc desc;
1884 struct i40e_aqc_add_get_update_vsi *cmd =
1885 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1886 struct i40e_aqc_add_get_update_vsi_completion *resp =
1887 (struct i40e_aqc_add_get_update_vsi_completion *)
1889 enum i40e_status_code status;
1891 UNREFERENCED_1PARAMETER(cmd_details);
1892 i40e_fill_default_direct_cmd_desc(&desc,
1893 i40e_aqc_opc_get_vsi_parameters);
1895 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1897 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1899 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1900 sizeof(vsi_ctx->info), NULL);
1902 if (status != I40E_SUCCESS)
1903 goto aq_get_vsi_params_exit;
1905 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1906 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1907 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1908 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1910 aq_get_vsi_params_exit:
1915 * i40e_aq_update_vsi_params
1916 * @hw: pointer to the hw struct
1917 * @vsi_ctx: pointer to a vsi context struct
1918 * @cmd_details: pointer to command details structure or NULL
1920 * Update a VSI context.
1922 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1923 struct i40e_vsi_context *vsi_ctx,
1924 struct i40e_asq_cmd_details *cmd_details)
1926 struct i40e_aq_desc desc;
1927 struct i40e_aqc_add_get_update_vsi *cmd =
1928 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1929 enum i40e_status_code status;
1931 i40e_fill_default_direct_cmd_desc(&desc,
1932 i40e_aqc_opc_update_vsi_parameters);
1933 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1935 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1937 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1938 sizeof(vsi_ctx->info), cmd_details);
1944 * i40e_aq_get_switch_config
1945 * @hw: pointer to the hardware structure
1946 * @buf: pointer to the result buffer
1947 * @buf_size: length of input buffer
1948 * @start_seid: seid to start for the report, 0 == beginning
1949 * @cmd_details: pointer to command details structure or NULL
1951 * Fill the buf with switch configuration returned from AdminQ command
1953 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1954 struct i40e_aqc_get_switch_config_resp *buf,
1955 u16 buf_size, u16 *start_seid,
1956 struct i40e_asq_cmd_details *cmd_details)
1958 struct i40e_aq_desc desc;
1959 struct i40e_aqc_switch_seid *scfg =
1960 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1961 enum i40e_status_code status;
1963 i40e_fill_default_direct_cmd_desc(&desc,
1964 i40e_aqc_opc_get_switch_config);
1965 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1966 if (buf_size > I40E_AQ_LARGE_BUF)
1967 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1968 scfg->seid = CPU_TO_LE16(*start_seid);
1970 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1971 *start_seid = LE16_TO_CPU(scfg->seid);
1977 * i40e_aq_get_firmware_version
1978 * @hw: pointer to the hw struct
1979 * @fw_major_version: firmware major version
1980 * @fw_minor_version: firmware minor version
1981 * @fw_build: firmware build number
1982 * @api_major_version: major queue version
1983 * @api_minor_version: minor queue version
1984 * @cmd_details: pointer to command details structure or NULL
1986 * Get the firmware version from the admin queue commands
1988 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1989 u16 *fw_major_version, u16 *fw_minor_version,
1991 u16 *api_major_version, u16 *api_minor_version,
1992 struct i40e_asq_cmd_details *cmd_details)
1994 struct i40e_aq_desc desc;
1995 struct i40e_aqc_get_version *resp =
1996 (struct i40e_aqc_get_version *)&desc.params.raw;
1997 enum i40e_status_code status;
1999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003 if (status == I40E_SUCCESS) {
2004 if (fw_major_version != NULL)
2005 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2006 if (fw_minor_version != NULL)
2007 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2008 if (fw_build != NULL)
2009 *fw_build = LE32_TO_CPU(resp->fw_build);
2010 if (api_major_version != NULL)
2011 *api_major_version = LE16_TO_CPU(resp->api_major);
2012 if (api_minor_version != NULL)
2013 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2015 /* A workaround to fix the API version in SW */
2016 if (api_major_version && api_minor_version &&
2017 fw_major_version && fw_minor_version &&
2018 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2019 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2020 (*fw_major_version > 4)))
2021 *api_minor_version = 2;
2028 * i40e_aq_send_driver_version
2029 * @hw: pointer to the hw struct
2030 * @dv: driver's major, minor version
2031 * @cmd_details: pointer to command details structure or NULL
2033 * Send the driver version to the firmware
2035 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2036 struct i40e_driver_version *dv,
2037 struct i40e_asq_cmd_details *cmd_details)
2039 struct i40e_aq_desc desc;
2040 struct i40e_aqc_driver_version *cmd =
2041 (struct i40e_aqc_driver_version *)&desc.params.raw;
2042 enum i40e_status_code status;
2046 return I40E_ERR_PARAM;
2048 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2050 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2051 cmd->driver_major_ver = dv->major_version;
2052 cmd->driver_minor_ver = dv->minor_version;
2053 cmd->driver_build_ver = dv->build_version;
2054 cmd->driver_subbuild_ver = dv->subbuild_version;
2057 while (len < sizeof(dv->driver_string) &&
2058 (dv->driver_string[len] < 0x80) &&
2059 dv->driver_string[len])
2061 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2068 * i40e_get_link_status - get status of the HW network link
2069 * @hw: pointer to the hw struct
2071 * Returns true if link is up, false if link is down.
2073 * Side effect: LinkStatusEvent reporting becomes enabled
2075 bool i40e_get_link_status(struct i40e_hw *hw)
2077 enum i40e_status_code status = I40E_SUCCESS;
2078 bool link_status = false;
2080 if (hw->phy.get_link_info) {
2081 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2083 if (status != I40E_SUCCESS)
2084 goto i40e_get_link_status_exit;
2087 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2089 i40e_get_link_status_exit:
2094 * i40e_get_link_speed
2095 * @hw: pointer to the hw struct
2097 * Returns the link speed of the adapter.
2099 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2101 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2102 enum i40e_status_code status = I40E_SUCCESS;
2104 if (hw->phy.get_link_info) {
2105 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2107 if (status != I40E_SUCCESS)
2108 goto i40e_link_speed_exit;
2111 speed = hw->phy.link_info.link_speed;
2113 i40e_link_speed_exit:
2118 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2119 * @hw: pointer to the hw struct
2120 * @uplink_seid: the MAC or other gizmo SEID
2121 * @downlink_seid: the VSI SEID
2122 * @enabled_tc: bitmap of TCs to be enabled
2123 * @default_port: true for default port VSI, false for control port
2124 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2125 * @veb_seid: pointer to where to put the resulting VEB SEID
2126 * @cmd_details: pointer to command details structure or NULL
2128 * This asks the FW to add a VEB between the uplink and downlink
2129 * elements. If the uplink SEID is 0, this will be a floating VEB.
2131 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2132 u16 downlink_seid, u8 enabled_tc,
2133 bool default_port, bool enable_l2_filtering,
2135 struct i40e_asq_cmd_details *cmd_details)
2137 struct i40e_aq_desc desc;
2138 struct i40e_aqc_add_veb *cmd =
2139 (struct i40e_aqc_add_veb *)&desc.params.raw;
2140 struct i40e_aqc_add_veb_completion *resp =
2141 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2142 enum i40e_status_code status;
2145 /* SEIDs need to either both be set or both be 0 for floating VEB */
2146 if (!!uplink_seid != !!downlink_seid)
2147 return I40E_ERR_PARAM;
2149 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2151 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2152 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2153 cmd->enable_tcs = enabled_tc;
2155 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2157 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2159 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2161 if (enable_l2_filtering)
2162 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2164 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2166 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2168 if (!status && veb_seid)
2169 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2175 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2176 * @hw: pointer to the hw struct
2177 * @veb_seid: the SEID of the VEB to query
2178 * @switch_id: the uplink switch id
2179 * @floating: set to true if the VEB is floating
2180 * @statistic_index: index of the stats counter block for this VEB
2181 * @vebs_used: number of VEB's used by function
2182 * @vebs_free: total VEB's not reserved by any function
2183 * @cmd_details: pointer to command details structure or NULL
2185 * This retrieves the parameters for a particular VEB, specified by
2186 * uplink_seid, and returns them to the caller.
2188 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2189 u16 veb_seid, u16 *switch_id,
2190 bool *floating, u16 *statistic_index,
2191 u16 *vebs_used, u16 *vebs_free,
2192 struct i40e_asq_cmd_details *cmd_details)
2194 struct i40e_aq_desc desc;
2195 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2196 (struct i40e_aqc_get_veb_parameters_completion *)
2198 enum i40e_status_code status;
2201 return I40E_ERR_PARAM;
2203 i40e_fill_default_direct_cmd_desc(&desc,
2204 i40e_aqc_opc_get_veb_parameters);
2205 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2212 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2213 if (statistic_index)
2214 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2216 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2218 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2220 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2221 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2232 * i40e_aq_add_macvlan
2233 * @hw: pointer to the hw struct
2234 * @seid: VSI for the mac address
2235 * @mv_list: list of macvlans to be added
2236 * @count: length of the list
2237 * @cmd_details: pointer to command details structure or NULL
2239 * Add MAC/VLAN addresses to the HW filtering
2241 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2242 struct i40e_aqc_add_macvlan_element_data *mv_list,
2243 u16 count, struct i40e_asq_cmd_details *cmd_details)
2245 struct i40e_aq_desc desc;
2246 struct i40e_aqc_macvlan *cmd =
2247 (struct i40e_aqc_macvlan *)&desc.params.raw;
2248 enum i40e_status_code status;
2251 if (count == 0 || !mv_list || !hw)
2252 return I40E_ERR_PARAM;
2254 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2256 /* prep the rest of the request */
2257 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2258 cmd->num_addresses = CPU_TO_LE16(count);
2259 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2263 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2264 if (buf_size > I40E_AQ_LARGE_BUF)
2265 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2267 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2274 * i40e_aq_remove_macvlan
2275 * @hw: pointer to the hw struct
2276 * @seid: VSI for the mac address
2277 * @mv_list: list of macvlans to be removed
2278 * @count: length of the list
2279 * @cmd_details: pointer to command details structure or NULL
2281 * Remove MAC/VLAN addresses from the HW filtering
2283 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2284 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2285 u16 count, struct i40e_asq_cmd_details *cmd_details)
2287 struct i40e_aq_desc desc;
2288 struct i40e_aqc_macvlan *cmd =
2289 (struct i40e_aqc_macvlan *)&desc.params.raw;
2290 enum i40e_status_code status;
2293 if (count == 0 || !mv_list || !hw)
2294 return I40E_ERR_PARAM;
2296 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2298 /* prep the rest of the request */
2299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2300 cmd->num_addresses = CPU_TO_LE16(count);
2301 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2305 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2306 if (buf_size > I40E_AQ_LARGE_BUF)
2307 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2309 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2316 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2317 * @hw: pointer to the hw struct
2318 * @seid: VSI for the vlan filters
2319 * @v_list: list of vlan filters to be added
2320 * @count: length of the list
2321 * @cmd_details: pointer to command details structure or NULL
2323 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2324 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2325 u8 count, struct i40e_asq_cmd_details *cmd_details)
2327 struct i40e_aq_desc desc;
2328 struct i40e_aqc_macvlan *cmd =
2329 (struct i40e_aqc_macvlan *)&desc.params.raw;
2330 enum i40e_status_code status;
2333 if (count == 0 || !v_list || !hw)
2334 return I40E_ERR_PARAM;
2336 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2338 /* prep the rest of the request */
2339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2340 cmd->num_addresses = CPU_TO_LE16(count);
2341 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2345 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2346 if (buf_size > I40E_AQ_LARGE_BUF)
2347 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2349 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2356 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2357 * @hw: pointer to the hw struct
2358 * @seid: VSI for the vlan filters
2359 * @v_list: list of macvlans to be removed
2360 * @count: length of the list
2361 * @cmd_details: pointer to command details structure or NULL
2363 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2364 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2365 u8 count, struct i40e_asq_cmd_details *cmd_details)
2367 struct i40e_aq_desc desc;
2368 struct i40e_aqc_macvlan *cmd =
2369 (struct i40e_aqc_macvlan *)&desc.params.raw;
2370 enum i40e_status_code status;
2373 if (count == 0 || !v_list || !hw)
2374 return I40E_ERR_PARAM;
2376 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2378 /* prep the rest of the request */
2379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2380 cmd->num_addresses = CPU_TO_LE16(count);
2381 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2385 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2386 if (buf_size > I40E_AQ_LARGE_BUF)
2387 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2389 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2396 * i40e_aq_send_msg_to_vf
2397 * @hw: pointer to the hardware structure
2398 * @vfid: vf id to send msg
2399 * @v_opcode: opcodes for VF-PF communication
2400 * @v_retval: return error code
2401 * @msg: pointer to the msg buffer
2402 * @msglen: msg length
2403 * @cmd_details: pointer to command details
2407 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2408 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2409 struct i40e_asq_cmd_details *cmd_details)
2411 struct i40e_aq_desc desc;
2412 struct i40e_aqc_pf_vf_message *cmd =
2413 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2414 enum i40e_status_code status;
2416 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2417 cmd->id = CPU_TO_LE32(vfid);
2418 desc.cookie_high = CPU_TO_LE32(v_opcode);
2419 desc.cookie_low = CPU_TO_LE32(v_retval);
2420 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2422 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2424 if (msglen > I40E_AQ_LARGE_BUF)
2425 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2426 desc.datalen = CPU_TO_LE16(msglen);
2428 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2434 * i40e_aq_debug_read_register
2435 * @hw: pointer to the hw struct
2436 * @reg_addr: register address
2437 * @reg_val: register value
2438 * @cmd_details: pointer to command details structure or NULL
2440 * Read the register using the admin queue commands
2442 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2443 u32 reg_addr, u64 *reg_val,
2444 struct i40e_asq_cmd_details *cmd_details)
2446 struct i40e_aq_desc desc;
2447 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2448 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2449 enum i40e_status_code status;
2451 if (reg_val == NULL)
2452 return I40E_ERR_PARAM;
2454 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2456 cmd_resp->address = CPU_TO_LE32(reg_addr);
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2460 if (status == I40E_SUCCESS) {
2461 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2462 (u64)LE32_TO_CPU(cmd_resp->value_low);
2469 * i40e_aq_debug_write_register
2470 * @hw: pointer to the hw struct
2471 * @reg_addr: register address
2472 * @reg_val: register value
2473 * @cmd_details: pointer to command details structure or NULL
2475 * Write to a register using the admin queue commands
2477 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2478 u32 reg_addr, u64 reg_val,
2479 struct i40e_asq_cmd_details *cmd_details)
2481 struct i40e_aq_desc desc;
2482 struct i40e_aqc_debug_reg_read_write *cmd =
2483 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2484 enum i40e_status_code status;
2486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2488 cmd->address = CPU_TO_LE32(reg_addr);
2489 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2490 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 * i40e_aq_get_hmc_resource_profile
2499 * @hw: pointer to the hw struct
2500 * @profile: type of profile the HMC is to be set as
2501 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2502 * @cmd_details: pointer to command details structure or NULL
2504 * query the HMC profile of the device.
2506 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2507 enum i40e_aq_hmc_profile *profile,
2508 u8 *pe_vf_enabled_count,
2509 struct i40e_asq_cmd_details *cmd_details)
2511 struct i40e_aq_desc desc;
2512 struct i40e_aq_get_set_hmc_resource_profile *resp =
2513 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2514 enum i40e_status_code status;
2516 i40e_fill_default_direct_cmd_desc(&desc,
2517 i40e_aqc_opc_query_hmc_resource_profile);
2518 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2520 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2521 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2522 *pe_vf_enabled_count = resp->pe_vf_enabled &
2523 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2529 * i40e_aq_set_hmc_resource_profile
2530 * @hw: pointer to the hw struct
2531 * @profile: type of profile the HMC is to be set as
2532 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2533 * @cmd_details: pointer to command details structure or NULL
2535 * set the HMC profile of the device.
2537 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2538 enum i40e_aq_hmc_profile profile,
2539 u8 pe_vf_enabled_count,
2540 struct i40e_asq_cmd_details *cmd_details)
2542 struct i40e_aq_desc desc;
2543 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2544 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2545 enum i40e_status_code status;
2547 i40e_fill_default_direct_cmd_desc(&desc,
2548 i40e_aqc_opc_set_hmc_resource_profile);
2550 cmd->pm_profile = (u8)profile;
2551 cmd->pe_vf_enabled = pe_vf_enabled_count;
2553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559 * i40e_aq_request_resource
2560 * @hw: pointer to the hw struct
2561 * @resource: resource id
2562 * @access: access type
2563 * @sdp_number: resource number
2564 * @timeout: the maximum time in ms that the driver may hold the resource
2565 * @cmd_details: pointer to command details structure or NULL
2567 * requests common resource using the admin queue commands
2569 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2570 enum i40e_aq_resources_ids resource,
2571 enum i40e_aq_resource_access_type access,
2572 u8 sdp_number, u64 *timeout,
2573 struct i40e_asq_cmd_details *cmd_details)
2575 struct i40e_aq_desc desc;
2576 struct i40e_aqc_request_resource *cmd_resp =
2577 (struct i40e_aqc_request_resource *)&desc.params.raw;
2578 enum i40e_status_code status;
2580 DEBUGFUNC("i40e_aq_request_resource");
2582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2584 cmd_resp->resource_id = CPU_TO_LE16(resource);
2585 cmd_resp->access_type = CPU_TO_LE16(access);
2586 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2589 /* The completion specifies the maximum time in ms that the driver
2590 * may hold the resource in the Timeout field.
2591 * If the resource is held by someone else, the command completes with
2592 * busy return value and the timeout field indicates the maximum time
2593 * the current owner of the resource has to free it.
2595 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2596 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2602 * i40e_aq_release_resource
2603 * @hw: pointer to the hw struct
2604 * @resource: resource id
2605 * @sdp_number: resource number
2606 * @cmd_details: pointer to command details structure or NULL
2608 * release common resource using the admin queue commands
2610 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2611 enum i40e_aq_resources_ids resource,
2613 struct i40e_asq_cmd_details *cmd_details)
2615 struct i40e_aq_desc desc;
2616 struct i40e_aqc_request_resource *cmd =
2617 (struct i40e_aqc_request_resource *)&desc.params.raw;
2618 enum i40e_status_code status;
2620 DEBUGFUNC("i40e_aq_release_resource");
2622 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2624 cmd->resource_id = CPU_TO_LE16(resource);
2625 cmd->resource_number = CPU_TO_LE32(sdp_number);
2627 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2634 * @hw: pointer to the hw struct
2635 * @module_pointer: module pointer location in words from the NVM beginning
2636 * @offset: byte offset from the module beginning
2637 * @length: length of the section to be read (in bytes from the offset)
2638 * @data: command buffer (size [bytes] = length)
2639 * @last_command: tells if this is the last command in a series
2640 * @cmd_details: pointer to command details structure or NULL
2642 * Read the NVM using the admin queue commands
2644 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2645 u32 offset, u16 length, void *data,
2647 struct i40e_asq_cmd_details *cmd_details)
2649 struct i40e_aq_desc desc;
2650 struct i40e_aqc_nvm_update *cmd =
2651 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2652 enum i40e_status_code status;
2654 DEBUGFUNC("i40e_aq_read_nvm");
2656 /* In offset the highest byte must be zeroed. */
2657 if (offset & 0xFF000000) {
2658 status = I40E_ERR_PARAM;
2659 goto i40e_aq_read_nvm_exit;
2662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2664 /* If this is the last command in a series, set the proper flag. */
2666 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2667 cmd->module_pointer = module_pointer;
2668 cmd->offset = CPU_TO_LE32(offset);
2669 cmd->length = CPU_TO_LE16(length);
2671 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2672 if (length > I40E_AQ_LARGE_BUF)
2673 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2675 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2677 i40e_aq_read_nvm_exit:
2682 * i40e_aq_read_nvm_config - read an nvm config block
2683 * @hw: pointer to the hw struct
2684 * @cmd_flags: NVM access admin command bits
2685 * @field_id: field or feature id
2686 * @data: buffer for result
2687 * @buf_size: buffer size
2688 * @element_count: pointer to count of elements read by FW
2689 * @cmd_details: pointer to command details structure or NULL
2691 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2692 u8 cmd_flags, u32 field_id, void *data,
2693 u16 buf_size, u16 *element_count,
2694 struct i40e_asq_cmd_details *cmd_details)
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_nvm_config_read *cmd =
2698 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2699 enum i40e_status_code status;
2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2702 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2703 if (buf_size > I40E_AQ_LARGE_BUF)
2704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2706 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2707 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2708 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2709 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2711 cmd->element_id_msw = 0;
2713 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2715 if (!status && element_count)
2716 *element_count = LE16_TO_CPU(cmd->element_count);
2722 * i40e_aq_write_nvm_config - write an nvm config block
2723 * @hw: pointer to the hw struct
2724 * @cmd_flags: NVM access admin command bits
2725 * @data: buffer for result
2726 * @buf_size: buffer size
2727 * @element_count: count of elements to be written
2728 * @cmd_details: pointer to command details structure or NULL
2730 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2731 u8 cmd_flags, void *data, u16 buf_size,
2733 struct i40e_asq_cmd_details *cmd_details)
2735 struct i40e_aq_desc desc;
2736 struct i40e_aqc_nvm_config_write *cmd =
2737 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2738 enum i40e_status_code status;
2740 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2741 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2742 if (buf_size > I40E_AQ_LARGE_BUF)
2743 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2745 cmd->element_count = CPU_TO_LE16(element_count);
2746 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2747 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2754 * @hw: pointer to the hw struct
2755 * @module_pointer: module pointer location in words from the NVM beginning
2756 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2757 * @length: length of the section to be erased (expressed in 4 KB)
2758 * @last_command: tells if this is the last command in a series
2759 * @cmd_details: pointer to command details structure or NULL
2761 * Erase the NVM sector using the admin queue commands
2763 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2764 u32 offset, u16 length, bool last_command,
2765 struct i40e_asq_cmd_details *cmd_details)
2767 struct i40e_aq_desc desc;
2768 struct i40e_aqc_nvm_update *cmd =
2769 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2770 enum i40e_status_code status;
2772 DEBUGFUNC("i40e_aq_erase_nvm");
2774 /* In offset the highest byte must be zeroed. */
2775 if (offset & 0xFF000000) {
2776 status = I40E_ERR_PARAM;
2777 goto i40e_aq_erase_nvm_exit;
2780 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2782 /* If this is the last command in a series, set the proper flag. */
2784 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2785 cmd->module_pointer = module_pointer;
2786 cmd->offset = CPU_TO_LE32(offset);
2787 cmd->length = CPU_TO_LE16(length);
2789 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2791 i40e_aq_erase_nvm_exit:
2795 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2796 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2797 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2798 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2799 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2800 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2801 #define I40E_DEV_FUNC_CAP_VF 0x13
2802 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2803 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2804 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2805 #define I40E_DEV_FUNC_CAP_VSI 0x17
2806 #define I40E_DEV_FUNC_CAP_DCB 0x18
2807 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2808 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2809 #define I40E_DEV_FUNC_CAP_RSS 0x40
2810 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2811 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2812 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2813 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2814 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2815 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2816 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2817 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2818 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2819 #define I40E_DEV_FUNC_CAP_LED 0x61
2820 #define I40E_DEV_FUNC_CAP_SDP 0x62
2821 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2824 * i40e_parse_discover_capabilities
2825 * @hw: pointer to the hw struct
2826 * @buff: pointer to a buffer containing device/function capability records
2827 * @cap_count: number of capability records in the list
2828 * @list_type_opc: type of capabilities list to parse
2830 * Parse the device/function capabilities list.
2832 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2834 enum i40e_admin_queue_opc list_type_opc)
2836 struct i40e_aqc_list_capabilities_element_resp *cap;
2837 u32 valid_functions, num_functions;
2838 u32 number, logical_id, phys_id;
2839 struct i40e_hw_capabilities *p;
2843 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2845 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2846 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2847 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2848 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2852 for (i = 0; i < cap_count; i++, cap++) {
2853 id = LE16_TO_CPU(cap->id);
2854 number = LE32_TO_CPU(cap->number);
2855 logical_id = LE32_TO_CPU(cap->logical_id);
2856 phys_id = LE32_TO_CPU(cap->phys_id);
2859 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2860 p->switch_mode = number;
2862 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2863 p->management_mode = number;
2865 case I40E_DEV_FUNC_CAP_NPAR:
2866 p->npar_enable = number;
2868 case I40E_DEV_FUNC_CAP_OS2BMC:
2871 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2872 p->valid_functions = number;
2874 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2876 p->sr_iov_1_1 = true;
2878 case I40E_DEV_FUNC_CAP_VF:
2879 p->num_vfs = number;
2880 p->vf_base_id = logical_id;
2882 case I40E_DEV_FUNC_CAP_VMDQ:
2886 case I40E_DEV_FUNC_CAP_802_1_QBG:
2888 p->evb_802_1_qbg = true;
2890 case I40E_DEV_FUNC_CAP_802_1_QBH:
2892 p->evb_802_1_qbh = true;
2894 case I40E_DEV_FUNC_CAP_VSI:
2895 p->num_vsis = number;
2897 case I40E_DEV_FUNC_CAP_DCB:
2900 p->enabled_tcmap = logical_id;
2904 case I40E_DEV_FUNC_CAP_FCOE:
2908 case I40E_DEV_FUNC_CAP_ISCSI:
2912 case I40E_DEV_FUNC_CAP_RSS:
2914 p->rss_table_size = number;
2915 p->rss_table_entry_width = logical_id;
2917 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2918 p->num_rx_qp = number;
2919 p->base_queue = phys_id;
2921 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2922 p->num_tx_qp = number;
2923 p->base_queue = phys_id;
2925 case I40E_DEV_FUNC_CAP_MSIX:
2926 p->num_msix_vectors = number;
2928 case I40E_DEV_FUNC_CAP_MSIX_VF:
2929 p->num_msix_vectors_vf = number;
2931 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2933 p->mfp_mode_1 = true;
2935 case I40E_DEV_FUNC_CAP_CEM:
2939 case I40E_DEV_FUNC_CAP_IWARP:
2943 case I40E_DEV_FUNC_CAP_LED:
2944 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2945 p->led[phys_id] = true;
2947 case I40E_DEV_FUNC_CAP_SDP:
2948 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2949 p->sdp[phys_id] = true;
2951 case I40E_DEV_FUNC_CAP_MDIO:
2953 p->mdio_port_num = phys_id;
2954 p->mdio_port_mode = logical_id;
2957 case I40E_DEV_FUNC_CAP_IEEE_1588:
2959 p->ieee_1588 = true;
2961 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2963 p->fd_filters_guaranteed = number;
2964 p->fd_filters_best_effort = logical_id;
2971 #ifdef I40E_FCOE_ENA
2972 /* Software override ensuring FCoE is disabled if npar or mfp
2973 * mode because it is not supported in these modes.
2975 if (p->npar_enable || p->mfp_mode_1)
2978 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2982 /* count the enabled ports (aka the "not disabled" ports) */
2984 for (i = 0; i < 4; i++) {
2985 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2988 /* use AQ read to get the physical register offset instead
2989 * of the port relative offset
2991 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2992 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2996 valid_functions = p->valid_functions;
2998 while (valid_functions) {
2999 if (valid_functions & 1)
3001 valid_functions >>= 1;
3004 /* partition id is 1-based, and functions are evenly spread
3005 * across the ports as partitions
3007 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3008 hw->num_partitions = num_functions / hw->num_ports;
3010 /* additional HW specific goodies that might
3011 * someday be HW version specific
3013 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3017 * i40e_aq_discover_capabilities
3018 * @hw: pointer to the hw struct
3019 * @buff: a virtual buffer to hold the capabilities
3020 * @buff_size: Size of the virtual buffer
3021 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3022 * @list_type_opc: capabilities type to discover - pass in the command opcode
3023 * @cmd_details: pointer to command details structure or NULL
3025 * Get the device capabilities descriptions from the firmware
3027 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3028 void *buff, u16 buff_size, u16 *data_size,
3029 enum i40e_admin_queue_opc list_type_opc,
3030 struct i40e_asq_cmd_details *cmd_details)
3032 struct i40e_aqc_list_capabilites *cmd;
3033 struct i40e_aq_desc desc;
3034 enum i40e_status_code status = I40E_SUCCESS;
3036 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3038 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3039 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3040 status = I40E_ERR_PARAM;
3044 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3046 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3047 if (buff_size > I40E_AQ_LARGE_BUF)
3048 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3050 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3051 *data_size = LE16_TO_CPU(desc.datalen);
3056 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3064 * i40e_aq_update_nvm
3065 * @hw: pointer to the hw struct
3066 * @module_pointer: module pointer location in words from the NVM beginning
3067 * @offset: byte offset from the module beginning
3068 * @length: length of the section to be written (in bytes from the offset)
3069 * @data: command buffer (size [bytes] = length)
3070 * @last_command: tells if this is the last command in a series
3071 * @cmd_details: pointer to command details structure or NULL
3073 * Update the NVM using the admin queue commands
3075 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3076 u32 offset, u16 length, void *data,
3078 struct i40e_asq_cmd_details *cmd_details)
3080 struct i40e_aq_desc desc;
3081 struct i40e_aqc_nvm_update *cmd =
3082 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3083 enum i40e_status_code status;
3085 DEBUGFUNC("i40e_aq_update_nvm");
3087 /* In offset the highest byte must be zeroed. */
3088 if (offset & 0xFF000000) {
3089 status = I40E_ERR_PARAM;
3090 goto i40e_aq_update_nvm_exit;
3093 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3095 /* If this is the last command in a series, set the proper flag. */
3097 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3098 cmd->module_pointer = module_pointer;
3099 cmd->offset = CPU_TO_LE32(offset);
3100 cmd->length = CPU_TO_LE16(length);
3102 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3103 if (length > I40E_AQ_LARGE_BUF)
3104 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3106 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3108 i40e_aq_update_nvm_exit:
3113 * i40e_aq_get_lldp_mib
3114 * @hw: pointer to the hw struct
3115 * @bridge_type: type of bridge requested
3116 * @mib_type: Local, Remote or both Local and Remote MIBs
3117 * @buff: pointer to a user supplied buffer to store the MIB block
3118 * @buff_size: size of the buffer (in bytes)
3119 * @local_len : length of the returned Local LLDP MIB
3120 * @remote_len: length of the returned Remote LLDP MIB
3121 * @cmd_details: pointer to command details structure or NULL
3123 * Requests the complete LLDP MIB (entire packet).
3125 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3126 u8 mib_type, void *buff, u16 buff_size,
3127 u16 *local_len, u16 *remote_len,
3128 struct i40e_asq_cmd_details *cmd_details)
3130 struct i40e_aq_desc desc;
3131 struct i40e_aqc_lldp_get_mib *cmd =
3132 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3133 struct i40e_aqc_lldp_get_mib *resp =
3134 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3135 enum i40e_status_code status;
3137 if (buff_size == 0 || !buff)
3138 return I40E_ERR_PARAM;
3140 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3141 /* Indirect Command */
3142 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3144 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3145 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3146 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3148 desc.datalen = CPU_TO_LE16(buff_size);
3150 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3151 if (buff_size > I40E_AQ_LARGE_BUF)
3152 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3154 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3156 if (local_len != NULL)
3157 *local_len = LE16_TO_CPU(resp->local_len);
3158 if (remote_len != NULL)
3159 *remote_len = LE16_TO_CPU(resp->remote_len);
3166 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3167 * @hw: pointer to the hw struct
3168 * @mib_type: Local, Remote or both Local and Remote MIBs
3169 * @buff: pointer to a user supplied buffer to store the MIB block
3170 * @buff_size: size of the buffer (in bytes)
3171 * @cmd_details: pointer to command details structure or NULL
3175 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3176 u8 mib_type, void *buff, u16 buff_size,
3177 struct i40e_asq_cmd_details *cmd_details)
3179 struct i40e_aq_desc desc;
3180 struct i40e_aqc_lldp_set_local_mib *cmd =
3181 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3182 enum i40e_status_code status;
3184 if (buff_size == 0 || !buff)
3185 return I40E_ERR_PARAM;
3187 i40e_fill_default_direct_cmd_desc(&desc,
3188 i40e_aqc_opc_lldp_set_local_mib);
3189 /* Indirect Command */
3190 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3191 if (buff_size > I40E_AQ_LARGE_BUF)
3192 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3193 desc.datalen = CPU_TO_LE16(buff_size);
3195 cmd->type = mib_type;
3196 cmd->length = CPU_TO_LE16(buff_size);
3197 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3198 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3200 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3205 * i40e_aq_cfg_lldp_mib_change_event
3206 * @hw: pointer to the hw struct
3207 * @enable_update: Enable or Disable event posting
3208 * @cmd_details: pointer to command details structure or NULL
3210 * Enable or Disable posting of an event on ARQ when LLDP MIB
3211 * associated with the interface changes
3213 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3215 struct i40e_asq_cmd_details *cmd_details)
3217 struct i40e_aq_desc desc;
3218 struct i40e_aqc_lldp_update_mib *cmd =
3219 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3220 enum i40e_status_code status;
3222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3225 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3227 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3233 * i40e_aq_add_lldp_tlv
3234 * @hw: pointer to the hw struct
3235 * @bridge_type: type of bridge
3236 * @buff: buffer with TLV to add
3237 * @buff_size: length of the buffer
3238 * @tlv_len: length of the TLV to be added
3239 * @mib_len: length of the LLDP MIB returned in response
3240 * @cmd_details: pointer to command details structure or NULL
3242 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3243 * it is responsibility of the caller to make sure that the TLV is not
3244 * already present in the LLDPDU.
3245 * In return firmware will write the complete LLDP MIB with the newly
3246 * added TLV in the response buffer.
3248 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3249 void *buff, u16 buff_size, u16 tlv_len,
3251 struct i40e_asq_cmd_details *cmd_details)
3253 struct i40e_aq_desc desc;
3254 struct i40e_aqc_lldp_add_tlv *cmd =
3255 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3256 enum i40e_status_code status;
3258 if (buff_size == 0 || !buff || tlv_len == 0)
3259 return I40E_ERR_PARAM;
3261 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3263 /* Indirect Command */
3264 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3265 if (buff_size > I40E_AQ_LARGE_BUF)
3266 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3267 desc.datalen = CPU_TO_LE16(buff_size);
3269 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3270 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3271 cmd->len = CPU_TO_LE16(tlv_len);
3273 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3275 if (mib_len != NULL)
3276 *mib_len = LE16_TO_CPU(desc.datalen);
3283 * i40e_aq_update_lldp_tlv
3284 * @hw: pointer to the hw struct
3285 * @bridge_type: type of bridge
3286 * @buff: buffer with TLV to update
3287 * @buff_size: size of the buffer holding original and updated TLVs
3288 * @old_len: Length of the Original TLV
3289 * @new_len: Length of the Updated TLV
3290 * @offset: offset of the updated TLV in the buff
3291 * @mib_len: length of the returned LLDP MIB
3292 * @cmd_details: pointer to command details structure or NULL
3294 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3295 * Firmware will place the complete LLDP MIB in response buffer with the
3298 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3299 u8 bridge_type, void *buff, u16 buff_size,
3300 u16 old_len, u16 new_len, u16 offset,
3302 struct i40e_asq_cmd_details *cmd_details)
3304 struct i40e_aq_desc desc;
3305 struct i40e_aqc_lldp_update_tlv *cmd =
3306 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3307 enum i40e_status_code status;
3309 if (buff_size == 0 || !buff || offset == 0 ||
3310 old_len == 0 || new_len == 0)
3311 return I40E_ERR_PARAM;
3313 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3315 /* Indirect Command */
3316 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3317 if (buff_size > I40E_AQ_LARGE_BUF)
3318 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3319 desc.datalen = CPU_TO_LE16(buff_size);
3321 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3322 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3323 cmd->old_len = CPU_TO_LE16(old_len);
3324 cmd->new_offset = CPU_TO_LE16(offset);
3325 cmd->new_len = CPU_TO_LE16(new_len);
3327 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3329 if (mib_len != NULL)
3330 *mib_len = LE16_TO_CPU(desc.datalen);
3337 * i40e_aq_delete_lldp_tlv
3338 * @hw: pointer to the hw struct
3339 * @bridge_type: type of bridge
3340 * @buff: pointer to a user supplied buffer that has the TLV
3341 * @buff_size: length of the buffer
3342 * @tlv_len: length of the TLV to be deleted
3343 * @mib_len: length of the returned LLDP MIB
3344 * @cmd_details: pointer to command details structure or NULL
3346 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3347 * The firmware places the entire LLDP MIB in the response buffer.
3349 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3350 u8 bridge_type, void *buff, u16 buff_size,
3351 u16 tlv_len, u16 *mib_len,
3352 struct i40e_asq_cmd_details *cmd_details)
3354 struct i40e_aq_desc desc;
3355 struct i40e_aqc_lldp_add_tlv *cmd =
3356 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3357 enum i40e_status_code status;
3359 if (buff_size == 0 || !buff)
3360 return I40E_ERR_PARAM;
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3364 /* Indirect Command */
3365 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3366 if (buff_size > I40E_AQ_LARGE_BUF)
3367 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3368 desc.datalen = CPU_TO_LE16(buff_size);
3369 cmd->len = CPU_TO_LE16(tlv_len);
3370 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3371 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3373 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3375 if (mib_len != NULL)
3376 *mib_len = LE16_TO_CPU(desc.datalen);
3384 * @hw: pointer to the hw struct
3385 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3386 * @cmd_details: pointer to command details structure or NULL
3388 * Stop or Shutdown the embedded LLDP Agent
3390 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3391 struct i40e_asq_cmd_details *cmd_details)
3393 struct i40e_aq_desc desc;
3394 struct i40e_aqc_lldp_stop *cmd =
3395 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3396 enum i40e_status_code status;
3398 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3401 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3409 * i40e_aq_start_lldp
3410 * @hw: pointer to the hw struct
3411 * @cmd_details: pointer to command details structure or NULL
3413 * Start the embedded LLDP Agent on all ports.
3415 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3416 struct i40e_asq_cmd_details *cmd_details)
3418 struct i40e_aq_desc desc;
3419 struct i40e_aqc_lldp_start *cmd =
3420 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3421 enum i40e_status_code status;
3423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3425 cmd->command = I40E_AQ_LLDP_AGENT_START;
3427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3433 * i40e_aq_get_cee_dcb_config
3434 * @hw: pointer to the hw struct
3435 * @buff: response buffer that stores CEE operational configuration
3436 * @buff_size: size of the buffer passed
3437 * @cmd_details: pointer to command details structure or NULL
3439 * Get CEE DCBX mode operational configuration from firmware
3441 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3442 void *buff, u16 buff_size,
3443 struct i40e_asq_cmd_details *cmd_details)
3445 struct i40e_aq_desc desc;
3446 enum i40e_status_code status;
3448 if (buff_size == 0 || !buff)
3449 return I40E_ERR_PARAM;
3451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3453 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3454 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3461 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3462 * @hw: pointer to the hw struct
3463 * @start_agent: True if DCBx Agent needs to be Started
3464 * False if DCBx Agent needs to be Stopped
3465 * @cmd_details: pointer to command details structure or NULL
3467 * Start/Stop the embedded dcbx Agent
3469 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3471 struct i40e_asq_cmd_details *cmd_details)
3473 struct i40e_aq_desc desc;
3474 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3475 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3477 enum i40e_status_code status;
3479 i40e_fill_default_direct_cmd_desc(&desc,
3480 i40e_aqc_opc_lldp_stop_start_spec_agent);
3483 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3491 * i40e_aq_add_udp_tunnel
3492 * @hw: pointer to the hw struct
3493 * @udp_port: the UDP port to add
3494 * @header_len: length of the tunneling header length in DWords
3495 * @protocol_index: protocol index type
3496 * @filter_index: pointer to filter index
3497 * @cmd_details: pointer to command details structure or NULL
3499 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3500 u16 udp_port, u8 protocol_index,
3502 struct i40e_asq_cmd_details *cmd_details)
3504 struct i40e_aq_desc desc;
3505 struct i40e_aqc_add_udp_tunnel *cmd =
3506 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3507 struct i40e_aqc_del_udp_tunnel_completion *resp =
3508 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3509 enum i40e_status_code status;
3511 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3513 cmd->udp_port = CPU_TO_LE16(udp_port);
3514 cmd->protocol_type = protocol_index;
3516 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3519 *filter_index = resp->index;
3525 * i40e_aq_del_udp_tunnel
3526 * @hw: pointer to the hw struct
3527 * @index: filter index
3528 * @cmd_details: pointer to command details structure or NULL
3530 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3531 struct i40e_asq_cmd_details *cmd_details)
3533 struct i40e_aq_desc desc;
3534 struct i40e_aqc_remove_udp_tunnel *cmd =
3535 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3536 enum i40e_status_code status;
3538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3542 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3548 * i40e_aq_get_switch_resource_alloc (0x0204)
3549 * @hw: pointer to the hw struct
3550 * @num_entries: pointer to u8 to store the number of resource entries returned
3551 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3552 * to store the resource information for all resource types. Each
3553 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3554 * @count: size, in bytes, of the buffer provided
3555 * @cmd_details: pointer to command details structure or NULL
3557 * Query the resources allocated to a function.
3559 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3561 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3563 struct i40e_asq_cmd_details *cmd_details)
3565 struct i40e_aq_desc desc;
3566 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3567 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3568 enum i40e_status_code status;
3570 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3572 i40e_fill_default_direct_cmd_desc(&desc,
3573 i40e_aqc_opc_get_switch_resource_alloc);
3575 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3576 if (length > I40E_AQ_LARGE_BUF)
3577 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3579 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3582 *num_entries = cmd_resp->num_entries;
3588 * i40e_aq_delete_element - Delete switch element
3589 * @hw: pointer to the hw struct
3590 * @seid: the SEID to delete from the switch
3591 * @cmd_details: pointer to command details structure or NULL
3593 * This deletes a switch element from the switch.
3595 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3596 struct i40e_asq_cmd_details *cmd_details)
3598 struct i40e_aq_desc desc;
3599 struct i40e_aqc_switch_seid *cmd =
3600 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3601 enum i40e_status_code status;
3604 return I40E_ERR_PARAM;
3606 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3608 cmd->seid = CPU_TO_LE16(seid);
3610 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3616 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3617 * @hw: pointer to the hw struct
3618 * @flags: component flags
3619 * @mac_seid: uplink seid (MAC SEID)
3620 * @vsi_seid: connected vsi seid
3621 * @ret_seid: seid of create pv component
3623 * This instantiates an i40e port virtualizer with specified flags.
3624 * Depending on specified flags the port virtualizer can act as a
3625 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3627 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3628 u16 mac_seid, u16 vsi_seid,
3631 struct i40e_aq_desc desc;
3632 struct i40e_aqc_add_update_pv *cmd =
3633 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3634 struct i40e_aqc_add_update_pv_completion *resp =
3635 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3636 enum i40e_status_code status;
3639 return I40E_ERR_PARAM;
3641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3642 cmd->command_flags = CPU_TO_LE16(flags);
3643 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3644 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3646 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3647 if (!status && ret_seid)
3648 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3654 * i40e_aq_add_tag - Add an S/E-tag
3655 * @hw: pointer to the hw struct
3656 * @direct_to_queue: should s-tag direct flow to a specific queue
3657 * @vsi_seid: VSI SEID to use this tag
3658 * @tag: value of the tag
3659 * @queue_num: queue number, only valid is direct_to_queue is true
3660 * @tags_used: return value, number of tags in use by this PF
3661 * @tags_free: return value, number of unallocated tags
3662 * @cmd_details: pointer to command details structure or NULL
3664 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3665 * the number of tags allocated by the PF, and the number of unallocated
3668 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3669 u16 vsi_seid, u16 tag, u16 queue_num,
3670 u16 *tags_used, u16 *tags_free,
3671 struct i40e_asq_cmd_details *cmd_details)
3673 struct i40e_aq_desc desc;
3674 struct i40e_aqc_add_tag *cmd =
3675 (struct i40e_aqc_add_tag *)&desc.params.raw;
3676 struct i40e_aqc_add_remove_tag_completion *resp =
3677 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3678 enum i40e_status_code status;
3681 return I40E_ERR_PARAM;
3683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3685 cmd->seid = CPU_TO_LE16(vsi_seid);
3686 cmd->tag = CPU_TO_LE16(tag);
3687 if (direct_to_queue) {
3688 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3689 cmd->queue_number = CPU_TO_LE16(queue_num);
3692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3695 if (tags_used != NULL)
3696 *tags_used = LE16_TO_CPU(resp->tags_used);
3697 if (tags_free != NULL)
3698 *tags_free = LE16_TO_CPU(resp->tags_free);
3705 * i40e_aq_remove_tag - Remove an S- or E-tag
3706 * @hw: pointer to the hw struct
3707 * @vsi_seid: VSI SEID this tag is associated with
3708 * @tag: value of the S-tag to delete
3709 * @tags_used: return value, number of tags in use by this PF
3710 * @tags_free: return value, number of unallocated tags
3711 * @cmd_details: pointer to command details structure or NULL
3713 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3714 * the number of tags allocated by the PF, and the number of unallocated
3717 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3718 u16 tag, u16 *tags_used, u16 *tags_free,
3719 struct i40e_asq_cmd_details *cmd_details)
3721 struct i40e_aq_desc desc;
3722 struct i40e_aqc_remove_tag *cmd =
3723 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3724 struct i40e_aqc_add_remove_tag_completion *resp =
3725 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3726 enum i40e_status_code status;
3729 return I40E_ERR_PARAM;
3731 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3733 cmd->seid = CPU_TO_LE16(vsi_seid);
3734 cmd->tag = CPU_TO_LE16(tag);
3736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3739 if (tags_used != NULL)
3740 *tags_used = LE16_TO_CPU(resp->tags_used);
3741 if (tags_free != NULL)
3742 *tags_free = LE16_TO_CPU(resp->tags_free);
3749 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3750 * @hw: pointer to the hw struct
3751 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3752 * @etag: value of E-tag to add
3753 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3754 * @buf: address of indirect buffer
3755 * @tags_used: return value, number of E-tags in use by this port
3756 * @tags_free: return value, number of unallocated M-tags
3757 * @cmd_details: pointer to command details structure or NULL
3759 * This associates a multicast E-tag to a port virtualizer. It will return
3760 * the number of tags allocated by the PF, and the number of unallocated
3763 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3764 * num_tags_in_buf long.
3766 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3767 u16 etag, u8 num_tags_in_buf, void *buf,
3768 u16 *tags_used, u16 *tags_free,
3769 struct i40e_asq_cmd_details *cmd_details)
3771 struct i40e_aq_desc desc;
3772 struct i40e_aqc_add_remove_mcast_etag *cmd =
3773 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3774 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3775 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3776 enum i40e_status_code status;
3777 u16 length = sizeof(u16) * num_tags_in_buf;
3779 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3780 return I40E_ERR_PARAM;
3782 i40e_fill_default_direct_cmd_desc(&desc,
3783 i40e_aqc_opc_add_multicast_etag);
3785 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3786 cmd->etag = CPU_TO_LE16(etag);
3787 cmd->num_unicast_etags = num_tags_in_buf;
3789 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3790 if (length > I40E_AQ_LARGE_BUF)
3791 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3793 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3796 if (tags_used != NULL)
3797 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3798 if (tags_free != NULL)
3799 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3806 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3807 * @hw: pointer to the hw struct
3808 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3809 * @etag: value of the E-tag to remove
3810 * @tags_used: return value, number of tags in use by this port
3811 * @tags_free: return value, number of unallocated tags
3812 * @cmd_details: pointer to command details structure or NULL
3814 * This deletes an E-tag from the port virtualizer. It will return
3815 * the number of tags allocated by the port, and the number of unallocated
3818 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3819 u16 etag, u16 *tags_used, u16 *tags_free,
3820 struct i40e_asq_cmd_details *cmd_details)
3822 struct i40e_aq_desc desc;
3823 struct i40e_aqc_add_remove_mcast_etag *cmd =
3824 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3825 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3826 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3827 enum i40e_status_code status;
3831 return I40E_ERR_PARAM;
3833 i40e_fill_default_direct_cmd_desc(&desc,
3834 i40e_aqc_opc_remove_multicast_etag);
3836 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3837 cmd->etag = CPU_TO_LE16(etag);
3839 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3842 if (tags_used != NULL)
3843 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3844 if (tags_free != NULL)
3845 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3852 * i40e_aq_update_tag - Update an S/E-tag
3853 * @hw: pointer to the hw struct
3854 * @vsi_seid: VSI SEID using this S-tag
3855 * @old_tag: old tag value
3856 * @new_tag: new tag value
3857 * @tags_used: return value, number of tags in use by this PF
3858 * @tags_free: return value, number of unallocated tags
3859 * @cmd_details: pointer to command details structure or NULL
3861 * This updates the value of the tag currently attached to this VSI
3862 * in the switch complex. It will return the number of tags allocated
3863 * by the PF, and the number of unallocated tags available.
3865 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3866 u16 old_tag, u16 new_tag, u16 *tags_used,
3868 struct i40e_asq_cmd_details *cmd_details)
3870 struct i40e_aq_desc desc;
3871 struct i40e_aqc_update_tag *cmd =
3872 (struct i40e_aqc_update_tag *)&desc.params.raw;
3873 struct i40e_aqc_update_tag_completion *resp =
3874 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3875 enum i40e_status_code status;
3878 return I40E_ERR_PARAM;
3880 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3882 cmd->seid = CPU_TO_LE16(vsi_seid);
3883 cmd->old_tag = CPU_TO_LE16(old_tag);
3884 cmd->new_tag = CPU_TO_LE16(new_tag);
3886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3889 if (tags_used != NULL)
3890 *tags_used = LE16_TO_CPU(resp->tags_used);
3891 if (tags_free != NULL)
3892 *tags_free = LE16_TO_CPU(resp->tags_free);
3899 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3900 * @hw: pointer to the hw struct
3901 * @tcmap: TC map for request/release any ignore PFC condition
3902 * @request: request or release ignore PFC condition
3903 * @tcmap_ret: return TCs for which PFC is currently ignored
3904 * @cmd_details: pointer to command details structure or NULL
3906 * This sends out request/release to ignore PFC condition for a TC.
3907 * It will return the TCs for which PFC is currently ignored.
3909 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3910 bool request, u8 *tcmap_ret,
3911 struct i40e_asq_cmd_details *cmd_details)
3913 struct i40e_aq_desc desc;
3914 struct i40e_aqc_pfc_ignore *cmd_resp =
3915 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3916 enum i40e_status_code status;
3918 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3921 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3923 cmd_resp->tc_bitmap = tcmap;
3925 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3928 if (tcmap_ret != NULL)
3929 *tcmap_ret = cmd_resp->tc_bitmap;
3936 * i40e_aq_dcb_updated - DCB Updated Command
3937 * @hw: pointer to the hw struct
3938 * @cmd_details: pointer to command details structure or NULL
3940 * When LLDP is handled in PF this command is used by the PF
3941 * to notify EMP that a DCB setting is modified.
3942 * When LLDP is handled in EMP this command is used by the PF
3943 * to notify EMP whenever one of the following parameters get
3945 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3946 * - PCIRTT in PRTDCB_GENC.PCIRTT
3947 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3948 * EMP will return when the shared RPB settings have been
3949 * recomputed and modified. The retval field in the descriptor
3950 * will be set to 0 when RPB is modified.
3952 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3953 struct i40e_asq_cmd_details *cmd_details)
3955 struct i40e_aq_desc desc;
3956 enum i40e_status_code status;
3958 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3960 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3966 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3967 * @hw: pointer to the hw struct
3968 * @seid: defines the SEID of the switch for which the stats are requested
3969 * @vlan_id: the VLAN ID for which the statistics are requested
3970 * @stat_index: index of the statistics counters block assigned to this VLAN
3971 * @cmd_details: pointer to command details structure or NULL
3973 * XL710 supports 128 smonVlanStats counters.This command is used to
3974 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3977 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3978 u16 vlan_id, u16 *stat_index,
3979 struct i40e_asq_cmd_details *cmd_details)
3981 struct i40e_aq_desc desc;
3982 struct i40e_aqc_add_remove_statistics *cmd_resp =
3983 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3984 enum i40e_status_code status;
3986 if ((seid == 0) || (stat_index == NULL))
3987 return I40E_ERR_PARAM;
3989 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3991 cmd_resp->seid = CPU_TO_LE16(seid);
3992 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3997 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4003 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4004 * @hw: pointer to the hw struct
4005 * @seid: defines the SEID of the switch for which the stats are requested
4006 * @vlan_id: the VLAN ID for which the statistics are requested
4007 * @stat_index: index of the statistics counters block assigned to this VLAN
4008 * @cmd_details: pointer to command details structure or NULL
4010 * XL710 supports 128 smonVlanStats counters.This command is used to
4011 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4014 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4015 u16 vlan_id, u16 stat_index,
4016 struct i40e_asq_cmd_details *cmd_details)
4018 struct i40e_aq_desc desc;
4019 struct i40e_aqc_add_remove_statistics *cmd =
4020 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4021 enum i40e_status_code status;
4024 return I40E_ERR_PARAM;
4026 i40e_fill_default_direct_cmd_desc(&desc,
4027 i40e_aqc_opc_remove_statistics);
4029 cmd->seid = CPU_TO_LE16(seid);
4030 cmd->vlan = CPU_TO_LE16(vlan_id);
4031 cmd->stat_index = CPU_TO_LE16(stat_index);
4033 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4039 * i40e_aq_set_port_parameters - set physical port parameters.
4040 * @hw: pointer to the hw struct
4041 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4042 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4043 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4044 * @double_vlan: if set double VLAN is enabled
4045 * @cmd_details: pointer to command details structure or NULL
4047 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4048 u16 bad_frame_vsi, bool save_bad_pac,
4049 bool pad_short_pac, bool double_vlan,
4050 struct i40e_asq_cmd_details *cmd_details)
4052 struct i40e_aqc_set_port_parameters *cmd;
4053 enum i40e_status_code status;
4054 struct i40e_aq_desc desc;
4055 u16 command_flags = 0;
4057 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4059 i40e_fill_default_direct_cmd_desc(&desc,
4060 i40e_aqc_opc_set_port_parameters);
4062 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4064 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4066 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4068 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4069 cmd->command_flags = CPU_TO_LE16(command_flags);
4071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4077 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4078 * @hw: pointer to the hw struct
4079 * @seid: seid for the physical port/switching component/vsi
4080 * @buff: Indirect buffer to hold data parameters and response
4081 * @buff_size: Indirect buffer size
4082 * @opcode: Tx scheduler AQ command opcode
4083 * @cmd_details: pointer to command details structure or NULL
4085 * Generic command handler for Tx scheduler AQ commands
4087 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4088 void *buff, u16 buff_size,
4089 enum i40e_admin_queue_opc opcode,
4090 struct i40e_asq_cmd_details *cmd_details)
4092 struct i40e_aq_desc desc;
4093 struct i40e_aqc_tx_sched_ind *cmd =
4094 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4095 enum i40e_status_code status;
4096 bool cmd_param_flag = false;
4099 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4100 case i40e_aqc_opc_configure_vsi_tc_bw:
4101 case i40e_aqc_opc_enable_switching_comp_ets:
4102 case i40e_aqc_opc_modify_switching_comp_ets:
4103 case i40e_aqc_opc_disable_switching_comp_ets:
4104 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4105 case i40e_aqc_opc_configure_switching_comp_bw_config:
4106 cmd_param_flag = true;
4108 case i40e_aqc_opc_query_vsi_bw_config:
4109 case i40e_aqc_opc_query_vsi_ets_sla_config:
4110 case i40e_aqc_opc_query_switching_comp_ets_config:
4111 case i40e_aqc_opc_query_port_ets_config:
4112 case i40e_aqc_opc_query_switching_comp_bw_config:
4113 cmd_param_flag = false;
4116 return I40E_ERR_PARAM;
4119 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4121 /* Indirect command */
4122 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4124 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4125 if (buff_size > I40E_AQ_LARGE_BUF)
4126 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4128 desc.datalen = CPU_TO_LE16(buff_size);
4130 cmd->vsi_seid = CPU_TO_LE16(seid);
4132 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4138 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4139 * @hw: pointer to the hw struct
4141 * @credit: BW limit credits (0 = disabled)
4142 * @max_credit: Max BW limit credits
4143 * @cmd_details: pointer to command details structure or NULL
4145 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4146 u16 seid, u16 credit, u8 max_credit,
4147 struct i40e_asq_cmd_details *cmd_details)
4149 struct i40e_aq_desc desc;
4150 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4151 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4152 enum i40e_status_code status;
4154 i40e_fill_default_direct_cmd_desc(&desc,
4155 i40e_aqc_opc_configure_vsi_bw_limit);
4157 cmd->vsi_seid = CPU_TO_LE16(seid);
4158 cmd->credit = CPU_TO_LE16(credit);
4159 cmd->max_credit = max_credit;
4161 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4167 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4168 * @hw: pointer to the hw struct
4169 * @seid: switching component seid
4170 * @credit: BW limit credits (0 = disabled)
4171 * @max_bw: Max BW limit credits
4172 * @cmd_details: pointer to command details structure or NULL
4174 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4175 u16 seid, u16 credit, u8 max_bw,
4176 struct i40e_asq_cmd_details *cmd_details)
4178 struct i40e_aq_desc desc;
4179 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4180 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4181 enum i40e_status_code status;
4183 i40e_fill_default_direct_cmd_desc(&desc,
4184 i40e_aqc_opc_configure_switching_comp_bw_limit);
4186 cmd->seid = CPU_TO_LE16(seid);
4187 cmd->credit = CPU_TO_LE16(credit);
4188 cmd->max_bw = max_bw;
4190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4196 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4197 * @hw: pointer to the hw struct
4199 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4200 * @cmd_details: pointer to command details structure or NULL
4202 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4204 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4205 struct i40e_asq_cmd_details *cmd_details)
4207 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4208 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4213 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4214 * @hw: pointer to the hw struct
4216 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4217 * @cmd_details: pointer to command details structure or NULL
4219 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4221 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4222 struct i40e_asq_cmd_details *cmd_details)
4224 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4225 i40e_aqc_opc_configure_vsi_tc_bw,
4230 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4231 * @hw: pointer to the hw struct
4232 * @seid: seid of the switching component
4233 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4234 * @cmd_details: pointer to command details structure or NULL
4236 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4237 struct i40e_hw *hw, u16 seid,
4238 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4239 struct i40e_asq_cmd_details *cmd_details)
4241 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4242 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4247 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4248 * @hw: pointer to the hw struct
4249 * @seid: seid of the VSI
4250 * @bw_data: Buffer to hold VSI BW configuration
4251 * @cmd_details: pointer to command details structure or NULL
4253 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4255 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4256 struct i40e_asq_cmd_details *cmd_details)
4258 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4259 i40e_aqc_opc_query_vsi_bw_config,
4264 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4265 * @hw: pointer to the hw struct
4266 * @seid: seid of the VSI
4267 * @bw_data: Buffer to hold VSI BW configuration per TC
4268 * @cmd_details: pointer to command details structure or NULL
4270 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4272 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4273 struct i40e_asq_cmd_details *cmd_details)
4275 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4276 i40e_aqc_opc_query_vsi_ets_sla_config,
4281 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4282 * @hw: pointer to the hw struct
4283 * @seid: seid of the switching component
4284 * @bw_data: Buffer to hold switching component's per TC BW config
4285 * @cmd_details: pointer to command details structure or NULL
4287 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4289 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4290 struct i40e_asq_cmd_details *cmd_details)
4292 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4293 i40e_aqc_opc_query_switching_comp_ets_config,
4298 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4299 * @hw: pointer to the hw struct
4300 * @seid: seid of the VSI or switching component connected to Physical Port
4301 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4302 * @cmd_details: pointer to command details structure or NULL
4304 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4306 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4307 struct i40e_asq_cmd_details *cmd_details)
4309 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4310 i40e_aqc_opc_query_port_ets_config,
4315 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4316 * @hw: pointer to the hw struct
4317 * @seid: seid of the switching component
4318 * @bw_data: Buffer to hold switching component's BW configuration
4319 * @cmd_details: pointer to command details structure or NULL
4321 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4323 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4324 struct i40e_asq_cmd_details *cmd_details)
4326 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4327 i40e_aqc_opc_query_switching_comp_bw_config,
4332 * i40e_validate_filter_settings
4333 * @hw: pointer to the hardware structure
4334 * @settings: Filter control settings
4336 * Check and validate the filter control settings passed.
4337 * The function checks for the valid filter/context sizes being
4338 * passed for FCoE and PE.
4340 * Returns I40E_SUCCESS if the values passed are valid and within
4341 * range else returns an error.
4343 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4344 struct i40e_filter_control_settings *settings)
4346 u32 fcoe_cntx_size, fcoe_filt_size;
4347 u32 pe_cntx_size, pe_filt_size;
4352 /* Validate FCoE settings passed */
4353 switch (settings->fcoe_filt_num) {
4354 case I40E_HASH_FILTER_SIZE_1K:
4355 case I40E_HASH_FILTER_SIZE_2K:
4356 case I40E_HASH_FILTER_SIZE_4K:
4357 case I40E_HASH_FILTER_SIZE_8K:
4358 case I40E_HASH_FILTER_SIZE_16K:
4359 case I40E_HASH_FILTER_SIZE_32K:
4360 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4361 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4364 return I40E_ERR_PARAM;
4367 switch (settings->fcoe_cntx_num) {
4368 case I40E_DMA_CNTX_SIZE_512:
4369 case I40E_DMA_CNTX_SIZE_1K:
4370 case I40E_DMA_CNTX_SIZE_2K:
4371 case I40E_DMA_CNTX_SIZE_4K:
4372 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4373 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4376 return I40E_ERR_PARAM;
4379 /* Validate PE settings passed */
4380 switch (settings->pe_filt_num) {
4381 case I40E_HASH_FILTER_SIZE_1K:
4382 case I40E_HASH_FILTER_SIZE_2K:
4383 case I40E_HASH_FILTER_SIZE_4K:
4384 case I40E_HASH_FILTER_SIZE_8K:
4385 case I40E_HASH_FILTER_SIZE_16K:
4386 case I40E_HASH_FILTER_SIZE_32K:
4387 case I40E_HASH_FILTER_SIZE_64K:
4388 case I40E_HASH_FILTER_SIZE_128K:
4389 case I40E_HASH_FILTER_SIZE_256K:
4390 case I40E_HASH_FILTER_SIZE_512K:
4391 case I40E_HASH_FILTER_SIZE_1M:
4392 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4393 pe_filt_size <<= (u32)settings->pe_filt_num;
4396 return I40E_ERR_PARAM;
4399 switch (settings->pe_cntx_num) {
4400 case I40E_DMA_CNTX_SIZE_512:
4401 case I40E_DMA_CNTX_SIZE_1K:
4402 case I40E_DMA_CNTX_SIZE_2K:
4403 case I40E_DMA_CNTX_SIZE_4K:
4404 case I40E_DMA_CNTX_SIZE_8K:
4405 case I40E_DMA_CNTX_SIZE_16K:
4406 case I40E_DMA_CNTX_SIZE_32K:
4407 case I40E_DMA_CNTX_SIZE_64K:
4408 case I40E_DMA_CNTX_SIZE_128K:
4409 case I40E_DMA_CNTX_SIZE_256K:
4410 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4411 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4414 return I40E_ERR_PARAM;
4417 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4418 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4419 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4420 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4421 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4422 return I40E_ERR_INVALID_SIZE;
4424 return I40E_SUCCESS;
4428 * i40e_set_filter_control
4429 * @hw: pointer to the hardware structure
4430 * @settings: Filter control settings
4432 * Set the Queue Filters for PE/FCoE and enable filters required
4433 * for a single PF. It is expected that these settings are programmed
4434 * at the driver initialization time.
4436 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4437 struct i40e_filter_control_settings *settings)
4439 enum i40e_status_code ret = I40E_SUCCESS;
4440 u32 hash_lut_size = 0;
4444 return I40E_ERR_PARAM;
4446 /* Validate the input settings */
4447 ret = i40e_validate_filter_settings(hw, settings);
4451 /* Read the PF Queue Filter control register */
4452 val = rd32(hw, I40E_PFQF_CTL_0);
4454 /* Program required PE hash buckets for the PF */
4455 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4456 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4457 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4458 /* Program required PE contexts for the PF */
4459 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4460 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4461 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4463 /* Program required FCoE hash buckets for the PF */
4464 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4465 val |= ((u32)settings->fcoe_filt_num <<
4466 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4467 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4468 /* Program required FCoE DDP contexts for the PF */
4469 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4470 val |= ((u32)settings->fcoe_cntx_num <<
4471 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4472 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4474 /* Program Hash LUT size for the PF */
4475 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4476 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4478 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4479 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4481 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4482 if (settings->enable_fdir)
4483 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4484 if (settings->enable_ethtype)
4485 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4486 if (settings->enable_macvlan)
4487 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4489 wr32(hw, I40E_PFQF_CTL_0, val);
4491 return I40E_SUCCESS;
4495 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4496 * @hw: pointer to the hw struct
4497 * @mac_addr: MAC address to use in the filter
4498 * @ethtype: Ethertype to use in the filter
4499 * @flags: Flags that needs to be applied to the filter
4500 * @vsi_seid: seid of the control VSI
4501 * @queue: VSI queue number to send the packet to
4502 * @is_add: Add control packet filter if True else remove
4503 * @stats: Structure to hold information on control filter counts
4504 * @cmd_details: pointer to command details structure or NULL
4506 * This command will Add or Remove control packet filter for a control VSI.
4507 * In return it will update the total number of perfect filter count in
4510 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4511 u8 *mac_addr, u16 ethtype, u16 flags,
4512 u16 vsi_seid, u16 queue, bool is_add,
4513 struct i40e_control_filter_stats *stats,
4514 struct i40e_asq_cmd_details *cmd_details)
4516 struct i40e_aq_desc desc;
4517 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4518 (struct i40e_aqc_add_remove_control_packet_filter *)
4520 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4521 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4523 enum i40e_status_code status;
4526 return I40E_ERR_PARAM;
4529 i40e_fill_default_direct_cmd_desc(&desc,
4530 i40e_aqc_opc_add_control_packet_filter);
4531 cmd->queue = CPU_TO_LE16(queue);
4533 i40e_fill_default_direct_cmd_desc(&desc,
4534 i40e_aqc_opc_remove_control_packet_filter);
4538 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4539 I40E_NONDMA_TO_NONDMA);
4541 cmd->etype = CPU_TO_LE16(ethtype);
4542 cmd->flags = CPU_TO_LE16(flags);
4543 cmd->seid = CPU_TO_LE16(vsi_seid);
4545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4547 if (!status && stats) {
4548 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4549 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4550 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4551 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4558 * i40e_aq_add_cloud_filters
4559 * @hw: pointer to the hardware structure
4560 * @seid: VSI seid to add cloud filters from
4561 * @filters: Buffer which contains the filters to be added
4562 * @filter_count: number of filters contained in the buffer
4564 * Set the cloud filters for a given VSI. The contents of the
4565 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4566 * in by the caller of the function.
4569 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4571 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4574 struct i40e_aq_desc desc;
4575 struct i40e_aqc_add_remove_cloud_filters *cmd =
4576 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4578 enum i40e_status_code status;
4580 i40e_fill_default_direct_cmd_desc(&desc,
4581 i40e_aqc_opc_add_cloud_filters);
4583 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4585 desc.datalen = CPU_TO_LE16(buff_len);
4586 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4587 cmd->num_filters = filter_count;
4588 cmd->seid = CPU_TO_LE16(seid);
4590 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4596 * i40e_aq_remove_cloud_filters
4597 * @hw: pointer to the hardware structure
4598 * @seid: VSI seid to remove cloud filters from
4599 * @filters: Buffer which contains the filters to be removed
4600 * @filter_count: number of filters contained in the buffer
4602 * Remove the cloud filters for a given VSI. The contents of the
4603 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4604 * in by the caller of the function.
4607 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4609 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4612 struct i40e_aq_desc desc;
4613 struct i40e_aqc_add_remove_cloud_filters *cmd =
4614 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4615 enum i40e_status_code status;
4618 i40e_fill_default_direct_cmd_desc(&desc,
4619 i40e_aqc_opc_remove_cloud_filters);
4621 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4623 desc.datalen = CPU_TO_LE16(buff_len);
4624 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4625 cmd->num_filters = filter_count;
4626 cmd->seid = CPU_TO_LE16(seid);
4628 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4634 * i40e_aq_alternate_write
4635 * @hw: pointer to the hardware structure
4636 * @reg_addr0: address of first dword to be read
4637 * @reg_val0: value to be written under 'reg_addr0'
4638 * @reg_addr1: address of second dword to be read
4639 * @reg_val1: value to be written under 'reg_addr1'
4641 * Write one or two dwords to alternate structure. Fields are indicated
4642 * by 'reg_addr0' and 'reg_addr1' register numbers.
4645 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4646 u32 reg_addr0, u32 reg_val0,
4647 u32 reg_addr1, u32 reg_val1)
4649 struct i40e_aq_desc desc;
4650 struct i40e_aqc_alternate_write *cmd_resp =
4651 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4652 enum i40e_status_code status;
4654 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4655 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4656 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4657 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4658 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4660 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4666 * i40e_aq_alternate_write_indirect
4667 * @hw: pointer to the hardware structure
4668 * @addr: address of a first register to be modified
4669 * @dw_count: number of alternate structure fields to write
4670 * @buffer: pointer to the command buffer
4672 * Write 'dw_count' dwords from 'buffer' to alternate structure
4673 * starting at 'addr'.
4676 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4677 u32 addr, u32 dw_count, void *buffer)
4679 struct i40e_aq_desc desc;
4680 struct i40e_aqc_alternate_ind_write *cmd_resp =
4681 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4682 enum i40e_status_code status;
4685 return I40E_ERR_PARAM;
4687 /* Indirect command */
4688 i40e_fill_default_direct_cmd_desc(&desc,
4689 i40e_aqc_opc_alternate_write_indirect);
4691 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4692 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4693 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4694 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4696 cmd_resp->address = CPU_TO_LE32(addr);
4697 cmd_resp->length = CPU_TO_LE32(dw_count);
4698 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4699 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4701 status = i40e_asq_send_command(hw, &desc, buffer,
4702 I40E_LO_DWORD(4*dw_count), NULL);
4708 * i40e_aq_alternate_read
4709 * @hw: pointer to the hardware structure
4710 * @reg_addr0: address of first dword to be read
4711 * @reg_val0: pointer for data read from 'reg_addr0'
4712 * @reg_addr1: address of second dword to be read
4713 * @reg_val1: pointer for data read from 'reg_addr1'
4715 * Read one or two dwords from alternate structure. Fields are indicated
4716 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4717 * is not passed then only register at 'reg_addr0' is read.
4720 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4721 u32 reg_addr0, u32 *reg_val0,
4722 u32 reg_addr1, u32 *reg_val1)
4724 struct i40e_aq_desc desc;
4725 struct i40e_aqc_alternate_write *cmd_resp =
4726 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4727 enum i40e_status_code status;
4729 if (reg_val0 == NULL)
4730 return I40E_ERR_PARAM;
4732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4733 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4734 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4736 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4738 if (status == I40E_SUCCESS) {
4739 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4741 if (reg_val1 != NULL)
4742 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4749 * i40e_aq_alternate_read_indirect
4750 * @hw: pointer to the hardware structure
4751 * @addr: address of the alternate structure field
4752 * @dw_count: number of alternate structure fields to read
4753 * @buffer: pointer to the command buffer
4755 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4756 * place them in 'buffer'. The buffer should be allocated by caller.
4759 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4760 u32 addr, u32 dw_count, void *buffer)
4762 struct i40e_aq_desc desc;
4763 struct i40e_aqc_alternate_ind_write *cmd_resp =
4764 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4765 enum i40e_status_code status;
4768 return I40E_ERR_PARAM;
4770 /* Indirect command */
4771 i40e_fill_default_direct_cmd_desc(&desc,
4772 i40e_aqc_opc_alternate_read_indirect);
4774 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4775 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4776 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4779 cmd_resp->address = CPU_TO_LE32(addr);
4780 cmd_resp->length = CPU_TO_LE32(dw_count);
4781 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4782 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4784 status = i40e_asq_send_command(hw, &desc, buffer,
4785 I40E_LO_DWORD(4*dw_count), NULL);
4791 * i40e_aq_alternate_clear
4792 * @hw: pointer to the HW structure.
4794 * Clear the alternate structures of the port from which the function
4798 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4800 struct i40e_aq_desc desc;
4801 enum i40e_status_code status;
4803 i40e_fill_default_direct_cmd_desc(&desc,
4804 i40e_aqc_opc_alternate_clear_port);
4806 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4812 * i40e_aq_alternate_write_done
4813 * @hw: pointer to the HW structure.
4814 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4815 * @reset_needed: indicates the SW should trigger GLOBAL reset
4817 * Indicates to the FW that alternate structures have been changed.
4820 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4821 u8 bios_mode, bool *reset_needed)
4823 struct i40e_aq_desc desc;
4824 struct i40e_aqc_alternate_write_done *cmd =
4825 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4826 enum i40e_status_code status;
4828 if (reset_needed == NULL)
4829 return I40E_ERR_PARAM;
4831 i40e_fill_default_direct_cmd_desc(&desc,
4832 i40e_aqc_opc_alternate_write_done);
4834 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4836 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4838 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4839 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4845 * i40e_aq_set_oem_mode
4846 * @hw: pointer to the HW structure.
4847 * @oem_mode: the OEM mode to be used
4849 * Sets the device to a specific operating mode. Currently the only supported
4850 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4853 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4856 struct i40e_aq_desc desc;
4857 struct i40e_aqc_alternate_write_done *cmd =
4858 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4859 enum i40e_status_code status;
4861 i40e_fill_default_direct_cmd_desc(&desc,
4862 i40e_aqc_opc_alternate_set_mode);
4864 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4866 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4872 * i40e_aq_resume_port_tx
4873 * @hw: pointer to the hardware structure
4874 * @cmd_details: pointer to command details structure or NULL
4876 * Resume port's Tx traffic
4878 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4879 struct i40e_asq_cmd_details *cmd_details)
4881 struct i40e_aq_desc desc;
4882 enum i40e_status_code status;
4884 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4892 * i40e_set_pci_config_data - store PCI bus info
4893 * @hw: pointer to hardware structure
4894 * @link_status: the link status word from PCI config space
4896 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4898 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4900 hw->bus.type = i40e_bus_type_pci_express;
4902 switch (link_status & I40E_PCI_LINK_WIDTH) {
4903 case I40E_PCI_LINK_WIDTH_1:
4904 hw->bus.width = i40e_bus_width_pcie_x1;
4906 case I40E_PCI_LINK_WIDTH_2:
4907 hw->bus.width = i40e_bus_width_pcie_x2;
4909 case I40E_PCI_LINK_WIDTH_4:
4910 hw->bus.width = i40e_bus_width_pcie_x4;
4912 case I40E_PCI_LINK_WIDTH_8:
4913 hw->bus.width = i40e_bus_width_pcie_x8;
4916 hw->bus.width = i40e_bus_width_unknown;
4920 switch (link_status & I40E_PCI_LINK_SPEED) {
4921 case I40E_PCI_LINK_SPEED_2500:
4922 hw->bus.speed = i40e_bus_speed_2500;
4924 case I40E_PCI_LINK_SPEED_5000:
4925 hw->bus.speed = i40e_bus_speed_5000;
4927 case I40E_PCI_LINK_SPEED_8000:
4928 hw->bus.speed = i40e_bus_speed_8000;
4931 hw->bus.speed = i40e_bus_speed_unknown;
4937 * i40e_read_bw_from_alt_ram
4938 * @hw: pointer to the hardware structure
4939 * @max_bw: pointer for max_bw read
4940 * @min_bw: pointer for min_bw read
4941 * @min_valid: pointer for bool that is true if min_bw is a valid value
4942 * @max_valid: pointer for bool that is true if max_bw is a valid value
4944 * Read bw from the alternate ram for the given pf
4946 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4947 u32 *max_bw, u32 *min_bw,
4948 bool *min_valid, bool *max_valid)
4950 enum i40e_status_code status;
4951 u32 max_bw_addr, min_bw_addr;
4953 /* Calculate the address of the min/max bw registers */
4954 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4955 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4956 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4957 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4958 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4959 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4961 /* Read the bandwidths from alt ram */
4962 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4963 min_bw_addr, min_bw);
4965 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4970 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4979 * i40e_aq_configure_partition_bw
4980 * @hw: pointer to the hardware structure
4981 * @bw_data: Buffer holding valid pfs and bw limits
4982 * @cmd_details: pointer to command details
4984 * Configure partitions guaranteed/max bw
4986 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4987 struct i40e_aqc_configure_partition_bw_data *bw_data,
4988 struct i40e_asq_cmd_details *cmd_details)
4990 enum i40e_status_code status;
4991 struct i40e_aq_desc desc;
4992 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4994 i40e_fill_default_direct_cmd_desc(&desc,
4995 i40e_aqc_opc_configure_partition_bw);
4997 /* Indirect command */
4998 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4999 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5001 if (bwd_size > I40E_AQ_LARGE_BUF)
5002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5004 desc.datalen = CPU_TO_LE16(bwd_size);
5006 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5010 #endif /* PF_DRIVER */
5014 * i40e_aq_send_msg_to_pf
5015 * @hw: pointer to the hardware structure
5016 * @v_opcode: opcodes for VF-PF communication
5017 * @v_retval: return error code
5018 * @msg: pointer to the msg buffer
5019 * @msglen: msg length
5020 * @cmd_details: pointer to command details
5022 * Send message to PF driver using admin queue. By default, this message
5023 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5024 * completion before returning.
5026 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5027 enum i40e_virtchnl_ops v_opcode,
5028 enum i40e_status_code v_retval,
5029 u8 *msg, u16 msglen,
5030 struct i40e_asq_cmd_details *cmd_details)
5032 struct i40e_aq_desc desc;
5033 struct i40e_asq_cmd_details details;
5034 enum i40e_status_code status;
5036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5037 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5038 desc.cookie_high = CPU_TO_LE32(v_opcode);
5039 desc.cookie_low = CPU_TO_LE32(v_retval);
5041 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5042 | I40E_AQ_FLAG_RD));
5043 if (msglen > I40E_AQ_LARGE_BUF)
5044 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5045 desc.datalen = CPU_TO_LE16(msglen);
5048 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5049 details.async = true;
5050 cmd_details = &details;
5052 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5053 msglen, cmd_details);
5058 * i40e_vf_parse_hw_config
5059 * @hw: pointer to the hardware structure
5060 * @msg: pointer to the virtual channel VF resource structure
5062 * Given a VF resource message from the PF, populate the hw struct
5063 * with appropriate information.
5065 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5066 struct i40e_virtchnl_vf_resource *msg)
5068 struct i40e_virtchnl_vsi_resource *vsi_res;
5071 vsi_res = &msg->vsi_res[0];
5073 hw->dev_caps.num_vsis = msg->num_vsis;
5074 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5075 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5076 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5077 hw->dev_caps.dcb = msg->vf_offload_flags &
5078 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5079 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5080 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5081 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5082 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5083 for (i = 0; i < msg->num_vsis; i++) {
5084 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5085 i40e_memcpy(hw->mac.perm_addr,
5086 vsi_res->default_mac_addr,
5087 I40E_ETH_LENGTH_OF_ADDRESS,
5088 I40E_NONDMA_TO_NONDMA);
5089 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5090 I40E_ETH_LENGTH_OF_ADDRESS,
5091 I40E_NONDMA_TO_NONDMA);
5099 * @hw: pointer to the hardware structure
5101 * Send a VF_RESET message to the PF. Does not wait for response from PF
5102 * as none will be forthcoming. Immediately after calling this function,
5103 * the admin queue should be shut down and (optionally) reinitialized.
5105 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5107 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5108 I40E_SUCCESS, NULL, 0, NULL);
5110 #endif /* VF_DRIVER */