1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *buf = (u8 *)buffer;
104 if ((!(mask & hw->debug_mask)) || (desc == NULL))
108 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
109 LE16_TO_CPU(aq_desc->opcode),
110 LE16_TO_CPU(aq_desc->flags),
111 LE16_TO_CPU(aq_desc->datalen),
112 LE16_TO_CPU(aq_desc->retval));
113 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
114 LE32_TO_CPU(aq_desc->cookie_high),
115 LE32_TO_CPU(aq_desc->cookie_low));
116 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
117 LE32_TO_CPU(aq_desc->params.internal.param0),
118 LE32_TO_CPU(aq_desc->params.internal.param1));
119 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
120 LE32_TO_CPU(aq_desc->params.external.addr_high),
121 LE32_TO_CPU(aq_desc->params.external.addr_low));
123 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
124 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
127 /* write the full 16-byte chunks */
128 for (i = 0; i < (len - 16); i += 16)
130 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
131 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
132 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
133 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
134 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
135 /* write whatever's left over without overrunning the buffer */
140 memset(d_buf, 0, sizeof(d_buf));
141 j += sprintf(d_buf, "\t0x%04X ", i);
143 j += sprintf(&d_buf[j], " %02X", buf[i++]);
144 i40e_debug(hw, mask, "%s\n", d_buf);
150 * i40e_check_asq_alive
151 * @hw: pointer to the hw struct
153 * Returns true if Queue is enabled else false.
155 bool i40e_check_asq_alive(struct i40e_hw *hw)
158 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
164 * i40e_aq_queue_shutdown
165 * @hw: pointer to the hw struct
166 * @unloading: is the driver unloading itself
168 * Tell the Firmware that we're shutting down the AdminQ and whether
169 * or not the driver is unloading as well.
171 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
174 struct i40e_aq_desc desc;
175 struct i40e_aqc_queue_shutdown *cmd =
176 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
177 enum i40e_status_code status;
179 i40e_fill_default_direct_cmd_desc(&desc,
180 i40e_aqc_opc_queue_shutdown);
183 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
189 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
190 * hardware to a bit-field that can be used by SW to more easily determine the
193 * Macros are used to shorten the table lines and make this table human
196 * We store the PTYPE in the top byte of the bit field - this is just so that
197 * we can check that the table doesn't have a row missing, as the index into
198 * the table should be the PTYPE.
202 * IF NOT i40e_ptype_lookup[ptype].known
205 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
206 * Use the rest of the fields to look at the tunnels, inner protocols, etc
208 * Use the enum i40e_rx_l2_ptype to decode the packet type
212 /* macro to make the table lines short */
213 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
216 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
217 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
218 I40E_RX_PTYPE_##OUTER_FRAG, \
219 I40E_RX_PTYPE_TUNNEL_##T, \
220 I40E_RX_PTYPE_TUNNEL_END_##TE, \
221 I40E_RX_PTYPE_##TEF, \
222 I40E_RX_PTYPE_INNER_PROT_##I, \
223 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
225 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
226 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
228 /* shorter macros makes the table fit but are terse */
229 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
230 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
231 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
233 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
234 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
235 /* L2 Packet types */
236 I40E_PTT_UNUSED_ENTRY(0),
237 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
239 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(4),
241 I40E_PTT_UNUSED_ENTRY(5),
242 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(8),
245 I40E_PTT_UNUSED_ENTRY(9),
246 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
248 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 /* Non Tunneled IPv4 */
260 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(25),
264 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
265 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
266 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
269 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
270 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
271 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(32),
273 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
274 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
275 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
278 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
279 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
280 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
281 I40E_PTT_UNUSED_ENTRY(39),
282 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
283 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
284 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
286 /* IPv4 --> GRE/NAT */
287 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
289 /* IPv4 --> GRE/NAT --> IPv4 */
290 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
291 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
292 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(47),
294 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
295 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
296 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> IPv6 */
299 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
300 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
301 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
302 I40E_PTT_UNUSED_ENTRY(54),
303 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
304 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
305 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
307 /* IPv4 --> GRE/NAT --> MAC */
308 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
310 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
311 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
312 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
313 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(62),
315 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
316 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
317 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
320 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
321 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
322 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
323 I40E_PTT_UNUSED_ENTRY(69),
324 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
325 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
326 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
328 /* IPv4 --> GRE/NAT --> MAC/VLAN */
329 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
331 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
332 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
333 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
334 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(77),
336 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
337 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
338 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
340 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
341 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
342 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
343 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(84),
345 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
346 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
347 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
349 /* Non Tunneled IPv6 */
350 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
353 I40E_PTT_UNUSED_ENTRY(91),
354 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
355 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
356 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
359 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
360 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
361 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(98),
363 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
364 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
365 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
368 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
369 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
370 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
371 I40E_PTT_UNUSED_ENTRY(105),
372 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
373 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
374 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
376 /* IPv6 --> GRE/NAT */
377 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
379 /* IPv6 --> GRE/NAT -> IPv4 */
380 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
381 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
382 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(113),
384 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
385 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
386 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> IPv6 */
389 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
390 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
391 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
392 I40E_PTT_UNUSED_ENTRY(120),
393 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
394 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
395 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
397 /* IPv6 --> GRE/NAT -> MAC */
398 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
401 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
402 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
403 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(128),
405 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
406 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
407 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
410 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
411 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
412 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
413 I40E_PTT_UNUSED_ENTRY(135),
414 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
415 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
416 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
418 /* IPv6 --> GRE/NAT -> MAC/VLAN */
419 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
422 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
423 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
424 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(143),
426 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
427 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
428 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
430 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
431 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
432 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
433 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
434 I40E_PTT_UNUSED_ENTRY(150),
435 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
436 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
437 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
440 I40E_PTT_UNUSED_ENTRY(154),
441 I40E_PTT_UNUSED_ENTRY(155),
442 I40E_PTT_UNUSED_ENTRY(156),
443 I40E_PTT_UNUSED_ENTRY(157),
444 I40E_PTT_UNUSED_ENTRY(158),
445 I40E_PTT_UNUSED_ENTRY(159),
447 I40E_PTT_UNUSED_ENTRY(160),
448 I40E_PTT_UNUSED_ENTRY(161),
449 I40E_PTT_UNUSED_ENTRY(162),
450 I40E_PTT_UNUSED_ENTRY(163),
451 I40E_PTT_UNUSED_ENTRY(164),
452 I40E_PTT_UNUSED_ENTRY(165),
453 I40E_PTT_UNUSED_ENTRY(166),
454 I40E_PTT_UNUSED_ENTRY(167),
455 I40E_PTT_UNUSED_ENTRY(168),
456 I40E_PTT_UNUSED_ENTRY(169),
458 I40E_PTT_UNUSED_ENTRY(170),
459 I40E_PTT_UNUSED_ENTRY(171),
460 I40E_PTT_UNUSED_ENTRY(172),
461 I40E_PTT_UNUSED_ENTRY(173),
462 I40E_PTT_UNUSED_ENTRY(174),
463 I40E_PTT_UNUSED_ENTRY(175),
464 I40E_PTT_UNUSED_ENTRY(176),
465 I40E_PTT_UNUSED_ENTRY(177),
466 I40E_PTT_UNUSED_ENTRY(178),
467 I40E_PTT_UNUSED_ENTRY(179),
469 I40E_PTT_UNUSED_ENTRY(180),
470 I40E_PTT_UNUSED_ENTRY(181),
471 I40E_PTT_UNUSED_ENTRY(182),
472 I40E_PTT_UNUSED_ENTRY(183),
473 I40E_PTT_UNUSED_ENTRY(184),
474 I40E_PTT_UNUSED_ENTRY(185),
475 I40E_PTT_UNUSED_ENTRY(186),
476 I40E_PTT_UNUSED_ENTRY(187),
477 I40E_PTT_UNUSED_ENTRY(188),
478 I40E_PTT_UNUSED_ENTRY(189),
480 I40E_PTT_UNUSED_ENTRY(190),
481 I40E_PTT_UNUSED_ENTRY(191),
482 I40E_PTT_UNUSED_ENTRY(192),
483 I40E_PTT_UNUSED_ENTRY(193),
484 I40E_PTT_UNUSED_ENTRY(194),
485 I40E_PTT_UNUSED_ENTRY(195),
486 I40E_PTT_UNUSED_ENTRY(196),
487 I40E_PTT_UNUSED_ENTRY(197),
488 I40E_PTT_UNUSED_ENTRY(198),
489 I40E_PTT_UNUSED_ENTRY(199),
491 I40E_PTT_UNUSED_ENTRY(200),
492 I40E_PTT_UNUSED_ENTRY(201),
493 I40E_PTT_UNUSED_ENTRY(202),
494 I40E_PTT_UNUSED_ENTRY(203),
495 I40E_PTT_UNUSED_ENTRY(204),
496 I40E_PTT_UNUSED_ENTRY(205),
497 I40E_PTT_UNUSED_ENTRY(206),
498 I40E_PTT_UNUSED_ENTRY(207),
499 I40E_PTT_UNUSED_ENTRY(208),
500 I40E_PTT_UNUSED_ENTRY(209),
502 I40E_PTT_UNUSED_ENTRY(210),
503 I40E_PTT_UNUSED_ENTRY(211),
504 I40E_PTT_UNUSED_ENTRY(212),
505 I40E_PTT_UNUSED_ENTRY(213),
506 I40E_PTT_UNUSED_ENTRY(214),
507 I40E_PTT_UNUSED_ENTRY(215),
508 I40E_PTT_UNUSED_ENTRY(216),
509 I40E_PTT_UNUSED_ENTRY(217),
510 I40E_PTT_UNUSED_ENTRY(218),
511 I40E_PTT_UNUSED_ENTRY(219),
513 I40E_PTT_UNUSED_ENTRY(220),
514 I40E_PTT_UNUSED_ENTRY(221),
515 I40E_PTT_UNUSED_ENTRY(222),
516 I40E_PTT_UNUSED_ENTRY(223),
517 I40E_PTT_UNUSED_ENTRY(224),
518 I40E_PTT_UNUSED_ENTRY(225),
519 I40E_PTT_UNUSED_ENTRY(226),
520 I40E_PTT_UNUSED_ENTRY(227),
521 I40E_PTT_UNUSED_ENTRY(228),
522 I40E_PTT_UNUSED_ENTRY(229),
524 I40E_PTT_UNUSED_ENTRY(230),
525 I40E_PTT_UNUSED_ENTRY(231),
526 I40E_PTT_UNUSED_ENTRY(232),
527 I40E_PTT_UNUSED_ENTRY(233),
528 I40E_PTT_UNUSED_ENTRY(234),
529 I40E_PTT_UNUSED_ENTRY(235),
530 I40E_PTT_UNUSED_ENTRY(236),
531 I40E_PTT_UNUSED_ENTRY(237),
532 I40E_PTT_UNUSED_ENTRY(238),
533 I40E_PTT_UNUSED_ENTRY(239),
535 I40E_PTT_UNUSED_ENTRY(240),
536 I40E_PTT_UNUSED_ENTRY(241),
537 I40E_PTT_UNUSED_ENTRY(242),
538 I40E_PTT_UNUSED_ENTRY(243),
539 I40E_PTT_UNUSED_ENTRY(244),
540 I40E_PTT_UNUSED_ENTRY(245),
541 I40E_PTT_UNUSED_ENTRY(246),
542 I40E_PTT_UNUSED_ENTRY(247),
543 I40E_PTT_UNUSED_ENTRY(248),
544 I40E_PTT_UNUSED_ENTRY(249),
546 I40E_PTT_UNUSED_ENTRY(250),
547 I40E_PTT_UNUSED_ENTRY(251),
548 I40E_PTT_UNUSED_ENTRY(252),
549 I40E_PTT_UNUSED_ENTRY(253),
550 I40E_PTT_UNUSED_ENTRY(254),
551 I40E_PTT_UNUSED_ENTRY(255)
557 * i40e_init_shared_code - Initialize the shared code
558 * @hw: pointer to hardware structure
560 * This assigns the MAC type and PHY code and inits the NVM.
561 * Does not touch the hardware. This function must be called prior to any
562 * other function in the shared code. The i40e_hw structure should be
563 * memset to 0 prior to calling this function. The following fields in
564 * hw structure should be filled in prior to calling this function:
565 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
566 * subsystem_vendor_id, and revision_id
568 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
570 enum i40e_status_code status = I40E_SUCCESS;
573 DEBUGFUNC("i40e_init_shared_code");
575 i40e_set_mac_type(hw);
577 switch (hw->mac.type) {
581 return I40E_ERR_DEVICE_NOT_SUPPORTED;
584 hw->phy.get_link_info = true;
586 /* Determine port number */
587 reg = rd32(hw, I40E_PFGEN_PORTNUM);
588 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
589 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
592 /* Determine the PF number based on the PCI fn */
593 reg = rd32(hw, I40E_GLPCI_CAPSUP);
594 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
595 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
597 hw->pf_id = (u8)hw->bus.func;
599 status = i40e_init_nvm(hw);
604 * i40e_aq_mac_address_read - Retrieve the MAC addresses
605 * @hw: pointer to the hw struct
606 * @flags: a return indicator of what addresses were added to the addr store
607 * @addrs: the requestor's mac addr store
608 * @cmd_details: pointer to command details structure or NULL
610 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
612 struct i40e_aqc_mac_address_read_data *addrs,
613 struct i40e_asq_cmd_details *cmd_details)
615 struct i40e_aq_desc desc;
616 struct i40e_aqc_mac_address_read *cmd_data =
617 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
618 enum i40e_status_code status;
620 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
621 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
623 status = i40e_asq_send_command(hw, &desc, addrs,
624 sizeof(*addrs), cmd_details);
625 *flags = LE16_TO_CPU(cmd_data->command_flags);
631 * i40e_aq_mac_address_write - Change the MAC addresses
632 * @hw: pointer to the hw struct
633 * @flags: indicates which MAC to be written
634 * @mac_addr: address to write
635 * @cmd_details: pointer to command details structure or NULL
637 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
638 u16 flags, u8 *mac_addr,
639 struct i40e_asq_cmd_details *cmd_details)
641 struct i40e_aq_desc desc;
642 struct i40e_aqc_mac_address_write *cmd_data =
643 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
644 enum i40e_status_code status;
646 i40e_fill_default_direct_cmd_desc(&desc,
647 i40e_aqc_opc_mac_address_write);
648 cmd_data->command_flags = CPU_TO_LE16(flags);
649 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
650 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
651 ((u32)mac_addr[3] << 16) |
652 ((u32)mac_addr[4] << 8) |
655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
661 * i40e_get_mac_addr - get MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to MAC address
665 * Reads the adapter's MAC address from register
667 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
669 struct i40e_aqc_mac_address_read_data addrs;
670 enum i40e_status_code status;
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
675 if (flags & I40E_AQC_LAN_ADDR_VALID)
676 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
682 * i40e_get_port_mac_addr - get Port MAC address
683 * @hw: pointer to the HW structure
684 * @mac_addr: pointer to Port MAC address
686 * Reads the adapter's Port MAC address
688 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
690 struct i40e_aqc_mac_address_read_data addrs;
691 enum i40e_status_code status;
694 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
698 if (flags & I40E_AQC_PORT_ADDR_VALID)
699 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
701 status = I40E_ERR_INVALID_MAC_ADDR;
707 * i40e_pre_tx_queue_cfg - pre tx queue configure
708 * @hw: pointer to the HW structure
709 * @queue: target pf queue index
710 * @enable: state change request
712 * Handles hw requirement to indicate intention to enable
713 * or disable target queue.
715 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
717 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
721 if (abs_queue_idx >= 128) {
722 reg_block = abs_queue_idx / 128;
723 abs_queue_idx %= 128;
726 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
727 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
728 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
731 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
733 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
735 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
739 * i40e_validate_mac_addr - Validate unicast MAC address
740 * @mac_addr: pointer to MAC address
742 * Tests a MAC address to ensure it is a valid Individual Address
744 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
746 enum i40e_status_code status = I40E_SUCCESS;
748 DEBUGFUNC("i40e_validate_mac_addr");
750 /* Broadcast addresses ARE multicast addresses
751 * Make sure it is not a multicast address
752 * Reject the zero address
754 if (I40E_IS_MULTICAST(mac_addr) ||
755 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
756 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
757 status = I40E_ERR_INVALID_MAC_ADDR;
763 * i40e_get_media_type - Gets media type
764 * @hw: pointer to the hardware structure
766 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
768 enum i40e_media_type media;
770 switch (hw->phy.link_info.phy_type) {
771 case I40E_PHY_TYPE_10GBASE_SR:
772 case I40E_PHY_TYPE_10GBASE_LR:
773 case I40E_PHY_TYPE_1000BASE_SX:
774 case I40E_PHY_TYPE_1000BASE_LX:
775 case I40E_PHY_TYPE_40GBASE_SR4:
776 case I40E_PHY_TYPE_40GBASE_LR4:
777 media = I40E_MEDIA_TYPE_FIBER;
779 case I40E_PHY_TYPE_100BASE_TX:
780 case I40E_PHY_TYPE_1000BASE_T:
781 case I40E_PHY_TYPE_10GBASE_T:
782 media = I40E_MEDIA_TYPE_BASET;
784 case I40E_PHY_TYPE_10GBASE_CR1_CU:
785 case I40E_PHY_TYPE_40GBASE_CR4_CU:
786 case I40E_PHY_TYPE_10GBASE_CR1:
787 case I40E_PHY_TYPE_40GBASE_CR4:
788 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
789 media = I40E_MEDIA_TYPE_DA;
791 case I40E_PHY_TYPE_1000BASE_KX:
792 case I40E_PHY_TYPE_10GBASE_KX4:
793 case I40E_PHY_TYPE_10GBASE_KR:
794 case I40E_PHY_TYPE_40GBASE_KR4:
795 media = I40E_MEDIA_TYPE_BACKPLANE;
797 case I40E_PHY_TYPE_SGMII:
798 case I40E_PHY_TYPE_XAUI:
799 case I40E_PHY_TYPE_XFI:
800 case I40E_PHY_TYPE_XLAUI:
801 case I40E_PHY_TYPE_XLPPI:
803 media = I40E_MEDIA_TYPE_UNKNOWN;
810 #define I40E_PF_RESET_WAIT_COUNT 100
812 * i40e_pf_reset - Reset the PF
813 * @hw: pointer to the hardware structure
815 * Assuming someone else has triggered a global reset,
816 * assure the global reset is complete and then reset the PF
818 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
825 /* Poll for Global Reset steady state in case of recent GRST.
826 * The grst delay value is in 100ms units, and we'll wait a
827 * couple counts longer to be sure we don't just miss the end.
829 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
830 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
831 for (cnt = 0; cnt < grst_del + 2; cnt++) {
832 reg = rd32(hw, I40E_GLGEN_RSTAT);
833 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
835 i40e_msec_delay(100);
837 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
838 DEBUGOUT("Global reset polling failed to complete.\n");
839 return I40E_ERR_RESET_FAILED;
842 /* Now Wait for the FW to be ready */
843 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
844 reg = rd32(hw, I40E_GLNVM_ULD);
845 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
846 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
847 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
848 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
849 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
854 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
855 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
856 DEBUGOUT("wait for FW Reset complete timedout\n");
857 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
858 return I40E_ERR_RESET_FAILED;
861 /* If there was a Global Reset in progress when we got here,
862 * we don't need to do the PF Reset
865 reg = rd32(hw, I40E_PFGEN_CTRL);
866 wr32(hw, I40E_PFGEN_CTRL,
867 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
868 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
869 reg = rd32(hw, I40E_PFGEN_CTRL);
870 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
874 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
875 DEBUGOUT("PF reset polling failed to complete.\n");
876 return I40E_ERR_RESET_FAILED;
880 i40e_clear_pxe_mode(hw);
887 * i40e_clear_hw - clear out any left over hw state
888 * @hw: pointer to the hw struct
890 * Clear queues and interrupts, typically called at init time,
891 * but after the capabilities have been found so we know how many
892 * queues and msix vectors have been allocated.
894 void i40e_clear_hw(struct i40e_hw *hw)
896 u32 num_queues, base_queue;
904 /* get number of interrupts, queues, and vfs */
905 val = rd32(hw, I40E_GLPCI_CNF2);
906 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
907 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
908 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
909 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
911 val = rd32(hw, I40E_PFLAN_QALLOC);
912 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
913 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
914 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
915 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
916 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
917 num_queues = (j - base_queue) + 1;
921 val = rd32(hw, I40E_PF_VT_PFALLOC);
922 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
923 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
924 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
925 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
926 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
927 num_vfs = (j - i) + 1;
931 /* stop all the interrupts */
932 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
933 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
934 for (i = 0; i < num_pf_int - 2; i++)
935 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
937 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
938 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
939 wr32(hw, I40E_PFINT_LNKLST0, val);
940 for (i = 0; i < num_pf_int - 2; i++)
941 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
942 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
943 for (i = 0; i < num_vfs; i++)
944 wr32(hw, I40E_VPINT_LNKLST0(i), val);
945 for (i = 0; i < num_vf_int - 2; i++)
946 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
948 /* warn the HW of the coming Tx disables */
949 for (i = 0; i < num_queues; i++) {
950 u32 abs_queue_idx = base_queue + i;
953 if (abs_queue_idx >= 128) {
954 reg_block = abs_queue_idx / 128;
955 abs_queue_idx %= 128;
958 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
959 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
960 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
961 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
963 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
965 i40e_usec_delay(400);
967 /* stop all the queues */
968 for (i = 0; i < num_queues; i++) {
969 wr32(hw, I40E_QINT_TQCTL(i), 0);
970 wr32(hw, I40E_QTX_ENA(i), 0);
971 wr32(hw, I40E_QINT_RQCTL(i), 0);
972 wr32(hw, I40E_QRX_ENA(i), 0);
975 /* short wait for all queue disables to settle */
980 * i40e_clear_pxe_mode - clear pxe operations mode
981 * @hw: pointer to the hw struct
983 * Make sure all PXE mode settings are cleared, including things
984 * like descriptor fetch/write-back mode.
986 void i40e_clear_pxe_mode(struct i40e_hw *hw)
988 if (i40e_check_asq_alive(hw))
989 i40e_aq_clear_pxe_mode(hw, NULL);
993 * i40e_led_is_mine - helper to find matching led
994 * @hw: pointer to the hw struct
995 * @idx: index into GPIO registers
997 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
999 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1004 if (!hw->func_caps.led[idx])
1007 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1008 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1009 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1011 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1012 * if it is not our port then ignore
1014 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1021 #define I40E_LED0 22
1022 #define I40E_LINK_ACTIVITY 0xC
1025 * i40e_led_get - return current on/off mode
1026 * @hw: pointer to the hw struct
1028 * The value returned is the 'mode' field as defined in the
1029 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1030 * values are variations of possible behaviors relating to
1031 * blink, link, and wire.
1033 u32 i40e_led_get(struct i40e_hw *hw)
1038 /* as per the documentation GPIO 22-29 are the LED
1039 * GPIO pins named LED0..LED7
1041 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1042 u32 gpio_val = i40e_led_is_mine(hw, i);
1047 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1048 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1056 * i40e_led_set - set new on/off mode
1057 * @hw: pointer to the hw struct
1058 * @mode: 0=off, 0xf=on (else see manual for mode details)
1059 * @blink: true if the LED should blink when on, false if steady
1061 * if this function is used to turn on the blink it should
1062 * be used to disable the blink when restoring the original state.
1064 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1068 if (mode & 0xfffffff0)
1069 DEBUGOUT1("invalid mode passed in %X\n", mode);
1071 /* as per the documentation GPIO 22-29 are the LED
1072 * GPIO pins named LED0..LED7
1074 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1075 u32 gpio_val = i40e_led_is_mine(hw, i);
1080 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1081 /* this & is a bit of paranoia, but serves as a range check */
1082 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1083 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1085 if (mode == I40E_LINK_ACTIVITY)
1088 gpio_val |= (blink ? 1 : 0) <<
1089 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1091 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1096 /* Admin command wrappers */
1099 * i40e_aq_get_phy_capabilities
1100 * @hw: pointer to the hw struct
1101 * @abilities: structure for PHY capabilities to be filled
1102 * @qualified_modules: report Qualified Modules
1103 * @report_init: report init capabilities (active are default)
1104 * @cmd_details: pointer to command details structure or NULL
1106 * Returns the various PHY abilities supported on the Port.
1108 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1109 bool qualified_modules, bool report_init,
1110 struct i40e_aq_get_phy_abilities_resp *abilities,
1111 struct i40e_asq_cmd_details *cmd_details)
1113 struct i40e_aq_desc desc;
1114 enum i40e_status_code status;
1115 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1118 return I40E_ERR_PARAM;
1120 i40e_fill_default_direct_cmd_desc(&desc,
1121 i40e_aqc_opc_get_phy_abilities);
1123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1124 if (abilities_size > I40E_AQ_LARGE_BUF)
1125 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1127 if (qualified_modules)
1128 desc.params.external.param0 |=
1129 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1132 desc.params.external.param0 |=
1133 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1135 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1138 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1139 status = I40E_ERR_UNKNOWN_PHY;
1145 * i40e_aq_set_phy_config
1146 * @hw: pointer to the hw struct
1147 * @config: structure with PHY configuration to be set
1148 * @cmd_details: pointer to command details structure or NULL
1150 * Set the various PHY configuration parameters
1151 * supported on the Port.One or more of the Set PHY config parameters may be
1152 * ignored in an MFP mode as the PF may not have the privilege to set some
1153 * of the PHY Config parameters. This status will be indicated by the
1156 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1157 struct i40e_aq_set_phy_config *config,
1158 struct i40e_asq_cmd_details *cmd_details)
1160 struct i40e_aq_desc desc;
1161 struct i40e_aq_set_phy_config *cmd =
1162 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1163 enum i40e_status_code status;
1166 return I40E_ERR_PARAM;
1168 i40e_fill_default_direct_cmd_desc(&desc,
1169 i40e_aqc_opc_set_phy_config);
1173 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1180 * @hw: pointer to the hw struct
1182 * Set the requested flow control mode using set_phy_config.
1184 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1185 bool atomic_restart)
1187 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1188 struct i40e_aq_get_phy_abilities_resp abilities;
1189 struct i40e_aq_set_phy_config config;
1190 enum i40e_status_code status;
1191 u8 pause_mask = 0x0;
1197 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1198 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1200 case I40E_FC_RX_PAUSE:
1201 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1203 case I40E_FC_TX_PAUSE:
1204 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1210 /* Get the current phy config */
1211 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1214 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1218 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1219 /* clear the old pause settings */
1220 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1221 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1222 /* set the new abilities */
1223 config.abilities |= pause_mask;
1224 /* If the abilities have changed, then set the new config */
1225 if (config.abilities != abilities.abilities) {
1226 /* Auto restart link so settings take effect */
1228 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1229 /* Copy over all the old settings */
1230 config.phy_type = abilities.phy_type;
1231 config.link_speed = abilities.link_speed;
1232 config.eee_capability = abilities.eee_capability;
1233 config.eeer = abilities.eeer_val;
1234 config.low_power_ctrl = abilities.d3_lpan;
1235 status = i40e_aq_set_phy_config(hw, &config, NULL);
1238 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1240 /* Update the link info */
1241 status = i40e_update_link_info(hw, true);
1243 /* Wait a little bit (on 40G cards it sometimes takes a really
1244 * long time for link to come back from the atomic reset)
1247 i40e_msec_delay(1000);
1248 status = i40e_update_link_info(hw, true);
1251 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1257 * i40e_aq_set_mac_config
1258 * @hw: pointer to the hw struct
1259 * @max_frame_size: Maximum Frame Size to be supported by the port
1260 * @crc_en: Tell HW to append a CRC to outgoing frames
1261 * @pacing: Pacing configurations
1262 * @cmd_details: pointer to command details structure or NULL
1264 * Configure MAC settings for frame size, jumbo frame support and the
1265 * addition of a CRC by the hardware.
1267 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1269 bool crc_en, u16 pacing,
1270 struct i40e_asq_cmd_details *cmd_details)
1272 struct i40e_aq_desc desc;
1273 struct i40e_aq_set_mac_config *cmd =
1274 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1275 enum i40e_status_code status;
1277 if (max_frame_size == 0)
1278 return I40E_ERR_PARAM;
1280 i40e_fill_default_direct_cmd_desc(&desc,
1281 i40e_aqc_opc_set_mac_config);
1283 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1284 cmd->params = ((u8)pacing & 0x0F) << 3;
1286 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1288 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1294 * i40e_aq_clear_pxe_mode
1295 * @hw: pointer to the hw struct
1296 * @cmd_details: pointer to command details structure or NULL
1298 * Tell the firmware that the driver is taking over from PXE
1300 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1301 struct i40e_asq_cmd_details *cmd_details)
1303 enum i40e_status_code status;
1304 struct i40e_aq_desc desc;
1305 struct i40e_aqc_clear_pxe *cmd =
1306 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1308 i40e_fill_default_direct_cmd_desc(&desc,
1309 i40e_aqc_opc_clear_pxe_mode);
1313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1315 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1321 * i40e_aq_set_link_restart_an
1322 * @hw: pointer to the hw struct
1323 * @enable_link: if true: enable link, if false: disable link
1324 * @cmd_details: pointer to command details structure or NULL
1326 * Sets up the link and restarts the Auto-Negotiation over the link.
1328 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1329 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1331 struct i40e_aq_desc desc;
1332 struct i40e_aqc_set_link_restart_an *cmd =
1333 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1334 enum i40e_status_code status;
1336 i40e_fill_default_direct_cmd_desc(&desc,
1337 i40e_aqc_opc_set_link_restart_an);
1339 cmd->command = I40E_AQ_PHY_RESTART_AN;
1341 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1343 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1351 * i40e_aq_get_link_info
1352 * @hw: pointer to the hw struct
1353 * @enable_lse: enable/disable LinkStatusEvent reporting
1354 * @link: pointer to link status structure - optional
1355 * @cmd_details: pointer to command details structure or NULL
1357 * Returns the link status of the adapter.
1359 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1360 bool enable_lse, struct i40e_link_status *link,
1361 struct i40e_asq_cmd_details *cmd_details)
1363 struct i40e_aq_desc desc;
1364 struct i40e_aqc_get_link_status *resp =
1365 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1366 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1367 enum i40e_status_code status;
1368 bool tx_pause, rx_pause;
1371 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1374 command_flags = I40E_AQ_LSE_ENABLE;
1376 command_flags = I40E_AQ_LSE_DISABLE;
1377 resp->command_flags = CPU_TO_LE16(command_flags);
1379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1381 if (status != I40E_SUCCESS)
1382 goto aq_get_link_info_exit;
1384 /* save off old link status information */
1385 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1386 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1388 /* update link status */
1389 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1390 hw->phy.media_type = i40e_get_media_type(hw);
1391 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1392 hw_link_info->link_info = resp->link_info;
1393 hw_link_info->an_info = resp->an_info;
1394 hw_link_info->ext_info = resp->ext_info;
1395 hw_link_info->loopback = resp->loopback;
1396 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1397 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1399 /* update fc info */
1400 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1401 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1402 if (tx_pause & rx_pause)
1403 hw->fc.current_mode = I40E_FC_FULL;
1405 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1407 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1409 hw->fc.current_mode = I40E_FC_NONE;
1411 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1412 hw_link_info->crc_enable = true;
1414 hw_link_info->crc_enable = false;
1416 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1417 hw_link_info->lse_enable = true;
1419 hw_link_info->lse_enable = false;
1421 /* save link status information */
1423 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1424 I40E_NONDMA_TO_NONDMA);
1426 /* flag cleared so helper functions don't call AQ again */
1427 hw->phy.get_link_info = false;
1429 aq_get_link_info_exit:
1434 * i40e_update_link_info
1435 * @hw: pointer to the hw struct
1436 * @enable_lse: enable/disable LinkStatusEvent reporting
1438 * Returns the link status of the adapter
1440 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1443 struct i40e_aq_get_phy_abilities_resp abilities;
1444 enum i40e_status_code status;
1446 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1450 status = i40e_aq_get_phy_capabilities(hw, false, false,
1455 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1456 hw->phy.link_info.an_enabled = true;
1458 hw->phy.link_info.an_enabled = false;
1464 * i40e_aq_set_phy_int_mask
1465 * @hw: pointer to the hw struct
1466 * @mask: interrupt mask to be set
1467 * @cmd_details: pointer to command details structure or NULL
1469 * Set link interrupt mask.
1471 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1473 struct i40e_asq_cmd_details *cmd_details)
1475 struct i40e_aq_desc desc;
1476 struct i40e_aqc_set_phy_int_mask *cmd =
1477 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1478 enum i40e_status_code status;
1480 i40e_fill_default_direct_cmd_desc(&desc,
1481 i40e_aqc_opc_set_phy_int_mask);
1483 cmd->event_mask = CPU_TO_LE16(mask);
1485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1491 * i40e_aq_get_local_advt_reg
1492 * @hw: pointer to the hw struct
1493 * @advt_reg: local AN advertisement register value
1494 * @cmd_details: pointer to command details structure or NULL
1496 * Get the Local AN advertisement register value.
1498 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1500 struct i40e_asq_cmd_details *cmd_details)
1502 struct i40e_aq_desc desc;
1503 struct i40e_aqc_an_advt_reg *resp =
1504 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1505 enum i40e_status_code status;
1507 i40e_fill_default_direct_cmd_desc(&desc,
1508 i40e_aqc_opc_get_local_advt_reg);
1510 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1512 if (status != I40E_SUCCESS)
1513 goto aq_get_local_advt_reg_exit;
1515 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1516 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1518 aq_get_local_advt_reg_exit:
1523 * i40e_aq_set_local_advt_reg
1524 * @hw: pointer to the hw struct
1525 * @advt_reg: local AN advertisement register value
1526 * @cmd_details: pointer to command details structure or NULL
1528 * Get the Local AN advertisement register value.
1530 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1532 struct i40e_asq_cmd_details *cmd_details)
1534 struct i40e_aq_desc desc;
1535 struct i40e_aqc_an_advt_reg *cmd =
1536 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1537 enum i40e_status_code status;
1539 i40e_fill_default_direct_cmd_desc(&desc,
1540 i40e_aqc_opc_get_local_advt_reg);
1542 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1543 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1551 * i40e_aq_get_partner_advt
1552 * @hw: pointer to the hw struct
1553 * @advt_reg: AN partner advertisement register value
1554 * @cmd_details: pointer to command details structure or NULL
1556 * Get the link partner AN advertisement register value.
1558 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1560 struct i40e_asq_cmd_details *cmd_details)
1562 struct i40e_aq_desc desc;
1563 struct i40e_aqc_an_advt_reg *resp =
1564 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1565 enum i40e_status_code status;
1567 i40e_fill_default_direct_cmd_desc(&desc,
1568 i40e_aqc_opc_get_partner_advt);
1570 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1572 if (status != I40E_SUCCESS)
1573 goto aq_get_partner_advt_exit;
1575 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1576 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1578 aq_get_partner_advt_exit:
1583 * i40e_aq_set_lb_modes
1584 * @hw: pointer to the hw struct
1585 * @lb_modes: loopback mode to be set
1586 * @cmd_details: pointer to command details structure or NULL
1588 * Sets loopback modes.
1590 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1592 struct i40e_asq_cmd_details *cmd_details)
1594 struct i40e_aq_desc desc;
1595 struct i40e_aqc_set_lb_mode *cmd =
1596 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1597 enum i40e_status_code status;
1599 i40e_fill_default_direct_cmd_desc(&desc,
1600 i40e_aqc_opc_set_lb_modes);
1602 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1604 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1610 * i40e_aq_set_phy_debug
1611 * @hw: pointer to the hw struct
1612 * @cmd_flags: debug command flags
1613 * @cmd_details: pointer to command details structure or NULL
1615 * Reset the external PHY.
1617 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1618 struct i40e_asq_cmd_details *cmd_details)
1620 struct i40e_aq_desc desc;
1621 struct i40e_aqc_set_phy_debug *cmd =
1622 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1623 enum i40e_status_code status;
1625 i40e_fill_default_direct_cmd_desc(&desc,
1626 i40e_aqc_opc_set_phy_debug);
1628 cmd->command_flags = cmd_flags;
1630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1637 * @hw: pointer to the hw struct
1638 * @vsi_ctx: pointer to a vsi context struct
1639 * @cmd_details: pointer to command details structure or NULL
1641 * Add a VSI context to the hardware.
1643 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1644 struct i40e_vsi_context *vsi_ctx,
1645 struct i40e_asq_cmd_details *cmd_details)
1647 struct i40e_aq_desc desc;
1648 struct i40e_aqc_add_get_update_vsi *cmd =
1649 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1650 struct i40e_aqc_add_get_update_vsi_completion *resp =
1651 (struct i40e_aqc_add_get_update_vsi_completion *)
1653 enum i40e_status_code status;
1655 i40e_fill_default_direct_cmd_desc(&desc,
1656 i40e_aqc_opc_add_vsi);
1658 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1659 cmd->connection_type = vsi_ctx->connection_type;
1660 cmd->vf_id = vsi_ctx->vf_num;
1661 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1663 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1665 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1666 sizeof(vsi_ctx->info), cmd_details);
1668 if (status != I40E_SUCCESS)
1669 goto aq_add_vsi_exit;
1671 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1672 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1673 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1674 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1681 * i40e_aq_set_default_vsi
1682 * @hw: pointer to the hw struct
1684 * @cmd_details: pointer to command details structure or NULL
1686 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1688 struct i40e_asq_cmd_details *cmd_details)
1690 struct i40e_aq_desc desc;
1691 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1692 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1694 enum i40e_status_code status;
1696 i40e_fill_default_direct_cmd_desc(&desc,
1697 i40e_aqc_opc_set_vsi_promiscuous_modes);
1699 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1700 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1701 cmd->seid = CPU_TO_LE16(seid);
1703 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1709 * i40e_aq_set_vsi_unicast_promiscuous
1710 * @hw: pointer to the hw struct
1712 * @set: set unicast promiscuous enable/disable
1713 * @cmd_details: pointer to command details structure or NULL
1715 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1717 struct i40e_asq_cmd_details *cmd_details)
1719 struct i40e_aq_desc desc;
1720 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1721 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1722 enum i40e_status_code status;
1725 i40e_fill_default_direct_cmd_desc(&desc,
1726 i40e_aqc_opc_set_vsi_promiscuous_modes);
1729 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1731 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1733 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1735 cmd->seid = CPU_TO_LE16(seid);
1736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1742 * i40e_aq_set_vsi_multicast_promiscuous
1743 * @hw: pointer to the hw struct
1745 * @set: set multicast promiscuous enable/disable
1746 * @cmd_details: pointer to command details structure or NULL
1748 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1749 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1751 struct i40e_aq_desc desc;
1752 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1753 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1754 enum i40e_status_code status;
1757 i40e_fill_default_direct_cmd_desc(&desc,
1758 i40e_aqc_opc_set_vsi_promiscuous_modes);
1761 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1763 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1765 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1767 cmd->seid = CPU_TO_LE16(seid);
1768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1774 * i40e_aq_set_vsi_broadcast
1775 * @hw: pointer to the hw struct
1777 * @set_filter: true to set filter, false to clear filter
1778 * @cmd_details: pointer to command details structure or NULL
1780 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1782 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1783 u16 seid, bool set_filter,
1784 struct i40e_asq_cmd_details *cmd_details)
1786 struct i40e_aq_desc desc;
1787 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1788 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1789 enum i40e_status_code status;
1791 i40e_fill_default_direct_cmd_desc(&desc,
1792 i40e_aqc_opc_set_vsi_promiscuous_modes);
1795 cmd->promiscuous_flags
1796 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1798 cmd->promiscuous_flags
1799 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1801 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1802 cmd->seid = CPU_TO_LE16(seid);
1803 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1809 * i40e_get_vsi_params - get VSI configuration info
1810 * @hw: pointer to the hw struct
1811 * @vsi_ctx: pointer to a vsi context struct
1812 * @cmd_details: pointer to command details structure or NULL
1814 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1815 struct i40e_vsi_context *vsi_ctx,
1816 struct i40e_asq_cmd_details *cmd_details)
1818 struct i40e_aq_desc desc;
1819 struct i40e_aqc_add_get_update_vsi *cmd =
1820 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1821 struct i40e_aqc_add_get_update_vsi_completion *resp =
1822 (struct i40e_aqc_add_get_update_vsi_completion *)
1824 enum i40e_status_code status;
1826 UNREFERENCED_1PARAMETER(cmd_details);
1827 i40e_fill_default_direct_cmd_desc(&desc,
1828 i40e_aqc_opc_get_vsi_parameters);
1830 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1832 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1834 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1835 sizeof(vsi_ctx->info), NULL);
1837 if (status != I40E_SUCCESS)
1838 goto aq_get_vsi_params_exit;
1840 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1841 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1842 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1843 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1845 aq_get_vsi_params_exit:
1850 * i40e_aq_update_vsi_params
1851 * @hw: pointer to the hw struct
1852 * @vsi_ctx: pointer to a vsi context struct
1853 * @cmd_details: pointer to command details structure or NULL
1855 * Update a VSI context.
1857 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1858 struct i40e_vsi_context *vsi_ctx,
1859 struct i40e_asq_cmd_details *cmd_details)
1861 struct i40e_aq_desc desc;
1862 struct i40e_aqc_add_get_update_vsi *cmd =
1863 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1864 enum i40e_status_code status;
1866 i40e_fill_default_direct_cmd_desc(&desc,
1867 i40e_aqc_opc_update_vsi_parameters);
1868 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1870 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1872 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1873 sizeof(vsi_ctx->info), cmd_details);
1879 * i40e_aq_get_switch_config
1880 * @hw: pointer to the hardware structure
1881 * @buf: pointer to the result buffer
1882 * @buf_size: length of input buffer
1883 * @start_seid: seid to start for the report, 0 == beginning
1884 * @cmd_details: pointer to command details structure or NULL
1886 * Fill the buf with switch configuration returned from AdminQ command
1888 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1889 struct i40e_aqc_get_switch_config_resp *buf,
1890 u16 buf_size, u16 *start_seid,
1891 struct i40e_asq_cmd_details *cmd_details)
1893 struct i40e_aq_desc desc;
1894 struct i40e_aqc_switch_seid *scfg =
1895 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1896 enum i40e_status_code status;
1898 i40e_fill_default_direct_cmd_desc(&desc,
1899 i40e_aqc_opc_get_switch_config);
1900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1901 if (buf_size > I40E_AQ_LARGE_BUF)
1902 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1903 scfg->seid = CPU_TO_LE16(*start_seid);
1905 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1906 *start_seid = LE16_TO_CPU(scfg->seid);
1912 * i40e_aq_get_firmware_version
1913 * @hw: pointer to the hw struct
1914 * @fw_major_version: firmware major version
1915 * @fw_minor_version: firmware minor version
1916 * @fw_build: firmware build number
1917 * @api_major_version: major queue version
1918 * @api_minor_version: minor queue version
1919 * @cmd_details: pointer to command details structure or NULL
1921 * Get the firmware version from the admin queue commands
1923 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1924 u16 *fw_major_version, u16 *fw_minor_version,
1926 u16 *api_major_version, u16 *api_minor_version,
1927 struct i40e_asq_cmd_details *cmd_details)
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_get_version *resp =
1931 (struct i40e_aqc_get_version *)&desc.params.raw;
1932 enum i40e_status_code status;
1934 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1936 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1938 if (status == I40E_SUCCESS) {
1939 if (fw_major_version != NULL)
1940 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1941 if (fw_minor_version != NULL)
1942 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1943 if (fw_build != NULL)
1944 *fw_build = LE32_TO_CPU(resp->fw_build);
1945 if (api_major_version != NULL)
1946 *api_major_version = LE16_TO_CPU(resp->api_major);
1947 if (api_minor_version != NULL)
1948 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1950 /* A workaround to fix the API version in SW */
1951 if (api_major_version && api_minor_version &&
1952 fw_major_version && fw_minor_version &&
1953 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1954 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1955 (*fw_major_version > 4)))
1956 *api_minor_version = 2;
1963 * i40e_aq_send_driver_version
1964 * @hw: pointer to the hw struct
1965 * @dv: driver's major, minor version
1966 * @cmd_details: pointer to command details structure or NULL
1968 * Send the driver version to the firmware
1970 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1971 struct i40e_driver_version *dv,
1972 struct i40e_asq_cmd_details *cmd_details)
1974 struct i40e_aq_desc desc;
1975 struct i40e_aqc_driver_version *cmd =
1976 (struct i40e_aqc_driver_version *)&desc.params.raw;
1977 enum i40e_status_code status;
1981 return I40E_ERR_PARAM;
1983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1985 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1986 cmd->driver_major_ver = dv->major_version;
1987 cmd->driver_minor_ver = dv->minor_version;
1988 cmd->driver_build_ver = dv->build_version;
1989 cmd->driver_subbuild_ver = dv->subbuild_version;
1992 while (len < sizeof(dv->driver_string) &&
1993 (dv->driver_string[len] < 0x80) &&
1994 dv->driver_string[len])
1996 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2003 * i40e_get_link_status - get status of the HW network link
2004 * @hw: pointer to the hw struct
2006 * Returns true if link is up, false if link is down.
2008 * Side effect: LinkStatusEvent reporting becomes enabled
2010 bool i40e_get_link_status(struct i40e_hw *hw)
2012 enum i40e_status_code status = I40E_SUCCESS;
2013 bool link_status = false;
2015 if (hw->phy.get_link_info) {
2016 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2018 if (status != I40E_SUCCESS)
2019 goto i40e_get_link_status_exit;
2022 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2024 i40e_get_link_status_exit:
2029 * i40e_get_link_speed
2030 * @hw: pointer to the hw struct
2032 * Returns the link speed of the adapter.
2034 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2036 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2037 enum i40e_status_code status = I40E_SUCCESS;
2039 if (hw->phy.get_link_info) {
2040 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2042 if (status != I40E_SUCCESS)
2043 goto i40e_link_speed_exit;
2046 speed = hw->phy.link_info.link_speed;
2048 i40e_link_speed_exit:
2053 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2054 * @hw: pointer to the hw struct
2055 * @uplink_seid: the MAC or other gizmo SEID
2056 * @downlink_seid: the VSI SEID
2057 * @enabled_tc: bitmap of TCs to be enabled
2058 * @default_port: true for default port VSI, false for control port
2059 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2060 * @veb_seid: pointer to where to put the resulting VEB SEID
2061 * @cmd_details: pointer to command details structure or NULL
2063 * This asks the FW to add a VEB between the uplink and downlink
2064 * elements. If the uplink SEID is 0, this will be a floating VEB.
2066 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2067 u16 downlink_seid, u8 enabled_tc,
2068 bool default_port, bool enable_l2_filtering,
2070 struct i40e_asq_cmd_details *cmd_details)
2072 struct i40e_aq_desc desc;
2073 struct i40e_aqc_add_veb *cmd =
2074 (struct i40e_aqc_add_veb *)&desc.params.raw;
2075 struct i40e_aqc_add_veb_completion *resp =
2076 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2077 enum i40e_status_code status;
2080 /* SEIDs need to either both be set or both be 0 for floating VEB */
2081 if (!!uplink_seid != !!downlink_seid)
2082 return I40E_ERR_PARAM;
2084 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2086 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2087 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2088 cmd->enable_tcs = enabled_tc;
2090 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2092 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2094 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2096 if (enable_l2_filtering)
2097 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2099 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2101 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2103 if (!status && veb_seid)
2104 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2110 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2111 * @hw: pointer to the hw struct
2112 * @veb_seid: the SEID of the VEB to query
2113 * @switch_id: the uplink switch id
2114 * @floating: set to true if the VEB is floating
2115 * @statistic_index: index of the stats counter block for this VEB
2116 * @vebs_used: number of VEB's used by function
2117 * @vebs_free: total VEB's not reserved by any function
2118 * @cmd_details: pointer to command details structure or NULL
2120 * This retrieves the parameters for a particular VEB, specified by
2121 * uplink_seid, and returns them to the caller.
2123 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2124 u16 veb_seid, u16 *switch_id,
2125 bool *floating, u16 *statistic_index,
2126 u16 *vebs_used, u16 *vebs_free,
2127 struct i40e_asq_cmd_details *cmd_details)
2129 struct i40e_aq_desc desc;
2130 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2131 (struct i40e_aqc_get_veb_parameters_completion *)
2133 enum i40e_status_code status;
2136 return I40E_ERR_PARAM;
2138 i40e_fill_default_direct_cmd_desc(&desc,
2139 i40e_aqc_opc_get_veb_parameters);
2140 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2142 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2147 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2148 if (statistic_index)
2149 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2151 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2153 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2155 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2156 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2167 * i40e_aq_add_macvlan
2168 * @hw: pointer to the hw struct
2169 * @seid: VSI for the mac address
2170 * @mv_list: list of macvlans to be added
2171 * @count: length of the list
2172 * @cmd_details: pointer to command details structure or NULL
2174 * Add MAC/VLAN addresses to the HW filtering
2176 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2177 struct i40e_aqc_add_macvlan_element_data *mv_list,
2178 u16 count, struct i40e_asq_cmd_details *cmd_details)
2180 struct i40e_aq_desc desc;
2181 struct i40e_aqc_macvlan *cmd =
2182 (struct i40e_aqc_macvlan *)&desc.params.raw;
2183 enum i40e_status_code status;
2186 if (count == 0 || !mv_list || !hw)
2187 return I40E_ERR_PARAM;
2189 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2191 /* prep the rest of the request */
2192 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2193 cmd->num_addresses = CPU_TO_LE16(count);
2194 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2198 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2199 if (buf_size > I40E_AQ_LARGE_BUF)
2200 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2202 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2209 * i40e_aq_remove_macvlan
2210 * @hw: pointer to the hw struct
2211 * @seid: VSI for the mac address
2212 * @mv_list: list of macvlans to be removed
2213 * @count: length of the list
2214 * @cmd_details: pointer to command details structure or NULL
2216 * Remove MAC/VLAN addresses from the HW filtering
2218 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2219 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2220 u16 count, struct i40e_asq_cmd_details *cmd_details)
2222 struct i40e_aq_desc desc;
2223 struct i40e_aqc_macvlan *cmd =
2224 (struct i40e_aqc_macvlan *)&desc.params.raw;
2225 enum i40e_status_code status;
2228 if (count == 0 || !mv_list || !hw)
2229 return I40E_ERR_PARAM;
2231 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2233 /* prep the rest of the request */
2234 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2235 cmd->num_addresses = CPU_TO_LE16(count);
2236 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2240 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2241 if (buf_size > I40E_AQ_LARGE_BUF)
2242 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2244 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2251 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2252 * @hw: pointer to the hw struct
2253 * @seid: VSI for the vlan filters
2254 * @v_list: list of vlan filters to be added
2255 * @count: length of the list
2256 * @cmd_details: pointer to command details structure or NULL
2258 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2259 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2260 u8 count, struct i40e_asq_cmd_details *cmd_details)
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_macvlan *cmd =
2264 (struct i40e_aqc_macvlan *)&desc.params.raw;
2265 enum i40e_status_code status;
2268 if (count == 0 || !v_list || !hw)
2269 return I40E_ERR_PARAM;
2271 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2273 /* prep the rest of the request */
2274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2275 cmd->num_addresses = CPU_TO_LE16(count);
2276 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2280 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2281 if (buf_size > I40E_AQ_LARGE_BUF)
2282 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2284 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2291 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2292 * @hw: pointer to the hw struct
2293 * @seid: VSI for the vlan filters
2294 * @v_list: list of macvlans to be removed
2295 * @count: length of the list
2296 * @cmd_details: pointer to command details structure or NULL
2298 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2299 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2300 u8 count, struct i40e_asq_cmd_details *cmd_details)
2302 struct i40e_aq_desc desc;
2303 struct i40e_aqc_macvlan *cmd =
2304 (struct i40e_aqc_macvlan *)&desc.params.raw;
2305 enum i40e_status_code status;
2308 if (count == 0 || !v_list || !hw)
2309 return I40E_ERR_PARAM;
2311 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2313 /* prep the rest of the request */
2314 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2315 cmd->num_addresses = CPU_TO_LE16(count);
2316 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2320 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2321 if (buf_size > I40E_AQ_LARGE_BUF)
2322 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2324 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2331 * i40e_aq_send_msg_to_vf
2332 * @hw: pointer to the hardware structure
2333 * @vfid: vf id to send msg
2334 * @v_opcode: opcodes for VF-PF communication
2335 * @v_retval: return error code
2336 * @msg: pointer to the msg buffer
2337 * @msglen: msg length
2338 * @cmd_details: pointer to command details
2342 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2343 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2344 struct i40e_asq_cmd_details *cmd_details)
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_pf_vf_message *cmd =
2348 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2349 enum i40e_status_code status;
2351 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2352 cmd->id = CPU_TO_LE32(vfid);
2353 desc.cookie_high = CPU_TO_LE32(v_opcode);
2354 desc.cookie_low = CPU_TO_LE32(v_retval);
2355 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2357 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2359 if (msglen > I40E_AQ_LARGE_BUF)
2360 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2361 desc.datalen = CPU_TO_LE16(msglen);
2363 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2369 * i40e_aq_debug_read_register
2370 * @hw: pointer to the hw struct
2371 * @reg_addr: register address
2372 * @reg_val: register value
2373 * @cmd_details: pointer to command details structure or NULL
2375 * Read the register using the admin queue commands
2377 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2378 u32 reg_addr, u64 *reg_val,
2379 struct i40e_asq_cmd_details *cmd_details)
2381 struct i40e_aq_desc desc;
2382 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2383 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2384 enum i40e_status_code status;
2386 if (reg_val == NULL)
2387 return I40E_ERR_PARAM;
2389 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2391 cmd_resp->address = CPU_TO_LE32(reg_addr);
2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2395 if (status == I40E_SUCCESS) {
2396 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2397 (u64)LE32_TO_CPU(cmd_resp->value_low);
2404 * i40e_aq_debug_write_register
2405 * @hw: pointer to the hw struct
2406 * @reg_addr: register address
2407 * @reg_val: register value
2408 * @cmd_details: pointer to command details structure or NULL
2410 * Write to a register using the admin queue commands
2412 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2413 u32 reg_addr, u64 reg_val,
2414 struct i40e_asq_cmd_details *cmd_details)
2416 struct i40e_aq_desc desc;
2417 struct i40e_aqc_debug_reg_read_write *cmd =
2418 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2419 enum i40e_status_code status;
2421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2423 cmd->address = CPU_TO_LE32(reg_addr);
2424 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2425 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2433 * i40e_aq_get_hmc_resource_profile
2434 * @hw: pointer to the hw struct
2435 * @profile: type of profile the HMC is to be set as
2436 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2437 * @cmd_details: pointer to command details structure or NULL
2439 * query the HMC profile of the device.
2441 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2442 enum i40e_aq_hmc_profile *profile,
2443 u8 *pe_vf_enabled_count,
2444 struct i40e_asq_cmd_details *cmd_details)
2446 struct i40e_aq_desc desc;
2447 struct i40e_aq_get_set_hmc_resource_profile *resp =
2448 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2449 enum i40e_status_code status;
2451 i40e_fill_default_direct_cmd_desc(&desc,
2452 i40e_aqc_opc_query_hmc_resource_profile);
2453 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2455 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2456 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2457 *pe_vf_enabled_count = resp->pe_vf_enabled &
2458 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2464 * i40e_aq_set_hmc_resource_profile
2465 * @hw: pointer to the hw struct
2466 * @profile: type of profile the HMC is to be set as
2467 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2468 * @cmd_details: pointer to command details structure or NULL
2470 * set the HMC profile of the device.
2472 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2473 enum i40e_aq_hmc_profile profile,
2474 u8 pe_vf_enabled_count,
2475 struct i40e_asq_cmd_details *cmd_details)
2477 struct i40e_aq_desc desc;
2478 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2479 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2480 enum i40e_status_code status;
2482 i40e_fill_default_direct_cmd_desc(&desc,
2483 i40e_aqc_opc_set_hmc_resource_profile);
2485 cmd->pm_profile = (u8)profile;
2486 cmd->pe_vf_enabled = pe_vf_enabled_count;
2488 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2494 * i40e_aq_request_resource
2495 * @hw: pointer to the hw struct
2496 * @resource: resource id
2497 * @access: access type
2498 * @sdp_number: resource number
2499 * @timeout: the maximum time in ms that the driver may hold the resource
2500 * @cmd_details: pointer to command details structure or NULL
2502 * requests common resource using the admin queue commands
2504 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2505 enum i40e_aq_resources_ids resource,
2506 enum i40e_aq_resource_access_type access,
2507 u8 sdp_number, u64 *timeout,
2508 struct i40e_asq_cmd_details *cmd_details)
2510 struct i40e_aq_desc desc;
2511 struct i40e_aqc_request_resource *cmd_resp =
2512 (struct i40e_aqc_request_resource *)&desc.params.raw;
2513 enum i40e_status_code status;
2515 DEBUGFUNC("i40e_aq_request_resource");
2517 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2519 cmd_resp->resource_id = CPU_TO_LE16(resource);
2520 cmd_resp->access_type = CPU_TO_LE16(access);
2521 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2524 /* The completion specifies the maximum time in ms that the driver
2525 * may hold the resource in the Timeout field.
2526 * If the resource is held by someone else, the command completes with
2527 * busy return value and the timeout field indicates the maximum time
2528 * the current owner of the resource has to free it.
2530 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2531 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2537 * i40e_aq_release_resource
2538 * @hw: pointer to the hw struct
2539 * @resource: resource id
2540 * @sdp_number: resource number
2541 * @cmd_details: pointer to command details structure or NULL
2543 * release common resource using the admin queue commands
2545 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2546 enum i40e_aq_resources_ids resource,
2548 struct i40e_asq_cmd_details *cmd_details)
2550 struct i40e_aq_desc desc;
2551 struct i40e_aqc_request_resource *cmd =
2552 (struct i40e_aqc_request_resource *)&desc.params.raw;
2553 enum i40e_status_code status;
2555 DEBUGFUNC("i40e_aq_release_resource");
2557 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2559 cmd->resource_id = CPU_TO_LE16(resource);
2560 cmd->resource_number = CPU_TO_LE32(sdp_number);
2562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2569 * @hw: pointer to the hw struct
2570 * @module_pointer: module pointer location in words from the NVM beginning
2571 * @offset: byte offset from the module beginning
2572 * @length: length of the section to be read (in bytes from the offset)
2573 * @data: command buffer (size [bytes] = length)
2574 * @last_command: tells if this is the last command in a series
2575 * @cmd_details: pointer to command details structure or NULL
2577 * Read the NVM using the admin queue commands
2579 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2580 u32 offset, u16 length, void *data,
2582 struct i40e_asq_cmd_details *cmd_details)
2584 struct i40e_aq_desc desc;
2585 struct i40e_aqc_nvm_update *cmd =
2586 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2587 enum i40e_status_code status;
2589 DEBUGFUNC("i40e_aq_read_nvm");
2591 /* In offset the highest byte must be zeroed. */
2592 if (offset & 0xFF000000) {
2593 status = I40E_ERR_PARAM;
2594 goto i40e_aq_read_nvm_exit;
2597 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2599 /* If this is the last command in a series, set the proper flag. */
2601 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2602 cmd->module_pointer = module_pointer;
2603 cmd->offset = CPU_TO_LE32(offset);
2604 cmd->length = CPU_TO_LE16(length);
2606 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2607 if (length > I40E_AQ_LARGE_BUF)
2608 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2610 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2612 i40e_aq_read_nvm_exit:
2618 * @hw: pointer to the hw struct
2619 * @module_pointer: module pointer location in words from the NVM beginning
2620 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2621 * @length: length of the section to be erased (expressed in 4 KB)
2622 * @last_command: tells if this is the last command in a series
2623 * @cmd_details: pointer to command details structure or NULL
2625 * Erase the NVM sector using the admin queue commands
2627 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2628 u32 offset, u16 length, bool last_command,
2629 struct i40e_asq_cmd_details *cmd_details)
2631 struct i40e_aq_desc desc;
2632 struct i40e_aqc_nvm_update *cmd =
2633 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2634 enum i40e_status_code status;
2636 DEBUGFUNC("i40e_aq_erase_nvm");
2638 /* In offset the highest byte must be zeroed. */
2639 if (offset & 0xFF000000) {
2640 status = I40E_ERR_PARAM;
2641 goto i40e_aq_erase_nvm_exit;
2644 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2646 /* If this is the last command in a series, set the proper flag. */
2648 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2649 cmd->module_pointer = module_pointer;
2650 cmd->offset = CPU_TO_LE32(offset);
2651 cmd->length = CPU_TO_LE16(length);
2653 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2655 i40e_aq_erase_nvm_exit:
2659 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2660 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2661 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2662 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2663 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2664 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2665 #define I40E_DEV_FUNC_CAP_VF 0x13
2666 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2667 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2668 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2669 #define I40E_DEV_FUNC_CAP_VSI 0x17
2670 #define I40E_DEV_FUNC_CAP_DCB 0x18
2671 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2672 #define I40E_DEV_FUNC_CAP_RSS 0x40
2673 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2674 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2675 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2676 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2677 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2678 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2679 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2680 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2681 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2682 #define I40E_DEV_FUNC_CAP_LED 0x61
2683 #define I40E_DEV_FUNC_CAP_SDP 0x62
2684 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2687 * i40e_parse_discover_capabilities
2688 * @hw: pointer to the hw struct
2689 * @buff: pointer to a buffer containing device/function capability records
2690 * @cap_count: number of capability records in the list
2691 * @list_type_opc: type of capabilities list to parse
2693 * Parse the device/function capabilities list.
2695 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2697 enum i40e_admin_queue_opc list_type_opc)
2699 struct i40e_aqc_list_capabilities_element_resp *cap;
2700 u32 number, logical_id, phys_id;
2701 struct i40e_hw_capabilities *p;
2705 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2707 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2708 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2709 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2710 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2714 for (i = 0; i < cap_count; i++, cap++) {
2715 id = LE16_TO_CPU(cap->id);
2716 number = LE32_TO_CPU(cap->number);
2717 logical_id = LE32_TO_CPU(cap->logical_id);
2718 phys_id = LE32_TO_CPU(cap->phys_id);
2721 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2722 p->switch_mode = number;
2724 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2725 p->management_mode = number;
2727 case I40E_DEV_FUNC_CAP_NPAR:
2728 p->npar_enable = number;
2730 case I40E_DEV_FUNC_CAP_OS2BMC:
2733 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2734 p->valid_functions = number;
2736 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2738 p->sr_iov_1_1 = true;
2740 case I40E_DEV_FUNC_CAP_VF:
2741 p->num_vfs = number;
2742 p->vf_base_id = logical_id;
2744 case I40E_DEV_FUNC_CAP_VMDQ:
2748 case I40E_DEV_FUNC_CAP_802_1_QBG:
2750 p->evb_802_1_qbg = true;
2752 case I40E_DEV_FUNC_CAP_802_1_QBH:
2754 p->evb_802_1_qbh = true;
2756 case I40E_DEV_FUNC_CAP_VSI:
2757 p->num_vsis = number;
2759 case I40E_DEV_FUNC_CAP_DCB:
2762 p->enabled_tcmap = logical_id;
2766 case I40E_DEV_FUNC_CAP_FCOE:
2770 case I40E_DEV_FUNC_CAP_RSS:
2772 p->rss_table_size = number;
2773 p->rss_table_entry_width = logical_id;
2775 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2776 p->num_rx_qp = number;
2777 p->base_queue = phys_id;
2779 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2780 p->num_tx_qp = number;
2781 p->base_queue = phys_id;
2783 case I40E_DEV_FUNC_CAP_MSIX:
2784 p->num_msix_vectors = number;
2786 case I40E_DEV_FUNC_CAP_MSIX_VF:
2787 p->num_msix_vectors_vf = number;
2789 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2791 p->mfp_mode_1 = true;
2793 case I40E_DEV_FUNC_CAP_CEM:
2797 case I40E_DEV_FUNC_CAP_IWARP:
2801 case I40E_DEV_FUNC_CAP_LED:
2802 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2803 p->led[phys_id] = true;
2805 case I40E_DEV_FUNC_CAP_SDP:
2806 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2807 p->sdp[phys_id] = true;
2809 case I40E_DEV_FUNC_CAP_MDIO:
2811 p->mdio_port_num = phys_id;
2812 p->mdio_port_mode = logical_id;
2815 case I40E_DEV_FUNC_CAP_IEEE_1588:
2817 p->ieee_1588 = true;
2819 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2821 p->fd_filters_guaranteed = number;
2822 p->fd_filters_best_effort = logical_id;
2829 /* Software override ensuring FCoE is disabled if npar or mfp
2830 * mode because it is not supported in these modes.
2832 if (p->npar_enable || p->mfp_mode_1)
2835 /* additional HW specific goodies that might
2836 * someday be HW version specific
2838 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2842 * i40e_aq_discover_capabilities
2843 * @hw: pointer to the hw struct
2844 * @buff: a virtual buffer to hold the capabilities
2845 * @buff_size: Size of the virtual buffer
2846 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2847 * @list_type_opc: capabilities type to discover - pass in the command opcode
2848 * @cmd_details: pointer to command details structure or NULL
2850 * Get the device capabilities descriptions from the firmware
2852 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2853 void *buff, u16 buff_size, u16 *data_size,
2854 enum i40e_admin_queue_opc list_type_opc,
2855 struct i40e_asq_cmd_details *cmd_details)
2857 struct i40e_aqc_list_capabilites *cmd;
2858 struct i40e_aq_desc desc;
2859 enum i40e_status_code status = I40E_SUCCESS;
2861 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2863 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2864 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2865 status = I40E_ERR_PARAM;
2869 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2871 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2872 if (buff_size > I40E_AQ_LARGE_BUF)
2873 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2875 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2876 *data_size = LE16_TO_CPU(desc.datalen);
2881 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2889 * i40e_aq_update_nvm
2890 * @hw: pointer to the hw struct
2891 * @module_pointer: module pointer location in words from the NVM beginning
2892 * @offset: byte offset from the module beginning
2893 * @length: length of the section to be written (in bytes from the offset)
2894 * @data: command buffer (size [bytes] = length)
2895 * @last_command: tells if this is the last command in a series
2896 * @cmd_details: pointer to command details structure or NULL
2898 * Update the NVM using the admin queue commands
2900 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2901 u32 offset, u16 length, void *data,
2903 struct i40e_asq_cmd_details *cmd_details)
2905 struct i40e_aq_desc desc;
2906 struct i40e_aqc_nvm_update *cmd =
2907 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2908 enum i40e_status_code status;
2910 DEBUGFUNC("i40e_aq_update_nvm");
2912 /* In offset the highest byte must be zeroed. */
2913 if (offset & 0xFF000000) {
2914 status = I40E_ERR_PARAM;
2915 goto i40e_aq_update_nvm_exit;
2918 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2920 /* If this is the last command in a series, set the proper flag. */
2922 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2923 cmd->module_pointer = module_pointer;
2924 cmd->offset = CPU_TO_LE32(offset);
2925 cmd->length = CPU_TO_LE16(length);
2927 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2928 if (length > I40E_AQ_LARGE_BUF)
2929 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2931 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2933 i40e_aq_update_nvm_exit:
2938 * i40e_aq_get_lldp_mib
2939 * @hw: pointer to the hw struct
2940 * @bridge_type: type of bridge requested
2941 * @mib_type: Local, Remote or both Local and Remote MIBs
2942 * @buff: pointer to a user supplied buffer to store the MIB block
2943 * @buff_size: size of the buffer (in bytes)
2944 * @local_len : length of the returned Local LLDP MIB
2945 * @remote_len: length of the returned Remote LLDP MIB
2946 * @cmd_details: pointer to command details structure or NULL
2948 * Requests the complete LLDP MIB (entire packet).
2950 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2951 u8 mib_type, void *buff, u16 buff_size,
2952 u16 *local_len, u16 *remote_len,
2953 struct i40e_asq_cmd_details *cmd_details)
2955 struct i40e_aq_desc desc;
2956 struct i40e_aqc_lldp_get_mib *cmd =
2957 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2958 struct i40e_aqc_lldp_get_mib *resp =
2959 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2960 enum i40e_status_code status;
2962 if (buff_size == 0 || !buff)
2963 return I40E_ERR_PARAM;
2965 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2966 /* Indirect Command */
2967 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2969 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2970 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2971 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2973 desc.datalen = CPU_TO_LE16(buff_size);
2975 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2976 if (buff_size > I40E_AQ_LARGE_BUF)
2977 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2979 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2981 if (local_len != NULL)
2982 *local_len = LE16_TO_CPU(resp->local_len);
2983 if (remote_len != NULL)
2984 *remote_len = LE16_TO_CPU(resp->remote_len);
2991 * i40e_aq_cfg_lldp_mib_change_event
2992 * @hw: pointer to the hw struct
2993 * @enable_update: Enable or Disable event posting
2994 * @cmd_details: pointer to command details structure or NULL
2996 * Enable or Disable posting of an event on ARQ when LLDP MIB
2997 * associated with the interface changes
2999 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3001 struct i40e_asq_cmd_details *cmd_details)
3003 struct i40e_aq_desc desc;
3004 struct i40e_aqc_lldp_update_mib *cmd =
3005 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3006 enum i40e_status_code status;
3008 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3011 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3019 * i40e_aq_add_lldp_tlv
3020 * @hw: pointer to the hw struct
3021 * @bridge_type: type of bridge
3022 * @buff: buffer with TLV to add
3023 * @buff_size: length of the buffer
3024 * @tlv_len: length of the TLV to be added
3025 * @mib_len: length of the LLDP MIB returned in response
3026 * @cmd_details: pointer to command details structure or NULL
3028 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3029 * it is responsibility of the caller to make sure that the TLV is not
3030 * already present in the LLDPDU.
3031 * In return firmware will write the complete LLDP MIB with the newly
3032 * added TLV in the response buffer.
3034 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3035 void *buff, u16 buff_size, u16 tlv_len,
3037 struct i40e_asq_cmd_details *cmd_details)
3039 struct i40e_aq_desc desc;
3040 struct i40e_aqc_lldp_add_tlv *cmd =
3041 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3042 enum i40e_status_code status;
3044 if (buff_size == 0 || !buff || tlv_len == 0)
3045 return I40E_ERR_PARAM;
3047 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3049 /* Indirect Command */
3050 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3051 if (buff_size > I40E_AQ_LARGE_BUF)
3052 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3053 desc.datalen = CPU_TO_LE16(buff_size);
3055 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3056 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3057 cmd->len = CPU_TO_LE16(tlv_len);
3059 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3061 if (mib_len != NULL)
3062 *mib_len = LE16_TO_CPU(desc.datalen);
3069 * i40e_aq_update_lldp_tlv
3070 * @hw: pointer to the hw struct
3071 * @bridge_type: type of bridge
3072 * @buff: buffer with TLV to update
3073 * @buff_size: size of the buffer holding original and updated TLVs
3074 * @old_len: Length of the Original TLV
3075 * @new_len: Length of the Updated TLV
3076 * @offset: offset of the updated TLV in the buff
3077 * @mib_len: length of the returned LLDP MIB
3078 * @cmd_details: pointer to command details structure or NULL
3080 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3081 * Firmware will place the complete LLDP MIB in response buffer with the
3084 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3085 u8 bridge_type, void *buff, u16 buff_size,
3086 u16 old_len, u16 new_len, u16 offset,
3088 struct i40e_asq_cmd_details *cmd_details)
3090 struct i40e_aq_desc desc;
3091 struct i40e_aqc_lldp_update_tlv *cmd =
3092 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3093 enum i40e_status_code status;
3095 if (buff_size == 0 || !buff || offset == 0 ||
3096 old_len == 0 || new_len == 0)
3097 return I40E_ERR_PARAM;
3099 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3101 /* Indirect Command */
3102 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3103 if (buff_size > I40E_AQ_LARGE_BUF)
3104 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3105 desc.datalen = CPU_TO_LE16(buff_size);
3107 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3108 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3109 cmd->old_len = CPU_TO_LE16(old_len);
3110 cmd->new_offset = CPU_TO_LE16(offset);
3111 cmd->new_len = CPU_TO_LE16(new_len);
3113 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3115 if (mib_len != NULL)
3116 *mib_len = LE16_TO_CPU(desc.datalen);
3123 * i40e_aq_delete_lldp_tlv
3124 * @hw: pointer to the hw struct
3125 * @bridge_type: type of bridge
3126 * @buff: pointer to a user supplied buffer that has the TLV
3127 * @buff_size: length of the buffer
3128 * @tlv_len: length of the TLV to be deleted
3129 * @mib_len: length of the returned LLDP MIB
3130 * @cmd_details: pointer to command details structure or NULL
3132 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3133 * The firmware places the entire LLDP MIB in the response buffer.
3135 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3136 u8 bridge_type, void *buff, u16 buff_size,
3137 u16 tlv_len, u16 *mib_len,
3138 struct i40e_asq_cmd_details *cmd_details)
3140 struct i40e_aq_desc desc;
3141 struct i40e_aqc_lldp_add_tlv *cmd =
3142 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3143 enum i40e_status_code status;
3145 if (buff_size == 0 || !buff)
3146 return I40E_ERR_PARAM;
3148 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3150 /* Indirect Command */
3151 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3152 if (buff_size > I40E_AQ_LARGE_BUF)
3153 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3154 desc.datalen = CPU_TO_LE16(buff_size);
3155 cmd->len = CPU_TO_LE16(tlv_len);
3156 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3157 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3159 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3161 if (mib_len != NULL)
3162 *mib_len = LE16_TO_CPU(desc.datalen);
3170 * @hw: pointer to the hw struct
3171 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3172 * @cmd_details: pointer to command details structure or NULL
3174 * Stop or Shutdown the embedded LLDP Agent
3176 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3177 struct i40e_asq_cmd_details *cmd_details)
3179 struct i40e_aq_desc desc;
3180 struct i40e_aqc_lldp_stop *cmd =
3181 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3182 enum i40e_status_code status;
3184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3187 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3189 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3195 * i40e_aq_start_lldp
3196 * @hw: pointer to the hw struct
3197 * @cmd_details: pointer to command details structure or NULL
3199 * Start the embedded LLDP Agent on all ports.
3201 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3202 struct i40e_asq_cmd_details *cmd_details)
3204 struct i40e_aq_desc desc;
3205 struct i40e_aqc_lldp_start *cmd =
3206 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3207 enum i40e_status_code status;
3209 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3211 cmd->command = I40E_AQ_LLDP_AGENT_START;
3213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3219 * i40e_aq_get_cee_dcb_config
3220 * @hw: pointer to the hw struct
3221 * @buff: response buffer that stores CEE operational configuration
3222 * @buff_size: size of the buffer passed
3223 * @cmd_details: pointer to command details structure or NULL
3225 * Get CEE DCBX mode operational configuration from firmware
3227 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3228 void *buff, u16 buff_size,
3229 struct i40e_asq_cmd_details *cmd_details)
3231 struct i40e_aq_desc desc;
3232 enum i40e_status_code status;
3234 if (buff_size == 0 || !buff)
3235 return I40E_ERR_PARAM;
3237 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3239 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3240 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3247 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3248 * @hw: pointer to the hw struct
3249 * @start_agent: True if DCBx Agent needs to be Started
3250 * False if DCBx Agent needs to be Stopped
3251 * @cmd_details: pointer to command details structure or NULL
3253 * Start/Stop the embedded dcbx Agent
3255 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3257 struct i40e_asq_cmd_details *cmd_details)
3259 struct i40e_aq_desc desc;
3260 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3261 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3263 enum i40e_status_code status;
3265 i40e_fill_default_direct_cmd_desc(&desc,
3266 i40e_aqc_opc_lldp_stop_start_spec_agent);
3269 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3277 * i40e_aq_add_udp_tunnel
3278 * @hw: pointer to the hw struct
3279 * @udp_port: the UDP port to add
3280 * @header_len: length of the tunneling header length in DWords
3281 * @protocol_index: protocol index type
3282 * @filter_index: pointer to filter index
3283 * @cmd_details: pointer to command details structure or NULL
3285 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3286 u16 udp_port, u8 protocol_index,
3288 struct i40e_asq_cmd_details *cmd_details)
3290 struct i40e_aq_desc desc;
3291 struct i40e_aqc_add_udp_tunnel *cmd =
3292 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3293 struct i40e_aqc_del_udp_tunnel_completion *resp =
3294 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3295 enum i40e_status_code status;
3297 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3299 cmd->udp_port = CPU_TO_LE16(udp_port);
3300 cmd->protocol_type = protocol_index;
3302 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3305 *filter_index = resp->index;
3311 * i40e_aq_del_udp_tunnel
3312 * @hw: pointer to the hw struct
3313 * @index: filter index
3314 * @cmd_details: pointer to command details structure or NULL
3316 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3317 struct i40e_asq_cmd_details *cmd_details)
3319 struct i40e_aq_desc desc;
3320 struct i40e_aqc_remove_udp_tunnel *cmd =
3321 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3322 enum i40e_status_code status;
3324 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3334 * i40e_aq_get_switch_resource_alloc (0x0204)
3335 * @hw: pointer to the hw struct
3336 * @num_entries: pointer to u8 to store the number of resource entries returned
3337 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3338 * to store the resource information for all resource types. Each
3339 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3340 * @count: size, in bytes, of the buffer provided
3341 * @cmd_details: pointer to command details structure or NULL
3343 * Query the resources allocated to a function.
3345 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3347 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3349 struct i40e_asq_cmd_details *cmd_details)
3351 struct i40e_aq_desc desc;
3352 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3353 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3354 enum i40e_status_code status;
3356 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3358 i40e_fill_default_direct_cmd_desc(&desc,
3359 i40e_aqc_opc_get_switch_resource_alloc);
3361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3362 if (length > I40E_AQ_LARGE_BUF)
3363 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3365 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3368 *num_entries = cmd_resp->num_entries;
3374 * i40e_aq_delete_element - Delete switch element
3375 * @hw: pointer to the hw struct
3376 * @seid: the SEID to delete from the switch
3377 * @cmd_details: pointer to command details structure or NULL
3379 * This deletes a switch element from the switch.
3381 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3382 struct i40e_asq_cmd_details *cmd_details)
3384 struct i40e_aq_desc desc;
3385 struct i40e_aqc_switch_seid *cmd =
3386 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3387 enum i40e_status_code status;
3390 return I40E_ERR_PARAM;
3392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3394 cmd->seid = CPU_TO_LE16(seid);
3396 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3402 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3403 * @hw: pointer to the hw struct
3404 * @flags: component flags
3405 * @mac_seid: uplink seid (MAC SEID)
3406 * @vsi_seid: connected vsi seid
3407 * @ret_seid: seid of create pv component
3409 * This instantiates an i40e port virtualizer with specified flags.
3410 * Depending on specified flags the port virtualizer can act as a
3411 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3413 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3414 u16 mac_seid, u16 vsi_seid,
3417 struct i40e_aq_desc desc;
3418 struct i40e_aqc_add_update_pv *cmd =
3419 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3420 struct i40e_aqc_add_update_pv_completion *resp =
3421 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3422 enum i40e_status_code status;
3425 return I40E_ERR_PARAM;
3427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3428 cmd->command_flags = CPU_TO_LE16(flags);
3429 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3430 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3432 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3433 if (!status && ret_seid)
3434 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3440 * i40e_aq_add_tag - Add an S/E-tag
3441 * @hw: pointer to the hw struct
3442 * @direct_to_queue: should s-tag direct flow to a specific queue
3443 * @vsi_seid: VSI SEID to use this tag
3444 * @tag: value of the tag
3445 * @queue_num: queue number, only valid is direct_to_queue is true
3446 * @tags_used: return value, number of tags in use by this PF
3447 * @tags_free: return value, number of unallocated tags
3448 * @cmd_details: pointer to command details structure or NULL
3450 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3451 * the number of tags allocated by the PF, and the number of unallocated
3454 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3455 u16 vsi_seid, u16 tag, u16 queue_num,
3456 u16 *tags_used, u16 *tags_free,
3457 struct i40e_asq_cmd_details *cmd_details)
3459 struct i40e_aq_desc desc;
3460 struct i40e_aqc_add_tag *cmd =
3461 (struct i40e_aqc_add_tag *)&desc.params.raw;
3462 struct i40e_aqc_add_remove_tag_completion *resp =
3463 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3464 enum i40e_status_code status;
3467 return I40E_ERR_PARAM;
3469 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3471 cmd->seid = CPU_TO_LE16(vsi_seid);
3472 cmd->tag = CPU_TO_LE16(tag);
3473 if (direct_to_queue) {
3474 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3475 cmd->queue_number = CPU_TO_LE16(queue_num);
3478 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3481 if (tags_used != NULL)
3482 *tags_used = LE16_TO_CPU(resp->tags_used);
3483 if (tags_free != NULL)
3484 *tags_free = LE16_TO_CPU(resp->tags_free);
3491 * i40e_aq_remove_tag - Remove an S- or E-tag
3492 * @hw: pointer to the hw struct
3493 * @vsi_seid: VSI SEID this tag is associated with
3494 * @tag: value of the S-tag to delete
3495 * @tags_used: return value, number of tags in use by this PF
3496 * @tags_free: return value, number of unallocated tags
3497 * @cmd_details: pointer to command details structure or NULL
3499 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3500 * the number of tags allocated by the PF, and the number of unallocated
3503 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3504 u16 tag, u16 *tags_used, u16 *tags_free,
3505 struct i40e_asq_cmd_details *cmd_details)
3507 struct i40e_aq_desc desc;
3508 struct i40e_aqc_remove_tag *cmd =
3509 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3510 struct i40e_aqc_add_remove_tag_completion *resp =
3511 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3512 enum i40e_status_code status;
3515 return I40E_ERR_PARAM;
3517 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3519 cmd->seid = CPU_TO_LE16(vsi_seid);
3520 cmd->tag = CPU_TO_LE16(tag);
3522 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3525 if (tags_used != NULL)
3526 *tags_used = LE16_TO_CPU(resp->tags_used);
3527 if (tags_free != NULL)
3528 *tags_free = LE16_TO_CPU(resp->tags_free);
3535 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3536 * @hw: pointer to the hw struct
3537 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3538 * @etag: value of E-tag to add
3539 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3540 * @buf: address of indirect buffer
3541 * @tags_used: return value, number of E-tags in use by this port
3542 * @tags_free: return value, number of unallocated M-tags
3543 * @cmd_details: pointer to command details structure or NULL
3545 * This associates a multicast E-tag to a port virtualizer. It will return
3546 * the number of tags allocated by the PF, and the number of unallocated
3549 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3550 * num_tags_in_buf long.
3552 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3553 u16 etag, u8 num_tags_in_buf, void *buf,
3554 u16 *tags_used, u16 *tags_free,
3555 struct i40e_asq_cmd_details *cmd_details)
3557 struct i40e_aq_desc desc;
3558 struct i40e_aqc_add_remove_mcast_etag *cmd =
3559 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3560 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3561 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3562 enum i40e_status_code status;
3563 u16 length = sizeof(u16) * num_tags_in_buf;
3565 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3566 return I40E_ERR_PARAM;
3568 i40e_fill_default_direct_cmd_desc(&desc,
3569 i40e_aqc_opc_add_multicast_etag);
3571 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3572 cmd->etag = CPU_TO_LE16(etag);
3573 cmd->num_unicast_etags = num_tags_in_buf;
3575 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3576 if (length > I40E_AQ_LARGE_BUF)
3577 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3579 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3582 if (tags_used != NULL)
3583 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3584 if (tags_free != NULL)
3585 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3592 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3593 * @hw: pointer to the hw struct
3594 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3595 * @etag: value of the E-tag to remove
3596 * @tags_used: return value, number of tags in use by this port
3597 * @tags_free: return value, number of unallocated tags
3598 * @cmd_details: pointer to command details structure or NULL
3600 * This deletes an E-tag from the port virtualizer. It will return
3601 * the number of tags allocated by the port, and the number of unallocated
3604 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3605 u16 etag, u16 *tags_used, u16 *tags_free,
3606 struct i40e_asq_cmd_details *cmd_details)
3608 struct i40e_aq_desc desc;
3609 struct i40e_aqc_add_remove_mcast_etag *cmd =
3610 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3611 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3612 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3613 enum i40e_status_code status;
3617 return I40E_ERR_PARAM;
3619 i40e_fill_default_direct_cmd_desc(&desc,
3620 i40e_aqc_opc_remove_multicast_etag);
3622 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3623 cmd->etag = CPU_TO_LE16(etag);
3625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3628 if (tags_used != NULL)
3629 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3630 if (tags_free != NULL)
3631 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3638 * i40e_aq_update_tag - Update an S/E-tag
3639 * @hw: pointer to the hw struct
3640 * @vsi_seid: VSI SEID using this S-tag
3641 * @old_tag: old tag value
3642 * @new_tag: new tag value
3643 * @tags_used: return value, number of tags in use by this PF
3644 * @tags_free: return value, number of unallocated tags
3645 * @cmd_details: pointer to command details structure or NULL
3647 * This updates the value of the tag currently attached to this VSI
3648 * in the switch complex. It will return the number of tags allocated
3649 * by the PF, and the number of unallocated tags available.
3651 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3652 u16 old_tag, u16 new_tag, u16 *tags_used,
3654 struct i40e_asq_cmd_details *cmd_details)
3656 struct i40e_aq_desc desc;
3657 struct i40e_aqc_update_tag *cmd =
3658 (struct i40e_aqc_update_tag *)&desc.params.raw;
3659 struct i40e_aqc_update_tag_completion *resp =
3660 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3661 enum i40e_status_code status;
3664 return I40E_ERR_PARAM;
3666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3668 cmd->seid = CPU_TO_LE16(vsi_seid);
3669 cmd->old_tag = CPU_TO_LE16(old_tag);
3670 cmd->new_tag = CPU_TO_LE16(new_tag);
3672 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3675 if (tags_used != NULL)
3676 *tags_used = LE16_TO_CPU(resp->tags_used);
3677 if (tags_free != NULL)
3678 *tags_free = LE16_TO_CPU(resp->tags_free);
3685 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3686 * @hw: pointer to the hw struct
3687 * @tcmap: TC map for request/release any ignore PFC condition
3688 * @request: request or release ignore PFC condition
3689 * @tcmap_ret: return TCs for which PFC is currently ignored
3690 * @cmd_details: pointer to command details structure or NULL
3692 * This sends out request/release to ignore PFC condition for a TC.
3693 * It will return the TCs for which PFC is currently ignored.
3695 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3696 bool request, u8 *tcmap_ret,
3697 struct i40e_asq_cmd_details *cmd_details)
3699 struct i40e_aq_desc desc;
3700 struct i40e_aqc_pfc_ignore *cmd_resp =
3701 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3702 enum i40e_status_code status;
3704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3707 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3709 cmd_resp->tc_bitmap = tcmap;
3711 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3714 if (tcmap_ret != NULL)
3715 *tcmap_ret = cmd_resp->tc_bitmap;
3722 * i40e_aq_dcb_updated - DCB Updated Command
3723 * @hw: pointer to the hw struct
3724 * @cmd_details: pointer to command details structure or NULL
3726 * When LLDP is handled in PF this command is used by the PF
3727 * to notify EMP that a DCB setting is modified.
3728 * When LLDP is handled in EMP this command is used by the PF
3729 * to notify EMP whenever one of the following parameters get
3731 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3732 * - PCIRTT in PRTDCB_GENC.PCIRTT
3733 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3734 * EMP will return when the shared RPB settings have been
3735 * recomputed and modified. The retval field in the descriptor
3736 * will be set to 0 when RPB is modified.
3738 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3739 struct i40e_asq_cmd_details *cmd_details)
3741 struct i40e_aq_desc desc;
3742 enum i40e_status_code status;
3744 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3752 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3753 * @hw: pointer to the hw struct
3754 * @seid: defines the SEID of the switch for which the stats are requested
3755 * @vlan_id: the VLAN ID for which the statistics are requested
3756 * @stat_index: index of the statistics counters block assigned to this VLAN
3757 * @cmd_details: pointer to command details structure or NULL
3759 * XL710 supports 128 smonVlanStats counters.This command is used to
3760 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3763 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3764 u16 vlan_id, u16 *stat_index,
3765 struct i40e_asq_cmd_details *cmd_details)
3767 struct i40e_aq_desc desc;
3768 struct i40e_aqc_add_remove_statistics *cmd_resp =
3769 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3770 enum i40e_status_code status;
3772 if ((seid == 0) || (stat_index == NULL))
3773 return I40E_ERR_PARAM;
3775 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3777 cmd_resp->seid = CPU_TO_LE16(seid);
3778 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3780 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3783 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3789 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3790 * @hw: pointer to the hw struct
3791 * @seid: defines the SEID of the switch for which the stats are requested
3792 * @vlan_id: the VLAN ID for which the statistics are requested
3793 * @stat_index: index of the statistics counters block assigned to this VLAN
3794 * @cmd_details: pointer to command details structure or NULL
3796 * XL710 supports 128 smonVlanStats counters.This command is used to
3797 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3800 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3801 u16 vlan_id, u16 stat_index,
3802 struct i40e_asq_cmd_details *cmd_details)
3804 struct i40e_aq_desc desc;
3805 struct i40e_aqc_add_remove_statistics *cmd =
3806 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3807 enum i40e_status_code status;
3810 return I40E_ERR_PARAM;
3812 i40e_fill_default_direct_cmd_desc(&desc,
3813 i40e_aqc_opc_remove_statistics);
3815 cmd->seid = CPU_TO_LE16(seid);
3816 cmd->vlan = CPU_TO_LE16(vlan_id);
3817 cmd->stat_index = CPU_TO_LE16(stat_index);
3819 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3825 * i40e_aq_set_port_parameters - set physical port parameters.
3826 * @hw: pointer to the hw struct
3827 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3828 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3829 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3830 * @double_vlan: if set double VLAN is enabled
3831 * @cmd_details: pointer to command details structure or NULL
3833 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3834 u16 bad_frame_vsi, bool save_bad_pac,
3835 bool pad_short_pac, bool double_vlan,
3836 struct i40e_asq_cmd_details *cmd_details)
3838 struct i40e_aqc_set_port_parameters *cmd;
3839 enum i40e_status_code status;
3840 struct i40e_aq_desc desc;
3841 u16 command_flags = 0;
3843 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3845 i40e_fill_default_direct_cmd_desc(&desc,
3846 i40e_aqc_opc_set_port_parameters);
3848 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3850 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3852 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3854 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3855 cmd->command_flags = CPU_TO_LE16(command_flags);
3857 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3863 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3864 * @hw: pointer to the hw struct
3865 * @seid: seid for the physical port/switching component/vsi
3866 * @buff: Indirect buffer to hold data parameters and response
3867 * @buff_size: Indirect buffer size
3868 * @opcode: Tx scheduler AQ command opcode
3869 * @cmd_details: pointer to command details structure or NULL
3871 * Generic command handler for Tx scheduler AQ commands
3873 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3874 void *buff, u16 buff_size,
3875 enum i40e_admin_queue_opc opcode,
3876 struct i40e_asq_cmd_details *cmd_details)
3878 struct i40e_aq_desc desc;
3879 struct i40e_aqc_tx_sched_ind *cmd =
3880 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3881 enum i40e_status_code status;
3882 bool cmd_param_flag = false;
3885 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3886 case i40e_aqc_opc_configure_vsi_tc_bw:
3887 case i40e_aqc_opc_enable_switching_comp_ets:
3888 case i40e_aqc_opc_modify_switching_comp_ets:
3889 case i40e_aqc_opc_disable_switching_comp_ets:
3890 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3891 case i40e_aqc_opc_configure_switching_comp_bw_config:
3892 cmd_param_flag = true;
3894 case i40e_aqc_opc_query_vsi_bw_config:
3895 case i40e_aqc_opc_query_vsi_ets_sla_config:
3896 case i40e_aqc_opc_query_switching_comp_ets_config:
3897 case i40e_aqc_opc_query_port_ets_config:
3898 case i40e_aqc_opc_query_switching_comp_bw_config:
3899 cmd_param_flag = false;
3902 return I40E_ERR_PARAM;
3905 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3907 /* Indirect command */
3908 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3910 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3911 if (buff_size > I40E_AQ_LARGE_BUF)
3912 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3914 desc.datalen = CPU_TO_LE16(buff_size);
3916 cmd->vsi_seid = CPU_TO_LE16(seid);
3918 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3924 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3925 * @hw: pointer to the hw struct
3927 * @credit: BW limit credits (0 = disabled)
3928 * @max_credit: Max BW limit credits
3929 * @cmd_details: pointer to command details structure or NULL
3931 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3932 u16 seid, u16 credit, u8 max_credit,
3933 struct i40e_asq_cmd_details *cmd_details)
3935 struct i40e_aq_desc desc;
3936 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3937 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3938 enum i40e_status_code status;
3940 i40e_fill_default_direct_cmd_desc(&desc,
3941 i40e_aqc_opc_configure_vsi_bw_limit);
3943 cmd->vsi_seid = CPU_TO_LE16(seid);
3944 cmd->credit = CPU_TO_LE16(credit);
3945 cmd->max_credit = max_credit;
3947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3953 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3954 * @hw: pointer to the hw struct
3955 * @seid: switching component seid
3956 * @credit: BW limit credits (0 = disabled)
3957 * @max_bw: Max BW limit credits
3958 * @cmd_details: pointer to command details structure or NULL
3960 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3961 u16 seid, u16 credit, u8 max_bw,
3962 struct i40e_asq_cmd_details *cmd_details)
3964 struct i40e_aq_desc desc;
3965 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3966 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3967 enum i40e_status_code status;
3969 i40e_fill_default_direct_cmd_desc(&desc,
3970 i40e_aqc_opc_configure_switching_comp_bw_limit);
3972 cmd->seid = CPU_TO_LE16(seid);
3973 cmd->credit = CPU_TO_LE16(credit);
3974 cmd->max_bw = max_bw;
3976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3982 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3983 * @hw: pointer to the hw struct
3985 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3986 * @cmd_details: pointer to command details structure or NULL
3988 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3990 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3991 struct i40e_asq_cmd_details *cmd_details)
3993 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3994 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3999 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4000 * @hw: pointer to the hw struct
4002 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4003 * @cmd_details: pointer to command details structure or NULL
4005 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4007 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4008 struct i40e_asq_cmd_details *cmd_details)
4010 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4011 i40e_aqc_opc_configure_vsi_tc_bw,
4016 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4017 * @hw: pointer to the hw struct
4018 * @seid: seid of the switching component
4019 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4020 * @cmd_details: pointer to command details structure or NULL
4022 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4023 struct i40e_hw *hw, u16 seid,
4024 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4025 struct i40e_asq_cmd_details *cmd_details)
4027 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4028 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4033 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4034 * @hw: pointer to the hw struct
4035 * @seid: seid of the VSI
4036 * @bw_data: Buffer to hold VSI BW configuration
4037 * @cmd_details: pointer to command details structure or NULL
4039 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4041 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4042 struct i40e_asq_cmd_details *cmd_details)
4044 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4045 i40e_aqc_opc_query_vsi_bw_config,
4050 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4051 * @hw: pointer to the hw struct
4052 * @seid: seid of the VSI
4053 * @bw_data: Buffer to hold VSI BW configuration per TC
4054 * @cmd_details: pointer to command details structure or NULL
4056 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4058 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4059 struct i40e_asq_cmd_details *cmd_details)
4061 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4062 i40e_aqc_opc_query_vsi_ets_sla_config,
4067 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4068 * @hw: pointer to the hw struct
4069 * @seid: seid of the switching component
4070 * @bw_data: Buffer to hold switching component's per TC BW config
4071 * @cmd_details: pointer to command details structure or NULL
4073 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4075 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4076 struct i40e_asq_cmd_details *cmd_details)
4078 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4079 i40e_aqc_opc_query_switching_comp_ets_config,
4084 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4085 * @hw: pointer to the hw struct
4086 * @seid: seid of the VSI or switching component connected to Physical Port
4087 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4088 * @cmd_details: pointer to command details structure or NULL
4090 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4092 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4093 struct i40e_asq_cmd_details *cmd_details)
4095 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4096 i40e_aqc_opc_query_port_ets_config,
4101 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4102 * @hw: pointer to the hw struct
4103 * @seid: seid of the switching component
4104 * @bw_data: Buffer to hold switching component's BW configuration
4105 * @cmd_details: pointer to command details structure or NULL
4107 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4109 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4110 struct i40e_asq_cmd_details *cmd_details)
4112 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4113 i40e_aqc_opc_query_switching_comp_bw_config,
4118 * i40e_validate_filter_settings
4119 * @hw: pointer to the hardware structure
4120 * @settings: Filter control settings
4122 * Check and validate the filter control settings passed.
4123 * The function checks for the valid filter/context sizes being
4124 * passed for FCoE and PE.
4126 * Returns I40E_SUCCESS if the values passed are valid and within
4127 * range else returns an error.
4129 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4130 struct i40e_filter_control_settings *settings)
4132 u32 fcoe_cntx_size, fcoe_filt_size;
4133 u32 pe_cntx_size, pe_filt_size;
4138 /* Validate FCoE settings passed */
4139 switch (settings->fcoe_filt_num) {
4140 case I40E_HASH_FILTER_SIZE_1K:
4141 case I40E_HASH_FILTER_SIZE_2K:
4142 case I40E_HASH_FILTER_SIZE_4K:
4143 case I40E_HASH_FILTER_SIZE_8K:
4144 case I40E_HASH_FILTER_SIZE_16K:
4145 case I40E_HASH_FILTER_SIZE_32K:
4146 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4147 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4150 return I40E_ERR_PARAM;
4153 switch (settings->fcoe_cntx_num) {
4154 case I40E_DMA_CNTX_SIZE_512:
4155 case I40E_DMA_CNTX_SIZE_1K:
4156 case I40E_DMA_CNTX_SIZE_2K:
4157 case I40E_DMA_CNTX_SIZE_4K:
4158 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4159 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4162 return I40E_ERR_PARAM;
4165 /* Validate PE settings passed */
4166 switch (settings->pe_filt_num) {
4167 case I40E_HASH_FILTER_SIZE_1K:
4168 case I40E_HASH_FILTER_SIZE_2K:
4169 case I40E_HASH_FILTER_SIZE_4K:
4170 case I40E_HASH_FILTER_SIZE_8K:
4171 case I40E_HASH_FILTER_SIZE_16K:
4172 case I40E_HASH_FILTER_SIZE_32K:
4173 case I40E_HASH_FILTER_SIZE_64K:
4174 case I40E_HASH_FILTER_SIZE_128K:
4175 case I40E_HASH_FILTER_SIZE_256K:
4176 case I40E_HASH_FILTER_SIZE_512K:
4177 case I40E_HASH_FILTER_SIZE_1M:
4178 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4179 pe_filt_size <<= (u32)settings->pe_filt_num;
4182 return I40E_ERR_PARAM;
4185 switch (settings->pe_cntx_num) {
4186 case I40E_DMA_CNTX_SIZE_512:
4187 case I40E_DMA_CNTX_SIZE_1K:
4188 case I40E_DMA_CNTX_SIZE_2K:
4189 case I40E_DMA_CNTX_SIZE_4K:
4190 case I40E_DMA_CNTX_SIZE_8K:
4191 case I40E_DMA_CNTX_SIZE_16K:
4192 case I40E_DMA_CNTX_SIZE_32K:
4193 case I40E_DMA_CNTX_SIZE_64K:
4194 case I40E_DMA_CNTX_SIZE_128K:
4195 case I40E_DMA_CNTX_SIZE_256K:
4196 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4197 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4200 return I40E_ERR_PARAM;
4203 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4204 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4205 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4206 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4207 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4208 return I40E_ERR_INVALID_SIZE;
4210 return I40E_SUCCESS;
4214 * i40e_set_filter_control
4215 * @hw: pointer to the hardware structure
4216 * @settings: Filter control settings
4218 * Set the Queue Filters for PE/FCoE and enable filters required
4219 * for a single PF. It is expected that these settings are programmed
4220 * at the driver initialization time.
4222 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4223 struct i40e_filter_control_settings *settings)
4225 enum i40e_status_code ret = I40E_SUCCESS;
4226 u32 hash_lut_size = 0;
4230 return I40E_ERR_PARAM;
4232 /* Validate the input settings */
4233 ret = i40e_validate_filter_settings(hw, settings);
4237 /* Read the PF Queue Filter control register */
4238 val = rd32(hw, I40E_PFQF_CTL_0);
4240 /* Program required PE hash buckets for the PF */
4241 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4242 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4243 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4244 /* Program required PE contexts for the PF */
4245 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4246 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4247 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4249 /* Program required FCoE hash buckets for the PF */
4250 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4251 val |= ((u32)settings->fcoe_filt_num <<
4252 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4253 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4254 /* Program required FCoE DDP contexts for the PF */
4255 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4256 val |= ((u32)settings->fcoe_cntx_num <<
4257 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4258 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4260 /* Program Hash LUT size for the PF */
4261 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4262 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4264 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4265 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4267 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4268 if (settings->enable_fdir)
4269 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4270 if (settings->enable_ethtype)
4271 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4272 if (settings->enable_macvlan)
4273 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4275 wr32(hw, I40E_PFQF_CTL_0, val);
4277 return I40E_SUCCESS;
4281 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4282 * @hw: pointer to the hw struct
4283 * @mac_addr: MAC address to use in the filter
4284 * @ethtype: Ethertype to use in the filter
4285 * @flags: Flags that needs to be applied to the filter
4286 * @vsi_seid: seid of the control VSI
4287 * @queue: VSI queue number to send the packet to
4288 * @is_add: Add control packet filter if True else remove
4289 * @stats: Structure to hold information on control filter counts
4290 * @cmd_details: pointer to command details structure or NULL
4292 * This command will Add or Remove control packet filter for a control VSI.
4293 * In return it will update the total number of perfect filter count in
4296 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4297 u8 *mac_addr, u16 ethtype, u16 flags,
4298 u16 vsi_seid, u16 queue, bool is_add,
4299 struct i40e_control_filter_stats *stats,
4300 struct i40e_asq_cmd_details *cmd_details)
4302 struct i40e_aq_desc desc;
4303 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4304 (struct i40e_aqc_add_remove_control_packet_filter *)
4306 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4307 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4309 enum i40e_status_code status;
4312 return I40E_ERR_PARAM;
4315 i40e_fill_default_direct_cmd_desc(&desc,
4316 i40e_aqc_opc_add_control_packet_filter);
4317 cmd->queue = CPU_TO_LE16(queue);
4319 i40e_fill_default_direct_cmd_desc(&desc,
4320 i40e_aqc_opc_remove_control_packet_filter);
4324 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4325 I40E_NONDMA_TO_NONDMA);
4327 cmd->etype = CPU_TO_LE16(ethtype);
4328 cmd->flags = CPU_TO_LE16(flags);
4329 cmd->seid = CPU_TO_LE16(vsi_seid);
4331 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4333 if (!status && stats) {
4334 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4335 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4336 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4337 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4344 * i40e_aq_add_cloud_filters
4345 * @hw: pointer to the hardware structure
4346 * @seid: VSI seid to add cloud filters from
4347 * @filters: Buffer which contains the filters to be added
4348 * @filter_count: number of filters contained in the buffer
4350 * Set the cloud filters for a given VSI. The contents of the
4351 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4352 * in by the caller of the function.
4355 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4357 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4360 struct i40e_aq_desc desc;
4361 struct i40e_aqc_add_remove_cloud_filters *cmd =
4362 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4364 enum i40e_status_code status;
4366 i40e_fill_default_direct_cmd_desc(&desc,
4367 i40e_aqc_opc_add_cloud_filters);
4369 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4371 desc.datalen = CPU_TO_LE16(buff_len);
4372 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4373 cmd->num_filters = filter_count;
4374 cmd->seid = CPU_TO_LE16(seid);
4376 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4382 * i40e_aq_remove_cloud_filters
4383 * @hw: pointer to the hardware structure
4384 * @seid: VSI seid to remove cloud filters from
4385 * @filters: Buffer which contains the filters to be removed
4386 * @filter_count: number of filters contained in the buffer
4388 * Remove the cloud filters for a given VSI. The contents of the
4389 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4390 * in by the caller of the function.
4393 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4395 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4398 struct i40e_aq_desc desc;
4399 struct i40e_aqc_add_remove_cloud_filters *cmd =
4400 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4401 enum i40e_status_code status;
4404 i40e_fill_default_direct_cmd_desc(&desc,
4405 i40e_aqc_opc_remove_cloud_filters);
4407 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4409 desc.datalen = CPU_TO_LE16(buff_len);
4410 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4411 cmd->num_filters = filter_count;
4412 cmd->seid = CPU_TO_LE16(seid);
4414 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4420 * i40e_aq_alternate_write
4421 * @hw: pointer to the hardware structure
4422 * @reg_addr0: address of first dword to be read
4423 * @reg_val0: value to be written under 'reg_addr0'
4424 * @reg_addr1: address of second dword to be read
4425 * @reg_val1: value to be written under 'reg_addr1'
4427 * Write one or two dwords to alternate structure. Fields are indicated
4428 * by 'reg_addr0' and 'reg_addr1' register numbers.
4431 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4432 u32 reg_addr0, u32 reg_val0,
4433 u32 reg_addr1, u32 reg_val1)
4435 struct i40e_aq_desc desc;
4436 struct i40e_aqc_alternate_write *cmd_resp =
4437 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4438 enum i40e_status_code status;
4440 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4441 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4442 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4443 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4444 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4446 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4452 * i40e_aq_alternate_write_indirect
4453 * @hw: pointer to the hardware structure
4454 * @addr: address of a first register to be modified
4455 * @dw_count: number of alternate structure fields to write
4456 * @buffer: pointer to the command buffer
4458 * Write 'dw_count' dwords from 'buffer' to alternate structure
4459 * starting at 'addr'.
4462 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4463 u32 addr, u32 dw_count, void *buffer)
4465 struct i40e_aq_desc desc;
4466 struct i40e_aqc_alternate_ind_write *cmd_resp =
4467 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4468 enum i40e_status_code status;
4471 return I40E_ERR_PARAM;
4473 /* Indirect command */
4474 i40e_fill_default_direct_cmd_desc(&desc,
4475 i40e_aqc_opc_alternate_write_indirect);
4477 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4478 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4479 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4482 cmd_resp->address = CPU_TO_LE32(addr);
4483 cmd_resp->length = CPU_TO_LE32(dw_count);
4484 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4485 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4487 status = i40e_asq_send_command(hw, &desc, buffer,
4488 I40E_LO_DWORD(4*dw_count), NULL);
4494 * i40e_aq_alternate_read
4495 * @hw: pointer to the hardware structure
4496 * @reg_addr0: address of first dword to be read
4497 * @reg_val0: pointer for data read from 'reg_addr0'
4498 * @reg_addr1: address of second dword to be read
4499 * @reg_val1: pointer for data read from 'reg_addr1'
4501 * Read one or two dwords from alternate structure. Fields are indicated
4502 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4503 * is not passed then only register at 'reg_addr0' is read.
4506 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4507 u32 reg_addr0, u32 *reg_val0,
4508 u32 reg_addr1, u32 *reg_val1)
4510 struct i40e_aq_desc desc;
4511 struct i40e_aqc_alternate_write *cmd_resp =
4512 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4513 enum i40e_status_code status;
4515 if (reg_val0 == NULL)
4516 return I40E_ERR_PARAM;
4518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4519 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4520 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4522 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4524 if (status == I40E_SUCCESS) {
4525 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4527 if (reg_val1 != NULL)
4528 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4535 * i40e_aq_alternate_read_indirect
4536 * @hw: pointer to the hardware structure
4537 * @addr: address of the alternate structure field
4538 * @dw_count: number of alternate structure fields to read
4539 * @buffer: pointer to the command buffer
4541 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4542 * place them in 'buffer'. The buffer should be allocated by caller.
4545 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4546 u32 addr, u32 dw_count, void *buffer)
4548 struct i40e_aq_desc desc;
4549 struct i40e_aqc_alternate_ind_write *cmd_resp =
4550 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4551 enum i40e_status_code status;
4554 return I40E_ERR_PARAM;
4556 /* Indirect command */
4557 i40e_fill_default_direct_cmd_desc(&desc,
4558 i40e_aqc_opc_alternate_read_indirect);
4560 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4561 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4562 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4563 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4565 cmd_resp->address = CPU_TO_LE32(addr);
4566 cmd_resp->length = CPU_TO_LE32(dw_count);
4567 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4568 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4570 status = i40e_asq_send_command(hw, &desc, buffer,
4571 I40E_LO_DWORD(4*dw_count), NULL);
4577 * i40e_aq_alternate_clear
4578 * @hw: pointer to the HW structure.
4580 * Clear the alternate structures of the port from which the function
4584 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4586 struct i40e_aq_desc desc;
4587 enum i40e_status_code status;
4589 i40e_fill_default_direct_cmd_desc(&desc,
4590 i40e_aqc_opc_alternate_clear_port);
4592 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4598 * i40e_aq_alternate_write_done
4599 * @hw: pointer to the HW structure.
4600 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4601 * @reset_needed: indicates the SW should trigger GLOBAL reset
4603 * Indicates to the FW that alternate structures have been changed.
4606 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4607 u8 bios_mode, bool *reset_needed)
4609 struct i40e_aq_desc desc;
4610 struct i40e_aqc_alternate_write_done *cmd =
4611 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4612 enum i40e_status_code status;
4614 if (reset_needed == NULL)
4615 return I40E_ERR_PARAM;
4617 i40e_fill_default_direct_cmd_desc(&desc,
4618 i40e_aqc_opc_alternate_write_done);
4620 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4622 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4624 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4625 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4631 * i40e_aq_set_oem_mode
4632 * @hw: pointer to the HW structure.
4633 * @oem_mode: the OEM mode to be used
4635 * Sets the device to a specific operating mode. Currently the only supported
4636 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4639 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4642 struct i40e_aq_desc desc;
4643 struct i40e_aqc_alternate_write_done *cmd =
4644 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4645 enum i40e_status_code status;
4647 i40e_fill_default_direct_cmd_desc(&desc,
4648 i40e_aqc_opc_alternate_set_mode);
4650 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4652 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4658 * i40e_aq_resume_port_tx
4659 * @hw: pointer to the hardware structure
4660 * @cmd_details: pointer to command details structure or NULL
4662 * Resume port's Tx traffic
4664 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4665 struct i40e_asq_cmd_details *cmd_details)
4667 struct i40e_aq_desc desc;
4668 enum i40e_status_code status;
4670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4672 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4678 * i40e_set_pci_config_data - store PCI bus info
4679 * @hw: pointer to hardware structure
4680 * @link_status: the link status word from PCI config space
4682 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4684 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4686 hw->bus.type = i40e_bus_type_pci_express;
4688 switch (link_status & I40E_PCI_LINK_WIDTH) {
4689 case I40E_PCI_LINK_WIDTH_1:
4690 hw->bus.width = i40e_bus_width_pcie_x1;
4692 case I40E_PCI_LINK_WIDTH_2:
4693 hw->bus.width = i40e_bus_width_pcie_x2;
4695 case I40E_PCI_LINK_WIDTH_4:
4696 hw->bus.width = i40e_bus_width_pcie_x4;
4698 case I40E_PCI_LINK_WIDTH_8:
4699 hw->bus.width = i40e_bus_width_pcie_x8;
4702 hw->bus.width = i40e_bus_width_unknown;
4706 switch (link_status & I40E_PCI_LINK_SPEED) {
4707 case I40E_PCI_LINK_SPEED_2500:
4708 hw->bus.speed = i40e_bus_speed_2500;
4710 case I40E_PCI_LINK_SPEED_5000:
4711 hw->bus.speed = i40e_bus_speed_5000;
4713 case I40E_PCI_LINK_SPEED_8000:
4714 hw->bus.speed = i40e_bus_speed_8000;
4717 hw->bus.speed = i40e_bus_speed_unknown;
4723 * i40e_read_bw_from_alt_ram
4724 * @hw: pointer to the hardware structure
4725 * @max_bw: pointer for max_bw read
4726 * @min_bw: pointer for min_bw read
4727 * @min_valid: pointer for bool that is true if min_bw is a valid value
4728 * @max_valid: pointer for bool that is true if max_bw is a valid value
4730 * Read bw from the alternate ram for the given pf
4732 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4733 u32 *max_bw, u32 *min_bw,
4734 bool *min_valid, bool *max_valid)
4736 enum i40e_status_code status;
4737 u32 max_bw_addr, min_bw_addr;
4739 /* Calculate the address of the min/max bw registers */
4740 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4741 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4742 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4743 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4744 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4745 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4747 /* Read the bandwidths from alt ram */
4748 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4749 min_bw_addr, min_bw);
4751 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4756 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4765 * i40e_aq_configure_partition_bw
4766 * @hw: pointer to the hardware structure
4767 * @bw_data: Buffer holding valid pfs and bw limits
4768 * @cmd_details: pointer to command details
4770 * Configure partitions guaranteed/max bw
4772 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4773 struct i40e_aqc_configure_partition_bw_data *bw_data,
4774 struct i40e_asq_cmd_details *cmd_details)
4776 enum i40e_status_code status;
4777 struct i40e_aq_desc desc;
4778 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4780 i40e_fill_default_direct_cmd_desc(&desc,
4781 i40e_aqc_opc_configure_partition_bw);
4783 /* Indirect command */
4784 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4785 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4787 if (bwd_size > I40E_AQ_LARGE_BUF)
4788 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4790 desc.datalen = CPU_TO_LE16(bwd_size);
4792 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4796 #endif /* PF_DRIVER */
4800 * i40e_aq_send_msg_to_pf
4801 * @hw: pointer to the hardware structure
4802 * @v_opcode: opcodes for VF-PF communication
4803 * @v_retval: return error code
4804 * @msg: pointer to the msg buffer
4805 * @msglen: msg length
4806 * @cmd_details: pointer to command details
4808 * Send message to PF driver using admin queue. By default, this message
4809 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4810 * completion before returning.
4812 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4813 enum i40e_virtchnl_ops v_opcode,
4814 enum i40e_status_code v_retval,
4815 u8 *msg, u16 msglen,
4816 struct i40e_asq_cmd_details *cmd_details)
4818 struct i40e_aq_desc desc;
4819 struct i40e_asq_cmd_details details;
4820 enum i40e_status_code status;
4822 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4823 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4824 desc.cookie_high = CPU_TO_LE32(v_opcode);
4825 desc.cookie_low = CPU_TO_LE32(v_retval);
4827 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4828 | I40E_AQ_FLAG_RD));
4829 if (msglen > I40E_AQ_LARGE_BUF)
4830 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4831 desc.datalen = CPU_TO_LE16(msglen);
4834 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4835 details.async = true;
4836 cmd_details = &details;
4838 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4839 msglen, cmd_details);
4844 * i40e_vf_parse_hw_config
4845 * @hw: pointer to the hardware structure
4846 * @msg: pointer to the virtual channel VF resource structure
4848 * Given a VF resource message from the PF, populate the hw struct
4849 * with appropriate information.
4851 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4852 struct i40e_virtchnl_vf_resource *msg)
4854 struct i40e_virtchnl_vsi_resource *vsi_res;
4857 vsi_res = &msg->vsi_res[0];
4859 hw->dev_caps.num_vsis = msg->num_vsis;
4860 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4861 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4862 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4863 hw->dev_caps.dcb = msg->vf_offload_flags &
4864 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4865 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4866 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4867 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4868 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4869 for (i = 0; i < msg->num_vsis; i++) {
4870 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4871 i40e_memcpy(hw->mac.perm_addr,
4872 vsi_res->default_mac_addr,
4873 I40E_ETH_LENGTH_OF_ADDRESS,
4874 I40E_NONDMA_TO_NONDMA);
4875 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4876 I40E_ETH_LENGTH_OF_ADDRESS,
4877 I40E_NONDMA_TO_NONDMA);
4885 * @hw: pointer to the hardware structure
4887 * Send a VF_RESET message to the PF. Does not wait for response from PF
4888 * as none will be forthcoming. Immediately after calling this function,
4889 * the admin queue should be shut down and (optionally) reinitialized.
4891 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4893 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4894 I40E_SUCCESS, NULL, 0, NULL);
4896 #endif /* VF_DRIVER */