1 /*******************************************************************************
3 Copyright (c) 2013 - 2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 hw->mac.type = I40E_MAC_XL710;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
87 * @hw: debug mask related to admin queue
89 * @desc: pointer to admin queue descriptor
90 * @buffer: pointer to command buffer
92 * Dumps debug log about adminq command with descriptor contents.
94 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
98 u8 *aq_buffer = (u8 *)buffer;
102 if ((!(mask & hw->debug_mask)) || (desc == NULL))
106 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
107 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
109 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
110 aq_desc->cookie_high, aq_desc->cookie_low);
111 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
112 aq_desc->params.internal.param0,
113 aq_desc->params.internal.param1);
114 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
115 aq_desc->params.external.addr_high,
116 aq_desc->params.external.addr_low);
118 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
119 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
120 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
121 for (i = 0; i < LE16_TO_CPU(aq_desc->datalen); i++) {
122 data[((i % 16) / 4)] |=
123 ((u32)aq_buffer[i]) << (8 * (i % 4));
124 if ((i % 16) == 15) {
126 "\t0x%04X %08X %08X %08X %08X\n",
127 i - 15, data[0], data[1], data[2],
129 i40e_memset(data, 0, sizeof(data),
134 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
135 i - (i % 16), data[0], data[1], data[2],
141 * i40e_check_asq_alive
142 * @hw: pointer to the hw struct
144 * Returns true if Queue is enabled else false.
146 bool i40e_check_asq_alive(struct i40e_hw *hw)
149 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
155 * i40e_aq_queue_shutdown
156 * @hw: pointer to the hw struct
157 * @unloading: is the driver unloading itself
159 * Tell the Firmware that we're shutting down the AdminQ and whether
160 * or not the driver is unloading as well.
162 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
165 struct i40e_aq_desc desc;
166 struct i40e_aqc_queue_shutdown *cmd =
167 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
168 enum i40e_status_code status;
170 i40e_fill_default_direct_cmd_desc(&desc,
171 i40e_aqc_opc_queue_shutdown);
174 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
175 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
180 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
181 * hardware to a bit-field that can be used by SW to more easily determine the
184 * Macros are used to shorten the table lines and make this table human
187 * We store the PTYPE in the top byte of the bit field - this is just so that
188 * we can check that the table doesn't have a row missing, as the index into
189 * the table should be the PTYPE.
193 * IF NOT i40e_ptype_lookup[ptype].known
196 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
197 * Use the rest of the fields to look at the tunnels, inner protocols, etc
199 * Use the enum i40e_rx_l2_ptype to decode the packet type
203 /* macro to make the table lines short */
204 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
207 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
208 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
209 I40E_RX_PTYPE_##OUTER_FRAG, \
210 I40E_RX_PTYPE_TUNNEL_##T, \
211 I40E_RX_PTYPE_TUNNEL_END_##TE, \
212 I40E_RX_PTYPE_##TEF, \
213 I40E_RX_PTYPE_INNER_PROT_##I, \
214 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
216 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
217 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
219 /* shorter macros makes the table fit but are terse */
220 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
221 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
222 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
224 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
225 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
226 /* L2 Packet types */
227 I40E_PTT_UNUSED_ENTRY(0),
228 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
229 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
230 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
231 I40E_PTT_UNUSED_ENTRY(4),
232 I40E_PTT_UNUSED_ENTRY(5),
233 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
235 I40E_PTT_UNUSED_ENTRY(8),
236 I40E_PTT_UNUSED_ENTRY(9),
237 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
239 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 /* Non Tunneled IPv4 */
251 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
254 I40E_PTT_UNUSED_ENTRY(25),
255 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
256 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
257 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
260 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
261 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
262 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(32),
264 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
265 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
266 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
269 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
270 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
271 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(39),
273 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
274 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
275 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
277 /* IPv4 --> GRE/NAT */
278 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
280 /* IPv4 --> GRE/NAT --> IPv4 */
281 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
282 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
283 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
284 I40E_PTT_UNUSED_ENTRY(47),
285 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
286 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
287 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
289 /* IPv4 --> GRE/NAT --> IPv6 */
290 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
291 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
292 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(54),
294 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
295 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
296 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> MAC */
299 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
301 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
302 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
303 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
304 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
305 I40E_PTT_UNUSED_ENTRY(62),
306 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
307 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
308 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
310 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
311 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
312 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
313 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(69),
315 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
316 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
317 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT --> MAC/VLAN */
320 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
322 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
323 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
324 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
325 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
326 I40E_PTT_UNUSED_ENTRY(77),
327 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
328 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
329 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
331 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
332 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
333 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
334 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(84),
336 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
337 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
338 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
340 /* Non Tunneled IPv6 */
341 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
342 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
343 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
344 I40E_PTT_UNUSED_ENTRY(91),
345 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
346 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
347 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
350 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
351 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
352 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
353 I40E_PTT_UNUSED_ENTRY(98),
354 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
355 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
356 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
359 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
360 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
361 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(105),
363 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
364 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
365 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
367 /* IPv6 --> GRE/NAT */
368 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
370 /* IPv6 --> GRE/NAT -> IPv4 */
371 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
372 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
373 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
374 I40E_PTT_UNUSED_ENTRY(113),
375 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
376 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
377 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
379 /* IPv6 --> GRE/NAT -> IPv6 */
380 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
381 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
382 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(120),
384 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
385 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
386 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> MAC */
389 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
391 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
392 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
393 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
394 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
395 I40E_PTT_UNUSED_ENTRY(128),
396 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
397 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
398 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
401 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
402 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
403 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(135),
405 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
406 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
407 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC/VLAN */
410 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
413 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
414 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
415 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
416 I40E_PTT_UNUSED_ENTRY(143),
417 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
418 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
419 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
422 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
423 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
424 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(150),
426 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
427 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
428 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
431 I40E_PTT_UNUSED_ENTRY(154),
432 I40E_PTT_UNUSED_ENTRY(155),
433 I40E_PTT_UNUSED_ENTRY(156),
434 I40E_PTT_UNUSED_ENTRY(157),
435 I40E_PTT_UNUSED_ENTRY(158),
436 I40E_PTT_UNUSED_ENTRY(159),
438 I40E_PTT_UNUSED_ENTRY(160),
439 I40E_PTT_UNUSED_ENTRY(161),
440 I40E_PTT_UNUSED_ENTRY(162),
441 I40E_PTT_UNUSED_ENTRY(163),
442 I40E_PTT_UNUSED_ENTRY(164),
443 I40E_PTT_UNUSED_ENTRY(165),
444 I40E_PTT_UNUSED_ENTRY(166),
445 I40E_PTT_UNUSED_ENTRY(167),
446 I40E_PTT_UNUSED_ENTRY(168),
447 I40E_PTT_UNUSED_ENTRY(169),
449 I40E_PTT_UNUSED_ENTRY(170),
450 I40E_PTT_UNUSED_ENTRY(171),
451 I40E_PTT_UNUSED_ENTRY(172),
452 I40E_PTT_UNUSED_ENTRY(173),
453 I40E_PTT_UNUSED_ENTRY(174),
454 I40E_PTT_UNUSED_ENTRY(175),
455 I40E_PTT_UNUSED_ENTRY(176),
456 I40E_PTT_UNUSED_ENTRY(177),
457 I40E_PTT_UNUSED_ENTRY(178),
458 I40E_PTT_UNUSED_ENTRY(179),
460 I40E_PTT_UNUSED_ENTRY(180),
461 I40E_PTT_UNUSED_ENTRY(181),
462 I40E_PTT_UNUSED_ENTRY(182),
463 I40E_PTT_UNUSED_ENTRY(183),
464 I40E_PTT_UNUSED_ENTRY(184),
465 I40E_PTT_UNUSED_ENTRY(185),
466 I40E_PTT_UNUSED_ENTRY(186),
467 I40E_PTT_UNUSED_ENTRY(187),
468 I40E_PTT_UNUSED_ENTRY(188),
469 I40E_PTT_UNUSED_ENTRY(189),
471 I40E_PTT_UNUSED_ENTRY(190),
472 I40E_PTT_UNUSED_ENTRY(191),
473 I40E_PTT_UNUSED_ENTRY(192),
474 I40E_PTT_UNUSED_ENTRY(193),
475 I40E_PTT_UNUSED_ENTRY(194),
476 I40E_PTT_UNUSED_ENTRY(195),
477 I40E_PTT_UNUSED_ENTRY(196),
478 I40E_PTT_UNUSED_ENTRY(197),
479 I40E_PTT_UNUSED_ENTRY(198),
480 I40E_PTT_UNUSED_ENTRY(199),
482 I40E_PTT_UNUSED_ENTRY(200),
483 I40E_PTT_UNUSED_ENTRY(201),
484 I40E_PTT_UNUSED_ENTRY(202),
485 I40E_PTT_UNUSED_ENTRY(203),
486 I40E_PTT_UNUSED_ENTRY(204),
487 I40E_PTT_UNUSED_ENTRY(205),
488 I40E_PTT_UNUSED_ENTRY(206),
489 I40E_PTT_UNUSED_ENTRY(207),
490 I40E_PTT_UNUSED_ENTRY(208),
491 I40E_PTT_UNUSED_ENTRY(209),
493 I40E_PTT_UNUSED_ENTRY(210),
494 I40E_PTT_UNUSED_ENTRY(211),
495 I40E_PTT_UNUSED_ENTRY(212),
496 I40E_PTT_UNUSED_ENTRY(213),
497 I40E_PTT_UNUSED_ENTRY(214),
498 I40E_PTT_UNUSED_ENTRY(215),
499 I40E_PTT_UNUSED_ENTRY(216),
500 I40E_PTT_UNUSED_ENTRY(217),
501 I40E_PTT_UNUSED_ENTRY(218),
502 I40E_PTT_UNUSED_ENTRY(219),
504 I40E_PTT_UNUSED_ENTRY(220),
505 I40E_PTT_UNUSED_ENTRY(221),
506 I40E_PTT_UNUSED_ENTRY(222),
507 I40E_PTT_UNUSED_ENTRY(223),
508 I40E_PTT_UNUSED_ENTRY(224),
509 I40E_PTT_UNUSED_ENTRY(225),
510 I40E_PTT_UNUSED_ENTRY(226),
511 I40E_PTT_UNUSED_ENTRY(227),
512 I40E_PTT_UNUSED_ENTRY(228),
513 I40E_PTT_UNUSED_ENTRY(229),
515 I40E_PTT_UNUSED_ENTRY(230),
516 I40E_PTT_UNUSED_ENTRY(231),
517 I40E_PTT_UNUSED_ENTRY(232),
518 I40E_PTT_UNUSED_ENTRY(233),
519 I40E_PTT_UNUSED_ENTRY(234),
520 I40E_PTT_UNUSED_ENTRY(235),
521 I40E_PTT_UNUSED_ENTRY(236),
522 I40E_PTT_UNUSED_ENTRY(237),
523 I40E_PTT_UNUSED_ENTRY(238),
524 I40E_PTT_UNUSED_ENTRY(239),
526 I40E_PTT_UNUSED_ENTRY(240),
527 I40E_PTT_UNUSED_ENTRY(241),
528 I40E_PTT_UNUSED_ENTRY(242),
529 I40E_PTT_UNUSED_ENTRY(243),
530 I40E_PTT_UNUSED_ENTRY(244),
531 I40E_PTT_UNUSED_ENTRY(245),
532 I40E_PTT_UNUSED_ENTRY(246),
533 I40E_PTT_UNUSED_ENTRY(247),
534 I40E_PTT_UNUSED_ENTRY(248),
535 I40E_PTT_UNUSED_ENTRY(249),
537 I40E_PTT_UNUSED_ENTRY(250),
538 I40E_PTT_UNUSED_ENTRY(251),
539 I40E_PTT_UNUSED_ENTRY(252),
540 I40E_PTT_UNUSED_ENTRY(253),
541 I40E_PTT_UNUSED_ENTRY(254),
542 I40E_PTT_UNUSED_ENTRY(255)
548 * i40e_init_shared_code - Initialize the shared code
549 * @hw: pointer to hardware structure
551 * This assigns the MAC type and PHY code and inits the NVM.
552 * Does not touch the hardware. This function must be called prior to any
553 * other function in the shared code. The i40e_hw structure should be
554 * memset to 0 prior to calling this function. The following fields in
555 * hw structure should be filled in prior to calling this function:
556 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
557 * subsystem_vendor_id, and revision_id
559 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
561 enum i40e_status_code status = I40E_SUCCESS;
564 DEBUGFUNC("i40e_init_shared_code");
566 i40e_set_mac_type(hw);
568 switch (hw->mac.type) {
572 return I40E_ERR_DEVICE_NOT_SUPPORTED;
576 hw->phy.get_link_info = true;
578 /* Determine port number */
579 reg = rd32(hw, I40E_PFGEN_PORTNUM);
580 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
581 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
584 /* Determine the PF number based on the PCI fn */
585 reg = rd32(hw, I40E_GLPCI_CAPSUP);
586 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
587 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
589 hw->pf_id = (u8)hw->bus.func;
591 status = i40e_init_nvm(hw);
596 * i40e_aq_mac_address_read - Retrieve the MAC addresses
597 * @hw: pointer to the hw struct
598 * @flags: a return indicator of what addresses were added to the addr store
599 * @addrs: the requestor's mac addr store
600 * @cmd_details: pointer to command details structure or NULL
602 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
604 struct i40e_aqc_mac_address_read_data *addrs,
605 struct i40e_asq_cmd_details *cmd_details)
607 struct i40e_aq_desc desc;
608 struct i40e_aqc_mac_address_read *cmd_data =
609 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
610 enum i40e_status_code status;
612 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
613 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
615 status = i40e_asq_send_command(hw, &desc, addrs,
616 sizeof(*addrs), cmd_details);
617 *flags = LE16_TO_CPU(cmd_data->command_flags);
623 * i40e_aq_mac_address_write - Change the MAC addresses
624 * @hw: pointer to the hw struct
625 * @flags: indicates which MAC to be written
626 * @mac_addr: address to write
627 * @cmd_details: pointer to command details structure or NULL
629 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
630 u16 flags, u8 *mac_addr,
631 struct i40e_asq_cmd_details *cmd_details)
633 struct i40e_aq_desc desc;
634 struct i40e_aqc_mac_address_write *cmd_data =
635 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
636 enum i40e_status_code status;
638 i40e_fill_default_direct_cmd_desc(&desc,
639 i40e_aqc_opc_mac_address_write);
640 cmd_data->command_flags = CPU_TO_LE16(flags);
641 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
642 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
643 ((u32)mac_addr[3] << 16) |
644 ((u32)mac_addr[4] << 8) |
647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
653 * i40e_get_mac_addr - get MAC address
654 * @hw: pointer to the HW structure
655 * @mac_addr: pointer to MAC address
657 * Reads the adapter's MAC address from register
659 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
661 struct i40e_aqc_mac_address_read_data addrs;
662 enum i40e_status_code status;
665 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
667 if (flags & I40E_AQC_LAN_ADDR_VALID)
668 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
674 * i40e_get_port_mac_addr - get Port MAC address
675 * @hw: pointer to the HW structure
676 * @mac_addr: pointer to Port MAC address
678 * Reads the adapter's Port MAC address
680 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
682 struct i40e_aqc_mac_address_read_data addrs;
683 enum i40e_status_code status;
686 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
690 if (flags & I40E_AQC_PORT_ADDR_VALID)
691 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
693 status = I40E_ERR_INVALID_MAC_ADDR;
699 * i40e_pre_tx_queue_cfg - pre tx queue configure
700 * @hw: pointer to the HW structure
701 * @queue: target pf queue index
702 * @enable: state change request
704 * Handles hw requirement to indicate intention to enable
705 * or disable target queue.
707 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
709 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
713 if (abs_queue_idx >= 128) {
714 reg_block = abs_queue_idx / 128;
715 abs_queue_idx %= 128;
718 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
719 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
720 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
723 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
725 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
727 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
731 * i40e_validate_mac_addr - Validate unicast MAC address
732 * @mac_addr: pointer to MAC address
734 * Tests a MAC address to ensure it is a valid Individual Address
736 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
738 enum i40e_status_code status = I40E_SUCCESS;
740 DEBUGFUNC("i40e_validate_mac_addr");
742 /* Broadcast addresses ARE multicast addresses
743 * Make sure it is not a multicast address
744 * Reject the zero address
746 if (I40E_IS_MULTICAST(mac_addr) ||
747 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
748 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
749 status = I40E_ERR_INVALID_MAC_ADDR;
755 * i40e_get_media_type - Gets media type
756 * @hw: pointer to the hardware structure
758 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
760 enum i40e_media_type media;
762 switch (hw->phy.link_info.phy_type) {
763 case I40E_PHY_TYPE_10GBASE_SR:
764 case I40E_PHY_TYPE_10GBASE_LR:
765 case I40E_PHY_TYPE_40GBASE_SR4:
766 case I40E_PHY_TYPE_40GBASE_LR4:
767 media = I40E_MEDIA_TYPE_FIBER;
769 case I40E_PHY_TYPE_100BASE_TX:
770 case I40E_PHY_TYPE_1000BASE_T:
771 case I40E_PHY_TYPE_10GBASE_T:
772 media = I40E_MEDIA_TYPE_BASET;
774 case I40E_PHY_TYPE_10GBASE_CR1_CU:
775 case I40E_PHY_TYPE_40GBASE_CR4_CU:
776 case I40E_PHY_TYPE_10GBASE_CR1:
777 case I40E_PHY_TYPE_40GBASE_CR4:
778 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
779 media = I40E_MEDIA_TYPE_DA;
781 case I40E_PHY_TYPE_1000BASE_KX:
782 case I40E_PHY_TYPE_10GBASE_KX4:
783 case I40E_PHY_TYPE_10GBASE_KR:
784 case I40E_PHY_TYPE_40GBASE_KR4:
785 media = I40E_MEDIA_TYPE_BACKPLANE;
787 case I40E_PHY_TYPE_SGMII:
788 case I40E_PHY_TYPE_XAUI:
789 case I40E_PHY_TYPE_XFI:
790 case I40E_PHY_TYPE_XLAUI:
791 case I40E_PHY_TYPE_XLPPI:
793 media = I40E_MEDIA_TYPE_UNKNOWN;
800 #define I40E_PF_RESET_WAIT_COUNT 100
802 * i40e_pf_reset - Reset the PF
803 * @hw: pointer to the hardware structure
805 * Assuming someone else has triggered a global reset,
806 * assure the global reset is complete and then reset the PF
808 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
815 /* Poll for Global Reset steady state in case of recent GRST.
816 * The grst delay value is in 100ms units, and we'll wait a
817 * couple counts longer to be sure we don't just miss the end.
819 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
820 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
821 for (cnt = 0; cnt < grst_del + 2; cnt++) {
822 reg = rd32(hw, I40E_GLGEN_RSTAT);
823 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
825 i40e_msec_delay(100);
827 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
828 DEBUGOUT("Global reset polling failed to complete.\n");
829 return I40E_ERR_RESET_FAILED;
832 /* Now Wait for the FW to be ready */
833 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
834 reg = rd32(hw, I40E_GLNVM_ULD);
835 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
836 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
837 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
838 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
839 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
844 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
845 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
846 DEBUGOUT("wait for FW Reset complete timedout\n");
847 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
848 return I40E_ERR_RESET_FAILED;
851 /* If there was a Global Reset in progress when we got here,
852 * we don't need to do the PF Reset
855 reg = rd32(hw, I40E_PFGEN_CTRL);
856 wr32(hw, I40E_PFGEN_CTRL,
857 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
858 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
859 reg = rd32(hw, I40E_PFGEN_CTRL);
860 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
864 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
865 DEBUGOUT("PF reset polling failed to complete.\n");
866 return I40E_ERR_RESET_FAILED;
870 i40e_clear_pxe_mode(hw);
876 * i40e_clear_hw - clear out any left over hw state
877 * @hw: pointer to the hw struct
879 * Clear queues and interrupts, typically called at init time,
880 * but after the capabilities have been found so we know how many
881 * queues and msix vectors have been allocated.
883 void i40e_clear_hw(struct i40e_hw *hw)
885 u32 num_queues, base_queue;
893 /* get number of interrupts, queues, and vfs */
894 val = rd32(hw, I40E_GLPCI_CNF2);
895 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
896 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
897 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
898 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
900 val = rd32(hw, I40E_PFLAN_QALLOC);
901 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
902 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
903 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
904 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
905 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
906 num_queues = (j - base_queue) + 1;
910 val = rd32(hw, I40E_PF_VT_PFALLOC);
911 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
912 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
913 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
914 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
915 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
916 num_vfs = (j - i) + 1;
920 /* stop all the interrupts */
921 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
922 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
923 for (i = 0; i < num_pf_int - 2; i++)
924 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
926 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
927 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
928 wr32(hw, I40E_PFINT_LNKLST0, val);
929 for (i = 0; i < num_pf_int - 2; i++)
930 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
931 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
932 for (i = 0; i < num_vfs; i++)
933 wr32(hw, I40E_VPINT_LNKLST0(i), val);
934 for (i = 0; i < num_vf_int - 2; i++)
935 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
937 /* warn the HW of the coming Tx disables */
938 for (i = 0; i < num_queues; i++) {
939 u32 abs_queue_idx = base_queue + i;
942 if (abs_queue_idx >= 128) {
943 reg_block = abs_queue_idx / 128;
944 abs_queue_idx %= 128;
947 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
948 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
949 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
950 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
952 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
954 i40e_usec_delay(400);
956 /* stop all the queues */
957 for (i = 0; i < num_queues; i++) {
958 wr32(hw, I40E_QINT_TQCTL(i), 0);
959 wr32(hw, I40E_QTX_ENA(i), 0);
960 wr32(hw, I40E_QINT_RQCTL(i), 0);
961 wr32(hw, I40E_QRX_ENA(i), 0);
964 /* short wait for all queue disables to settle */
969 * i40e_clear_pxe_mode - clear pxe operations mode
970 * @hw: pointer to the hw struct
972 * Make sure all PXE mode settings are cleared, including things
973 * like descriptor fetch/write-back mode.
975 void i40e_clear_pxe_mode(struct i40e_hw *hw)
977 if (i40e_check_asq_alive(hw))
978 i40e_aq_clear_pxe_mode(hw, NULL);
982 * i40e_led_is_mine - helper to find matching led
983 * @hw: pointer to the hw struct
984 * @idx: index into GPIO registers
986 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
988 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
993 if (!hw->func_caps.led[idx])
996 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
997 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
998 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1000 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1001 * if it is not our port then ignore
1003 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1010 #define I40E_LED0 22
1011 #define I40E_LINK_ACTIVITY 0xC
1014 * i40e_led_get - return current on/off mode
1015 * @hw: pointer to the hw struct
1017 * The value returned is the 'mode' field as defined in the
1018 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1019 * values are variations of possible behaviors relating to
1020 * blink, link, and wire.
1022 u32 i40e_led_get(struct i40e_hw *hw)
1027 /* as per the documentation GPIO 22-29 are the LED
1028 * GPIO pins named LED0..LED7
1030 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1031 u32 gpio_val = i40e_led_is_mine(hw, i);
1036 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1037 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1045 * i40e_led_set - set new on/off mode
1046 * @hw: pointer to the hw struct
1047 * @mode: 0=off, 0xf=on (else see manual for mode details)
1048 * @blink: true if the LED should blink when on, false if steady
1050 * if this function is used to turn on the blink it should
1051 * be used to disable the blink when restoring the original state.
1053 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1057 if (mode & 0xfffffff0)
1058 DEBUGOUT1("invalid mode passed in %X\n", mode);
1060 /* as per the documentation GPIO 22-29 are the LED
1061 * GPIO pins named LED0..LED7
1063 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1064 u32 gpio_val = i40e_led_is_mine(hw, i);
1069 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1070 /* this & is a bit of paranoia, but serves as a range check */
1071 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1072 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1074 if (mode == I40E_LINK_ACTIVITY)
1077 gpio_val |= (blink ? 1 : 0) <<
1078 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1080 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1085 /* Admin command wrappers */
1088 * i40e_aq_get_phy_capabilities
1089 * @hw: pointer to the hw struct
1090 * @abilities: structure for PHY capabilities to be filled
1091 * @qualified_modules: report Qualified Modules
1092 * @report_init: report init capabilities (active are default)
1093 * @cmd_details: pointer to command details structure or NULL
1095 * Returns the various PHY abilities supported on the Port.
1097 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1098 bool qualified_modules, bool report_init,
1099 struct i40e_aq_get_phy_abilities_resp *abilities,
1100 struct i40e_asq_cmd_details *cmd_details)
1102 struct i40e_aq_desc desc;
1103 enum i40e_status_code status;
1104 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1107 return I40E_ERR_PARAM;
1109 i40e_fill_default_direct_cmd_desc(&desc,
1110 i40e_aqc_opc_get_phy_abilities);
1112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1113 if (abilities_size > I40E_AQ_LARGE_BUF)
1114 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1116 if (qualified_modules)
1117 desc.params.external.param0 |=
1118 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1121 desc.params.external.param0 |=
1122 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1124 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1127 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1128 status = I40E_ERR_UNKNOWN_PHY;
1134 * i40e_aq_set_phy_config
1135 * @hw: pointer to the hw struct
1136 * @config: structure with PHY configuration to be set
1137 * @cmd_details: pointer to command details structure or NULL
1139 * Set the various PHY configuration parameters
1140 * supported on the Port.One or more of the Set PHY config parameters may be
1141 * ignored in an MFP mode as the PF may not have the privilege to set some
1142 * of the PHY Config parameters. This status will be indicated by the
1145 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1146 struct i40e_aq_set_phy_config *config,
1147 struct i40e_asq_cmd_details *cmd_details)
1149 struct i40e_aq_desc desc;
1150 struct i40e_aq_set_phy_config *cmd =
1151 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1152 enum i40e_status_code status;
1155 return I40E_ERR_PARAM;
1157 i40e_fill_default_direct_cmd_desc(&desc,
1158 i40e_aqc_opc_set_phy_config);
1162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1169 * @hw: pointer to the hw struct
1171 * Set the requested flow control mode using set_phy_config.
1173 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1174 bool atomic_restart)
1176 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1177 struct i40e_aq_get_phy_abilities_resp abilities;
1178 struct i40e_aq_set_phy_config config;
1179 enum i40e_status_code status;
1180 u8 pause_mask = 0x0;
1186 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1187 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1189 case I40E_FC_RX_PAUSE:
1190 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1192 case I40E_FC_TX_PAUSE:
1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1199 /* Get the current phy config */
1200 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1203 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET1;
1207 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1208 /* clear the old pause settings */
1209 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1210 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1211 /* set the new abilities */
1212 config.abilities |= pause_mask;
1213 /* If the abilities have changed, then set the new config */
1214 if (config.abilities != abilities.abilities) {
1215 /* Auto restart link so settings take effect */
1217 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1218 /* Copy over all the old settings */
1219 config.phy_type = abilities.phy_type;
1220 config.link_speed = abilities.link_speed;
1221 config.eee_capability = abilities.eee_capability;
1222 config.eeer = abilities.eeer_val;
1223 config.low_power_ctrl = abilities.d3_lpan;
1224 status = i40e_aq_set_phy_config(hw, &config, NULL);
1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1229 /* Get the abilities to set hw->fc.current_mode correctly */
1230 status = i40e_aq_get_phy_capabilities(hw, false, false,
1233 /* Wait a little bit and try once more */
1234 i40e_msec_delay(1000);
1235 status = i40e_aq_get_phy_capabilities(hw, false, false,
1239 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET2;
1243 /* Copy the what was returned from get capabilities into fc */
1244 if ((abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX) &&
1245 (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX))
1246 hw->fc.current_mode = I40E_FC_FULL;
1247 else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX)
1248 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1249 else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX)
1250 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1252 hw->fc.current_mode = I40E_FC_NONE;
1258 * i40e_aq_set_mac_config
1259 * @hw: pointer to the hw struct
1260 * @max_frame_size: Maximum Frame Size to be supported by the port
1261 * @crc_en: Tell HW to append a CRC to outgoing frames
1262 * @pacing: Pacing configurations
1263 * @cmd_details: pointer to command details structure or NULL
1265 * Configure MAC settings for frame size, jumbo frame support and the
1266 * addition of a CRC by the hardware.
1268 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1270 bool crc_en, u16 pacing,
1271 struct i40e_asq_cmd_details *cmd_details)
1273 struct i40e_aq_desc desc;
1274 struct i40e_aq_set_mac_config *cmd =
1275 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1276 enum i40e_status_code status;
1278 if (max_frame_size == 0)
1279 return I40E_ERR_PARAM;
1281 i40e_fill_default_direct_cmd_desc(&desc,
1282 i40e_aqc_opc_set_mac_config);
1284 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1285 cmd->params = ((u8)pacing & 0x0F) << 3;
1287 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1289 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1295 * i40e_aq_clear_pxe_mode
1296 * @hw: pointer to the hw struct
1297 * @cmd_details: pointer to command details structure or NULL
1299 * Tell the firmware that the driver is taking over from PXE
1301 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1302 struct i40e_asq_cmd_details *cmd_details)
1304 enum i40e_status_code status;
1305 struct i40e_aq_desc desc;
1306 struct i40e_aqc_clear_pxe *cmd =
1307 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1309 i40e_fill_default_direct_cmd_desc(&desc,
1310 i40e_aqc_opc_clear_pxe_mode);
1314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1316 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1322 * i40e_aq_set_link_restart_an
1323 * @hw: pointer to the hw struct
1324 * @enable_link: if true: enable link, if false: disable link
1325 * @cmd_details: pointer to command details structure or NULL
1327 * Sets up the link and restarts the Auto-Negotiation over the link.
1329 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1330 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1332 struct i40e_aq_desc desc;
1333 struct i40e_aqc_set_link_restart_an *cmd =
1334 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1335 enum i40e_status_code status;
1337 i40e_fill_default_direct_cmd_desc(&desc,
1338 i40e_aqc_opc_set_link_restart_an);
1340 cmd->command = I40E_AQ_PHY_RESTART_AN;
1342 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1344 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1352 * i40e_aq_get_link_info
1353 * @hw: pointer to the hw struct
1354 * @enable_lse: enable/disable LinkStatusEvent reporting
1355 * @link: pointer to link status structure - optional
1356 * @cmd_details: pointer to command details structure or NULL
1358 * Returns the link status of the adapter.
1360 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1361 bool enable_lse, struct i40e_link_status *link,
1362 struct i40e_asq_cmd_details *cmd_details)
1364 struct i40e_aq_desc desc;
1365 struct i40e_aqc_get_link_status *resp =
1366 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1367 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1368 enum i40e_status_code status;
1369 bool tx_pause, rx_pause;
1372 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1375 command_flags = I40E_AQ_LSE_ENABLE;
1377 command_flags = I40E_AQ_LSE_DISABLE;
1378 resp->command_flags = CPU_TO_LE16(command_flags);
1380 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1382 if (status != I40E_SUCCESS)
1383 goto aq_get_link_info_exit;
1385 /* save off old link status information */
1386 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1387 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1389 /* update link status */
1390 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1391 hw->phy.media_type = i40e_get_media_type(hw);
1392 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1393 hw_link_info->link_info = resp->link_info;
1394 hw_link_info->an_info = resp->an_info;
1395 hw_link_info->ext_info = resp->ext_info;
1396 hw_link_info->loopback = resp->loopback;
1397 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1398 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1400 /* update fc info */
1401 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1402 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1403 if (tx_pause & rx_pause)
1404 hw->fc.current_mode = I40E_FC_FULL;
1406 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1408 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1410 hw->fc.current_mode = I40E_FC_NONE;
1412 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1413 hw_link_info->crc_enable = true;
1415 hw_link_info->crc_enable = false;
1417 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1418 hw_link_info->lse_enable = true;
1420 hw_link_info->lse_enable = false;
1422 /* save link status information */
1424 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1425 I40E_NONDMA_TO_NONDMA);
1427 /* flag cleared so helper functions don't call AQ again */
1428 hw->phy.get_link_info = false;
1430 aq_get_link_info_exit:
1435 * i40e_update_link_info
1436 * @hw: pointer to the hw struct
1437 * @enable_lse: enable/disable LinkStatusEvent reporting
1439 * Returns the link status of the adapter
1441 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1444 struct i40e_aq_get_phy_abilities_resp abilities;
1445 enum i40e_status_code status;
1447 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1451 status = i40e_aq_get_phy_capabilities(hw, false, false,
1456 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1457 hw->phy.link_info.an_enabled = true;
1459 hw->phy.link_info.an_enabled = false;
1465 * i40e_aq_set_phy_int_mask
1466 * @hw: pointer to the hw struct
1467 * @mask: interrupt mask to be set
1468 * @cmd_details: pointer to command details structure or NULL
1470 * Set link interrupt mask.
1472 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1474 struct i40e_asq_cmd_details *cmd_details)
1476 struct i40e_aq_desc desc;
1477 struct i40e_aqc_set_phy_int_mask *cmd =
1478 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1479 enum i40e_status_code status;
1481 i40e_fill_default_direct_cmd_desc(&desc,
1482 i40e_aqc_opc_set_phy_int_mask);
1484 cmd->event_mask = CPU_TO_LE16(mask);
1486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1492 * i40e_aq_get_local_advt_reg
1493 * @hw: pointer to the hw struct
1494 * @advt_reg: local AN advertisement register value
1495 * @cmd_details: pointer to command details structure or NULL
1497 * Get the Local AN advertisement register value.
1499 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1501 struct i40e_asq_cmd_details *cmd_details)
1503 struct i40e_aq_desc desc;
1504 struct i40e_aqc_an_advt_reg *resp =
1505 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1506 enum i40e_status_code status;
1508 i40e_fill_default_direct_cmd_desc(&desc,
1509 i40e_aqc_opc_get_local_advt_reg);
1511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1513 if (status != I40E_SUCCESS)
1514 goto aq_get_local_advt_reg_exit;
1516 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1517 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1519 aq_get_local_advt_reg_exit:
1524 * i40e_aq_set_local_advt_reg
1525 * @hw: pointer to the hw struct
1526 * @advt_reg: local AN advertisement register value
1527 * @cmd_details: pointer to command details structure or NULL
1529 * Get the Local AN advertisement register value.
1531 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1533 struct i40e_asq_cmd_details *cmd_details)
1535 struct i40e_aq_desc desc;
1536 struct i40e_aqc_an_advt_reg *cmd =
1537 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1538 enum i40e_status_code status;
1540 i40e_fill_default_direct_cmd_desc(&desc,
1541 i40e_aqc_opc_get_local_advt_reg);
1543 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1544 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1546 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1552 * i40e_aq_get_partner_advt
1553 * @hw: pointer to the hw struct
1554 * @advt_reg: AN partner advertisement register value
1555 * @cmd_details: pointer to command details structure or NULL
1557 * Get the link partner AN advertisement register value.
1559 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1561 struct i40e_asq_cmd_details *cmd_details)
1563 struct i40e_aq_desc desc;
1564 struct i40e_aqc_an_advt_reg *resp =
1565 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1566 enum i40e_status_code status;
1568 i40e_fill_default_direct_cmd_desc(&desc,
1569 i40e_aqc_opc_get_partner_advt);
1571 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1573 if (status != I40E_SUCCESS)
1574 goto aq_get_partner_advt_exit;
1576 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1577 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1579 aq_get_partner_advt_exit:
1584 * i40e_aq_set_lb_modes
1585 * @hw: pointer to the hw struct
1586 * @lb_modes: loopback mode to be set
1587 * @cmd_details: pointer to command details structure or NULL
1589 * Sets loopback modes.
1591 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1593 struct i40e_asq_cmd_details *cmd_details)
1595 struct i40e_aq_desc desc;
1596 struct i40e_aqc_set_lb_mode *cmd =
1597 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1598 enum i40e_status_code status;
1600 i40e_fill_default_direct_cmd_desc(&desc,
1601 i40e_aqc_opc_set_lb_modes);
1603 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1611 * i40e_aq_set_phy_debug
1612 * @hw: pointer to the hw struct
1613 * @cmd_flags: debug command flags
1614 * @cmd_details: pointer to command details structure or NULL
1616 * Reset the external PHY.
1618 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1619 struct i40e_asq_cmd_details *cmd_details)
1621 struct i40e_aq_desc desc;
1622 struct i40e_aqc_set_phy_debug *cmd =
1623 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1624 enum i40e_status_code status;
1626 i40e_fill_default_direct_cmd_desc(&desc,
1627 i40e_aqc_opc_set_phy_debug);
1629 cmd->command_flags = cmd_flags;
1631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1638 * @hw: pointer to the hw struct
1639 * @vsi_ctx: pointer to a vsi context struct
1640 * @cmd_details: pointer to command details structure or NULL
1642 * Add a VSI context to the hardware.
1644 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1645 struct i40e_vsi_context *vsi_ctx,
1646 struct i40e_asq_cmd_details *cmd_details)
1648 struct i40e_aq_desc desc;
1649 struct i40e_aqc_add_get_update_vsi *cmd =
1650 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1651 struct i40e_aqc_add_get_update_vsi_completion *resp =
1652 (struct i40e_aqc_add_get_update_vsi_completion *)
1654 enum i40e_status_code status;
1656 i40e_fill_default_direct_cmd_desc(&desc,
1657 i40e_aqc_opc_add_vsi);
1659 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1660 cmd->connection_type = vsi_ctx->connection_type;
1661 cmd->vf_id = vsi_ctx->vf_num;
1662 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1664 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1666 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1667 sizeof(vsi_ctx->info), cmd_details);
1669 if (status != I40E_SUCCESS)
1670 goto aq_add_vsi_exit;
1672 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1673 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1674 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1675 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1682 * i40e_aq_set_default_vsi
1683 * @hw: pointer to the hw struct
1685 * @cmd_details: pointer to command details structure or NULL
1687 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1689 struct i40e_asq_cmd_details *cmd_details)
1691 struct i40e_aq_desc desc;
1692 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1693 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1695 enum i40e_status_code status;
1697 i40e_fill_default_direct_cmd_desc(&desc,
1698 i40e_aqc_opc_set_vsi_promiscuous_modes);
1700 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1701 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1702 cmd->seid = CPU_TO_LE16(seid);
1704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1710 * i40e_aq_set_vsi_unicast_promiscuous
1711 * @hw: pointer to the hw struct
1713 * @set: set unicast promiscuous enable/disable
1714 * @cmd_details: pointer to command details structure or NULL
1716 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1718 struct i40e_asq_cmd_details *cmd_details)
1720 struct i40e_aq_desc desc;
1721 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1722 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1723 enum i40e_status_code status;
1726 i40e_fill_default_direct_cmd_desc(&desc,
1727 i40e_aqc_opc_set_vsi_promiscuous_modes);
1730 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1732 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1734 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1736 cmd->seid = CPU_TO_LE16(seid);
1737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1743 * i40e_aq_set_vsi_multicast_promiscuous
1744 * @hw: pointer to the hw struct
1746 * @set: set multicast promiscuous enable/disable
1747 * @cmd_details: pointer to command details structure or NULL
1749 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1750 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1752 struct i40e_aq_desc desc;
1753 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1754 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1755 enum i40e_status_code status;
1758 i40e_fill_default_direct_cmd_desc(&desc,
1759 i40e_aqc_opc_set_vsi_promiscuous_modes);
1762 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1764 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1766 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1768 cmd->seid = CPU_TO_LE16(seid);
1769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1775 * i40e_aq_set_vsi_broadcast
1776 * @hw: pointer to the hw struct
1778 * @set_filter: true to set filter, false to clear filter
1779 * @cmd_details: pointer to command details structure or NULL
1781 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1783 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1784 u16 seid, bool set_filter,
1785 struct i40e_asq_cmd_details *cmd_details)
1787 struct i40e_aq_desc desc;
1788 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1789 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1790 enum i40e_status_code status;
1792 i40e_fill_default_direct_cmd_desc(&desc,
1793 i40e_aqc_opc_set_vsi_promiscuous_modes);
1796 cmd->promiscuous_flags
1797 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1799 cmd->promiscuous_flags
1800 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1802 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1803 cmd->seid = CPU_TO_LE16(seid);
1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1810 * i40e_get_vsi_params - get VSI configuration info
1811 * @hw: pointer to the hw struct
1812 * @vsi_ctx: pointer to a vsi context struct
1813 * @cmd_details: pointer to command details structure or NULL
1815 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1816 struct i40e_vsi_context *vsi_ctx,
1817 struct i40e_asq_cmd_details *cmd_details)
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_add_get_update_vsi *cmd =
1821 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1822 struct i40e_aqc_add_get_update_vsi_completion *resp =
1823 (struct i40e_aqc_add_get_update_vsi_completion *)
1825 enum i40e_status_code status;
1827 UNREFERENCED_1PARAMETER(cmd_details);
1828 i40e_fill_default_direct_cmd_desc(&desc,
1829 i40e_aqc_opc_get_vsi_parameters);
1831 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1833 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1835 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1836 sizeof(vsi_ctx->info), NULL);
1838 if (status != I40E_SUCCESS)
1839 goto aq_get_vsi_params_exit;
1841 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1842 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1843 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1844 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1846 aq_get_vsi_params_exit:
1851 * i40e_aq_update_vsi_params
1852 * @hw: pointer to the hw struct
1853 * @vsi_ctx: pointer to a vsi context struct
1854 * @cmd_details: pointer to command details structure or NULL
1856 * Update a VSI context.
1858 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1859 struct i40e_vsi_context *vsi_ctx,
1860 struct i40e_asq_cmd_details *cmd_details)
1862 struct i40e_aq_desc desc;
1863 struct i40e_aqc_add_get_update_vsi *cmd =
1864 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1865 enum i40e_status_code status;
1867 i40e_fill_default_direct_cmd_desc(&desc,
1868 i40e_aqc_opc_update_vsi_parameters);
1869 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1871 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1873 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1874 sizeof(vsi_ctx->info), cmd_details);
1880 * i40e_aq_get_switch_config
1881 * @hw: pointer to the hardware structure
1882 * @buf: pointer to the result buffer
1883 * @buf_size: length of input buffer
1884 * @start_seid: seid to start for the report, 0 == beginning
1885 * @cmd_details: pointer to command details structure or NULL
1887 * Fill the buf with switch configuration returned from AdminQ command
1889 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1890 struct i40e_aqc_get_switch_config_resp *buf,
1891 u16 buf_size, u16 *start_seid,
1892 struct i40e_asq_cmd_details *cmd_details)
1894 struct i40e_aq_desc desc;
1895 struct i40e_aqc_switch_seid *scfg =
1896 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1897 enum i40e_status_code status;
1899 i40e_fill_default_direct_cmd_desc(&desc,
1900 i40e_aqc_opc_get_switch_config);
1901 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1902 if (buf_size > I40E_AQ_LARGE_BUF)
1903 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1904 scfg->seid = CPU_TO_LE16(*start_seid);
1906 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1907 *start_seid = LE16_TO_CPU(scfg->seid);
1913 * i40e_aq_get_firmware_version
1914 * @hw: pointer to the hw struct
1915 * @fw_major_version: firmware major version
1916 * @fw_minor_version: firmware minor version
1917 * @api_major_version: major queue version
1918 * @api_minor_version: minor queue version
1919 * @cmd_details: pointer to command details structure or NULL
1921 * Get the firmware version from the admin queue commands
1923 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1924 u16 *fw_major_version, u16 *fw_minor_version,
1925 u16 *api_major_version, u16 *api_minor_version,
1926 struct i40e_asq_cmd_details *cmd_details)
1928 struct i40e_aq_desc desc;
1929 struct i40e_aqc_get_version *resp =
1930 (struct i40e_aqc_get_version *)&desc.params.raw;
1931 enum i40e_status_code status;
1933 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1935 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1937 if (status == I40E_SUCCESS) {
1938 if (fw_major_version != NULL)
1939 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1940 if (fw_minor_version != NULL)
1941 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1942 if (api_major_version != NULL)
1943 *api_major_version = LE16_TO_CPU(resp->api_major);
1944 if (api_minor_version != NULL)
1945 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1952 * i40e_aq_send_driver_version
1953 * @hw: pointer to the hw struct
1954 * @dv: driver's major, minor version
1955 * @cmd_details: pointer to command details structure or NULL
1957 * Send the driver version to the firmware
1959 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1960 struct i40e_driver_version *dv,
1961 struct i40e_asq_cmd_details *cmd_details)
1963 struct i40e_aq_desc desc;
1964 struct i40e_aqc_driver_version *cmd =
1965 (struct i40e_aqc_driver_version *)&desc.params.raw;
1966 enum i40e_status_code status;
1970 return I40E_ERR_PARAM;
1972 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1974 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI);
1975 cmd->driver_major_ver = dv->major_version;
1976 cmd->driver_minor_ver = dv->minor_version;
1977 cmd->driver_build_ver = dv->build_version;
1978 cmd->driver_subbuild_ver = dv->subbuild_version;
1981 while (len < sizeof(dv->driver_string) &&
1982 (dv->driver_string[len] < 0x80) &&
1983 dv->driver_string[len])
1985 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1992 * i40e_get_link_status - get status of the HW network link
1993 * @hw: pointer to the hw struct
1995 * Returns true if link is up, false if link is down.
1997 * Side effect: LinkStatusEvent reporting becomes enabled
1999 bool i40e_get_link_status(struct i40e_hw *hw)
2001 enum i40e_status_code status = I40E_SUCCESS;
2002 bool link_status = false;
2004 if (hw->phy.get_link_info) {
2005 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2007 if (status != I40E_SUCCESS)
2008 goto i40e_get_link_status_exit;
2011 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2013 i40e_get_link_status_exit:
2018 * i40e_get_link_speed
2019 * @hw: pointer to the hw struct
2021 * Returns the link speed of the adapter.
2023 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2025 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2026 enum i40e_status_code status = I40E_SUCCESS;
2028 if (hw->phy.get_link_info) {
2029 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2031 if (status != I40E_SUCCESS)
2032 goto i40e_link_speed_exit;
2035 speed = hw->phy.link_info.link_speed;
2037 i40e_link_speed_exit:
2042 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2043 * @hw: pointer to the hw struct
2044 * @uplink_seid: the MAC or other gizmo SEID
2045 * @downlink_seid: the VSI SEID
2046 * @enabled_tc: bitmap of TCs to be enabled
2047 * @default_port: true for default port VSI, false for control port
2048 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2049 * @veb_seid: pointer to where to put the resulting VEB SEID
2050 * @cmd_details: pointer to command details structure or NULL
2052 * This asks the FW to add a VEB between the uplink and downlink
2053 * elements. If the uplink SEID is 0, this will be a floating VEB.
2055 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2056 u16 downlink_seid, u8 enabled_tc,
2057 bool default_port, bool enable_l2_filtering,
2059 struct i40e_asq_cmd_details *cmd_details)
2061 struct i40e_aq_desc desc;
2062 struct i40e_aqc_add_veb *cmd =
2063 (struct i40e_aqc_add_veb *)&desc.params.raw;
2064 struct i40e_aqc_add_veb_completion *resp =
2065 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2066 enum i40e_status_code status;
2069 /* SEIDs need to either both be set or both be 0 for floating VEB */
2070 if (!!uplink_seid != !!downlink_seid)
2071 return I40E_ERR_PARAM;
2073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2075 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2076 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2077 cmd->enable_tcs = enabled_tc;
2079 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2081 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2083 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2085 if (enable_l2_filtering)
2086 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2088 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2092 if (!status && veb_seid)
2093 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2099 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2100 * @hw: pointer to the hw struct
2101 * @veb_seid: the SEID of the VEB to query
2102 * @switch_id: the uplink switch id
2103 * @floating: set to true if the VEB is floating
2104 * @statistic_index: index of the stats counter block for this VEB
2105 * @vebs_used: number of VEB's used by function
2106 * @vebs_free: total VEB's not reserved by any function
2107 * @cmd_details: pointer to command details structure or NULL
2109 * This retrieves the parameters for a particular VEB, specified by
2110 * uplink_seid, and returns them to the caller.
2112 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2113 u16 veb_seid, u16 *switch_id,
2114 bool *floating, u16 *statistic_index,
2115 u16 *vebs_used, u16 *vebs_free,
2116 struct i40e_asq_cmd_details *cmd_details)
2118 struct i40e_aq_desc desc;
2119 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2120 (struct i40e_aqc_get_veb_parameters_completion *)
2122 enum i40e_status_code status;
2125 return I40E_ERR_PARAM;
2127 i40e_fill_default_direct_cmd_desc(&desc,
2128 i40e_aqc_opc_get_veb_parameters);
2129 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2131 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2136 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2137 if (statistic_index)
2138 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2140 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2142 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2144 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2145 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2156 * i40e_aq_add_macvlan
2157 * @hw: pointer to the hw struct
2158 * @seid: VSI for the mac address
2159 * @mv_list: list of macvlans to be added
2160 * @count: length of the list
2161 * @cmd_details: pointer to command details structure or NULL
2163 * Add MAC/VLAN addresses to the HW filtering
2165 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2166 struct i40e_aqc_add_macvlan_element_data *mv_list,
2167 u16 count, struct i40e_asq_cmd_details *cmd_details)
2169 struct i40e_aq_desc desc;
2170 struct i40e_aqc_macvlan *cmd =
2171 (struct i40e_aqc_macvlan *)&desc.params.raw;
2172 enum i40e_status_code status;
2175 if (count == 0 || !mv_list || !hw)
2176 return I40E_ERR_PARAM;
2178 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2180 /* prep the rest of the request */
2181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2182 cmd->num_addresses = CPU_TO_LE16(count);
2183 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2187 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2188 if (buf_size > I40E_AQ_LARGE_BUF)
2189 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2191 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2198 * i40e_aq_remove_macvlan
2199 * @hw: pointer to the hw struct
2200 * @seid: VSI for the mac address
2201 * @mv_list: list of macvlans to be removed
2202 * @count: length of the list
2203 * @cmd_details: pointer to command details structure or NULL
2205 * Remove MAC/VLAN addresses from the HW filtering
2207 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2208 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2209 u16 count, struct i40e_asq_cmd_details *cmd_details)
2211 struct i40e_aq_desc desc;
2212 struct i40e_aqc_macvlan *cmd =
2213 (struct i40e_aqc_macvlan *)&desc.params.raw;
2214 enum i40e_status_code status;
2217 if (count == 0 || !mv_list || !hw)
2218 return I40E_ERR_PARAM;
2220 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2222 /* prep the rest of the request */
2223 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2224 cmd->num_addresses = CPU_TO_LE16(count);
2225 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2229 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2230 if (buf_size > I40E_AQ_LARGE_BUF)
2231 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2233 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2240 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2241 * @hw: pointer to the hw struct
2242 * @seid: VSI for the vlan filters
2243 * @v_list: list of vlan filters to be added
2244 * @count: length of the list
2245 * @cmd_details: pointer to command details structure or NULL
2247 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2248 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2249 u8 count, struct i40e_asq_cmd_details *cmd_details)
2251 struct i40e_aq_desc desc;
2252 struct i40e_aqc_macvlan *cmd =
2253 (struct i40e_aqc_macvlan *)&desc.params.raw;
2254 enum i40e_status_code status;
2257 if (count == 0 || !v_list || !hw)
2258 return I40E_ERR_PARAM;
2260 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2262 /* prep the rest of the request */
2263 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2264 cmd->num_addresses = CPU_TO_LE16(count);
2265 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2269 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2270 if (buf_size > I40E_AQ_LARGE_BUF)
2271 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2273 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2280 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2281 * @hw: pointer to the hw struct
2282 * @seid: VSI for the vlan filters
2283 * @v_list: list of macvlans to be removed
2284 * @count: length of the list
2285 * @cmd_details: pointer to command details structure or NULL
2287 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2288 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2289 u8 count, struct i40e_asq_cmd_details *cmd_details)
2291 struct i40e_aq_desc desc;
2292 struct i40e_aqc_macvlan *cmd =
2293 (struct i40e_aqc_macvlan *)&desc.params.raw;
2294 enum i40e_status_code status;
2297 if (count == 0 || !v_list || !hw)
2298 return I40E_ERR_PARAM;
2300 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2302 /* prep the rest of the request */
2303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2304 cmd->num_addresses = CPU_TO_LE16(count);
2305 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2309 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2310 if (buf_size > I40E_AQ_LARGE_BUF)
2311 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2313 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2320 * i40e_aq_send_msg_to_vf
2321 * @hw: pointer to the hardware structure
2322 * @vfid: vf id to send msg
2323 * @v_opcode: opcodes for VF-PF communication
2324 * @v_retval: return error code
2325 * @msg: pointer to the msg buffer
2326 * @msglen: msg length
2327 * @cmd_details: pointer to command details
2331 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2332 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2333 struct i40e_asq_cmd_details *cmd_details)
2335 struct i40e_aq_desc desc;
2336 struct i40e_aqc_pf_vf_message *cmd =
2337 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2338 enum i40e_status_code status;
2340 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2341 cmd->id = CPU_TO_LE32(vfid);
2342 desc.cookie_high = CPU_TO_LE32(v_opcode);
2343 desc.cookie_low = CPU_TO_LE32(v_retval);
2344 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2346 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2348 if (msglen > I40E_AQ_LARGE_BUF)
2349 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2350 desc.datalen = CPU_TO_LE16(msglen);
2352 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2358 * i40e_aq_get_hmc_resource_profile
2359 * @hw: pointer to the hw struct
2360 * @profile: type of profile the HMC is to be set as
2361 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2362 * @cmd_details: pointer to command details structure or NULL
2364 * query the HMC profile of the device.
2366 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2367 enum i40e_aq_hmc_profile *profile,
2368 u8 *pe_vf_enabled_count,
2369 struct i40e_asq_cmd_details *cmd_details)
2371 struct i40e_aq_desc desc;
2372 struct i40e_aq_get_set_hmc_resource_profile *resp =
2373 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2374 enum i40e_status_code status;
2376 i40e_fill_default_direct_cmd_desc(&desc,
2377 i40e_aqc_opc_query_hmc_resource_profile);
2378 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2380 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2381 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2382 *pe_vf_enabled_count = resp->pe_vf_enabled &
2383 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2389 * i40e_aq_set_hmc_resource_profile
2390 * @hw: pointer to the hw struct
2391 * @profile: type of profile the HMC is to be set as
2392 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2393 * @cmd_details: pointer to command details structure or NULL
2395 * set the HMC profile of the device.
2397 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2398 enum i40e_aq_hmc_profile profile,
2399 u8 pe_vf_enabled_count,
2400 struct i40e_asq_cmd_details *cmd_details)
2402 struct i40e_aq_desc desc;
2403 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2404 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2405 enum i40e_status_code status;
2407 i40e_fill_default_direct_cmd_desc(&desc,
2408 i40e_aqc_opc_set_hmc_resource_profile);
2410 cmd->pm_profile = (u8)profile;
2411 cmd->pe_vf_enabled = pe_vf_enabled_count;
2413 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2419 * i40e_aq_request_resource
2420 * @hw: pointer to the hw struct
2421 * @resource: resource id
2422 * @access: access type
2423 * @sdp_number: resource number
2424 * @timeout: the maximum time in ms that the driver may hold the resource
2425 * @cmd_details: pointer to command details structure or NULL
2427 * requests common resource using the admin queue commands
2429 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2430 enum i40e_aq_resources_ids resource,
2431 enum i40e_aq_resource_access_type access,
2432 u8 sdp_number, u64 *timeout,
2433 struct i40e_asq_cmd_details *cmd_details)
2435 struct i40e_aq_desc desc;
2436 struct i40e_aqc_request_resource *cmd_resp =
2437 (struct i40e_aqc_request_resource *)&desc.params.raw;
2438 enum i40e_status_code status;
2440 DEBUGFUNC("i40e_aq_request_resource");
2442 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2444 cmd_resp->resource_id = CPU_TO_LE16(resource);
2445 cmd_resp->access_type = CPU_TO_LE16(access);
2446 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2448 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2449 /* The completion specifies the maximum time in ms that the driver
2450 * may hold the resource in the Timeout field.
2451 * If the resource is held by someone else, the command completes with
2452 * busy return value and the timeout field indicates the maximum time
2453 * the current owner of the resource has to free it.
2455 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2456 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2462 * i40e_aq_release_resource
2463 * @hw: pointer to the hw struct
2464 * @resource: resource id
2465 * @sdp_number: resource number
2466 * @cmd_details: pointer to command details structure or NULL
2468 * release common resource using the admin queue commands
2470 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2471 enum i40e_aq_resources_ids resource,
2473 struct i40e_asq_cmd_details *cmd_details)
2475 struct i40e_aq_desc desc;
2476 struct i40e_aqc_request_resource *cmd =
2477 (struct i40e_aqc_request_resource *)&desc.params.raw;
2478 enum i40e_status_code status;
2480 DEBUGFUNC("i40e_aq_release_resource");
2482 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2484 cmd->resource_id = CPU_TO_LE16(resource);
2485 cmd->resource_number = CPU_TO_LE32(sdp_number);
2487 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2494 * @hw: pointer to the hw struct
2495 * @module_pointer: module pointer location in words from the NVM beginning
2496 * @offset: byte offset from the module beginning
2497 * @length: length of the section to be read (in bytes from the offset)
2498 * @data: command buffer (size [bytes] = length)
2499 * @last_command: tells if this is the last command in a series
2500 * @cmd_details: pointer to command details structure or NULL
2502 * Read the NVM using the admin queue commands
2504 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2505 u32 offset, u16 length, void *data,
2507 struct i40e_asq_cmd_details *cmd_details)
2509 struct i40e_aq_desc desc;
2510 struct i40e_aqc_nvm_update *cmd =
2511 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2512 enum i40e_status_code status;
2514 DEBUGFUNC("i40e_aq_read_nvm");
2516 /* In offset the highest byte must be zeroed. */
2517 if (offset & 0xFF000000) {
2518 status = I40E_ERR_PARAM;
2519 goto i40e_aq_read_nvm_exit;
2522 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2524 /* If this is the last command in a series, set the proper flag. */
2526 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2527 cmd->module_pointer = module_pointer;
2528 cmd->offset = CPU_TO_LE32(offset);
2529 cmd->length = CPU_TO_LE16(length);
2531 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2532 if (length > I40E_AQ_LARGE_BUF)
2533 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2535 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2537 i40e_aq_read_nvm_exit:
2543 * @hw: pointer to the hw struct
2544 * @module_pointer: module pointer location in words from the NVM beginning
2545 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2546 * @length: length of the section to be erased (expressed in 4 KB)
2547 * @last_command: tells if this is the last command in a series
2548 * @cmd_details: pointer to command details structure or NULL
2550 * Erase the NVM sector using the admin queue commands
2552 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2553 u32 offset, u16 length, bool last_command,
2554 struct i40e_asq_cmd_details *cmd_details)
2556 struct i40e_aq_desc desc;
2557 struct i40e_aqc_nvm_update *cmd =
2558 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2559 enum i40e_status_code status;
2561 DEBUGFUNC("i40e_aq_erase_nvm");
2563 /* In offset the highest byte must be zeroed. */
2564 if (offset & 0xFF000000) {
2565 status = I40E_ERR_PARAM;
2566 goto i40e_aq_erase_nvm_exit;
2569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2571 /* If this is the last command in a series, set the proper flag. */
2573 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2574 cmd->module_pointer = module_pointer;
2575 cmd->offset = CPU_TO_LE32(offset);
2576 cmd->length = CPU_TO_LE16(length);
2578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2580 i40e_aq_erase_nvm_exit:
2584 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2585 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2586 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2587 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2588 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2589 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2590 #define I40E_DEV_FUNC_CAP_VF 0x13
2591 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2592 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2593 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2594 #define I40E_DEV_FUNC_CAP_VSI 0x17
2595 #define I40E_DEV_FUNC_CAP_DCB 0x18
2596 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2597 #define I40E_DEV_FUNC_CAP_RSS 0x40
2598 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2599 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2600 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2601 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2602 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2603 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2604 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2605 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2606 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2607 #define I40E_DEV_FUNC_CAP_LED 0x61
2608 #define I40E_DEV_FUNC_CAP_SDP 0x62
2609 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2612 * i40e_parse_discover_capabilities
2613 * @hw: pointer to the hw struct
2614 * @buff: pointer to a buffer containing device/function capability records
2615 * @cap_count: number of capability records in the list
2616 * @list_type_opc: type of capabilities list to parse
2618 * Parse the device/function capabilities list.
2620 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2622 enum i40e_admin_queue_opc list_type_opc)
2624 struct i40e_aqc_list_capabilities_element_resp *cap;
2625 u32 number, logical_id, phys_id;
2626 struct i40e_hw_capabilities *p;
2630 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2632 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2633 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2634 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2635 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2639 for (i = 0; i < cap_count; i++, cap++) {
2640 id = LE16_TO_CPU(cap->id);
2641 number = LE32_TO_CPU(cap->number);
2642 logical_id = LE32_TO_CPU(cap->logical_id);
2643 phys_id = LE32_TO_CPU(cap->phys_id);
2646 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2647 p->switch_mode = number;
2649 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2650 p->management_mode = number;
2652 case I40E_DEV_FUNC_CAP_NPAR:
2653 p->npar_enable = number;
2655 case I40E_DEV_FUNC_CAP_OS2BMC:
2658 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2659 p->valid_functions = number;
2661 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2663 p->sr_iov_1_1 = true;
2665 case I40E_DEV_FUNC_CAP_VF:
2666 p->num_vfs = number;
2667 p->vf_base_id = logical_id;
2669 case I40E_DEV_FUNC_CAP_VMDQ:
2673 case I40E_DEV_FUNC_CAP_802_1_QBG:
2675 p->evb_802_1_qbg = true;
2677 case I40E_DEV_FUNC_CAP_802_1_QBH:
2679 p->evb_802_1_qbh = true;
2681 case I40E_DEV_FUNC_CAP_VSI:
2682 p->num_vsis = number;
2684 case I40E_DEV_FUNC_CAP_DCB:
2687 p->enabled_tcmap = logical_id;
2691 case I40E_DEV_FUNC_CAP_FCOE:
2695 case I40E_DEV_FUNC_CAP_RSS:
2697 p->rss_table_size = number;
2698 p->rss_table_entry_width = logical_id;
2700 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2701 p->num_rx_qp = number;
2702 p->base_queue = phys_id;
2704 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2705 p->num_tx_qp = number;
2706 p->base_queue = phys_id;
2708 case I40E_DEV_FUNC_CAP_MSIX:
2709 p->num_msix_vectors = number;
2711 case I40E_DEV_FUNC_CAP_MSIX_VF:
2712 p->num_msix_vectors_vf = number;
2714 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2716 p->mfp_mode_1 = true;
2718 case I40E_DEV_FUNC_CAP_CEM:
2722 case I40E_DEV_FUNC_CAP_IWARP:
2726 case I40E_DEV_FUNC_CAP_LED:
2727 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2728 p->led[phys_id] = true;
2730 case I40E_DEV_FUNC_CAP_SDP:
2731 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2732 p->sdp[phys_id] = true;
2734 case I40E_DEV_FUNC_CAP_MDIO:
2736 p->mdio_port_num = phys_id;
2737 p->mdio_port_mode = logical_id;
2740 case I40E_DEV_FUNC_CAP_IEEE_1588:
2742 p->ieee_1588 = true;
2744 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2746 p->fd_filters_guaranteed = number;
2747 p->fd_filters_best_effort = logical_id;
2754 /* Software override ensuring FCoE is disabled if npar or mfp
2755 * mode because it is not supported in these modes.
2757 if (p->npar_enable || p->mfp_mode_1)
2760 /* additional HW specific goodies that might
2761 * someday be HW version specific
2763 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2767 * i40e_aq_discover_capabilities
2768 * @hw: pointer to the hw struct
2769 * @buff: a virtual buffer to hold the capabilities
2770 * @buff_size: Size of the virtual buffer
2771 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2772 * @list_type_opc: capabilities type to discover - pass in the command opcode
2773 * @cmd_details: pointer to command details structure or NULL
2775 * Get the device capabilities descriptions from the firmware
2777 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2778 void *buff, u16 buff_size, u16 *data_size,
2779 enum i40e_admin_queue_opc list_type_opc,
2780 struct i40e_asq_cmd_details *cmd_details)
2782 struct i40e_aqc_list_capabilites *cmd;
2783 struct i40e_aq_desc desc;
2784 enum i40e_status_code status = I40E_SUCCESS;
2786 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2788 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2789 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2790 status = I40E_ERR_PARAM;
2794 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2796 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2797 if (buff_size > I40E_AQ_LARGE_BUF)
2798 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2800 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2801 *data_size = LE16_TO_CPU(desc.datalen);
2806 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2814 * i40e_aq_update_nvm
2815 * @hw: pointer to the hw struct
2816 * @module_pointer: module pointer location in words from the NVM beginning
2817 * @offset: byte offset from the module beginning
2818 * @length: length of the section to be written (in bytes from the offset)
2819 * @data: command buffer (size [bytes] = length)
2820 * @last_command: tells if this is the last command in a series
2821 * @cmd_details: pointer to command details structure or NULL
2823 * Update the NVM using the admin queue commands
2825 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2826 u32 offset, u16 length, void *data,
2828 struct i40e_asq_cmd_details *cmd_details)
2830 struct i40e_aq_desc desc;
2831 struct i40e_aqc_nvm_update *cmd =
2832 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2833 enum i40e_status_code status;
2835 DEBUGFUNC("i40e_aq_update_nvm");
2837 /* In offset the highest byte must be zeroed. */
2838 if (offset & 0xFF000000) {
2839 status = I40E_ERR_PARAM;
2840 goto i40e_aq_update_nvm_exit;
2843 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2845 /* If this is the last command in a series, set the proper flag. */
2847 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2848 cmd->module_pointer = module_pointer;
2849 cmd->offset = CPU_TO_LE32(offset);
2850 cmd->length = CPU_TO_LE16(length);
2852 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2853 if (length > I40E_AQ_LARGE_BUF)
2854 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2856 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2858 i40e_aq_update_nvm_exit:
2863 * i40e_aq_get_lldp_mib
2864 * @hw: pointer to the hw struct
2865 * @bridge_type: type of bridge requested
2866 * @mib_type: Local, Remote or both Local and Remote MIBs
2867 * @buff: pointer to a user supplied buffer to store the MIB block
2868 * @buff_size: size of the buffer (in bytes)
2869 * @local_len : length of the returned Local LLDP MIB
2870 * @remote_len: length of the returned Remote LLDP MIB
2871 * @cmd_details: pointer to command details structure or NULL
2873 * Requests the complete LLDP MIB (entire packet).
2875 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2876 u8 mib_type, void *buff, u16 buff_size,
2877 u16 *local_len, u16 *remote_len,
2878 struct i40e_asq_cmd_details *cmd_details)
2880 struct i40e_aq_desc desc;
2881 struct i40e_aqc_lldp_get_mib *cmd =
2882 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2883 struct i40e_aqc_lldp_get_mib *resp =
2884 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2885 enum i40e_status_code status;
2887 if (buff_size == 0 || !buff)
2888 return I40E_ERR_PARAM;
2890 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2891 /* Indirect Command */
2892 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2894 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2895 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2896 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2898 desc.datalen = CPU_TO_LE16(buff_size);
2900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2901 if (buff_size > I40E_AQ_LARGE_BUF)
2902 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2904 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2906 if (local_len != NULL)
2907 *local_len = LE16_TO_CPU(resp->local_len);
2908 if (remote_len != NULL)
2909 *remote_len = LE16_TO_CPU(resp->remote_len);
2916 * i40e_aq_cfg_lldp_mib_change_event
2917 * @hw: pointer to the hw struct
2918 * @enable_update: Enable or Disable event posting
2919 * @cmd_details: pointer to command details structure or NULL
2921 * Enable or Disable posting of an event on ARQ when LLDP MIB
2922 * associated with the interface changes
2924 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2926 struct i40e_asq_cmd_details *cmd_details)
2928 struct i40e_aq_desc desc;
2929 struct i40e_aqc_lldp_update_mib *cmd =
2930 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2931 enum i40e_status_code status;
2933 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2936 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2938 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2944 * i40e_aq_add_lldp_tlv
2945 * @hw: pointer to the hw struct
2946 * @bridge_type: type of bridge
2947 * @buff: buffer with TLV to add
2948 * @buff_size: length of the buffer
2949 * @tlv_len: length of the TLV to be added
2950 * @mib_len: length of the LLDP MIB returned in response
2951 * @cmd_details: pointer to command details structure or NULL
2953 * Add the specified TLV to LLDP Local MIB for the given bridge type,
2954 * it is responsibility of the caller to make sure that the TLV is not
2955 * already present in the LLDPDU.
2956 * In return firmware will write the complete LLDP MIB with the newly
2957 * added TLV in the response buffer.
2959 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
2960 void *buff, u16 buff_size, u16 tlv_len,
2962 struct i40e_asq_cmd_details *cmd_details)
2964 struct i40e_aq_desc desc;
2965 struct i40e_aqc_lldp_add_tlv *cmd =
2966 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
2967 enum i40e_status_code status;
2969 if (buff_size == 0 || !buff || tlv_len == 0)
2970 return I40E_ERR_PARAM;
2972 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
2974 /* Indirect Command */
2975 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2976 if (buff_size > I40E_AQ_LARGE_BUF)
2977 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2978 desc.datalen = CPU_TO_LE16(buff_size);
2980 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2981 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2982 cmd->len = CPU_TO_LE16(tlv_len);
2984 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2986 if (mib_len != NULL)
2987 *mib_len = LE16_TO_CPU(desc.datalen);
2994 * i40e_aq_update_lldp_tlv
2995 * @hw: pointer to the hw struct
2996 * @bridge_type: type of bridge
2997 * @buff: buffer with TLV to update
2998 * @buff_size: size of the buffer holding original and updated TLVs
2999 * @old_len: Length of the Original TLV
3000 * @new_len: Length of the Updated TLV
3001 * @offset: offset of the updated TLV in the buff
3002 * @mib_len: length of the returned LLDP MIB
3003 * @cmd_details: pointer to command details structure or NULL
3005 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3006 * Firmware will place the complete LLDP MIB in response buffer with the
3009 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3010 u8 bridge_type, void *buff, u16 buff_size,
3011 u16 old_len, u16 new_len, u16 offset,
3013 struct i40e_asq_cmd_details *cmd_details)
3015 struct i40e_aq_desc desc;
3016 struct i40e_aqc_lldp_update_tlv *cmd =
3017 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3018 enum i40e_status_code status;
3020 if (buff_size == 0 || !buff || offset == 0 ||
3021 old_len == 0 || new_len == 0)
3022 return I40E_ERR_PARAM;
3024 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3026 /* Indirect Command */
3027 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3028 if (buff_size > I40E_AQ_LARGE_BUF)
3029 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3030 desc.datalen = CPU_TO_LE16(buff_size);
3032 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3033 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3034 cmd->old_len = CPU_TO_LE16(old_len);
3035 cmd->new_offset = CPU_TO_LE16(offset);
3036 cmd->new_len = CPU_TO_LE16(new_len);
3038 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3040 if (mib_len != NULL)
3041 *mib_len = LE16_TO_CPU(desc.datalen);
3048 * i40e_aq_delete_lldp_tlv
3049 * @hw: pointer to the hw struct
3050 * @bridge_type: type of bridge
3051 * @buff: pointer to a user supplied buffer that has the TLV
3052 * @buff_size: length of the buffer
3053 * @tlv_len: length of the TLV to be deleted
3054 * @mib_len: length of the returned LLDP MIB
3055 * @cmd_details: pointer to command details structure or NULL
3057 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3058 * The firmware places the entire LLDP MIB in the response buffer.
3060 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3061 u8 bridge_type, void *buff, u16 buff_size,
3062 u16 tlv_len, u16 *mib_len,
3063 struct i40e_asq_cmd_details *cmd_details)
3065 struct i40e_aq_desc desc;
3066 struct i40e_aqc_lldp_add_tlv *cmd =
3067 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3068 enum i40e_status_code status;
3070 if (buff_size == 0 || !buff)
3071 return I40E_ERR_PARAM;
3073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3075 /* Indirect Command */
3076 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3077 if (buff_size > I40E_AQ_LARGE_BUF)
3078 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3079 desc.datalen = CPU_TO_LE16(buff_size);
3080 cmd->len = CPU_TO_LE16(tlv_len);
3081 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3082 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3084 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3086 if (mib_len != NULL)
3087 *mib_len = LE16_TO_CPU(desc.datalen);
3095 * @hw: pointer to the hw struct
3096 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3097 * @cmd_details: pointer to command details structure or NULL
3099 * Stop or Shutdown the embedded LLDP Agent
3101 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3102 struct i40e_asq_cmd_details *cmd_details)
3104 struct i40e_aq_desc desc;
3105 struct i40e_aqc_lldp_stop *cmd =
3106 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3107 enum i40e_status_code status;
3109 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3112 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3114 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3120 * i40e_aq_start_lldp
3121 * @hw: pointer to the hw struct
3122 * @cmd_details: pointer to command details structure or NULL
3124 * Start the embedded LLDP Agent on all ports.
3126 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3127 struct i40e_asq_cmd_details *cmd_details)
3129 struct i40e_aq_desc desc;
3130 struct i40e_aqc_lldp_start *cmd =
3131 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3132 enum i40e_status_code status;
3134 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3136 cmd->command = I40E_AQ_LLDP_AGENT_START;
3138 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3144 * i40e_aq_add_udp_tunnel
3145 * @hw: pointer to the hw struct
3146 * @udp_port: the UDP port to add
3147 * @header_len: length of the tunneling header length in DWords
3148 * @protocol_index: protocol index type
3149 * @filter_index: pointer to filter index
3150 * @cmd_details: pointer to command details structure or NULL
3152 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3153 u16 udp_port, u8 protocol_index,
3155 struct i40e_asq_cmd_details *cmd_details)
3157 struct i40e_aq_desc desc;
3158 struct i40e_aqc_add_udp_tunnel *cmd =
3159 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3160 struct i40e_aqc_del_udp_tunnel_completion *resp =
3161 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3162 enum i40e_status_code status;
3164 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3166 cmd->udp_port = CPU_TO_LE16(udp_port);
3167 cmd->protocol_type = protocol_index;
3169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3172 *filter_index = resp->index;
3178 * i40e_aq_del_udp_tunnel
3179 * @hw: pointer to the hw struct
3180 * @index: filter index
3181 * @cmd_details: pointer to command details structure or NULL
3183 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3184 struct i40e_asq_cmd_details *cmd_details)
3186 struct i40e_aq_desc desc;
3187 struct i40e_aqc_remove_udp_tunnel *cmd =
3188 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3189 enum i40e_status_code status;
3191 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3195 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3201 * i40e_aq_get_switch_resource_alloc (0x0204)
3202 * @hw: pointer to the hw struct
3203 * @num_entries: pointer to u8 to store the number of resource entries returned
3204 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3205 * to store the resource information for all resource types. Each
3206 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3207 * @count: size, in bytes, of the buffer provided
3208 * @cmd_details: pointer to command details structure or NULL
3210 * Query the resources allocated to a function.
3212 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3214 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3216 struct i40e_asq_cmd_details *cmd_details)
3218 struct i40e_aq_desc desc;
3219 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3220 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3221 enum i40e_status_code status;
3223 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3225 i40e_fill_default_direct_cmd_desc(&desc,
3226 i40e_aqc_opc_get_switch_resource_alloc);
3228 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3229 if (length > I40E_AQ_LARGE_BUF)
3230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3232 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3235 *num_entries = cmd_resp->num_entries;
3241 * i40e_aq_delete_element - Delete switch element
3242 * @hw: pointer to the hw struct
3243 * @seid: the SEID to delete from the switch
3244 * @cmd_details: pointer to command details structure or NULL
3246 * This deletes a switch element from the switch.
3248 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3249 struct i40e_asq_cmd_details *cmd_details)
3251 struct i40e_aq_desc desc;
3252 struct i40e_aqc_switch_seid *cmd =
3253 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3254 enum i40e_status_code status;
3257 return I40E_ERR_PARAM;
3259 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3261 cmd->seid = CPU_TO_LE16(seid);
3263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3269 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3270 * @hw: pointer to the hw struct
3271 * @flags: component flags
3272 * @mac_seid: uplink seid (MAC SEID)
3273 * @vsi_seid: connected vsi seid
3274 * @ret_seid: seid of create pv component
3276 * This instantiates an i40e port virtualizer with specified flags.
3277 * Depending on specified flags the port virtualizer can act as a
3278 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3280 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3281 u16 mac_seid, u16 vsi_seid,
3284 struct i40e_aq_desc desc;
3285 struct i40e_aqc_add_update_pv *cmd =
3286 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3287 struct i40e_aqc_add_update_pv_completion *resp =
3288 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3289 enum i40e_status_code status;
3292 return I40E_ERR_PARAM;
3294 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3295 cmd->command_flags = CPU_TO_LE16(flags);
3296 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3297 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3299 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3300 if (!status && ret_seid)
3301 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3307 * i40e_aq_add_tag - Add an S/E-tag
3308 * @hw: pointer to the hw struct
3309 * @direct_to_queue: should s-tag direct flow to a specific queue
3310 * @vsi_seid: VSI SEID to use this tag
3311 * @tag: value of the tag
3312 * @queue_num: queue number, only valid is direct_to_queue is true
3313 * @tags_used: return value, number of tags in use by this PF
3314 * @tags_free: return value, number of unallocated tags
3315 * @cmd_details: pointer to command details structure or NULL
3317 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3318 * the number of tags allocated by the PF, and the number of unallocated
3321 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3322 u16 vsi_seid, u16 tag, u16 queue_num,
3323 u16 *tags_used, u16 *tags_free,
3324 struct i40e_asq_cmd_details *cmd_details)
3326 struct i40e_aq_desc desc;
3327 struct i40e_aqc_add_tag *cmd =
3328 (struct i40e_aqc_add_tag *)&desc.params.raw;
3329 struct i40e_aqc_add_remove_tag_completion *resp =
3330 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3331 enum i40e_status_code status;
3334 return I40E_ERR_PARAM;
3336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3338 cmd->seid = CPU_TO_LE16(vsi_seid);
3339 cmd->tag = CPU_TO_LE16(tag);
3340 if (direct_to_queue) {
3341 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3342 cmd->queue_number = CPU_TO_LE16(queue_num);
3345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3348 if (tags_used != NULL)
3349 *tags_used = LE16_TO_CPU(resp->tags_used);
3350 if (tags_free != NULL)
3351 *tags_free = LE16_TO_CPU(resp->tags_free);
3358 * i40e_aq_remove_tag - Remove an S- or E-tag
3359 * @hw: pointer to the hw struct
3360 * @vsi_seid: VSI SEID this tag is associated with
3361 * @tag: value of the S-tag to delete
3362 * @tags_used: return value, number of tags in use by this PF
3363 * @tags_free: return value, number of unallocated tags
3364 * @cmd_details: pointer to command details structure or NULL
3366 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3367 * the number of tags allocated by the PF, and the number of unallocated
3370 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3371 u16 tag, u16 *tags_used, u16 *tags_free,
3372 struct i40e_asq_cmd_details *cmd_details)
3374 struct i40e_aq_desc desc;
3375 struct i40e_aqc_remove_tag *cmd =
3376 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3377 struct i40e_aqc_add_remove_tag_completion *resp =
3378 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3379 enum i40e_status_code status;
3382 return I40E_ERR_PARAM;
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3386 cmd->seid = CPU_TO_LE16(vsi_seid);
3387 cmd->tag = CPU_TO_LE16(tag);
3389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3392 if (tags_used != NULL)
3393 *tags_used = LE16_TO_CPU(resp->tags_used);
3394 if (tags_free != NULL)
3395 *tags_free = LE16_TO_CPU(resp->tags_free);
3402 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3403 * @hw: pointer to the hw struct
3404 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3405 * @etag: value of E-tag to add
3406 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3407 * @buf: address of indirect buffer
3408 * @tags_used: return value, number of E-tags in use by this port
3409 * @tags_free: return value, number of unallocated M-tags
3410 * @cmd_details: pointer to command details structure or NULL
3412 * This associates a multicast E-tag to a port virtualizer. It will return
3413 * the number of tags allocated by the PF, and the number of unallocated
3416 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3417 * num_tags_in_buf long.
3419 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3420 u16 etag, u8 num_tags_in_buf, void *buf,
3421 u16 *tags_used, u16 *tags_free,
3422 struct i40e_asq_cmd_details *cmd_details)
3424 struct i40e_aq_desc desc;
3425 struct i40e_aqc_add_remove_mcast_etag *cmd =
3426 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3427 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3428 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3429 enum i40e_status_code status;
3430 u16 length = sizeof(u16) * num_tags_in_buf;
3432 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3433 return I40E_ERR_PARAM;
3435 i40e_fill_default_direct_cmd_desc(&desc,
3436 i40e_aqc_opc_add_multicast_etag);
3438 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3439 cmd->etag = CPU_TO_LE16(etag);
3440 cmd->num_unicast_etags = num_tags_in_buf;
3442 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3443 if (length > I40E_AQ_LARGE_BUF)
3444 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3446 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3449 if (tags_used != NULL)
3450 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3451 if (tags_free != NULL)
3452 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3459 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3460 * @hw: pointer to the hw struct
3461 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3462 * @etag: value of the E-tag to remove
3463 * @tags_used: return value, number of tags in use by this port
3464 * @tags_free: return value, number of unallocated tags
3465 * @cmd_details: pointer to command details structure or NULL
3467 * This deletes an E-tag from the port virtualizer. It will return
3468 * the number of tags allocated by the port, and the number of unallocated
3471 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3472 u16 etag, u16 *tags_used, u16 *tags_free,
3473 struct i40e_asq_cmd_details *cmd_details)
3475 struct i40e_aq_desc desc;
3476 struct i40e_aqc_add_remove_mcast_etag *cmd =
3477 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3478 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3479 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3480 enum i40e_status_code status;
3484 return I40E_ERR_PARAM;
3486 i40e_fill_default_direct_cmd_desc(&desc,
3487 i40e_aqc_opc_remove_multicast_etag);
3489 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3490 cmd->etag = CPU_TO_LE16(etag);
3492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3495 if (tags_used != NULL)
3496 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3497 if (tags_free != NULL)
3498 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3505 * i40e_aq_update_tag - Update an S/E-tag
3506 * @hw: pointer to the hw struct
3507 * @vsi_seid: VSI SEID using this S-tag
3508 * @old_tag: old tag value
3509 * @new_tag: new tag value
3510 * @tags_used: return value, number of tags in use by this PF
3511 * @tags_free: return value, number of unallocated tags
3512 * @cmd_details: pointer to command details structure or NULL
3514 * This updates the value of the tag currently attached to this VSI
3515 * in the switch complex. It will return the number of tags allocated
3516 * by the PF, and the number of unallocated tags available.
3518 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3519 u16 old_tag, u16 new_tag, u16 *tags_used,
3521 struct i40e_asq_cmd_details *cmd_details)
3523 struct i40e_aq_desc desc;
3524 struct i40e_aqc_update_tag *cmd =
3525 (struct i40e_aqc_update_tag *)&desc.params.raw;
3526 struct i40e_aqc_update_tag_completion *resp =
3527 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3528 enum i40e_status_code status;
3531 return I40E_ERR_PARAM;
3533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3535 cmd->seid = CPU_TO_LE16(vsi_seid);
3536 cmd->old_tag = CPU_TO_LE16(old_tag);
3537 cmd->new_tag = CPU_TO_LE16(new_tag);
3539 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3542 if (tags_used != NULL)
3543 *tags_used = LE16_TO_CPU(resp->tags_used);
3544 if (tags_free != NULL)
3545 *tags_free = LE16_TO_CPU(resp->tags_free);
3552 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3553 * @hw: pointer to the hw struct
3554 * @tcmap: TC map for request/release any ignore PFC condition
3555 * @request: request or release ignore PFC condition
3556 * @tcmap_ret: return TCs for which PFC is currently ignored
3557 * @cmd_details: pointer to command details structure or NULL
3559 * This sends out request/release to ignore PFC condition for a TC.
3560 * It will return the TCs for which PFC is currently ignored.
3562 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3563 bool request, u8 *tcmap_ret,
3564 struct i40e_asq_cmd_details *cmd_details)
3566 struct i40e_aq_desc desc;
3567 struct i40e_aqc_pfc_ignore *cmd_resp =
3568 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3569 enum i40e_status_code status;
3571 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3574 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3576 cmd_resp->tc_bitmap = tcmap;
3578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3581 if (tcmap_ret != NULL)
3582 *tcmap_ret = cmd_resp->tc_bitmap;
3589 * i40e_aq_dcb_updated - DCB Updated Command
3590 * @hw: pointer to the hw struct
3591 * @cmd_details: pointer to command details structure or NULL
3593 * When LLDP is handled in PF this command is used by the PF
3594 * to notify EMP that a DCB setting is modified.
3595 * When LLDP is handled in EMP this command is used by the PF
3596 * to notify EMP whenever one of the following parameters get
3598 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3599 * - PCIRTT in PRTDCB_GENC.PCIRTT
3600 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3601 * EMP will return when the shared RPB settings have been
3602 * recomputed and modified. The retval field in the descriptor
3603 * will be set to 0 when RPB is modified.
3605 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3606 struct i40e_asq_cmd_details *cmd_details)
3608 struct i40e_aq_desc desc;
3609 enum i40e_status_code status;
3611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3613 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3619 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3620 * @hw: pointer to the hw struct
3621 * @seid: defines the SEID of the switch for which the stats are requested
3622 * @vlan_id: the VLAN ID for which the statistics are requested
3623 * @stat_index: index of the statistics counters block assigned to this VLAN
3624 * @cmd_details: pointer to command details structure or NULL
3626 * XL710 supports 128 smonVlanStats counters.This command is used to
3627 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3630 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3631 u16 vlan_id, u16 *stat_index,
3632 struct i40e_asq_cmd_details *cmd_details)
3634 struct i40e_aq_desc desc;
3635 struct i40e_aqc_add_remove_statistics *cmd_resp =
3636 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3637 enum i40e_status_code status;
3639 if ((seid == 0) || (stat_index == NULL))
3640 return I40E_ERR_PARAM;
3642 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3644 cmd_resp->seid = CPU_TO_LE16(seid);
3645 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3650 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3656 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3657 * @hw: pointer to the hw struct
3658 * @seid: defines the SEID of the switch for which the stats are requested
3659 * @vlan_id: the VLAN ID for which the statistics are requested
3660 * @stat_index: index of the statistics counters block assigned to this VLAN
3661 * @cmd_details: pointer to command details structure or NULL
3663 * XL710 supports 128 smonVlanStats counters.This command is used to
3664 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3667 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3668 u16 vlan_id, u16 stat_index,
3669 struct i40e_asq_cmd_details *cmd_details)
3671 struct i40e_aq_desc desc;
3672 struct i40e_aqc_add_remove_statistics *cmd =
3673 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3674 enum i40e_status_code status;
3677 return I40E_ERR_PARAM;
3679 i40e_fill_default_direct_cmd_desc(&desc,
3680 i40e_aqc_opc_remove_statistics);
3682 cmd->seid = CPU_TO_LE16(seid);
3683 cmd->vlan = CPU_TO_LE16(vlan_id);
3684 cmd->stat_index = CPU_TO_LE16(stat_index);
3686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3692 * i40e_aq_set_port_parameters - set physical port parameters.
3693 * @hw: pointer to the hw struct
3694 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3695 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3696 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3697 * @double_vlan: if set double VLAN is enabled
3698 * @cmd_details: pointer to command details structure or NULL
3700 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3701 u16 bad_frame_vsi, bool save_bad_pac,
3702 bool pad_short_pac, bool double_vlan,
3703 struct i40e_asq_cmd_details *cmd_details)
3705 struct i40e_aqc_set_port_parameters *cmd;
3706 enum i40e_status_code status;
3707 struct i40e_aq_desc desc;
3708 u16 command_flags = 0;
3710 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3712 i40e_fill_default_direct_cmd_desc(&desc,
3713 i40e_aqc_opc_set_port_parameters);
3715 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3717 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3719 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3721 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3722 cmd->command_flags = CPU_TO_LE16(command_flags);
3724 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3730 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3731 * @hw: pointer to the hw struct
3732 * @seid: seid for the physical port/switching component/vsi
3733 * @buff: Indirect buffer to hold data parameters and response
3734 * @buff_size: Indirect buffer size
3735 * @opcode: Tx scheduler AQ command opcode
3736 * @cmd_details: pointer to command details structure or NULL
3738 * Generic command handler for Tx scheduler AQ commands
3740 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3741 void *buff, u16 buff_size,
3742 enum i40e_admin_queue_opc opcode,
3743 struct i40e_asq_cmd_details *cmd_details)
3745 struct i40e_aq_desc desc;
3746 struct i40e_aqc_tx_sched_ind *cmd =
3747 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3748 enum i40e_status_code status;
3749 bool cmd_param_flag = false;
3752 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3753 case i40e_aqc_opc_configure_vsi_tc_bw:
3754 case i40e_aqc_opc_enable_switching_comp_ets:
3755 case i40e_aqc_opc_modify_switching_comp_ets:
3756 case i40e_aqc_opc_disable_switching_comp_ets:
3757 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3758 case i40e_aqc_opc_configure_switching_comp_bw_config:
3759 cmd_param_flag = true;
3761 case i40e_aqc_opc_query_vsi_bw_config:
3762 case i40e_aqc_opc_query_vsi_ets_sla_config:
3763 case i40e_aqc_opc_query_switching_comp_ets_config:
3764 case i40e_aqc_opc_query_port_ets_config:
3765 case i40e_aqc_opc_query_switching_comp_bw_config:
3766 cmd_param_flag = false;
3769 return I40E_ERR_PARAM;
3772 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3774 /* Indirect command */
3775 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3778 if (buff_size > I40E_AQ_LARGE_BUF)
3779 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3781 desc.datalen = CPU_TO_LE16(buff_size);
3783 cmd->vsi_seid = CPU_TO_LE16(seid);
3785 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3791 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3792 * @hw: pointer to the hw struct
3794 * @credit: BW limit credits (0 = disabled)
3795 * @max_credit: Max BW limit credits
3796 * @cmd_details: pointer to command details structure or NULL
3798 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3799 u16 seid, u16 credit, u8 max_credit,
3800 struct i40e_asq_cmd_details *cmd_details)
3802 struct i40e_aq_desc desc;
3803 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3804 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3805 enum i40e_status_code status;
3807 i40e_fill_default_direct_cmd_desc(&desc,
3808 i40e_aqc_opc_configure_vsi_bw_limit);
3810 cmd->vsi_seid = CPU_TO_LE16(seid);
3811 cmd->credit = CPU_TO_LE16(credit);
3812 cmd->max_credit = max_credit;
3814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3820 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3821 * @hw: pointer to the hw struct
3822 * @seid: switching component seid
3823 * @credit: BW limit credits (0 = disabled)
3824 * @max_bw: Max BW limit credits
3825 * @cmd_details: pointer to command details structure or NULL
3827 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3828 u16 seid, u16 credit, u8 max_bw,
3829 struct i40e_asq_cmd_details *cmd_details)
3831 struct i40e_aq_desc desc;
3832 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3833 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3834 enum i40e_status_code status;
3836 i40e_fill_default_direct_cmd_desc(&desc,
3837 i40e_aqc_opc_configure_switching_comp_bw_limit);
3839 cmd->seid = CPU_TO_LE16(seid);
3840 cmd->credit = CPU_TO_LE16(credit);
3841 cmd->max_bw = max_bw;
3843 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3849 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3850 * @hw: pointer to the hw struct
3852 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3853 * @cmd_details: pointer to command details structure or NULL
3855 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3857 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3858 struct i40e_asq_cmd_details *cmd_details)
3860 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3861 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3866 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3867 * @hw: pointer to the hw struct
3869 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3870 * @cmd_details: pointer to command details structure or NULL
3872 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3874 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3875 struct i40e_asq_cmd_details *cmd_details)
3877 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3878 i40e_aqc_opc_configure_vsi_tc_bw,
3883 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
3884 * @hw: pointer to the hw struct
3885 * @seid: seid of the switching component
3886 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3887 * @cmd_details: pointer to command details structure or NULL
3889 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
3890 struct i40e_hw *hw, u16 seid,
3891 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
3892 struct i40e_asq_cmd_details *cmd_details)
3894 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3895 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
3900 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3901 * @hw: pointer to the hw struct
3902 * @seid: seid of the VSI
3903 * @bw_data: Buffer to hold VSI BW configuration
3904 * @cmd_details: pointer to command details structure or NULL
3906 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3908 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3909 struct i40e_asq_cmd_details *cmd_details)
3911 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3912 i40e_aqc_opc_query_vsi_bw_config,
3917 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3918 * @hw: pointer to the hw struct
3919 * @seid: seid of the VSI
3920 * @bw_data: Buffer to hold VSI BW configuration per TC
3921 * @cmd_details: pointer to command details structure or NULL
3923 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3925 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3926 struct i40e_asq_cmd_details *cmd_details)
3928 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3929 i40e_aqc_opc_query_vsi_ets_sla_config,
3934 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3935 * @hw: pointer to the hw struct
3936 * @seid: seid of the switching component
3937 * @bw_data: Buffer to hold switching component's per TC BW config
3938 * @cmd_details: pointer to command details structure or NULL
3940 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3942 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3943 struct i40e_asq_cmd_details *cmd_details)
3945 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3946 i40e_aqc_opc_query_switching_comp_ets_config,
3951 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3952 * @hw: pointer to the hw struct
3953 * @seid: seid of the VSI or switching component connected to Physical Port
3954 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3955 * @cmd_details: pointer to command details structure or NULL
3957 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3959 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3960 struct i40e_asq_cmd_details *cmd_details)
3962 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3963 i40e_aqc_opc_query_port_ets_config,
3968 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3969 * @hw: pointer to the hw struct
3970 * @seid: seid of the switching component
3971 * @bw_data: Buffer to hold switching component's BW configuration
3972 * @cmd_details: pointer to command details structure or NULL
3974 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3976 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3977 struct i40e_asq_cmd_details *cmd_details)
3979 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3980 i40e_aqc_opc_query_switching_comp_bw_config,
3985 * i40e_validate_filter_settings
3986 * @hw: pointer to the hardware structure
3987 * @settings: Filter control settings
3989 * Check and validate the filter control settings passed.
3990 * The function checks for the valid filter/context sizes being
3991 * passed for FCoE and PE.
3993 * Returns I40E_SUCCESS if the values passed are valid and within
3994 * range else returns an error.
3996 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
3997 struct i40e_filter_control_settings *settings)
3999 u32 fcoe_cntx_size, fcoe_filt_size;
4000 u32 pe_cntx_size, pe_filt_size;
4005 /* Validate FCoE settings passed */
4006 switch (settings->fcoe_filt_num) {
4007 case I40E_HASH_FILTER_SIZE_1K:
4008 case I40E_HASH_FILTER_SIZE_2K:
4009 case I40E_HASH_FILTER_SIZE_4K:
4010 case I40E_HASH_FILTER_SIZE_8K:
4011 case I40E_HASH_FILTER_SIZE_16K:
4012 case I40E_HASH_FILTER_SIZE_32K:
4013 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4014 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4017 return I40E_ERR_PARAM;
4020 switch (settings->fcoe_cntx_num) {
4021 case I40E_DMA_CNTX_SIZE_512:
4022 case I40E_DMA_CNTX_SIZE_1K:
4023 case I40E_DMA_CNTX_SIZE_2K:
4024 case I40E_DMA_CNTX_SIZE_4K:
4025 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4026 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4029 return I40E_ERR_PARAM;
4032 /* Validate PE settings passed */
4033 switch (settings->pe_filt_num) {
4034 case I40E_HASH_FILTER_SIZE_1K:
4035 case I40E_HASH_FILTER_SIZE_2K:
4036 case I40E_HASH_FILTER_SIZE_4K:
4037 case I40E_HASH_FILTER_SIZE_8K:
4038 case I40E_HASH_FILTER_SIZE_16K:
4039 case I40E_HASH_FILTER_SIZE_32K:
4040 case I40E_HASH_FILTER_SIZE_64K:
4041 case I40E_HASH_FILTER_SIZE_128K:
4042 case I40E_HASH_FILTER_SIZE_256K:
4043 case I40E_HASH_FILTER_SIZE_512K:
4044 case I40E_HASH_FILTER_SIZE_1M:
4045 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4046 pe_filt_size <<= (u32)settings->pe_filt_num;
4049 return I40E_ERR_PARAM;
4052 switch (settings->pe_cntx_num) {
4053 case I40E_DMA_CNTX_SIZE_512:
4054 case I40E_DMA_CNTX_SIZE_1K:
4055 case I40E_DMA_CNTX_SIZE_2K:
4056 case I40E_DMA_CNTX_SIZE_4K:
4057 case I40E_DMA_CNTX_SIZE_8K:
4058 case I40E_DMA_CNTX_SIZE_16K:
4059 case I40E_DMA_CNTX_SIZE_32K:
4060 case I40E_DMA_CNTX_SIZE_64K:
4061 case I40E_DMA_CNTX_SIZE_128K:
4062 case I40E_DMA_CNTX_SIZE_256K:
4063 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4064 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4067 return I40E_ERR_PARAM;
4070 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4071 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4072 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4073 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4074 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4075 return I40E_ERR_INVALID_SIZE;
4077 return I40E_SUCCESS;
4081 * i40e_set_filter_control
4082 * @hw: pointer to the hardware structure
4083 * @settings: Filter control settings
4085 * Set the Queue Filters for PE/FCoE and enable filters required
4086 * for a single PF. It is expected that these settings are programmed
4087 * at the driver initialization time.
4089 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4090 struct i40e_filter_control_settings *settings)
4092 enum i40e_status_code ret = I40E_SUCCESS;
4093 u32 hash_lut_size = 0;
4097 return I40E_ERR_PARAM;
4099 /* Validate the input settings */
4100 ret = i40e_validate_filter_settings(hw, settings);
4104 /* Read the PF Queue Filter control register */
4105 val = rd32(hw, I40E_PFQF_CTL_0);
4107 /* Program required PE hash buckets for the PF */
4108 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4109 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4110 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4111 /* Program required PE contexts for the PF */
4112 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4113 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4114 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4116 /* Program required FCoE hash buckets for the PF */
4117 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4118 val |= ((u32)settings->fcoe_filt_num <<
4119 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4120 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4121 /* Program required FCoE DDP contexts for the PF */
4122 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4123 val |= ((u32)settings->fcoe_cntx_num <<
4124 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4125 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4127 /* Program Hash LUT size for the PF */
4128 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4129 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4131 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4132 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4134 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4135 if (settings->enable_fdir)
4136 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4137 if (settings->enable_ethtype)
4138 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4139 if (settings->enable_macvlan)
4140 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4142 wr32(hw, I40E_PFQF_CTL_0, val);
4144 return I40E_SUCCESS;
4148 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4149 * @hw: pointer to the hw struct
4150 * @mac_addr: MAC address to use in the filter
4151 * @ethtype: Ethertype to use in the filter
4152 * @flags: Flags that needs to be applied to the filter
4153 * @vsi_seid: seid of the control VSI
4154 * @queue: VSI queue number to send the packet to
4155 * @is_add: Add control packet filter if True else remove
4156 * @stats: Structure to hold information on control filter counts
4157 * @cmd_details: pointer to command details structure or NULL
4159 * This command will Add or Remove control packet filter for a control VSI.
4160 * In return it will update the total number of perfect filter count in
4163 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4164 u8 *mac_addr, u16 ethtype, u16 flags,
4165 u16 vsi_seid, u16 queue, bool is_add,
4166 struct i40e_control_filter_stats *stats,
4167 struct i40e_asq_cmd_details *cmd_details)
4169 struct i40e_aq_desc desc;
4170 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4171 (struct i40e_aqc_add_remove_control_packet_filter *)
4173 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4174 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4176 enum i40e_status_code status;
4179 return I40E_ERR_PARAM;
4182 i40e_fill_default_direct_cmd_desc(&desc,
4183 i40e_aqc_opc_add_control_packet_filter);
4184 cmd->queue = CPU_TO_LE16(queue);
4186 i40e_fill_default_direct_cmd_desc(&desc,
4187 i40e_aqc_opc_remove_control_packet_filter);
4191 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4192 I40E_NONDMA_TO_NONDMA);
4194 cmd->etype = CPU_TO_LE16(ethtype);
4195 cmd->flags = CPU_TO_LE16(flags);
4196 cmd->seid = CPU_TO_LE16(vsi_seid);
4198 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4200 if (!status && stats) {
4201 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4202 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4203 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4204 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4211 * i40e_aq_add_cloud_filters
4212 * @hw: pointer to the hardware structure
4213 * @seid: VSI seid to add cloud filters from
4214 * @filters: Buffer which contains the filters to be added
4215 * @filter_count: number of filters contained in the buffer
4217 * Set the cloud filters for a given VSI. The contents of the
4218 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4219 * in by the caller of the function.
4222 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4224 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4227 struct i40e_aq_desc desc;
4228 struct i40e_aqc_add_remove_cloud_filters *cmd =
4229 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4231 enum i40e_status_code status;
4233 i40e_fill_default_direct_cmd_desc(&desc,
4234 i40e_aqc_opc_add_cloud_filters);
4236 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4238 desc.datalen = CPU_TO_LE16(buff_len);
4239 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4240 cmd->num_filters = filter_count;
4241 cmd->seid = CPU_TO_LE16(seid);
4243 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4249 * i40e_aq_remove_cloud_filters
4250 * @hw: pointer to the hardware structure
4251 * @seid: VSI seid to remove cloud filters from
4252 * @filters: Buffer which contains the filters to be removed
4253 * @filter_count: number of filters contained in the buffer
4255 * Remove the cloud filters for a given VSI. The contents of the
4256 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4257 * in by the caller of the function.
4260 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4262 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4265 struct i40e_aq_desc desc;
4266 struct i40e_aqc_add_remove_cloud_filters *cmd =
4267 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4268 enum i40e_status_code status;
4271 i40e_fill_default_direct_cmd_desc(&desc,
4272 i40e_aqc_opc_remove_cloud_filters);
4274 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4276 desc.datalen = CPU_TO_LE16(buff_len);
4277 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4278 cmd->num_filters = filter_count;
4279 cmd->seid = CPU_TO_LE16(seid);
4281 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4287 * i40e_aq_alternate_write
4288 * @hw: pointer to the hardware structure
4289 * @reg_addr0: address of first dword to be read
4290 * @reg_val0: value to be written under 'reg_addr0'
4291 * @reg_addr1: address of second dword to be read
4292 * @reg_val1: value to be written under 'reg_addr1'
4294 * Write one or two dwords to alternate structure. Fields are indicated
4295 * by 'reg_addr0' and 'reg_addr1' register numbers.
4298 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4299 u32 reg_addr0, u32 reg_val0,
4300 u32 reg_addr1, u32 reg_val1)
4302 struct i40e_aq_desc desc;
4303 struct i40e_aqc_alternate_write *cmd_resp =
4304 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4305 enum i40e_status_code status;
4307 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4308 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4309 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4310 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4311 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4313 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4319 * i40e_aq_alternate_write_indirect
4320 * @hw: pointer to the hardware structure
4321 * @addr: address of a first register to be modified
4322 * @dw_count: number of alternate structure fields to write
4323 * @buffer: pointer to the command buffer
4325 * Write 'dw_count' dwords from 'buffer' to alternate structure
4326 * starting at 'addr'.
4329 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4330 u32 addr, u32 dw_count, void *buffer)
4332 struct i40e_aq_desc desc;
4333 struct i40e_aqc_alternate_ind_write *cmd_resp =
4334 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4335 enum i40e_status_code status;
4338 return I40E_ERR_PARAM;
4340 /* Indirect command */
4341 i40e_fill_default_direct_cmd_desc(&desc,
4342 i40e_aqc_opc_alternate_write_indirect);
4344 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4345 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4346 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4347 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4349 cmd_resp->address = CPU_TO_LE32(addr);
4350 cmd_resp->length = CPU_TO_LE32(dw_count);
4351 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4352 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4354 status = i40e_asq_send_command(hw, &desc, buffer,
4355 I40E_LO_DWORD(4*dw_count), NULL);
4361 * i40e_aq_alternate_read
4362 * @hw: pointer to the hardware structure
4363 * @reg_addr0: address of first dword to be read
4364 * @reg_val0: pointer for data read from 'reg_addr0'
4365 * @reg_addr1: address of second dword to be read
4366 * @reg_val1: pointer for data read from 'reg_addr1'
4368 * Read one or two dwords from alternate structure. Fields are indicated
4369 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4370 * is not passed then only register at 'reg_addr0' is read.
4373 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4374 u32 reg_addr0, u32 *reg_val0,
4375 u32 reg_addr1, u32 *reg_val1)
4377 struct i40e_aq_desc desc;
4378 struct i40e_aqc_alternate_write *cmd_resp =
4379 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4380 enum i40e_status_code status;
4382 if (reg_val0 == NULL)
4383 return I40E_ERR_PARAM;
4385 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4386 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4387 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4389 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4391 if (status == I40E_SUCCESS) {
4392 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4394 if (reg_val1 != NULL)
4395 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4402 * i40e_aq_alternate_read_indirect
4403 * @hw: pointer to the hardware structure
4404 * @addr: address of the alternate structure field
4405 * @dw_count: number of alternate structure fields to read
4406 * @buffer: pointer to the command buffer
4408 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4409 * place them in 'buffer'. The buffer should be allocated by caller.
4412 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4413 u32 addr, u32 dw_count, void *buffer)
4415 struct i40e_aq_desc desc;
4416 struct i40e_aqc_alternate_ind_write *cmd_resp =
4417 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4418 enum i40e_status_code status;
4421 return I40E_ERR_PARAM;
4423 /* Indirect command */
4424 i40e_fill_default_direct_cmd_desc(&desc,
4425 i40e_aqc_opc_alternate_read_indirect);
4427 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4428 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4429 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4430 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4432 cmd_resp->address = CPU_TO_LE32(addr);
4433 cmd_resp->length = CPU_TO_LE32(dw_count);
4434 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4435 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4437 status = i40e_asq_send_command(hw, &desc, buffer,
4438 I40E_LO_DWORD(4*dw_count), NULL);
4444 * i40e_aq_alternate_clear
4445 * @hw: pointer to the HW structure.
4447 * Clear the alternate structures of the port from which the function
4451 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4453 struct i40e_aq_desc desc;
4454 enum i40e_status_code status;
4456 i40e_fill_default_direct_cmd_desc(&desc,
4457 i40e_aqc_opc_alternate_clear_port);
4459 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4465 * i40e_aq_alternate_write_done
4466 * @hw: pointer to the HW structure.
4467 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4468 * @reset_needed: indicates the SW should trigger GLOBAL reset
4470 * Indicates to the FW that alternate structures have been changed.
4473 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4474 u8 bios_mode, bool *reset_needed)
4476 struct i40e_aq_desc desc;
4477 struct i40e_aqc_alternate_write_done *cmd =
4478 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4479 enum i40e_status_code status;
4481 if (reset_needed == NULL)
4482 return I40E_ERR_PARAM;
4484 i40e_fill_default_direct_cmd_desc(&desc,
4485 i40e_aqc_opc_alternate_write_done);
4487 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4489 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4491 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4492 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4498 * i40e_aq_set_oem_mode
4499 * @hw: pointer to the HW structure.
4500 * @oem_mode: the OEM mode to be used
4502 * Sets the device to a specific operating mode. Currently the only supported
4503 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4506 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4509 struct i40e_aq_desc desc;
4510 struct i40e_aqc_alternate_write_done *cmd =
4511 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4512 enum i40e_status_code status;
4514 i40e_fill_default_direct_cmd_desc(&desc,
4515 i40e_aqc_opc_alternate_set_mode);
4517 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4519 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4525 * i40e_aq_resume_port_tx
4526 * @hw: pointer to the hardware structure
4527 * @cmd_details: pointer to command details structure or NULL
4529 * Resume port's Tx traffic
4531 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4532 struct i40e_asq_cmd_details *cmd_details)
4534 struct i40e_aq_desc desc;
4535 enum i40e_status_code status;
4537 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4539 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4545 * i40e_set_pci_config_data - store PCI bus info
4546 * @hw: pointer to hardware structure
4547 * @link_status: the link status word from PCI config space
4549 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4551 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4553 hw->bus.type = i40e_bus_type_pci_express;
4555 switch (link_status & I40E_PCI_LINK_WIDTH) {
4556 case I40E_PCI_LINK_WIDTH_1:
4557 hw->bus.width = i40e_bus_width_pcie_x1;
4559 case I40E_PCI_LINK_WIDTH_2:
4560 hw->bus.width = i40e_bus_width_pcie_x2;
4562 case I40E_PCI_LINK_WIDTH_4:
4563 hw->bus.width = i40e_bus_width_pcie_x4;
4565 case I40E_PCI_LINK_WIDTH_8:
4566 hw->bus.width = i40e_bus_width_pcie_x8;
4569 hw->bus.width = i40e_bus_width_unknown;
4573 switch (link_status & I40E_PCI_LINK_SPEED) {
4574 case I40E_PCI_LINK_SPEED_2500:
4575 hw->bus.speed = i40e_bus_speed_2500;
4577 case I40E_PCI_LINK_SPEED_5000:
4578 hw->bus.speed = i40e_bus_speed_5000;
4580 case I40E_PCI_LINK_SPEED_8000:
4581 hw->bus.speed = i40e_bus_speed_8000;
4584 hw->bus.speed = i40e_bus_speed_unknown;
4590 * i40e_read_bw_from_alt_ram
4591 * @hw: pointer to the hardware structure
4592 * @max_bw: pointer for max_bw read
4593 * @min_bw: pointer for min_bw read
4594 * @min_valid: pointer for bool that is true if min_bw is a valid value
4595 * @max_valid: pointer for bool that is true if max_bw is a valid value
4597 * Read bw from the alternate ram for the given pf
4599 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4600 u32 *max_bw, u32 *min_bw,
4601 bool *min_valid, bool *max_valid)
4603 enum i40e_status_code status;
4604 u32 max_bw_addr, min_bw_addr;
4606 /* Calculate the address of the min/max bw registers */
4607 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4608 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4609 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4610 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4611 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4612 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4614 /* Read the bandwidths from alt ram */
4615 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4616 min_bw_addr, min_bw);
4618 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4623 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4632 * i40e_aq_configure_partition_bw
4633 * @hw: pointer to the hardware structure
4634 * @bw_data: Buffer holding valid pfs and bw limits
4635 * @cmd_details: pointer to command details
4637 * Configure partitions guaranteed/max bw
4639 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4640 struct i40e_aqc_configure_partition_bw_data *bw_data,
4641 struct i40e_asq_cmd_details *cmd_details)
4643 enum i40e_status_code status;
4644 struct i40e_aq_desc desc;
4645 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4647 i40e_fill_default_direct_cmd_desc(&desc,
4648 i40e_aqc_opc_configure_partition_bw);
4650 /* Indirect command */
4651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4652 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4654 if (bwd_size > I40E_AQ_LARGE_BUF)
4655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4657 desc.datalen = CPU_TO_LE16(bwd_size);
4659 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4665 * i40e_aq_send_msg_to_pf
4666 * @hw: pointer to the hardware structure
4667 * @v_opcode: opcodes for VF-PF communication
4668 * @v_retval: return error code
4669 * @msg: pointer to the msg buffer
4670 * @msglen: msg length
4671 * @cmd_details: pointer to command details
4673 * Send message to PF driver using admin queue. By default, this message
4674 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4675 * completion before returning.
4677 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4678 enum i40e_virtchnl_ops v_opcode,
4679 enum i40e_status_code v_retval,
4680 u8 *msg, u16 msglen,
4681 struct i40e_asq_cmd_details *cmd_details)
4683 struct i40e_aq_desc desc;
4684 enum i40e_status_code status;
4686 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4687 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4688 desc.cookie_high = CPU_TO_LE32(v_opcode);
4689 desc.cookie_low = CPU_TO_LE32(v_retval);
4691 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4692 | I40E_AQ_FLAG_RD));
4693 if (msglen > I40E_AQ_LARGE_BUF)
4694 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4695 desc.datalen = CPU_TO_LE16(msglen);
4698 struct i40e_asq_cmd_details details;
4699 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4700 details.async = true;
4701 cmd_details = &details;
4703 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4704 msglen, cmd_details);
4709 * i40e_vf_parse_hw_config
4710 * @hw: pointer to the hardware structure
4711 * @msg: pointer to the virtual channel VF resource structure
4713 * Given a VF resource message from the PF, populate the hw struct
4714 * with appropriate information.
4716 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4717 struct i40e_virtchnl_vf_resource *msg)
4719 struct i40e_virtchnl_vsi_resource *vsi_res;
4722 vsi_res = &msg->vsi_res[0];
4724 hw->dev_caps.num_vsis = msg->num_vsis;
4725 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4726 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4727 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4728 hw->dev_caps.dcb = msg->vf_offload_flags &
4729 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4730 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4731 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4732 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4733 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4734 for (i = 0; i < msg->num_vsis; i++) {
4735 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4736 i40e_memcpy(hw->mac.perm_addr,
4737 vsi_res->default_mac_addr,
4738 I40E_ETH_LENGTH_OF_ADDRESS,
4739 I40E_NONDMA_TO_NONDMA);
4740 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4741 I40E_ETH_LENGTH_OF_ADDRESS,
4742 I40E_NONDMA_TO_NONDMA);
4750 * @hw: pointer to the hardware structure
4752 * Send a VF_RESET message to the PF. Does not wait for response from PF
4753 * as none will be forthcoming. Immediately after calling this function,
4754 * the admin queue should be shut down and (optionally) reinitialized.
4756 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4758 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4759 I40E_SUCCESS, NULL, 0, NULL);
4761 #endif /* VF_DRIVER */