1 /*******************************************************************************
3 Copyright (c) 2013 - 2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 hw->mac.type = I40E_MAC_XL710;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
87 * @hw: debug mask related to admin queue
89 * @desc: pointer to admin queue descriptor
90 * @buffer: pointer to command buffer
92 * Dumps debug log about adminq command with descriptor contents.
94 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
98 u8 *aq_buffer = (u8 *)buffer;
102 if ((!(mask & hw->debug_mask)) || (desc == NULL))
106 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
107 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
109 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
110 aq_desc->cookie_high, aq_desc->cookie_low);
111 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
112 aq_desc->params.internal.param0,
113 aq_desc->params.internal.param1);
114 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
115 aq_desc->params.external.addr_high,
116 aq_desc->params.external.addr_low);
118 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
119 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
120 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
121 for (i = 0; i < LE16_TO_CPU(aq_desc->datalen); i++) {
122 data[((i % 16) / 4)] |=
123 ((u32)aq_buffer[i]) << (8 * (i % 4));
124 if ((i % 16) == 15) {
126 "\t0x%04X %08X %08X %08X %08X\n",
127 i - 15, data[0], data[1], data[2],
129 i40e_memset(data, 0, sizeof(data),
134 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
135 i - (i % 16), data[0], data[1], data[2],
141 * i40e_check_asq_alive
142 * @hw: pointer to the hw struct
144 * Returns true if Queue is enabled else false.
146 bool i40e_check_asq_alive(struct i40e_hw *hw)
149 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
155 * i40e_aq_queue_shutdown
156 * @hw: pointer to the hw struct
157 * @unloading: is the driver unloading itself
159 * Tell the Firmware that we're shutting down the AdminQ and whether
160 * or not the driver is unloading as well.
162 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
165 struct i40e_aq_desc desc;
166 struct i40e_aqc_queue_shutdown *cmd =
167 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
168 enum i40e_status_code status;
170 i40e_fill_default_direct_cmd_desc(&desc,
171 i40e_aqc_opc_queue_shutdown);
174 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
175 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
180 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
181 * hardware to a bit-field that can be used by SW to more easily determine the
184 * Macros are used to shorten the table lines and make this table human
187 * We store the PTYPE in the top byte of the bit field - this is just so that
188 * we can check that the table doesn't have a row missing, as the index into
189 * the table should be the PTYPE.
193 * IF NOT i40e_ptype_lookup[ptype].known
196 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
197 * Use the rest of the fields to look at the tunnels, inner protocols, etc
199 * Use the enum i40e_rx_l2_ptype to decode the packet type
203 /* macro to make the table lines short */
204 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
207 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
208 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
209 I40E_RX_PTYPE_##OUTER_FRAG, \
210 I40E_RX_PTYPE_TUNNEL_##T, \
211 I40E_RX_PTYPE_TUNNEL_END_##TE, \
212 I40E_RX_PTYPE_##TEF, \
213 I40E_RX_PTYPE_INNER_PROT_##I, \
214 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
216 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
217 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
219 /* shorter macros makes the table fit but are terse */
220 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
221 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
222 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
224 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
225 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
226 /* L2 Packet types */
227 I40E_PTT_UNUSED_ENTRY(0),
228 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
229 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
230 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
231 I40E_PTT_UNUSED_ENTRY(4),
232 I40E_PTT_UNUSED_ENTRY(5),
233 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
235 I40E_PTT_UNUSED_ENTRY(8),
236 I40E_PTT_UNUSED_ENTRY(9),
237 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
239 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 /* Non Tunneled IPv4 */
251 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
254 I40E_PTT_UNUSED_ENTRY(25),
255 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
256 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
257 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
260 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
261 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
262 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(32),
264 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
265 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
266 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
269 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
270 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
271 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(39),
273 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
274 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
275 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
277 /* IPv4 --> GRE/NAT */
278 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
280 /* IPv4 --> GRE/NAT --> IPv4 */
281 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
282 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
283 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
284 I40E_PTT_UNUSED_ENTRY(47),
285 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
286 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
287 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
289 /* IPv4 --> GRE/NAT --> IPv6 */
290 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
291 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
292 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(54),
294 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
295 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
296 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> MAC */
299 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
301 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
302 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
303 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
304 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
305 I40E_PTT_UNUSED_ENTRY(62),
306 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
307 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
308 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
310 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
311 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
312 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
313 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(69),
315 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
316 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
317 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT --> MAC/VLAN */
320 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
322 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
323 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
324 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
325 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
326 I40E_PTT_UNUSED_ENTRY(77),
327 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
328 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
329 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
331 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
332 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
333 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
334 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(84),
336 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
337 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
338 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
340 /* Non Tunneled IPv6 */
341 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
342 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
343 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
344 I40E_PTT_UNUSED_ENTRY(91),
345 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
346 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
347 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
350 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
351 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
352 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
353 I40E_PTT_UNUSED_ENTRY(98),
354 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
355 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
356 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
359 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
360 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
361 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(105),
363 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
364 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
365 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
367 /* IPv6 --> GRE/NAT */
368 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
370 /* IPv6 --> GRE/NAT -> IPv4 */
371 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
372 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
373 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
374 I40E_PTT_UNUSED_ENTRY(113),
375 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
376 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
377 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
379 /* IPv6 --> GRE/NAT -> IPv6 */
380 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
381 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
382 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(120),
384 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
385 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
386 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> MAC */
389 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
391 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
392 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
393 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
394 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
395 I40E_PTT_UNUSED_ENTRY(128),
396 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
397 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
398 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
401 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
402 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
403 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(135),
405 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
406 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
407 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC/VLAN */
410 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
413 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
414 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
415 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
416 I40E_PTT_UNUSED_ENTRY(143),
417 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
418 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
419 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
422 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
423 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
424 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(150),
426 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
427 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
428 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
431 I40E_PTT_UNUSED_ENTRY(154),
432 I40E_PTT_UNUSED_ENTRY(155),
433 I40E_PTT_UNUSED_ENTRY(156),
434 I40E_PTT_UNUSED_ENTRY(157),
435 I40E_PTT_UNUSED_ENTRY(158),
436 I40E_PTT_UNUSED_ENTRY(159),
438 I40E_PTT_UNUSED_ENTRY(160),
439 I40E_PTT_UNUSED_ENTRY(161),
440 I40E_PTT_UNUSED_ENTRY(162),
441 I40E_PTT_UNUSED_ENTRY(163),
442 I40E_PTT_UNUSED_ENTRY(164),
443 I40E_PTT_UNUSED_ENTRY(165),
444 I40E_PTT_UNUSED_ENTRY(166),
445 I40E_PTT_UNUSED_ENTRY(167),
446 I40E_PTT_UNUSED_ENTRY(168),
447 I40E_PTT_UNUSED_ENTRY(169),
449 I40E_PTT_UNUSED_ENTRY(170),
450 I40E_PTT_UNUSED_ENTRY(171),
451 I40E_PTT_UNUSED_ENTRY(172),
452 I40E_PTT_UNUSED_ENTRY(173),
453 I40E_PTT_UNUSED_ENTRY(174),
454 I40E_PTT_UNUSED_ENTRY(175),
455 I40E_PTT_UNUSED_ENTRY(176),
456 I40E_PTT_UNUSED_ENTRY(177),
457 I40E_PTT_UNUSED_ENTRY(178),
458 I40E_PTT_UNUSED_ENTRY(179),
460 I40E_PTT_UNUSED_ENTRY(180),
461 I40E_PTT_UNUSED_ENTRY(181),
462 I40E_PTT_UNUSED_ENTRY(182),
463 I40E_PTT_UNUSED_ENTRY(183),
464 I40E_PTT_UNUSED_ENTRY(184),
465 I40E_PTT_UNUSED_ENTRY(185),
466 I40E_PTT_UNUSED_ENTRY(186),
467 I40E_PTT_UNUSED_ENTRY(187),
468 I40E_PTT_UNUSED_ENTRY(188),
469 I40E_PTT_UNUSED_ENTRY(189),
471 I40E_PTT_UNUSED_ENTRY(190),
472 I40E_PTT_UNUSED_ENTRY(191),
473 I40E_PTT_UNUSED_ENTRY(192),
474 I40E_PTT_UNUSED_ENTRY(193),
475 I40E_PTT_UNUSED_ENTRY(194),
476 I40E_PTT_UNUSED_ENTRY(195),
477 I40E_PTT_UNUSED_ENTRY(196),
478 I40E_PTT_UNUSED_ENTRY(197),
479 I40E_PTT_UNUSED_ENTRY(198),
480 I40E_PTT_UNUSED_ENTRY(199),
482 I40E_PTT_UNUSED_ENTRY(200),
483 I40E_PTT_UNUSED_ENTRY(201),
484 I40E_PTT_UNUSED_ENTRY(202),
485 I40E_PTT_UNUSED_ENTRY(203),
486 I40E_PTT_UNUSED_ENTRY(204),
487 I40E_PTT_UNUSED_ENTRY(205),
488 I40E_PTT_UNUSED_ENTRY(206),
489 I40E_PTT_UNUSED_ENTRY(207),
490 I40E_PTT_UNUSED_ENTRY(208),
491 I40E_PTT_UNUSED_ENTRY(209),
493 I40E_PTT_UNUSED_ENTRY(210),
494 I40E_PTT_UNUSED_ENTRY(211),
495 I40E_PTT_UNUSED_ENTRY(212),
496 I40E_PTT_UNUSED_ENTRY(213),
497 I40E_PTT_UNUSED_ENTRY(214),
498 I40E_PTT_UNUSED_ENTRY(215),
499 I40E_PTT_UNUSED_ENTRY(216),
500 I40E_PTT_UNUSED_ENTRY(217),
501 I40E_PTT_UNUSED_ENTRY(218),
502 I40E_PTT_UNUSED_ENTRY(219),
504 I40E_PTT_UNUSED_ENTRY(220),
505 I40E_PTT_UNUSED_ENTRY(221),
506 I40E_PTT_UNUSED_ENTRY(222),
507 I40E_PTT_UNUSED_ENTRY(223),
508 I40E_PTT_UNUSED_ENTRY(224),
509 I40E_PTT_UNUSED_ENTRY(225),
510 I40E_PTT_UNUSED_ENTRY(226),
511 I40E_PTT_UNUSED_ENTRY(227),
512 I40E_PTT_UNUSED_ENTRY(228),
513 I40E_PTT_UNUSED_ENTRY(229),
515 I40E_PTT_UNUSED_ENTRY(230),
516 I40E_PTT_UNUSED_ENTRY(231),
517 I40E_PTT_UNUSED_ENTRY(232),
518 I40E_PTT_UNUSED_ENTRY(233),
519 I40E_PTT_UNUSED_ENTRY(234),
520 I40E_PTT_UNUSED_ENTRY(235),
521 I40E_PTT_UNUSED_ENTRY(236),
522 I40E_PTT_UNUSED_ENTRY(237),
523 I40E_PTT_UNUSED_ENTRY(238),
524 I40E_PTT_UNUSED_ENTRY(239),
526 I40E_PTT_UNUSED_ENTRY(240),
527 I40E_PTT_UNUSED_ENTRY(241),
528 I40E_PTT_UNUSED_ENTRY(242),
529 I40E_PTT_UNUSED_ENTRY(243),
530 I40E_PTT_UNUSED_ENTRY(244),
531 I40E_PTT_UNUSED_ENTRY(245),
532 I40E_PTT_UNUSED_ENTRY(246),
533 I40E_PTT_UNUSED_ENTRY(247),
534 I40E_PTT_UNUSED_ENTRY(248),
535 I40E_PTT_UNUSED_ENTRY(249),
537 I40E_PTT_UNUSED_ENTRY(250),
538 I40E_PTT_UNUSED_ENTRY(251),
539 I40E_PTT_UNUSED_ENTRY(252),
540 I40E_PTT_UNUSED_ENTRY(253),
541 I40E_PTT_UNUSED_ENTRY(254),
542 I40E_PTT_UNUSED_ENTRY(255)
548 * i40e_init_shared_code - Initialize the shared code
549 * @hw: pointer to hardware structure
551 * This assigns the MAC type and PHY code and inits the NVM.
552 * Does not touch the hardware. This function must be called prior to any
553 * other function in the shared code. The i40e_hw structure should be
554 * memset to 0 prior to calling this function. The following fields in
555 * hw structure should be filled in prior to calling this function:
556 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
557 * subsystem_vendor_id, and revision_id
559 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
561 enum i40e_status_code status = I40E_SUCCESS;
564 DEBUGFUNC("i40e_init_shared_code");
566 i40e_set_mac_type(hw);
568 switch (hw->mac.type) {
572 return I40E_ERR_DEVICE_NOT_SUPPORTED;
575 hw->phy.get_link_info = true;
577 /* Determine port number */
578 reg = rd32(hw, I40E_PFGEN_PORTNUM);
579 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
580 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
583 /* Determine the PF number based on the PCI fn */
584 reg = rd32(hw, I40E_GLPCI_CAPSUP);
585 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
586 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
588 hw->pf_id = (u8)hw->bus.func;
590 status = i40e_init_nvm(hw);
595 * i40e_aq_mac_address_read - Retrieve the MAC addresses
596 * @hw: pointer to the hw struct
597 * @flags: a return indicator of what addresses were added to the addr store
598 * @addrs: the requestor's mac addr store
599 * @cmd_details: pointer to command details structure or NULL
601 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
603 struct i40e_aqc_mac_address_read_data *addrs,
604 struct i40e_asq_cmd_details *cmd_details)
606 struct i40e_aq_desc desc;
607 struct i40e_aqc_mac_address_read *cmd_data =
608 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
609 enum i40e_status_code status;
611 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
612 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
614 status = i40e_asq_send_command(hw, &desc, addrs,
615 sizeof(*addrs), cmd_details);
616 *flags = LE16_TO_CPU(cmd_data->command_flags);
622 * i40e_aq_mac_address_write - Change the MAC addresses
623 * @hw: pointer to the hw struct
624 * @flags: indicates which MAC to be written
625 * @mac_addr: address to write
626 * @cmd_details: pointer to command details structure or NULL
628 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
629 u16 flags, u8 *mac_addr,
630 struct i40e_asq_cmd_details *cmd_details)
632 struct i40e_aq_desc desc;
633 struct i40e_aqc_mac_address_write *cmd_data =
634 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
635 enum i40e_status_code status;
637 i40e_fill_default_direct_cmd_desc(&desc,
638 i40e_aqc_opc_mac_address_write);
639 cmd_data->command_flags = CPU_TO_LE16(flags);
640 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
641 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
642 ((u32)mac_addr[3] << 16) |
643 ((u32)mac_addr[4] << 8) |
646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
652 * i40e_get_mac_addr - get MAC address
653 * @hw: pointer to the HW structure
654 * @mac_addr: pointer to MAC address
656 * Reads the adapter's MAC address from register
658 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
660 struct i40e_aqc_mac_address_read_data addrs;
661 enum i40e_status_code status;
664 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
666 if (flags & I40E_AQC_LAN_ADDR_VALID)
667 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
673 * i40e_get_port_mac_addr - get Port MAC address
674 * @hw: pointer to the HW structure
675 * @mac_addr: pointer to Port MAC address
677 * Reads the adapter's Port MAC address
679 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
681 struct i40e_aqc_mac_address_read_data addrs;
682 enum i40e_status_code status;
685 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
689 if (flags & I40E_AQC_PORT_ADDR_VALID)
690 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
692 status = I40E_ERR_INVALID_MAC_ADDR;
698 * i40e_pre_tx_queue_cfg - pre tx queue configure
699 * @hw: pointer to the HW structure
700 * @queue: target pf queue index
701 * @enable: state change request
703 * Handles hw requirement to indicate intention to enable
704 * or disable target queue.
706 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
708 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
712 if (abs_queue_idx >= 128) {
713 reg_block = abs_queue_idx / 128;
714 abs_queue_idx %= 128;
717 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
718 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
719 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
722 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
724 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
726 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
730 * i40e_validate_mac_addr - Validate unicast MAC address
731 * @mac_addr: pointer to MAC address
733 * Tests a MAC address to ensure it is a valid Individual Address
735 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
737 enum i40e_status_code status = I40E_SUCCESS;
739 DEBUGFUNC("i40e_validate_mac_addr");
741 /* Broadcast addresses ARE multicast addresses
742 * Make sure it is not a multicast address
743 * Reject the zero address
745 if (I40E_IS_MULTICAST(mac_addr) ||
746 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
747 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
748 status = I40E_ERR_INVALID_MAC_ADDR;
754 * i40e_get_media_type - Gets media type
755 * @hw: pointer to the hardware structure
757 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
759 enum i40e_media_type media;
761 switch (hw->phy.link_info.phy_type) {
762 case I40E_PHY_TYPE_10GBASE_SR:
763 case I40E_PHY_TYPE_10GBASE_LR:
764 case I40E_PHY_TYPE_40GBASE_SR4:
765 case I40E_PHY_TYPE_40GBASE_LR4:
766 media = I40E_MEDIA_TYPE_FIBER;
768 case I40E_PHY_TYPE_100BASE_TX:
769 case I40E_PHY_TYPE_1000BASE_T:
770 case I40E_PHY_TYPE_10GBASE_T:
771 media = I40E_MEDIA_TYPE_BASET;
773 case I40E_PHY_TYPE_10GBASE_CR1_CU:
774 case I40E_PHY_TYPE_40GBASE_CR4_CU:
775 case I40E_PHY_TYPE_10GBASE_CR1:
776 case I40E_PHY_TYPE_40GBASE_CR4:
777 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
778 media = I40E_MEDIA_TYPE_DA;
780 case I40E_PHY_TYPE_1000BASE_KX:
781 case I40E_PHY_TYPE_10GBASE_KX4:
782 case I40E_PHY_TYPE_10GBASE_KR:
783 case I40E_PHY_TYPE_40GBASE_KR4:
784 media = I40E_MEDIA_TYPE_BACKPLANE;
786 case I40E_PHY_TYPE_SGMII:
787 case I40E_PHY_TYPE_XAUI:
788 case I40E_PHY_TYPE_XFI:
789 case I40E_PHY_TYPE_XLAUI:
790 case I40E_PHY_TYPE_XLPPI:
792 media = I40E_MEDIA_TYPE_UNKNOWN;
799 #define I40E_PF_RESET_WAIT_COUNT 100
801 * i40e_pf_reset - Reset the PF
802 * @hw: pointer to the hardware structure
804 * Assuming someone else has triggered a global reset,
805 * assure the global reset is complete and then reset the PF
807 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
814 /* Poll for Global Reset steady state in case of recent GRST.
815 * The grst delay value is in 100ms units, and we'll wait a
816 * couple counts longer to be sure we don't just miss the end.
818 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
819 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
820 for (cnt = 0; cnt < grst_del + 2; cnt++) {
821 reg = rd32(hw, I40E_GLGEN_RSTAT);
822 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
824 i40e_msec_delay(100);
826 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
827 DEBUGOUT("Global reset polling failed to complete.\n");
828 return I40E_ERR_RESET_FAILED;
831 /* Now Wait for the FW to be ready */
832 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
833 reg = rd32(hw, I40E_GLNVM_ULD);
834 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
835 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
836 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
837 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
838 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
843 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
844 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
845 DEBUGOUT("wait for FW Reset complete timedout\n");
846 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
847 return I40E_ERR_RESET_FAILED;
850 /* If there was a Global Reset in progress when we got here,
851 * we don't need to do the PF Reset
854 reg = rd32(hw, I40E_PFGEN_CTRL);
855 wr32(hw, I40E_PFGEN_CTRL,
856 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
857 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
858 reg = rd32(hw, I40E_PFGEN_CTRL);
859 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
863 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
864 DEBUGOUT("PF reset polling failed to complete.\n");
865 return I40E_ERR_RESET_FAILED;
869 i40e_clear_pxe_mode(hw);
876 * i40e_clear_hw - clear out any left over hw state
877 * @hw: pointer to the hw struct
879 * Clear queues and interrupts, typically called at init time,
880 * but after the capabilities have been found so we know how many
881 * queues and msix vectors have been allocated.
883 void i40e_clear_hw(struct i40e_hw *hw)
885 u32 num_queues, base_queue;
893 /* get number of interrupts, queues, and vfs */
894 val = rd32(hw, I40E_GLPCI_CNF2);
895 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
896 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
897 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
898 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
900 val = rd32(hw, I40E_PFLAN_QALLOC);
901 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
902 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
903 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
904 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
905 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
906 num_queues = (j - base_queue) + 1;
910 val = rd32(hw, I40E_PF_VT_PFALLOC);
911 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
912 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
913 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
914 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
915 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
916 num_vfs = (j - i) + 1;
920 /* stop all the interrupts */
921 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
922 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
923 for (i = 0; i < num_pf_int - 2; i++)
924 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
926 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
927 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
928 wr32(hw, I40E_PFINT_LNKLST0, val);
929 for (i = 0; i < num_pf_int - 2; i++)
930 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
931 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
932 for (i = 0; i < num_vfs; i++)
933 wr32(hw, I40E_VPINT_LNKLST0(i), val);
934 for (i = 0; i < num_vf_int - 2; i++)
935 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
937 /* warn the HW of the coming Tx disables */
938 for (i = 0; i < num_queues; i++) {
939 u32 abs_queue_idx = base_queue + i;
942 if (abs_queue_idx >= 128) {
943 reg_block = abs_queue_idx / 128;
944 abs_queue_idx %= 128;
947 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
948 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
949 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
950 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
952 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
954 i40e_usec_delay(400);
956 /* stop all the queues */
957 for (i = 0; i < num_queues; i++) {
958 wr32(hw, I40E_QINT_TQCTL(i), 0);
959 wr32(hw, I40E_QTX_ENA(i), 0);
960 wr32(hw, I40E_QINT_RQCTL(i), 0);
961 wr32(hw, I40E_QRX_ENA(i), 0);
964 /* short wait for all queue disables to settle */
969 * i40e_clear_pxe_mode - clear pxe operations mode
970 * @hw: pointer to the hw struct
972 * Make sure all PXE mode settings are cleared, including things
973 * like descriptor fetch/write-back mode.
975 void i40e_clear_pxe_mode(struct i40e_hw *hw)
977 if (i40e_check_asq_alive(hw))
978 i40e_aq_clear_pxe_mode(hw, NULL);
982 * i40e_led_is_mine - helper to find matching led
983 * @hw: pointer to the hw struct
984 * @idx: index into GPIO registers
986 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
988 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
993 if (!hw->func_caps.led[idx])
996 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
997 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
998 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1000 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1001 * if it is not our port then ignore
1003 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1010 #define I40E_LED0 22
1011 #define I40E_LINK_ACTIVITY 0xC
1014 * i40e_led_get - return current on/off mode
1015 * @hw: pointer to the hw struct
1017 * The value returned is the 'mode' field as defined in the
1018 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1019 * values are variations of possible behaviors relating to
1020 * blink, link, and wire.
1022 u32 i40e_led_get(struct i40e_hw *hw)
1027 /* as per the documentation GPIO 22-29 are the LED
1028 * GPIO pins named LED0..LED7
1030 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1031 u32 gpio_val = i40e_led_is_mine(hw, i);
1036 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1037 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1045 * i40e_led_set - set new on/off mode
1046 * @hw: pointer to the hw struct
1047 * @mode: 0=off, 0xf=on (else see manual for mode details)
1048 * @blink: true if the LED should blink when on, false if steady
1050 * if this function is used to turn on the blink it should
1051 * be used to disable the blink when restoring the original state.
1053 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1057 if (mode & 0xfffffff0)
1058 DEBUGOUT1("invalid mode passed in %X\n", mode);
1060 /* as per the documentation GPIO 22-29 are the LED
1061 * GPIO pins named LED0..LED7
1063 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1064 u32 gpio_val = i40e_led_is_mine(hw, i);
1069 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1070 /* this & is a bit of paranoia, but serves as a range check */
1071 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1072 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1074 if (mode == I40E_LINK_ACTIVITY)
1077 gpio_val |= (blink ? 1 : 0) <<
1078 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1080 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1085 /* Admin command wrappers */
1088 * i40e_aq_get_phy_capabilities
1089 * @hw: pointer to the hw struct
1090 * @abilities: structure for PHY capabilities to be filled
1091 * @qualified_modules: report Qualified Modules
1092 * @report_init: report init capabilities (active are default)
1093 * @cmd_details: pointer to command details structure or NULL
1095 * Returns the various PHY abilities supported on the Port.
1097 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1098 bool qualified_modules, bool report_init,
1099 struct i40e_aq_get_phy_abilities_resp *abilities,
1100 struct i40e_asq_cmd_details *cmd_details)
1102 struct i40e_aq_desc desc;
1103 enum i40e_status_code status;
1104 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1107 return I40E_ERR_PARAM;
1109 i40e_fill_default_direct_cmd_desc(&desc,
1110 i40e_aqc_opc_get_phy_abilities);
1112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1113 if (abilities_size > I40E_AQ_LARGE_BUF)
1114 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1116 if (qualified_modules)
1117 desc.params.external.param0 |=
1118 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1121 desc.params.external.param0 |=
1122 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1124 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1127 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1128 status = I40E_ERR_UNKNOWN_PHY;
1134 * i40e_aq_set_phy_config
1135 * @hw: pointer to the hw struct
1136 * @config: structure with PHY configuration to be set
1137 * @cmd_details: pointer to command details structure or NULL
1139 * Set the various PHY configuration parameters
1140 * supported on the Port.One or more of the Set PHY config parameters may be
1141 * ignored in an MFP mode as the PF may not have the privilege to set some
1142 * of the PHY Config parameters. This status will be indicated by the
1145 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1146 struct i40e_aq_set_phy_config *config,
1147 struct i40e_asq_cmd_details *cmd_details)
1149 struct i40e_aq_desc desc;
1150 struct i40e_aq_set_phy_config *cmd =
1151 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1152 enum i40e_status_code status;
1155 return I40E_ERR_PARAM;
1157 i40e_fill_default_direct_cmd_desc(&desc,
1158 i40e_aqc_opc_set_phy_config);
1162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1169 * @hw: pointer to the hw struct
1171 * Set the requested flow control mode using set_phy_config.
1173 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1174 bool atomic_restart)
1176 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1177 struct i40e_aq_get_phy_abilities_resp abilities;
1178 struct i40e_aq_set_phy_config config;
1179 enum i40e_status_code status;
1180 u8 pause_mask = 0x0;
1186 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1187 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1189 case I40E_FC_RX_PAUSE:
1190 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1192 case I40E_FC_TX_PAUSE:
1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1199 /* Get the current phy config */
1200 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1203 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET1;
1207 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1208 /* clear the old pause settings */
1209 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1210 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1211 /* set the new abilities */
1212 config.abilities |= pause_mask;
1213 /* If the abilities have changed, then set the new config */
1214 if (config.abilities != abilities.abilities) {
1215 /* Auto restart link so settings take effect */
1217 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1218 /* Copy over all the old settings */
1219 config.phy_type = abilities.phy_type;
1220 config.link_speed = abilities.link_speed;
1221 config.eee_capability = abilities.eee_capability;
1222 config.eeer = abilities.eeer_val;
1223 config.low_power_ctrl = abilities.d3_lpan;
1224 status = i40e_aq_set_phy_config(hw, &config, NULL);
1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1229 /* Get the abilities to set hw->fc.current_mode correctly */
1230 status = i40e_aq_get_phy_capabilities(hw, false, false,
1233 /* Wait a little bit and try once more */
1234 i40e_msec_delay(1000);
1235 status = i40e_aq_get_phy_capabilities(hw, false, false,
1239 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET2;
1243 /* Copy the what was returned from get capabilities into fc */
1244 if ((abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX) &&
1245 (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX))
1246 hw->fc.current_mode = I40E_FC_FULL;
1247 else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX)
1248 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1249 else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX)
1250 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1252 hw->fc.current_mode = I40E_FC_NONE;
1258 * i40e_aq_set_mac_config
1259 * @hw: pointer to the hw struct
1260 * @max_frame_size: Maximum Frame Size to be supported by the port
1261 * @crc_en: Tell HW to append a CRC to outgoing frames
1262 * @pacing: Pacing configurations
1263 * @cmd_details: pointer to command details structure or NULL
1265 * Configure MAC settings for frame size, jumbo frame support and the
1266 * addition of a CRC by the hardware.
1268 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1270 bool crc_en, u16 pacing,
1271 struct i40e_asq_cmd_details *cmd_details)
1273 struct i40e_aq_desc desc;
1274 struct i40e_aq_set_mac_config *cmd =
1275 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1276 enum i40e_status_code status;
1278 if (max_frame_size == 0)
1279 return I40E_ERR_PARAM;
1281 i40e_fill_default_direct_cmd_desc(&desc,
1282 i40e_aqc_opc_set_mac_config);
1284 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1285 cmd->params = ((u8)pacing & 0x0F) << 3;
1287 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1289 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1295 * i40e_aq_clear_pxe_mode
1296 * @hw: pointer to the hw struct
1297 * @cmd_details: pointer to command details structure or NULL
1299 * Tell the firmware that the driver is taking over from PXE
1301 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1302 struct i40e_asq_cmd_details *cmd_details)
1304 enum i40e_status_code status;
1305 struct i40e_aq_desc desc;
1306 struct i40e_aqc_clear_pxe *cmd =
1307 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1309 i40e_fill_default_direct_cmd_desc(&desc,
1310 i40e_aqc_opc_clear_pxe_mode);
1314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1316 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1322 * i40e_aq_set_link_restart_an
1323 * @hw: pointer to the hw struct
1324 * @enable_link: if true: enable link, if false: disable link
1325 * @cmd_details: pointer to command details structure or NULL
1327 * Sets up the link and restarts the Auto-Negotiation over the link.
1329 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1330 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1332 struct i40e_aq_desc desc;
1333 struct i40e_aqc_set_link_restart_an *cmd =
1334 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1335 enum i40e_status_code status;
1337 i40e_fill_default_direct_cmd_desc(&desc,
1338 i40e_aqc_opc_set_link_restart_an);
1340 cmd->command = I40E_AQ_PHY_RESTART_AN;
1342 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1344 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1352 * i40e_aq_get_link_info
1353 * @hw: pointer to the hw struct
1354 * @enable_lse: enable/disable LinkStatusEvent reporting
1355 * @link: pointer to link status structure - optional
1356 * @cmd_details: pointer to command details structure or NULL
1358 * Returns the link status of the adapter.
1360 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1361 bool enable_lse, struct i40e_link_status *link,
1362 struct i40e_asq_cmd_details *cmd_details)
1364 struct i40e_aq_desc desc;
1365 struct i40e_aqc_get_link_status *resp =
1366 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1367 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1368 enum i40e_status_code status;
1369 bool tx_pause, rx_pause;
1372 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1375 command_flags = I40E_AQ_LSE_ENABLE;
1377 command_flags = I40E_AQ_LSE_DISABLE;
1378 resp->command_flags = CPU_TO_LE16(command_flags);
1380 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1382 if (status != I40E_SUCCESS)
1383 goto aq_get_link_info_exit;
1385 /* save off old link status information */
1386 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1387 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1389 /* update link status */
1390 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1391 hw->phy.media_type = i40e_get_media_type(hw);
1392 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1393 hw_link_info->link_info = resp->link_info;
1394 hw_link_info->an_info = resp->an_info;
1395 hw_link_info->ext_info = resp->ext_info;
1396 hw_link_info->loopback = resp->loopback;
1397 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1398 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1400 /* update fc info */
1401 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1402 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1403 if (tx_pause & rx_pause)
1404 hw->fc.current_mode = I40E_FC_FULL;
1406 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1408 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1410 hw->fc.current_mode = I40E_FC_NONE;
1412 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1413 hw_link_info->crc_enable = true;
1415 hw_link_info->crc_enable = false;
1417 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1418 hw_link_info->lse_enable = true;
1420 hw_link_info->lse_enable = false;
1422 /* save link status information */
1424 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1425 I40E_NONDMA_TO_NONDMA);
1427 /* flag cleared so helper functions don't call AQ again */
1428 hw->phy.get_link_info = false;
1430 aq_get_link_info_exit:
1435 * i40e_update_link_info
1436 * @hw: pointer to the hw struct
1437 * @enable_lse: enable/disable LinkStatusEvent reporting
1439 * Returns the link status of the adapter
1441 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1444 struct i40e_aq_get_phy_abilities_resp abilities;
1445 enum i40e_status_code status;
1447 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1451 status = i40e_aq_get_phy_capabilities(hw, false, false,
1456 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1457 hw->phy.link_info.an_enabled = true;
1459 hw->phy.link_info.an_enabled = false;
1465 * i40e_aq_set_phy_int_mask
1466 * @hw: pointer to the hw struct
1467 * @mask: interrupt mask to be set
1468 * @cmd_details: pointer to command details structure or NULL
1470 * Set link interrupt mask.
1472 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1474 struct i40e_asq_cmd_details *cmd_details)
1476 struct i40e_aq_desc desc;
1477 struct i40e_aqc_set_phy_int_mask *cmd =
1478 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1479 enum i40e_status_code status;
1481 i40e_fill_default_direct_cmd_desc(&desc,
1482 i40e_aqc_opc_set_phy_int_mask);
1484 cmd->event_mask = CPU_TO_LE16(mask);
1486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1492 * i40e_aq_get_local_advt_reg
1493 * @hw: pointer to the hw struct
1494 * @advt_reg: local AN advertisement register value
1495 * @cmd_details: pointer to command details structure or NULL
1497 * Get the Local AN advertisement register value.
1499 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1501 struct i40e_asq_cmd_details *cmd_details)
1503 struct i40e_aq_desc desc;
1504 struct i40e_aqc_an_advt_reg *resp =
1505 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1506 enum i40e_status_code status;
1508 i40e_fill_default_direct_cmd_desc(&desc,
1509 i40e_aqc_opc_get_local_advt_reg);
1511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1513 if (status != I40E_SUCCESS)
1514 goto aq_get_local_advt_reg_exit;
1516 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1517 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1519 aq_get_local_advt_reg_exit:
1524 * i40e_aq_set_local_advt_reg
1525 * @hw: pointer to the hw struct
1526 * @advt_reg: local AN advertisement register value
1527 * @cmd_details: pointer to command details structure or NULL
1529 * Get the Local AN advertisement register value.
1531 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1533 struct i40e_asq_cmd_details *cmd_details)
1535 struct i40e_aq_desc desc;
1536 struct i40e_aqc_an_advt_reg *cmd =
1537 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1538 enum i40e_status_code status;
1540 i40e_fill_default_direct_cmd_desc(&desc,
1541 i40e_aqc_opc_get_local_advt_reg);
1543 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1544 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1546 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1552 * i40e_aq_get_partner_advt
1553 * @hw: pointer to the hw struct
1554 * @advt_reg: AN partner advertisement register value
1555 * @cmd_details: pointer to command details structure or NULL
1557 * Get the link partner AN advertisement register value.
1559 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1561 struct i40e_asq_cmd_details *cmd_details)
1563 struct i40e_aq_desc desc;
1564 struct i40e_aqc_an_advt_reg *resp =
1565 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1566 enum i40e_status_code status;
1568 i40e_fill_default_direct_cmd_desc(&desc,
1569 i40e_aqc_opc_get_partner_advt);
1571 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1573 if (status != I40E_SUCCESS)
1574 goto aq_get_partner_advt_exit;
1576 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1577 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1579 aq_get_partner_advt_exit:
1584 * i40e_aq_set_lb_modes
1585 * @hw: pointer to the hw struct
1586 * @lb_modes: loopback mode to be set
1587 * @cmd_details: pointer to command details structure or NULL
1589 * Sets loopback modes.
1591 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1593 struct i40e_asq_cmd_details *cmd_details)
1595 struct i40e_aq_desc desc;
1596 struct i40e_aqc_set_lb_mode *cmd =
1597 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1598 enum i40e_status_code status;
1600 i40e_fill_default_direct_cmd_desc(&desc,
1601 i40e_aqc_opc_set_lb_modes);
1603 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1611 * i40e_aq_set_phy_debug
1612 * @hw: pointer to the hw struct
1613 * @cmd_flags: debug command flags
1614 * @cmd_details: pointer to command details structure or NULL
1616 * Reset the external PHY.
1618 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1619 struct i40e_asq_cmd_details *cmd_details)
1621 struct i40e_aq_desc desc;
1622 struct i40e_aqc_set_phy_debug *cmd =
1623 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1624 enum i40e_status_code status;
1626 i40e_fill_default_direct_cmd_desc(&desc,
1627 i40e_aqc_opc_set_phy_debug);
1629 cmd->command_flags = cmd_flags;
1631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1638 * @hw: pointer to the hw struct
1639 * @vsi_ctx: pointer to a vsi context struct
1640 * @cmd_details: pointer to command details structure or NULL
1642 * Add a VSI context to the hardware.
1644 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1645 struct i40e_vsi_context *vsi_ctx,
1646 struct i40e_asq_cmd_details *cmd_details)
1648 struct i40e_aq_desc desc;
1649 struct i40e_aqc_add_get_update_vsi *cmd =
1650 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1651 struct i40e_aqc_add_get_update_vsi_completion *resp =
1652 (struct i40e_aqc_add_get_update_vsi_completion *)
1654 enum i40e_status_code status;
1656 i40e_fill_default_direct_cmd_desc(&desc,
1657 i40e_aqc_opc_add_vsi);
1659 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1660 cmd->connection_type = vsi_ctx->connection_type;
1661 cmd->vf_id = vsi_ctx->vf_num;
1662 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1664 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1666 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1667 sizeof(vsi_ctx->info), cmd_details);
1669 if (status != I40E_SUCCESS)
1670 goto aq_add_vsi_exit;
1672 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1673 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1674 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1675 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1682 * i40e_aq_set_default_vsi
1683 * @hw: pointer to the hw struct
1685 * @cmd_details: pointer to command details structure or NULL
1687 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1689 struct i40e_asq_cmd_details *cmd_details)
1691 struct i40e_aq_desc desc;
1692 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1693 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1695 enum i40e_status_code status;
1697 i40e_fill_default_direct_cmd_desc(&desc,
1698 i40e_aqc_opc_set_vsi_promiscuous_modes);
1700 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1701 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1702 cmd->seid = CPU_TO_LE16(seid);
1704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1710 * i40e_aq_set_vsi_unicast_promiscuous
1711 * @hw: pointer to the hw struct
1713 * @set: set unicast promiscuous enable/disable
1714 * @cmd_details: pointer to command details structure or NULL
1716 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1718 struct i40e_asq_cmd_details *cmd_details)
1720 struct i40e_aq_desc desc;
1721 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1722 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1723 enum i40e_status_code status;
1726 i40e_fill_default_direct_cmd_desc(&desc,
1727 i40e_aqc_opc_set_vsi_promiscuous_modes);
1730 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1732 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1734 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1736 cmd->seid = CPU_TO_LE16(seid);
1737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1743 * i40e_aq_set_vsi_multicast_promiscuous
1744 * @hw: pointer to the hw struct
1746 * @set: set multicast promiscuous enable/disable
1747 * @cmd_details: pointer to command details structure or NULL
1749 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1750 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1752 struct i40e_aq_desc desc;
1753 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1754 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1755 enum i40e_status_code status;
1758 i40e_fill_default_direct_cmd_desc(&desc,
1759 i40e_aqc_opc_set_vsi_promiscuous_modes);
1762 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1764 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1766 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1768 cmd->seid = CPU_TO_LE16(seid);
1769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1775 * i40e_aq_set_vsi_broadcast
1776 * @hw: pointer to the hw struct
1778 * @set_filter: true to set filter, false to clear filter
1779 * @cmd_details: pointer to command details structure or NULL
1781 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1783 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1784 u16 seid, bool set_filter,
1785 struct i40e_asq_cmd_details *cmd_details)
1787 struct i40e_aq_desc desc;
1788 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1789 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1790 enum i40e_status_code status;
1792 i40e_fill_default_direct_cmd_desc(&desc,
1793 i40e_aqc_opc_set_vsi_promiscuous_modes);
1796 cmd->promiscuous_flags
1797 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1799 cmd->promiscuous_flags
1800 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1802 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1803 cmd->seid = CPU_TO_LE16(seid);
1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1810 * i40e_get_vsi_params - get VSI configuration info
1811 * @hw: pointer to the hw struct
1812 * @vsi_ctx: pointer to a vsi context struct
1813 * @cmd_details: pointer to command details structure or NULL
1815 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1816 struct i40e_vsi_context *vsi_ctx,
1817 struct i40e_asq_cmd_details *cmd_details)
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_add_get_update_vsi *cmd =
1821 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1822 struct i40e_aqc_add_get_update_vsi_completion *resp =
1823 (struct i40e_aqc_add_get_update_vsi_completion *)
1825 enum i40e_status_code status;
1827 UNREFERENCED_1PARAMETER(cmd_details);
1828 i40e_fill_default_direct_cmd_desc(&desc,
1829 i40e_aqc_opc_get_vsi_parameters);
1831 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1833 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1835 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1836 sizeof(vsi_ctx->info), NULL);
1838 if (status != I40E_SUCCESS)
1839 goto aq_get_vsi_params_exit;
1841 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1842 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1843 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1844 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1846 aq_get_vsi_params_exit:
1851 * i40e_aq_update_vsi_params
1852 * @hw: pointer to the hw struct
1853 * @vsi_ctx: pointer to a vsi context struct
1854 * @cmd_details: pointer to command details structure or NULL
1856 * Update a VSI context.
1858 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1859 struct i40e_vsi_context *vsi_ctx,
1860 struct i40e_asq_cmd_details *cmd_details)
1862 struct i40e_aq_desc desc;
1863 struct i40e_aqc_add_get_update_vsi *cmd =
1864 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1865 enum i40e_status_code status;
1867 i40e_fill_default_direct_cmd_desc(&desc,
1868 i40e_aqc_opc_update_vsi_parameters);
1869 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1871 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1873 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1874 sizeof(vsi_ctx->info), cmd_details);
1880 * i40e_aq_get_switch_config
1881 * @hw: pointer to the hardware structure
1882 * @buf: pointer to the result buffer
1883 * @buf_size: length of input buffer
1884 * @start_seid: seid to start for the report, 0 == beginning
1885 * @cmd_details: pointer to command details structure or NULL
1887 * Fill the buf with switch configuration returned from AdminQ command
1889 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1890 struct i40e_aqc_get_switch_config_resp *buf,
1891 u16 buf_size, u16 *start_seid,
1892 struct i40e_asq_cmd_details *cmd_details)
1894 struct i40e_aq_desc desc;
1895 struct i40e_aqc_switch_seid *scfg =
1896 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1897 enum i40e_status_code status;
1899 i40e_fill_default_direct_cmd_desc(&desc,
1900 i40e_aqc_opc_get_switch_config);
1901 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1902 if (buf_size > I40E_AQ_LARGE_BUF)
1903 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1904 scfg->seid = CPU_TO_LE16(*start_seid);
1906 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1907 *start_seid = LE16_TO_CPU(scfg->seid);
1913 * i40e_aq_get_firmware_version
1914 * @hw: pointer to the hw struct
1915 * @fw_major_version: firmware major version
1916 * @fw_minor_version: firmware minor version
1917 * @api_major_version: major queue version
1918 * @api_minor_version: minor queue version
1919 * @cmd_details: pointer to command details structure or NULL
1921 * Get the firmware version from the admin queue commands
1923 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1924 u16 *fw_major_version, u16 *fw_minor_version,
1925 u16 *api_major_version, u16 *api_minor_version,
1926 struct i40e_asq_cmd_details *cmd_details)
1928 struct i40e_aq_desc desc;
1929 struct i40e_aqc_get_version *resp =
1930 (struct i40e_aqc_get_version *)&desc.params.raw;
1931 enum i40e_status_code status;
1933 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1935 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1937 if (status == I40E_SUCCESS) {
1938 if (fw_major_version != NULL)
1939 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1940 if (fw_minor_version != NULL)
1941 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1942 if (api_major_version != NULL)
1943 *api_major_version = LE16_TO_CPU(resp->api_major);
1944 if (api_minor_version != NULL)
1945 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1947 /* A workaround to fix the API version in SW */
1948 if (api_major_version && api_minor_version &&
1949 fw_major_version && fw_minor_version &&
1950 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1951 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1952 (*fw_major_version > 4)))
1953 *api_minor_version = 2;
1960 * i40e_aq_send_driver_version
1961 * @hw: pointer to the hw struct
1962 * @dv: driver's major, minor version
1963 * @cmd_details: pointer to command details structure or NULL
1965 * Send the driver version to the firmware
1967 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1968 struct i40e_driver_version *dv,
1969 struct i40e_asq_cmd_details *cmd_details)
1971 struct i40e_aq_desc desc;
1972 struct i40e_aqc_driver_version *cmd =
1973 (struct i40e_aqc_driver_version *)&desc.params.raw;
1974 enum i40e_status_code status;
1978 return I40E_ERR_PARAM;
1980 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1982 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI);
1983 cmd->driver_major_ver = dv->major_version;
1984 cmd->driver_minor_ver = dv->minor_version;
1985 cmd->driver_build_ver = dv->build_version;
1986 cmd->driver_subbuild_ver = dv->subbuild_version;
1989 while (len < sizeof(dv->driver_string) &&
1990 (dv->driver_string[len] < 0x80) &&
1991 dv->driver_string[len])
1993 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2000 * i40e_get_link_status - get status of the HW network link
2001 * @hw: pointer to the hw struct
2003 * Returns true if link is up, false if link is down.
2005 * Side effect: LinkStatusEvent reporting becomes enabled
2007 bool i40e_get_link_status(struct i40e_hw *hw)
2009 enum i40e_status_code status = I40E_SUCCESS;
2010 bool link_status = false;
2012 if (hw->phy.get_link_info) {
2013 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2015 if (status != I40E_SUCCESS)
2016 goto i40e_get_link_status_exit;
2019 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2021 i40e_get_link_status_exit:
2026 * i40e_get_link_speed
2027 * @hw: pointer to the hw struct
2029 * Returns the link speed of the adapter.
2031 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2033 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2034 enum i40e_status_code status = I40E_SUCCESS;
2036 if (hw->phy.get_link_info) {
2037 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2039 if (status != I40E_SUCCESS)
2040 goto i40e_link_speed_exit;
2043 speed = hw->phy.link_info.link_speed;
2045 i40e_link_speed_exit:
2050 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2051 * @hw: pointer to the hw struct
2052 * @uplink_seid: the MAC or other gizmo SEID
2053 * @downlink_seid: the VSI SEID
2054 * @enabled_tc: bitmap of TCs to be enabled
2055 * @default_port: true for default port VSI, false for control port
2056 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2057 * @veb_seid: pointer to where to put the resulting VEB SEID
2058 * @cmd_details: pointer to command details structure or NULL
2060 * This asks the FW to add a VEB between the uplink and downlink
2061 * elements. If the uplink SEID is 0, this will be a floating VEB.
2063 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2064 u16 downlink_seid, u8 enabled_tc,
2065 bool default_port, bool enable_l2_filtering,
2067 struct i40e_asq_cmd_details *cmd_details)
2069 struct i40e_aq_desc desc;
2070 struct i40e_aqc_add_veb *cmd =
2071 (struct i40e_aqc_add_veb *)&desc.params.raw;
2072 struct i40e_aqc_add_veb_completion *resp =
2073 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2074 enum i40e_status_code status;
2077 /* SEIDs need to either both be set or both be 0 for floating VEB */
2078 if (!!uplink_seid != !!downlink_seid)
2079 return I40E_ERR_PARAM;
2081 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2083 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2084 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2085 cmd->enable_tcs = enabled_tc;
2087 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2089 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2091 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2093 if (enable_l2_filtering)
2094 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2096 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2100 if (!status && veb_seid)
2101 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2107 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2108 * @hw: pointer to the hw struct
2109 * @veb_seid: the SEID of the VEB to query
2110 * @switch_id: the uplink switch id
2111 * @floating: set to true if the VEB is floating
2112 * @statistic_index: index of the stats counter block for this VEB
2113 * @vebs_used: number of VEB's used by function
2114 * @vebs_free: total VEB's not reserved by any function
2115 * @cmd_details: pointer to command details structure or NULL
2117 * This retrieves the parameters for a particular VEB, specified by
2118 * uplink_seid, and returns them to the caller.
2120 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2121 u16 veb_seid, u16 *switch_id,
2122 bool *floating, u16 *statistic_index,
2123 u16 *vebs_used, u16 *vebs_free,
2124 struct i40e_asq_cmd_details *cmd_details)
2126 struct i40e_aq_desc desc;
2127 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2128 (struct i40e_aqc_get_veb_parameters_completion *)
2130 enum i40e_status_code status;
2133 return I40E_ERR_PARAM;
2135 i40e_fill_default_direct_cmd_desc(&desc,
2136 i40e_aqc_opc_get_veb_parameters);
2137 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2144 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2145 if (statistic_index)
2146 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2148 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2150 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2152 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2153 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2164 * i40e_aq_add_macvlan
2165 * @hw: pointer to the hw struct
2166 * @seid: VSI for the mac address
2167 * @mv_list: list of macvlans to be added
2168 * @count: length of the list
2169 * @cmd_details: pointer to command details structure or NULL
2171 * Add MAC/VLAN addresses to the HW filtering
2173 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2174 struct i40e_aqc_add_macvlan_element_data *mv_list,
2175 u16 count, struct i40e_asq_cmd_details *cmd_details)
2177 struct i40e_aq_desc desc;
2178 struct i40e_aqc_macvlan *cmd =
2179 (struct i40e_aqc_macvlan *)&desc.params.raw;
2180 enum i40e_status_code status;
2183 if (count == 0 || !mv_list || !hw)
2184 return I40E_ERR_PARAM;
2186 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2188 /* prep the rest of the request */
2189 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2190 cmd->num_addresses = CPU_TO_LE16(count);
2191 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2195 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2196 if (buf_size > I40E_AQ_LARGE_BUF)
2197 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2199 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2206 * i40e_aq_remove_macvlan
2207 * @hw: pointer to the hw struct
2208 * @seid: VSI for the mac address
2209 * @mv_list: list of macvlans to be removed
2210 * @count: length of the list
2211 * @cmd_details: pointer to command details structure or NULL
2213 * Remove MAC/VLAN addresses from the HW filtering
2215 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2216 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2217 u16 count, struct i40e_asq_cmd_details *cmd_details)
2219 struct i40e_aq_desc desc;
2220 struct i40e_aqc_macvlan *cmd =
2221 (struct i40e_aqc_macvlan *)&desc.params.raw;
2222 enum i40e_status_code status;
2225 if (count == 0 || !mv_list || !hw)
2226 return I40E_ERR_PARAM;
2228 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2230 /* prep the rest of the request */
2231 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2232 cmd->num_addresses = CPU_TO_LE16(count);
2233 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2237 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2238 if (buf_size > I40E_AQ_LARGE_BUF)
2239 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2241 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2248 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2249 * @hw: pointer to the hw struct
2250 * @seid: VSI for the vlan filters
2251 * @v_list: list of vlan filters to be added
2252 * @count: length of the list
2253 * @cmd_details: pointer to command details structure or NULL
2255 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2256 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2257 u8 count, struct i40e_asq_cmd_details *cmd_details)
2259 struct i40e_aq_desc desc;
2260 struct i40e_aqc_macvlan *cmd =
2261 (struct i40e_aqc_macvlan *)&desc.params.raw;
2262 enum i40e_status_code status;
2265 if (count == 0 || !v_list || !hw)
2266 return I40E_ERR_PARAM;
2268 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2270 /* prep the rest of the request */
2271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2272 cmd->num_addresses = CPU_TO_LE16(count);
2273 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2277 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2278 if (buf_size > I40E_AQ_LARGE_BUF)
2279 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2281 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2288 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2289 * @hw: pointer to the hw struct
2290 * @seid: VSI for the vlan filters
2291 * @v_list: list of macvlans to be removed
2292 * @count: length of the list
2293 * @cmd_details: pointer to command details structure or NULL
2295 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2296 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2297 u8 count, struct i40e_asq_cmd_details *cmd_details)
2299 struct i40e_aq_desc desc;
2300 struct i40e_aqc_macvlan *cmd =
2301 (struct i40e_aqc_macvlan *)&desc.params.raw;
2302 enum i40e_status_code status;
2305 if (count == 0 || !v_list || !hw)
2306 return I40E_ERR_PARAM;
2308 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2310 /* prep the rest of the request */
2311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2312 cmd->num_addresses = CPU_TO_LE16(count);
2313 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2317 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2318 if (buf_size > I40E_AQ_LARGE_BUF)
2319 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2321 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2328 * i40e_aq_send_msg_to_vf
2329 * @hw: pointer to the hardware structure
2330 * @vfid: vf id to send msg
2331 * @v_opcode: opcodes for VF-PF communication
2332 * @v_retval: return error code
2333 * @msg: pointer to the msg buffer
2334 * @msglen: msg length
2335 * @cmd_details: pointer to command details
2339 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2340 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2341 struct i40e_asq_cmd_details *cmd_details)
2343 struct i40e_aq_desc desc;
2344 struct i40e_aqc_pf_vf_message *cmd =
2345 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2346 enum i40e_status_code status;
2348 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2349 cmd->id = CPU_TO_LE32(vfid);
2350 desc.cookie_high = CPU_TO_LE32(v_opcode);
2351 desc.cookie_low = CPU_TO_LE32(v_retval);
2352 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2354 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2356 if (msglen > I40E_AQ_LARGE_BUF)
2357 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2358 desc.datalen = CPU_TO_LE16(msglen);
2360 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2366 * i40e_aq_get_hmc_resource_profile
2367 * @hw: pointer to the hw struct
2368 * @profile: type of profile the HMC is to be set as
2369 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2370 * @cmd_details: pointer to command details structure or NULL
2372 * query the HMC profile of the device.
2374 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2375 enum i40e_aq_hmc_profile *profile,
2376 u8 *pe_vf_enabled_count,
2377 struct i40e_asq_cmd_details *cmd_details)
2379 struct i40e_aq_desc desc;
2380 struct i40e_aq_get_set_hmc_resource_profile *resp =
2381 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2382 enum i40e_status_code status;
2384 i40e_fill_default_direct_cmd_desc(&desc,
2385 i40e_aqc_opc_query_hmc_resource_profile);
2386 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2388 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2389 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2390 *pe_vf_enabled_count = resp->pe_vf_enabled &
2391 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2397 * i40e_aq_set_hmc_resource_profile
2398 * @hw: pointer to the hw struct
2399 * @profile: type of profile the HMC is to be set as
2400 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2401 * @cmd_details: pointer to command details structure or NULL
2403 * set the HMC profile of the device.
2405 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2406 enum i40e_aq_hmc_profile profile,
2407 u8 pe_vf_enabled_count,
2408 struct i40e_asq_cmd_details *cmd_details)
2410 struct i40e_aq_desc desc;
2411 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2412 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2413 enum i40e_status_code status;
2415 i40e_fill_default_direct_cmd_desc(&desc,
2416 i40e_aqc_opc_set_hmc_resource_profile);
2418 cmd->pm_profile = (u8)profile;
2419 cmd->pe_vf_enabled = pe_vf_enabled_count;
2421 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427 * i40e_aq_request_resource
2428 * @hw: pointer to the hw struct
2429 * @resource: resource id
2430 * @access: access type
2431 * @sdp_number: resource number
2432 * @timeout: the maximum time in ms that the driver may hold the resource
2433 * @cmd_details: pointer to command details structure or NULL
2435 * requests common resource using the admin queue commands
2437 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2438 enum i40e_aq_resources_ids resource,
2439 enum i40e_aq_resource_access_type access,
2440 u8 sdp_number, u64 *timeout,
2441 struct i40e_asq_cmd_details *cmd_details)
2443 struct i40e_aq_desc desc;
2444 struct i40e_aqc_request_resource *cmd_resp =
2445 (struct i40e_aqc_request_resource *)&desc.params.raw;
2446 enum i40e_status_code status;
2448 DEBUGFUNC("i40e_aq_request_resource");
2450 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2452 cmd_resp->resource_id = CPU_TO_LE16(resource);
2453 cmd_resp->access_type = CPU_TO_LE16(access);
2454 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2457 /* The completion specifies the maximum time in ms that the driver
2458 * may hold the resource in the Timeout field.
2459 * If the resource is held by someone else, the command completes with
2460 * busy return value and the timeout field indicates the maximum time
2461 * the current owner of the resource has to free it.
2463 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2464 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2470 * i40e_aq_release_resource
2471 * @hw: pointer to the hw struct
2472 * @resource: resource id
2473 * @sdp_number: resource number
2474 * @cmd_details: pointer to command details structure or NULL
2476 * release common resource using the admin queue commands
2478 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2479 enum i40e_aq_resources_ids resource,
2481 struct i40e_asq_cmd_details *cmd_details)
2483 struct i40e_aq_desc desc;
2484 struct i40e_aqc_request_resource *cmd =
2485 (struct i40e_aqc_request_resource *)&desc.params.raw;
2486 enum i40e_status_code status;
2488 DEBUGFUNC("i40e_aq_release_resource");
2490 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2492 cmd->resource_id = CPU_TO_LE16(resource);
2493 cmd->resource_number = CPU_TO_LE32(sdp_number);
2495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2502 * @hw: pointer to the hw struct
2503 * @module_pointer: module pointer location in words from the NVM beginning
2504 * @offset: byte offset from the module beginning
2505 * @length: length of the section to be read (in bytes from the offset)
2506 * @data: command buffer (size [bytes] = length)
2507 * @last_command: tells if this is the last command in a series
2508 * @cmd_details: pointer to command details structure or NULL
2510 * Read the NVM using the admin queue commands
2512 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2513 u32 offset, u16 length, void *data,
2515 struct i40e_asq_cmd_details *cmd_details)
2517 struct i40e_aq_desc desc;
2518 struct i40e_aqc_nvm_update *cmd =
2519 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2520 enum i40e_status_code status;
2522 DEBUGFUNC("i40e_aq_read_nvm");
2524 /* In offset the highest byte must be zeroed. */
2525 if (offset & 0xFF000000) {
2526 status = I40E_ERR_PARAM;
2527 goto i40e_aq_read_nvm_exit;
2530 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2532 /* If this is the last command in a series, set the proper flag. */
2534 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2535 cmd->module_pointer = module_pointer;
2536 cmd->offset = CPU_TO_LE32(offset);
2537 cmd->length = CPU_TO_LE16(length);
2539 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2540 if (length > I40E_AQ_LARGE_BUF)
2541 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2543 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2545 i40e_aq_read_nvm_exit:
2551 * @hw: pointer to the hw struct
2552 * @module_pointer: module pointer location in words from the NVM beginning
2553 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2554 * @length: length of the section to be erased (expressed in 4 KB)
2555 * @last_command: tells if this is the last command in a series
2556 * @cmd_details: pointer to command details structure or NULL
2558 * Erase the NVM sector using the admin queue commands
2560 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2561 u32 offset, u16 length, bool last_command,
2562 struct i40e_asq_cmd_details *cmd_details)
2564 struct i40e_aq_desc desc;
2565 struct i40e_aqc_nvm_update *cmd =
2566 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2567 enum i40e_status_code status;
2569 DEBUGFUNC("i40e_aq_erase_nvm");
2571 /* In offset the highest byte must be zeroed. */
2572 if (offset & 0xFF000000) {
2573 status = I40E_ERR_PARAM;
2574 goto i40e_aq_erase_nvm_exit;
2577 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2579 /* If this is the last command in a series, set the proper flag. */
2581 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2582 cmd->module_pointer = module_pointer;
2583 cmd->offset = CPU_TO_LE32(offset);
2584 cmd->length = CPU_TO_LE16(length);
2586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2588 i40e_aq_erase_nvm_exit:
2592 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2593 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2594 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2595 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2596 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2597 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2598 #define I40E_DEV_FUNC_CAP_VF 0x13
2599 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2600 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2601 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2602 #define I40E_DEV_FUNC_CAP_VSI 0x17
2603 #define I40E_DEV_FUNC_CAP_DCB 0x18
2604 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2605 #define I40E_DEV_FUNC_CAP_RSS 0x40
2606 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2607 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2608 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2609 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2610 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2611 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2612 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2613 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2614 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2615 #define I40E_DEV_FUNC_CAP_LED 0x61
2616 #define I40E_DEV_FUNC_CAP_SDP 0x62
2617 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2620 * i40e_parse_discover_capabilities
2621 * @hw: pointer to the hw struct
2622 * @buff: pointer to a buffer containing device/function capability records
2623 * @cap_count: number of capability records in the list
2624 * @list_type_opc: type of capabilities list to parse
2626 * Parse the device/function capabilities list.
2628 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2630 enum i40e_admin_queue_opc list_type_opc)
2632 struct i40e_aqc_list_capabilities_element_resp *cap;
2633 u32 number, logical_id, phys_id;
2634 struct i40e_hw_capabilities *p;
2638 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2640 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2641 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2642 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2643 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2647 for (i = 0; i < cap_count; i++, cap++) {
2648 id = LE16_TO_CPU(cap->id);
2649 number = LE32_TO_CPU(cap->number);
2650 logical_id = LE32_TO_CPU(cap->logical_id);
2651 phys_id = LE32_TO_CPU(cap->phys_id);
2654 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2655 p->switch_mode = number;
2657 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2658 p->management_mode = number;
2660 case I40E_DEV_FUNC_CAP_NPAR:
2661 p->npar_enable = number;
2663 case I40E_DEV_FUNC_CAP_OS2BMC:
2666 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2667 p->valid_functions = number;
2669 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2671 p->sr_iov_1_1 = true;
2673 case I40E_DEV_FUNC_CAP_VF:
2674 p->num_vfs = number;
2675 p->vf_base_id = logical_id;
2677 case I40E_DEV_FUNC_CAP_VMDQ:
2681 case I40E_DEV_FUNC_CAP_802_1_QBG:
2683 p->evb_802_1_qbg = true;
2685 case I40E_DEV_FUNC_CAP_802_1_QBH:
2687 p->evb_802_1_qbh = true;
2689 case I40E_DEV_FUNC_CAP_VSI:
2690 p->num_vsis = number;
2692 case I40E_DEV_FUNC_CAP_DCB:
2695 p->enabled_tcmap = logical_id;
2699 case I40E_DEV_FUNC_CAP_FCOE:
2703 case I40E_DEV_FUNC_CAP_RSS:
2705 p->rss_table_size = number;
2706 p->rss_table_entry_width = logical_id;
2708 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2709 p->num_rx_qp = number;
2710 p->base_queue = phys_id;
2712 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2713 p->num_tx_qp = number;
2714 p->base_queue = phys_id;
2716 case I40E_DEV_FUNC_CAP_MSIX:
2717 p->num_msix_vectors = number;
2719 case I40E_DEV_FUNC_CAP_MSIX_VF:
2720 p->num_msix_vectors_vf = number;
2722 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2724 p->mfp_mode_1 = true;
2726 case I40E_DEV_FUNC_CAP_CEM:
2730 case I40E_DEV_FUNC_CAP_IWARP:
2734 case I40E_DEV_FUNC_CAP_LED:
2735 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2736 p->led[phys_id] = true;
2738 case I40E_DEV_FUNC_CAP_SDP:
2739 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2740 p->sdp[phys_id] = true;
2742 case I40E_DEV_FUNC_CAP_MDIO:
2744 p->mdio_port_num = phys_id;
2745 p->mdio_port_mode = logical_id;
2748 case I40E_DEV_FUNC_CAP_IEEE_1588:
2750 p->ieee_1588 = true;
2752 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2754 p->fd_filters_guaranteed = number;
2755 p->fd_filters_best_effort = logical_id;
2762 /* Software override ensuring FCoE is disabled if npar or mfp
2763 * mode because it is not supported in these modes.
2765 if (p->npar_enable || p->mfp_mode_1)
2768 /* additional HW specific goodies that might
2769 * someday be HW version specific
2771 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2775 * i40e_aq_discover_capabilities
2776 * @hw: pointer to the hw struct
2777 * @buff: a virtual buffer to hold the capabilities
2778 * @buff_size: Size of the virtual buffer
2779 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2780 * @list_type_opc: capabilities type to discover - pass in the command opcode
2781 * @cmd_details: pointer to command details structure or NULL
2783 * Get the device capabilities descriptions from the firmware
2785 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2786 void *buff, u16 buff_size, u16 *data_size,
2787 enum i40e_admin_queue_opc list_type_opc,
2788 struct i40e_asq_cmd_details *cmd_details)
2790 struct i40e_aqc_list_capabilites *cmd;
2791 struct i40e_aq_desc desc;
2792 enum i40e_status_code status = I40E_SUCCESS;
2794 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2796 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2797 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2798 status = I40E_ERR_PARAM;
2802 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2804 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2805 if (buff_size > I40E_AQ_LARGE_BUF)
2806 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2808 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2809 *data_size = LE16_TO_CPU(desc.datalen);
2814 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2822 * i40e_aq_update_nvm
2823 * @hw: pointer to the hw struct
2824 * @module_pointer: module pointer location in words from the NVM beginning
2825 * @offset: byte offset from the module beginning
2826 * @length: length of the section to be written (in bytes from the offset)
2827 * @data: command buffer (size [bytes] = length)
2828 * @last_command: tells if this is the last command in a series
2829 * @cmd_details: pointer to command details structure or NULL
2831 * Update the NVM using the admin queue commands
2833 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2834 u32 offset, u16 length, void *data,
2836 struct i40e_asq_cmd_details *cmd_details)
2838 struct i40e_aq_desc desc;
2839 struct i40e_aqc_nvm_update *cmd =
2840 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2841 enum i40e_status_code status;
2843 DEBUGFUNC("i40e_aq_update_nvm");
2845 /* In offset the highest byte must be zeroed. */
2846 if (offset & 0xFF000000) {
2847 status = I40E_ERR_PARAM;
2848 goto i40e_aq_update_nvm_exit;
2851 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2853 /* If this is the last command in a series, set the proper flag. */
2855 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2856 cmd->module_pointer = module_pointer;
2857 cmd->offset = CPU_TO_LE32(offset);
2858 cmd->length = CPU_TO_LE16(length);
2860 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2861 if (length > I40E_AQ_LARGE_BUF)
2862 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2864 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2866 i40e_aq_update_nvm_exit:
2871 * i40e_aq_get_lldp_mib
2872 * @hw: pointer to the hw struct
2873 * @bridge_type: type of bridge requested
2874 * @mib_type: Local, Remote or both Local and Remote MIBs
2875 * @buff: pointer to a user supplied buffer to store the MIB block
2876 * @buff_size: size of the buffer (in bytes)
2877 * @local_len : length of the returned Local LLDP MIB
2878 * @remote_len: length of the returned Remote LLDP MIB
2879 * @cmd_details: pointer to command details structure or NULL
2881 * Requests the complete LLDP MIB (entire packet).
2883 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2884 u8 mib_type, void *buff, u16 buff_size,
2885 u16 *local_len, u16 *remote_len,
2886 struct i40e_asq_cmd_details *cmd_details)
2888 struct i40e_aq_desc desc;
2889 struct i40e_aqc_lldp_get_mib *cmd =
2890 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2891 struct i40e_aqc_lldp_get_mib *resp =
2892 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2893 enum i40e_status_code status;
2895 if (buff_size == 0 || !buff)
2896 return I40E_ERR_PARAM;
2898 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2899 /* Indirect Command */
2900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2902 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2903 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2904 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2906 desc.datalen = CPU_TO_LE16(buff_size);
2908 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2909 if (buff_size > I40E_AQ_LARGE_BUF)
2910 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2912 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2914 if (local_len != NULL)
2915 *local_len = LE16_TO_CPU(resp->local_len);
2916 if (remote_len != NULL)
2917 *remote_len = LE16_TO_CPU(resp->remote_len);
2924 * i40e_aq_cfg_lldp_mib_change_event
2925 * @hw: pointer to the hw struct
2926 * @enable_update: Enable or Disable event posting
2927 * @cmd_details: pointer to command details structure or NULL
2929 * Enable or Disable posting of an event on ARQ when LLDP MIB
2930 * associated with the interface changes
2932 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2934 struct i40e_asq_cmd_details *cmd_details)
2936 struct i40e_aq_desc desc;
2937 struct i40e_aqc_lldp_update_mib *cmd =
2938 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2939 enum i40e_status_code status;
2941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2944 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2952 * i40e_aq_add_lldp_tlv
2953 * @hw: pointer to the hw struct
2954 * @bridge_type: type of bridge
2955 * @buff: buffer with TLV to add
2956 * @buff_size: length of the buffer
2957 * @tlv_len: length of the TLV to be added
2958 * @mib_len: length of the LLDP MIB returned in response
2959 * @cmd_details: pointer to command details structure or NULL
2961 * Add the specified TLV to LLDP Local MIB for the given bridge type,
2962 * it is responsibility of the caller to make sure that the TLV is not
2963 * already present in the LLDPDU.
2964 * In return firmware will write the complete LLDP MIB with the newly
2965 * added TLV in the response buffer.
2967 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
2968 void *buff, u16 buff_size, u16 tlv_len,
2970 struct i40e_asq_cmd_details *cmd_details)
2972 struct i40e_aq_desc desc;
2973 struct i40e_aqc_lldp_add_tlv *cmd =
2974 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
2975 enum i40e_status_code status;
2977 if (buff_size == 0 || !buff || tlv_len == 0)
2978 return I40E_ERR_PARAM;
2980 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
2982 /* Indirect Command */
2983 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2984 if (buff_size > I40E_AQ_LARGE_BUF)
2985 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2986 desc.datalen = CPU_TO_LE16(buff_size);
2988 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2989 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2990 cmd->len = CPU_TO_LE16(tlv_len);
2992 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2994 if (mib_len != NULL)
2995 *mib_len = LE16_TO_CPU(desc.datalen);
3002 * i40e_aq_update_lldp_tlv
3003 * @hw: pointer to the hw struct
3004 * @bridge_type: type of bridge
3005 * @buff: buffer with TLV to update
3006 * @buff_size: size of the buffer holding original and updated TLVs
3007 * @old_len: Length of the Original TLV
3008 * @new_len: Length of the Updated TLV
3009 * @offset: offset of the updated TLV in the buff
3010 * @mib_len: length of the returned LLDP MIB
3011 * @cmd_details: pointer to command details structure or NULL
3013 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3014 * Firmware will place the complete LLDP MIB in response buffer with the
3017 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3018 u8 bridge_type, void *buff, u16 buff_size,
3019 u16 old_len, u16 new_len, u16 offset,
3021 struct i40e_asq_cmd_details *cmd_details)
3023 struct i40e_aq_desc desc;
3024 struct i40e_aqc_lldp_update_tlv *cmd =
3025 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3026 enum i40e_status_code status;
3028 if (buff_size == 0 || !buff || offset == 0 ||
3029 old_len == 0 || new_len == 0)
3030 return I40E_ERR_PARAM;
3032 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3034 /* Indirect Command */
3035 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3036 if (buff_size > I40E_AQ_LARGE_BUF)
3037 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3038 desc.datalen = CPU_TO_LE16(buff_size);
3040 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3041 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3042 cmd->old_len = CPU_TO_LE16(old_len);
3043 cmd->new_offset = CPU_TO_LE16(offset);
3044 cmd->new_len = CPU_TO_LE16(new_len);
3046 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3048 if (mib_len != NULL)
3049 *mib_len = LE16_TO_CPU(desc.datalen);
3056 * i40e_aq_delete_lldp_tlv
3057 * @hw: pointer to the hw struct
3058 * @bridge_type: type of bridge
3059 * @buff: pointer to a user supplied buffer that has the TLV
3060 * @buff_size: length of the buffer
3061 * @tlv_len: length of the TLV to be deleted
3062 * @mib_len: length of the returned LLDP MIB
3063 * @cmd_details: pointer to command details structure or NULL
3065 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3066 * The firmware places the entire LLDP MIB in the response buffer.
3068 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3069 u8 bridge_type, void *buff, u16 buff_size,
3070 u16 tlv_len, u16 *mib_len,
3071 struct i40e_asq_cmd_details *cmd_details)
3073 struct i40e_aq_desc desc;
3074 struct i40e_aqc_lldp_add_tlv *cmd =
3075 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3076 enum i40e_status_code status;
3078 if (buff_size == 0 || !buff)
3079 return I40E_ERR_PARAM;
3081 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3083 /* Indirect Command */
3084 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3085 if (buff_size > I40E_AQ_LARGE_BUF)
3086 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3087 desc.datalen = CPU_TO_LE16(buff_size);
3088 cmd->len = CPU_TO_LE16(tlv_len);
3089 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3090 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3092 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3094 if (mib_len != NULL)
3095 *mib_len = LE16_TO_CPU(desc.datalen);
3103 * @hw: pointer to the hw struct
3104 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3105 * @cmd_details: pointer to command details structure or NULL
3107 * Stop or Shutdown the embedded LLDP Agent
3109 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3110 struct i40e_asq_cmd_details *cmd_details)
3112 struct i40e_aq_desc desc;
3113 struct i40e_aqc_lldp_stop *cmd =
3114 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3115 enum i40e_status_code status;
3117 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3120 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3128 * i40e_aq_start_lldp
3129 * @hw: pointer to the hw struct
3130 * @cmd_details: pointer to command details structure or NULL
3132 * Start the embedded LLDP Agent on all ports.
3134 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3135 struct i40e_asq_cmd_details *cmd_details)
3137 struct i40e_aq_desc desc;
3138 struct i40e_aqc_lldp_start *cmd =
3139 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3140 enum i40e_status_code status;
3142 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3144 cmd->command = I40E_AQ_LLDP_AGENT_START;
3146 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3152 * i40e_aq_add_udp_tunnel
3153 * @hw: pointer to the hw struct
3154 * @udp_port: the UDP port to add
3155 * @header_len: length of the tunneling header length in DWords
3156 * @protocol_index: protocol index type
3157 * @filter_index: pointer to filter index
3158 * @cmd_details: pointer to command details structure or NULL
3160 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3161 u16 udp_port, u8 protocol_index,
3163 struct i40e_asq_cmd_details *cmd_details)
3165 struct i40e_aq_desc desc;
3166 struct i40e_aqc_add_udp_tunnel *cmd =
3167 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3168 struct i40e_aqc_del_udp_tunnel_completion *resp =
3169 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3170 enum i40e_status_code status;
3172 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3174 cmd->udp_port = CPU_TO_LE16(udp_port);
3175 cmd->protocol_type = protocol_index;
3177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3180 *filter_index = resp->index;
3186 * i40e_aq_del_udp_tunnel
3187 * @hw: pointer to the hw struct
3188 * @index: filter index
3189 * @cmd_details: pointer to command details structure or NULL
3191 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3192 struct i40e_asq_cmd_details *cmd_details)
3194 struct i40e_aq_desc desc;
3195 struct i40e_aqc_remove_udp_tunnel *cmd =
3196 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3197 enum i40e_status_code status;
3199 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3209 * i40e_aq_get_switch_resource_alloc (0x0204)
3210 * @hw: pointer to the hw struct
3211 * @num_entries: pointer to u8 to store the number of resource entries returned
3212 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3213 * to store the resource information for all resource types. Each
3214 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3215 * @count: size, in bytes, of the buffer provided
3216 * @cmd_details: pointer to command details structure or NULL
3218 * Query the resources allocated to a function.
3220 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3222 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3224 struct i40e_asq_cmd_details *cmd_details)
3226 struct i40e_aq_desc desc;
3227 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3228 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3229 enum i40e_status_code status;
3231 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3233 i40e_fill_default_direct_cmd_desc(&desc,
3234 i40e_aqc_opc_get_switch_resource_alloc);
3236 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3237 if (length > I40E_AQ_LARGE_BUF)
3238 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3240 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3243 *num_entries = cmd_resp->num_entries;
3249 * i40e_aq_delete_element - Delete switch element
3250 * @hw: pointer to the hw struct
3251 * @seid: the SEID to delete from the switch
3252 * @cmd_details: pointer to command details structure or NULL
3254 * This deletes a switch element from the switch.
3256 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3257 struct i40e_asq_cmd_details *cmd_details)
3259 struct i40e_aq_desc desc;
3260 struct i40e_aqc_switch_seid *cmd =
3261 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3262 enum i40e_status_code status;
3265 return I40E_ERR_PARAM;
3267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3269 cmd->seid = CPU_TO_LE16(seid);
3271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3277 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3278 * @hw: pointer to the hw struct
3279 * @flags: component flags
3280 * @mac_seid: uplink seid (MAC SEID)
3281 * @vsi_seid: connected vsi seid
3282 * @ret_seid: seid of create pv component
3284 * This instantiates an i40e port virtualizer with specified flags.
3285 * Depending on specified flags the port virtualizer can act as a
3286 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3288 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3289 u16 mac_seid, u16 vsi_seid,
3292 struct i40e_aq_desc desc;
3293 struct i40e_aqc_add_update_pv *cmd =
3294 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3295 struct i40e_aqc_add_update_pv_completion *resp =
3296 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3297 enum i40e_status_code status;
3300 return I40E_ERR_PARAM;
3302 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3303 cmd->command_flags = CPU_TO_LE16(flags);
3304 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3305 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3307 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3308 if (!status && ret_seid)
3309 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3315 * i40e_aq_add_tag - Add an S/E-tag
3316 * @hw: pointer to the hw struct
3317 * @direct_to_queue: should s-tag direct flow to a specific queue
3318 * @vsi_seid: VSI SEID to use this tag
3319 * @tag: value of the tag
3320 * @queue_num: queue number, only valid is direct_to_queue is true
3321 * @tags_used: return value, number of tags in use by this PF
3322 * @tags_free: return value, number of unallocated tags
3323 * @cmd_details: pointer to command details structure or NULL
3325 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3326 * the number of tags allocated by the PF, and the number of unallocated
3329 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3330 u16 vsi_seid, u16 tag, u16 queue_num,
3331 u16 *tags_used, u16 *tags_free,
3332 struct i40e_asq_cmd_details *cmd_details)
3334 struct i40e_aq_desc desc;
3335 struct i40e_aqc_add_tag *cmd =
3336 (struct i40e_aqc_add_tag *)&desc.params.raw;
3337 struct i40e_aqc_add_remove_tag_completion *resp =
3338 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3339 enum i40e_status_code status;
3342 return I40E_ERR_PARAM;
3344 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3346 cmd->seid = CPU_TO_LE16(vsi_seid);
3347 cmd->tag = CPU_TO_LE16(tag);
3348 if (direct_to_queue) {
3349 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3350 cmd->queue_number = CPU_TO_LE16(queue_num);
3353 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3356 if (tags_used != NULL)
3357 *tags_used = LE16_TO_CPU(resp->tags_used);
3358 if (tags_free != NULL)
3359 *tags_free = LE16_TO_CPU(resp->tags_free);
3366 * i40e_aq_remove_tag - Remove an S- or E-tag
3367 * @hw: pointer to the hw struct
3368 * @vsi_seid: VSI SEID this tag is associated with
3369 * @tag: value of the S-tag to delete
3370 * @tags_used: return value, number of tags in use by this PF
3371 * @tags_free: return value, number of unallocated tags
3372 * @cmd_details: pointer to command details structure or NULL
3374 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3375 * the number of tags allocated by the PF, and the number of unallocated
3378 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3379 u16 tag, u16 *tags_used, u16 *tags_free,
3380 struct i40e_asq_cmd_details *cmd_details)
3382 struct i40e_aq_desc desc;
3383 struct i40e_aqc_remove_tag *cmd =
3384 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3385 struct i40e_aqc_add_remove_tag_completion *resp =
3386 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3387 enum i40e_status_code status;
3390 return I40E_ERR_PARAM;
3392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3394 cmd->seid = CPU_TO_LE16(vsi_seid);
3395 cmd->tag = CPU_TO_LE16(tag);
3397 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3400 if (tags_used != NULL)
3401 *tags_used = LE16_TO_CPU(resp->tags_used);
3402 if (tags_free != NULL)
3403 *tags_free = LE16_TO_CPU(resp->tags_free);
3410 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3411 * @hw: pointer to the hw struct
3412 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3413 * @etag: value of E-tag to add
3414 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3415 * @buf: address of indirect buffer
3416 * @tags_used: return value, number of E-tags in use by this port
3417 * @tags_free: return value, number of unallocated M-tags
3418 * @cmd_details: pointer to command details structure or NULL
3420 * This associates a multicast E-tag to a port virtualizer. It will return
3421 * the number of tags allocated by the PF, and the number of unallocated
3424 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3425 * num_tags_in_buf long.
3427 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3428 u16 etag, u8 num_tags_in_buf, void *buf,
3429 u16 *tags_used, u16 *tags_free,
3430 struct i40e_asq_cmd_details *cmd_details)
3432 struct i40e_aq_desc desc;
3433 struct i40e_aqc_add_remove_mcast_etag *cmd =
3434 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3435 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3436 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3437 enum i40e_status_code status;
3438 u16 length = sizeof(u16) * num_tags_in_buf;
3440 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3441 return I40E_ERR_PARAM;
3443 i40e_fill_default_direct_cmd_desc(&desc,
3444 i40e_aqc_opc_add_multicast_etag);
3446 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3447 cmd->etag = CPU_TO_LE16(etag);
3448 cmd->num_unicast_etags = num_tags_in_buf;
3450 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3451 if (length > I40E_AQ_LARGE_BUF)
3452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3454 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3457 if (tags_used != NULL)
3458 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3459 if (tags_free != NULL)
3460 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3467 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3468 * @hw: pointer to the hw struct
3469 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3470 * @etag: value of the E-tag to remove
3471 * @tags_used: return value, number of tags in use by this port
3472 * @tags_free: return value, number of unallocated tags
3473 * @cmd_details: pointer to command details structure or NULL
3475 * This deletes an E-tag from the port virtualizer. It will return
3476 * the number of tags allocated by the port, and the number of unallocated
3479 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3480 u16 etag, u16 *tags_used, u16 *tags_free,
3481 struct i40e_asq_cmd_details *cmd_details)
3483 struct i40e_aq_desc desc;
3484 struct i40e_aqc_add_remove_mcast_etag *cmd =
3485 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3486 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3487 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3488 enum i40e_status_code status;
3492 return I40E_ERR_PARAM;
3494 i40e_fill_default_direct_cmd_desc(&desc,
3495 i40e_aqc_opc_remove_multicast_etag);
3497 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3498 cmd->etag = CPU_TO_LE16(etag);
3500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3503 if (tags_used != NULL)
3504 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3505 if (tags_free != NULL)
3506 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3513 * i40e_aq_update_tag - Update an S/E-tag
3514 * @hw: pointer to the hw struct
3515 * @vsi_seid: VSI SEID using this S-tag
3516 * @old_tag: old tag value
3517 * @new_tag: new tag value
3518 * @tags_used: return value, number of tags in use by this PF
3519 * @tags_free: return value, number of unallocated tags
3520 * @cmd_details: pointer to command details structure or NULL
3522 * This updates the value of the tag currently attached to this VSI
3523 * in the switch complex. It will return the number of tags allocated
3524 * by the PF, and the number of unallocated tags available.
3526 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3527 u16 old_tag, u16 new_tag, u16 *tags_used,
3529 struct i40e_asq_cmd_details *cmd_details)
3531 struct i40e_aq_desc desc;
3532 struct i40e_aqc_update_tag *cmd =
3533 (struct i40e_aqc_update_tag *)&desc.params.raw;
3534 struct i40e_aqc_update_tag_completion *resp =
3535 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3536 enum i40e_status_code status;
3539 return I40E_ERR_PARAM;
3541 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3543 cmd->seid = CPU_TO_LE16(vsi_seid);
3544 cmd->old_tag = CPU_TO_LE16(old_tag);
3545 cmd->new_tag = CPU_TO_LE16(new_tag);
3547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3550 if (tags_used != NULL)
3551 *tags_used = LE16_TO_CPU(resp->tags_used);
3552 if (tags_free != NULL)
3553 *tags_free = LE16_TO_CPU(resp->tags_free);
3560 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3561 * @hw: pointer to the hw struct
3562 * @tcmap: TC map for request/release any ignore PFC condition
3563 * @request: request or release ignore PFC condition
3564 * @tcmap_ret: return TCs for which PFC is currently ignored
3565 * @cmd_details: pointer to command details structure or NULL
3567 * This sends out request/release to ignore PFC condition for a TC.
3568 * It will return the TCs for which PFC is currently ignored.
3570 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3571 bool request, u8 *tcmap_ret,
3572 struct i40e_asq_cmd_details *cmd_details)
3574 struct i40e_aq_desc desc;
3575 struct i40e_aqc_pfc_ignore *cmd_resp =
3576 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3577 enum i40e_status_code status;
3579 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3582 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3584 cmd_resp->tc_bitmap = tcmap;
3586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3589 if (tcmap_ret != NULL)
3590 *tcmap_ret = cmd_resp->tc_bitmap;
3597 * i40e_aq_dcb_updated - DCB Updated Command
3598 * @hw: pointer to the hw struct
3599 * @cmd_details: pointer to command details structure or NULL
3601 * When LLDP is handled in PF this command is used by the PF
3602 * to notify EMP that a DCB setting is modified.
3603 * When LLDP is handled in EMP this command is used by the PF
3604 * to notify EMP whenever one of the following parameters get
3606 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3607 * - PCIRTT in PRTDCB_GENC.PCIRTT
3608 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3609 * EMP will return when the shared RPB settings have been
3610 * recomputed and modified. The retval field in the descriptor
3611 * will be set to 0 when RPB is modified.
3613 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3614 struct i40e_asq_cmd_details *cmd_details)
3616 struct i40e_aq_desc desc;
3617 enum i40e_status_code status;
3619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3627 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3628 * @hw: pointer to the hw struct
3629 * @seid: defines the SEID of the switch for which the stats are requested
3630 * @vlan_id: the VLAN ID for which the statistics are requested
3631 * @stat_index: index of the statistics counters block assigned to this VLAN
3632 * @cmd_details: pointer to command details structure or NULL
3634 * XL710 supports 128 smonVlanStats counters.This command is used to
3635 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3638 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3639 u16 vlan_id, u16 *stat_index,
3640 struct i40e_asq_cmd_details *cmd_details)
3642 struct i40e_aq_desc desc;
3643 struct i40e_aqc_add_remove_statistics *cmd_resp =
3644 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3645 enum i40e_status_code status;
3647 if ((seid == 0) || (stat_index == NULL))
3648 return I40E_ERR_PARAM;
3650 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3652 cmd_resp->seid = CPU_TO_LE16(seid);
3653 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3658 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3664 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3665 * @hw: pointer to the hw struct
3666 * @seid: defines the SEID of the switch for which the stats are requested
3667 * @vlan_id: the VLAN ID for which the statistics are requested
3668 * @stat_index: index of the statistics counters block assigned to this VLAN
3669 * @cmd_details: pointer to command details structure or NULL
3671 * XL710 supports 128 smonVlanStats counters.This command is used to
3672 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3675 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3676 u16 vlan_id, u16 stat_index,
3677 struct i40e_asq_cmd_details *cmd_details)
3679 struct i40e_aq_desc desc;
3680 struct i40e_aqc_add_remove_statistics *cmd =
3681 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3682 enum i40e_status_code status;
3685 return I40E_ERR_PARAM;
3687 i40e_fill_default_direct_cmd_desc(&desc,
3688 i40e_aqc_opc_remove_statistics);
3690 cmd->seid = CPU_TO_LE16(seid);
3691 cmd->vlan = CPU_TO_LE16(vlan_id);
3692 cmd->stat_index = CPU_TO_LE16(stat_index);
3694 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3700 * i40e_aq_set_port_parameters - set physical port parameters.
3701 * @hw: pointer to the hw struct
3702 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3703 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3704 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3705 * @double_vlan: if set double VLAN is enabled
3706 * @cmd_details: pointer to command details structure or NULL
3708 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3709 u16 bad_frame_vsi, bool save_bad_pac,
3710 bool pad_short_pac, bool double_vlan,
3711 struct i40e_asq_cmd_details *cmd_details)
3713 struct i40e_aqc_set_port_parameters *cmd;
3714 enum i40e_status_code status;
3715 struct i40e_aq_desc desc;
3716 u16 command_flags = 0;
3718 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3720 i40e_fill_default_direct_cmd_desc(&desc,
3721 i40e_aqc_opc_set_port_parameters);
3723 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3725 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3727 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3729 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3730 cmd->command_flags = CPU_TO_LE16(command_flags);
3732 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3738 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3739 * @hw: pointer to the hw struct
3740 * @seid: seid for the physical port/switching component/vsi
3741 * @buff: Indirect buffer to hold data parameters and response
3742 * @buff_size: Indirect buffer size
3743 * @opcode: Tx scheduler AQ command opcode
3744 * @cmd_details: pointer to command details structure or NULL
3746 * Generic command handler for Tx scheduler AQ commands
3748 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3749 void *buff, u16 buff_size,
3750 enum i40e_admin_queue_opc opcode,
3751 struct i40e_asq_cmd_details *cmd_details)
3753 struct i40e_aq_desc desc;
3754 struct i40e_aqc_tx_sched_ind *cmd =
3755 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3756 enum i40e_status_code status;
3757 bool cmd_param_flag = false;
3760 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3761 case i40e_aqc_opc_configure_vsi_tc_bw:
3762 case i40e_aqc_opc_enable_switching_comp_ets:
3763 case i40e_aqc_opc_modify_switching_comp_ets:
3764 case i40e_aqc_opc_disable_switching_comp_ets:
3765 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3766 case i40e_aqc_opc_configure_switching_comp_bw_config:
3767 cmd_param_flag = true;
3769 case i40e_aqc_opc_query_vsi_bw_config:
3770 case i40e_aqc_opc_query_vsi_ets_sla_config:
3771 case i40e_aqc_opc_query_switching_comp_ets_config:
3772 case i40e_aqc_opc_query_port_ets_config:
3773 case i40e_aqc_opc_query_switching_comp_bw_config:
3774 cmd_param_flag = false;
3777 return I40E_ERR_PARAM;
3780 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3782 /* Indirect command */
3783 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3785 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3786 if (buff_size > I40E_AQ_LARGE_BUF)
3787 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3789 desc.datalen = CPU_TO_LE16(buff_size);
3791 cmd->vsi_seid = CPU_TO_LE16(seid);
3793 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3799 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3800 * @hw: pointer to the hw struct
3802 * @credit: BW limit credits (0 = disabled)
3803 * @max_credit: Max BW limit credits
3804 * @cmd_details: pointer to command details structure or NULL
3806 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3807 u16 seid, u16 credit, u8 max_credit,
3808 struct i40e_asq_cmd_details *cmd_details)
3810 struct i40e_aq_desc desc;
3811 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3812 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3813 enum i40e_status_code status;
3815 i40e_fill_default_direct_cmd_desc(&desc,
3816 i40e_aqc_opc_configure_vsi_bw_limit);
3818 cmd->vsi_seid = CPU_TO_LE16(seid);
3819 cmd->credit = CPU_TO_LE16(credit);
3820 cmd->max_credit = max_credit;
3822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3828 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3829 * @hw: pointer to the hw struct
3830 * @seid: switching component seid
3831 * @credit: BW limit credits (0 = disabled)
3832 * @max_bw: Max BW limit credits
3833 * @cmd_details: pointer to command details structure or NULL
3835 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3836 u16 seid, u16 credit, u8 max_bw,
3837 struct i40e_asq_cmd_details *cmd_details)
3839 struct i40e_aq_desc desc;
3840 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3841 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3842 enum i40e_status_code status;
3844 i40e_fill_default_direct_cmd_desc(&desc,
3845 i40e_aqc_opc_configure_switching_comp_bw_limit);
3847 cmd->seid = CPU_TO_LE16(seid);
3848 cmd->credit = CPU_TO_LE16(credit);
3849 cmd->max_bw = max_bw;
3851 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3857 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3858 * @hw: pointer to the hw struct
3860 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3861 * @cmd_details: pointer to command details structure or NULL
3863 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3865 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3866 struct i40e_asq_cmd_details *cmd_details)
3868 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3869 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3874 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3875 * @hw: pointer to the hw struct
3877 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3878 * @cmd_details: pointer to command details structure or NULL
3880 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3882 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3883 struct i40e_asq_cmd_details *cmd_details)
3885 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3886 i40e_aqc_opc_configure_vsi_tc_bw,
3891 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
3892 * @hw: pointer to the hw struct
3893 * @seid: seid of the switching component
3894 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3895 * @cmd_details: pointer to command details structure or NULL
3897 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
3898 struct i40e_hw *hw, u16 seid,
3899 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
3900 struct i40e_asq_cmd_details *cmd_details)
3902 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3903 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
3908 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3909 * @hw: pointer to the hw struct
3910 * @seid: seid of the VSI
3911 * @bw_data: Buffer to hold VSI BW configuration
3912 * @cmd_details: pointer to command details structure or NULL
3914 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3916 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3917 struct i40e_asq_cmd_details *cmd_details)
3919 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3920 i40e_aqc_opc_query_vsi_bw_config,
3925 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3926 * @hw: pointer to the hw struct
3927 * @seid: seid of the VSI
3928 * @bw_data: Buffer to hold VSI BW configuration per TC
3929 * @cmd_details: pointer to command details structure or NULL
3931 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3933 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3934 struct i40e_asq_cmd_details *cmd_details)
3936 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3937 i40e_aqc_opc_query_vsi_ets_sla_config,
3942 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3943 * @hw: pointer to the hw struct
3944 * @seid: seid of the switching component
3945 * @bw_data: Buffer to hold switching component's per TC BW config
3946 * @cmd_details: pointer to command details structure or NULL
3948 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3950 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3951 struct i40e_asq_cmd_details *cmd_details)
3953 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3954 i40e_aqc_opc_query_switching_comp_ets_config,
3959 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3960 * @hw: pointer to the hw struct
3961 * @seid: seid of the VSI or switching component connected to Physical Port
3962 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3963 * @cmd_details: pointer to command details structure or NULL
3965 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3967 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3968 struct i40e_asq_cmd_details *cmd_details)
3970 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3971 i40e_aqc_opc_query_port_ets_config,
3976 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3977 * @hw: pointer to the hw struct
3978 * @seid: seid of the switching component
3979 * @bw_data: Buffer to hold switching component's BW configuration
3980 * @cmd_details: pointer to command details structure or NULL
3982 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3984 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3985 struct i40e_asq_cmd_details *cmd_details)
3987 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3988 i40e_aqc_opc_query_switching_comp_bw_config,
3993 * i40e_validate_filter_settings
3994 * @hw: pointer to the hardware structure
3995 * @settings: Filter control settings
3997 * Check and validate the filter control settings passed.
3998 * The function checks for the valid filter/context sizes being
3999 * passed for FCoE and PE.
4001 * Returns I40E_SUCCESS if the values passed are valid and within
4002 * range else returns an error.
4004 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4005 struct i40e_filter_control_settings *settings)
4007 u32 fcoe_cntx_size, fcoe_filt_size;
4008 u32 pe_cntx_size, pe_filt_size;
4013 /* Validate FCoE settings passed */
4014 switch (settings->fcoe_filt_num) {
4015 case I40E_HASH_FILTER_SIZE_1K:
4016 case I40E_HASH_FILTER_SIZE_2K:
4017 case I40E_HASH_FILTER_SIZE_4K:
4018 case I40E_HASH_FILTER_SIZE_8K:
4019 case I40E_HASH_FILTER_SIZE_16K:
4020 case I40E_HASH_FILTER_SIZE_32K:
4021 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4022 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4025 return I40E_ERR_PARAM;
4028 switch (settings->fcoe_cntx_num) {
4029 case I40E_DMA_CNTX_SIZE_512:
4030 case I40E_DMA_CNTX_SIZE_1K:
4031 case I40E_DMA_CNTX_SIZE_2K:
4032 case I40E_DMA_CNTX_SIZE_4K:
4033 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4034 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4037 return I40E_ERR_PARAM;
4040 /* Validate PE settings passed */
4041 switch (settings->pe_filt_num) {
4042 case I40E_HASH_FILTER_SIZE_1K:
4043 case I40E_HASH_FILTER_SIZE_2K:
4044 case I40E_HASH_FILTER_SIZE_4K:
4045 case I40E_HASH_FILTER_SIZE_8K:
4046 case I40E_HASH_FILTER_SIZE_16K:
4047 case I40E_HASH_FILTER_SIZE_32K:
4048 case I40E_HASH_FILTER_SIZE_64K:
4049 case I40E_HASH_FILTER_SIZE_128K:
4050 case I40E_HASH_FILTER_SIZE_256K:
4051 case I40E_HASH_FILTER_SIZE_512K:
4052 case I40E_HASH_FILTER_SIZE_1M:
4053 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4054 pe_filt_size <<= (u32)settings->pe_filt_num;
4057 return I40E_ERR_PARAM;
4060 switch (settings->pe_cntx_num) {
4061 case I40E_DMA_CNTX_SIZE_512:
4062 case I40E_DMA_CNTX_SIZE_1K:
4063 case I40E_DMA_CNTX_SIZE_2K:
4064 case I40E_DMA_CNTX_SIZE_4K:
4065 case I40E_DMA_CNTX_SIZE_8K:
4066 case I40E_DMA_CNTX_SIZE_16K:
4067 case I40E_DMA_CNTX_SIZE_32K:
4068 case I40E_DMA_CNTX_SIZE_64K:
4069 case I40E_DMA_CNTX_SIZE_128K:
4070 case I40E_DMA_CNTX_SIZE_256K:
4071 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4072 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4075 return I40E_ERR_PARAM;
4078 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4079 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4080 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4081 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4082 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4083 return I40E_ERR_INVALID_SIZE;
4085 return I40E_SUCCESS;
4089 * i40e_set_filter_control
4090 * @hw: pointer to the hardware structure
4091 * @settings: Filter control settings
4093 * Set the Queue Filters for PE/FCoE and enable filters required
4094 * for a single PF. It is expected that these settings are programmed
4095 * at the driver initialization time.
4097 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4098 struct i40e_filter_control_settings *settings)
4100 enum i40e_status_code ret = I40E_SUCCESS;
4101 u32 hash_lut_size = 0;
4105 return I40E_ERR_PARAM;
4107 /* Validate the input settings */
4108 ret = i40e_validate_filter_settings(hw, settings);
4112 /* Read the PF Queue Filter control register */
4113 val = rd32(hw, I40E_PFQF_CTL_0);
4115 /* Program required PE hash buckets for the PF */
4116 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4117 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4118 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4119 /* Program required PE contexts for the PF */
4120 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4121 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4122 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4124 /* Program required FCoE hash buckets for the PF */
4125 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4126 val |= ((u32)settings->fcoe_filt_num <<
4127 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4128 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4129 /* Program required FCoE DDP contexts for the PF */
4130 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4131 val |= ((u32)settings->fcoe_cntx_num <<
4132 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4133 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4135 /* Program Hash LUT size for the PF */
4136 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4137 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4139 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4140 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4142 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4143 if (settings->enable_fdir)
4144 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4145 if (settings->enable_ethtype)
4146 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4147 if (settings->enable_macvlan)
4148 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4150 wr32(hw, I40E_PFQF_CTL_0, val);
4152 return I40E_SUCCESS;
4156 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4157 * @hw: pointer to the hw struct
4158 * @mac_addr: MAC address to use in the filter
4159 * @ethtype: Ethertype to use in the filter
4160 * @flags: Flags that needs to be applied to the filter
4161 * @vsi_seid: seid of the control VSI
4162 * @queue: VSI queue number to send the packet to
4163 * @is_add: Add control packet filter if True else remove
4164 * @stats: Structure to hold information on control filter counts
4165 * @cmd_details: pointer to command details structure or NULL
4167 * This command will Add or Remove control packet filter for a control VSI.
4168 * In return it will update the total number of perfect filter count in
4171 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4172 u8 *mac_addr, u16 ethtype, u16 flags,
4173 u16 vsi_seid, u16 queue, bool is_add,
4174 struct i40e_control_filter_stats *stats,
4175 struct i40e_asq_cmd_details *cmd_details)
4177 struct i40e_aq_desc desc;
4178 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4179 (struct i40e_aqc_add_remove_control_packet_filter *)
4181 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4182 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4184 enum i40e_status_code status;
4187 return I40E_ERR_PARAM;
4190 i40e_fill_default_direct_cmd_desc(&desc,
4191 i40e_aqc_opc_add_control_packet_filter);
4192 cmd->queue = CPU_TO_LE16(queue);
4194 i40e_fill_default_direct_cmd_desc(&desc,
4195 i40e_aqc_opc_remove_control_packet_filter);
4199 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4200 I40E_NONDMA_TO_NONDMA);
4202 cmd->etype = CPU_TO_LE16(ethtype);
4203 cmd->flags = CPU_TO_LE16(flags);
4204 cmd->seid = CPU_TO_LE16(vsi_seid);
4206 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4208 if (!status && stats) {
4209 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4210 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4211 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4212 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4219 * i40e_aq_add_cloud_filters
4220 * @hw: pointer to the hardware structure
4221 * @seid: VSI seid to add cloud filters from
4222 * @filters: Buffer which contains the filters to be added
4223 * @filter_count: number of filters contained in the buffer
4225 * Set the cloud filters for a given VSI. The contents of the
4226 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4227 * in by the caller of the function.
4230 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4232 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4235 struct i40e_aq_desc desc;
4236 struct i40e_aqc_add_remove_cloud_filters *cmd =
4237 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4239 enum i40e_status_code status;
4241 i40e_fill_default_direct_cmd_desc(&desc,
4242 i40e_aqc_opc_add_cloud_filters);
4244 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4246 desc.datalen = CPU_TO_LE16(buff_len);
4247 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4248 cmd->num_filters = filter_count;
4249 cmd->seid = CPU_TO_LE16(seid);
4251 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4257 * i40e_aq_remove_cloud_filters
4258 * @hw: pointer to the hardware structure
4259 * @seid: VSI seid to remove cloud filters from
4260 * @filters: Buffer which contains the filters to be removed
4261 * @filter_count: number of filters contained in the buffer
4263 * Remove the cloud filters for a given VSI. The contents of the
4264 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4265 * in by the caller of the function.
4268 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4270 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4273 struct i40e_aq_desc desc;
4274 struct i40e_aqc_add_remove_cloud_filters *cmd =
4275 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4276 enum i40e_status_code status;
4279 i40e_fill_default_direct_cmd_desc(&desc,
4280 i40e_aqc_opc_remove_cloud_filters);
4282 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4284 desc.datalen = CPU_TO_LE16(buff_len);
4285 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4286 cmd->num_filters = filter_count;
4287 cmd->seid = CPU_TO_LE16(seid);
4289 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4295 * i40e_aq_alternate_write
4296 * @hw: pointer to the hardware structure
4297 * @reg_addr0: address of first dword to be read
4298 * @reg_val0: value to be written under 'reg_addr0'
4299 * @reg_addr1: address of second dword to be read
4300 * @reg_val1: value to be written under 'reg_addr1'
4302 * Write one or two dwords to alternate structure. Fields are indicated
4303 * by 'reg_addr0' and 'reg_addr1' register numbers.
4306 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4307 u32 reg_addr0, u32 reg_val0,
4308 u32 reg_addr1, u32 reg_val1)
4310 struct i40e_aq_desc desc;
4311 struct i40e_aqc_alternate_write *cmd_resp =
4312 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4313 enum i40e_status_code status;
4315 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4316 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4317 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4318 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4319 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4321 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4327 * i40e_aq_alternate_write_indirect
4328 * @hw: pointer to the hardware structure
4329 * @addr: address of a first register to be modified
4330 * @dw_count: number of alternate structure fields to write
4331 * @buffer: pointer to the command buffer
4333 * Write 'dw_count' dwords from 'buffer' to alternate structure
4334 * starting at 'addr'.
4337 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4338 u32 addr, u32 dw_count, void *buffer)
4340 struct i40e_aq_desc desc;
4341 struct i40e_aqc_alternate_ind_write *cmd_resp =
4342 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4343 enum i40e_status_code status;
4346 return I40E_ERR_PARAM;
4348 /* Indirect command */
4349 i40e_fill_default_direct_cmd_desc(&desc,
4350 i40e_aqc_opc_alternate_write_indirect);
4352 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4353 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4354 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4355 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4357 cmd_resp->address = CPU_TO_LE32(addr);
4358 cmd_resp->length = CPU_TO_LE32(dw_count);
4359 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4360 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4362 status = i40e_asq_send_command(hw, &desc, buffer,
4363 I40E_LO_DWORD(4*dw_count), NULL);
4369 * i40e_aq_alternate_read
4370 * @hw: pointer to the hardware structure
4371 * @reg_addr0: address of first dword to be read
4372 * @reg_val0: pointer for data read from 'reg_addr0'
4373 * @reg_addr1: address of second dword to be read
4374 * @reg_val1: pointer for data read from 'reg_addr1'
4376 * Read one or two dwords from alternate structure. Fields are indicated
4377 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4378 * is not passed then only register at 'reg_addr0' is read.
4381 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4382 u32 reg_addr0, u32 *reg_val0,
4383 u32 reg_addr1, u32 *reg_val1)
4385 struct i40e_aq_desc desc;
4386 struct i40e_aqc_alternate_write *cmd_resp =
4387 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4388 enum i40e_status_code status;
4390 if (reg_val0 == NULL)
4391 return I40E_ERR_PARAM;
4393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4394 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4395 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4397 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4399 if (status == I40E_SUCCESS) {
4400 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4402 if (reg_val1 != NULL)
4403 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4410 * i40e_aq_alternate_read_indirect
4411 * @hw: pointer to the hardware structure
4412 * @addr: address of the alternate structure field
4413 * @dw_count: number of alternate structure fields to read
4414 * @buffer: pointer to the command buffer
4416 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4417 * place them in 'buffer'. The buffer should be allocated by caller.
4420 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4421 u32 addr, u32 dw_count, void *buffer)
4423 struct i40e_aq_desc desc;
4424 struct i40e_aqc_alternate_ind_write *cmd_resp =
4425 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4426 enum i40e_status_code status;
4429 return I40E_ERR_PARAM;
4431 /* Indirect command */
4432 i40e_fill_default_direct_cmd_desc(&desc,
4433 i40e_aqc_opc_alternate_read_indirect);
4435 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4436 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4437 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4438 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4440 cmd_resp->address = CPU_TO_LE32(addr);
4441 cmd_resp->length = CPU_TO_LE32(dw_count);
4442 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4443 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4445 status = i40e_asq_send_command(hw, &desc, buffer,
4446 I40E_LO_DWORD(4*dw_count), NULL);
4452 * i40e_aq_alternate_clear
4453 * @hw: pointer to the HW structure.
4455 * Clear the alternate structures of the port from which the function
4459 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4461 struct i40e_aq_desc desc;
4462 enum i40e_status_code status;
4464 i40e_fill_default_direct_cmd_desc(&desc,
4465 i40e_aqc_opc_alternate_clear_port);
4467 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4473 * i40e_aq_alternate_write_done
4474 * @hw: pointer to the HW structure.
4475 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4476 * @reset_needed: indicates the SW should trigger GLOBAL reset
4478 * Indicates to the FW that alternate structures have been changed.
4481 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4482 u8 bios_mode, bool *reset_needed)
4484 struct i40e_aq_desc desc;
4485 struct i40e_aqc_alternate_write_done *cmd =
4486 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4487 enum i40e_status_code status;
4489 if (reset_needed == NULL)
4490 return I40E_ERR_PARAM;
4492 i40e_fill_default_direct_cmd_desc(&desc,
4493 i40e_aqc_opc_alternate_write_done);
4495 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4497 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4499 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4500 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4506 * i40e_aq_set_oem_mode
4507 * @hw: pointer to the HW structure.
4508 * @oem_mode: the OEM mode to be used
4510 * Sets the device to a specific operating mode. Currently the only supported
4511 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4514 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4517 struct i40e_aq_desc desc;
4518 struct i40e_aqc_alternate_write_done *cmd =
4519 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4520 enum i40e_status_code status;
4522 i40e_fill_default_direct_cmd_desc(&desc,
4523 i40e_aqc_opc_alternate_set_mode);
4525 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4527 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4533 * i40e_aq_resume_port_tx
4534 * @hw: pointer to the hardware structure
4535 * @cmd_details: pointer to command details structure or NULL
4537 * Resume port's Tx traffic
4539 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4540 struct i40e_asq_cmd_details *cmd_details)
4542 struct i40e_aq_desc desc;
4543 enum i40e_status_code status;
4545 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4553 * i40e_set_pci_config_data - store PCI bus info
4554 * @hw: pointer to hardware structure
4555 * @link_status: the link status word from PCI config space
4557 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4559 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4561 hw->bus.type = i40e_bus_type_pci_express;
4563 switch (link_status & I40E_PCI_LINK_WIDTH) {
4564 case I40E_PCI_LINK_WIDTH_1:
4565 hw->bus.width = i40e_bus_width_pcie_x1;
4567 case I40E_PCI_LINK_WIDTH_2:
4568 hw->bus.width = i40e_bus_width_pcie_x2;
4570 case I40E_PCI_LINK_WIDTH_4:
4571 hw->bus.width = i40e_bus_width_pcie_x4;
4573 case I40E_PCI_LINK_WIDTH_8:
4574 hw->bus.width = i40e_bus_width_pcie_x8;
4577 hw->bus.width = i40e_bus_width_unknown;
4581 switch (link_status & I40E_PCI_LINK_SPEED) {
4582 case I40E_PCI_LINK_SPEED_2500:
4583 hw->bus.speed = i40e_bus_speed_2500;
4585 case I40E_PCI_LINK_SPEED_5000:
4586 hw->bus.speed = i40e_bus_speed_5000;
4588 case I40E_PCI_LINK_SPEED_8000:
4589 hw->bus.speed = i40e_bus_speed_8000;
4592 hw->bus.speed = i40e_bus_speed_unknown;
4598 * i40e_read_bw_from_alt_ram
4599 * @hw: pointer to the hardware structure
4600 * @max_bw: pointer for max_bw read
4601 * @min_bw: pointer for min_bw read
4602 * @min_valid: pointer for bool that is true if min_bw is a valid value
4603 * @max_valid: pointer for bool that is true if max_bw is a valid value
4605 * Read bw from the alternate ram for the given pf
4607 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4608 u32 *max_bw, u32 *min_bw,
4609 bool *min_valid, bool *max_valid)
4611 enum i40e_status_code status;
4612 u32 max_bw_addr, min_bw_addr;
4614 /* Calculate the address of the min/max bw registers */
4615 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4616 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4617 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4618 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4619 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4620 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4622 /* Read the bandwidths from alt ram */
4623 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4624 min_bw_addr, min_bw);
4626 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4631 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4640 * i40e_aq_configure_partition_bw
4641 * @hw: pointer to the hardware structure
4642 * @bw_data: Buffer holding valid pfs and bw limits
4643 * @cmd_details: pointer to command details
4645 * Configure partitions guaranteed/max bw
4647 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4648 struct i40e_aqc_configure_partition_bw_data *bw_data,
4649 struct i40e_asq_cmd_details *cmd_details)
4651 enum i40e_status_code status;
4652 struct i40e_aq_desc desc;
4653 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4655 i40e_fill_default_direct_cmd_desc(&desc,
4656 i40e_aqc_opc_configure_partition_bw);
4658 /* Indirect command */
4659 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4660 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4662 if (bwd_size > I40E_AQ_LARGE_BUF)
4663 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4665 desc.datalen = CPU_TO_LE16(bwd_size);
4667 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4673 * i40e_aq_send_msg_to_pf
4674 * @hw: pointer to the hardware structure
4675 * @v_opcode: opcodes for VF-PF communication
4676 * @v_retval: return error code
4677 * @msg: pointer to the msg buffer
4678 * @msglen: msg length
4679 * @cmd_details: pointer to command details
4681 * Send message to PF driver using admin queue. By default, this message
4682 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4683 * completion before returning.
4685 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4686 enum i40e_virtchnl_ops v_opcode,
4687 enum i40e_status_code v_retval,
4688 u8 *msg, u16 msglen,
4689 struct i40e_asq_cmd_details *cmd_details)
4691 struct i40e_aq_desc desc;
4692 struct i40e_asq_cmd_details details;
4693 enum i40e_status_code status;
4695 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4696 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4697 desc.cookie_high = CPU_TO_LE32(v_opcode);
4698 desc.cookie_low = CPU_TO_LE32(v_retval);
4700 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4701 | I40E_AQ_FLAG_RD));
4702 if (msglen > I40E_AQ_LARGE_BUF)
4703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4704 desc.datalen = CPU_TO_LE16(msglen);
4707 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4708 details.async = true;
4709 cmd_details = &details;
4711 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4712 msglen, cmd_details);
4717 * i40e_vf_parse_hw_config
4718 * @hw: pointer to the hardware structure
4719 * @msg: pointer to the virtual channel VF resource structure
4721 * Given a VF resource message from the PF, populate the hw struct
4722 * with appropriate information.
4724 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4725 struct i40e_virtchnl_vf_resource *msg)
4727 struct i40e_virtchnl_vsi_resource *vsi_res;
4730 vsi_res = &msg->vsi_res[0];
4732 hw->dev_caps.num_vsis = msg->num_vsis;
4733 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4734 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4735 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4736 hw->dev_caps.dcb = msg->vf_offload_flags &
4737 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4738 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4739 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4740 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4741 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4742 for (i = 0; i < msg->num_vsis; i++) {
4743 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4744 i40e_memcpy(hw->mac.perm_addr,
4745 vsi_res->default_mac_addr,
4746 I40E_ETH_LENGTH_OF_ADDRESS,
4747 I40E_NONDMA_TO_NONDMA);
4748 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4749 I40E_ETH_LENGTH_OF_ADDRESS,
4750 I40E_NONDMA_TO_NONDMA);
4758 * @hw: pointer to the hardware structure
4760 * Send a VF_RESET message to the PF. Does not wait for response from PF
4761 * as none will be forthcoming. Immediately after calling this function,
4762 * the admin queue should be shut down and (optionally) reinitialized.
4764 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4766 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4767 I40E_SUCCESS, NULL, 0, NULL);
4769 #endif /* VF_DRIVER */