1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *buf = (u8 *)buffer;
104 if ((!(mask & hw->debug_mask)) || (desc == NULL))
108 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
109 LE16_TO_CPU(aq_desc->opcode),
110 LE16_TO_CPU(aq_desc->flags),
111 LE16_TO_CPU(aq_desc->datalen),
112 LE16_TO_CPU(aq_desc->retval));
113 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
114 LE32_TO_CPU(aq_desc->cookie_high),
115 LE32_TO_CPU(aq_desc->cookie_low));
116 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
117 LE32_TO_CPU(aq_desc->params.internal.param0),
118 LE32_TO_CPU(aq_desc->params.internal.param1));
119 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
120 LE32_TO_CPU(aq_desc->params.external.addr_high),
121 LE32_TO_CPU(aq_desc->params.external.addr_low));
123 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
124 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
127 /* write the full 16-byte chunks */
128 for (i = 0; i < (len - 16); i += 16)
130 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
131 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
132 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
133 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
134 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
135 /* write whatever's left over without overrunning the buffer */
140 memset(d_buf, 0, sizeof(d_buf));
141 j += sprintf(d_buf, "\t0x%04X ", i);
143 j += sprintf(&d_buf[j], " %02X", buf[i++]);
144 i40e_debug(hw, mask, "%s\n", d_buf);
150 * i40e_check_asq_alive
151 * @hw: pointer to the hw struct
153 * Returns true if Queue is enabled else false.
155 bool i40e_check_asq_alive(struct i40e_hw *hw)
158 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
164 * i40e_aq_queue_shutdown
165 * @hw: pointer to the hw struct
166 * @unloading: is the driver unloading itself
168 * Tell the Firmware that we're shutting down the AdminQ and whether
169 * or not the driver is unloading as well.
171 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
174 struct i40e_aq_desc desc;
175 struct i40e_aqc_queue_shutdown *cmd =
176 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
177 enum i40e_status_code status;
179 i40e_fill_default_direct_cmd_desc(&desc,
180 i40e_aqc_opc_queue_shutdown);
183 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
189 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
190 * hardware to a bit-field that can be used by SW to more easily determine the
193 * Macros are used to shorten the table lines and make this table human
196 * We store the PTYPE in the top byte of the bit field - this is just so that
197 * we can check that the table doesn't have a row missing, as the index into
198 * the table should be the PTYPE.
202 * IF NOT i40e_ptype_lookup[ptype].known
205 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
206 * Use the rest of the fields to look at the tunnels, inner protocols, etc
208 * Use the enum i40e_rx_l2_ptype to decode the packet type
212 /* macro to make the table lines short */
213 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
216 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
217 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
218 I40E_RX_PTYPE_##OUTER_FRAG, \
219 I40E_RX_PTYPE_TUNNEL_##T, \
220 I40E_RX_PTYPE_TUNNEL_END_##TE, \
221 I40E_RX_PTYPE_##TEF, \
222 I40E_RX_PTYPE_INNER_PROT_##I, \
223 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
225 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
226 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
228 /* shorter macros makes the table fit but are terse */
229 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
230 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
231 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
233 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
234 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
235 /* L2 Packet types */
236 I40E_PTT_UNUSED_ENTRY(0),
237 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
239 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(4),
241 I40E_PTT_UNUSED_ENTRY(5),
242 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(8),
245 I40E_PTT_UNUSED_ENTRY(9),
246 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
248 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 /* Non Tunneled IPv4 */
260 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(25),
264 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
265 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
266 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
269 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
270 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
271 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(32),
273 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
274 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
275 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
278 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
279 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
280 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
281 I40E_PTT_UNUSED_ENTRY(39),
282 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
283 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
284 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
286 /* IPv4 --> GRE/NAT */
287 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
289 /* IPv4 --> GRE/NAT --> IPv4 */
290 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
291 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
292 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(47),
294 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
295 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
296 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> IPv6 */
299 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
300 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
301 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
302 I40E_PTT_UNUSED_ENTRY(54),
303 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
304 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
305 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
307 /* IPv4 --> GRE/NAT --> MAC */
308 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
310 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
311 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
312 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
313 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(62),
315 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
316 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
317 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
320 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
321 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
322 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
323 I40E_PTT_UNUSED_ENTRY(69),
324 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
325 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
326 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
328 /* IPv4 --> GRE/NAT --> MAC/VLAN */
329 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
331 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
332 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
333 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
334 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(77),
336 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
337 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
338 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
340 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
341 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
342 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
343 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(84),
345 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
346 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
347 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
349 /* Non Tunneled IPv6 */
350 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
353 I40E_PTT_UNUSED_ENTRY(91),
354 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
355 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
356 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
359 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
360 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
361 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(98),
363 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
364 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
365 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
368 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
369 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
370 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
371 I40E_PTT_UNUSED_ENTRY(105),
372 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
373 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
374 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
376 /* IPv6 --> GRE/NAT */
377 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
379 /* IPv6 --> GRE/NAT -> IPv4 */
380 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
381 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
382 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(113),
384 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
385 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
386 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> IPv6 */
389 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
390 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
391 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
392 I40E_PTT_UNUSED_ENTRY(120),
393 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
394 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
395 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
397 /* IPv6 --> GRE/NAT -> MAC */
398 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
401 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
402 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
403 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(128),
405 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
406 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
407 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
410 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
411 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
412 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
413 I40E_PTT_UNUSED_ENTRY(135),
414 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
415 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
416 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
418 /* IPv6 --> GRE/NAT -> MAC/VLAN */
419 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
422 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
423 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
424 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(143),
426 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
427 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
428 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
430 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
431 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
432 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
433 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
434 I40E_PTT_UNUSED_ENTRY(150),
435 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
436 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
437 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
440 I40E_PTT_UNUSED_ENTRY(154),
441 I40E_PTT_UNUSED_ENTRY(155),
442 I40E_PTT_UNUSED_ENTRY(156),
443 I40E_PTT_UNUSED_ENTRY(157),
444 I40E_PTT_UNUSED_ENTRY(158),
445 I40E_PTT_UNUSED_ENTRY(159),
447 I40E_PTT_UNUSED_ENTRY(160),
448 I40E_PTT_UNUSED_ENTRY(161),
449 I40E_PTT_UNUSED_ENTRY(162),
450 I40E_PTT_UNUSED_ENTRY(163),
451 I40E_PTT_UNUSED_ENTRY(164),
452 I40E_PTT_UNUSED_ENTRY(165),
453 I40E_PTT_UNUSED_ENTRY(166),
454 I40E_PTT_UNUSED_ENTRY(167),
455 I40E_PTT_UNUSED_ENTRY(168),
456 I40E_PTT_UNUSED_ENTRY(169),
458 I40E_PTT_UNUSED_ENTRY(170),
459 I40E_PTT_UNUSED_ENTRY(171),
460 I40E_PTT_UNUSED_ENTRY(172),
461 I40E_PTT_UNUSED_ENTRY(173),
462 I40E_PTT_UNUSED_ENTRY(174),
463 I40E_PTT_UNUSED_ENTRY(175),
464 I40E_PTT_UNUSED_ENTRY(176),
465 I40E_PTT_UNUSED_ENTRY(177),
466 I40E_PTT_UNUSED_ENTRY(178),
467 I40E_PTT_UNUSED_ENTRY(179),
469 I40E_PTT_UNUSED_ENTRY(180),
470 I40E_PTT_UNUSED_ENTRY(181),
471 I40E_PTT_UNUSED_ENTRY(182),
472 I40E_PTT_UNUSED_ENTRY(183),
473 I40E_PTT_UNUSED_ENTRY(184),
474 I40E_PTT_UNUSED_ENTRY(185),
475 I40E_PTT_UNUSED_ENTRY(186),
476 I40E_PTT_UNUSED_ENTRY(187),
477 I40E_PTT_UNUSED_ENTRY(188),
478 I40E_PTT_UNUSED_ENTRY(189),
480 I40E_PTT_UNUSED_ENTRY(190),
481 I40E_PTT_UNUSED_ENTRY(191),
482 I40E_PTT_UNUSED_ENTRY(192),
483 I40E_PTT_UNUSED_ENTRY(193),
484 I40E_PTT_UNUSED_ENTRY(194),
485 I40E_PTT_UNUSED_ENTRY(195),
486 I40E_PTT_UNUSED_ENTRY(196),
487 I40E_PTT_UNUSED_ENTRY(197),
488 I40E_PTT_UNUSED_ENTRY(198),
489 I40E_PTT_UNUSED_ENTRY(199),
491 I40E_PTT_UNUSED_ENTRY(200),
492 I40E_PTT_UNUSED_ENTRY(201),
493 I40E_PTT_UNUSED_ENTRY(202),
494 I40E_PTT_UNUSED_ENTRY(203),
495 I40E_PTT_UNUSED_ENTRY(204),
496 I40E_PTT_UNUSED_ENTRY(205),
497 I40E_PTT_UNUSED_ENTRY(206),
498 I40E_PTT_UNUSED_ENTRY(207),
499 I40E_PTT_UNUSED_ENTRY(208),
500 I40E_PTT_UNUSED_ENTRY(209),
502 I40E_PTT_UNUSED_ENTRY(210),
503 I40E_PTT_UNUSED_ENTRY(211),
504 I40E_PTT_UNUSED_ENTRY(212),
505 I40E_PTT_UNUSED_ENTRY(213),
506 I40E_PTT_UNUSED_ENTRY(214),
507 I40E_PTT_UNUSED_ENTRY(215),
508 I40E_PTT_UNUSED_ENTRY(216),
509 I40E_PTT_UNUSED_ENTRY(217),
510 I40E_PTT_UNUSED_ENTRY(218),
511 I40E_PTT_UNUSED_ENTRY(219),
513 I40E_PTT_UNUSED_ENTRY(220),
514 I40E_PTT_UNUSED_ENTRY(221),
515 I40E_PTT_UNUSED_ENTRY(222),
516 I40E_PTT_UNUSED_ENTRY(223),
517 I40E_PTT_UNUSED_ENTRY(224),
518 I40E_PTT_UNUSED_ENTRY(225),
519 I40E_PTT_UNUSED_ENTRY(226),
520 I40E_PTT_UNUSED_ENTRY(227),
521 I40E_PTT_UNUSED_ENTRY(228),
522 I40E_PTT_UNUSED_ENTRY(229),
524 I40E_PTT_UNUSED_ENTRY(230),
525 I40E_PTT_UNUSED_ENTRY(231),
526 I40E_PTT_UNUSED_ENTRY(232),
527 I40E_PTT_UNUSED_ENTRY(233),
528 I40E_PTT_UNUSED_ENTRY(234),
529 I40E_PTT_UNUSED_ENTRY(235),
530 I40E_PTT_UNUSED_ENTRY(236),
531 I40E_PTT_UNUSED_ENTRY(237),
532 I40E_PTT_UNUSED_ENTRY(238),
533 I40E_PTT_UNUSED_ENTRY(239),
535 I40E_PTT_UNUSED_ENTRY(240),
536 I40E_PTT_UNUSED_ENTRY(241),
537 I40E_PTT_UNUSED_ENTRY(242),
538 I40E_PTT_UNUSED_ENTRY(243),
539 I40E_PTT_UNUSED_ENTRY(244),
540 I40E_PTT_UNUSED_ENTRY(245),
541 I40E_PTT_UNUSED_ENTRY(246),
542 I40E_PTT_UNUSED_ENTRY(247),
543 I40E_PTT_UNUSED_ENTRY(248),
544 I40E_PTT_UNUSED_ENTRY(249),
546 I40E_PTT_UNUSED_ENTRY(250),
547 I40E_PTT_UNUSED_ENTRY(251),
548 I40E_PTT_UNUSED_ENTRY(252),
549 I40E_PTT_UNUSED_ENTRY(253),
550 I40E_PTT_UNUSED_ENTRY(254),
551 I40E_PTT_UNUSED_ENTRY(255)
557 * i40e_init_shared_code - Initialize the shared code
558 * @hw: pointer to hardware structure
560 * This assigns the MAC type and PHY code and inits the NVM.
561 * Does not touch the hardware. This function must be called prior to any
562 * other function in the shared code. The i40e_hw structure should be
563 * memset to 0 prior to calling this function. The following fields in
564 * hw structure should be filled in prior to calling this function:
565 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
566 * subsystem_vendor_id, and revision_id
568 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
570 enum i40e_status_code status = I40E_SUCCESS;
571 u32 port, ari, func_rid;
573 DEBUGFUNC("i40e_init_shared_code");
575 i40e_set_mac_type(hw);
577 switch (hw->mac.type) {
581 return I40E_ERR_DEVICE_NOT_SUPPORTED;
584 hw->phy.get_link_info = true;
586 /* Determine port number and PF number*/
587 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
588 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
590 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
591 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
592 func_rid = rd32(hw, I40E_PF_FUNC_RID);
594 hw->pf_id = (u8)(func_rid & 0xff);
596 hw->pf_id = (u8)(func_rid & 0x7);
598 status = i40e_init_nvm(hw);
603 * i40e_aq_mac_address_read - Retrieve the MAC addresses
604 * @hw: pointer to the hw struct
605 * @flags: a return indicator of what addresses were added to the addr store
606 * @addrs: the requestor's mac addr store
607 * @cmd_details: pointer to command details structure or NULL
609 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
611 struct i40e_aqc_mac_address_read_data *addrs,
612 struct i40e_asq_cmd_details *cmd_details)
614 struct i40e_aq_desc desc;
615 struct i40e_aqc_mac_address_read *cmd_data =
616 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
617 enum i40e_status_code status;
619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
620 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
622 status = i40e_asq_send_command(hw, &desc, addrs,
623 sizeof(*addrs), cmd_details);
624 *flags = LE16_TO_CPU(cmd_data->command_flags);
630 * i40e_aq_mac_address_write - Change the MAC addresses
631 * @hw: pointer to the hw struct
632 * @flags: indicates which MAC to be written
633 * @mac_addr: address to write
634 * @cmd_details: pointer to command details structure or NULL
636 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
637 u16 flags, u8 *mac_addr,
638 struct i40e_asq_cmd_details *cmd_details)
640 struct i40e_aq_desc desc;
641 struct i40e_aqc_mac_address_write *cmd_data =
642 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
643 enum i40e_status_code status;
645 i40e_fill_default_direct_cmd_desc(&desc,
646 i40e_aqc_opc_mac_address_write);
647 cmd_data->command_flags = CPU_TO_LE16(flags);
648 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
649 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
650 ((u32)mac_addr[3] << 16) |
651 ((u32)mac_addr[4] << 8) |
654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
660 * i40e_get_mac_addr - get MAC address
661 * @hw: pointer to the HW structure
662 * @mac_addr: pointer to MAC address
664 * Reads the adapter's MAC address from register
666 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668 struct i40e_aqc_mac_address_read_data addrs;
669 enum i40e_status_code status;
672 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (flags & I40E_AQC_LAN_ADDR_VALID)
675 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
681 * i40e_get_port_mac_addr - get Port MAC address
682 * @hw: pointer to the HW structure
683 * @mac_addr: pointer to Port MAC address
685 * Reads the adapter's Port MAC address
687 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
689 struct i40e_aqc_mac_address_read_data addrs;
690 enum i40e_status_code status;
693 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
697 if (flags & I40E_AQC_PORT_ADDR_VALID)
698 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
700 status = I40E_ERR_INVALID_MAC_ADDR;
706 * i40e_pre_tx_queue_cfg - pre tx queue configure
707 * @hw: pointer to the HW structure
708 * @queue: target pf queue index
709 * @enable: state change request
711 * Handles hw requirement to indicate intention to enable
712 * or disable target queue.
714 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
716 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
720 if (abs_queue_idx >= 128) {
721 reg_block = abs_queue_idx / 128;
722 abs_queue_idx %= 128;
725 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
726 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
727 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
730 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
732 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
734 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
738 * i40e_validate_mac_addr - Validate unicast MAC address
739 * @mac_addr: pointer to MAC address
741 * Tests a MAC address to ensure it is a valid Individual Address
743 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
745 enum i40e_status_code status = I40E_SUCCESS;
747 DEBUGFUNC("i40e_validate_mac_addr");
749 /* Broadcast addresses ARE multicast addresses
750 * Make sure it is not a multicast address
751 * Reject the zero address
753 if (I40E_IS_MULTICAST(mac_addr) ||
754 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
755 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
756 status = I40E_ERR_INVALID_MAC_ADDR;
762 * i40e_get_media_type - Gets media type
763 * @hw: pointer to the hardware structure
765 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
767 enum i40e_media_type media;
769 switch (hw->phy.link_info.phy_type) {
770 case I40E_PHY_TYPE_10GBASE_SR:
771 case I40E_PHY_TYPE_10GBASE_LR:
772 case I40E_PHY_TYPE_1000BASE_SX:
773 case I40E_PHY_TYPE_1000BASE_LX:
774 case I40E_PHY_TYPE_40GBASE_SR4:
775 case I40E_PHY_TYPE_40GBASE_LR4:
776 media = I40E_MEDIA_TYPE_FIBER;
778 case I40E_PHY_TYPE_100BASE_TX:
779 case I40E_PHY_TYPE_1000BASE_T:
780 case I40E_PHY_TYPE_10GBASE_T:
781 media = I40E_MEDIA_TYPE_BASET;
783 case I40E_PHY_TYPE_10GBASE_CR1_CU:
784 case I40E_PHY_TYPE_40GBASE_CR4_CU:
785 case I40E_PHY_TYPE_10GBASE_CR1:
786 case I40E_PHY_TYPE_40GBASE_CR4:
787 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
788 case I40E_PHY_TYPE_40GBASE_AOC:
789 case I40E_PHY_TYPE_10GBASE_AOC:
790 media = I40E_MEDIA_TYPE_DA;
792 case I40E_PHY_TYPE_1000BASE_KX:
793 case I40E_PHY_TYPE_10GBASE_KX4:
794 case I40E_PHY_TYPE_10GBASE_KR:
795 case I40E_PHY_TYPE_40GBASE_KR4:
796 media = I40E_MEDIA_TYPE_BACKPLANE;
798 case I40E_PHY_TYPE_SGMII:
799 case I40E_PHY_TYPE_XAUI:
800 case I40E_PHY_TYPE_XFI:
801 case I40E_PHY_TYPE_XLAUI:
802 case I40E_PHY_TYPE_XLPPI:
804 media = I40E_MEDIA_TYPE_UNKNOWN;
811 #define I40E_PF_RESET_WAIT_COUNT 100
813 * i40e_pf_reset - Reset the PF
814 * @hw: pointer to the hardware structure
816 * Assuming someone else has triggered a global reset,
817 * assure the global reset is complete and then reset the PF
819 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
826 /* Poll for Global Reset steady state in case of recent GRST.
827 * The grst delay value is in 100ms units, and we'll wait a
828 * couple counts longer to be sure we don't just miss the end.
830 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
831 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
832 for (cnt = 0; cnt < grst_del + 2; cnt++) {
833 reg = rd32(hw, I40E_GLGEN_RSTAT);
834 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
836 i40e_msec_delay(100);
838 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
839 DEBUGOUT("Global reset polling failed to complete.\n");
840 return I40E_ERR_RESET_FAILED;
843 /* Now Wait for the FW to be ready */
844 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
845 reg = rd32(hw, I40E_GLNVM_ULD);
846 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
847 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
848 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
849 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
850 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
855 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
856 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
857 DEBUGOUT("wait for FW Reset complete timedout\n");
858 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
859 return I40E_ERR_RESET_FAILED;
862 /* If there was a Global Reset in progress when we got here,
863 * we don't need to do the PF Reset
866 reg = rd32(hw, I40E_PFGEN_CTRL);
867 wr32(hw, I40E_PFGEN_CTRL,
868 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
869 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
870 reg = rd32(hw, I40E_PFGEN_CTRL);
871 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
875 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
876 DEBUGOUT("PF reset polling failed to complete.\n");
877 return I40E_ERR_RESET_FAILED;
881 i40e_clear_pxe_mode(hw);
888 * i40e_clear_hw - clear out any left over hw state
889 * @hw: pointer to the hw struct
891 * Clear queues and interrupts, typically called at init time,
892 * but after the capabilities have been found so we know how many
893 * queues and msix vectors have been allocated.
895 void i40e_clear_hw(struct i40e_hw *hw)
897 u32 num_queues, base_queue;
905 /* get number of interrupts, queues, and vfs */
906 val = rd32(hw, I40E_GLPCI_CNF2);
907 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
908 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
909 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
910 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
912 val = rd32(hw, I40E_PFLAN_QALLOC);
913 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
914 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
915 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
916 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
917 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
918 num_queues = (j - base_queue) + 1;
922 val = rd32(hw, I40E_PF_VT_PFALLOC);
923 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
924 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
925 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
926 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
927 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
928 num_vfs = (j - i) + 1;
932 /* stop all the interrupts */
933 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
934 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
935 for (i = 0; i < num_pf_int - 2; i++)
936 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
938 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
939 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
940 wr32(hw, I40E_PFINT_LNKLST0, val);
941 for (i = 0; i < num_pf_int - 2; i++)
942 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
943 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
944 for (i = 0; i < num_vfs; i++)
945 wr32(hw, I40E_VPINT_LNKLST0(i), val);
946 for (i = 0; i < num_vf_int - 2; i++)
947 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
949 /* warn the HW of the coming Tx disables */
950 for (i = 0; i < num_queues; i++) {
951 u32 abs_queue_idx = base_queue + i;
954 if (abs_queue_idx >= 128) {
955 reg_block = abs_queue_idx / 128;
956 abs_queue_idx %= 128;
959 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
960 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
961 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
962 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
964 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
966 i40e_usec_delay(400);
968 /* stop all the queues */
969 for (i = 0; i < num_queues; i++) {
970 wr32(hw, I40E_QINT_TQCTL(i), 0);
971 wr32(hw, I40E_QTX_ENA(i), 0);
972 wr32(hw, I40E_QINT_RQCTL(i), 0);
973 wr32(hw, I40E_QRX_ENA(i), 0);
976 /* short wait for all queue disables to settle */
981 * i40e_clear_pxe_mode - clear pxe operations mode
982 * @hw: pointer to the hw struct
984 * Make sure all PXE mode settings are cleared, including things
985 * like descriptor fetch/write-back mode.
987 void i40e_clear_pxe_mode(struct i40e_hw *hw)
989 if (i40e_check_asq_alive(hw))
990 i40e_aq_clear_pxe_mode(hw, NULL);
994 * i40e_led_is_mine - helper to find matching led
995 * @hw: pointer to the hw struct
996 * @idx: index into GPIO registers
998 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1000 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1005 if (!hw->func_caps.led[idx])
1008 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1009 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1010 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1012 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1013 * if it is not our port then ignore
1015 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1022 #define I40E_COMBINED_ACTIVITY 0xA
1023 #define I40E_FILTER_ACTIVITY 0xE
1024 #define I40E_LINK_ACTIVITY 0xC
1025 #define I40E_MAC_ACTIVITY 0xD
1026 #define I40E_LED0 22
1029 * i40e_led_get - return current on/off mode
1030 * @hw: pointer to the hw struct
1032 * The value returned is the 'mode' field as defined in the
1033 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1034 * values are variations of possible behaviors relating to
1035 * blink, link, and wire.
1037 u32 i40e_led_get(struct i40e_hw *hw)
1039 u32 current_mode = 0;
1043 /* as per the documentation GPIO 22-29 are the LED
1044 * GPIO pins named LED0..LED7
1046 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1047 u32 gpio_val = i40e_led_is_mine(hw, i);
1052 /* ignore gpio LED src mode entries related to the activity LEDs */
1053 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1054 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1055 switch (current_mode) {
1056 case I40E_COMBINED_ACTIVITY:
1057 case I40E_FILTER_ACTIVITY:
1058 case I40E_MAC_ACTIVITY:
1064 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1065 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1073 * i40e_led_set - set new on/off mode
1074 * @hw: pointer to the hw struct
1075 * @mode: 0=off, 0xf=on (else see manual for mode details)
1076 * @blink: true if the LED should blink when on, false if steady
1078 * if this function is used to turn on the blink it should
1079 * be used to disable the blink when restoring the original state.
1081 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1083 u32 current_mode = 0;
1086 if (mode & 0xfffffff0)
1087 DEBUGOUT1("invalid mode passed in %X\n", mode);
1089 /* as per the documentation GPIO 22-29 are the LED
1090 * GPIO pins named LED0..LED7
1092 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1093 u32 gpio_val = i40e_led_is_mine(hw, i);
1098 /* ignore gpio LED src mode entries related to the activity LEDs */
1099 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1100 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1101 switch (current_mode) {
1102 case I40E_COMBINED_ACTIVITY:
1103 case I40E_FILTER_ACTIVITY:
1104 case I40E_MAC_ACTIVITY:
1110 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1111 /* this & is a bit of paranoia, but serves as a range check */
1112 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1113 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1115 if (mode == I40E_LINK_ACTIVITY)
1119 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1121 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1123 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1128 /* Admin command wrappers */
1131 * i40e_aq_get_phy_capabilities
1132 * @hw: pointer to the hw struct
1133 * @abilities: structure for PHY capabilities to be filled
1134 * @qualified_modules: report Qualified Modules
1135 * @report_init: report init capabilities (active are default)
1136 * @cmd_details: pointer to command details structure or NULL
1138 * Returns the various PHY abilities supported on the Port.
1140 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1141 bool qualified_modules, bool report_init,
1142 struct i40e_aq_get_phy_abilities_resp *abilities,
1143 struct i40e_asq_cmd_details *cmd_details)
1145 struct i40e_aq_desc desc;
1146 enum i40e_status_code status;
1147 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1150 return I40E_ERR_PARAM;
1152 i40e_fill_default_direct_cmd_desc(&desc,
1153 i40e_aqc_opc_get_phy_abilities);
1155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1156 if (abilities_size > I40E_AQ_LARGE_BUF)
1157 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1159 if (qualified_modules)
1160 desc.params.external.param0 |=
1161 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1164 desc.params.external.param0 |=
1165 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1167 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1170 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1171 status = I40E_ERR_UNKNOWN_PHY;
1177 * i40e_aq_set_phy_config
1178 * @hw: pointer to the hw struct
1179 * @config: structure with PHY configuration to be set
1180 * @cmd_details: pointer to command details structure or NULL
1182 * Set the various PHY configuration parameters
1183 * supported on the Port.One or more of the Set PHY config parameters may be
1184 * ignored in an MFP mode as the PF may not have the privilege to set some
1185 * of the PHY Config parameters. This status will be indicated by the
1188 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1189 struct i40e_aq_set_phy_config *config,
1190 struct i40e_asq_cmd_details *cmd_details)
1192 struct i40e_aq_desc desc;
1193 struct i40e_aq_set_phy_config *cmd =
1194 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1195 enum i40e_status_code status;
1198 return I40E_ERR_PARAM;
1200 i40e_fill_default_direct_cmd_desc(&desc,
1201 i40e_aqc_opc_set_phy_config);
1205 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1212 * @hw: pointer to the hw struct
1214 * Set the requested flow control mode using set_phy_config.
1216 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1217 bool atomic_restart)
1219 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1220 struct i40e_aq_get_phy_abilities_resp abilities;
1221 struct i40e_aq_set_phy_config config;
1222 enum i40e_status_code status;
1223 u8 pause_mask = 0x0;
1229 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1230 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1232 case I40E_FC_RX_PAUSE:
1233 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1235 case I40E_FC_TX_PAUSE:
1236 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1242 /* Get the current phy config */
1243 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1246 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1250 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1251 /* clear the old pause settings */
1252 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1253 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1254 /* set the new abilities */
1255 config.abilities |= pause_mask;
1256 /* If the abilities have changed, then set the new config */
1257 if (config.abilities != abilities.abilities) {
1258 /* Auto restart link so settings take effect */
1260 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1261 /* Copy over all the old settings */
1262 config.phy_type = abilities.phy_type;
1263 config.link_speed = abilities.link_speed;
1264 config.eee_capability = abilities.eee_capability;
1265 config.eeer = abilities.eeer_val;
1266 config.low_power_ctrl = abilities.d3_lpan;
1267 status = i40e_aq_set_phy_config(hw, &config, NULL);
1270 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1272 /* Update the link info */
1273 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1275 /* Wait a little bit (on 40G cards it sometimes takes a really
1276 * long time for link to come back from the atomic reset)
1279 i40e_msec_delay(1000);
1280 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1283 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1289 * i40e_aq_set_mac_config
1290 * @hw: pointer to the hw struct
1291 * @max_frame_size: Maximum Frame Size to be supported by the port
1292 * @crc_en: Tell HW to append a CRC to outgoing frames
1293 * @pacing: Pacing configurations
1294 * @cmd_details: pointer to command details structure or NULL
1296 * Configure MAC settings for frame size, jumbo frame support and the
1297 * addition of a CRC by the hardware.
1299 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1301 bool crc_en, u16 pacing,
1302 struct i40e_asq_cmd_details *cmd_details)
1304 struct i40e_aq_desc desc;
1305 struct i40e_aq_set_mac_config *cmd =
1306 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1307 enum i40e_status_code status;
1309 if (max_frame_size == 0)
1310 return I40E_ERR_PARAM;
1312 i40e_fill_default_direct_cmd_desc(&desc,
1313 i40e_aqc_opc_set_mac_config);
1315 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1316 cmd->params = ((u8)pacing & 0x0F) << 3;
1318 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1320 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1326 * i40e_aq_clear_pxe_mode
1327 * @hw: pointer to the hw struct
1328 * @cmd_details: pointer to command details structure or NULL
1330 * Tell the firmware that the driver is taking over from PXE
1332 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1333 struct i40e_asq_cmd_details *cmd_details)
1335 enum i40e_status_code status;
1336 struct i40e_aq_desc desc;
1337 struct i40e_aqc_clear_pxe *cmd =
1338 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1340 i40e_fill_default_direct_cmd_desc(&desc,
1341 i40e_aqc_opc_clear_pxe_mode);
1345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1347 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1353 * i40e_aq_set_link_restart_an
1354 * @hw: pointer to the hw struct
1355 * @enable_link: if true: enable link, if false: disable link
1356 * @cmd_details: pointer to command details structure or NULL
1358 * Sets up the link and restarts the Auto-Negotiation over the link.
1360 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1361 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1363 struct i40e_aq_desc desc;
1364 struct i40e_aqc_set_link_restart_an *cmd =
1365 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1366 enum i40e_status_code status;
1368 i40e_fill_default_direct_cmd_desc(&desc,
1369 i40e_aqc_opc_set_link_restart_an);
1371 cmd->command = I40E_AQ_PHY_RESTART_AN;
1373 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1375 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1377 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1383 * i40e_aq_get_link_info
1384 * @hw: pointer to the hw struct
1385 * @enable_lse: enable/disable LinkStatusEvent reporting
1386 * @link: pointer to link status structure - optional
1387 * @cmd_details: pointer to command details structure or NULL
1389 * Returns the link status of the adapter.
1391 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1392 bool enable_lse, struct i40e_link_status *link,
1393 struct i40e_asq_cmd_details *cmd_details)
1395 struct i40e_aq_desc desc;
1396 struct i40e_aqc_get_link_status *resp =
1397 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1398 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1399 enum i40e_status_code status;
1400 bool tx_pause, rx_pause;
1403 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1406 command_flags = I40E_AQ_LSE_ENABLE;
1408 command_flags = I40E_AQ_LSE_DISABLE;
1409 resp->command_flags = CPU_TO_LE16(command_flags);
1411 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1413 if (status != I40E_SUCCESS)
1414 goto aq_get_link_info_exit;
1416 /* save off old link status information */
1417 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1418 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1420 /* update link status */
1421 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1422 hw->phy.media_type = i40e_get_media_type(hw);
1423 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1424 hw_link_info->link_info = resp->link_info;
1425 hw_link_info->an_info = resp->an_info;
1426 hw_link_info->ext_info = resp->ext_info;
1427 hw_link_info->loopback = resp->loopback;
1428 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1429 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1431 /* update fc info */
1432 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1433 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1434 if (tx_pause & rx_pause)
1435 hw->fc.current_mode = I40E_FC_FULL;
1437 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1439 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1441 hw->fc.current_mode = I40E_FC_NONE;
1443 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1444 hw_link_info->crc_enable = true;
1446 hw_link_info->crc_enable = false;
1448 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1449 hw_link_info->lse_enable = true;
1451 hw_link_info->lse_enable = false;
1453 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1454 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1455 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1457 /* save link status information */
1459 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1460 I40E_NONDMA_TO_NONDMA);
1462 /* flag cleared so helper functions don't call AQ again */
1463 hw->phy.get_link_info = false;
1465 aq_get_link_info_exit:
1470 * i40e_aq_set_phy_int_mask
1471 * @hw: pointer to the hw struct
1472 * @mask: interrupt mask to be set
1473 * @cmd_details: pointer to command details structure or NULL
1475 * Set link interrupt mask.
1477 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1479 struct i40e_asq_cmd_details *cmd_details)
1481 struct i40e_aq_desc desc;
1482 struct i40e_aqc_set_phy_int_mask *cmd =
1483 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1484 enum i40e_status_code status;
1486 i40e_fill_default_direct_cmd_desc(&desc,
1487 i40e_aqc_opc_set_phy_int_mask);
1489 cmd->event_mask = CPU_TO_LE16(mask);
1491 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1497 * i40e_aq_get_local_advt_reg
1498 * @hw: pointer to the hw struct
1499 * @advt_reg: local AN advertisement register value
1500 * @cmd_details: pointer to command details structure or NULL
1502 * Get the Local AN advertisement register value.
1504 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1506 struct i40e_asq_cmd_details *cmd_details)
1508 struct i40e_aq_desc desc;
1509 struct i40e_aqc_an_advt_reg *resp =
1510 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1511 enum i40e_status_code status;
1513 i40e_fill_default_direct_cmd_desc(&desc,
1514 i40e_aqc_opc_get_local_advt_reg);
1516 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1518 if (status != I40E_SUCCESS)
1519 goto aq_get_local_advt_reg_exit;
1521 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1522 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1524 aq_get_local_advt_reg_exit:
1529 * i40e_aq_set_local_advt_reg
1530 * @hw: pointer to the hw struct
1531 * @advt_reg: local AN advertisement register value
1532 * @cmd_details: pointer to command details structure or NULL
1534 * Get the Local AN advertisement register value.
1536 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1538 struct i40e_asq_cmd_details *cmd_details)
1540 struct i40e_aq_desc desc;
1541 struct i40e_aqc_an_advt_reg *cmd =
1542 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1543 enum i40e_status_code status;
1545 i40e_fill_default_direct_cmd_desc(&desc,
1546 i40e_aqc_opc_get_local_advt_reg);
1548 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1549 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1551 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1557 * i40e_aq_get_partner_advt
1558 * @hw: pointer to the hw struct
1559 * @advt_reg: AN partner advertisement register value
1560 * @cmd_details: pointer to command details structure or NULL
1562 * Get the link partner AN advertisement register value.
1564 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1566 struct i40e_asq_cmd_details *cmd_details)
1568 struct i40e_aq_desc desc;
1569 struct i40e_aqc_an_advt_reg *resp =
1570 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1571 enum i40e_status_code status;
1573 i40e_fill_default_direct_cmd_desc(&desc,
1574 i40e_aqc_opc_get_partner_advt);
1576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1578 if (status != I40E_SUCCESS)
1579 goto aq_get_partner_advt_exit;
1581 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1582 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1584 aq_get_partner_advt_exit:
1589 * i40e_aq_set_lb_modes
1590 * @hw: pointer to the hw struct
1591 * @lb_modes: loopback mode to be set
1592 * @cmd_details: pointer to command details structure or NULL
1594 * Sets loopback modes.
1596 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1598 struct i40e_asq_cmd_details *cmd_details)
1600 struct i40e_aq_desc desc;
1601 struct i40e_aqc_set_lb_mode *cmd =
1602 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1603 enum i40e_status_code status;
1605 i40e_fill_default_direct_cmd_desc(&desc,
1606 i40e_aqc_opc_set_lb_modes);
1608 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1610 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1616 * i40e_aq_set_phy_debug
1617 * @hw: pointer to the hw struct
1618 * @cmd_flags: debug command flags
1619 * @cmd_details: pointer to command details structure or NULL
1621 * Reset the external PHY.
1623 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1624 struct i40e_asq_cmd_details *cmd_details)
1626 struct i40e_aq_desc desc;
1627 struct i40e_aqc_set_phy_debug *cmd =
1628 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1629 enum i40e_status_code status;
1631 i40e_fill_default_direct_cmd_desc(&desc,
1632 i40e_aqc_opc_set_phy_debug);
1634 cmd->command_flags = cmd_flags;
1636 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1643 * @hw: pointer to the hw struct
1644 * @vsi_ctx: pointer to a vsi context struct
1645 * @cmd_details: pointer to command details structure or NULL
1647 * Add a VSI context to the hardware.
1649 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1650 struct i40e_vsi_context *vsi_ctx,
1651 struct i40e_asq_cmd_details *cmd_details)
1653 struct i40e_aq_desc desc;
1654 struct i40e_aqc_add_get_update_vsi *cmd =
1655 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1656 struct i40e_aqc_add_get_update_vsi_completion *resp =
1657 (struct i40e_aqc_add_get_update_vsi_completion *)
1659 enum i40e_status_code status;
1661 i40e_fill_default_direct_cmd_desc(&desc,
1662 i40e_aqc_opc_add_vsi);
1664 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1665 cmd->connection_type = vsi_ctx->connection_type;
1666 cmd->vf_id = vsi_ctx->vf_num;
1667 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1669 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1671 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1672 sizeof(vsi_ctx->info), cmd_details);
1674 if (status != I40E_SUCCESS)
1675 goto aq_add_vsi_exit;
1677 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1678 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1679 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1680 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1687 * i40e_aq_set_default_vsi
1688 * @hw: pointer to the hw struct
1690 * @cmd_details: pointer to command details structure or NULL
1692 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1694 struct i40e_asq_cmd_details *cmd_details)
1696 struct i40e_aq_desc desc;
1697 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1698 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1700 enum i40e_status_code status;
1702 i40e_fill_default_direct_cmd_desc(&desc,
1703 i40e_aqc_opc_set_vsi_promiscuous_modes);
1705 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1706 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1707 cmd->seid = CPU_TO_LE16(seid);
1709 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1715 * i40e_aq_set_vsi_unicast_promiscuous
1716 * @hw: pointer to the hw struct
1718 * @set: set unicast promiscuous enable/disable
1719 * @cmd_details: pointer to command details structure or NULL
1721 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1723 struct i40e_asq_cmd_details *cmd_details)
1725 struct i40e_aq_desc desc;
1726 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1727 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1728 enum i40e_status_code status;
1731 i40e_fill_default_direct_cmd_desc(&desc,
1732 i40e_aqc_opc_set_vsi_promiscuous_modes);
1735 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1737 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1739 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1741 cmd->seid = CPU_TO_LE16(seid);
1742 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1748 * i40e_aq_set_vsi_multicast_promiscuous
1749 * @hw: pointer to the hw struct
1751 * @set: set multicast promiscuous enable/disable
1752 * @cmd_details: pointer to command details structure or NULL
1754 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1755 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1757 struct i40e_aq_desc desc;
1758 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1759 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1760 enum i40e_status_code status;
1763 i40e_fill_default_direct_cmd_desc(&desc,
1764 i40e_aqc_opc_set_vsi_promiscuous_modes);
1767 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1769 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1771 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1773 cmd->seid = CPU_TO_LE16(seid);
1774 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1780 * i40e_aq_set_vsi_broadcast
1781 * @hw: pointer to the hw struct
1783 * @set_filter: true to set filter, false to clear filter
1784 * @cmd_details: pointer to command details structure or NULL
1786 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1788 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1789 u16 seid, bool set_filter,
1790 struct i40e_asq_cmd_details *cmd_details)
1792 struct i40e_aq_desc desc;
1793 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1794 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1795 enum i40e_status_code status;
1797 i40e_fill_default_direct_cmd_desc(&desc,
1798 i40e_aqc_opc_set_vsi_promiscuous_modes);
1801 cmd->promiscuous_flags
1802 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1804 cmd->promiscuous_flags
1805 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1807 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1808 cmd->seid = CPU_TO_LE16(seid);
1809 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815 * i40e_get_vsi_params - get VSI configuration info
1816 * @hw: pointer to the hw struct
1817 * @vsi_ctx: pointer to a vsi context struct
1818 * @cmd_details: pointer to command details structure or NULL
1820 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1821 struct i40e_vsi_context *vsi_ctx,
1822 struct i40e_asq_cmd_details *cmd_details)
1824 struct i40e_aq_desc desc;
1825 struct i40e_aqc_add_get_update_vsi *cmd =
1826 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1827 struct i40e_aqc_add_get_update_vsi_completion *resp =
1828 (struct i40e_aqc_add_get_update_vsi_completion *)
1830 enum i40e_status_code status;
1832 UNREFERENCED_1PARAMETER(cmd_details);
1833 i40e_fill_default_direct_cmd_desc(&desc,
1834 i40e_aqc_opc_get_vsi_parameters);
1836 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1838 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1840 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1841 sizeof(vsi_ctx->info), NULL);
1843 if (status != I40E_SUCCESS)
1844 goto aq_get_vsi_params_exit;
1846 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1847 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1848 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1849 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1851 aq_get_vsi_params_exit:
1856 * i40e_aq_update_vsi_params
1857 * @hw: pointer to the hw struct
1858 * @vsi_ctx: pointer to a vsi context struct
1859 * @cmd_details: pointer to command details structure or NULL
1861 * Update a VSI context.
1863 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1864 struct i40e_vsi_context *vsi_ctx,
1865 struct i40e_asq_cmd_details *cmd_details)
1867 struct i40e_aq_desc desc;
1868 struct i40e_aqc_add_get_update_vsi *cmd =
1869 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1870 enum i40e_status_code status;
1872 i40e_fill_default_direct_cmd_desc(&desc,
1873 i40e_aqc_opc_update_vsi_parameters);
1874 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1876 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1878 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1879 sizeof(vsi_ctx->info), cmd_details);
1885 * i40e_aq_get_switch_config
1886 * @hw: pointer to the hardware structure
1887 * @buf: pointer to the result buffer
1888 * @buf_size: length of input buffer
1889 * @start_seid: seid to start for the report, 0 == beginning
1890 * @cmd_details: pointer to command details structure or NULL
1892 * Fill the buf with switch configuration returned from AdminQ command
1894 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1895 struct i40e_aqc_get_switch_config_resp *buf,
1896 u16 buf_size, u16 *start_seid,
1897 struct i40e_asq_cmd_details *cmd_details)
1899 struct i40e_aq_desc desc;
1900 struct i40e_aqc_switch_seid *scfg =
1901 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1902 enum i40e_status_code status;
1904 i40e_fill_default_direct_cmd_desc(&desc,
1905 i40e_aqc_opc_get_switch_config);
1906 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1907 if (buf_size > I40E_AQ_LARGE_BUF)
1908 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1909 scfg->seid = CPU_TO_LE16(*start_seid);
1911 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1912 *start_seid = LE16_TO_CPU(scfg->seid);
1918 * i40e_aq_get_firmware_version
1919 * @hw: pointer to the hw struct
1920 * @fw_major_version: firmware major version
1921 * @fw_minor_version: firmware minor version
1922 * @fw_build: firmware build number
1923 * @api_major_version: major queue version
1924 * @api_minor_version: minor queue version
1925 * @cmd_details: pointer to command details structure or NULL
1927 * Get the firmware version from the admin queue commands
1929 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1930 u16 *fw_major_version, u16 *fw_minor_version,
1932 u16 *api_major_version, u16 *api_minor_version,
1933 struct i40e_asq_cmd_details *cmd_details)
1935 struct i40e_aq_desc desc;
1936 struct i40e_aqc_get_version *resp =
1937 (struct i40e_aqc_get_version *)&desc.params.raw;
1938 enum i40e_status_code status;
1940 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1942 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1944 if (status == I40E_SUCCESS) {
1945 if (fw_major_version != NULL)
1946 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1947 if (fw_minor_version != NULL)
1948 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1949 if (fw_build != NULL)
1950 *fw_build = LE32_TO_CPU(resp->fw_build);
1951 if (api_major_version != NULL)
1952 *api_major_version = LE16_TO_CPU(resp->api_major);
1953 if (api_minor_version != NULL)
1954 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1956 /* A workaround to fix the API version in SW */
1957 if (api_major_version && api_minor_version &&
1958 fw_major_version && fw_minor_version &&
1959 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1960 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1961 (*fw_major_version > 4)))
1962 *api_minor_version = 2;
1969 * i40e_aq_send_driver_version
1970 * @hw: pointer to the hw struct
1971 * @dv: driver's major, minor version
1972 * @cmd_details: pointer to command details structure or NULL
1974 * Send the driver version to the firmware
1976 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1977 struct i40e_driver_version *dv,
1978 struct i40e_asq_cmd_details *cmd_details)
1980 struct i40e_aq_desc desc;
1981 struct i40e_aqc_driver_version *cmd =
1982 (struct i40e_aqc_driver_version *)&desc.params.raw;
1983 enum i40e_status_code status;
1987 return I40E_ERR_PARAM;
1989 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1991 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1992 cmd->driver_major_ver = dv->major_version;
1993 cmd->driver_minor_ver = dv->minor_version;
1994 cmd->driver_build_ver = dv->build_version;
1995 cmd->driver_subbuild_ver = dv->subbuild_version;
1998 while (len < sizeof(dv->driver_string) &&
1999 (dv->driver_string[len] < 0x80) &&
2000 dv->driver_string[len])
2002 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2009 * i40e_get_link_status - get status of the HW network link
2010 * @hw: pointer to the hw struct
2012 * Returns true if link is up, false if link is down.
2014 * Side effect: LinkStatusEvent reporting becomes enabled
2016 bool i40e_get_link_status(struct i40e_hw *hw)
2018 enum i40e_status_code status = I40E_SUCCESS;
2019 bool link_status = false;
2021 if (hw->phy.get_link_info) {
2022 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2024 if (status != I40E_SUCCESS)
2025 goto i40e_get_link_status_exit;
2028 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2030 i40e_get_link_status_exit:
2035 * i40e_get_link_speed
2036 * @hw: pointer to the hw struct
2038 * Returns the link speed of the adapter.
2040 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2042 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2043 enum i40e_status_code status = I40E_SUCCESS;
2045 if (hw->phy.get_link_info) {
2046 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2048 if (status != I40E_SUCCESS)
2049 goto i40e_link_speed_exit;
2052 speed = hw->phy.link_info.link_speed;
2054 i40e_link_speed_exit:
2059 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2060 * @hw: pointer to the hw struct
2061 * @uplink_seid: the MAC or other gizmo SEID
2062 * @downlink_seid: the VSI SEID
2063 * @enabled_tc: bitmap of TCs to be enabled
2064 * @default_port: true for default port VSI, false for control port
2065 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2066 * @veb_seid: pointer to where to put the resulting VEB SEID
2067 * @cmd_details: pointer to command details structure or NULL
2069 * This asks the FW to add a VEB between the uplink and downlink
2070 * elements. If the uplink SEID is 0, this will be a floating VEB.
2072 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2073 u16 downlink_seid, u8 enabled_tc,
2074 bool default_port, bool enable_l2_filtering,
2076 struct i40e_asq_cmd_details *cmd_details)
2078 struct i40e_aq_desc desc;
2079 struct i40e_aqc_add_veb *cmd =
2080 (struct i40e_aqc_add_veb *)&desc.params.raw;
2081 struct i40e_aqc_add_veb_completion *resp =
2082 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2083 enum i40e_status_code status;
2086 /* SEIDs need to either both be set or both be 0 for floating VEB */
2087 if (!!uplink_seid != !!downlink_seid)
2088 return I40E_ERR_PARAM;
2090 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2092 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2093 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2094 cmd->enable_tcs = enabled_tc;
2096 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2098 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2100 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2102 if (enable_l2_filtering)
2103 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2105 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2107 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109 if (!status && veb_seid)
2110 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2116 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2117 * @hw: pointer to the hw struct
2118 * @veb_seid: the SEID of the VEB to query
2119 * @switch_id: the uplink switch id
2120 * @floating: set to true if the VEB is floating
2121 * @statistic_index: index of the stats counter block for this VEB
2122 * @vebs_used: number of VEB's used by function
2123 * @vebs_free: total VEB's not reserved by any function
2124 * @cmd_details: pointer to command details structure or NULL
2126 * This retrieves the parameters for a particular VEB, specified by
2127 * uplink_seid, and returns them to the caller.
2129 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2130 u16 veb_seid, u16 *switch_id,
2131 bool *floating, u16 *statistic_index,
2132 u16 *vebs_used, u16 *vebs_free,
2133 struct i40e_asq_cmd_details *cmd_details)
2135 struct i40e_aq_desc desc;
2136 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2137 (struct i40e_aqc_get_veb_parameters_completion *)
2139 enum i40e_status_code status;
2142 return I40E_ERR_PARAM;
2144 i40e_fill_default_direct_cmd_desc(&desc,
2145 i40e_aqc_opc_get_veb_parameters);
2146 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2148 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2153 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2154 if (statistic_index)
2155 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2157 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2159 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2161 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2162 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2173 * i40e_aq_add_macvlan
2174 * @hw: pointer to the hw struct
2175 * @seid: VSI for the mac address
2176 * @mv_list: list of macvlans to be added
2177 * @count: length of the list
2178 * @cmd_details: pointer to command details structure or NULL
2180 * Add MAC/VLAN addresses to the HW filtering
2182 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2183 struct i40e_aqc_add_macvlan_element_data *mv_list,
2184 u16 count, struct i40e_asq_cmd_details *cmd_details)
2186 struct i40e_aq_desc desc;
2187 struct i40e_aqc_macvlan *cmd =
2188 (struct i40e_aqc_macvlan *)&desc.params.raw;
2189 enum i40e_status_code status;
2192 if (count == 0 || !mv_list || !hw)
2193 return I40E_ERR_PARAM;
2195 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2197 /* prep the rest of the request */
2198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2199 cmd->num_addresses = CPU_TO_LE16(count);
2200 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2204 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2205 if (buf_size > I40E_AQ_LARGE_BUF)
2206 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2208 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2215 * i40e_aq_remove_macvlan
2216 * @hw: pointer to the hw struct
2217 * @seid: VSI for the mac address
2218 * @mv_list: list of macvlans to be removed
2219 * @count: length of the list
2220 * @cmd_details: pointer to command details structure or NULL
2222 * Remove MAC/VLAN addresses from the HW filtering
2224 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2225 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2226 u16 count, struct i40e_asq_cmd_details *cmd_details)
2228 struct i40e_aq_desc desc;
2229 struct i40e_aqc_macvlan *cmd =
2230 (struct i40e_aqc_macvlan *)&desc.params.raw;
2231 enum i40e_status_code status;
2234 if (count == 0 || !mv_list || !hw)
2235 return I40E_ERR_PARAM;
2237 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2239 /* prep the rest of the request */
2240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2241 cmd->num_addresses = CPU_TO_LE16(count);
2242 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2246 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2247 if (buf_size > I40E_AQ_LARGE_BUF)
2248 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2250 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2257 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2258 * @hw: pointer to the hw struct
2259 * @seid: VSI for the vlan filters
2260 * @v_list: list of vlan filters to be added
2261 * @count: length of the list
2262 * @cmd_details: pointer to command details structure or NULL
2264 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2265 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2266 u8 count, struct i40e_asq_cmd_details *cmd_details)
2268 struct i40e_aq_desc desc;
2269 struct i40e_aqc_macvlan *cmd =
2270 (struct i40e_aqc_macvlan *)&desc.params.raw;
2271 enum i40e_status_code status;
2274 if (count == 0 || !v_list || !hw)
2275 return I40E_ERR_PARAM;
2277 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2279 /* prep the rest of the request */
2280 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2281 cmd->num_addresses = CPU_TO_LE16(count);
2282 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2286 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2287 if (buf_size > I40E_AQ_LARGE_BUF)
2288 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2290 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2297 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2298 * @hw: pointer to the hw struct
2299 * @seid: VSI for the vlan filters
2300 * @v_list: list of macvlans to be removed
2301 * @count: length of the list
2302 * @cmd_details: pointer to command details structure or NULL
2304 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2305 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2306 u8 count, struct i40e_asq_cmd_details *cmd_details)
2308 struct i40e_aq_desc desc;
2309 struct i40e_aqc_macvlan *cmd =
2310 (struct i40e_aqc_macvlan *)&desc.params.raw;
2311 enum i40e_status_code status;
2314 if (count == 0 || !v_list || !hw)
2315 return I40E_ERR_PARAM;
2317 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2319 /* prep the rest of the request */
2320 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2321 cmd->num_addresses = CPU_TO_LE16(count);
2322 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2326 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2327 if (buf_size > I40E_AQ_LARGE_BUF)
2328 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2330 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2337 * i40e_aq_send_msg_to_vf
2338 * @hw: pointer to the hardware structure
2339 * @vfid: vf id to send msg
2340 * @v_opcode: opcodes for VF-PF communication
2341 * @v_retval: return error code
2342 * @msg: pointer to the msg buffer
2343 * @msglen: msg length
2344 * @cmd_details: pointer to command details
2348 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2349 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2350 struct i40e_asq_cmd_details *cmd_details)
2352 struct i40e_aq_desc desc;
2353 struct i40e_aqc_pf_vf_message *cmd =
2354 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2355 enum i40e_status_code status;
2357 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2358 cmd->id = CPU_TO_LE32(vfid);
2359 desc.cookie_high = CPU_TO_LE32(v_opcode);
2360 desc.cookie_low = CPU_TO_LE32(v_retval);
2361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2363 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2365 if (msglen > I40E_AQ_LARGE_BUF)
2366 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2367 desc.datalen = CPU_TO_LE16(msglen);
2369 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2375 * i40e_aq_debug_read_register
2376 * @hw: pointer to the hw struct
2377 * @reg_addr: register address
2378 * @reg_val: register value
2379 * @cmd_details: pointer to command details structure or NULL
2381 * Read the register using the admin queue commands
2383 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2384 u32 reg_addr, u64 *reg_val,
2385 struct i40e_asq_cmd_details *cmd_details)
2387 struct i40e_aq_desc desc;
2388 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2389 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2390 enum i40e_status_code status;
2392 if (reg_val == NULL)
2393 return I40E_ERR_PARAM;
2395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2397 cmd_resp->address = CPU_TO_LE32(reg_addr);
2399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2401 if (status == I40E_SUCCESS) {
2402 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2403 (u64)LE32_TO_CPU(cmd_resp->value_low);
2410 * i40e_aq_debug_write_register
2411 * @hw: pointer to the hw struct
2412 * @reg_addr: register address
2413 * @reg_val: register value
2414 * @cmd_details: pointer to command details structure or NULL
2416 * Write to a register using the admin queue commands
2418 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2419 u32 reg_addr, u64 reg_val,
2420 struct i40e_asq_cmd_details *cmd_details)
2422 struct i40e_aq_desc desc;
2423 struct i40e_aqc_debug_reg_read_write *cmd =
2424 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2425 enum i40e_status_code status;
2427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2429 cmd->address = CPU_TO_LE32(reg_addr);
2430 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2431 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2433 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2439 * i40e_aq_get_hmc_resource_profile
2440 * @hw: pointer to the hw struct
2441 * @profile: type of profile the HMC is to be set as
2442 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2443 * @cmd_details: pointer to command details structure or NULL
2445 * query the HMC profile of the device.
2447 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2448 enum i40e_aq_hmc_profile *profile,
2449 u8 *pe_vf_enabled_count,
2450 struct i40e_asq_cmd_details *cmd_details)
2452 struct i40e_aq_desc desc;
2453 struct i40e_aq_get_set_hmc_resource_profile *resp =
2454 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2455 enum i40e_status_code status;
2457 i40e_fill_default_direct_cmd_desc(&desc,
2458 i40e_aqc_opc_query_hmc_resource_profile);
2459 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2461 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2462 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2463 *pe_vf_enabled_count = resp->pe_vf_enabled &
2464 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2470 * i40e_aq_set_hmc_resource_profile
2471 * @hw: pointer to the hw struct
2472 * @profile: type of profile the HMC is to be set as
2473 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2474 * @cmd_details: pointer to command details structure or NULL
2476 * set the HMC profile of the device.
2478 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2479 enum i40e_aq_hmc_profile profile,
2480 u8 pe_vf_enabled_count,
2481 struct i40e_asq_cmd_details *cmd_details)
2483 struct i40e_aq_desc desc;
2484 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2485 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2486 enum i40e_status_code status;
2488 i40e_fill_default_direct_cmd_desc(&desc,
2489 i40e_aqc_opc_set_hmc_resource_profile);
2491 cmd->pm_profile = (u8)profile;
2492 cmd->pe_vf_enabled = pe_vf_enabled_count;
2494 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2500 * i40e_aq_request_resource
2501 * @hw: pointer to the hw struct
2502 * @resource: resource id
2503 * @access: access type
2504 * @sdp_number: resource number
2505 * @timeout: the maximum time in ms that the driver may hold the resource
2506 * @cmd_details: pointer to command details structure or NULL
2508 * requests common resource using the admin queue commands
2510 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2511 enum i40e_aq_resources_ids resource,
2512 enum i40e_aq_resource_access_type access,
2513 u8 sdp_number, u64 *timeout,
2514 struct i40e_asq_cmd_details *cmd_details)
2516 struct i40e_aq_desc desc;
2517 struct i40e_aqc_request_resource *cmd_resp =
2518 (struct i40e_aqc_request_resource *)&desc.params.raw;
2519 enum i40e_status_code status;
2521 DEBUGFUNC("i40e_aq_request_resource");
2523 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2525 cmd_resp->resource_id = CPU_TO_LE16(resource);
2526 cmd_resp->access_type = CPU_TO_LE16(access);
2527 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2529 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2530 /* The completion specifies the maximum time in ms that the driver
2531 * may hold the resource in the Timeout field.
2532 * If the resource is held by someone else, the command completes with
2533 * busy return value and the timeout field indicates the maximum time
2534 * the current owner of the resource has to free it.
2536 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2537 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2543 * i40e_aq_release_resource
2544 * @hw: pointer to the hw struct
2545 * @resource: resource id
2546 * @sdp_number: resource number
2547 * @cmd_details: pointer to command details structure or NULL
2549 * release common resource using the admin queue commands
2551 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2552 enum i40e_aq_resources_ids resource,
2554 struct i40e_asq_cmd_details *cmd_details)
2556 struct i40e_aq_desc desc;
2557 struct i40e_aqc_request_resource *cmd =
2558 (struct i40e_aqc_request_resource *)&desc.params.raw;
2559 enum i40e_status_code status;
2561 DEBUGFUNC("i40e_aq_release_resource");
2563 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2565 cmd->resource_id = CPU_TO_LE16(resource);
2566 cmd->resource_number = CPU_TO_LE32(sdp_number);
2568 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2575 * @hw: pointer to the hw struct
2576 * @module_pointer: module pointer location in words from the NVM beginning
2577 * @offset: byte offset from the module beginning
2578 * @length: length of the section to be read (in bytes from the offset)
2579 * @data: command buffer (size [bytes] = length)
2580 * @last_command: tells if this is the last command in a series
2581 * @cmd_details: pointer to command details structure or NULL
2583 * Read the NVM using the admin queue commands
2585 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2586 u32 offset, u16 length, void *data,
2588 struct i40e_asq_cmd_details *cmd_details)
2590 struct i40e_aq_desc desc;
2591 struct i40e_aqc_nvm_update *cmd =
2592 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2593 enum i40e_status_code status;
2595 DEBUGFUNC("i40e_aq_read_nvm");
2597 /* In offset the highest byte must be zeroed. */
2598 if (offset & 0xFF000000) {
2599 status = I40E_ERR_PARAM;
2600 goto i40e_aq_read_nvm_exit;
2603 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2605 /* If this is the last command in a series, set the proper flag. */
2607 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2608 cmd->module_pointer = module_pointer;
2609 cmd->offset = CPU_TO_LE32(offset);
2610 cmd->length = CPU_TO_LE16(length);
2612 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2613 if (length > I40E_AQ_LARGE_BUF)
2614 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2616 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2618 i40e_aq_read_nvm_exit:
2624 * @hw: pointer to the hw struct
2625 * @module_pointer: module pointer location in words from the NVM beginning
2626 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2627 * @length: length of the section to be erased (expressed in 4 KB)
2628 * @last_command: tells if this is the last command in a series
2629 * @cmd_details: pointer to command details structure or NULL
2631 * Erase the NVM sector using the admin queue commands
2633 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2634 u32 offset, u16 length, bool last_command,
2635 struct i40e_asq_cmd_details *cmd_details)
2637 struct i40e_aq_desc desc;
2638 struct i40e_aqc_nvm_update *cmd =
2639 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2640 enum i40e_status_code status;
2642 DEBUGFUNC("i40e_aq_erase_nvm");
2644 /* In offset the highest byte must be zeroed. */
2645 if (offset & 0xFF000000) {
2646 status = I40E_ERR_PARAM;
2647 goto i40e_aq_erase_nvm_exit;
2650 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2652 /* If this is the last command in a series, set the proper flag. */
2654 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2655 cmd->module_pointer = module_pointer;
2656 cmd->offset = CPU_TO_LE32(offset);
2657 cmd->length = CPU_TO_LE16(length);
2659 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2661 i40e_aq_erase_nvm_exit:
2665 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2666 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2667 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2668 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2669 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2670 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2671 #define I40E_DEV_FUNC_CAP_VF 0x13
2672 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2673 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2674 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2675 #define I40E_DEV_FUNC_CAP_VSI 0x17
2676 #define I40E_DEV_FUNC_CAP_DCB 0x18
2677 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2678 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2679 #define I40E_DEV_FUNC_CAP_RSS 0x40
2680 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2681 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2682 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2683 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2684 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2685 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2686 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2687 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2688 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2689 #define I40E_DEV_FUNC_CAP_LED 0x61
2690 #define I40E_DEV_FUNC_CAP_SDP 0x62
2691 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2694 * i40e_parse_discover_capabilities
2695 * @hw: pointer to the hw struct
2696 * @buff: pointer to a buffer containing device/function capability records
2697 * @cap_count: number of capability records in the list
2698 * @list_type_opc: type of capabilities list to parse
2700 * Parse the device/function capabilities list.
2702 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2704 enum i40e_admin_queue_opc list_type_opc)
2706 struct i40e_aqc_list_capabilities_element_resp *cap;
2707 u32 valid_functions, num_functions;
2708 u32 number, logical_id, phys_id;
2709 struct i40e_hw_capabilities *p;
2713 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2715 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2716 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2717 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2718 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2722 for (i = 0; i < cap_count; i++, cap++) {
2723 id = LE16_TO_CPU(cap->id);
2724 number = LE32_TO_CPU(cap->number);
2725 logical_id = LE32_TO_CPU(cap->logical_id);
2726 phys_id = LE32_TO_CPU(cap->phys_id);
2729 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2730 p->switch_mode = number;
2732 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2733 p->management_mode = number;
2735 case I40E_DEV_FUNC_CAP_NPAR:
2736 p->npar_enable = number;
2738 case I40E_DEV_FUNC_CAP_OS2BMC:
2741 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2742 p->valid_functions = number;
2744 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2746 p->sr_iov_1_1 = true;
2748 case I40E_DEV_FUNC_CAP_VF:
2749 p->num_vfs = number;
2750 p->vf_base_id = logical_id;
2752 case I40E_DEV_FUNC_CAP_VMDQ:
2756 case I40E_DEV_FUNC_CAP_802_1_QBG:
2758 p->evb_802_1_qbg = true;
2760 case I40E_DEV_FUNC_CAP_802_1_QBH:
2762 p->evb_802_1_qbh = true;
2764 case I40E_DEV_FUNC_CAP_VSI:
2765 p->num_vsis = number;
2767 case I40E_DEV_FUNC_CAP_DCB:
2770 p->enabled_tcmap = logical_id;
2774 case I40E_DEV_FUNC_CAP_FCOE:
2778 case I40E_DEV_FUNC_CAP_ISCSI:
2782 case I40E_DEV_FUNC_CAP_RSS:
2784 p->rss_table_size = number;
2785 p->rss_table_entry_width = logical_id;
2787 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2788 p->num_rx_qp = number;
2789 p->base_queue = phys_id;
2791 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2792 p->num_tx_qp = number;
2793 p->base_queue = phys_id;
2795 case I40E_DEV_FUNC_CAP_MSIX:
2796 p->num_msix_vectors = number;
2798 case I40E_DEV_FUNC_CAP_MSIX_VF:
2799 p->num_msix_vectors_vf = number;
2801 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2803 p->mfp_mode_1 = true;
2805 case I40E_DEV_FUNC_CAP_CEM:
2809 case I40E_DEV_FUNC_CAP_IWARP:
2813 case I40E_DEV_FUNC_CAP_LED:
2814 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2815 p->led[phys_id] = true;
2817 case I40E_DEV_FUNC_CAP_SDP:
2818 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2819 p->sdp[phys_id] = true;
2821 case I40E_DEV_FUNC_CAP_MDIO:
2823 p->mdio_port_num = phys_id;
2824 p->mdio_port_mode = logical_id;
2827 case I40E_DEV_FUNC_CAP_IEEE_1588:
2829 p->ieee_1588 = true;
2831 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2833 p->fd_filters_guaranteed = number;
2834 p->fd_filters_best_effort = logical_id;
2841 #ifdef I40E_FCOE_ENA
2842 /* Software override ensuring FCoE is disabled if npar or mfp
2843 * mode because it is not supported in these modes.
2845 if (p->npar_enable || p->mfp_mode_1)
2848 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2852 /* count the enabled ports (aka the "not disabled" ports) */
2854 for (i = 0; i < 4; i++) {
2855 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2858 /* use AQ read to get the physical register offset instead
2859 * of the port relative offset
2861 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2862 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2866 valid_functions = p->valid_functions;
2868 while (valid_functions) {
2869 if (valid_functions & 1)
2871 valid_functions >>= 1;
2874 /* partition id is 1-based, and functions are evenly spread
2875 * across the ports as partitions
2877 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2878 hw->num_partitions = num_functions / hw->num_ports;
2880 /* additional HW specific goodies that might
2881 * someday be HW version specific
2883 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2887 * i40e_aq_discover_capabilities
2888 * @hw: pointer to the hw struct
2889 * @buff: a virtual buffer to hold the capabilities
2890 * @buff_size: Size of the virtual buffer
2891 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2892 * @list_type_opc: capabilities type to discover - pass in the command opcode
2893 * @cmd_details: pointer to command details structure or NULL
2895 * Get the device capabilities descriptions from the firmware
2897 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2898 void *buff, u16 buff_size, u16 *data_size,
2899 enum i40e_admin_queue_opc list_type_opc,
2900 struct i40e_asq_cmd_details *cmd_details)
2902 struct i40e_aqc_list_capabilites *cmd;
2903 struct i40e_aq_desc desc;
2904 enum i40e_status_code status = I40E_SUCCESS;
2906 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2908 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2909 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2910 status = I40E_ERR_PARAM;
2914 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2916 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2917 if (buff_size > I40E_AQ_LARGE_BUF)
2918 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2920 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2921 *data_size = LE16_TO_CPU(desc.datalen);
2926 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2934 * i40e_aq_update_nvm
2935 * @hw: pointer to the hw struct
2936 * @module_pointer: module pointer location in words from the NVM beginning
2937 * @offset: byte offset from the module beginning
2938 * @length: length of the section to be written (in bytes from the offset)
2939 * @data: command buffer (size [bytes] = length)
2940 * @last_command: tells if this is the last command in a series
2941 * @cmd_details: pointer to command details structure or NULL
2943 * Update the NVM using the admin queue commands
2945 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2946 u32 offset, u16 length, void *data,
2948 struct i40e_asq_cmd_details *cmd_details)
2950 struct i40e_aq_desc desc;
2951 struct i40e_aqc_nvm_update *cmd =
2952 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2953 enum i40e_status_code status;
2955 DEBUGFUNC("i40e_aq_update_nvm");
2957 /* In offset the highest byte must be zeroed. */
2958 if (offset & 0xFF000000) {
2959 status = I40E_ERR_PARAM;
2960 goto i40e_aq_update_nvm_exit;
2963 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2965 /* If this is the last command in a series, set the proper flag. */
2967 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2968 cmd->module_pointer = module_pointer;
2969 cmd->offset = CPU_TO_LE32(offset);
2970 cmd->length = CPU_TO_LE16(length);
2972 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2973 if (length > I40E_AQ_LARGE_BUF)
2974 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2976 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2978 i40e_aq_update_nvm_exit:
2983 * i40e_aq_get_lldp_mib
2984 * @hw: pointer to the hw struct
2985 * @bridge_type: type of bridge requested
2986 * @mib_type: Local, Remote or both Local and Remote MIBs
2987 * @buff: pointer to a user supplied buffer to store the MIB block
2988 * @buff_size: size of the buffer (in bytes)
2989 * @local_len : length of the returned Local LLDP MIB
2990 * @remote_len: length of the returned Remote LLDP MIB
2991 * @cmd_details: pointer to command details structure or NULL
2993 * Requests the complete LLDP MIB (entire packet).
2995 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2996 u8 mib_type, void *buff, u16 buff_size,
2997 u16 *local_len, u16 *remote_len,
2998 struct i40e_asq_cmd_details *cmd_details)
3000 struct i40e_aq_desc desc;
3001 struct i40e_aqc_lldp_get_mib *cmd =
3002 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3003 struct i40e_aqc_lldp_get_mib *resp =
3004 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3005 enum i40e_status_code status;
3007 if (buff_size == 0 || !buff)
3008 return I40E_ERR_PARAM;
3010 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3011 /* Indirect Command */
3012 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3014 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3015 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3016 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3018 desc.datalen = CPU_TO_LE16(buff_size);
3020 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3021 if (buff_size > I40E_AQ_LARGE_BUF)
3022 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3024 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3026 if (local_len != NULL)
3027 *local_len = LE16_TO_CPU(resp->local_len);
3028 if (remote_len != NULL)
3029 *remote_len = LE16_TO_CPU(resp->remote_len);
3036 * i40e_aq_cfg_lldp_mib_change_event
3037 * @hw: pointer to the hw struct
3038 * @enable_update: Enable or Disable event posting
3039 * @cmd_details: pointer to command details structure or NULL
3041 * Enable or Disable posting of an event on ARQ when LLDP MIB
3042 * associated with the interface changes
3044 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3046 struct i40e_asq_cmd_details *cmd_details)
3048 struct i40e_aq_desc desc;
3049 struct i40e_aqc_lldp_update_mib *cmd =
3050 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3051 enum i40e_status_code status;
3053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3056 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3058 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3064 * i40e_aq_add_lldp_tlv
3065 * @hw: pointer to the hw struct
3066 * @bridge_type: type of bridge
3067 * @buff: buffer with TLV to add
3068 * @buff_size: length of the buffer
3069 * @tlv_len: length of the TLV to be added
3070 * @mib_len: length of the LLDP MIB returned in response
3071 * @cmd_details: pointer to command details structure or NULL
3073 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3074 * it is responsibility of the caller to make sure that the TLV is not
3075 * already present in the LLDPDU.
3076 * In return firmware will write the complete LLDP MIB with the newly
3077 * added TLV in the response buffer.
3079 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3080 void *buff, u16 buff_size, u16 tlv_len,
3082 struct i40e_asq_cmd_details *cmd_details)
3084 struct i40e_aq_desc desc;
3085 struct i40e_aqc_lldp_add_tlv *cmd =
3086 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3087 enum i40e_status_code status;
3089 if (buff_size == 0 || !buff || tlv_len == 0)
3090 return I40E_ERR_PARAM;
3092 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3094 /* Indirect Command */
3095 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3096 if (buff_size > I40E_AQ_LARGE_BUF)
3097 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3098 desc.datalen = CPU_TO_LE16(buff_size);
3100 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3101 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3102 cmd->len = CPU_TO_LE16(tlv_len);
3104 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3106 if (mib_len != NULL)
3107 *mib_len = LE16_TO_CPU(desc.datalen);
3114 * i40e_aq_update_lldp_tlv
3115 * @hw: pointer to the hw struct
3116 * @bridge_type: type of bridge
3117 * @buff: buffer with TLV to update
3118 * @buff_size: size of the buffer holding original and updated TLVs
3119 * @old_len: Length of the Original TLV
3120 * @new_len: Length of the Updated TLV
3121 * @offset: offset of the updated TLV in the buff
3122 * @mib_len: length of the returned LLDP MIB
3123 * @cmd_details: pointer to command details structure or NULL
3125 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3126 * Firmware will place the complete LLDP MIB in response buffer with the
3129 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3130 u8 bridge_type, void *buff, u16 buff_size,
3131 u16 old_len, u16 new_len, u16 offset,
3133 struct i40e_asq_cmd_details *cmd_details)
3135 struct i40e_aq_desc desc;
3136 struct i40e_aqc_lldp_update_tlv *cmd =
3137 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3138 enum i40e_status_code status;
3140 if (buff_size == 0 || !buff || offset == 0 ||
3141 old_len == 0 || new_len == 0)
3142 return I40E_ERR_PARAM;
3144 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3146 /* Indirect Command */
3147 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3148 if (buff_size > I40E_AQ_LARGE_BUF)
3149 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3150 desc.datalen = CPU_TO_LE16(buff_size);
3152 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3153 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3154 cmd->old_len = CPU_TO_LE16(old_len);
3155 cmd->new_offset = CPU_TO_LE16(offset);
3156 cmd->new_len = CPU_TO_LE16(new_len);
3158 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3160 if (mib_len != NULL)
3161 *mib_len = LE16_TO_CPU(desc.datalen);
3168 * i40e_aq_delete_lldp_tlv
3169 * @hw: pointer to the hw struct
3170 * @bridge_type: type of bridge
3171 * @buff: pointer to a user supplied buffer that has the TLV
3172 * @buff_size: length of the buffer
3173 * @tlv_len: length of the TLV to be deleted
3174 * @mib_len: length of the returned LLDP MIB
3175 * @cmd_details: pointer to command details structure or NULL
3177 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3178 * The firmware places the entire LLDP MIB in the response buffer.
3180 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3181 u8 bridge_type, void *buff, u16 buff_size,
3182 u16 tlv_len, u16 *mib_len,
3183 struct i40e_asq_cmd_details *cmd_details)
3185 struct i40e_aq_desc desc;
3186 struct i40e_aqc_lldp_add_tlv *cmd =
3187 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3188 enum i40e_status_code status;
3190 if (buff_size == 0 || !buff)
3191 return I40E_ERR_PARAM;
3193 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3195 /* Indirect Command */
3196 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3197 if (buff_size > I40E_AQ_LARGE_BUF)
3198 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3199 desc.datalen = CPU_TO_LE16(buff_size);
3200 cmd->len = CPU_TO_LE16(tlv_len);
3201 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3202 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3204 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3206 if (mib_len != NULL)
3207 *mib_len = LE16_TO_CPU(desc.datalen);
3215 * @hw: pointer to the hw struct
3216 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3217 * @cmd_details: pointer to command details structure or NULL
3219 * Stop or Shutdown the embedded LLDP Agent
3221 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3222 struct i40e_asq_cmd_details *cmd_details)
3224 struct i40e_aq_desc desc;
3225 struct i40e_aqc_lldp_stop *cmd =
3226 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3227 enum i40e_status_code status;
3229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3232 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3234 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3240 * i40e_aq_start_lldp
3241 * @hw: pointer to the hw struct
3242 * @cmd_details: pointer to command details structure or NULL
3244 * Start the embedded LLDP Agent on all ports.
3246 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3247 struct i40e_asq_cmd_details *cmd_details)
3249 struct i40e_aq_desc desc;
3250 struct i40e_aqc_lldp_start *cmd =
3251 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3252 enum i40e_status_code status;
3254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3256 cmd->command = I40E_AQ_LLDP_AGENT_START;
3258 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3264 * i40e_aq_get_cee_dcb_config
3265 * @hw: pointer to the hw struct
3266 * @buff: response buffer that stores CEE operational configuration
3267 * @buff_size: size of the buffer passed
3268 * @cmd_details: pointer to command details structure or NULL
3270 * Get CEE DCBX mode operational configuration from firmware
3272 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3273 void *buff, u16 buff_size,
3274 struct i40e_asq_cmd_details *cmd_details)
3276 struct i40e_aq_desc desc;
3277 enum i40e_status_code status;
3279 if (buff_size == 0 || !buff)
3280 return I40E_ERR_PARAM;
3282 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3284 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3285 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3292 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3293 * @hw: pointer to the hw struct
3294 * @start_agent: True if DCBx Agent needs to be Started
3295 * False if DCBx Agent needs to be Stopped
3296 * @cmd_details: pointer to command details structure or NULL
3298 * Start/Stop the embedded dcbx Agent
3300 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3302 struct i40e_asq_cmd_details *cmd_details)
3304 struct i40e_aq_desc desc;
3305 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3306 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3308 enum i40e_status_code status;
3310 i40e_fill_default_direct_cmd_desc(&desc,
3311 i40e_aqc_opc_lldp_stop_start_spec_agent);
3314 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3316 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3322 * i40e_aq_add_udp_tunnel
3323 * @hw: pointer to the hw struct
3324 * @udp_port: the UDP port to add
3325 * @header_len: length of the tunneling header length in DWords
3326 * @protocol_index: protocol index type
3327 * @filter_index: pointer to filter index
3328 * @cmd_details: pointer to command details structure or NULL
3330 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3331 u16 udp_port, u8 protocol_index,
3333 struct i40e_asq_cmd_details *cmd_details)
3335 struct i40e_aq_desc desc;
3336 struct i40e_aqc_add_udp_tunnel *cmd =
3337 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3338 struct i40e_aqc_del_udp_tunnel_completion *resp =
3339 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3340 enum i40e_status_code status;
3342 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3344 cmd->udp_port = CPU_TO_LE16(udp_port);
3345 cmd->protocol_type = protocol_index;
3347 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3350 *filter_index = resp->index;
3356 * i40e_aq_del_udp_tunnel
3357 * @hw: pointer to the hw struct
3358 * @index: filter index
3359 * @cmd_details: pointer to command details structure or NULL
3361 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3362 struct i40e_asq_cmd_details *cmd_details)
3364 struct i40e_aq_desc desc;
3365 struct i40e_aqc_remove_udp_tunnel *cmd =
3366 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3367 enum i40e_status_code status;
3369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3373 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3379 * i40e_aq_get_switch_resource_alloc (0x0204)
3380 * @hw: pointer to the hw struct
3381 * @num_entries: pointer to u8 to store the number of resource entries returned
3382 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3383 * to store the resource information for all resource types. Each
3384 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3385 * @count: size, in bytes, of the buffer provided
3386 * @cmd_details: pointer to command details structure or NULL
3388 * Query the resources allocated to a function.
3390 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3392 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3394 struct i40e_asq_cmd_details *cmd_details)
3396 struct i40e_aq_desc desc;
3397 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3398 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3399 enum i40e_status_code status;
3401 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3403 i40e_fill_default_direct_cmd_desc(&desc,
3404 i40e_aqc_opc_get_switch_resource_alloc);
3406 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3407 if (length > I40E_AQ_LARGE_BUF)
3408 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3410 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3413 *num_entries = cmd_resp->num_entries;
3419 * i40e_aq_delete_element - Delete switch element
3420 * @hw: pointer to the hw struct
3421 * @seid: the SEID to delete from the switch
3422 * @cmd_details: pointer to command details structure or NULL
3424 * This deletes a switch element from the switch.
3426 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3427 struct i40e_asq_cmd_details *cmd_details)
3429 struct i40e_aq_desc desc;
3430 struct i40e_aqc_switch_seid *cmd =
3431 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3432 enum i40e_status_code status;
3435 return I40E_ERR_PARAM;
3437 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3439 cmd->seid = CPU_TO_LE16(seid);
3441 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3447 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3448 * @hw: pointer to the hw struct
3449 * @flags: component flags
3450 * @mac_seid: uplink seid (MAC SEID)
3451 * @vsi_seid: connected vsi seid
3452 * @ret_seid: seid of create pv component
3454 * This instantiates an i40e port virtualizer with specified flags.
3455 * Depending on specified flags the port virtualizer can act as a
3456 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3458 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3459 u16 mac_seid, u16 vsi_seid,
3462 struct i40e_aq_desc desc;
3463 struct i40e_aqc_add_update_pv *cmd =
3464 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3465 struct i40e_aqc_add_update_pv_completion *resp =
3466 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3467 enum i40e_status_code status;
3470 return I40E_ERR_PARAM;
3472 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3473 cmd->command_flags = CPU_TO_LE16(flags);
3474 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3475 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3477 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3478 if (!status && ret_seid)
3479 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3485 * i40e_aq_add_tag - Add an S/E-tag
3486 * @hw: pointer to the hw struct
3487 * @direct_to_queue: should s-tag direct flow to a specific queue
3488 * @vsi_seid: VSI SEID to use this tag
3489 * @tag: value of the tag
3490 * @queue_num: queue number, only valid is direct_to_queue is true
3491 * @tags_used: return value, number of tags in use by this PF
3492 * @tags_free: return value, number of unallocated tags
3493 * @cmd_details: pointer to command details structure or NULL
3495 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3496 * the number of tags allocated by the PF, and the number of unallocated
3499 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3500 u16 vsi_seid, u16 tag, u16 queue_num,
3501 u16 *tags_used, u16 *tags_free,
3502 struct i40e_asq_cmd_details *cmd_details)
3504 struct i40e_aq_desc desc;
3505 struct i40e_aqc_add_tag *cmd =
3506 (struct i40e_aqc_add_tag *)&desc.params.raw;
3507 struct i40e_aqc_add_remove_tag_completion *resp =
3508 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3509 enum i40e_status_code status;
3512 return I40E_ERR_PARAM;
3514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3516 cmd->seid = CPU_TO_LE16(vsi_seid);
3517 cmd->tag = CPU_TO_LE16(tag);
3518 if (direct_to_queue) {
3519 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3520 cmd->queue_number = CPU_TO_LE16(queue_num);
3523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3526 if (tags_used != NULL)
3527 *tags_used = LE16_TO_CPU(resp->tags_used);
3528 if (tags_free != NULL)
3529 *tags_free = LE16_TO_CPU(resp->tags_free);
3536 * i40e_aq_remove_tag - Remove an S- or E-tag
3537 * @hw: pointer to the hw struct
3538 * @vsi_seid: VSI SEID this tag is associated with
3539 * @tag: value of the S-tag to delete
3540 * @tags_used: return value, number of tags in use by this PF
3541 * @tags_free: return value, number of unallocated tags
3542 * @cmd_details: pointer to command details structure or NULL
3544 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3545 * the number of tags allocated by the PF, and the number of unallocated
3548 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3549 u16 tag, u16 *tags_used, u16 *tags_free,
3550 struct i40e_asq_cmd_details *cmd_details)
3552 struct i40e_aq_desc desc;
3553 struct i40e_aqc_remove_tag *cmd =
3554 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3555 struct i40e_aqc_add_remove_tag_completion *resp =
3556 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3557 enum i40e_status_code status;
3560 return I40E_ERR_PARAM;
3562 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3564 cmd->seid = CPU_TO_LE16(vsi_seid);
3565 cmd->tag = CPU_TO_LE16(tag);
3567 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3570 if (tags_used != NULL)
3571 *tags_used = LE16_TO_CPU(resp->tags_used);
3572 if (tags_free != NULL)
3573 *tags_free = LE16_TO_CPU(resp->tags_free);
3580 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3581 * @hw: pointer to the hw struct
3582 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3583 * @etag: value of E-tag to add
3584 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3585 * @buf: address of indirect buffer
3586 * @tags_used: return value, number of E-tags in use by this port
3587 * @tags_free: return value, number of unallocated M-tags
3588 * @cmd_details: pointer to command details structure or NULL
3590 * This associates a multicast E-tag to a port virtualizer. It will return
3591 * the number of tags allocated by the PF, and the number of unallocated
3594 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3595 * num_tags_in_buf long.
3597 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3598 u16 etag, u8 num_tags_in_buf, void *buf,
3599 u16 *tags_used, u16 *tags_free,
3600 struct i40e_asq_cmd_details *cmd_details)
3602 struct i40e_aq_desc desc;
3603 struct i40e_aqc_add_remove_mcast_etag *cmd =
3604 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3605 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3606 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3607 enum i40e_status_code status;
3608 u16 length = sizeof(u16) * num_tags_in_buf;
3610 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3611 return I40E_ERR_PARAM;
3613 i40e_fill_default_direct_cmd_desc(&desc,
3614 i40e_aqc_opc_add_multicast_etag);
3616 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3617 cmd->etag = CPU_TO_LE16(etag);
3618 cmd->num_unicast_etags = num_tags_in_buf;
3620 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3621 if (length > I40E_AQ_LARGE_BUF)
3622 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3624 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3627 if (tags_used != NULL)
3628 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3629 if (tags_free != NULL)
3630 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3637 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3638 * @hw: pointer to the hw struct
3639 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3640 * @etag: value of the E-tag to remove
3641 * @tags_used: return value, number of tags in use by this port
3642 * @tags_free: return value, number of unallocated tags
3643 * @cmd_details: pointer to command details structure or NULL
3645 * This deletes an E-tag from the port virtualizer. It will return
3646 * the number of tags allocated by the port, and the number of unallocated
3649 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3650 u16 etag, u16 *tags_used, u16 *tags_free,
3651 struct i40e_asq_cmd_details *cmd_details)
3653 struct i40e_aq_desc desc;
3654 struct i40e_aqc_add_remove_mcast_etag *cmd =
3655 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3656 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3657 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3658 enum i40e_status_code status;
3662 return I40E_ERR_PARAM;
3664 i40e_fill_default_direct_cmd_desc(&desc,
3665 i40e_aqc_opc_remove_multicast_etag);
3667 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3668 cmd->etag = CPU_TO_LE16(etag);
3670 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3673 if (tags_used != NULL)
3674 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3675 if (tags_free != NULL)
3676 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3683 * i40e_aq_update_tag - Update an S/E-tag
3684 * @hw: pointer to the hw struct
3685 * @vsi_seid: VSI SEID using this S-tag
3686 * @old_tag: old tag value
3687 * @new_tag: new tag value
3688 * @tags_used: return value, number of tags in use by this PF
3689 * @tags_free: return value, number of unallocated tags
3690 * @cmd_details: pointer to command details structure or NULL
3692 * This updates the value of the tag currently attached to this VSI
3693 * in the switch complex. It will return the number of tags allocated
3694 * by the PF, and the number of unallocated tags available.
3696 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3697 u16 old_tag, u16 new_tag, u16 *tags_used,
3699 struct i40e_asq_cmd_details *cmd_details)
3701 struct i40e_aq_desc desc;
3702 struct i40e_aqc_update_tag *cmd =
3703 (struct i40e_aqc_update_tag *)&desc.params.raw;
3704 struct i40e_aqc_update_tag_completion *resp =
3705 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3706 enum i40e_status_code status;
3709 return I40E_ERR_PARAM;
3711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3713 cmd->seid = CPU_TO_LE16(vsi_seid);
3714 cmd->old_tag = CPU_TO_LE16(old_tag);
3715 cmd->new_tag = CPU_TO_LE16(new_tag);
3717 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3720 if (tags_used != NULL)
3721 *tags_used = LE16_TO_CPU(resp->tags_used);
3722 if (tags_free != NULL)
3723 *tags_free = LE16_TO_CPU(resp->tags_free);
3730 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3731 * @hw: pointer to the hw struct
3732 * @tcmap: TC map for request/release any ignore PFC condition
3733 * @request: request or release ignore PFC condition
3734 * @tcmap_ret: return TCs for which PFC is currently ignored
3735 * @cmd_details: pointer to command details structure or NULL
3737 * This sends out request/release to ignore PFC condition for a TC.
3738 * It will return the TCs for which PFC is currently ignored.
3740 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3741 bool request, u8 *tcmap_ret,
3742 struct i40e_asq_cmd_details *cmd_details)
3744 struct i40e_aq_desc desc;
3745 struct i40e_aqc_pfc_ignore *cmd_resp =
3746 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3747 enum i40e_status_code status;
3749 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3752 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3754 cmd_resp->tc_bitmap = tcmap;
3756 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3759 if (tcmap_ret != NULL)
3760 *tcmap_ret = cmd_resp->tc_bitmap;
3767 * i40e_aq_dcb_updated - DCB Updated Command
3768 * @hw: pointer to the hw struct
3769 * @cmd_details: pointer to command details structure or NULL
3771 * When LLDP is handled in PF this command is used by the PF
3772 * to notify EMP that a DCB setting is modified.
3773 * When LLDP is handled in EMP this command is used by the PF
3774 * to notify EMP whenever one of the following parameters get
3776 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3777 * - PCIRTT in PRTDCB_GENC.PCIRTT
3778 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3779 * EMP will return when the shared RPB settings have been
3780 * recomputed and modified. The retval field in the descriptor
3781 * will be set to 0 when RPB is modified.
3783 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3784 struct i40e_asq_cmd_details *cmd_details)
3786 struct i40e_aq_desc desc;
3787 enum i40e_status_code status;
3789 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3791 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3797 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3798 * @hw: pointer to the hw struct
3799 * @seid: defines the SEID of the switch for which the stats are requested
3800 * @vlan_id: the VLAN ID for which the statistics are requested
3801 * @stat_index: index of the statistics counters block assigned to this VLAN
3802 * @cmd_details: pointer to command details structure or NULL
3804 * XL710 supports 128 smonVlanStats counters.This command is used to
3805 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3808 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3809 u16 vlan_id, u16 *stat_index,
3810 struct i40e_asq_cmd_details *cmd_details)
3812 struct i40e_aq_desc desc;
3813 struct i40e_aqc_add_remove_statistics *cmd_resp =
3814 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3815 enum i40e_status_code status;
3817 if ((seid == 0) || (stat_index == NULL))
3818 return I40E_ERR_PARAM;
3820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3822 cmd_resp->seid = CPU_TO_LE16(seid);
3823 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3825 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3828 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3834 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3835 * @hw: pointer to the hw struct
3836 * @seid: defines the SEID of the switch for which the stats are requested
3837 * @vlan_id: the VLAN ID for which the statistics are requested
3838 * @stat_index: index of the statistics counters block assigned to this VLAN
3839 * @cmd_details: pointer to command details structure or NULL
3841 * XL710 supports 128 smonVlanStats counters.This command is used to
3842 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3845 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3846 u16 vlan_id, u16 stat_index,
3847 struct i40e_asq_cmd_details *cmd_details)
3849 struct i40e_aq_desc desc;
3850 struct i40e_aqc_add_remove_statistics *cmd =
3851 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3852 enum i40e_status_code status;
3855 return I40E_ERR_PARAM;
3857 i40e_fill_default_direct_cmd_desc(&desc,
3858 i40e_aqc_opc_remove_statistics);
3860 cmd->seid = CPU_TO_LE16(seid);
3861 cmd->vlan = CPU_TO_LE16(vlan_id);
3862 cmd->stat_index = CPU_TO_LE16(stat_index);
3864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3870 * i40e_aq_set_port_parameters - set physical port parameters.
3871 * @hw: pointer to the hw struct
3872 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3873 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3874 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3875 * @double_vlan: if set double VLAN is enabled
3876 * @cmd_details: pointer to command details structure or NULL
3878 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3879 u16 bad_frame_vsi, bool save_bad_pac,
3880 bool pad_short_pac, bool double_vlan,
3881 struct i40e_asq_cmd_details *cmd_details)
3883 struct i40e_aqc_set_port_parameters *cmd;
3884 enum i40e_status_code status;
3885 struct i40e_aq_desc desc;
3886 u16 command_flags = 0;
3888 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3890 i40e_fill_default_direct_cmd_desc(&desc,
3891 i40e_aqc_opc_set_port_parameters);
3893 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3895 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3897 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3899 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3900 cmd->command_flags = CPU_TO_LE16(command_flags);
3902 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3908 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3909 * @hw: pointer to the hw struct
3910 * @seid: seid for the physical port/switching component/vsi
3911 * @buff: Indirect buffer to hold data parameters and response
3912 * @buff_size: Indirect buffer size
3913 * @opcode: Tx scheduler AQ command opcode
3914 * @cmd_details: pointer to command details structure or NULL
3916 * Generic command handler for Tx scheduler AQ commands
3918 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3919 void *buff, u16 buff_size,
3920 enum i40e_admin_queue_opc opcode,
3921 struct i40e_asq_cmd_details *cmd_details)
3923 struct i40e_aq_desc desc;
3924 struct i40e_aqc_tx_sched_ind *cmd =
3925 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3926 enum i40e_status_code status;
3927 bool cmd_param_flag = false;
3930 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3931 case i40e_aqc_opc_configure_vsi_tc_bw:
3932 case i40e_aqc_opc_enable_switching_comp_ets:
3933 case i40e_aqc_opc_modify_switching_comp_ets:
3934 case i40e_aqc_opc_disable_switching_comp_ets:
3935 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3936 case i40e_aqc_opc_configure_switching_comp_bw_config:
3937 cmd_param_flag = true;
3939 case i40e_aqc_opc_query_vsi_bw_config:
3940 case i40e_aqc_opc_query_vsi_ets_sla_config:
3941 case i40e_aqc_opc_query_switching_comp_ets_config:
3942 case i40e_aqc_opc_query_port_ets_config:
3943 case i40e_aqc_opc_query_switching_comp_bw_config:
3944 cmd_param_flag = false;
3947 return I40E_ERR_PARAM;
3950 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3952 /* Indirect command */
3953 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3955 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3956 if (buff_size > I40E_AQ_LARGE_BUF)
3957 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3959 desc.datalen = CPU_TO_LE16(buff_size);
3961 cmd->vsi_seid = CPU_TO_LE16(seid);
3963 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3969 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3970 * @hw: pointer to the hw struct
3972 * @credit: BW limit credits (0 = disabled)
3973 * @max_credit: Max BW limit credits
3974 * @cmd_details: pointer to command details structure or NULL
3976 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3977 u16 seid, u16 credit, u8 max_credit,
3978 struct i40e_asq_cmd_details *cmd_details)
3980 struct i40e_aq_desc desc;
3981 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3982 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3983 enum i40e_status_code status;
3985 i40e_fill_default_direct_cmd_desc(&desc,
3986 i40e_aqc_opc_configure_vsi_bw_limit);
3988 cmd->vsi_seid = CPU_TO_LE16(seid);
3989 cmd->credit = CPU_TO_LE16(credit);
3990 cmd->max_credit = max_credit;
3992 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3998 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3999 * @hw: pointer to the hw struct
4000 * @seid: switching component seid
4001 * @credit: BW limit credits (0 = disabled)
4002 * @max_bw: Max BW limit credits
4003 * @cmd_details: pointer to command details structure or NULL
4005 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4006 u16 seid, u16 credit, u8 max_bw,
4007 struct i40e_asq_cmd_details *cmd_details)
4009 struct i40e_aq_desc desc;
4010 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4011 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4012 enum i40e_status_code status;
4014 i40e_fill_default_direct_cmd_desc(&desc,
4015 i40e_aqc_opc_configure_switching_comp_bw_limit);
4017 cmd->seid = CPU_TO_LE16(seid);
4018 cmd->credit = CPU_TO_LE16(credit);
4019 cmd->max_bw = max_bw;
4021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4027 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4028 * @hw: pointer to the hw struct
4030 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4031 * @cmd_details: pointer to command details structure or NULL
4033 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4035 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4036 struct i40e_asq_cmd_details *cmd_details)
4038 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4039 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4044 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4045 * @hw: pointer to the hw struct
4047 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4048 * @cmd_details: pointer to command details structure or NULL
4050 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4052 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4053 struct i40e_asq_cmd_details *cmd_details)
4055 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4056 i40e_aqc_opc_configure_vsi_tc_bw,
4061 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4062 * @hw: pointer to the hw struct
4063 * @seid: seid of the switching component
4064 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4065 * @cmd_details: pointer to command details structure or NULL
4067 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4068 struct i40e_hw *hw, u16 seid,
4069 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4070 struct i40e_asq_cmd_details *cmd_details)
4072 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4073 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4078 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4079 * @hw: pointer to the hw struct
4080 * @seid: seid of the VSI
4081 * @bw_data: Buffer to hold VSI BW configuration
4082 * @cmd_details: pointer to command details structure or NULL
4084 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4086 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4087 struct i40e_asq_cmd_details *cmd_details)
4089 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4090 i40e_aqc_opc_query_vsi_bw_config,
4095 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4096 * @hw: pointer to the hw struct
4097 * @seid: seid of the VSI
4098 * @bw_data: Buffer to hold VSI BW configuration per TC
4099 * @cmd_details: pointer to command details structure or NULL
4101 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4103 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4104 struct i40e_asq_cmd_details *cmd_details)
4106 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4107 i40e_aqc_opc_query_vsi_ets_sla_config,
4112 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4113 * @hw: pointer to the hw struct
4114 * @seid: seid of the switching component
4115 * @bw_data: Buffer to hold switching component's per TC BW config
4116 * @cmd_details: pointer to command details structure or NULL
4118 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4120 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4121 struct i40e_asq_cmd_details *cmd_details)
4123 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4124 i40e_aqc_opc_query_switching_comp_ets_config,
4129 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4130 * @hw: pointer to the hw struct
4131 * @seid: seid of the VSI or switching component connected to Physical Port
4132 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4133 * @cmd_details: pointer to command details structure or NULL
4135 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4137 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4138 struct i40e_asq_cmd_details *cmd_details)
4140 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4141 i40e_aqc_opc_query_port_ets_config,
4146 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4147 * @hw: pointer to the hw struct
4148 * @seid: seid of the switching component
4149 * @bw_data: Buffer to hold switching component's BW configuration
4150 * @cmd_details: pointer to command details structure or NULL
4152 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4154 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4155 struct i40e_asq_cmd_details *cmd_details)
4157 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4158 i40e_aqc_opc_query_switching_comp_bw_config,
4163 * i40e_validate_filter_settings
4164 * @hw: pointer to the hardware structure
4165 * @settings: Filter control settings
4167 * Check and validate the filter control settings passed.
4168 * The function checks for the valid filter/context sizes being
4169 * passed for FCoE and PE.
4171 * Returns I40E_SUCCESS if the values passed are valid and within
4172 * range else returns an error.
4174 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4175 struct i40e_filter_control_settings *settings)
4177 u32 fcoe_cntx_size, fcoe_filt_size;
4178 u32 pe_cntx_size, pe_filt_size;
4183 /* Validate FCoE settings passed */
4184 switch (settings->fcoe_filt_num) {
4185 case I40E_HASH_FILTER_SIZE_1K:
4186 case I40E_HASH_FILTER_SIZE_2K:
4187 case I40E_HASH_FILTER_SIZE_4K:
4188 case I40E_HASH_FILTER_SIZE_8K:
4189 case I40E_HASH_FILTER_SIZE_16K:
4190 case I40E_HASH_FILTER_SIZE_32K:
4191 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4192 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4195 return I40E_ERR_PARAM;
4198 switch (settings->fcoe_cntx_num) {
4199 case I40E_DMA_CNTX_SIZE_512:
4200 case I40E_DMA_CNTX_SIZE_1K:
4201 case I40E_DMA_CNTX_SIZE_2K:
4202 case I40E_DMA_CNTX_SIZE_4K:
4203 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4204 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4207 return I40E_ERR_PARAM;
4210 /* Validate PE settings passed */
4211 switch (settings->pe_filt_num) {
4212 case I40E_HASH_FILTER_SIZE_1K:
4213 case I40E_HASH_FILTER_SIZE_2K:
4214 case I40E_HASH_FILTER_SIZE_4K:
4215 case I40E_HASH_FILTER_SIZE_8K:
4216 case I40E_HASH_FILTER_SIZE_16K:
4217 case I40E_HASH_FILTER_SIZE_32K:
4218 case I40E_HASH_FILTER_SIZE_64K:
4219 case I40E_HASH_FILTER_SIZE_128K:
4220 case I40E_HASH_FILTER_SIZE_256K:
4221 case I40E_HASH_FILTER_SIZE_512K:
4222 case I40E_HASH_FILTER_SIZE_1M:
4223 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4224 pe_filt_size <<= (u32)settings->pe_filt_num;
4227 return I40E_ERR_PARAM;
4230 switch (settings->pe_cntx_num) {
4231 case I40E_DMA_CNTX_SIZE_512:
4232 case I40E_DMA_CNTX_SIZE_1K:
4233 case I40E_DMA_CNTX_SIZE_2K:
4234 case I40E_DMA_CNTX_SIZE_4K:
4235 case I40E_DMA_CNTX_SIZE_8K:
4236 case I40E_DMA_CNTX_SIZE_16K:
4237 case I40E_DMA_CNTX_SIZE_32K:
4238 case I40E_DMA_CNTX_SIZE_64K:
4239 case I40E_DMA_CNTX_SIZE_128K:
4240 case I40E_DMA_CNTX_SIZE_256K:
4241 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4242 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4245 return I40E_ERR_PARAM;
4248 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4249 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4250 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4251 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4252 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4253 return I40E_ERR_INVALID_SIZE;
4255 return I40E_SUCCESS;
4259 * i40e_set_filter_control
4260 * @hw: pointer to the hardware structure
4261 * @settings: Filter control settings
4263 * Set the Queue Filters for PE/FCoE and enable filters required
4264 * for a single PF. It is expected that these settings are programmed
4265 * at the driver initialization time.
4267 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4268 struct i40e_filter_control_settings *settings)
4270 enum i40e_status_code ret = I40E_SUCCESS;
4271 u32 hash_lut_size = 0;
4275 return I40E_ERR_PARAM;
4277 /* Validate the input settings */
4278 ret = i40e_validate_filter_settings(hw, settings);
4282 /* Read the PF Queue Filter control register */
4283 val = rd32(hw, I40E_PFQF_CTL_0);
4285 /* Program required PE hash buckets for the PF */
4286 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4287 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4288 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4289 /* Program required PE contexts for the PF */
4290 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4291 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4292 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4294 /* Program required FCoE hash buckets for the PF */
4295 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4296 val |= ((u32)settings->fcoe_filt_num <<
4297 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4298 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4299 /* Program required FCoE DDP contexts for the PF */
4300 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4301 val |= ((u32)settings->fcoe_cntx_num <<
4302 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4303 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4305 /* Program Hash LUT size for the PF */
4306 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4307 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4309 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4310 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4312 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4313 if (settings->enable_fdir)
4314 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4315 if (settings->enable_ethtype)
4316 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4317 if (settings->enable_macvlan)
4318 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4320 wr32(hw, I40E_PFQF_CTL_0, val);
4322 return I40E_SUCCESS;
4326 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4327 * @hw: pointer to the hw struct
4328 * @mac_addr: MAC address to use in the filter
4329 * @ethtype: Ethertype to use in the filter
4330 * @flags: Flags that needs to be applied to the filter
4331 * @vsi_seid: seid of the control VSI
4332 * @queue: VSI queue number to send the packet to
4333 * @is_add: Add control packet filter if True else remove
4334 * @stats: Structure to hold information on control filter counts
4335 * @cmd_details: pointer to command details structure or NULL
4337 * This command will Add or Remove control packet filter for a control VSI.
4338 * In return it will update the total number of perfect filter count in
4341 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4342 u8 *mac_addr, u16 ethtype, u16 flags,
4343 u16 vsi_seid, u16 queue, bool is_add,
4344 struct i40e_control_filter_stats *stats,
4345 struct i40e_asq_cmd_details *cmd_details)
4347 struct i40e_aq_desc desc;
4348 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4349 (struct i40e_aqc_add_remove_control_packet_filter *)
4351 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4352 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4354 enum i40e_status_code status;
4357 return I40E_ERR_PARAM;
4360 i40e_fill_default_direct_cmd_desc(&desc,
4361 i40e_aqc_opc_add_control_packet_filter);
4362 cmd->queue = CPU_TO_LE16(queue);
4364 i40e_fill_default_direct_cmd_desc(&desc,
4365 i40e_aqc_opc_remove_control_packet_filter);
4369 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4370 I40E_NONDMA_TO_NONDMA);
4372 cmd->etype = CPU_TO_LE16(ethtype);
4373 cmd->flags = CPU_TO_LE16(flags);
4374 cmd->seid = CPU_TO_LE16(vsi_seid);
4376 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4378 if (!status && stats) {
4379 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4380 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4381 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4382 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4389 * i40e_aq_add_cloud_filters
4390 * @hw: pointer to the hardware structure
4391 * @seid: VSI seid to add cloud filters from
4392 * @filters: Buffer which contains the filters to be added
4393 * @filter_count: number of filters contained in the buffer
4395 * Set the cloud filters for a given VSI. The contents of the
4396 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4397 * in by the caller of the function.
4400 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4402 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4405 struct i40e_aq_desc desc;
4406 struct i40e_aqc_add_remove_cloud_filters *cmd =
4407 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4409 enum i40e_status_code status;
4411 i40e_fill_default_direct_cmd_desc(&desc,
4412 i40e_aqc_opc_add_cloud_filters);
4414 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4416 desc.datalen = CPU_TO_LE16(buff_len);
4417 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4418 cmd->num_filters = filter_count;
4419 cmd->seid = CPU_TO_LE16(seid);
4421 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4427 * i40e_aq_remove_cloud_filters
4428 * @hw: pointer to the hardware structure
4429 * @seid: VSI seid to remove cloud filters from
4430 * @filters: Buffer which contains the filters to be removed
4431 * @filter_count: number of filters contained in the buffer
4433 * Remove the cloud filters for a given VSI. The contents of the
4434 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4435 * in by the caller of the function.
4438 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4440 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4443 struct i40e_aq_desc desc;
4444 struct i40e_aqc_add_remove_cloud_filters *cmd =
4445 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4446 enum i40e_status_code status;
4449 i40e_fill_default_direct_cmd_desc(&desc,
4450 i40e_aqc_opc_remove_cloud_filters);
4452 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4454 desc.datalen = CPU_TO_LE16(buff_len);
4455 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4456 cmd->num_filters = filter_count;
4457 cmd->seid = CPU_TO_LE16(seid);
4459 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4465 * i40e_aq_alternate_write
4466 * @hw: pointer to the hardware structure
4467 * @reg_addr0: address of first dword to be read
4468 * @reg_val0: value to be written under 'reg_addr0'
4469 * @reg_addr1: address of second dword to be read
4470 * @reg_val1: value to be written under 'reg_addr1'
4472 * Write one or two dwords to alternate structure. Fields are indicated
4473 * by 'reg_addr0' and 'reg_addr1' register numbers.
4476 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4477 u32 reg_addr0, u32 reg_val0,
4478 u32 reg_addr1, u32 reg_val1)
4480 struct i40e_aq_desc desc;
4481 struct i40e_aqc_alternate_write *cmd_resp =
4482 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4483 enum i40e_status_code status;
4485 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4486 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4487 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4488 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4489 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4491 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4497 * i40e_aq_alternate_write_indirect
4498 * @hw: pointer to the hardware structure
4499 * @addr: address of a first register to be modified
4500 * @dw_count: number of alternate structure fields to write
4501 * @buffer: pointer to the command buffer
4503 * Write 'dw_count' dwords from 'buffer' to alternate structure
4504 * starting at 'addr'.
4507 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4508 u32 addr, u32 dw_count, void *buffer)
4510 struct i40e_aq_desc desc;
4511 struct i40e_aqc_alternate_ind_write *cmd_resp =
4512 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4513 enum i40e_status_code status;
4516 return I40E_ERR_PARAM;
4518 /* Indirect command */
4519 i40e_fill_default_direct_cmd_desc(&desc,
4520 i40e_aqc_opc_alternate_write_indirect);
4522 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4523 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4524 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4527 cmd_resp->address = CPU_TO_LE32(addr);
4528 cmd_resp->length = CPU_TO_LE32(dw_count);
4529 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4530 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4532 status = i40e_asq_send_command(hw, &desc, buffer,
4533 I40E_LO_DWORD(4*dw_count), NULL);
4539 * i40e_aq_alternate_read
4540 * @hw: pointer to the hardware structure
4541 * @reg_addr0: address of first dword to be read
4542 * @reg_val0: pointer for data read from 'reg_addr0'
4543 * @reg_addr1: address of second dword to be read
4544 * @reg_val1: pointer for data read from 'reg_addr1'
4546 * Read one or two dwords from alternate structure. Fields are indicated
4547 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4548 * is not passed then only register at 'reg_addr0' is read.
4551 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4552 u32 reg_addr0, u32 *reg_val0,
4553 u32 reg_addr1, u32 *reg_val1)
4555 struct i40e_aq_desc desc;
4556 struct i40e_aqc_alternate_write *cmd_resp =
4557 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4558 enum i40e_status_code status;
4560 if (reg_val0 == NULL)
4561 return I40E_ERR_PARAM;
4563 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4564 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4565 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4567 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4569 if (status == I40E_SUCCESS) {
4570 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4572 if (reg_val1 != NULL)
4573 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4580 * i40e_aq_alternate_read_indirect
4581 * @hw: pointer to the hardware structure
4582 * @addr: address of the alternate structure field
4583 * @dw_count: number of alternate structure fields to read
4584 * @buffer: pointer to the command buffer
4586 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4587 * place them in 'buffer'. The buffer should be allocated by caller.
4590 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4591 u32 addr, u32 dw_count, void *buffer)
4593 struct i40e_aq_desc desc;
4594 struct i40e_aqc_alternate_ind_write *cmd_resp =
4595 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4596 enum i40e_status_code status;
4599 return I40E_ERR_PARAM;
4601 /* Indirect command */
4602 i40e_fill_default_direct_cmd_desc(&desc,
4603 i40e_aqc_opc_alternate_read_indirect);
4605 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4606 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4607 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4608 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4610 cmd_resp->address = CPU_TO_LE32(addr);
4611 cmd_resp->length = CPU_TO_LE32(dw_count);
4612 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4613 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4615 status = i40e_asq_send_command(hw, &desc, buffer,
4616 I40E_LO_DWORD(4*dw_count), NULL);
4622 * i40e_aq_alternate_clear
4623 * @hw: pointer to the HW structure.
4625 * Clear the alternate structures of the port from which the function
4629 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4631 struct i40e_aq_desc desc;
4632 enum i40e_status_code status;
4634 i40e_fill_default_direct_cmd_desc(&desc,
4635 i40e_aqc_opc_alternate_clear_port);
4637 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4643 * i40e_aq_alternate_write_done
4644 * @hw: pointer to the HW structure.
4645 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4646 * @reset_needed: indicates the SW should trigger GLOBAL reset
4648 * Indicates to the FW that alternate structures have been changed.
4651 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4652 u8 bios_mode, bool *reset_needed)
4654 struct i40e_aq_desc desc;
4655 struct i40e_aqc_alternate_write_done *cmd =
4656 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4657 enum i40e_status_code status;
4659 if (reset_needed == NULL)
4660 return I40E_ERR_PARAM;
4662 i40e_fill_default_direct_cmd_desc(&desc,
4663 i40e_aqc_opc_alternate_write_done);
4665 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4667 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4669 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4670 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4676 * i40e_aq_set_oem_mode
4677 * @hw: pointer to the HW structure.
4678 * @oem_mode: the OEM mode to be used
4680 * Sets the device to a specific operating mode. Currently the only supported
4681 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4684 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4687 struct i40e_aq_desc desc;
4688 struct i40e_aqc_alternate_write_done *cmd =
4689 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4690 enum i40e_status_code status;
4692 i40e_fill_default_direct_cmd_desc(&desc,
4693 i40e_aqc_opc_alternate_set_mode);
4695 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4697 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4703 * i40e_aq_resume_port_tx
4704 * @hw: pointer to the hardware structure
4705 * @cmd_details: pointer to command details structure or NULL
4707 * Resume port's Tx traffic
4709 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4710 struct i40e_asq_cmd_details *cmd_details)
4712 struct i40e_aq_desc desc;
4713 enum i40e_status_code status;
4715 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4717 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4723 * i40e_set_pci_config_data - store PCI bus info
4724 * @hw: pointer to hardware structure
4725 * @link_status: the link status word from PCI config space
4727 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4729 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4731 hw->bus.type = i40e_bus_type_pci_express;
4733 switch (link_status & I40E_PCI_LINK_WIDTH) {
4734 case I40E_PCI_LINK_WIDTH_1:
4735 hw->bus.width = i40e_bus_width_pcie_x1;
4737 case I40E_PCI_LINK_WIDTH_2:
4738 hw->bus.width = i40e_bus_width_pcie_x2;
4740 case I40E_PCI_LINK_WIDTH_4:
4741 hw->bus.width = i40e_bus_width_pcie_x4;
4743 case I40E_PCI_LINK_WIDTH_8:
4744 hw->bus.width = i40e_bus_width_pcie_x8;
4747 hw->bus.width = i40e_bus_width_unknown;
4751 switch (link_status & I40E_PCI_LINK_SPEED) {
4752 case I40E_PCI_LINK_SPEED_2500:
4753 hw->bus.speed = i40e_bus_speed_2500;
4755 case I40E_PCI_LINK_SPEED_5000:
4756 hw->bus.speed = i40e_bus_speed_5000;
4758 case I40E_PCI_LINK_SPEED_8000:
4759 hw->bus.speed = i40e_bus_speed_8000;
4762 hw->bus.speed = i40e_bus_speed_unknown;
4768 * i40e_read_bw_from_alt_ram
4769 * @hw: pointer to the hardware structure
4770 * @max_bw: pointer for max_bw read
4771 * @min_bw: pointer for min_bw read
4772 * @min_valid: pointer for bool that is true if min_bw is a valid value
4773 * @max_valid: pointer for bool that is true if max_bw is a valid value
4775 * Read bw from the alternate ram for the given pf
4777 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4778 u32 *max_bw, u32 *min_bw,
4779 bool *min_valid, bool *max_valid)
4781 enum i40e_status_code status;
4782 u32 max_bw_addr, min_bw_addr;
4784 /* Calculate the address of the min/max bw registers */
4785 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4786 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4787 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4788 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4789 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4790 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4792 /* Read the bandwidths from alt ram */
4793 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4794 min_bw_addr, min_bw);
4796 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4801 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4810 * i40e_aq_configure_partition_bw
4811 * @hw: pointer to the hardware structure
4812 * @bw_data: Buffer holding valid pfs and bw limits
4813 * @cmd_details: pointer to command details
4815 * Configure partitions guaranteed/max bw
4817 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4818 struct i40e_aqc_configure_partition_bw_data *bw_data,
4819 struct i40e_asq_cmd_details *cmd_details)
4821 enum i40e_status_code status;
4822 struct i40e_aq_desc desc;
4823 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4825 i40e_fill_default_direct_cmd_desc(&desc,
4826 i40e_aqc_opc_configure_partition_bw);
4828 /* Indirect command */
4829 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4830 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4832 if (bwd_size > I40E_AQ_LARGE_BUF)
4833 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4835 desc.datalen = CPU_TO_LE16(bwd_size);
4837 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4841 #endif /* PF_DRIVER */
4845 * i40e_aq_send_msg_to_pf
4846 * @hw: pointer to the hardware structure
4847 * @v_opcode: opcodes for VF-PF communication
4848 * @v_retval: return error code
4849 * @msg: pointer to the msg buffer
4850 * @msglen: msg length
4851 * @cmd_details: pointer to command details
4853 * Send message to PF driver using admin queue. By default, this message
4854 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4855 * completion before returning.
4857 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4858 enum i40e_virtchnl_ops v_opcode,
4859 enum i40e_status_code v_retval,
4860 u8 *msg, u16 msglen,
4861 struct i40e_asq_cmd_details *cmd_details)
4863 struct i40e_aq_desc desc;
4864 struct i40e_asq_cmd_details details;
4865 enum i40e_status_code status;
4867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4868 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4869 desc.cookie_high = CPU_TO_LE32(v_opcode);
4870 desc.cookie_low = CPU_TO_LE32(v_retval);
4872 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4873 | I40E_AQ_FLAG_RD));
4874 if (msglen > I40E_AQ_LARGE_BUF)
4875 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4876 desc.datalen = CPU_TO_LE16(msglen);
4879 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4880 details.async = true;
4881 cmd_details = &details;
4883 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4884 msglen, cmd_details);
4889 * i40e_vf_parse_hw_config
4890 * @hw: pointer to the hardware structure
4891 * @msg: pointer to the virtual channel VF resource structure
4893 * Given a VF resource message from the PF, populate the hw struct
4894 * with appropriate information.
4896 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4897 struct i40e_virtchnl_vf_resource *msg)
4899 struct i40e_virtchnl_vsi_resource *vsi_res;
4902 vsi_res = &msg->vsi_res[0];
4904 hw->dev_caps.num_vsis = msg->num_vsis;
4905 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4906 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4907 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4908 hw->dev_caps.dcb = msg->vf_offload_flags &
4909 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4910 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4911 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4912 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4913 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4914 for (i = 0; i < msg->num_vsis; i++) {
4915 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4916 i40e_memcpy(hw->mac.perm_addr,
4917 vsi_res->default_mac_addr,
4918 I40E_ETH_LENGTH_OF_ADDRESS,
4919 I40E_NONDMA_TO_NONDMA);
4920 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4921 I40E_ETH_LENGTH_OF_ADDRESS,
4922 I40E_NONDMA_TO_NONDMA);
4930 * @hw: pointer to the hardware structure
4932 * Send a VF_RESET message to the PF. Does not wait for response from PF
4933 * as none will be forthcoming. Immediately after calling this function,
4934 * the admin queue should be shut down and (optionally) reinitialized.
4936 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4938 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4939 I40E_SUCCESS, NULL, 0, NULL);
4941 #endif /* VF_DRIVER */