1 /*******************************************************************************
3 Copyright (c) 2013 - 2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
93 * Dumps debug log about adminq command with descriptor contents.
95 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
98 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
99 u8 *aq_buffer = (u8 *)buffer;
103 if ((!(mask & hw->debug_mask)) || (desc == NULL))
107 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
108 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
110 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
111 aq_desc->cookie_high, aq_desc->cookie_low);
112 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
113 aq_desc->params.internal.param0,
114 aq_desc->params.internal.param1);
115 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
116 aq_desc->params.external.addr_high,
117 aq_desc->params.external.addr_low);
119 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
120 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
121 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
122 for (i = 0; i < LE16_TO_CPU(aq_desc->datalen); i++) {
123 data[((i % 16) / 4)] |=
124 ((u32)aq_buffer[i]) << (8 * (i % 4));
125 if ((i % 16) == 15) {
127 "\t0x%04X %08X %08X %08X %08X\n",
128 i - 15, data[0], data[1], data[2],
130 i40e_memset(data, 0, sizeof(data),
135 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
136 i - (i % 16), data[0], data[1], data[2],
142 * i40e_check_asq_alive
143 * @hw: pointer to the hw struct
145 * Returns true if Queue is enabled else false.
147 bool i40e_check_asq_alive(struct i40e_hw *hw)
150 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
156 * i40e_aq_queue_shutdown
157 * @hw: pointer to the hw struct
158 * @unloading: is the driver unloading itself
160 * Tell the Firmware that we're shutting down the AdminQ and whether
161 * or not the driver is unloading as well.
163 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
166 struct i40e_aq_desc desc;
167 struct i40e_aqc_queue_shutdown *cmd =
168 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
169 enum i40e_status_code status;
171 i40e_fill_default_direct_cmd_desc(&desc,
172 i40e_aqc_opc_queue_shutdown);
175 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
176 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
181 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
182 * hardware to a bit-field that can be used by SW to more easily determine the
185 * Macros are used to shorten the table lines and make this table human
188 * We store the PTYPE in the top byte of the bit field - this is just so that
189 * we can check that the table doesn't have a row missing, as the index into
190 * the table should be the PTYPE.
194 * IF NOT i40e_ptype_lookup[ptype].known
197 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
198 * Use the rest of the fields to look at the tunnels, inner protocols, etc
200 * Use the enum i40e_rx_l2_ptype to decode the packet type
204 /* macro to make the table lines short */
205 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
208 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
209 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
210 I40E_RX_PTYPE_##OUTER_FRAG, \
211 I40E_RX_PTYPE_TUNNEL_##T, \
212 I40E_RX_PTYPE_TUNNEL_END_##TE, \
213 I40E_RX_PTYPE_##TEF, \
214 I40E_RX_PTYPE_INNER_PROT_##I, \
215 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
217 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
218 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
220 /* shorter macros makes the table fit but are terse */
221 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
222 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
223 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
225 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
226 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
227 /* L2 Packet types */
228 I40E_PTT_UNUSED_ENTRY(0),
229 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
231 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
232 I40E_PTT_UNUSED_ENTRY(4),
233 I40E_PTT_UNUSED_ENTRY(5),
234 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
235 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
236 I40E_PTT_UNUSED_ENTRY(8),
237 I40E_PTT_UNUSED_ENTRY(9),
238 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
239 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
240 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 /* Non Tunneled IPv4 */
252 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
255 I40E_PTT_UNUSED_ENTRY(25),
256 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
257 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
258 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
261 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
262 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
263 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(32),
265 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
266 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
267 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
270 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
271 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
272 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
273 I40E_PTT_UNUSED_ENTRY(39),
274 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
275 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
276 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
278 /* IPv4 --> GRE/NAT */
279 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
281 /* IPv4 --> GRE/NAT --> IPv4 */
282 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
283 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
284 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(47),
286 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
287 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
288 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
290 /* IPv4 --> GRE/NAT --> IPv6 */
291 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
292 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
293 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
294 I40E_PTT_UNUSED_ENTRY(54),
295 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
296 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
297 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
299 /* IPv4 --> GRE/NAT --> MAC */
300 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
302 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
303 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
304 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
305 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(62),
307 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
308 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
309 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
311 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
312 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
313 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
314 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
315 I40E_PTT_UNUSED_ENTRY(69),
316 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
317 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
318 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
320 /* IPv4 --> GRE/NAT --> MAC/VLAN */
321 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
323 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
324 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
325 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
326 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(77),
328 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
329 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
330 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
332 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
333 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
334 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
335 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
336 I40E_PTT_UNUSED_ENTRY(84),
337 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
338 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
339 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
341 /* Non Tunneled IPv6 */
342 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
343 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
344 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
345 I40E_PTT_UNUSED_ENTRY(91),
346 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
347 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
348 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
351 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
352 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
353 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
354 I40E_PTT_UNUSED_ENTRY(98),
355 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
356 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
357 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
360 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
361 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
362 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
363 I40E_PTT_UNUSED_ENTRY(105),
364 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
365 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
366 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
368 /* IPv6 --> GRE/NAT */
369 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
371 /* IPv6 --> GRE/NAT -> IPv4 */
372 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
373 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
374 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(113),
376 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
377 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
378 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
380 /* IPv6 --> GRE/NAT -> IPv6 */
381 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
382 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
383 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
384 I40E_PTT_UNUSED_ENTRY(120),
385 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
386 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
387 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
389 /* IPv6 --> GRE/NAT -> MAC */
390 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
392 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
393 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
394 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
395 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(128),
397 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
398 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
399 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
401 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
402 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
403 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
404 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
405 I40E_PTT_UNUSED_ENTRY(135),
406 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
407 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
408 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
410 /* IPv6 --> GRE/NAT -> MAC/VLAN */
411 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
414 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
415 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
416 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(143),
418 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
419 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
420 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
422 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
423 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
424 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
425 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
426 I40E_PTT_UNUSED_ENTRY(150),
427 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
428 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
429 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
432 I40E_PTT_UNUSED_ENTRY(154),
433 I40E_PTT_UNUSED_ENTRY(155),
434 I40E_PTT_UNUSED_ENTRY(156),
435 I40E_PTT_UNUSED_ENTRY(157),
436 I40E_PTT_UNUSED_ENTRY(158),
437 I40E_PTT_UNUSED_ENTRY(159),
439 I40E_PTT_UNUSED_ENTRY(160),
440 I40E_PTT_UNUSED_ENTRY(161),
441 I40E_PTT_UNUSED_ENTRY(162),
442 I40E_PTT_UNUSED_ENTRY(163),
443 I40E_PTT_UNUSED_ENTRY(164),
444 I40E_PTT_UNUSED_ENTRY(165),
445 I40E_PTT_UNUSED_ENTRY(166),
446 I40E_PTT_UNUSED_ENTRY(167),
447 I40E_PTT_UNUSED_ENTRY(168),
448 I40E_PTT_UNUSED_ENTRY(169),
450 I40E_PTT_UNUSED_ENTRY(170),
451 I40E_PTT_UNUSED_ENTRY(171),
452 I40E_PTT_UNUSED_ENTRY(172),
453 I40E_PTT_UNUSED_ENTRY(173),
454 I40E_PTT_UNUSED_ENTRY(174),
455 I40E_PTT_UNUSED_ENTRY(175),
456 I40E_PTT_UNUSED_ENTRY(176),
457 I40E_PTT_UNUSED_ENTRY(177),
458 I40E_PTT_UNUSED_ENTRY(178),
459 I40E_PTT_UNUSED_ENTRY(179),
461 I40E_PTT_UNUSED_ENTRY(180),
462 I40E_PTT_UNUSED_ENTRY(181),
463 I40E_PTT_UNUSED_ENTRY(182),
464 I40E_PTT_UNUSED_ENTRY(183),
465 I40E_PTT_UNUSED_ENTRY(184),
466 I40E_PTT_UNUSED_ENTRY(185),
467 I40E_PTT_UNUSED_ENTRY(186),
468 I40E_PTT_UNUSED_ENTRY(187),
469 I40E_PTT_UNUSED_ENTRY(188),
470 I40E_PTT_UNUSED_ENTRY(189),
472 I40E_PTT_UNUSED_ENTRY(190),
473 I40E_PTT_UNUSED_ENTRY(191),
474 I40E_PTT_UNUSED_ENTRY(192),
475 I40E_PTT_UNUSED_ENTRY(193),
476 I40E_PTT_UNUSED_ENTRY(194),
477 I40E_PTT_UNUSED_ENTRY(195),
478 I40E_PTT_UNUSED_ENTRY(196),
479 I40E_PTT_UNUSED_ENTRY(197),
480 I40E_PTT_UNUSED_ENTRY(198),
481 I40E_PTT_UNUSED_ENTRY(199),
483 I40E_PTT_UNUSED_ENTRY(200),
484 I40E_PTT_UNUSED_ENTRY(201),
485 I40E_PTT_UNUSED_ENTRY(202),
486 I40E_PTT_UNUSED_ENTRY(203),
487 I40E_PTT_UNUSED_ENTRY(204),
488 I40E_PTT_UNUSED_ENTRY(205),
489 I40E_PTT_UNUSED_ENTRY(206),
490 I40E_PTT_UNUSED_ENTRY(207),
491 I40E_PTT_UNUSED_ENTRY(208),
492 I40E_PTT_UNUSED_ENTRY(209),
494 I40E_PTT_UNUSED_ENTRY(210),
495 I40E_PTT_UNUSED_ENTRY(211),
496 I40E_PTT_UNUSED_ENTRY(212),
497 I40E_PTT_UNUSED_ENTRY(213),
498 I40E_PTT_UNUSED_ENTRY(214),
499 I40E_PTT_UNUSED_ENTRY(215),
500 I40E_PTT_UNUSED_ENTRY(216),
501 I40E_PTT_UNUSED_ENTRY(217),
502 I40E_PTT_UNUSED_ENTRY(218),
503 I40E_PTT_UNUSED_ENTRY(219),
505 I40E_PTT_UNUSED_ENTRY(220),
506 I40E_PTT_UNUSED_ENTRY(221),
507 I40E_PTT_UNUSED_ENTRY(222),
508 I40E_PTT_UNUSED_ENTRY(223),
509 I40E_PTT_UNUSED_ENTRY(224),
510 I40E_PTT_UNUSED_ENTRY(225),
511 I40E_PTT_UNUSED_ENTRY(226),
512 I40E_PTT_UNUSED_ENTRY(227),
513 I40E_PTT_UNUSED_ENTRY(228),
514 I40E_PTT_UNUSED_ENTRY(229),
516 I40E_PTT_UNUSED_ENTRY(230),
517 I40E_PTT_UNUSED_ENTRY(231),
518 I40E_PTT_UNUSED_ENTRY(232),
519 I40E_PTT_UNUSED_ENTRY(233),
520 I40E_PTT_UNUSED_ENTRY(234),
521 I40E_PTT_UNUSED_ENTRY(235),
522 I40E_PTT_UNUSED_ENTRY(236),
523 I40E_PTT_UNUSED_ENTRY(237),
524 I40E_PTT_UNUSED_ENTRY(238),
525 I40E_PTT_UNUSED_ENTRY(239),
527 I40E_PTT_UNUSED_ENTRY(240),
528 I40E_PTT_UNUSED_ENTRY(241),
529 I40E_PTT_UNUSED_ENTRY(242),
530 I40E_PTT_UNUSED_ENTRY(243),
531 I40E_PTT_UNUSED_ENTRY(244),
532 I40E_PTT_UNUSED_ENTRY(245),
533 I40E_PTT_UNUSED_ENTRY(246),
534 I40E_PTT_UNUSED_ENTRY(247),
535 I40E_PTT_UNUSED_ENTRY(248),
536 I40E_PTT_UNUSED_ENTRY(249),
538 I40E_PTT_UNUSED_ENTRY(250),
539 I40E_PTT_UNUSED_ENTRY(251),
540 I40E_PTT_UNUSED_ENTRY(252),
541 I40E_PTT_UNUSED_ENTRY(253),
542 I40E_PTT_UNUSED_ENTRY(254),
543 I40E_PTT_UNUSED_ENTRY(255)
549 * i40e_init_shared_code - Initialize the shared code
550 * @hw: pointer to hardware structure
552 * This assigns the MAC type and PHY code and inits the NVM.
553 * Does not touch the hardware. This function must be called prior to any
554 * other function in the shared code. The i40e_hw structure should be
555 * memset to 0 prior to calling this function. The following fields in
556 * hw structure should be filled in prior to calling this function:
557 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
558 * subsystem_vendor_id, and revision_id
560 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
562 enum i40e_status_code status = I40E_SUCCESS;
565 DEBUGFUNC("i40e_init_shared_code");
567 i40e_set_mac_type(hw);
569 switch (hw->mac.type) {
573 return I40E_ERR_DEVICE_NOT_SUPPORTED;
576 hw->phy.get_link_info = true;
578 /* Determine port number */
579 reg = rd32(hw, I40E_PFGEN_PORTNUM);
580 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
581 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
584 /* Determine the PF number based on the PCI fn */
585 reg = rd32(hw, I40E_GLPCI_CAPSUP);
586 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
587 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
589 hw->pf_id = (u8)hw->bus.func;
591 status = i40e_init_nvm(hw);
596 * i40e_aq_mac_address_read - Retrieve the MAC addresses
597 * @hw: pointer to the hw struct
598 * @flags: a return indicator of what addresses were added to the addr store
599 * @addrs: the requestor's mac addr store
600 * @cmd_details: pointer to command details structure or NULL
602 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
604 struct i40e_aqc_mac_address_read_data *addrs,
605 struct i40e_asq_cmd_details *cmd_details)
607 struct i40e_aq_desc desc;
608 struct i40e_aqc_mac_address_read *cmd_data =
609 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
610 enum i40e_status_code status;
612 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
613 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
615 status = i40e_asq_send_command(hw, &desc, addrs,
616 sizeof(*addrs), cmd_details);
617 *flags = LE16_TO_CPU(cmd_data->command_flags);
623 * i40e_aq_mac_address_write - Change the MAC addresses
624 * @hw: pointer to the hw struct
625 * @flags: indicates which MAC to be written
626 * @mac_addr: address to write
627 * @cmd_details: pointer to command details structure or NULL
629 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
630 u16 flags, u8 *mac_addr,
631 struct i40e_asq_cmd_details *cmd_details)
633 struct i40e_aq_desc desc;
634 struct i40e_aqc_mac_address_write *cmd_data =
635 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
636 enum i40e_status_code status;
638 i40e_fill_default_direct_cmd_desc(&desc,
639 i40e_aqc_opc_mac_address_write);
640 cmd_data->command_flags = CPU_TO_LE16(flags);
641 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
642 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
643 ((u32)mac_addr[3] << 16) |
644 ((u32)mac_addr[4] << 8) |
647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
653 * i40e_get_mac_addr - get MAC address
654 * @hw: pointer to the HW structure
655 * @mac_addr: pointer to MAC address
657 * Reads the adapter's MAC address from register
659 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
661 struct i40e_aqc_mac_address_read_data addrs;
662 enum i40e_status_code status;
665 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
667 if (flags & I40E_AQC_LAN_ADDR_VALID)
668 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
674 * i40e_get_port_mac_addr - get Port MAC address
675 * @hw: pointer to the HW structure
676 * @mac_addr: pointer to Port MAC address
678 * Reads the adapter's Port MAC address
680 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
682 struct i40e_aqc_mac_address_read_data addrs;
683 enum i40e_status_code status;
686 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
690 if (flags & I40E_AQC_PORT_ADDR_VALID)
691 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
693 status = I40E_ERR_INVALID_MAC_ADDR;
699 * i40e_pre_tx_queue_cfg - pre tx queue configure
700 * @hw: pointer to the HW structure
701 * @queue: target pf queue index
702 * @enable: state change request
704 * Handles hw requirement to indicate intention to enable
705 * or disable target queue.
707 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
709 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
713 if (abs_queue_idx >= 128) {
714 reg_block = abs_queue_idx / 128;
715 abs_queue_idx %= 128;
718 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
719 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
720 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
723 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
725 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
727 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
731 * i40e_validate_mac_addr - Validate unicast MAC address
732 * @mac_addr: pointer to MAC address
734 * Tests a MAC address to ensure it is a valid Individual Address
736 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
738 enum i40e_status_code status = I40E_SUCCESS;
740 DEBUGFUNC("i40e_validate_mac_addr");
742 /* Broadcast addresses ARE multicast addresses
743 * Make sure it is not a multicast address
744 * Reject the zero address
746 if (I40E_IS_MULTICAST(mac_addr) ||
747 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
748 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
749 status = I40E_ERR_INVALID_MAC_ADDR;
755 * i40e_get_media_type - Gets media type
756 * @hw: pointer to the hardware structure
758 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
760 enum i40e_media_type media;
762 switch (hw->phy.link_info.phy_type) {
763 case I40E_PHY_TYPE_10GBASE_SR:
764 case I40E_PHY_TYPE_10GBASE_LR:
765 case I40E_PHY_TYPE_1000BASE_SX:
766 case I40E_PHY_TYPE_1000BASE_LX:
767 case I40E_PHY_TYPE_40GBASE_SR4:
768 case I40E_PHY_TYPE_40GBASE_LR4:
769 media = I40E_MEDIA_TYPE_FIBER;
771 case I40E_PHY_TYPE_100BASE_TX:
772 case I40E_PHY_TYPE_1000BASE_T:
773 case I40E_PHY_TYPE_10GBASE_T:
774 media = I40E_MEDIA_TYPE_BASET;
776 case I40E_PHY_TYPE_10GBASE_CR1_CU:
777 case I40E_PHY_TYPE_40GBASE_CR4_CU:
778 case I40E_PHY_TYPE_10GBASE_CR1:
779 case I40E_PHY_TYPE_40GBASE_CR4:
780 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
781 media = I40E_MEDIA_TYPE_DA;
783 case I40E_PHY_TYPE_1000BASE_KX:
784 case I40E_PHY_TYPE_10GBASE_KX4:
785 case I40E_PHY_TYPE_10GBASE_KR:
786 case I40E_PHY_TYPE_40GBASE_KR4:
787 media = I40E_MEDIA_TYPE_BACKPLANE;
789 case I40E_PHY_TYPE_SGMII:
790 case I40E_PHY_TYPE_XAUI:
791 case I40E_PHY_TYPE_XFI:
792 case I40E_PHY_TYPE_XLAUI:
793 case I40E_PHY_TYPE_XLPPI:
795 media = I40E_MEDIA_TYPE_UNKNOWN;
802 #define I40E_PF_RESET_WAIT_COUNT 100
804 * i40e_pf_reset - Reset the PF
805 * @hw: pointer to the hardware structure
807 * Assuming someone else has triggered a global reset,
808 * assure the global reset is complete and then reset the PF
810 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
817 /* Poll for Global Reset steady state in case of recent GRST.
818 * The grst delay value is in 100ms units, and we'll wait a
819 * couple counts longer to be sure we don't just miss the end.
821 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
822 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
823 for (cnt = 0; cnt < grst_del + 2; cnt++) {
824 reg = rd32(hw, I40E_GLGEN_RSTAT);
825 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
827 i40e_msec_delay(100);
829 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
830 DEBUGOUT("Global reset polling failed to complete.\n");
831 return I40E_ERR_RESET_FAILED;
834 /* Now Wait for the FW to be ready */
835 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
836 reg = rd32(hw, I40E_GLNVM_ULD);
837 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
838 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
839 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
840 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
841 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
846 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
847 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
848 DEBUGOUT("wait for FW Reset complete timedout\n");
849 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
850 return I40E_ERR_RESET_FAILED;
853 /* If there was a Global Reset in progress when we got here,
854 * we don't need to do the PF Reset
857 reg = rd32(hw, I40E_PFGEN_CTRL);
858 wr32(hw, I40E_PFGEN_CTRL,
859 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
860 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
861 reg = rd32(hw, I40E_PFGEN_CTRL);
862 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
866 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
867 DEBUGOUT("PF reset polling failed to complete.\n");
868 return I40E_ERR_RESET_FAILED;
872 i40e_clear_pxe_mode(hw);
879 * i40e_clear_hw - clear out any left over hw state
880 * @hw: pointer to the hw struct
882 * Clear queues and interrupts, typically called at init time,
883 * but after the capabilities have been found so we know how many
884 * queues and msix vectors have been allocated.
886 void i40e_clear_hw(struct i40e_hw *hw)
888 u32 num_queues, base_queue;
896 /* get number of interrupts, queues, and vfs */
897 val = rd32(hw, I40E_GLPCI_CNF2);
898 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
899 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
900 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
901 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
903 val = rd32(hw, I40E_PFLAN_QALLOC);
904 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
905 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
906 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
907 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
908 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
909 num_queues = (j - base_queue) + 1;
913 val = rd32(hw, I40E_PF_VT_PFALLOC);
914 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
915 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
916 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
917 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
918 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
919 num_vfs = (j - i) + 1;
923 /* stop all the interrupts */
924 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
925 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
926 for (i = 0; i < num_pf_int - 2; i++)
927 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
929 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
930 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
931 wr32(hw, I40E_PFINT_LNKLST0, val);
932 for (i = 0; i < num_pf_int - 2; i++)
933 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
934 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
935 for (i = 0; i < num_vfs; i++)
936 wr32(hw, I40E_VPINT_LNKLST0(i), val);
937 for (i = 0; i < num_vf_int - 2; i++)
938 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
940 /* warn the HW of the coming Tx disables */
941 for (i = 0; i < num_queues; i++) {
942 u32 abs_queue_idx = base_queue + i;
945 if (abs_queue_idx >= 128) {
946 reg_block = abs_queue_idx / 128;
947 abs_queue_idx %= 128;
950 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
951 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
952 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
953 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
955 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
957 i40e_usec_delay(400);
959 /* stop all the queues */
960 for (i = 0; i < num_queues; i++) {
961 wr32(hw, I40E_QINT_TQCTL(i), 0);
962 wr32(hw, I40E_QTX_ENA(i), 0);
963 wr32(hw, I40E_QINT_RQCTL(i), 0);
964 wr32(hw, I40E_QRX_ENA(i), 0);
967 /* short wait for all queue disables to settle */
972 * i40e_clear_pxe_mode - clear pxe operations mode
973 * @hw: pointer to the hw struct
975 * Make sure all PXE mode settings are cleared, including things
976 * like descriptor fetch/write-back mode.
978 void i40e_clear_pxe_mode(struct i40e_hw *hw)
980 if (i40e_check_asq_alive(hw))
981 i40e_aq_clear_pxe_mode(hw, NULL);
985 * i40e_led_is_mine - helper to find matching led
986 * @hw: pointer to the hw struct
987 * @idx: index into GPIO registers
989 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
991 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
996 if (!hw->func_caps.led[idx])
999 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1000 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1001 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1003 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1004 * if it is not our port then ignore
1006 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1013 #define I40E_LED0 22
1014 #define I40E_LINK_ACTIVITY 0xC
1017 * i40e_led_get - return current on/off mode
1018 * @hw: pointer to the hw struct
1020 * The value returned is the 'mode' field as defined in the
1021 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1022 * values are variations of possible behaviors relating to
1023 * blink, link, and wire.
1025 u32 i40e_led_get(struct i40e_hw *hw)
1030 /* as per the documentation GPIO 22-29 are the LED
1031 * GPIO pins named LED0..LED7
1033 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1034 u32 gpio_val = i40e_led_is_mine(hw, i);
1039 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1040 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1048 * i40e_led_set - set new on/off mode
1049 * @hw: pointer to the hw struct
1050 * @mode: 0=off, 0xf=on (else see manual for mode details)
1051 * @blink: true if the LED should blink when on, false if steady
1053 * if this function is used to turn on the blink it should
1054 * be used to disable the blink when restoring the original state.
1056 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1060 if (mode & 0xfffffff0)
1061 DEBUGOUT1("invalid mode passed in %X\n", mode);
1063 /* as per the documentation GPIO 22-29 are the LED
1064 * GPIO pins named LED0..LED7
1066 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1067 u32 gpio_val = i40e_led_is_mine(hw, i);
1072 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1073 /* this & is a bit of paranoia, but serves as a range check */
1074 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1075 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1077 if (mode == I40E_LINK_ACTIVITY)
1080 gpio_val |= (blink ? 1 : 0) <<
1081 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1083 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1088 /* Admin command wrappers */
1091 * i40e_aq_get_phy_capabilities
1092 * @hw: pointer to the hw struct
1093 * @abilities: structure for PHY capabilities to be filled
1094 * @qualified_modules: report Qualified Modules
1095 * @report_init: report init capabilities (active are default)
1096 * @cmd_details: pointer to command details structure or NULL
1098 * Returns the various PHY abilities supported on the Port.
1100 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1101 bool qualified_modules, bool report_init,
1102 struct i40e_aq_get_phy_abilities_resp *abilities,
1103 struct i40e_asq_cmd_details *cmd_details)
1105 struct i40e_aq_desc desc;
1106 enum i40e_status_code status;
1107 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1110 return I40E_ERR_PARAM;
1112 i40e_fill_default_direct_cmd_desc(&desc,
1113 i40e_aqc_opc_get_phy_abilities);
1115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1116 if (abilities_size > I40E_AQ_LARGE_BUF)
1117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1119 if (qualified_modules)
1120 desc.params.external.param0 |=
1121 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1124 desc.params.external.param0 |=
1125 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1127 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1130 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1131 status = I40E_ERR_UNKNOWN_PHY;
1137 * i40e_aq_set_phy_config
1138 * @hw: pointer to the hw struct
1139 * @config: structure with PHY configuration to be set
1140 * @cmd_details: pointer to command details structure or NULL
1142 * Set the various PHY configuration parameters
1143 * supported on the Port.One or more of the Set PHY config parameters may be
1144 * ignored in an MFP mode as the PF may not have the privilege to set some
1145 * of the PHY Config parameters. This status will be indicated by the
1148 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1149 struct i40e_aq_set_phy_config *config,
1150 struct i40e_asq_cmd_details *cmd_details)
1152 struct i40e_aq_desc desc;
1153 struct i40e_aq_set_phy_config *cmd =
1154 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1155 enum i40e_status_code status;
1158 return I40E_ERR_PARAM;
1160 i40e_fill_default_direct_cmd_desc(&desc,
1161 i40e_aqc_opc_set_phy_config);
1165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1172 * @hw: pointer to the hw struct
1174 * Set the requested flow control mode using set_phy_config.
1176 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1177 bool atomic_restart)
1179 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1180 struct i40e_aq_get_phy_abilities_resp abilities;
1181 struct i40e_aq_set_phy_config config;
1182 enum i40e_status_code status;
1183 u8 pause_mask = 0x0;
1189 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1190 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1192 case I40E_FC_RX_PAUSE:
1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1195 case I40E_FC_TX_PAUSE:
1196 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1202 /* Get the current phy config */
1203 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1206 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1210 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1211 /* clear the old pause settings */
1212 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1213 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1214 /* set the new abilities */
1215 config.abilities |= pause_mask;
1216 /* If the abilities have changed, then set the new config */
1217 if (config.abilities != abilities.abilities) {
1218 /* Auto restart link so settings take effect */
1220 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1221 /* Copy over all the old settings */
1222 config.phy_type = abilities.phy_type;
1223 config.link_speed = abilities.link_speed;
1224 config.eee_capability = abilities.eee_capability;
1225 config.eeer = abilities.eeer_val;
1226 config.low_power_ctrl = abilities.d3_lpan;
1227 status = i40e_aq_set_phy_config(hw, &config, NULL);
1230 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1232 /* Update the link info */
1233 status = i40e_update_link_info(hw, true);
1235 /* Wait a little bit (on 40G cards it sometimes takes a really
1236 * long time for link to come back from the atomic reset)
1239 i40e_msec_delay(1000);
1240 status = i40e_update_link_info(hw, true);
1243 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1249 * i40e_aq_set_mac_config
1250 * @hw: pointer to the hw struct
1251 * @max_frame_size: Maximum Frame Size to be supported by the port
1252 * @crc_en: Tell HW to append a CRC to outgoing frames
1253 * @pacing: Pacing configurations
1254 * @cmd_details: pointer to command details structure or NULL
1256 * Configure MAC settings for frame size, jumbo frame support and the
1257 * addition of a CRC by the hardware.
1259 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1261 bool crc_en, u16 pacing,
1262 struct i40e_asq_cmd_details *cmd_details)
1264 struct i40e_aq_desc desc;
1265 struct i40e_aq_set_mac_config *cmd =
1266 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1267 enum i40e_status_code status;
1269 if (max_frame_size == 0)
1270 return I40E_ERR_PARAM;
1272 i40e_fill_default_direct_cmd_desc(&desc,
1273 i40e_aqc_opc_set_mac_config);
1275 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1276 cmd->params = ((u8)pacing & 0x0F) << 3;
1278 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1280 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1286 * i40e_aq_clear_pxe_mode
1287 * @hw: pointer to the hw struct
1288 * @cmd_details: pointer to command details structure or NULL
1290 * Tell the firmware that the driver is taking over from PXE
1292 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1293 struct i40e_asq_cmd_details *cmd_details)
1295 enum i40e_status_code status;
1296 struct i40e_aq_desc desc;
1297 struct i40e_aqc_clear_pxe *cmd =
1298 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1300 i40e_fill_default_direct_cmd_desc(&desc,
1301 i40e_aqc_opc_clear_pxe_mode);
1305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1307 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1313 * i40e_aq_set_link_restart_an
1314 * @hw: pointer to the hw struct
1315 * @enable_link: if true: enable link, if false: disable link
1316 * @cmd_details: pointer to command details structure or NULL
1318 * Sets up the link and restarts the Auto-Negotiation over the link.
1320 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1321 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1323 struct i40e_aq_desc desc;
1324 struct i40e_aqc_set_link_restart_an *cmd =
1325 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1326 enum i40e_status_code status;
1328 i40e_fill_default_direct_cmd_desc(&desc,
1329 i40e_aqc_opc_set_link_restart_an);
1331 cmd->command = I40E_AQ_PHY_RESTART_AN;
1333 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1335 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1337 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1343 * i40e_aq_get_link_info
1344 * @hw: pointer to the hw struct
1345 * @enable_lse: enable/disable LinkStatusEvent reporting
1346 * @link: pointer to link status structure - optional
1347 * @cmd_details: pointer to command details structure or NULL
1349 * Returns the link status of the adapter.
1351 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1352 bool enable_lse, struct i40e_link_status *link,
1353 struct i40e_asq_cmd_details *cmd_details)
1355 struct i40e_aq_desc desc;
1356 struct i40e_aqc_get_link_status *resp =
1357 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1358 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1359 enum i40e_status_code status;
1360 bool tx_pause, rx_pause;
1363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1366 command_flags = I40E_AQ_LSE_ENABLE;
1368 command_flags = I40E_AQ_LSE_DISABLE;
1369 resp->command_flags = CPU_TO_LE16(command_flags);
1371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1373 if (status != I40E_SUCCESS)
1374 goto aq_get_link_info_exit;
1376 /* save off old link status information */
1377 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1378 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1380 /* update link status */
1381 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1382 hw->phy.media_type = i40e_get_media_type(hw);
1383 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1384 hw_link_info->link_info = resp->link_info;
1385 hw_link_info->an_info = resp->an_info;
1386 hw_link_info->ext_info = resp->ext_info;
1387 hw_link_info->loopback = resp->loopback;
1388 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1389 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1391 /* update fc info */
1392 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1393 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1394 if (tx_pause & rx_pause)
1395 hw->fc.current_mode = I40E_FC_FULL;
1397 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1399 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1401 hw->fc.current_mode = I40E_FC_NONE;
1403 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1404 hw_link_info->crc_enable = true;
1406 hw_link_info->crc_enable = false;
1408 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1409 hw_link_info->lse_enable = true;
1411 hw_link_info->lse_enable = false;
1413 /* save link status information */
1415 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1416 I40E_NONDMA_TO_NONDMA);
1418 /* flag cleared so helper functions don't call AQ again */
1419 hw->phy.get_link_info = false;
1421 aq_get_link_info_exit:
1426 * i40e_update_link_info
1427 * @hw: pointer to the hw struct
1428 * @enable_lse: enable/disable LinkStatusEvent reporting
1430 * Returns the link status of the adapter
1432 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1435 struct i40e_aq_get_phy_abilities_resp abilities;
1436 enum i40e_status_code status;
1438 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1442 status = i40e_aq_get_phy_capabilities(hw, false, false,
1447 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1448 hw->phy.link_info.an_enabled = true;
1450 hw->phy.link_info.an_enabled = false;
1456 * i40e_aq_set_phy_int_mask
1457 * @hw: pointer to the hw struct
1458 * @mask: interrupt mask to be set
1459 * @cmd_details: pointer to command details structure or NULL
1461 * Set link interrupt mask.
1463 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1465 struct i40e_asq_cmd_details *cmd_details)
1467 struct i40e_aq_desc desc;
1468 struct i40e_aqc_set_phy_int_mask *cmd =
1469 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1470 enum i40e_status_code status;
1472 i40e_fill_default_direct_cmd_desc(&desc,
1473 i40e_aqc_opc_set_phy_int_mask);
1475 cmd->event_mask = CPU_TO_LE16(mask);
1477 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1483 * i40e_aq_get_local_advt_reg
1484 * @hw: pointer to the hw struct
1485 * @advt_reg: local AN advertisement register value
1486 * @cmd_details: pointer to command details structure or NULL
1488 * Get the Local AN advertisement register value.
1490 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1492 struct i40e_asq_cmd_details *cmd_details)
1494 struct i40e_aq_desc desc;
1495 struct i40e_aqc_an_advt_reg *resp =
1496 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1497 enum i40e_status_code status;
1499 i40e_fill_default_direct_cmd_desc(&desc,
1500 i40e_aqc_opc_get_local_advt_reg);
1502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1504 if (status != I40E_SUCCESS)
1505 goto aq_get_local_advt_reg_exit;
1507 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1508 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1510 aq_get_local_advt_reg_exit:
1515 * i40e_aq_set_local_advt_reg
1516 * @hw: pointer to the hw struct
1517 * @advt_reg: local AN advertisement register value
1518 * @cmd_details: pointer to command details structure or NULL
1520 * Get the Local AN advertisement register value.
1522 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1524 struct i40e_asq_cmd_details *cmd_details)
1526 struct i40e_aq_desc desc;
1527 struct i40e_aqc_an_advt_reg *cmd =
1528 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1529 enum i40e_status_code status;
1531 i40e_fill_default_direct_cmd_desc(&desc,
1532 i40e_aqc_opc_get_local_advt_reg);
1534 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1535 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1537 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1543 * i40e_aq_get_partner_advt
1544 * @hw: pointer to the hw struct
1545 * @advt_reg: AN partner advertisement register value
1546 * @cmd_details: pointer to command details structure or NULL
1548 * Get the link partner AN advertisement register value.
1550 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1552 struct i40e_asq_cmd_details *cmd_details)
1554 struct i40e_aq_desc desc;
1555 struct i40e_aqc_an_advt_reg *resp =
1556 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1557 enum i40e_status_code status;
1559 i40e_fill_default_direct_cmd_desc(&desc,
1560 i40e_aqc_opc_get_partner_advt);
1562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1564 if (status != I40E_SUCCESS)
1565 goto aq_get_partner_advt_exit;
1567 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1568 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1570 aq_get_partner_advt_exit:
1575 * i40e_aq_set_lb_modes
1576 * @hw: pointer to the hw struct
1577 * @lb_modes: loopback mode to be set
1578 * @cmd_details: pointer to command details structure or NULL
1580 * Sets loopback modes.
1582 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1584 struct i40e_asq_cmd_details *cmd_details)
1586 struct i40e_aq_desc desc;
1587 struct i40e_aqc_set_lb_mode *cmd =
1588 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1589 enum i40e_status_code status;
1591 i40e_fill_default_direct_cmd_desc(&desc,
1592 i40e_aqc_opc_set_lb_modes);
1594 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1602 * i40e_aq_set_phy_debug
1603 * @hw: pointer to the hw struct
1604 * @cmd_flags: debug command flags
1605 * @cmd_details: pointer to command details structure or NULL
1607 * Reset the external PHY.
1609 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1610 struct i40e_asq_cmd_details *cmd_details)
1612 struct i40e_aq_desc desc;
1613 struct i40e_aqc_set_phy_debug *cmd =
1614 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1615 enum i40e_status_code status;
1617 i40e_fill_default_direct_cmd_desc(&desc,
1618 i40e_aqc_opc_set_phy_debug);
1620 cmd->command_flags = cmd_flags;
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1629 * @hw: pointer to the hw struct
1630 * @vsi_ctx: pointer to a vsi context struct
1631 * @cmd_details: pointer to command details structure or NULL
1633 * Add a VSI context to the hardware.
1635 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1636 struct i40e_vsi_context *vsi_ctx,
1637 struct i40e_asq_cmd_details *cmd_details)
1639 struct i40e_aq_desc desc;
1640 struct i40e_aqc_add_get_update_vsi *cmd =
1641 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1642 struct i40e_aqc_add_get_update_vsi_completion *resp =
1643 (struct i40e_aqc_add_get_update_vsi_completion *)
1645 enum i40e_status_code status;
1647 i40e_fill_default_direct_cmd_desc(&desc,
1648 i40e_aqc_opc_add_vsi);
1650 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1651 cmd->connection_type = vsi_ctx->connection_type;
1652 cmd->vf_id = vsi_ctx->vf_num;
1653 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1655 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1657 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1658 sizeof(vsi_ctx->info), cmd_details);
1660 if (status != I40E_SUCCESS)
1661 goto aq_add_vsi_exit;
1663 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1664 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1665 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1666 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1673 * i40e_aq_set_default_vsi
1674 * @hw: pointer to the hw struct
1676 * @cmd_details: pointer to command details structure or NULL
1678 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1680 struct i40e_asq_cmd_details *cmd_details)
1682 struct i40e_aq_desc desc;
1683 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1684 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1686 enum i40e_status_code status;
1688 i40e_fill_default_direct_cmd_desc(&desc,
1689 i40e_aqc_opc_set_vsi_promiscuous_modes);
1691 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1692 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1693 cmd->seid = CPU_TO_LE16(seid);
1695 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1701 * i40e_aq_set_vsi_unicast_promiscuous
1702 * @hw: pointer to the hw struct
1704 * @set: set unicast promiscuous enable/disable
1705 * @cmd_details: pointer to command details structure or NULL
1707 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1709 struct i40e_asq_cmd_details *cmd_details)
1711 struct i40e_aq_desc desc;
1712 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1713 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1714 enum i40e_status_code status;
1717 i40e_fill_default_direct_cmd_desc(&desc,
1718 i40e_aqc_opc_set_vsi_promiscuous_modes);
1721 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1723 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1725 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1727 cmd->seid = CPU_TO_LE16(seid);
1728 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1734 * i40e_aq_set_vsi_multicast_promiscuous
1735 * @hw: pointer to the hw struct
1737 * @set: set multicast promiscuous enable/disable
1738 * @cmd_details: pointer to command details structure or NULL
1740 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1741 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1743 struct i40e_aq_desc desc;
1744 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1745 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1746 enum i40e_status_code status;
1749 i40e_fill_default_direct_cmd_desc(&desc,
1750 i40e_aqc_opc_set_vsi_promiscuous_modes);
1753 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1755 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1757 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1759 cmd->seid = CPU_TO_LE16(seid);
1760 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1766 * i40e_aq_set_vsi_broadcast
1767 * @hw: pointer to the hw struct
1769 * @set_filter: true to set filter, false to clear filter
1770 * @cmd_details: pointer to command details structure or NULL
1772 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1774 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1775 u16 seid, bool set_filter,
1776 struct i40e_asq_cmd_details *cmd_details)
1778 struct i40e_aq_desc desc;
1779 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1780 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1781 enum i40e_status_code status;
1783 i40e_fill_default_direct_cmd_desc(&desc,
1784 i40e_aqc_opc_set_vsi_promiscuous_modes);
1787 cmd->promiscuous_flags
1788 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1790 cmd->promiscuous_flags
1791 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1793 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1794 cmd->seid = CPU_TO_LE16(seid);
1795 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1801 * i40e_get_vsi_params - get VSI configuration info
1802 * @hw: pointer to the hw struct
1803 * @vsi_ctx: pointer to a vsi context struct
1804 * @cmd_details: pointer to command details structure or NULL
1806 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1807 struct i40e_vsi_context *vsi_ctx,
1808 struct i40e_asq_cmd_details *cmd_details)
1810 struct i40e_aq_desc desc;
1811 struct i40e_aqc_add_get_update_vsi *cmd =
1812 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1813 struct i40e_aqc_add_get_update_vsi_completion *resp =
1814 (struct i40e_aqc_add_get_update_vsi_completion *)
1816 enum i40e_status_code status;
1818 UNREFERENCED_1PARAMETER(cmd_details);
1819 i40e_fill_default_direct_cmd_desc(&desc,
1820 i40e_aqc_opc_get_vsi_parameters);
1822 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1824 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1826 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1827 sizeof(vsi_ctx->info), NULL);
1829 if (status != I40E_SUCCESS)
1830 goto aq_get_vsi_params_exit;
1832 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1833 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1834 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1835 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1837 aq_get_vsi_params_exit:
1842 * i40e_aq_update_vsi_params
1843 * @hw: pointer to the hw struct
1844 * @vsi_ctx: pointer to a vsi context struct
1845 * @cmd_details: pointer to command details structure or NULL
1847 * Update a VSI context.
1849 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1850 struct i40e_vsi_context *vsi_ctx,
1851 struct i40e_asq_cmd_details *cmd_details)
1853 struct i40e_aq_desc desc;
1854 struct i40e_aqc_add_get_update_vsi *cmd =
1855 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1856 enum i40e_status_code status;
1858 i40e_fill_default_direct_cmd_desc(&desc,
1859 i40e_aqc_opc_update_vsi_parameters);
1860 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1862 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1864 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1865 sizeof(vsi_ctx->info), cmd_details);
1871 * i40e_aq_get_switch_config
1872 * @hw: pointer to the hardware structure
1873 * @buf: pointer to the result buffer
1874 * @buf_size: length of input buffer
1875 * @start_seid: seid to start for the report, 0 == beginning
1876 * @cmd_details: pointer to command details structure or NULL
1878 * Fill the buf with switch configuration returned from AdminQ command
1880 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1881 struct i40e_aqc_get_switch_config_resp *buf,
1882 u16 buf_size, u16 *start_seid,
1883 struct i40e_asq_cmd_details *cmd_details)
1885 struct i40e_aq_desc desc;
1886 struct i40e_aqc_switch_seid *scfg =
1887 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1888 enum i40e_status_code status;
1890 i40e_fill_default_direct_cmd_desc(&desc,
1891 i40e_aqc_opc_get_switch_config);
1892 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1893 if (buf_size > I40E_AQ_LARGE_BUF)
1894 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1895 scfg->seid = CPU_TO_LE16(*start_seid);
1897 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1898 *start_seid = LE16_TO_CPU(scfg->seid);
1904 * i40e_aq_get_firmware_version
1905 * @hw: pointer to the hw struct
1906 * @fw_major_version: firmware major version
1907 * @fw_minor_version: firmware minor version
1908 * @api_major_version: major queue version
1909 * @api_minor_version: minor queue version
1910 * @cmd_details: pointer to command details structure or NULL
1912 * Get the firmware version from the admin queue commands
1914 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1915 u16 *fw_major_version, u16 *fw_minor_version,
1916 u16 *api_major_version, u16 *api_minor_version,
1917 struct i40e_asq_cmd_details *cmd_details)
1919 struct i40e_aq_desc desc;
1920 struct i40e_aqc_get_version *resp =
1921 (struct i40e_aqc_get_version *)&desc.params.raw;
1922 enum i40e_status_code status;
1924 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1926 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1928 if (status == I40E_SUCCESS) {
1929 if (fw_major_version != NULL)
1930 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1931 if (fw_minor_version != NULL)
1932 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1933 if (api_major_version != NULL)
1934 *api_major_version = LE16_TO_CPU(resp->api_major);
1935 if (api_minor_version != NULL)
1936 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1938 /* A workaround to fix the API version in SW */
1939 if (api_major_version && api_minor_version &&
1940 fw_major_version && fw_minor_version &&
1941 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1942 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1943 (*fw_major_version > 4)))
1944 *api_minor_version = 2;
1951 * i40e_aq_send_driver_version
1952 * @hw: pointer to the hw struct
1953 * @dv: driver's major, minor version
1954 * @cmd_details: pointer to command details structure or NULL
1956 * Send the driver version to the firmware
1958 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1959 struct i40e_driver_version *dv,
1960 struct i40e_asq_cmd_details *cmd_details)
1962 struct i40e_aq_desc desc;
1963 struct i40e_aqc_driver_version *cmd =
1964 (struct i40e_aqc_driver_version *)&desc.params.raw;
1965 enum i40e_status_code status;
1969 return I40E_ERR_PARAM;
1971 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1973 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI);
1974 cmd->driver_major_ver = dv->major_version;
1975 cmd->driver_minor_ver = dv->minor_version;
1976 cmd->driver_build_ver = dv->build_version;
1977 cmd->driver_subbuild_ver = dv->subbuild_version;
1980 while (len < sizeof(dv->driver_string) &&
1981 (dv->driver_string[len] < 0x80) &&
1982 dv->driver_string[len])
1984 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1991 * i40e_get_link_status - get status of the HW network link
1992 * @hw: pointer to the hw struct
1994 * Returns true if link is up, false if link is down.
1996 * Side effect: LinkStatusEvent reporting becomes enabled
1998 bool i40e_get_link_status(struct i40e_hw *hw)
2000 enum i40e_status_code status = I40E_SUCCESS;
2001 bool link_status = false;
2003 if (hw->phy.get_link_info) {
2004 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2006 if (status != I40E_SUCCESS)
2007 goto i40e_get_link_status_exit;
2010 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2012 i40e_get_link_status_exit:
2017 * i40e_get_link_speed
2018 * @hw: pointer to the hw struct
2020 * Returns the link speed of the adapter.
2022 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2024 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2025 enum i40e_status_code status = I40E_SUCCESS;
2027 if (hw->phy.get_link_info) {
2028 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2030 if (status != I40E_SUCCESS)
2031 goto i40e_link_speed_exit;
2034 speed = hw->phy.link_info.link_speed;
2036 i40e_link_speed_exit:
2041 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2042 * @hw: pointer to the hw struct
2043 * @uplink_seid: the MAC or other gizmo SEID
2044 * @downlink_seid: the VSI SEID
2045 * @enabled_tc: bitmap of TCs to be enabled
2046 * @default_port: true for default port VSI, false for control port
2047 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2048 * @veb_seid: pointer to where to put the resulting VEB SEID
2049 * @cmd_details: pointer to command details structure or NULL
2051 * This asks the FW to add a VEB between the uplink and downlink
2052 * elements. If the uplink SEID is 0, this will be a floating VEB.
2054 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2055 u16 downlink_seid, u8 enabled_tc,
2056 bool default_port, bool enable_l2_filtering,
2058 struct i40e_asq_cmd_details *cmd_details)
2060 struct i40e_aq_desc desc;
2061 struct i40e_aqc_add_veb *cmd =
2062 (struct i40e_aqc_add_veb *)&desc.params.raw;
2063 struct i40e_aqc_add_veb_completion *resp =
2064 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2065 enum i40e_status_code status;
2068 /* SEIDs need to either both be set or both be 0 for floating VEB */
2069 if (!!uplink_seid != !!downlink_seid)
2070 return I40E_ERR_PARAM;
2072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2074 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2075 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2076 cmd->enable_tcs = enabled_tc;
2078 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2080 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2082 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2084 if (enable_l2_filtering)
2085 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2087 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091 if (!status && veb_seid)
2092 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2098 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2099 * @hw: pointer to the hw struct
2100 * @veb_seid: the SEID of the VEB to query
2101 * @switch_id: the uplink switch id
2102 * @floating: set to true if the VEB is floating
2103 * @statistic_index: index of the stats counter block for this VEB
2104 * @vebs_used: number of VEB's used by function
2105 * @vebs_free: total VEB's not reserved by any function
2106 * @cmd_details: pointer to command details structure or NULL
2108 * This retrieves the parameters for a particular VEB, specified by
2109 * uplink_seid, and returns them to the caller.
2111 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2112 u16 veb_seid, u16 *switch_id,
2113 bool *floating, u16 *statistic_index,
2114 u16 *vebs_used, u16 *vebs_free,
2115 struct i40e_asq_cmd_details *cmd_details)
2117 struct i40e_aq_desc desc;
2118 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2119 (struct i40e_aqc_get_veb_parameters_completion *)
2121 enum i40e_status_code status;
2124 return I40E_ERR_PARAM;
2126 i40e_fill_default_direct_cmd_desc(&desc,
2127 i40e_aqc_opc_get_veb_parameters);
2128 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2130 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2135 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2136 if (statistic_index)
2137 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2139 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2141 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2143 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2144 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2155 * i40e_aq_add_macvlan
2156 * @hw: pointer to the hw struct
2157 * @seid: VSI for the mac address
2158 * @mv_list: list of macvlans to be added
2159 * @count: length of the list
2160 * @cmd_details: pointer to command details structure or NULL
2162 * Add MAC/VLAN addresses to the HW filtering
2164 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2165 struct i40e_aqc_add_macvlan_element_data *mv_list,
2166 u16 count, struct i40e_asq_cmd_details *cmd_details)
2168 struct i40e_aq_desc desc;
2169 struct i40e_aqc_macvlan *cmd =
2170 (struct i40e_aqc_macvlan *)&desc.params.raw;
2171 enum i40e_status_code status;
2174 if (count == 0 || !mv_list || !hw)
2175 return I40E_ERR_PARAM;
2177 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2179 /* prep the rest of the request */
2180 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2181 cmd->num_addresses = CPU_TO_LE16(count);
2182 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2186 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2187 if (buf_size > I40E_AQ_LARGE_BUF)
2188 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2190 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2197 * i40e_aq_remove_macvlan
2198 * @hw: pointer to the hw struct
2199 * @seid: VSI for the mac address
2200 * @mv_list: list of macvlans to be removed
2201 * @count: length of the list
2202 * @cmd_details: pointer to command details structure or NULL
2204 * Remove MAC/VLAN addresses from the HW filtering
2206 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2207 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2208 u16 count, struct i40e_asq_cmd_details *cmd_details)
2210 struct i40e_aq_desc desc;
2211 struct i40e_aqc_macvlan *cmd =
2212 (struct i40e_aqc_macvlan *)&desc.params.raw;
2213 enum i40e_status_code status;
2216 if (count == 0 || !mv_list || !hw)
2217 return I40E_ERR_PARAM;
2219 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2221 /* prep the rest of the request */
2222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2223 cmd->num_addresses = CPU_TO_LE16(count);
2224 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2228 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2229 if (buf_size > I40E_AQ_LARGE_BUF)
2230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2232 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2239 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2240 * @hw: pointer to the hw struct
2241 * @seid: VSI for the vlan filters
2242 * @v_list: list of vlan filters to be added
2243 * @count: length of the list
2244 * @cmd_details: pointer to command details structure or NULL
2246 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2247 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2248 u8 count, struct i40e_asq_cmd_details *cmd_details)
2250 struct i40e_aq_desc desc;
2251 struct i40e_aqc_macvlan *cmd =
2252 (struct i40e_aqc_macvlan *)&desc.params.raw;
2253 enum i40e_status_code status;
2256 if (count == 0 || !v_list || !hw)
2257 return I40E_ERR_PARAM;
2259 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2261 /* prep the rest of the request */
2262 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2263 cmd->num_addresses = CPU_TO_LE16(count);
2264 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2268 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2269 if (buf_size > I40E_AQ_LARGE_BUF)
2270 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2272 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2279 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2280 * @hw: pointer to the hw struct
2281 * @seid: VSI for the vlan filters
2282 * @v_list: list of macvlans to be removed
2283 * @count: length of the list
2284 * @cmd_details: pointer to command details structure or NULL
2286 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2287 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2288 u8 count, struct i40e_asq_cmd_details *cmd_details)
2290 struct i40e_aq_desc desc;
2291 struct i40e_aqc_macvlan *cmd =
2292 (struct i40e_aqc_macvlan *)&desc.params.raw;
2293 enum i40e_status_code status;
2296 if (count == 0 || !v_list || !hw)
2297 return I40E_ERR_PARAM;
2299 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2301 /* prep the rest of the request */
2302 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2303 cmd->num_addresses = CPU_TO_LE16(count);
2304 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2308 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2309 if (buf_size > I40E_AQ_LARGE_BUF)
2310 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2312 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2319 * i40e_aq_send_msg_to_vf
2320 * @hw: pointer to the hardware structure
2321 * @vfid: vf id to send msg
2322 * @v_opcode: opcodes for VF-PF communication
2323 * @v_retval: return error code
2324 * @msg: pointer to the msg buffer
2325 * @msglen: msg length
2326 * @cmd_details: pointer to command details
2330 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2331 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2332 struct i40e_asq_cmd_details *cmd_details)
2334 struct i40e_aq_desc desc;
2335 struct i40e_aqc_pf_vf_message *cmd =
2336 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2337 enum i40e_status_code status;
2339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2340 cmd->id = CPU_TO_LE32(vfid);
2341 desc.cookie_high = CPU_TO_LE32(v_opcode);
2342 desc.cookie_low = CPU_TO_LE32(v_retval);
2343 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2345 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2347 if (msglen > I40E_AQ_LARGE_BUF)
2348 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2349 desc.datalen = CPU_TO_LE16(msglen);
2351 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2357 * i40e_aq_get_hmc_resource_profile
2358 * @hw: pointer to the hw struct
2359 * @profile: type of profile the HMC is to be set as
2360 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2361 * @cmd_details: pointer to command details structure or NULL
2363 * query the HMC profile of the device.
2365 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2366 enum i40e_aq_hmc_profile *profile,
2367 u8 *pe_vf_enabled_count,
2368 struct i40e_asq_cmd_details *cmd_details)
2370 struct i40e_aq_desc desc;
2371 struct i40e_aq_get_set_hmc_resource_profile *resp =
2372 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2373 enum i40e_status_code status;
2375 i40e_fill_default_direct_cmd_desc(&desc,
2376 i40e_aqc_opc_query_hmc_resource_profile);
2377 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2379 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2380 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2381 *pe_vf_enabled_count = resp->pe_vf_enabled &
2382 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2388 * i40e_aq_set_hmc_resource_profile
2389 * @hw: pointer to the hw struct
2390 * @profile: type of profile the HMC is to be set as
2391 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2392 * @cmd_details: pointer to command details structure or NULL
2394 * set the HMC profile of the device.
2396 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2397 enum i40e_aq_hmc_profile profile,
2398 u8 pe_vf_enabled_count,
2399 struct i40e_asq_cmd_details *cmd_details)
2401 struct i40e_aq_desc desc;
2402 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2403 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2404 enum i40e_status_code status;
2406 i40e_fill_default_direct_cmd_desc(&desc,
2407 i40e_aqc_opc_set_hmc_resource_profile);
2409 cmd->pm_profile = (u8)profile;
2410 cmd->pe_vf_enabled = pe_vf_enabled_count;
2412 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2418 * i40e_aq_request_resource
2419 * @hw: pointer to the hw struct
2420 * @resource: resource id
2421 * @access: access type
2422 * @sdp_number: resource number
2423 * @timeout: the maximum time in ms that the driver may hold the resource
2424 * @cmd_details: pointer to command details structure or NULL
2426 * requests common resource using the admin queue commands
2428 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2429 enum i40e_aq_resources_ids resource,
2430 enum i40e_aq_resource_access_type access,
2431 u8 sdp_number, u64 *timeout,
2432 struct i40e_asq_cmd_details *cmd_details)
2434 struct i40e_aq_desc desc;
2435 struct i40e_aqc_request_resource *cmd_resp =
2436 (struct i40e_aqc_request_resource *)&desc.params.raw;
2437 enum i40e_status_code status;
2439 DEBUGFUNC("i40e_aq_request_resource");
2441 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2443 cmd_resp->resource_id = CPU_TO_LE16(resource);
2444 cmd_resp->access_type = CPU_TO_LE16(access);
2445 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2447 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2448 /* The completion specifies the maximum time in ms that the driver
2449 * may hold the resource in the Timeout field.
2450 * If the resource is held by someone else, the command completes with
2451 * busy return value and the timeout field indicates the maximum time
2452 * the current owner of the resource has to free it.
2454 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2455 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2461 * i40e_aq_release_resource
2462 * @hw: pointer to the hw struct
2463 * @resource: resource id
2464 * @sdp_number: resource number
2465 * @cmd_details: pointer to command details structure or NULL
2467 * release common resource using the admin queue commands
2469 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2470 enum i40e_aq_resources_ids resource,
2472 struct i40e_asq_cmd_details *cmd_details)
2474 struct i40e_aq_desc desc;
2475 struct i40e_aqc_request_resource *cmd =
2476 (struct i40e_aqc_request_resource *)&desc.params.raw;
2477 enum i40e_status_code status;
2479 DEBUGFUNC("i40e_aq_release_resource");
2481 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2483 cmd->resource_id = CPU_TO_LE16(resource);
2484 cmd->resource_number = CPU_TO_LE32(sdp_number);
2486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2493 * @hw: pointer to the hw struct
2494 * @module_pointer: module pointer location in words from the NVM beginning
2495 * @offset: byte offset from the module beginning
2496 * @length: length of the section to be read (in bytes from the offset)
2497 * @data: command buffer (size [bytes] = length)
2498 * @last_command: tells if this is the last command in a series
2499 * @cmd_details: pointer to command details structure or NULL
2501 * Read the NVM using the admin queue commands
2503 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2504 u32 offset, u16 length, void *data,
2506 struct i40e_asq_cmd_details *cmd_details)
2508 struct i40e_aq_desc desc;
2509 struct i40e_aqc_nvm_update *cmd =
2510 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2511 enum i40e_status_code status;
2513 DEBUGFUNC("i40e_aq_read_nvm");
2515 /* In offset the highest byte must be zeroed. */
2516 if (offset & 0xFF000000) {
2517 status = I40E_ERR_PARAM;
2518 goto i40e_aq_read_nvm_exit;
2521 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2523 /* If this is the last command in a series, set the proper flag. */
2525 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2526 cmd->module_pointer = module_pointer;
2527 cmd->offset = CPU_TO_LE32(offset);
2528 cmd->length = CPU_TO_LE16(length);
2530 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2531 if (length > I40E_AQ_LARGE_BUF)
2532 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2534 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2536 i40e_aq_read_nvm_exit:
2542 * @hw: pointer to the hw struct
2543 * @module_pointer: module pointer location in words from the NVM beginning
2544 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2545 * @length: length of the section to be erased (expressed in 4 KB)
2546 * @last_command: tells if this is the last command in a series
2547 * @cmd_details: pointer to command details structure or NULL
2549 * Erase the NVM sector using the admin queue commands
2551 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2552 u32 offset, u16 length, bool last_command,
2553 struct i40e_asq_cmd_details *cmd_details)
2555 struct i40e_aq_desc desc;
2556 struct i40e_aqc_nvm_update *cmd =
2557 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2558 enum i40e_status_code status;
2560 DEBUGFUNC("i40e_aq_erase_nvm");
2562 /* In offset the highest byte must be zeroed. */
2563 if (offset & 0xFF000000) {
2564 status = I40E_ERR_PARAM;
2565 goto i40e_aq_erase_nvm_exit;
2568 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2570 /* If this is the last command in a series, set the proper flag. */
2572 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2573 cmd->module_pointer = module_pointer;
2574 cmd->offset = CPU_TO_LE32(offset);
2575 cmd->length = CPU_TO_LE16(length);
2577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2579 i40e_aq_erase_nvm_exit:
2583 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2584 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2585 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2586 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2587 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2588 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2589 #define I40E_DEV_FUNC_CAP_VF 0x13
2590 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2591 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2592 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2593 #define I40E_DEV_FUNC_CAP_VSI 0x17
2594 #define I40E_DEV_FUNC_CAP_DCB 0x18
2595 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2596 #define I40E_DEV_FUNC_CAP_RSS 0x40
2597 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2598 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2599 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2600 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2601 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2602 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2603 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2604 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2605 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2606 #define I40E_DEV_FUNC_CAP_LED 0x61
2607 #define I40E_DEV_FUNC_CAP_SDP 0x62
2608 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2611 * i40e_parse_discover_capabilities
2612 * @hw: pointer to the hw struct
2613 * @buff: pointer to a buffer containing device/function capability records
2614 * @cap_count: number of capability records in the list
2615 * @list_type_opc: type of capabilities list to parse
2617 * Parse the device/function capabilities list.
2619 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2621 enum i40e_admin_queue_opc list_type_opc)
2623 struct i40e_aqc_list_capabilities_element_resp *cap;
2624 u32 number, logical_id, phys_id;
2625 struct i40e_hw_capabilities *p;
2629 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2631 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2632 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2633 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2634 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2638 for (i = 0; i < cap_count; i++, cap++) {
2639 id = LE16_TO_CPU(cap->id);
2640 number = LE32_TO_CPU(cap->number);
2641 logical_id = LE32_TO_CPU(cap->logical_id);
2642 phys_id = LE32_TO_CPU(cap->phys_id);
2645 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2646 p->switch_mode = number;
2648 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2649 p->management_mode = number;
2651 case I40E_DEV_FUNC_CAP_NPAR:
2652 p->npar_enable = number;
2654 case I40E_DEV_FUNC_CAP_OS2BMC:
2657 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2658 p->valid_functions = number;
2660 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2662 p->sr_iov_1_1 = true;
2664 case I40E_DEV_FUNC_CAP_VF:
2665 p->num_vfs = number;
2666 p->vf_base_id = logical_id;
2668 case I40E_DEV_FUNC_CAP_VMDQ:
2672 case I40E_DEV_FUNC_CAP_802_1_QBG:
2674 p->evb_802_1_qbg = true;
2676 case I40E_DEV_FUNC_CAP_802_1_QBH:
2678 p->evb_802_1_qbh = true;
2680 case I40E_DEV_FUNC_CAP_VSI:
2681 p->num_vsis = number;
2683 case I40E_DEV_FUNC_CAP_DCB:
2686 p->enabled_tcmap = logical_id;
2690 case I40E_DEV_FUNC_CAP_FCOE:
2694 case I40E_DEV_FUNC_CAP_RSS:
2696 p->rss_table_size = number;
2697 p->rss_table_entry_width = logical_id;
2699 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2700 p->num_rx_qp = number;
2701 p->base_queue = phys_id;
2703 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2704 p->num_tx_qp = number;
2705 p->base_queue = phys_id;
2707 case I40E_DEV_FUNC_CAP_MSIX:
2708 p->num_msix_vectors = number;
2710 case I40E_DEV_FUNC_CAP_MSIX_VF:
2711 p->num_msix_vectors_vf = number;
2713 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2715 p->mfp_mode_1 = true;
2717 case I40E_DEV_FUNC_CAP_CEM:
2721 case I40E_DEV_FUNC_CAP_IWARP:
2725 case I40E_DEV_FUNC_CAP_LED:
2726 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2727 p->led[phys_id] = true;
2729 case I40E_DEV_FUNC_CAP_SDP:
2730 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2731 p->sdp[phys_id] = true;
2733 case I40E_DEV_FUNC_CAP_MDIO:
2735 p->mdio_port_num = phys_id;
2736 p->mdio_port_mode = logical_id;
2739 case I40E_DEV_FUNC_CAP_IEEE_1588:
2741 p->ieee_1588 = true;
2743 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2745 p->fd_filters_guaranteed = number;
2746 p->fd_filters_best_effort = logical_id;
2753 /* Software override ensuring FCoE is disabled if npar or mfp
2754 * mode because it is not supported in these modes.
2756 if (p->npar_enable || p->mfp_mode_1)
2759 /* additional HW specific goodies that might
2760 * someday be HW version specific
2762 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2766 * i40e_aq_discover_capabilities
2767 * @hw: pointer to the hw struct
2768 * @buff: a virtual buffer to hold the capabilities
2769 * @buff_size: Size of the virtual buffer
2770 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2771 * @list_type_opc: capabilities type to discover - pass in the command opcode
2772 * @cmd_details: pointer to command details structure or NULL
2774 * Get the device capabilities descriptions from the firmware
2776 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2777 void *buff, u16 buff_size, u16 *data_size,
2778 enum i40e_admin_queue_opc list_type_opc,
2779 struct i40e_asq_cmd_details *cmd_details)
2781 struct i40e_aqc_list_capabilites *cmd;
2782 struct i40e_aq_desc desc;
2783 enum i40e_status_code status = I40E_SUCCESS;
2785 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2787 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2788 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2789 status = I40E_ERR_PARAM;
2793 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2795 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2796 if (buff_size > I40E_AQ_LARGE_BUF)
2797 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2799 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2800 *data_size = LE16_TO_CPU(desc.datalen);
2805 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2813 * i40e_aq_update_nvm
2814 * @hw: pointer to the hw struct
2815 * @module_pointer: module pointer location in words from the NVM beginning
2816 * @offset: byte offset from the module beginning
2817 * @length: length of the section to be written (in bytes from the offset)
2818 * @data: command buffer (size [bytes] = length)
2819 * @last_command: tells if this is the last command in a series
2820 * @cmd_details: pointer to command details structure or NULL
2822 * Update the NVM using the admin queue commands
2824 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2825 u32 offset, u16 length, void *data,
2827 struct i40e_asq_cmd_details *cmd_details)
2829 struct i40e_aq_desc desc;
2830 struct i40e_aqc_nvm_update *cmd =
2831 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2832 enum i40e_status_code status;
2834 DEBUGFUNC("i40e_aq_update_nvm");
2836 /* In offset the highest byte must be zeroed. */
2837 if (offset & 0xFF000000) {
2838 status = I40E_ERR_PARAM;
2839 goto i40e_aq_update_nvm_exit;
2842 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2844 /* If this is the last command in a series, set the proper flag. */
2846 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2847 cmd->module_pointer = module_pointer;
2848 cmd->offset = CPU_TO_LE32(offset);
2849 cmd->length = CPU_TO_LE16(length);
2851 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2852 if (length > I40E_AQ_LARGE_BUF)
2853 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2855 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2857 i40e_aq_update_nvm_exit:
2862 * i40e_aq_get_lldp_mib
2863 * @hw: pointer to the hw struct
2864 * @bridge_type: type of bridge requested
2865 * @mib_type: Local, Remote or both Local and Remote MIBs
2866 * @buff: pointer to a user supplied buffer to store the MIB block
2867 * @buff_size: size of the buffer (in bytes)
2868 * @local_len : length of the returned Local LLDP MIB
2869 * @remote_len: length of the returned Remote LLDP MIB
2870 * @cmd_details: pointer to command details structure or NULL
2872 * Requests the complete LLDP MIB (entire packet).
2874 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2875 u8 mib_type, void *buff, u16 buff_size,
2876 u16 *local_len, u16 *remote_len,
2877 struct i40e_asq_cmd_details *cmd_details)
2879 struct i40e_aq_desc desc;
2880 struct i40e_aqc_lldp_get_mib *cmd =
2881 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2882 struct i40e_aqc_lldp_get_mib *resp =
2883 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2884 enum i40e_status_code status;
2886 if (buff_size == 0 || !buff)
2887 return I40E_ERR_PARAM;
2889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2890 /* Indirect Command */
2891 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2893 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2894 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2895 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2897 desc.datalen = CPU_TO_LE16(buff_size);
2899 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2900 if (buff_size > I40E_AQ_LARGE_BUF)
2901 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2903 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2905 if (local_len != NULL)
2906 *local_len = LE16_TO_CPU(resp->local_len);
2907 if (remote_len != NULL)
2908 *remote_len = LE16_TO_CPU(resp->remote_len);
2915 * i40e_aq_cfg_lldp_mib_change_event
2916 * @hw: pointer to the hw struct
2917 * @enable_update: Enable or Disable event posting
2918 * @cmd_details: pointer to command details structure or NULL
2920 * Enable or Disable posting of an event on ARQ when LLDP MIB
2921 * associated with the interface changes
2923 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2925 struct i40e_asq_cmd_details *cmd_details)
2927 struct i40e_aq_desc desc;
2928 struct i40e_aqc_lldp_update_mib *cmd =
2929 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2930 enum i40e_status_code status;
2932 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2935 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2937 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2943 * i40e_aq_add_lldp_tlv
2944 * @hw: pointer to the hw struct
2945 * @bridge_type: type of bridge
2946 * @buff: buffer with TLV to add
2947 * @buff_size: length of the buffer
2948 * @tlv_len: length of the TLV to be added
2949 * @mib_len: length of the LLDP MIB returned in response
2950 * @cmd_details: pointer to command details structure or NULL
2952 * Add the specified TLV to LLDP Local MIB for the given bridge type,
2953 * it is responsibility of the caller to make sure that the TLV is not
2954 * already present in the LLDPDU.
2955 * In return firmware will write the complete LLDP MIB with the newly
2956 * added TLV in the response buffer.
2958 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
2959 void *buff, u16 buff_size, u16 tlv_len,
2961 struct i40e_asq_cmd_details *cmd_details)
2963 struct i40e_aq_desc desc;
2964 struct i40e_aqc_lldp_add_tlv *cmd =
2965 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
2966 enum i40e_status_code status;
2968 if (buff_size == 0 || !buff || tlv_len == 0)
2969 return I40E_ERR_PARAM;
2971 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
2973 /* Indirect Command */
2974 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2975 if (buff_size > I40E_AQ_LARGE_BUF)
2976 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2977 desc.datalen = CPU_TO_LE16(buff_size);
2979 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2980 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2981 cmd->len = CPU_TO_LE16(tlv_len);
2983 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2985 if (mib_len != NULL)
2986 *mib_len = LE16_TO_CPU(desc.datalen);
2993 * i40e_aq_update_lldp_tlv
2994 * @hw: pointer to the hw struct
2995 * @bridge_type: type of bridge
2996 * @buff: buffer with TLV to update
2997 * @buff_size: size of the buffer holding original and updated TLVs
2998 * @old_len: Length of the Original TLV
2999 * @new_len: Length of the Updated TLV
3000 * @offset: offset of the updated TLV in the buff
3001 * @mib_len: length of the returned LLDP MIB
3002 * @cmd_details: pointer to command details structure or NULL
3004 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3005 * Firmware will place the complete LLDP MIB in response buffer with the
3008 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3009 u8 bridge_type, void *buff, u16 buff_size,
3010 u16 old_len, u16 new_len, u16 offset,
3012 struct i40e_asq_cmd_details *cmd_details)
3014 struct i40e_aq_desc desc;
3015 struct i40e_aqc_lldp_update_tlv *cmd =
3016 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3017 enum i40e_status_code status;
3019 if (buff_size == 0 || !buff || offset == 0 ||
3020 old_len == 0 || new_len == 0)
3021 return I40E_ERR_PARAM;
3023 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3025 /* Indirect Command */
3026 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3027 if (buff_size > I40E_AQ_LARGE_BUF)
3028 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3029 desc.datalen = CPU_TO_LE16(buff_size);
3031 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3032 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3033 cmd->old_len = CPU_TO_LE16(old_len);
3034 cmd->new_offset = CPU_TO_LE16(offset);
3035 cmd->new_len = CPU_TO_LE16(new_len);
3037 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3039 if (mib_len != NULL)
3040 *mib_len = LE16_TO_CPU(desc.datalen);
3047 * i40e_aq_delete_lldp_tlv
3048 * @hw: pointer to the hw struct
3049 * @bridge_type: type of bridge
3050 * @buff: pointer to a user supplied buffer that has the TLV
3051 * @buff_size: length of the buffer
3052 * @tlv_len: length of the TLV to be deleted
3053 * @mib_len: length of the returned LLDP MIB
3054 * @cmd_details: pointer to command details structure or NULL
3056 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3057 * The firmware places the entire LLDP MIB in the response buffer.
3059 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3060 u8 bridge_type, void *buff, u16 buff_size,
3061 u16 tlv_len, u16 *mib_len,
3062 struct i40e_asq_cmd_details *cmd_details)
3064 struct i40e_aq_desc desc;
3065 struct i40e_aqc_lldp_add_tlv *cmd =
3066 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3067 enum i40e_status_code status;
3069 if (buff_size == 0 || !buff)
3070 return I40E_ERR_PARAM;
3072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3074 /* Indirect Command */
3075 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3076 if (buff_size > I40E_AQ_LARGE_BUF)
3077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3078 desc.datalen = CPU_TO_LE16(buff_size);
3079 cmd->len = CPU_TO_LE16(tlv_len);
3080 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3081 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3083 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3085 if (mib_len != NULL)
3086 *mib_len = LE16_TO_CPU(desc.datalen);
3094 * @hw: pointer to the hw struct
3095 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3096 * @cmd_details: pointer to command details structure or NULL
3098 * Stop or Shutdown the embedded LLDP Agent
3100 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3101 struct i40e_asq_cmd_details *cmd_details)
3103 struct i40e_aq_desc desc;
3104 struct i40e_aqc_lldp_stop *cmd =
3105 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3106 enum i40e_status_code status;
3108 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3111 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3119 * i40e_aq_start_lldp
3120 * @hw: pointer to the hw struct
3121 * @cmd_details: pointer to command details structure or NULL
3123 * Start the embedded LLDP Agent on all ports.
3125 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3126 struct i40e_asq_cmd_details *cmd_details)
3128 struct i40e_aq_desc desc;
3129 struct i40e_aqc_lldp_start *cmd =
3130 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3131 enum i40e_status_code status;
3133 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3135 cmd->command = I40E_AQ_LLDP_AGENT_START;
3137 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3143 * i40e_aq_add_udp_tunnel
3144 * @hw: pointer to the hw struct
3145 * @udp_port: the UDP port to add
3146 * @header_len: length of the tunneling header length in DWords
3147 * @protocol_index: protocol index type
3148 * @filter_index: pointer to filter index
3149 * @cmd_details: pointer to command details structure or NULL
3151 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3152 u16 udp_port, u8 protocol_index,
3154 struct i40e_asq_cmd_details *cmd_details)
3156 struct i40e_aq_desc desc;
3157 struct i40e_aqc_add_udp_tunnel *cmd =
3158 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3159 struct i40e_aqc_del_udp_tunnel_completion *resp =
3160 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3161 enum i40e_status_code status;
3163 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3165 cmd->udp_port = CPU_TO_LE16(udp_port);
3166 cmd->protocol_type = protocol_index;
3168 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3171 *filter_index = resp->index;
3177 * i40e_aq_del_udp_tunnel
3178 * @hw: pointer to the hw struct
3179 * @index: filter index
3180 * @cmd_details: pointer to command details structure or NULL
3182 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3183 struct i40e_asq_cmd_details *cmd_details)
3185 struct i40e_aq_desc desc;
3186 struct i40e_aqc_remove_udp_tunnel *cmd =
3187 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3188 enum i40e_status_code status;
3190 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3194 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3200 * i40e_aq_get_switch_resource_alloc (0x0204)
3201 * @hw: pointer to the hw struct
3202 * @num_entries: pointer to u8 to store the number of resource entries returned
3203 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3204 * to store the resource information for all resource types. Each
3205 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3206 * @count: size, in bytes, of the buffer provided
3207 * @cmd_details: pointer to command details structure or NULL
3209 * Query the resources allocated to a function.
3211 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3213 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3215 struct i40e_asq_cmd_details *cmd_details)
3217 struct i40e_aq_desc desc;
3218 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3219 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3220 enum i40e_status_code status;
3222 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3224 i40e_fill_default_direct_cmd_desc(&desc,
3225 i40e_aqc_opc_get_switch_resource_alloc);
3227 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3228 if (length > I40E_AQ_LARGE_BUF)
3229 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3231 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3234 *num_entries = cmd_resp->num_entries;
3240 * i40e_aq_delete_element - Delete switch element
3241 * @hw: pointer to the hw struct
3242 * @seid: the SEID to delete from the switch
3243 * @cmd_details: pointer to command details structure or NULL
3245 * This deletes a switch element from the switch.
3247 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3248 struct i40e_asq_cmd_details *cmd_details)
3250 struct i40e_aq_desc desc;
3251 struct i40e_aqc_switch_seid *cmd =
3252 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3253 enum i40e_status_code status;
3256 return I40E_ERR_PARAM;
3258 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3260 cmd->seid = CPU_TO_LE16(seid);
3262 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3268 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3269 * @hw: pointer to the hw struct
3270 * @flags: component flags
3271 * @mac_seid: uplink seid (MAC SEID)
3272 * @vsi_seid: connected vsi seid
3273 * @ret_seid: seid of create pv component
3275 * This instantiates an i40e port virtualizer with specified flags.
3276 * Depending on specified flags the port virtualizer can act as a
3277 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3279 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3280 u16 mac_seid, u16 vsi_seid,
3283 struct i40e_aq_desc desc;
3284 struct i40e_aqc_add_update_pv *cmd =
3285 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3286 struct i40e_aqc_add_update_pv_completion *resp =
3287 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3288 enum i40e_status_code status;
3291 return I40E_ERR_PARAM;
3293 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3294 cmd->command_flags = CPU_TO_LE16(flags);
3295 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3296 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3298 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3299 if (!status && ret_seid)
3300 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3306 * i40e_aq_add_tag - Add an S/E-tag
3307 * @hw: pointer to the hw struct
3308 * @direct_to_queue: should s-tag direct flow to a specific queue
3309 * @vsi_seid: VSI SEID to use this tag
3310 * @tag: value of the tag
3311 * @queue_num: queue number, only valid is direct_to_queue is true
3312 * @tags_used: return value, number of tags in use by this PF
3313 * @tags_free: return value, number of unallocated tags
3314 * @cmd_details: pointer to command details structure or NULL
3316 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3317 * the number of tags allocated by the PF, and the number of unallocated
3320 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3321 u16 vsi_seid, u16 tag, u16 queue_num,
3322 u16 *tags_used, u16 *tags_free,
3323 struct i40e_asq_cmd_details *cmd_details)
3325 struct i40e_aq_desc desc;
3326 struct i40e_aqc_add_tag *cmd =
3327 (struct i40e_aqc_add_tag *)&desc.params.raw;
3328 struct i40e_aqc_add_remove_tag_completion *resp =
3329 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3330 enum i40e_status_code status;
3333 return I40E_ERR_PARAM;
3335 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3337 cmd->seid = CPU_TO_LE16(vsi_seid);
3338 cmd->tag = CPU_TO_LE16(tag);
3339 if (direct_to_queue) {
3340 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3341 cmd->queue_number = CPU_TO_LE16(queue_num);
3344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3347 if (tags_used != NULL)
3348 *tags_used = LE16_TO_CPU(resp->tags_used);
3349 if (tags_free != NULL)
3350 *tags_free = LE16_TO_CPU(resp->tags_free);
3357 * i40e_aq_remove_tag - Remove an S- or E-tag
3358 * @hw: pointer to the hw struct
3359 * @vsi_seid: VSI SEID this tag is associated with
3360 * @tag: value of the S-tag to delete
3361 * @tags_used: return value, number of tags in use by this PF
3362 * @tags_free: return value, number of unallocated tags
3363 * @cmd_details: pointer to command details structure or NULL
3365 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3366 * the number of tags allocated by the PF, and the number of unallocated
3369 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3370 u16 tag, u16 *tags_used, u16 *tags_free,
3371 struct i40e_asq_cmd_details *cmd_details)
3373 struct i40e_aq_desc desc;
3374 struct i40e_aqc_remove_tag *cmd =
3375 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3376 struct i40e_aqc_add_remove_tag_completion *resp =
3377 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3378 enum i40e_status_code status;
3381 return I40E_ERR_PARAM;
3383 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3385 cmd->seid = CPU_TO_LE16(vsi_seid);
3386 cmd->tag = CPU_TO_LE16(tag);
3388 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3391 if (tags_used != NULL)
3392 *tags_used = LE16_TO_CPU(resp->tags_used);
3393 if (tags_free != NULL)
3394 *tags_free = LE16_TO_CPU(resp->tags_free);
3401 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3402 * @hw: pointer to the hw struct
3403 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3404 * @etag: value of E-tag to add
3405 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3406 * @buf: address of indirect buffer
3407 * @tags_used: return value, number of E-tags in use by this port
3408 * @tags_free: return value, number of unallocated M-tags
3409 * @cmd_details: pointer to command details structure or NULL
3411 * This associates a multicast E-tag to a port virtualizer. It will return
3412 * the number of tags allocated by the PF, and the number of unallocated
3415 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3416 * num_tags_in_buf long.
3418 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3419 u16 etag, u8 num_tags_in_buf, void *buf,
3420 u16 *tags_used, u16 *tags_free,
3421 struct i40e_asq_cmd_details *cmd_details)
3423 struct i40e_aq_desc desc;
3424 struct i40e_aqc_add_remove_mcast_etag *cmd =
3425 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3426 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3427 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3428 enum i40e_status_code status;
3429 u16 length = sizeof(u16) * num_tags_in_buf;
3431 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3432 return I40E_ERR_PARAM;
3434 i40e_fill_default_direct_cmd_desc(&desc,
3435 i40e_aqc_opc_add_multicast_etag);
3437 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3438 cmd->etag = CPU_TO_LE16(etag);
3439 cmd->num_unicast_etags = num_tags_in_buf;
3441 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3442 if (length > I40E_AQ_LARGE_BUF)
3443 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3445 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3448 if (tags_used != NULL)
3449 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3450 if (tags_free != NULL)
3451 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3458 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3459 * @hw: pointer to the hw struct
3460 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3461 * @etag: value of the E-tag to remove
3462 * @tags_used: return value, number of tags in use by this port
3463 * @tags_free: return value, number of unallocated tags
3464 * @cmd_details: pointer to command details structure or NULL
3466 * This deletes an E-tag from the port virtualizer. It will return
3467 * the number of tags allocated by the port, and the number of unallocated
3470 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3471 u16 etag, u16 *tags_used, u16 *tags_free,
3472 struct i40e_asq_cmd_details *cmd_details)
3474 struct i40e_aq_desc desc;
3475 struct i40e_aqc_add_remove_mcast_etag *cmd =
3476 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3477 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3478 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3479 enum i40e_status_code status;
3483 return I40E_ERR_PARAM;
3485 i40e_fill_default_direct_cmd_desc(&desc,
3486 i40e_aqc_opc_remove_multicast_etag);
3488 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3489 cmd->etag = CPU_TO_LE16(etag);
3491 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3494 if (tags_used != NULL)
3495 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3496 if (tags_free != NULL)
3497 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3504 * i40e_aq_update_tag - Update an S/E-tag
3505 * @hw: pointer to the hw struct
3506 * @vsi_seid: VSI SEID using this S-tag
3507 * @old_tag: old tag value
3508 * @new_tag: new tag value
3509 * @tags_used: return value, number of tags in use by this PF
3510 * @tags_free: return value, number of unallocated tags
3511 * @cmd_details: pointer to command details structure or NULL
3513 * This updates the value of the tag currently attached to this VSI
3514 * in the switch complex. It will return the number of tags allocated
3515 * by the PF, and the number of unallocated tags available.
3517 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3518 u16 old_tag, u16 new_tag, u16 *tags_used,
3520 struct i40e_asq_cmd_details *cmd_details)
3522 struct i40e_aq_desc desc;
3523 struct i40e_aqc_update_tag *cmd =
3524 (struct i40e_aqc_update_tag *)&desc.params.raw;
3525 struct i40e_aqc_update_tag_completion *resp =
3526 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3527 enum i40e_status_code status;
3530 return I40E_ERR_PARAM;
3532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3534 cmd->seid = CPU_TO_LE16(vsi_seid);
3535 cmd->old_tag = CPU_TO_LE16(old_tag);
3536 cmd->new_tag = CPU_TO_LE16(new_tag);
3538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3541 if (tags_used != NULL)
3542 *tags_used = LE16_TO_CPU(resp->tags_used);
3543 if (tags_free != NULL)
3544 *tags_free = LE16_TO_CPU(resp->tags_free);
3551 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3552 * @hw: pointer to the hw struct
3553 * @tcmap: TC map for request/release any ignore PFC condition
3554 * @request: request or release ignore PFC condition
3555 * @tcmap_ret: return TCs for which PFC is currently ignored
3556 * @cmd_details: pointer to command details structure or NULL
3558 * This sends out request/release to ignore PFC condition for a TC.
3559 * It will return the TCs for which PFC is currently ignored.
3561 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3562 bool request, u8 *tcmap_ret,
3563 struct i40e_asq_cmd_details *cmd_details)
3565 struct i40e_aq_desc desc;
3566 struct i40e_aqc_pfc_ignore *cmd_resp =
3567 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3568 enum i40e_status_code status;
3570 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3573 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3575 cmd_resp->tc_bitmap = tcmap;
3577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3580 if (tcmap_ret != NULL)
3581 *tcmap_ret = cmd_resp->tc_bitmap;
3588 * i40e_aq_dcb_updated - DCB Updated Command
3589 * @hw: pointer to the hw struct
3590 * @cmd_details: pointer to command details structure or NULL
3592 * When LLDP is handled in PF this command is used by the PF
3593 * to notify EMP that a DCB setting is modified.
3594 * When LLDP is handled in EMP this command is used by the PF
3595 * to notify EMP whenever one of the following parameters get
3597 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3598 * - PCIRTT in PRTDCB_GENC.PCIRTT
3599 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3600 * EMP will return when the shared RPB settings have been
3601 * recomputed and modified. The retval field in the descriptor
3602 * will be set to 0 when RPB is modified.
3604 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3605 struct i40e_asq_cmd_details *cmd_details)
3607 struct i40e_aq_desc desc;
3608 enum i40e_status_code status;
3610 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3612 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3618 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3619 * @hw: pointer to the hw struct
3620 * @seid: defines the SEID of the switch for which the stats are requested
3621 * @vlan_id: the VLAN ID for which the statistics are requested
3622 * @stat_index: index of the statistics counters block assigned to this VLAN
3623 * @cmd_details: pointer to command details structure or NULL
3625 * XL710 supports 128 smonVlanStats counters.This command is used to
3626 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3629 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3630 u16 vlan_id, u16 *stat_index,
3631 struct i40e_asq_cmd_details *cmd_details)
3633 struct i40e_aq_desc desc;
3634 struct i40e_aqc_add_remove_statistics *cmd_resp =
3635 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3636 enum i40e_status_code status;
3638 if ((seid == 0) || (stat_index == NULL))
3639 return I40E_ERR_PARAM;
3641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3643 cmd_resp->seid = CPU_TO_LE16(seid);
3644 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3649 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3655 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3656 * @hw: pointer to the hw struct
3657 * @seid: defines the SEID of the switch for which the stats are requested
3658 * @vlan_id: the VLAN ID for which the statistics are requested
3659 * @stat_index: index of the statistics counters block assigned to this VLAN
3660 * @cmd_details: pointer to command details structure or NULL
3662 * XL710 supports 128 smonVlanStats counters.This command is used to
3663 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3666 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3667 u16 vlan_id, u16 stat_index,
3668 struct i40e_asq_cmd_details *cmd_details)
3670 struct i40e_aq_desc desc;
3671 struct i40e_aqc_add_remove_statistics *cmd =
3672 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3673 enum i40e_status_code status;
3676 return I40E_ERR_PARAM;
3678 i40e_fill_default_direct_cmd_desc(&desc,
3679 i40e_aqc_opc_remove_statistics);
3681 cmd->seid = CPU_TO_LE16(seid);
3682 cmd->vlan = CPU_TO_LE16(vlan_id);
3683 cmd->stat_index = CPU_TO_LE16(stat_index);
3685 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3691 * i40e_aq_set_port_parameters - set physical port parameters.
3692 * @hw: pointer to the hw struct
3693 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3694 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3695 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3696 * @double_vlan: if set double VLAN is enabled
3697 * @cmd_details: pointer to command details structure or NULL
3699 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3700 u16 bad_frame_vsi, bool save_bad_pac,
3701 bool pad_short_pac, bool double_vlan,
3702 struct i40e_asq_cmd_details *cmd_details)
3704 struct i40e_aqc_set_port_parameters *cmd;
3705 enum i40e_status_code status;
3706 struct i40e_aq_desc desc;
3707 u16 command_flags = 0;
3709 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3711 i40e_fill_default_direct_cmd_desc(&desc,
3712 i40e_aqc_opc_set_port_parameters);
3714 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3716 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3718 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3720 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3721 cmd->command_flags = CPU_TO_LE16(command_flags);
3723 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3729 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3730 * @hw: pointer to the hw struct
3731 * @seid: seid for the physical port/switching component/vsi
3732 * @buff: Indirect buffer to hold data parameters and response
3733 * @buff_size: Indirect buffer size
3734 * @opcode: Tx scheduler AQ command opcode
3735 * @cmd_details: pointer to command details structure or NULL
3737 * Generic command handler for Tx scheduler AQ commands
3739 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3740 void *buff, u16 buff_size,
3741 enum i40e_admin_queue_opc opcode,
3742 struct i40e_asq_cmd_details *cmd_details)
3744 struct i40e_aq_desc desc;
3745 struct i40e_aqc_tx_sched_ind *cmd =
3746 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3747 enum i40e_status_code status;
3748 bool cmd_param_flag = false;
3751 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3752 case i40e_aqc_opc_configure_vsi_tc_bw:
3753 case i40e_aqc_opc_enable_switching_comp_ets:
3754 case i40e_aqc_opc_modify_switching_comp_ets:
3755 case i40e_aqc_opc_disable_switching_comp_ets:
3756 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3757 case i40e_aqc_opc_configure_switching_comp_bw_config:
3758 cmd_param_flag = true;
3760 case i40e_aqc_opc_query_vsi_bw_config:
3761 case i40e_aqc_opc_query_vsi_ets_sla_config:
3762 case i40e_aqc_opc_query_switching_comp_ets_config:
3763 case i40e_aqc_opc_query_port_ets_config:
3764 case i40e_aqc_opc_query_switching_comp_bw_config:
3765 cmd_param_flag = false;
3768 return I40E_ERR_PARAM;
3771 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3773 /* Indirect command */
3774 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3777 if (buff_size > I40E_AQ_LARGE_BUF)
3778 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3780 desc.datalen = CPU_TO_LE16(buff_size);
3782 cmd->vsi_seid = CPU_TO_LE16(seid);
3784 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3790 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3791 * @hw: pointer to the hw struct
3793 * @credit: BW limit credits (0 = disabled)
3794 * @max_credit: Max BW limit credits
3795 * @cmd_details: pointer to command details structure or NULL
3797 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3798 u16 seid, u16 credit, u8 max_credit,
3799 struct i40e_asq_cmd_details *cmd_details)
3801 struct i40e_aq_desc desc;
3802 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3803 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3804 enum i40e_status_code status;
3806 i40e_fill_default_direct_cmd_desc(&desc,
3807 i40e_aqc_opc_configure_vsi_bw_limit);
3809 cmd->vsi_seid = CPU_TO_LE16(seid);
3810 cmd->credit = CPU_TO_LE16(credit);
3811 cmd->max_credit = max_credit;
3813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3819 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3820 * @hw: pointer to the hw struct
3821 * @seid: switching component seid
3822 * @credit: BW limit credits (0 = disabled)
3823 * @max_bw: Max BW limit credits
3824 * @cmd_details: pointer to command details structure or NULL
3826 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3827 u16 seid, u16 credit, u8 max_bw,
3828 struct i40e_asq_cmd_details *cmd_details)
3830 struct i40e_aq_desc desc;
3831 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3832 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3833 enum i40e_status_code status;
3835 i40e_fill_default_direct_cmd_desc(&desc,
3836 i40e_aqc_opc_configure_switching_comp_bw_limit);
3838 cmd->seid = CPU_TO_LE16(seid);
3839 cmd->credit = CPU_TO_LE16(credit);
3840 cmd->max_bw = max_bw;
3842 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3848 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3849 * @hw: pointer to the hw struct
3851 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3852 * @cmd_details: pointer to command details structure or NULL
3854 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3856 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3857 struct i40e_asq_cmd_details *cmd_details)
3859 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3860 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3865 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3866 * @hw: pointer to the hw struct
3868 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3869 * @cmd_details: pointer to command details structure or NULL
3871 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3873 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3874 struct i40e_asq_cmd_details *cmd_details)
3876 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3877 i40e_aqc_opc_configure_vsi_tc_bw,
3882 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
3883 * @hw: pointer to the hw struct
3884 * @seid: seid of the switching component
3885 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3886 * @cmd_details: pointer to command details structure or NULL
3888 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
3889 struct i40e_hw *hw, u16 seid,
3890 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
3891 struct i40e_asq_cmd_details *cmd_details)
3893 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3894 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
3899 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3900 * @hw: pointer to the hw struct
3901 * @seid: seid of the VSI
3902 * @bw_data: Buffer to hold VSI BW configuration
3903 * @cmd_details: pointer to command details structure or NULL
3905 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3907 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3908 struct i40e_asq_cmd_details *cmd_details)
3910 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3911 i40e_aqc_opc_query_vsi_bw_config,
3916 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3917 * @hw: pointer to the hw struct
3918 * @seid: seid of the VSI
3919 * @bw_data: Buffer to hold VSI BW configuration per TC
3920 * @cmd_details: pointer to command details structure or NULL
3922 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3924 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3925 struct i40e_asq_cmd_details *cmd_details)
3927 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3928 i40e_aqc_opc_query_vsi_ets_sla_config,
3933 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3934 * @hw: pointer to the hw struct
3935 * @seid: seid of the switching component
3936 * @bw_data: Buffer to hold switching component's per TC BW config
3937 * @cmd_details: pointer to command details structure or NULL
3939 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3941 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3942 struct i40e_asq_cmd_details *cmd_details)
3944 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3945 i40e_aqc_opc_query_switching_comp_ets_config,
3950 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3951 * @hw: pointer to the hw struct
3952 * @seid: seid of the VSI or switching component connected to Physical Port
3953 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3954 * @cmd_details: pointer to command details structure or NULL
3956 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3958 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3959 struct i40e_asq_cmd_details *cmd_details)
3961 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3962 i40e_aqc_opc_query_port_ets_config,
3967 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3968 * @hw: pointer to the hw struct
3969 * @seid: seid of the switching component
3970 * @bw_data: Buffer to hold switching component's BW configuration
3971 * @cmd_details: pointer to command details structure or NULL
3973 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3975 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3976 struct i40e_asq_cmd_details *cmd_details)
3978 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3979 i40e_aqc_opc_query_switching_comp_bw_config,
3984 * i40e_validate_filter_settings
3985 * @hw: pointer to the hardware structure
3986 * @settings: Filter control settings
3988 * Check and validate the filter control settings passed.
3989 * The function checks for the valid filter/context sizes being
3990 * passed for FCoE and PE.
3992 * Returns I40E_SUCCESS if the values passed are valid and within
3993 * range else returns an error.
3995 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
3996 struct i40e_filter_control_settings *settings)
3998 u32 fcoe_cntx_size, fcoe_filt_size;
3999 u32 pe_cntx_size, pe_filt_size;
4004 /* Validate FCoE settings passed */
4005 switch (settings->fcoe_filt_num) {
4006 case I40E_HASH_FILTER_SIZE_1K:
4007 case I40E_HASH_FILTER_SIZE_2K:
4008 case I40E_HASH_FILTER_SIZE_4K:
4009 case I40E_HASH_FILTER_SIZE_8K:
4010 case I40E_HASH_FILTER_SIZE_16K:
4011 case I40E_HASH_FILTER_SIZE_32K:
4012 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4013 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4016 return I40E_ERR_PARAM;
4019 switch (settings->fcoe_cntx_num) {
4020 case I40E_DMA_CNTX_SIZE_512:
4021 case I40E_DMA_CNTX_SIZE_1K:
4022 case I40E_DMA_CNTX_SIZE_2K:
4023 case I40E_DMA_CNTX_SIZE_4K:
4024 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4025 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4028 return I40E_ERR_PARAM;
4031 /* Validate PE settings passed */
4032 switch (settings->pe_filt_num) {
4033 case I40E_HASH_FILTER_SIZE_1K:
4034 case I40E_HASH_FILTER_SIZE_2K:
4035 case I40E_HASH_FILTER_SIZE_4K:
4036 case I40E_HASH_FILTER_SIZE_8K:
4037 case I40E_HASH_FILTER_SIZE_16K:
4038 case I40E_HASH_FILTER_SIZE_32K:
4039 case I40E_HASH_FILTER_SIZE_64K:
4040 case I40E_HASH_FILTER_SIZE_128K:
4041 case I40E_HASH_FILTER_SIZE_256K:
4042 case I40E_HASH_FILTER_SIZE_512K:
4043 case I40E_HASH_FILTER_SIZE_1M:
4044 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4045 pe_filt_size <<= (u32)settings->pe_filt_num;
4048 return I40E_ERR_PARAM;
4051 switch (settings->pe_cntx_num) {
4052 case I40E_DMA_CNTX_SIZE_512:
4053 case I40E_DMA_CNTX_SIZE_1K:
4054 case I40E_DMA_CNTX_SIZE_2K:
4055 case I40E_DMA_CNTX_SIZE_4K:
4056 case I40E_DMA_CNTX_SIZE_8K:
4057 case I40E_DMA_CNTX_SIZE_16K:
4058 case I40E_DMA_CNTX_SIZE_32K:
4059 case I40E_DMA_CNTX_SIZE_64K:
4060 case I40E_DMA_CNTX_SIZE_128K:
4061 case I40E_DMA_CNTX_SIZE_256K:
4062 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4063 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4066 return I40E_ERR_PARAM;
4069 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4070 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4071 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4072 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4073 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4074 return I40E_ERR_INVALID_SIZE;
4076 return I40E_SUCCESS;
4080 * i40e_set_filter_control
4081 * @hw: pointer to the hardware structure
4082 * @settings: Filter control settings
4084 * Set the Queue Filters for PE/FCoE and enable filters required
4085 * for a single PF. It is expected that these settings are programmed
4086 * at the driver initialization time.
4088 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4089 struct i40e_filter_control_settings *settings)
4091 enum i40e_status_code ret = I40E_SUCCESS;
4092 u32 hash_lut_size = 0;
4096 return I40E_ERR_PARAM;
4098 /* Validate the input settings */
4099 ret = i40e_validate_filter_settings(hw, settings);
4103 /* Read the PF Queue Filter control register */
4104 val = rd32(hw, I40E_PFQF_CTL_0);
4106 /* Program required PE hash buckets for the PF */
4107 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4108 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4109 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4110 /* Program required PE contexts for the PF */
4111 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4112 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4113 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4115 /* Program required FCoE hash buckets for the PF */
4116 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4117 val |= ((u32)settings->fcoe_filt_num <<
4118 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4119 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4120 /* Program required FCoE DDP contexts for the PF */
4121 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4122 val |= ((u32)settings->fcoe_cntx_num <<
4123 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4124 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4126 /* Program Hash LUT size for the PF */
4127 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4128 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4130 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4131 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4133 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4134 if (settings->enable_fdir)
4135 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4136 if (settings->enable_ethtype)
4137 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4138 if (settings->enable_macvlan)
4139 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4141 wr32(hw, I40E_PFQF_CTL_0, val);
4143 return I40E_SUCCESS;
4147 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4148 * @hw: pointer to the hw struct
4149 * @mac_addr: MAC address to use in the filter
4150 * @ethtype: Ethertype to use in the filter
4151 * @flags: Flags that needs to be applied to the filter
4152 * @vsi_seid: seid of the control VSI
4153 * @queue: VSI queue number to send the packet to
4154 * @is_add: Add control packet filter if True else remove
4155 * @stats: Structure to hold information on control filter counts
4156 * @cmd_details: pointer to command details structure or NULL
4158 * This command will Add or Remove control packet filter for a control VSI.
4159 * In return it will update the total number of perfect filter count in
4162 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4163 u8 *mac_addr, u16 ethtype, u16 flags,
4164 u16 vsi_seid, u16 queue, bool is_add,
4165 struct i40e_control_filter_stats *stats,
4166 struct i40e_asq_cmd_details *cmd_details)
4168 struct i40e_aq_desc desc;
4169 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4170 (struct i40e_aqc_add_remove_control_packet_filter *)
4172 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4173 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4175 enum i40e_status_code status;
4178 return I40E_ERR_PARAM;
4181 i40e_fill_default_direct_cmd_desc(&desc,
4182 i40e_aqc_opc_add_control_packet_filter);
4183 cmd->queue = CPU_TO_LE16(queue);
4185 i40e_fill_default_direct_cmd_desc(&desc,
4186 i40e_aqc_opc_remove_control_packet_filter);
4190 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4191 I40E_NONDMA_TO_NONDMA);
4193 cmd->etype = CPU_TO_LE16(ethtype);
4194 cmd->flags = CPU_TO_LE16(flags);
4195 cmd->seid = CPU_TO_LE16(vsi_seid);
4197 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4199 if (!status && stats) {
4200 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4201 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4202 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4203 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4210 * i40e_aq_add_cloud_filters
4211 * @hw: pointer to the hardware structure
4212 * @seid: VSI seid to add cloud filters from
4213 * @filters: Buffer which contains the filters to be added
4214 * @filter_count: number of filters contained in the buffer
4216 * Set the cloud filters for a given VSI. The contents of the
4217 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4218 * in by the caller of the function.
4221 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4223 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4226 struct i40e_aq_desc desc;
4227 struct i40e_aqc_add_remove_cloud_filters *cmd =
4228 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4230 enum i40e_status_code status;
4232 i40e_fill_default_direct_cmd_desc(&desc,
4233 i40e_aqc_opc_add_cloud_filters);
4235 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4237 desc.datalen = CPU_TO_LE16(buff_len);
4238 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4239 cmd->num_filters = filter_count;
4240 cmd->seid = CPU_TO_LE16(seid);
4242 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4248 * i40e_aq_remove_cloud_filters
4249 * @hw: pointer to the hardware structure
4250 * @seid: VSI seid to remove cloud filters from
4251 * @filters: Buffer which contains the filters to be removed
4252 * @filter_count: number of filters contained in the buffer
4254 * Remove the cloud filters for a given VSI. The contents of the
4255 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4256 * in by the caller of the function.
4259 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4261 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4264 struct i40e_aq_desc desc;
4265 struct i40e_aqc_add_remove_cloud_filters *cmd =
4266 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4267 enum i40e_status_code status;
4270 i40e_fill_default_direct_cmd_desc(&desc,
4271 i40e_aqc_opc_remove_cloud_filters);
4273 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4275 desc.datalen = CPU_TO_LE16(buff_len);
4276 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4277 cmd->num_filters = filter_count;
4278 cmd->seid = CPU_TO_LE16(seid);
4280 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4286 * i40e_aq_alternate_write
4287 * @hw: pointer to the hardware structure
4288 * @reg_addr0: address of first dword to be read
4289 * @reg_val0: value to be written under 'reg_addr0'
4290 * @reg_addr1: address of second dword to be read
4291 * @reg_val1: value to be written under 'reg_addr1'
4293 * Write one or two dwords to alternate structure. Fields are indicated
4294 * by 'reg_addr0' and 'reg_addr1' register numbers.
4297 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4298 u32 reg_addr0, u32 reg_val0,
4299 u32 reg_addr1, u32 reg_val1)
4301 struct i40e_aq_desc desc;
4302 struct i40e_aqc_alternate_write *cmd_resp =
4303 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4304 enum i40e_status_code status;
4306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4307 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4308 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4309 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4310 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4312 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4318 * i40e_aq_alternate_write_indirect
4319 * @hw: pointer to the hardware structure
4320 * @addr: address of a first register to be modified
4321 * @dw_count: number of alternate structure fields to write
4322 * @buffer: pointer to the command buffer
4324 * Write 'dw_count' dwords from 'buffer' to alternate structure
4325 * starting at 'addr'.
4328 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4329 u32 addr, u32 dw_count, void *buffer)
4331 struct i40e_aq_desc desc;
4332 struct i40e_aqc_alternate_ind_write *cmd_resp =
4333 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4334 enum i40e_status_code status;
4337 return I40E_ERR_PARAM;
4339 /* Indirect command */
4340 i40e_fill_default_direct_cmd_desc(&desc,
4341 i40e_aqc_opc_alternate_write_indirect);
4343 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4344 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4345 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4346 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4348 cmd_resp->address = CPU_TO_LE32(addr);
4349 cmd_resp->length = CPU_TO_LE32(dw_count);
4350 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4351 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4353 status = i40e_asq_send_command(hw, &desc, buffer,
4354 I40E_LO_DWORD(4*dw_count), NULL);
4360 * i40e_aq_alternate_read
4361 * @hw: pointer to the hardware structure
4362 * @reg_addr0: address of first dword to be read
4363 * @reg_val0: pointer for data read from 'reg_addr0'
4364 * @reg_addr1: address of second dword to be read
4365 * @reg_val1: pointer for data read from 'reg_addr1'
4367 * Read one or two dwords from alternate structure. Fields are indicated
4368 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4369 * is not passed then only register at 'reg_addr0' is read.
4372 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4373 u32 reg_addr0, u32 *reg_val0,
4374 u32 reg_addr1, u32 *reg_val1)
4376 struct i40e_aq_desc desc;
4377 struct i40e_aqc_alternate_write *cmd_resp =
4378 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4379 enum i40e_status_code status;
4381 if (reg_val0 == NULL)
4382 return I40E_ERR_PARAM;
4384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4385 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4386 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4388 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4390 if (status == I40E_SUCCESS) {
4391 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4393 if (reg_val1 != NULL)
4394 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4401 * i40e_aq_alternate_read_indirect
4402 * @hw: pointer to the hardware structure
4403 * @addr: address of the alternate structure field
4404 * @dw_count: number of alternate structure fields to read
4405 * @buffer: pointer to the command buffer
4407 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4408 * place them in 'buffer'. The buffer should be allocated by caller.
4411 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4412 u32 addr, u32 dw_count, void *buffer)
4414 struct i40e_aq_desc desc;
4415 struct i40e_aqc_alternate_ind_write *cmd_resp =
4416 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4417 enum i40e_status_code status;
4420 return I40E_ERR_PARAM;
4422 /* Indirect command */
4423 i40e_fill_default_direct_cmd_desc(&desc,
4424 i40e_aqc_opc_alternate_read_indirect);
4426 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4427 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4428 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4429 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4431 cmd_resp->address = CPU_TO_LE32(addr);
4432 cmd_resp->length = CPU_TO_LE32(dw_count);
4433 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4434 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4436 status = i40e_asq_send_command(hw, &desc, buffer,
4437 I40E_LO_DWORD(4*dw_count), NULL);
4443 * i40e_aq_alternate_clear
4444 * @hw: pointer to the HW structure.
4446 * Clear the alternate structures of the port from which the function
4450 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4452 struct i40e_aq_desc desc;
4453 enum i40e_status_code status;
4455 i40e_fill_default_direct_cmd_desc(&desc,
4456 i40e_aqc_opc_alternate_clear_port);
4458 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4464 * i40e_aq_alternate_write_done
4465 * @hw: pointer to the HW structure.
4466 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4467 * @reset_needed: indicates the SW should trigger GLOBAL reset
4469 * Indicates to the FW that alternate structures have been changed.
4472 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4473 u8 bios_mode, bool *reset_needed)
4475 struct i40e_aq_desc desc;
4476 struct i40e_aqc_alternate_write_done *cmd =
4477 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4478 enum i40e_status_code status;
4480 if (reset_needed == NULL)
4481 return I40E_ERR_PARAM;
4483 i40e_fill_default_direct_cmd_desc(&desc,
4484 i40e_aqc_opc_alternate_write_done);
4486 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4488 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4490 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4491 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4497 * i40e_aq_set_oem_mode
4498 * @hw: pointer to the HW structure.
4499 * @oem_mode: the OEM mode to be used
4501 * Sets the device to a specific operating mode. Currently the only supported
4502 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4505 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4508 struct i40e_aq_desc desc;
4509 struct i40e_aqc_alternate_write_done *cmd =
4510 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4511 enum i40e_status_code status;
4513 i40e_fill_default_direct_cmd_desc(&desc,
4514 i40e_aqc_opc_alternate_set_mode);
4516 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4518 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4524 * i40e_aq_resume_port_tx
4525 * @hw: pointer to the hardware structure
4526 * @cmd_details: pointer to command details structure or NULL
4528 * Resume port's Tx traffic
4530 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4531 struct i40e_asq_cmd_details *cmd_details)
4533 struct i40e_aq_desc desc;
4534 enum i40e_status_code status;
4536 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4544 * i40e_set_pci_config_data - store PCI bus info
4545 * @hw: pointer to hardware structure
4546 * @link_status: the link status word from PCI config space
4548 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4550 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4552 hw->bus.type = i40e_bus_type_pci_express;
4554 switch (link_status & I40E_PCI_LINK_WIDTH) {
4555 case I40E_PCI_LINK_WIDTH_1:
4556 hw->bus.width = i40e_bus_width_pcie_x1;
4558 case I40E_PCI_LINK_WIDTH_2:
4559 hw->bus.width = i40e_bus_width_pcie_x2;
4561 case I40E_PCI_LINK_WIDTH_4:
4562 hw->bus.width = i40e_bus_width_pcie_x4;
4564 case I40E_PCI_LINK_WIDTH_8:
4565 hw->bus.width = i40e_bus_width_pcie_x8;
4568 hw->bus.width = i40e_bus_width_unknown;
4572 switch (link_status & I40E_PCI_LINK_SPEED) {
4573 case I40E_PCI_LINK_SPEED_2500:
4574 hw->bus.speed = i40e_bus_speed_2500;
4576 case I40E_PCI_LINK_SPEED_5000:
4577 hw->bus.speed = i40e_bus_speed_5000;
4579 case I40E_PCI_LINK_SPEED_8000:
4580 hw->bus.speed = i40e_bus_speed_8000;
4583 hw->bus.speed = i40e_bus_speed_unknown;
4589 * i40e_read_bw_from_alt_ram
4590 * @hw: pointer to the hardware structure
4591 * @max_bw: pointer for max_bw read
4592 * @min_bw: pointer for min_bw read
4593 * @min_valid: pointer for bool that is true if min_bw is a valid value
4594 * @max_valid: pointer for bool that is true if max_bw is a valid value
4596 * Read bw from the alternate ram for the given pf
4598 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4599 u32 *max_bw, u32 *min_bw,
4600 bool *min_valid, bool *max_valid)
4602 enum i40e_status_code status;
4603 u32 max_bw_addr, min_bw_addr;
4605 /* Calculate the address of the min/max bw registers */
4606 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4607 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4608 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4609 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4610 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4611 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4613 /* Read the bandwidths from alt ram */
4614 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4615 min_bw_addr, min_bw);
4617 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4622 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4631 * i40e_aq_configure_partition_bw
4632 * @hw: pointer to the hardware structure
4633 * @bw_data: Buffer holding valid pfs and bw limits
4634 * @cmd_details: pointer to command details
4636 * Configure partitions guaranteed/max bw
4638 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4639 struct i40e_aqc_configure_partition_bw_data *bw_data,
4640 struct i40e_asq_cmd_details *cmd_details)
4642 enum i40e_status_code status;
4643 struct i40e_aq_desc desc;
4644 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4646 i40e_fill_default_direct_cmd_desc(&desc,
4647 i40e_aqc_opc_configure_partition_bw);
4649 /* Indirect command */
4650 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4653 if (bwd_size > I40E_AQ_LARGE_BUF)
4654 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4656 desc.datalen = CPU_TO_LE16(bwd_size);
4658 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4664 * i40e_aq_send_msg_to_pf
4665 * @hw: pointer to the hardware structure
4666 * @v_opcode: opcodes for VF-PF communication
4667 * @v_retval: return error code
4668 * @msg: pointer to the msg buffer
4669 * @msglen: msg length
4670 * @cmd_details: pointer to command details
4672 * Send message to PF driver using admin queue. By default, this message
4673 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4674 * completion before returning.
4676 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4677 enum i40e_virtchnl_ops v_opcode,
4678 enum i40e_status_code v_retval,
4679 u8 *msg, u16 msglen,
4680 struct i40e_asq_cmd_details *cmd_details)
4682 struct i40e_aq_desc desc;
4683 struct i40e_asq_cmd_details details;
4684 enum i40e_status_code status;
4686 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4687 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4688 desc.cookie_high = CPU_TO_LE32(v_opcode);
4689 desc.cookie_low = CPU_TO_LE32(v_retval);
4691 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4692 | I40E_AQ_FLAG_RD));
4693 if (msglen > I40E_AQ_LARGE_BUF)
4694 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4695 desc.datalen = CPU_TO_LE16(msglen);
4698 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4699 details.async = true;
4700 cmd_details = &details;
4702 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4703 msglen, cmd_details);
4708 * i40e_vf_parse_hw_config
4709 * @hw: pointer to the hardware structure
4710 * @msg: pointer to the virtual channel VF resource structure
4712 * Given a VF resource message from the PF, populate the hw struct
4713 * with appropriate information.
4715 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4716 struct i40e_virtchnl_vf_resource *msg)
4718 struct i40e_virtchnl_vsi_resource *vsi_res;
4721 vsi_res = &msg->vsi_res[0];
4723 hw->dev_caps.num_vsis = msg->num_vsis;
4724 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4725 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4726 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4727 hw->dev_caps.dcb = msg->vf_offload_flags &
4728 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4729 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4730 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4731 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4732 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4733 for (i = 0; i < msg->num_vsis; i++) {
4734 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4735 i40e_memcpy(hw->mac.perm_addr,
4736 vsi_res->default_mac_addr,
4737 I40E_ETH_LENGTH_OF_ADDRESS,
4738 I40E_NONDMA_TO_NONDMA);
4739 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4740 I40E_ETH_LENGTH_OF_ADDRESS,
4741 I40E_NONDMA_TO_NONDMA);
4749 * @hw: pointer to the hardware structure
4751 * Send a VF_RESET message to the PF. Does not wait for response from PF
4752 * as none will be forthcoming. Immediately after calling this function,
4753 * the admin queue should be shut down and (optionally) reinitialized.
4755 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4757 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4758 I40E_SUCCESS, NULL, 0, NULL);
4760 #endif /* VF_DRIVER */