1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *aq_buffer = (u8 *)buffer;
105 if ((!(mask & hw->debug_mask)) || (desc == NULL))
109 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
110 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
112 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
113 aq_desc->cookie_high, aq_desc->cookie_low);
114 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
115 aq_desc->params.internal.param0,
116 aq_desc->params.internal.param1);
117 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
118 aq_desc->params.external.addr_high,
119 aq_desc->params.external.addr_low);
121 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
122 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
123 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
126 for (i = 0; i < len; i++) {
127 data[((i % 16) / 4)] |=
128 ((u32)aq_buffer[i]) << (8 * (i % 4));
129 if ((i % 16) == 15) {
131 "\t0x%04X %08X %08X %08X %08X\n",
132 i - 15, data[0], data[1], data[2],
134 i40e_memset(data, 0, sizeof(data),
139 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
140 i - (i % 16), data[0], data[1], data[2],
146 * i40e_check_asq_alive
147 * @hw: pointer to the hw struct
149 * Returns true if Queue is enabled else false.
151 bool i40e_check_asq_alive(struct i40e_hw *hw)
154 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
160 * i40e_aq_queue_shutdown
161 * @hw: pointer to the hw struct
162 * @unloading: is the driver unloading itself
164 * Tell the Firmware that we're shutting down the AdminQ and whether
165 * or not the driver is unloading as well.
167 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
170 struct i40e_aq_desc desc;
171 struct i40e_aqc_queue_shutdown *cmd =
172 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
173 enum i40e_status_code status;
175 i40e_fill_default_direct_cmd_desc(&desc,
176 i40e_aqc_opc_queue_shutdown);
179 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
180 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
185 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
186 * hardware to a bit-field that can be used by SW to more easily determine the
189 * Macros are used to shorten the table lines and make this table human
192 * We store the PTYPE in the top byte of the bit field - this is just so that
193 * we can check that the table doesn't have a row missing, as the index into
194 * the table should be the PTYPE.
198 * IF NOT i40e_ptype_lookup[ptype].known
201 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
202 * Use the rest of the fields to look at the tunnels, inner protocols, etc
204 * Use the enum i40e_rx_l2_ptype to decode the packet type
208 /* macro to make the table lines short */
209 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
212 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
213 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
214 I40E_RX_PTYPE_##OUTER_FRAG, \
215 I40E_RX_PTYPE_TUNNEL_##T, \
216 I40E_RX_PTYPE_TUNNEL_END_##TE, \
217 I40E_RX_PTYPE_##TEF, \
218 I40E_RX_PTYPE_INNER_PROT_##I, \
219 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
221 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
222 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
224 /* shorter macros makes the table fit but are terse */
225 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
226 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
227 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
229 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
230 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
231 /* L2 Packet types */
232 I40E_PTT_UNUSED_ENTRY(0),
233 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
235 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
236 I40E_PTT_UNUSED_ENTRY(4),
237 I40E_PTT_UNUSED_ENTRY(5),
238 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
239 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(8),
241 I40E_PTT_UNUSED_ENTRY(9),
242 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
244 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 /* Non Tunneled IPv4 */
256 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
258 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
259 I40E_PTT_UNUSED_ENTRY(25),
260 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
261 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
262 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
265 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
266 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
267 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
268 I40E_PTT_UNUSED_ENTRY(32),
269 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
270 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
271 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
274 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
275 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
276 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
277 I40E_PTT_UNUSED_ENTRY(39),
278 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
279 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
280 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
282 /* IPv4 --> GRE/NAT */
283 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
285 /* IPv4 --> GRE/NAT --> IPv4 */
286 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
287 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
288 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
289 I40E_PTT_UNUSED_ENTRY(47),
290 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
291 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
292 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
294 /* IPv4 --> GRE/NAT --> IPv6 */
295 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
296 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
297 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
298 I40E_PTT_UNUSED_ENTRY(54),
299 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
300 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
301 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
303 /* IPv4 --> GRE/NAT --> MAC */
304 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
306 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
307 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
308 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
309 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
310 I40E_PTT_UNUSED_ENTRY(62),
311 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
312 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
313 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
315 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
316 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
317 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
318 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
319 I40E_PTT_UNUSED_ENTRY(69),
320 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
321 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
322 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
324 /* IPv4 --> GRE/NAT --> MAC/VLAN */
325 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
327 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
328 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
329 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
330 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
331 I40E_PTT_UNUSED_ENTRY(77),
332 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
333 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
334 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
336 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
337 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
338 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
339 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
340 I40E_PTT_UNUSED_ENTRY(84),
341 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
342 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
343 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
345 /* Non Tunneled IPv6 */
346 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
347 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
348 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
349 I40E_PTT_UNUSED_ENTRY(91),
350 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
351 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
352 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
355 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
356 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
357 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
358 I40E_PTT_UNUSED_ENTRY(98),
359 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
360 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
361 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
364 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
365 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
366 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
367 I40E_PTT_UNUSED_ENTRY(105),
368 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
369 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
370 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
372 /* IPv6 --> GRE/NAT */
373 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
375 /* IPv6 --> GRE/NAT -> IPv4 */
376 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
377 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
378 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
379 I40E_PTT_UNUSED_ENTRY(113),
380 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
381 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
382 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
384 /* IPv6 --> GRE/NAT -> IPv6 */
385 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
386 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
387 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
388 I40E_PTT_UNUSED_ENTRY(120),
389 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
390 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
391 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
393 /* IPv6 --> GRE/NAT -> MAC */
394 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
396 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
397 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
398 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
399 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
400 I40E_PTT_UNUSED_ENTRY(128),
401 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
402 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
403 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
405 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
406 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
407 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
408 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
409 I40E_PTT_UNUSED_ENTRY(135),
410 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
411 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
412 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
414 /* IPv6 --> GRE/NAT -> MAC/VLAN */
415 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
417 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
418 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
419 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
420 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
421 I40E_PTT_UNUSED_ENTRY(143),
422 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
423 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
424 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
426 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
427 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
428 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
429 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
430 I40E_PTT_UNUSED_ENTRY(150),
431 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
432 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
433 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
436 I40E_PTT_UNUSED_ENTRY(154),
437 I40E_PTT_UNUSED_ENTRY(155),
438 I40E_PTT_UNUSED_ENTRY(156),
439 I40E_PTT_UNUSED_ENTRY(157),
440 I40E_PTT_UNUSED_ENTRY(158),
441 I40E_PTT_UNUSED_ENTRY(159),
443 I40E_PTT_UNUSED_ENTRY(160),
444 I40E_PTT_UNUSED_ENTRY(161),
445 I40E_PTT_UNUSED_ENTRY(162),
446 I40E_PTT_UNUSED_ENTRY(163),
447 I40E_PTT_UNUSED_ENTRY(164),
448 I40E_PTT_UNUSED_ENTRY(165),
449 I40E_PTT_UNUSED_ENTRY(166),
450 I40E_PTT_UNUSED_ENTRY(167),
451 I40E_PTT_UNUSED_ENTRY(168),
452 I40E_PTT_UNUSED_ENTRY(169),
454 I40E_PTT_UNUSED_ENTRY(170),
455 I40E_PTT_UNUSED_ENTRY(171),
456 I40E_PTT_UNUSED_ENTRY(172),
457 I40E_PTT_UNUSED_ENTRY(173),
458 I40E_PTT_UNUSED_ENTRY(174),
459 I40E_PTT_UNUSED_ENTRY(175),
460 I40E_PTT_UNUSED_ENTRY(176),
461 I40E_PTT_UNUSED_ENTRY(177),
462 I40E_PTT_UNUSED_ENTRY(178),
463 I40E_PTT_UNUSED_ENTRY(179),
465 I40E_PTT_UNUSED_ENTRY(180),
466 I40E_PTT_UNUSED_ENTRY(181),
467 I40E_PTT_UNUSED_ENTRY(182),
468 I40E_PTT_UNUSED_ENTRY(183),
469 I40E_PTT_UNUSED_ENTRY(184),
470 I40E_PTT_UNUSED_ENTRY(185),
471 I40E_PTT_UNUSED_ENTRY(186),
472 I40E_PTT_UNUSED_ENTRY(187),
473 I40E_PTT_UNUSED_ENTRY(188),
474 I40E_PTT_UNUSED_ENTRY(189),
476 I40E_PTT_UNUSED_ENTRY(190),
477 I40E_PTT_UNUSED_ENTRY(191),
478 I40E_PTT_UNUSED_ENTRY(192),
479 I40E_PTT_UNUSED_ENTRY(193),
480 I40E_PTT_UNUSED_ENTRY(194),
481 I40E_PTT_UNUSED_ENTRY(195),
482 I40E_PTT_UNUSED_ENTRY(196),
483 I40E_PTT_UNUSED_ENTRY(197),
484 I40E_PTT_UNUSED_ENTRY(198),
485 I40E_PTT_UNUSED_ENTRY(199),
487 I40E_PTT_UNUSED_ENTRY(200),
488 I40E_PTT_UNUSED_ENTRY(201),
489 I40E_PTT_UNUSED_ENTRY(202),
490 I40E_PTT_UNUSED_ENTRY(203),
491 I40E_PTT_UNUSED_ENTRY(204),
492 I40E_PTT_UNUSED_ENTRY(205),
493 I40E_PTT_UNUSED_ENTRY(206),
494 I40E_PTT_UNUSED_ENTRY(207),
495 I40E_PTT_UNUSED_ENTRY(208),
496 I40E_PTT_UNUSED_ENTRY(209),
498 I40E_PTT_UNUSED_ENTRY(210),
499 I40E_PTT_UNUSED_ENTRY(211),
500 I40E_PTT_UNUSED_ENTRY(212),
501 I40E_PTT_UNUSED_ENTRY(213),
502 I40E_PTT_UNUSED_ENTRY(214),
503 I40E_PTT_UNUSED_ENTRY(215),
504 I40E_PTT_UNUSED_ENTRY(216),
505 I40E_PTT_UNUSED_ENTRY(217),
506 I40E_PTT_UNUSED_ENTRY(218),
507 I40E_PTT_UNUSED_ENTRY(219),
509 I40E_PTT_UNUSED_ENTRY(220),
510 I40E_PTT_UNUSED_ENTRY(221),
511 I40E_PTT_UNUSED_ENTRY(222),
512 I40E_PTT_UNUSED_ENTRY(223),
513 I40E_PTT_UNUSED_ENTRY(224),
514 I40E_PTT_UNUSED_ENTRY(225),
515 I40E_PTT_UNUSED_ENTRY(226),
516 I40E_PTT_UNUSED_ENTRY(227),
517 I40E_PTT_UNUSED_ENTRY(228),
518 I40E_PTT_UNUSED_ENTRY(229),
520 I40E_PTT_UNUSED_ENTRY(230),
521 I40E_PTT_UNUSED_ENTRY(231),
522 I40E_PTT_UNUSED_ENTRY(232),
523 I40E_PTT_UNUSED_ENTRY(233),
524 I40E_PTT_UNUSED_ENTRY(234),
525 I40E_PTT_UNUSED_ENTRY(235),
526 I40E_PTT_UNUSED_ENTRY(236),
527 I40E_PTT_UNUSED_ENTRY(237),
528 I40E_PTT_UNUSED_ENTRY(238),
529 I40E_PTT_UNUSED_ENTRY(239),
531 I40E_PTT_UNUSED_ENTRY(240),
532 I40E_PTT_UNUSED_ENTRY(241),
533 I40E_PTT_UNUSED_ENTRY(242),
534 I40E_PTT_UNUSED_ENTRY(243),
535 I40E_PTT_UNUSED_ENTRY(244),
536 I40E_PTT_UNUSED_ENTRY(245),
537 I40E_PTT_UNUSED_ENTRY(246),
538 I40E_PTT_UNUSED_ENTRY(247),
539 I40E_PTT_UNUSED_ENTRY(248),
540 I40E_PTT_UNUSED_ENTRY(249),
542 I40E_PTT_UNUSED_ENTRY(250),
543 I40E_PTT_UNUSED_ENTRY(251),
544 I40E_PTT_UNUSED_ENTRY(252),
545 I40E_PTT_UNUSED_ENTRY(253),
546 I40E_PTT_UNUSED_ENTRY(254),
547 I40E_PTT_UNUSED_ENTRY(255)
553 * i40e_init_shared_code - Initialize the shared code
554 * @hw: pointer to hardware structure
556 * This assigns the MAC type and PHY code and inits the NVM.
557 * Does not touch the hardware. This function must be called prior to any
558 * other function in the shared code. The i40e_hw structure should be
559 * memset to 0 prior to calling this function. The following fields in
560 * hw structure should be filled in prior to calling this function:
561 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
562 * subsystem_vendor_id, and revision_id
564 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
566 enum i40e_status_code status = I40E_SUCCESS;
569 DEBUGFUNC("i40e_init_shared_code");
571 i40e_set_mac_type(hw);
573 switch (hw->mac.type) {
577 return I40E_ERR_DEVICE_NOT_SUPPORTED;
580 hw->phy.get_link_info = true;
582 /* Determine port number */
583 reg = rd32(hw, I40E_PFGEN_PORTNUM);
584 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
585 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
588 /* Determine the PF number based on the PCI fn */
589 reg = rd32(hw, I40E_GLPCI_CAPSUP);
590 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
591 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
593 hw->pf_id = (u8)hw->bus.func;
595 status = i40e_init_nvm(hw);
600 * i40e_aq_mac_address_read - Retrieve the MAC addresses
601 * @hw: pointer to the hw struct
602 * @flags: a return indicator of what addresses were added to the addr store
603 * @addrs: the requestor's mac addr store
604 * @cmd_details: pointer to command details structure or NULL
606 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
608 struct i40e_aqc_mac_address_read_data *addrs,
609 struct i40e_asq_cmd_details *cmd_details)
611 struct i40e_aq_desc desc;
612 struct i40e_aqc_mac_address_read *cmd_data =
613 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
614 enum i40e_status_code status;
616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
617 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
619 status = i40e_asq_send_command(hw, &desc, addrs,
620 sizeof(*addrs), cmd_details);
621 *flags = LE16_TO_CPU(cmd_data->command_flags);
627 * i40e_aq_mac_address_write - Change the MAC addresses
628 * @hw: pointer to the hw struct
629 * @flags: indicates which MAC to be written
630 * @mac_addr: address to write
631 * @cmd_details: pointer to command details structure or NULL
633 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
634 u16 flags, u8 *mac_addr,
635 struct i40e_asq_cmd_details *cmd_details)
637 struct i40e_aq_desc desc;
638 struct i40e_aqc_mac_address_write *cmd_data =
639 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
640 enum i40e_status_code status;
642 i40e_fill_default_direct_cmd_desc(&desc,
643 i40e_aqc_opc_mac_address_write);
644 cmd_data->command_flags = CPU_TO_LE16(flags);
645 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
646 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
647 ((u32)mac_addr[3] << 16) |
648 ((u32)mac_addr[4] << 8) |
651 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
657 * i40e_get_mac_addr - get MAC address
658 * @hw: pointer to the HW structure
659 * @mac_addr: pointer to MAC address
661 * Reads the adapter's MAC address from register
663 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
665 struct i40e_aqc_mac_address_read_data addrs;
666 enum i40e_status_code status;
669 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
671 if (flags & I40E_AQC_LAN_ADDR_VALID)
672 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
678 * i40e_get_port_mac_addr - get Port MAC address
679 * @hw: pointer to the HW structure
680 * @mac_addr: pointer to Port MAC address
682 * Reads the adapter's Port MAC address
684 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
686 struct i40e_aqc_mac_address_read_data addrs;
687 enum i40e_status_code status;
690 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
694 if (flags & I40E_AQC_PORT_ADDR_VALID)
695 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
697 status = I40E_ERR_INVALID_MAC_ADDR;
703 * i40e_pre_tx_queue_cfg - pre tx queue configure
704 * @hw: pointer to the HW structure
705 * @queue: target pf queue index
706 * @enable: state change request
708 * Handles hw requirement to indicate intention to enable
709 * or disable target queue.
711 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
713 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
717 if (abs_queue_idx >= 128) {
718 reg_block = abs_queue_idx / 128;
719 abs_queue_idx %= 128;
722 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
723 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
724 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
727 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
729 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
731 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
735 * i40e_validate_mac_addr - Validate unicast MAC address
736 * @mac_addr: pointer to MAC address
738 * Tests a MAC address to ensure it is a valid Individual Address
740 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
742 enum i40e_status_code status = I40E_SUCCESS;
744 DEBUGFUNC("i40e_validate_mac_addr");
746 /* Broadcast addresses ARE multicast addresses
747 * Make sure it is not a multicast address
748 * Reject the zero address
750 if (I40E_IS_MULTICAST(mac_addr) ||
751 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
752 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
753 status = I40E_ERR_INVALID_MAC_ADDR;
759 * i40e_get_media_type - Gets media type
760 * @hw: pointer to the hardware structure
762 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
764 enum i40e_media_type media;
766 switch (hw->phy.link_info.phy_type) {
767 case I40E_PHY_TYPE_10GBASE_SR:
768 case I40E_PHY_TYPE_10GBASE_LR:
769 case I40E_PHY_TYPE_1000BASE_SX:
770 case I40E_PHY_TYPE_1000BASE_LX:
771 case I40E_PHY_TYPE_40GBASE_SR4:
772 case I40E_PHY_TYPE_40GBASE_LR4:
773 media = I40E_MEDIA_TYPE_FIBER;
775 case I40E_PHY_TYPE_100BASE_TX:
776 case I40E_PHY_TYPE_1000BASE_T:
777 case I40E_PHY_TYPE_10GBASE_T:
778 media = I40E_MEDIA_TYPE_BASET;
780 case I40E_PHY_TYPE_10GBASE_CR1_CU:
781 case I40E_PHY_TYPE_40GBASE_CR4_CU:
782 case I40E_PHY_TYPE_10GBASE_CR1:
783 case I40E_PHY_TYPE_40GBASE_CR4:
784 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
785 media = I40E_MEDIA_TYPE_DA;
787 case I40E_PHY_TYPE_1000BASE_KX:
788 case I40E_PHY_TYPE_10GBASE_KX4:
789 case I40E_PHY_TYPE_10GBASE_KR:
790 case I40E_PHY_TYPE_40GBASE_KR4:
791 media = I40E_MEDIA_TYPE_BACKPLANE;
793 case I40E_PHY_TYPE_SGMII:
794 case I40E_PHY_TYPE_XAUI:
795 case I40E_PHY_TYPE_XFI:
796 case I40E_PHY_TYPE_XLAUI:
797 case I40E_PHY_TYPE_XLPPI:
799 media = I40E_MEDIA_TYPE_UNKNOWN;
806 #define I40E_PF_RESET_WAIT_COUNT 100
808 * i40e_pf_reset - Reset the PF
809 * @hw: pointer to the hardware structure
811 * Assuming someone else has triggered a global reset,
812 * assure the global reset is complete and then reset the PF
814 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
821 /* Poll for Global Reset steady state in case of recent GRST.
822 * The grst delay value is in 100ms units, and we'll wait a
823 * couple counts longer to be sure we don't just miss the end.
825 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
826 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
827 for (cnt = 0; cnt < grst_del + 2; cnt++) {
828 reg = rd32(hw, I40E_GLGEN_RSTAT);
829 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
831 i40e_msec_delay(100);
833 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
834 DEBUGOUT("Global reset polling failed to complete.\n");
835 return I40E_ERR_RESET_FAILED;
838 /* Now Wait for the FW to be ready */
839 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
840 reg = rd32(hw, I40E_GLNVM_ULD);
841 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
842 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
843 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
844 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
845 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
850 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
851 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
852 DEBUGOUT("wait for FW Reset complete timedout\n");
853 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
854 return I40E_ERR_RESET_FAILED;
857 /* If there was a Global Reset in progress when we got here,
858 * we don't need to do the PF Reset
861 reg = rd32(hw, I40E_PFGEN_CTRL);
862 wr32(hw, I40E_PFGEN_CTRL,
863 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
864 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
865 reg = rd32(hw, I40E_PFGEN_CTRL);
866 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
870 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
871 DEBUGOUT("PF reset polling failed to complete.\n");
872 return I40E_ERR_RESET_FAILED;
876 i40e_clear_pxe_mode(hw);
883 * i40e_clear_hw - clear out any left over hw state
884 * @hw: pointer to the hw struct
886 * Clear queues and interrupts, typically called at init time,
887 * but after the capabilities have been found so we know how many
888 * queues and msix vectors have been allocated.
890 void i40e_clear_hw(struct i40e_hw *hw)
892 u32 num_queues, base_queue;
900 /* get number of interrupts, queues, and vfs */
901 val = rd32(hw, I40E_GLPCI_CNF2);
902 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
903 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
904 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
905 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
907 val = rd32(hw, I40E_PFLAN_QALLOC);
908 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
909 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
910 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
911 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
912 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
913 num_queues = (j - base_queue) + 1;
917 val = rd32(hw, I40E_PF_VT_PFALLOC);
918 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
919 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
920 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
921 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
922 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
923 num_vfs = (j - i) + 1;
927 /* stop all the interrupts */
928 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
929 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
930 for (i = 0; i < num_pf_int - 2; i++)
931 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
933 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
934 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
935 wr32(hw, I40E_PFINT_LNKLST0, val);
936 for (i = 0; i < num_pf_int - 2; i++)
937 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
938 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
939 for (i = 0; i < num_vfs; i++)
940 wr32(hw, I40E_VPINT_LNKLST0(i), val);
941 for (i = 0; i < num_vf_int - 2; i++)
942 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
944 /* warn the HW of the coming Tx disables */
945 for (i = 0; i < num_queues; i++) {
946 u32 abs_queue_idx = base_queue + i;
949 if (abs_queue_idx >= 128) {
950 reg_block = abs_queue_idx / 128;
951 abs_queue_idx %= 128;
954 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
955 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
956 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
957 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
959 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
961 i40e_usec_delay(400);
963 /* stop all the queues */
964 for (i = 0; i < num_queues; i++) {
965 wr32(hw, I40E_QINT_TQCTL(i), 0);
966 wr32(hw, I40E_QTX_ENA(i), 0);
967 wr32(hw, I40E_QINT_RQCTL(i), 0);
968 wr32(hw, I40E_QRX_ENA(i), 0);
971 /* short wait for all queue disables to settle */
976 * i40e_clear_pxe_mode - clear pxe operations mode
977 * @hw: pointer to the hw struct
979 * Make sure all PXE mode settings are cleared, including things
980 * like descriptor fetch/write-back mode.
982 void i40e_clear_pxe_mode(struct i40e_hw *hw)
984 if (i40e_check_asq_alive(hw))
985 i40e_aq_clear_pxe_mode(hw, NULL);
989 * i40e_led_is_mine - helper to find matching led
990 * @hw: pointer to the hw struct
991 * @idx: index into GPIO registers
993 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
995 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1000 if (!hw->func_caps.led[idx])
1003 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1004 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1005 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1007 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1008 * if it is not our port then ignore
1010 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1017 #define I40E_LED0 22
1018 #define I40E_LINK_ACTIVITY 0xC
1021 * i40e_led_get - return current on/off mode
1022 * @hw: pointer to the hw struct
1024 * The value returned is the 'mode' field as defined in the
1025 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1026 * values are variations of possible behaviors relating to
1027 * blink, link, and wire.
1029 u32 i40e_led_get(struct i40e_hw *hw)
1034 /* as per the documentation GPIO 22-29 are the LED
1035 * GPIO pins named LED0..LED7
1037 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1038 u32 gpio_val = i40e_led_is_mine(hw, i);
1043 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1044 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1052 * i40e_led_set - set new on/off mode
1053 * @hw: pointer to the hw struct
1054 * @mode: 0=off, 0xf=on (else see manual for mode details)
1055 * @blink: true if the LED should blink when on, false if steady
1057 * if this function is used to turn on the blink it should
1058 * be used to disable the blink when restoring the original state.
1060 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1064 if (mode & 0xfffffff0)
1065 DEBUGOUT1("invalid mode passed in %X\n", mode);
1067 /* as per the documentation GPIO 22-29 are the LED
1068 * GPIO pins named LED0..LED7
1070 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1071 u32 gpio_val = i40e_led_is_mine(hw, i);
1076 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1077 /* this & is a bit of paranoia, but serves as a range check */
1078 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1079 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1081 if (mode == I40E_LINK_ACTIVITY)
1084 gpio_val |= (blink ? 1 : 0) <<
1085 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1087 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1092 /* Admin command wrappers */
1095 * i40e_aq_get_phy_capabilities
1096 * @hw: pointer to the hw struct
1097 * @abilities: structure for PHY capabilities to be filled
1098 * @qualified_modules: report Qualified Modules
1099 * @report_init: report init capabilities (active are default)
1100 * @cmd_details: pointer to command details structure or NULL
1102 * Returns the various PHY abilities supported on the Port.
1104 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1105 bool qualified_modules, bool report_init,
1106 struct i40e_aq_get_phy_abilities_resp *abilities,
1107 struct i40e_asq_cmd_details *cmd_details)
1109 struct i40e_aq_desc desc;
1110 enum i40e_status_code status;
1111 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1114 return I40E_ERR_PARAM;
1116 i40e_fill_default_direct_cmd_desc(&desc,
1117 i40e_aqc_opc_get_phy_abilities);
1119 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1120 if (abilities_size > I40E_AQ_LARGE_BUF)
1121 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1123 if (qualified_modules)
1124 desc.params.external.param0 |=
1125 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1128 desc.params.external.param0 |=
1129 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1131 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1134 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1135 status = I40E_ERR_UNKNOWN_PHY;
1141 * i40e_aq_set_phy_config
1142 * @hw: pointer to the hw struct
1143 * @config: structure with PHY configuration to be set
1144 * @cmd_details: pointer to command details structure or NULL
1146 * Set the various PHY configuration parameters
1147 * supported on the Port.One or more of the Set PHY config parameters may be
1148 * ignored in an MFP mode as the PF may not have the privilege to set some
1149 * of the PHY Config parameters. This status will be indicated by the
1152 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1153 struct i40e_aq_set_phy_config *config,
1154 struct i40e_asq_cmd_details *cmd_details)
1156 struct i40e_aq_desc desc;
1157 struct i40e_aq_set_phy_config *cmd =
1158 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1159 enum i40e_status_code status;
1162 return I40E_ERR_PARAM;
1164 i40e_fill_default_direct_cmd_desc(&desc,
1165 i40e_aqc_opc_set_phy_config);
1169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1176 * @hw: pointer to the hw struct
1178 * Set the requested flow control mode using set_phy_config.
1180 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1181 bool atomic_restart)
1183 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1184 struct i40e_aq_get_phy_abilities_resp abilities;
1185 struct i40e_aq_set_phy_config config;
1186 enum i40e_status_code status;
1187 u8 pause_mask = 0x0;
1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1194 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1196 case I40E_FC_RX_PAUSE:
1197 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1199 case I40E_FC_TX_PAUSE:
1200 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1206 /* Get the current phy config */
1207 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1210 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1214 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1215 /* clear the old pause settings */
1216 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1217 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1218 /* set the new abilities */
1219 config.abilities |= pause_mask;
1220 /* If the abilities have changed, then set the new config */
1221 if (config.abilities != abilities.abilities) {
1222 /* Auto restart link so settings take effect */
1224 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1225 /* Copy over all the old settings */
1226 config.phy_type = abilities.phy_type;
1227 config.link_speed = abilities.link_speed;
1228 config.eee_capability = abilities.eee_capability;
1229 config.eeer = abilities.eeer_val;
1230 config.low_power_ctrl = abilities.d3_lpan;
1231 status = i40e_aq_set_phy_config(hw, &config, NULL);
1234 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1236 /* Update the link info */
1237 status = i40e_update_link_info(hw, true);
1239 /* Wait a little bit (on 40G cards it sometimes takes a really
1240 * long time for link to come back from the atomic reset)
1243 i40e_msec_delay(1000);
1244 status = i40e_update_link_info(hw, true);
1247 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1253 * i40e_aq_set_mac_config
1254 * @hw: pointer to the hw struct
1255 * @max_frame_size: Maximum Frame Size to be supported by the port
1256 * @crc_en: Tell HW to append a CRC to outgoing frames
1257 * @pacing: Pacing configurations
1258 * @cmd_details: pointer to command details structure or NULL
1260 * Configure MAC settings for frame size, jumbo frame support and the
1261 * addition of a CRC by the hardware.
1263 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1265 bool crc_en, u16 pacing,
1266 struct i40e_asq_cmd_details *cmd_details)
1268 struct i40e_aq_desc desc;
1269 struct i40e_aq_set_mac_config *cmd =
1270 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1271 enum i40e_status_code status;
1273 if (max_frame_size == 0)
1274 return I40E_ERR_PARAM;
1276 i40e_fill_default_direct_cmd_desc(&desc,
1277 i40e_aqc_opc_set_mac_config);
1279 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1280 cmd->params = ((u8)pacing & 0x0F) << 3;
1282 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1284 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1290 * i40e_aq_clear_pxe_mode
1291 * @hw: pointer to the hw struct
1292 * @cmd_details: pointer to command details structure or NULL
1294 * Tell the firmware that the driver is taking over from PXE
1296 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1297 struct i40e_asq_cmd_details *cmd_details)
1299 enum i40e_status_code status;
1300 struct i40e_aq_desc desc;
1301 struct i40e_aqc_clear_pxe *cmd =
1302 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1304 i40e_fill_default_direct_cmd_desc(&desc,
1305 i40e_aqc_opc_clear_pxe_mode);
1309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1311 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1317 * i40e_aq_set_link_restart_an
1318 * @hw: pointer to the hw struct
1319 * @enable_link: if true: enable link, if false: disable link
1320 * @cmd_details: pointer to command details structure or NULL
1322 * Sets up the link and restarts the Auto-Negotiation over the link.
1324 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1325 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1327 struct i40e_aq_desc desc;
1328 struct i40e_aqc_set_link_restart_an *cmd =
1329 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1330 enum i40e_status_code status;
1332 i40e_fill_default_direct_cmd_desc(&desc,
1333 i40e_aqc_opc_set_link_restart_an);
1335 cmd->command = I40E_AQ_PHY_RESTART_AN;
1337 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1339 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1347 * i40e_aq_get_link_info
1348 * @hw: pointer to the hw struct
1349 * @enable_lse: enable/disable LinkStatusEvent reporting
1350 * @link: pointer to link status structure - optional
1351 * @cmd_details: pointer to command details structure or NULL
1353 * Returns the link status of the adapter.
1355 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1356 bool enable_lse, struct i40e_link_status *link,
1357 struct i40e_asq_cmd_details *cmd_details)
1359 struct i40e_aq_desc desc;
1360 struct i40e_aqc_get_link_status *resp =
1361 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1362 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1363 enum i40e_status_code status;
1364 bool tx_pause, rx_pause;
1367 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1370 command_flags = I40E_AQ_LSE_ENABLE;
1372 command_flags = I40E_AQ_LSE_DISABLE;
1373 resp->command_flags = CPU_TO_LE16(command_flags);
1375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1377 if (status != I40E_SUCCESS)
1378 goto aq_get_link_info_exit;
1380 /* save off old link status information */
1381 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1382 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1384 /* update link status */
1385 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1386 hw->phy.media_type = i40e_get_media_type(hw);
1387 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1388 hw_link_info->link_info = resp->link_info;
1389 hw_link_info->an_info = resp->an_info;
1390 hw_link_info->ext_info = resp->ext_info;
1391 hw_link_info->loopback = resp->loopback;
1392 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1393 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1395 /* update fc info */
1396 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1397 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1398 if (tx_pause & rx_pause)
1399 hw->fc.current_mode = I40E_FC_FULL;
1401 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1403 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1405 hw->fc.current_mode = I40E_FC_NONE;
1407 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1408 hw_link_info->crc_enable = true;
1410 hw_link_info->crc_enable = false;
1412 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1413 hw_link_info->lse_enable = true;
1415 hw_link_info->lse_enable = false;
1417 /* save link status information */
1419 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1420 I40E_NONDMA_TO_NONDMA);
1422 /* flag cleared so helper functions don't call AQ again */
1423 hw->phy.get_link_info = false;
1425 aq_get_link_info_exit:
1430 * i40e_update_link_info
1431 * @hw: pointer to the hw struct
1432 * @enable_lse: enable/disable LinkStatusEvent reporting
1434 * Returns the link status of the adapter
1436 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
1439 struct i40e_aq_get_phy_abilities_resp abilities;
1440 enum i40e_status_code status;
1442 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1446 status = i40e_aq_get_phy_capabilities(hw, false, false,
1451 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1452 hw->phy.link_info.an_enabled = true;
1454 hw->phy.link_info.an_enabled = false;
1460 * i40e_aq_set_phy_int_mask
1461 * @hw: pointer to the hw struct
1462 * @mask: interrupt mask to be set
1463 * @cmd_details: pointer to command details structure or NULL
1465 * Set link interrupt mask.
1467 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1469 struct i40e_asq_cmd_details *cmd_details)
1471 struct i40e_aq_desc desc;
1472 struct i40e_aqc_set_phy_int_mask *cmd =
1473 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1474 enum i40e_status_code status;
1476 i40e_fill_default_direct_cmd_desc(&desc,
1477 i40e_aqc_opc_set_phy_int_mask);
1479 cmd->event_mask = CPU_TO_LE16(mask);
1481 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1487 * i40e_aq_get_local_advt_reg
1488 * @hw: pointer to the hw struct
1489 * @advt_reg: local AN advertisement register value
1490 * @cmd_details: pointer to command details structure or NULL
1492 * Get the Local AN advertisement register value.
1494 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1496 struct i40e_asq_cmd_details *cmd_details)
1498 struct i40e_aq_desc desc;
1499 struct i40e_aqc_an_advt_reg *resp =
1500 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1501 enum i40e_status_code status;
1503 i40e_fill_default_direct_cmd_desc(&desc,
1504 i40e_aqc_opc_get_local_advt_reg);
1506 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1508 if (status != I40E_SUCCESS)
1509 goto aq_get_local_advt_reg_exit;
1511 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1512 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1514 aq_get_local_advt_reg_exit:
1519 * i40e_aq_set_local_advt_reg
1520 * @hw: pointer to the hw struct
1521 * @advt_reg: local AN advertisement register value
1522 * @cmd_details: pointer to command details structure or NULL
1524 * Get the Local AN advertisement register value.
1526 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1528 struct i40e_asq_cmd_details *cmd_details)
1530 struct i40e_aq_desc desc;
1531 struct i40e_aqc_an_advt_reg *cmd =
1532 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1533 enum i40e_status_code status;
1535 i40e_fill_default_direct_cmd_desc(&desc,
1536 i40e_aqc_opc_get_local_advt_reg);
1538 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1539 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1541 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1547 * i40e_aq_get_partner_advt
1548 * @hw: pointer to the hw struct
1549 * @advt_reg: AN partner advertisement register value
1550 * @cmd_details: pointer to command details structure or NULL
1552 * Get the link partner AN advertisement register value.
1554 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1556 struct i40e_asq_cmd_details *cmd_details)
1558 struct i40e_aq_desc desc;
1559 struct i40e_aqc_an_advt_reg *resp =
1560 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1561 enum i40e_status_code status;
1563 i40e_fill_default_direct_cmd_desc(&desc,
1564 i40e_aqc_opc_get_partner_advt);
1566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1568 if (status != I40E_SUCCESS)
1569 goto aq_get_partner_advt_exit;
1571 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1572 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1574 aq_get_partner_advt_exit:
1579 * i40e_aq_set_lb_modes
1580 * @hw: pointer to the hw struct
1581 * @lb_modes: loopback mode to be set
1582 * @cmd_details: pointer to command details structure or NULL
1584 * Sets loopback modes.
1586 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1588 struct i40e_asq_cmd_details *cmd_details)
1590 struct i40e_aq_desc desc;
1591 struct i40e_aqc_set_lb_mode *cmd =
1592 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1593 enum i40e_status_code status;
1595 i40e_fill_default_direct_cmd_desc(&desc,
1596 i40e_aqc_opc_set_lb_modes);
1598 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1606 * i40e_aq_set_phy_debug
1607 * @hw: pointer to the hw struct
1608 * @cmd_flags: debug command flags
1609 * @cmd_details: pointer to command details structure or NULL
1611 * Reset the external PHY.
1613 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1614 struct i40e_asq_cmd_details *cmd_details)
1616 struct i40e_aq_desc desc;
1617 struct i40e_aqc_set_phy_debug *cmd =
1618 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1619 enum i40e_status_code status;
1621 i40e_fill_default_direct_cmd_desc(&desc,
1622 i40e_aqc_opc_set_phy_debug);
1624 cmd->command_flags = cmd_flags;
1626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1633 * @hw: pointer to the hw struct
1634 * @vsi_ctx: pointer to a vsi context struct
1635 * @cmd_details: pointer to command details structure or NULL
1637 * Add a VSI context to the hardware.
1639 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1640 struct i40e_vsi_context *vsi_ctx,
1641 struct i40e_asq_cmd_details *cmd_details)
1643 struct i40e_aq_desc desc;
1644 struct i40e_aqc_add_get_update_vsi *cmd =
1645 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1646 struct i40e_aqc_add_get_update_vsi_completion *resp =
1647 (struct i40e_aqc_add_get_update_vsi_completion *)
1649 enum i40e_status_code status;
1651 i40e_fill_default_direct_cmd_desc(&desc,
1652 i40e_aqc_opc_add_vsi);
1654 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1655 cmd->connection_type = vsi_ctx->connection_type;
1656 cmd->vf_id = vsi_ctx->vf_num;
1657 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1659 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1661 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1662 sizeof(vsi_ctx->info), cmd_details);
1664 if (status != I40E_SUCCESS)
1665 goto aq_add_vsi_exit;
1667 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1668 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1669 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1670 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1677 * i40e_aq_set_default_vsi
1678 * @hw: pointer to the hw struct
1680 * @cmd_details: pointer to command details structure or NULL
1682 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1684 struct i40e_asq_cmd_details *cmd_details)
1686 struct i40e_aq_desc desc;
1687 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1688 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1690 enum i40e_status_code status;
1692 i40e_fill_default_direct_cmd_desc(&desc,
1693 i40e_aqc_opc_set_vsi_promiscuous_modes);
1695 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1696 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1697 cmd->seid = CPU_TO_LE16(seid);
1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1705 * i40e_aq_set_vsi_unicast_promiscuous
1706 * @hw: pointer to the hw struct
1708 * @set: set unicast promiscuous enable/disable
1709 * @cmd_details: pointer to command details structure or NULL
1711 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1713 struct i40e_asq_cmd_details *cmd_details)
1715 struct i40e_aq_desc desc;
1716 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1717 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1718 enum i40e_status_code status;
1721 i40e_fill_default_direct_cmd_desc(&desc,
1722 i40e_aqc_opc_set_vsi_promiscuous_modes);
1725 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1727 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1729 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1731 cmd->seid = CPU_TO_LE16(seid);
1732 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1738 * i40e_aq_set_vsi_multicast_promiscuous
1739 * @hw: pointer to the hw struct
1741 * @set: set multicast promiscuous enable/disable
1742 * @cmd_details: pointer to command details structure or NULL
1744 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1745 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1747 struct i40e_aq_desc desc;
1748 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1749 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1750 enum i40e_status_code status;
1753 i40e_fill_default_direct_cmd_desc(&desc,
1754 i40e_aqc_opc_set_vsi_promiscuous_modes);
1757 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1759 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1761 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1763 cmd->seid = CPU_TO_LE16(seid);
1764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1770 * i40e_aq_set_vsi_broadcast
1771 * @hw: pointer to the hw struct
1773 * @set_filter: true to set filter, false to clear filter
1774 * @cmd_details: pointer to command details structure or NULL
1776 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1778 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1779 u16 seid, bool set_filter,
1780 struct i40e_asq_cmd_details *cmd_details)
1782 struct i40e_aq_desc desc;
1783 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1784 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1785 enum i40e_status_code status;
1787 i40e_fill_default_direct_cmd_desc(&desc,
1788 i40e_aqc_opc_set_vsi_promiscuous_modes);
1791 cmd->promiscuous_flags
1792 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1794 cmd->promiscuous_flags
1795 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1797 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1798 cmd->seid = CPU_TO_LE16(seid);
1799 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1805 * i40e_get_vsi_params - get VSI configuration info
1806 * @hw: pointer to the hw struct
1807 * @vsi_ctx: pointer to a vsi context struct
1808 * @cmd_details: pointer to command details structure or NULL
1810 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1811 struct i40e_vsi_context *vsi_ctx,
1812 struct i40e_asq_cmd_details *cmd_details)
1814 struct i40e_aq_desc desc;
1815 struct i40e_aqc_add_get_update_vsi *cmd =
1816 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1817 struct i40e_aqc_add_get_update_vsi_completion *resp =
1818 (struct i40e_aqc_add_get_update_vsi_completion *)
1820 enum i40e_status_code status;
1822 UNREFERENCED_1PARAMETER(cmd_details);
1823 i40e_fill_default_direct_cmd_desc(&desc,
1824 i40e_aqc_opc_get_vsi_parameters);
1826 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1828 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1830 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1831 sizeof(vsi_ctx->info), NULL);
1833 if (status != I40E_SUCCESS)
1834 goto aq_get_vsi_params_exit;
1836 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1837 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1838 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1839 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1841 aq_get_vsi_params_exit:
1846 * i40e_aq_update_vsi_params
1847 * @hw: pointer to the hw struct
1848 * @vsi_ctx: pointer to a vsi context struct
1849 * @cmd_details: pointer to command details structure or NULL
1851 * Update a VSI context.
1853 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1854 struct i40e_vsi_context *vsi_ctx,
1855 struct i40e_asq_cmd_details *cmd_details)
1857 struct i40e_aq_desc desc;
1858 struct i40e_aqc_add_get_update_vsi *cmd =
1859 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1860 enum i40e_status_code status;
1862 i40e_fill_default_direct_cmd_desc(&desc,
1863 i40e_aqc_opc_update_vsi_parameters);
1864 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1866 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1868 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1869 sizeof(vsi_ctx->info), cmd_details);
1875 * i40e_aq_get_switch_config
1876 * @hw: pointer to the hardware structure
1877 * @buf: pointer to the result buffer
1878 * @buf_size: length of input buffer
1879 * @start_seid: seid to start for the report, 0 == beginning
1880 * @cmd_details: pointer to command details structure or NULL
1882 * Fill the buf with switch configuration returned from AdminQ command
1884 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1885 struct i40e_aqc_get_switch_config_resp *buf,
1886 u16 buf_size, u16 *start_seid,
1887 struct i40e_asq_cmd_details *cmd_details)
1889 struct i40e_aq_desc desc;
1890 struct i40e_aqc_switch_seid *scfg =
1891 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1892 enum i40e_status_code status;
1894 i40e_fill_default_direct_cmd_desc(&desc,
1895 i40e_aqc_opc_get_switch_config);
1896 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1897 if (buf_size > I40E_AQ_LARGE_BUF)
1898 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1899 scfg->seid = CPU_TO_LE16(*start_seid);
1901 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1902 *start_seid = LE16_TO_CPU(scfg->seid);
1908 * i40e_aq_get_firmware_version
1909 * @hw: pointer to the hw struct
1910 * @fw_major_version: firmware major version
1911 * @fw_minor_version: firmware minor version
1912 * @api_major_version: major queue version
1913 * @api_minor_version: minor queue version
1914 * @cmd_details: pointer to command details structure or NULL
1916 * Get the firmware version from the admin queue commands
1918 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1919 u16 *fw_major_version, u16 *fw_minor_version,
1920 u16 *api_major_version, u16 *api_minor_version,
1921 struct i40e_asq_cmd_details *cmd_details)
1923 struct i40e_aq_desc desc;
1924 struct i40e_aqc_get_version *resp =
1925 (struct i40e_aqc_get_version *)&desc.params.raw;
1926 enum i40e_status_code status;
1928 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1930 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1932 if (status == I40E_SUCCESS) {
1933 if (fw_major_version != NULL)
1934 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1935 if (fw_minor_version != NULL)
1936 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1937 if (api_major_version != NULL)
1938 *api_major_version = LE16_TO_CPU(resp->api_major);
1939 if (api_minor_version != NULL)
1940 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1942 /* A workaround to fix the API version in SW */
1943 if (api_major_version && api_minor_version &&
1944 fw_major_version && fw_minor_version &&
1945 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1946 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1947 (*fw_major_version > 4)))
1948 *api_minor_version = 2;
1955 * i40e_aq_send_driver_version
1956 * @hw: pointer to the hw struct
1957 * @dv: driver's major, minor version
1958 * @cmd_details: pointer to command details structure or NULL
1960 * Send the driver version to the firmware
1962 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1963 struct i40e_driver_version *dv,
1964 struct i40e_asq_cmd_details *cmd_details)
1966 struct i40e_aq_desc desc;
1967 struct i40e_aqc_driver_version *cmd =
1968 (struct i40e_aqc_driver_version *)&desc.params.raw;
1969 enum i40e_status_code status;
1973 return I40E_ERR_PARAM;
1975 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1977 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI);
1978 cmd->driver_major_ver = dv->major_version;
1979 cmd->driver_minor_ver = dv->minor_version;
1980 cmd->driver_build_ver = dv->build_version;
1981 cmd->driver_subbuild_ver = dv->subbuild_version;
1984 while (len < sizeof(dv->driver_string) &&
1985 (dv->driver_string[len] < 0x80) &&
1986 dv->driver_string[len])
1988 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1995 * i40e_get_link_status - get status of the HW network link
1996 * @hw: pointer to the hw struct
1998 * Returns true if link is up, false if link is down.
2000 * Side effect: LinkStatusEvent reporting becomes enabled
2002 bool i40e_get_link_status(struct i40e_hw *hw)
2004 enum i40e_status_code status = I40E_SUCCESS;
2005 bool link_status = false;
2007 if (hw->phy.get_link_info) {
2008 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2010 if (status != I40E_SUCCESS)
2011 goto i40e_get_link_status_exit;
2014 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2016 i40e_get_link_status_exit:
2021 * i40e_get_link_speed
2022 * @hw: pointer to the hw struct
2024 * Returns the link speed of the adapter.
2026 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2028 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2029 enum i40e_status_code status = I40E_SUCCESS;
2031 if (hw->phy.get_link_info) {
2032 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2034 if (status != I40E_SUCCESS)
2035 goto i40e_link_speed_exit;
2038 speed = hw->phy.link_info.link_speed;
2040 i40e_link_speed_exit:
2045 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2046 * @hw: pointer to the hw struct
2047 * @uplink_seid: the MAC or other gizmo SEID
2048 * @downlink_seid: the VSI SEID
2049 * @enabled_tc: bitmap of TCs to be enabled
2050 * @default_port: true for default port VSI, false for control port
2051 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2052 * @veb_seid: pointer to where to put the resulting VEB SEID
2053 * @cmd_details: pointer to command details structure or NULL
2055 * This asks the FW to add a VEB between the uplink and downlink
2056 * elements. If the uplink SEID is 0, this will be a floating VEB.
2058 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2059 u16 downlink_seid, u8 enabled_tc,
2060 bool default_port, bool enable_l2_filtering,
2062 struct i40e_asq_cmd_details *cmd_details)
2064 struct i40e_aq_desc desc;
2065 struct i40e_aqc_add_veb *cmd =
2066 (struct i40e_aqc_add_veb *)&desc.params.raw;
2067 struct i40e_aqc_add_veb_completion *resp =
2068 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2069 enum i40e_status_code status;
2072 /* SEIDs need to either both be set or both be 0 for floating VEB */
2073 if (!!uplink_seid != !!downlink_seid)
2074 return I40E_ERR_PARAM;
2076 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2078 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2079 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2080 cmd->enable_tcs = enabled_tc;
2082 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2084 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2086 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2088 if (enable_l2_filtering)
2089 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2091 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2095 if (!status && veb_seid)
2096 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2102 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2103 * @hw: pointer to the hw struct
2104 * @veb_seid: the SEID of the VEB to query
2105 * @switch_id: the uplink switch id
2106 * @floating: set to true if the VEB is floating
2107 * @statistic_index: index of the stats counter block for this VEB
2108 * @vebs_used: number of VEB's used by function
2109 * @vebs_free: total VEB's not reserved by any function
2110 * @cmd_details: pointer to command details structure or NULL
2112 * This retrieves the parameters for a particular VEB, specified by
2113 * uplink_seid, and returns them to the caller.
2115 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2116 u16 veb_seid, u16 *switch_id,
2117 bool *floating, u16 *statistic_index,
2118 u16 *vebs_used, u16 *vebs_free,
2119 struct i40e_asq_cmd_details *cmd_details)
2121 struct i40e_aq_desc desc;
2122 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2123 (struct i40e_aqc_get_veb_parameters_completion *)
2125 enum i40e_status_code status;
2128 return I40E_ERR_PARAM;
2130 i40e_fill_default_direct_cmd_desc(&desc,
2131 i40e_aqc_opc_get_veb_parameters);
2132 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2139 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2140 if (statistic_index)
2141 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2143 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2145 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2147 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2148 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2159 * i40e_aq_add_macvlan
2160 * @hw: pointer to the hw struct
2161 * @seid: VSI for the mac address
2162 * @mv_list: list of macvlans to be added
2163 * @count: length of the list
2164 * @cmd_details: pointer to command details structure or NULL
2166 * Add MAC/VLAN addresses to the HW filtering
2168 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2169 struct i40e_aqc_add_macvlan_element_data *mv_list,
2170 u16 count, struct i40e_asq_cmd_details *cmd_details)
2172 struct i40e_aq_desc desc;
2173 struct i40e_aqc_macvlan *cmd =
2174 (struct i40e_aqc_macvlan *)&desc.params.raw;
2175 enum i40e_status_code status;
2178 if (count == 0 || !mv_list || !hw)
2179 return I40E_ERR_PARAM;
2181 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2183 /* prep the rest of the request */
2184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2185 cmd->num_addresses = CPU_TO_LE16(count);
2186 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2190 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2191 if (buf_size > I40E_AQ_LARGE_BUF)
2192 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2194 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2201 * i40e_aq_remove_macvlan
2202 * @hw: pointer to the hw struct
2203 * @seid: VSI for the mac address
2204 * @mv_list: list of macvlans to be removed
2205 * @count: length of the list
2206 * @cmd_details: pointer to command details structure or NULL
2208 * Remove MAC/VLAN addresses from the HW filtering
2210 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2211 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2212 u16 count, struct i40e_asq_cmd_details *cmd_details)
2214 struct i40e_aq_desc desc;
2215 struct i40e_aqc_macvlan *cmd =
2216 (struct i40e_aqc_macvlan *)&desc.params.raw;
2217 enum i40e_status_code status;
2220 if (count == 0 || !mv_list || !hw)
2221 return I40E_ERR_PARAM;
2223 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2225 /* prep the rest of the request */
2226 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2227 cmd->num_addresses = CPU_TO_LE16(count);
2228 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2232 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2233 if (buf_size > I40E_AQ_LARGE_BUF)
2234 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2236 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2243 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2244 * @hw: pointer to the hw struct
2245 * @seid: VSI for the vlan filters
2246 * @v_list: list of vlan filters to be added
2247 * @count: length of the list
2248 * @cmd_details: pointer to command details structure or NULL
2250 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2251 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2252 u8 count, struct i40e_asq_cmd_details *cmd_details)
2254 struct i40e_aq_desc desc;
2255 struct i40e_aqc_macvlan *cmd =
2256 (struct i40e_aqc_macvlan *)&desc.params.raw;
2257 enum i40e_status_code status;
2260 if (count == 0 || !v_list || !hw)
2261 return I40E_ERR_PARAM;
2263 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2265 /* prep the rest of the request */
2266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2267 cmd->num_addresses = CPU_TO_LE16(count);
2268 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2272 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2273 if (buf_size > I40E_AQ_LARGE_BUF)
2274 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2276 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2283 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2284 * @hw: pointer to the hw struct
2285 * @seid: VSI for the vlan filters
2286 * @v_list: list of macvlans to be removed
2287 * @count: length of the list
2288 * @cmd_details: pointer to command details structure or NULL
2290 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2291 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2292 u8 count, struct i40e_asq_cmd_details *cmd_details)
2294 struct i40e_aq_desc desc;
2295 struct i40e_aqc_macvlan *cmd =
2296 (struct i40e_aqc_macvlan *)&desc.params.raw;
2297 enum i40e_status_code status;
2300 if (count == 0 || !v_list || !hw)
2301 return I40E_ERR_PARAM;
2303 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2305 /* prep the rest of the request */
2306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2307 cmd->num_addresses = CPU_TO_LE16(count);
2308 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2312 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2313 if (buf_size > I40E_AQ_LARGE_BUF)
2314 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2316 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2323 * i40e_aq_send_msg_to_vf
2324 * @hw: pointer to the hardware structure
2325 * @vfid: vf id to send msg
2326 * @v_opcode: opcodes for VF-PF communication
2327 * @v_retval: return error code
2328 * @msg: pointer to the msg buffer
2329 * @msglen: msg length
2330 * @cmd_details: pointer to command details
2334 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2335 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2336 struct i40e_asq_cmd_details *cmd_details)
2338 struct i40e_aq_desc desc;
2339 struct i40e_aqc_pf_vf_message *cmd =
2340 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2341 enum i40e_status_code status;
2343 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2344 cmd->id = CPU_TO_LE32(vfid);
2345 desc.cookie_high = CPU_TO_LE32(v_opcode);
2346 desc.cookie_low = CPU_TO_LE32(v_retval);
2347 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2349 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2351 if (msglen > I40E_AQ_LARGE_BUF)
2352 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2353 desc.datalen = CPU_TO_LE16(msglen);
2355 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2361 * i40e_aq_debug_read_register
2362 * @hw: pointer to the hw struct
2363 * @reg_addr: register address
2364 * @reg_val: register value
2365 * @cmd_details: pointer to command details structure or NULL
2367 * Read the register using the admin queue commands
2369 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2370 u32 reg_addr, u64 *reg_val,
2371 struct i40e_asq_cmd_details *cmd_details)
2373 struct i40e_aq_desc desc;
2374 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2375 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2376 enum i40e_status_code status;
2378 if (reg_val == NULL)
2379 return I40E_ERR_PARAM;
2381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2383 cmd_resp->address = CPU_TO_LE32(reg_addr);
2385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2387 if (status == I40E_SUCCESS) {
2388 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2389 (u64)LE32_TO_CPU(cmd_resp->value_low);
2396 * i40e_aq_debug_write_register
2397 * @hw: pointer to the hw struct
2398 * @reg_addr: register address
2399 * @reg_val: register value
2400 * @cmd_details: pointer to command details structure or NULL
2402 * Write to a register using the admin queue commands
2404 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2405 u32 reg_addr, u64 reg_val,
2406 struct i40e_asq_cmd_details *cmd_details)
2408 struct i40e_aq_desc desc;
2409 struct i40e_aqc_debug_reg_read_write *cmd =
2410 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2411 enum i40e_status_code status;
2413 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2415 cmd->address = CPU_TO_LE32(reg_addr);
2416 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2417 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2419 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2425 * i40e_aq_get_hmc_resource_profile
2426 * @hw: pointer to the hw struct
2427 * @profile: type of profile the HMC is to be set as
2428 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2429 * @cmd_details: pointer to command details structure or NULL
2431 * query the HMC profile of the device.
2433 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2434 enum i40e_aq_hmc_profile *profile,
2435 u8 *pe_vf_enabled_count,
2436 struct i40e_asq_cmd_details *cmd_details)
2438 struct i40e_aq_desc desc;
2439 struct i40e_aq_get_set_hmc_resource_profile *resp =
2440 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2441 enum i40e_status_code status;
2443 i40e_fill_default_direct_cmd_desc(&desc,
2444 i40e_aqc_opc_query_hmc_resource_profile);
2445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2447 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2448 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2449 *pe_vf_enabled_count = resp->pe_vf_enabled &
2450 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2456 * i40e_aq_set_hmc_resource_profile
2457 * @hw: pointer to the hw struct
2458 * @profile: type of profile the HMC is to be set as
2459 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2460 * @cmd_details: pointer to command details structure or NULL
2462 * set the HMC profile of the device.
2464 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2465 enum i40e_aq_hmc_profile profile,
2466 u8 pe_vf_enabled_count,
2467 struct i40e_asq_cmd_details *cmd_details)
2469 struct i40e_aq_desc desc;
2470 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2471 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2472 enum i40e_status_code status;
2474 i40e_fill_default_direct_cmd_desc(&desc,
2475 i40e_aqc_opc_set_hmc_resource_profile);
2477 cmd->pm_profile = (u8)profile;
2478 cmd->pe_vf_enabled = pe_vf_enabled_count;
2480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2486 * i40e_aq_request_resource
2487 * @hw: pointer to the hw struct
2488 * @resource: resource id
2489 * @access: access type
2490 * @sdp_number: resource number
2491 * @timeout: the maximum time in ms that the driver may hold the resource
2492 * @cmd_details: pointer to command details structure or NULL
2494 * requests common resource using the admin queue commands
2496 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2497 enum i40e_aq_resources_ids resource,
2498 enum i40e_aq_resource_access_type access,
2499 u8 sdp_number, u64 *timeout,
2500 struct i40e_asq_cmd_details *cmd_details)
2502 struct i40e_aq_desc desc;
2503 struct i40e_aqc_request_resource *cmd_resp =
2504 (struct i40e_aqc_request_resource *)&desc.params.raw;
2505 enum i40e_status_code status;
2507 DEBUGFUNC("i40e_aq_request_resource");
2509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2511 cmd_resp->resource_id = CPU_TO_LE16(resource);
2512 cmd_resp->access_type = CPU_TO_LE16(access);
2513 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2515 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2516 /* The completion specifies the maximum time in ms that the driver
2517 * may hold the resource in the Timeout field.
2518 * If the resource is held by someone else, the command completes with
2519 * busy return value and the timeout field indicates the maximum time
2520 * the current owner of the resource has to free it.
2522 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2523 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2529 * i40e_aq_release_resource
2530 * @hw: pointer to the hw struct
2531 * @resource: resource id
2532 * @sdp_number: resource number
2533 * @cmd_details: pointer to command details structure or NULL
2535 * release common resource using the admin queue commands
2537 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2538 enum i40e_aq_resources_ids resource,
2540 struct i40e_asq_cmd_details *cmd_details)
2542 struct i40e_aq_desc desc;
2543 struct i40e_aqc_request_resource *cmd =
2544 (struct i40e_aqc_request_resource *)&desc.params.raw;
2545 enum i40e_status_code status;
2547 DEBUGFUNC("i40e_aq_release_resource");
2549 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2551 cmd->resource_id = CPU_TO_LE16(resource);
2552 cmd->resource_number = CPU_TO_LE32(sdp_number);
2554 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2561 * @hw: pointer to the hw struct
2562 * @module_pointer: module pointer location in words from the NVM beginning
2563 * @offset: byte offset from the module beginning
2564 * @length: length of the section to be read (in bytes from the offset)
2565 * @data: command buffer (size [bytes] = length)
2566 * @last_command: tells if this is the last command in a series
2567 * @cmd_details: pointer to command details structure or NULL
2569 * Read the NVM using the admin queue commands
2571 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2572 u32 offset, u16 length, void *data,
2574 struct i40e_asq_cmd_details *cmd_details)
2576 struct i40e_aq_desc desc;
2577 struct i40e_aqc_nvm_update *cmd =
2578 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2579 enum i40e_status_code status;
2581 DEBUGFUNC("i40e_aq_read_nvm");
2583 /* In offset the highest byte must be zeroed. */
2584 if (offset & 0xFF000000) {
2585 status = I40E_ERR_PARAM;
2586 goto i40e_aq_read_nvm_exit;
2589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2591 /* If this is the last command in a series, set the proper flag. */
2593 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2594 cmd->module_pointer = module_pointer;
2595 cmd->offset = CPU_TO_LE32(offset);
2596 cmd->length = CPU_TO_LE16(length);
2598 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2599 if (length > I40E_AQ_LARGE_BUF)
2600 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2602 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2604 i40e_aq_read_nvm_exit:
2610 * @hw: pointer to the hw struct
2611 * @module_pointer: module pointer location in words from the NVM beginning
2612 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2613 * @length: length of the section to be erased (expressed in 4 KB)
2614 * @last_command: tells if this is the last command in a series
2615 * @cmd_details: pointer to command details structure or NULL
2617 * Erase the NVM sector using the admin queue commands
2619 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2620 u32 offset, u16 length, bool last_command,
2621 struct i40e_asq_cmd_details *cmd_details)
2623 struct i40e_aq_desc desc;
2624 struct i40e_aqc_nvm_update *cmd =
2625 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2626 enum i40e_status_code status;
2628 DEBUGFUNC("i40e_aq_erase_nvm");
2630 /* In offset the highest byte must be zeroed. */
2631 if (offset & 0xFF000000) {
2632 status = I40E_ERR_PARAM;
2633 goto i40e_aq_erase_nvm_exit;
2636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2638 /* If this is the last command in a series, set the proper flag. */
2640 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2641 cmd->module_pointer = module_pointer;
2642 cmd->offset = CPU_TO_LE32(offset);
2643 cmd->length = CPU_TO_LE16(length);
2645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2647 i40e_aq_erase_nvm_exit:
2651 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2652 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2653 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2654 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2655 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2656 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2657 #define I40E_DEV_FUNC_CAP_VF 0x13
2658 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2659 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2660 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2661 #define I40E_DEV_FUNC_CAP_VSI 0x17
2662 #define I40E_DEV_FUNC_CAP_DCB 0x18
2663 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2664 #define I40E_DEV_FUNC_CAP_RSS 0x40
2665 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2666 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2667 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2668 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2669 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2670 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2671 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2672 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2673 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2674 #define I40E_DEV_FUNC_CAP_LED 0x61
2675 #define I40E_DEV_FUNC_CAP_SDP 0x62
2676 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2679 * i40e_parse_discover_capabilities
2680 * @hw: pointer to the hw struct
2681 * @buff: pointer to a buffer containing device/function capability records
2682 * @cap_count: number of capability records in the list
2683 * @list_type_opc: type of capabilities list to parse
2685 * Parse the device/function capabilities list.
2687 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2689 enum i40e_admin_queue_opc list_type_opc)
2691 struct i40e_aqc_list_capabilities_element_resp *cap;
2692 u32 number, logical_id, phys_id;
2693 struct i40e_hw_capabilities *p;
2697 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2699 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2700 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2701 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2702 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2706 for (i = 0; i < cap_count; i++, cap++) {
2707 id = LE16_TO_CPU(cap->id);
2708 number = LE32_TO_CPU(cap->number);
2709 logical_id = LE32_TO_CPU(cap->logical_id);
2710 phys_id = LE32_TO_CPU(cap->phys_id);
2713 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2714 p->switch_mode = number;
2716 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2717 p->management_mode = number;
2719 case I40E_DEV_FUNC_CAP_NPAR:
2720 p->npar_enable = number;
2722 case I40E_DEV_FUNC_CAP_OS2BMC:
2725 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2726 p->valid_functions = number;
2728 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2730 p->sr_iov_1_1 = true;
2732 case I40E_DEV_FUNC_CAP_VF:
2733 p->num_vfs = number;
2734 p->vf_base_id = logical_id;
2736 case I40E_DEV_FUNC_CAP_VMDQ:
2740 case I40E_DEV_FUNC_CAP_802_1_QBG:
2742 p->evb_802_1_qbg = true;
2744 case I40E_DEV_FUNC_CAP_802_1_QBH:
2746 p->evb_802_1_qbh = true;
2748 case I40E_DEV_FUNC_CAP_VSI:
2749 p->num_vsis = number;
2751 case I40E_DEV_FUNC_CAP_DCB:
2754 p->enabled_tcmap = logical_id;
2758 case I40E_DEV_FUNC_CAP_FCOE:
2762 case I40E_DEV_FUNC_CAP_RSS:
2764 p->rss_table_size = number;
2765 p->rss_table_entry_width = logical_id;
2767 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2768 p->num_rx_qp = number;
2769 p->base_queue = phys_id;
2771 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2772 p->num_tx_qp = number;
2773 p->base_queue = phys_id;
2775 case I40E_DEV_FUNC_CAP_MSIX:
2776 p->num_msix_vectors = number;
2778 case I40E_DEV_FUNC_CAP_MSIX_VF:
2779 p->num_msix_vectors_vf = number;
2781 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2783 p->mfp_mode_1 = true;
2785 case I40E_DEV_FUNC_CAP_CEM:
2789 case I40E_DEV_FUNC_CAP_IWARP:
2793 case I40E_DEV_FUNC_CAP_LED:
2794 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2795 p->led[phys_id] = true;
2797 case I40E_DEV_FUNC_CAP_SDP:
2798 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2799 p->sdp[phys_id] = true;
2801 case I40E_DEV_FUNC_CAP_MDIO:
2803 p->mdio_port_num = phys_id;
2804 p->mdio_port_mode = logical_id;
2807 case I40E_DEV_FUNC_CAP_IEEE_1588:
2809 p->ieee_1588 = true;
2811 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2813 p->fd_filters_guaranteed = number;
2814 p->fd_filters_best_effort = logical_id;
2821 /* Software override ensuring FCoE is disabled if npar or mfp
2822 * mode because it is not supported in these modes.
2824 if (p->npar_enable || p->mfp_mode_1)
2827 /* additional HW specific goodies that might
2828 * someday be HW version specific
2830 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2834 * i40e_aq_discover_capabilities
2835 * @hw: pointer to the hw struct
2836 * @buff: a virtual buffer to hold the capabilities
2837 * @buff_size: Size of the virtual buffer
2838 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2839 * @list_type_opc: capabilities type to discover - pass in the command opcode
2840 * @cmd_details: pointer to command details structure or NULL
2842 * Get the device capabilities descriptions from the firmware
2844 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2845 void *buff, u16 buff_size, u16 *data_size,
2846 enum i40e_admin_queue_opc list_type_opc,
2847 struct i40e_asq_cmd_details *cmd_details)
2849 struct i40e_aqc_list_capabilites *cmd;
2850 struct i40e_aq_desc desc;
2851 enum i40e_status_code status = I40E_SUCCESS;
2853 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2855 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2856 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2857 status = I40E_ERR_PARAM;
2861 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2863 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2864 if (buff_size > I40E_AQ_LARGE_BUF)
2865 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2867 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2868 *data_size = LE16_TO_CPU(desc.datalen);
2873 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2881 * i40e_aq_update_nvm
2882 * @hw: pointer to the hw struct
2883 * @module_pointer: module pointer location in words from the NVM beginning
2884 * @offset: byte offset from the module beginning
2885 * @length: length of the section to be written (in bytes from the offset)
2886 * @data: command buffer (size [bytes] = length)
2887 * @last_command: tells if this is the last command in a series
2888 * @cmd_details: pointer to command details structure or NULL
2890 * Update the NVM using the admin queue commands
2892 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2893 u32 offset, u16 length, void *data,
2895 struct i40e_asq_cmd_details *cmd_details)
2897 struct i40e_aq_desc desc;
2898 struct i40e_aqc_nvm_update *cmd =
2899 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2900 enum i40e_status_code status;
2902 DEBUGFUNC("i40e_aq_update_nvm");
2904 /* In offset the highest byte must be zeroed. */
2905 if (offset & 0xFF000000) {
2906 status = I40E_ERR_PARAM;
2907 goto i40e_aq_update_nvm_exit;
2910 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2912 /* If this is the last command in a series, set the proper flag. */
2914 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2915 cmd->module_pointer = module_pointer;
2916 cmd->offset = CPU_TO_LE32(offset);
2917 cmd->length = CPU_TO_LE16(length);
2919 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2920 if (length > I40E_AQ_LARGE_BUF)
2921 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2923 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2925 i40e_aq_update_nvm_exit:
2930 * i40e_aq_get_lldp_mib
2931 * @hw: pointer to the hw struct
2932 * @bridge_type: type of bridge requested
2933 * @mib_type: Local, Remote or both Local and Remote MIBs
2934 * @buff: pointer to a user supplied buffer to store the MIB block
2935 * @buff_size: size of the buffer (in bytes)
2936 * @local_len : length of the returned Local LLDP MIB
2937 * @remote_len: length of the returned Remote LLDP MIB
2938 * @cmd_details: pointer to command details structure or NULL
2940 * Requests the complete LLDP MIB (entire packet).
2942 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2943 u8 mib_type, void *buff, u16 buff_size,
2944 u16 *local_len, u16 *remote_len,
2945 struct i40e_asq_cmd_details *cmd_details)
2947 struct i40e_aq_desc desc;
2948 struct i40e_aqc_lldp_get_mib *cmd =
2949 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2950 struct i40e_aqc_lldp_get_mib *resp =
2951 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2952 enum i40e_status_code status;
2954 if (buff_size == 0 || !buff)
2955 return I40E_ERR_PARAM;
2957 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2958 /* Indirect Command */
2959 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2961 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2962 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2963 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2965 desc.datalen = CPU_TO_LE16(buff_size);
2967 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2968 if (buff_size > I40E_AQ_LARGE_BUF)
2969 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2971 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2973 if (local_len != NULL)
2974 *local_len = LE16_TO_CPU(resp->local_len);
2975 if (remote_len != NULL)
2976 *remote_len = LE16_TO_CPU(resp->remote_len);
2983 * i40e_aq_cfg_lldp_mib_change_event
2984 * @hw: pointer to the hw struct
2985 * @enable_update: Enable or Disable event posting
2986 * @cmd_details: pointer to command details structure or NULL
2988 * Enable or Disable posting of an event on ARQ when LLDP MIB
2989 * associated with the interface changes
2991 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2993 struct i40e_asq_cmd_details *cmd_details)
2995 struct i40e_aq_desc desc;
2996 struct i40e_aqc_lldp_update_mib *cmd =
2997 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2998 enum i40e_status_code status;
3000 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3003 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3005 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3011 * i40e_aq_add_lldp_tlv
3012 * @hw: pointer to the hw struct
3013 * @bridge_type: type of bridge
3014 * @buff: buffer with TLV to add
3015 * @buff_size: length of the buffer
3016 * @tlv_len: length of the TLV to be added
3017 * @mib_len: length of the LLDP MIB returned in response
3018 * @cmd_details: pointer to command details structure or NULL
3020 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3021 * it is responsibility of the caller to make sure that the TLV is not
3022 * already present in the LLDPDU.
3023 * In return firmware will write the complete LLDP MIB with the newly
3024 * added TLV in the response buffer.
3026 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3027 void *buff, u16 buff_size, u16 tlv_len,
3029 struct i40e_asq_cmd_details *cmd_details)
3031 struct i40e_aq_desc desc;
3032 struct i40e_aqc_lldp_add_tlv *cmd =
3033 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3034 enum i40e_status_code status;
3036 if (buff_size == 0 || !buff || tlv_len == 0)
3037 return I40E_ERR_PARAM;
3039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3041 /* Indirect Command */
3042 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3043 if (buff_size > I40E_AQ_LARGE_BUF)
3044 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3045 desc.datalen = CPU_TO_LE16(buff_size);
3047 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3048 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3049 cmd->len = CPU_TO_LE16(tlv_len);
3051 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3053 if (mib_len != NULL)
3054 *mib_len = LE16_TO_CPU(desc.datalen);
3061 * i40e_aq_update_lldp_tlv
3062 * @hw: pointer to the hw struct
3063 * @bridge_type: type of bridge
3064 * @buff: buffer with TLV to update
3065 * @buff_size: size of the buffer holding original and updated TLVs
3066 * @old_len: Length of the Original TLV
3067 * @new_len: Length of the Updated TLV
3068 * @offset: offset of the updated TLV in the buff
3069 * @mib_len: length of the returned LLDP MIB
3070 * @cmd_details: pointer to command details structure or NULL
3072 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3073 * Firmware will place the complete LLDP MIB in response buffer with the
3076 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3077 u8 bridge_type, void *buff, u16 buff_size,
3078 u16 old_len, u16 new_len, u16 offset,
3080 struct i40e_asq_cmd_details *cmd_details)
3082 struct i40e_aq_desc desc;
3083 struct i40e_aqc_lldp_update_tlv *cmd =
3084 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3085 enum i40e_status_code status;
3087 if (buff_size == 0 || !buff || offset == 0 ||
3088 old_len == 0 || new_len == 0)
3089 return I40E_ERR_PARAM;
3091 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3093 /* Indirect Command */
3094 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3095 if (buff_size > I40E_AQ_LARGE_BUF)
3096 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3097 desc.datalen = CPU_TO_LE16(buff_size);
3099 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3100 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3101 cmd->old_len = CPU_TO_LE16(old_len);
3102 cmd->new_offset = CPU_TO_LE16(offset);
3103 cmd->new_len = CPU_TO_LE16(new_len);
3105 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3107 if (mib_len != NULL)
3108 *mib_len = LE16_TO_CPU(desc.datalen);
3115 * i40e_aq_delete_lldp_tlv
3116 * @hw: pointer to the hw struct
3117 * @bridge_type: type of bridge
3118 * @buff: pointer to a user supplied buffer that has the TLV
3119 * @buff_size: length of the buffer
3120 * @tlv_len: length of the TLV to be deleted
3121 * @mib_len: length of the returned LLDP MIB
3122 * @cmd_details: pointer to command details structure or NULL
3124 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3125 * The firmware places the entire LLDP MIB in the response buffer.
3127 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3128 u8 bridge_type, void *buff, u16 buff_size,
3129 u16 tlv_len, u16 *mib_len,
3130 struct i40e_asq_cmd_details *cmd_details)
3132 struct i40e_aq_desc desc;
3133 struct i40e_aqc_lldp_add_tlv *cmd =
3134 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3135 enum i40e_status_code status;
3137 if (buff_size == 0 || !buff)
3138 return I40E_ERR_PARAM;
3140 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3142 /* Indirect Command */
3143 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3144 if (buff_size > I40E_AQ_LARGE_BUF)
3145 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3146 desc.datalen = CPU_TO_LE16(buff_size);
3147 cmd->len = CPU_TO_LE16(tlv_len);
3148 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3149 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3151 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3153 if (mib_len != NULL)
3154 *mib_len = LE16_TO_CPU(desc.datalen);
3162 * @hw: pointer to the hw struct
3163 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3164 * @cmd_details: pointer to command details structure or NULL
3166 * Stop or Shutdown the embedded LLDP Agent
3168 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3169 struct i40e_asq_cmd_details *cmd_details)
3171 struct i40e_aq_desc desc;
3172 struct i40e_aqc_lldp_stop *cmd =
3173 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3174 enum i40e_status_code status;
3176 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3179 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3181 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3187 * i40e_aq_start_lldp
3188 * @hw: pointer to the hw struct
3189 * @cmd_details: pointer to command details structure or NULL
3191 * Start the embedded LLDP Agent on all ports.
3193 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3194 struct i40e_asq_cmd_details *cmd_details)
3196 struct i40e_aq_desc desc;
3197 struct i40e_aqc_lldp_start *cmd =
3198 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3199 enum i40e_status_code status;
3201 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3203 cmd->command = I40E_AQ_LLDP_AGENT_START;
3205 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3211 * i40e_aq_get_cee_dcb_config
3212 * @hw: pointer to the hw struct
3213 * @buff: response buffer that stores CEE operational configuration
3214 * @buff_size: size of the buffer passed
3215 * @cmd_details: pointer to command details structure or NULL
3217 * Get CEE DCBX mode operational configuration from firmware
3219 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3220 void *buff, u16 buff_size,
3221 struct i40e_asq_cmd_details *cmd_details)
3223 struct i40e_aq_desc desc;
3224 enum i40e_status_code status;
3226 if (buff_size == 0 || !buff)
3227 return I40E_ERR_PARAM;
3229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3231 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3232 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3239 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3240 * @hw: pointer to the hw struct
3241 * @start_agent: True if DCBx Agent needs to be Started
3242 * False if DCBx Agent needs to be Stopped
3243 * @cmd_details: pointer to command details structure or NULL
3245 * Start/Stop the embedded dcbx Agent
3247 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3249 struct i40e_asq_cmd_details *cmd_details)
3251 struct i40e_aq_desc desc;
3252 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3253 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3255 enum i40e_status_code status;
3257 i40e_fill_default_direct_cmd_desc(&desc,
3258 i40e_aqc_opc_lldp_stop_start_spec_agent);
3261 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3269 * i40e_aq_add_udp_tunnel
3270 * @hw: pointer to the hw struct
3271 * @udp_port: the UDP port to add
3272 * @header_len: length of the tunneling header length in DWords
3273 * @protocol_index: protocol index type
3274 * @filter_index: pointer to filter index
3275 * @cmd_details: pointer to command details structure or NULL
3277 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3278 u16 udp_port, u8 protocol_index,
3280 struct i40e_asq_cmd_details *cmd_details)
3282 struct i40e_aq_desc desc;
3283 struct i40e_aqc_add_udp_tunnel *cmd =
3284 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3285 struct i40e_aqc_del_udp_tunnel_completion *resp =
3286 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3287 enum i40e_status_code status;
3289 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3291 cmd->udp_port = CPU_TO_LE16(udp_port);
3292 cmd->protocol_type = protocol_index;
3294 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3297 *filter_index = resp->index;
3303 * i40e_aq_del_udp_tunnel
3304 * @hw: pointer to the hw struct
3305 * @index: filter index
3306 * @cmd_details: pointer to command details structure or NULL
3308 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3309 struct i40e_asq_cmd_details *cmd_details)
3311 struct i40e_aq_desc desc;
3312 struct i40e_aqc_remove_udp_tunnel *cmd =
3313 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3314 enum i40e_status_code status;
3316 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3320 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3326 * i40e_aq_get_switch_resource_alloc (0x0204)
3327 * @hw: pointer to the hw struct
3328 * @num_entries: pointer to u8 to store the number of resource entries returned
3329 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3330 * to store the resource information for all resource types. Each
3331 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3332 * @count: size, in bytes, of the buffer provided
3333 * @cmd_details: pointer to command details structure or NULL
3335 * Query the resources allocated to a function.
3337 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3339 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3341 struct i40e_asq_cmd_details *cmd_details)
3343 struct i40e_aq_desc desc;
3344 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3345 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3346 enum i40e_status_code status;
3348 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3350 i40e_fill_default_direct_cmd_desc(&desc,
3351 i40e_aqc_opc_get_switch_resource_alloc);
3353 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3354 if (length > I40E_AQ_LARGE_BUF)
3355 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3357 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3360 *num_entries = cmd_resp->num_entries;
3366 * i40e_aq_delete_element - Delete switch element
3367 * @hw: pointer to the hw struct
3368 * @seid: the SEID to delete from the switch
3369 * @cmd_details: pointer to command details structure or NULL
3371 * This deletes a switch element from the switch.
3373 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3374 struct i40e_asq_cmd_details *cmd_details)
3376 struct i40e_aq_desc desc;
3377 struct i40e_aqc_switch_seid *cmd =
3378 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3379 enum i40e_status_code status;
3382 return I40E_ERR_PARAM;
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3386 cmd->seid = CPU_TO_LE16(seid);
3388 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3394 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3395 * @hw: pointer to the hw struct
3396 * @flags: component flags
3397 * @mac_seid: uplink seid (MAC SEID)
3398 * @vsi_seid: connected vsi seid
3399 * @ret_seid: seid of create pv component
3401 * This instantiates an i40e port virtualizer with specified flags.
3402 * Depending on specified flags the port virtualizer can act as a
3403 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3405 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3406 u16 mac_seid, u16 vsi_seid,
3409 struct i40e_aq_desc desc;
3410 struct i40e_aqc_add_update_pv *cmd =
3411 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3412 struct i40e_aqc_add_update_pv_completion *resp =
3413 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3414 enum i40e_status_code status;
3417 return I40E_ERR_PARAM;
3419 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3420 cmd->command_flags = CPU_TO_LE16(flags);
3421 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3422 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3424 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3425 if (!status && ret_seid)
3426 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3432 * i40e_aq_add_tag - Add an S/E-tag
3433 * @hw: pointer to the hw struct
3434 * @direct_to_queue: should s-tag direct flow to a specific queue
3435 * @vsi_seid: VSI SEID to use this tag
3436 * @tag: value of the tag
3437 * @queue_num: queue number, only valid is direct_to_queue is true
3438 * @tags_used: return value, number of tags in use by this PF
3439 * @tags_free: return value, number of unallocated tags
3440 * @cmd_details: pointer to command details structure or NULL
3442 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3443 * the number of tags allocated by the PF, and the number of unallocated
3446 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3447 u16 vsi_seid, u16 tag, u16 queue_num,
3448 u16 *tags_used, u16 *tags_free,
3449 struct i40e_asq_cmd_details *cmd_details)
3451 struct i40e_aq_desc desc;
3452 struct i40e_aqc_add_tag *cmd =
3453 (struct i40e_aqc_add_tag *)&desc.params.raw;
3454 struct i40e_aqc_add_remove_tag_completion *resp =
3455 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3456 enum i40e_status_code status;
3459 return I40E_ERR_PARAM;
3461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3463 cmd->seid = CPU_TO_LE16(vsi_seid);
3464 cmd->tag = CPU_TO_LE16(tag);
3465 if (direct_to_queue) {
3466 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3467 cmd->queue_number = CPU_TO_LE16(queue_num);
3470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3473 if (tags_used != NULL)
3474 *tags_used = LE16_TO_CPU(resp->tags_used);
3475 if (tags_free != NULL)
3476 *tags_free = LE16_TO_CPU(resp->tags_free);
3483 * i40e_aq_remove_tag - Remove an S- or E-tag
3484 * @hw: pointer to the hw struct
3485 * @vsi_seid: VSI SEID this tag is associated with
3486 * @tag: value of the S-tag to delete
3487 * @tags_used: return value, number of tags in use by this PF
3488 * @tags_free: return value, number of unallocated tags
3489 * @cmd_details: pointer to command details structure or NULL
3491 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3492 * the number of tags allocated by the PF, and the number of unallocated
3495 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3496 u16 tag, u16 *tags_used, u16 *tags_free,
3497 struct i40e_asq_cmd_details *cmd_details)
3499 struct i40e_aq_desc desc;
3500 struct i40e_aqc_remove_tag *cmd =
3501 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3502 struct i40e_aqc_add_remove_tag_completion *resp =
3503 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3504 enum i40e_status_code status;
3507 return I40E_ERR_PARAM;
3509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3511 cmd->seid = CPU_TO_LE16(vsi_seid);
3512 cmd->tag = CPU_TO_LE16(tag);
3514 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3517 if (tags_used != NULL)
3518 *tags_used = LE16_TO_CPU(resp->tags_used);
3519 if (tags_free != NULL)
3520 *tags_free = LE16_TO_CPU(resp->tags_free);
3527 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3528 * @hw: pointer to the hw struct
3529 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3530 * @etag: value of E-tag to add
3531 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3532 * @buf: address of indirect buffer
3533 * @tags_used: return value, number of E-tags in use by this port
3534 * @tags_free: return value, number of unallocated M-tags
3535 * @cmd_details: pointer to command details structure or NULL
3537 * This associates a multicast E-tag to a port virtualizer. It will return
3538 * the number of tags allocated by the PF, and the number of unallocated
3541 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3542 * num_tags_in_buf long.
3544 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3545 u16 etag, u8 num_tags_in_buf, void *buf,
3546 u16 *tags_used, u16 *tags_free,
3547 struct i40e_asq_cmd_details *cmd_details)
3549 struct i40e_aq_desc desc;
3550 struct i40e_aqc_add_remove_mcast_etag *cmd =
3551 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3552 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3553 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3554 enum i40e_status_code status;
3555 u16 length = sizeof(u16) * num_tags_in_buf;
3557 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3558 return I40E_ERR_PARAM;
3560 i40e_fill_default_direct_cmd_desc(&desc,
3561 i40e_aqc_opc_add_multicast_etag);
3563 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3564 cmd->etag = CPU_TO_LE16(etag);
3565 cmd->num_unicast_etags = num_tags_in_buf;
3567 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3568 if (length > I40E_AQ_LARGE_BUF)
3569 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3571 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3574 if (tags_used != NULL)
3575 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3576 if (tags_free != NULL)
3577 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3584 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3585 * @hw: pointer to the hw struct
3586 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3587 * @etag: value of the E-tag to remove
3588 * @tags_used: return value, number of tags in use by this port
3589 * @tags_free: return value, number of unallocated tags
3590 * @cmd_details: pointer to command details structure or NULL
3592 * This deletes an E-tag from the port virtualizer. It will return
3593 * the number of tags allocated by the port, and the number of unallocated
3596 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3597 u16 etag, u16 *tags_used, u16 *tags_free,
3598 struct i40e_asq_cmd_details *cmd_details)
3600 struct i40e_aq_desc desc;
3601 struct i40e_aqc_add_remove_mcast_etag *cmd =
3602 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3603 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3604 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3605 enum i40e_status_code status;
3609 return I40E_ERR_PARAM;
3611 i40e_fill_default_direct_cmd_desc(&desc,
3612 i40e_aqc_opc_remove_multicast_etag);
3614 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3615 cmd->etag = CPU_TO_LE16(etag);
3617 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3620 if (tags_used != NULL)
3621 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3622 if (tags_free != NULL)
3623 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3630 * i40e_aq_update_tag - Update an S/E-tag
3631 * @hw: pointer to the hw struct
3632 * @vsi_seid: VSI SEID using this S-tag
3633 * @old_tag: old tag value
3634 * @new_tag: new tag value
3635 * @tags_used: return value, number of tags in use by this PF
3636 * @tags_free: return value, number of unallocated tags
3637 * @cmd_details: pointer to command details structure or NULL
3639 * This updates the value of the tag currently attached to this VSI
3640 * in the switch complex. It will return the number of tags allocated
3641 * by the PF, and the number of unallocated tags available.
3643 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3644 u16 old_tag, u16 new_tag, u16 *tags_used,
3646 struct i40e_asq_cmd_details *cmd_details)
3648 struct i40e_aq_desc desc;
3649 struct i40e_aqc_update_tag *cmd =
3650 (struct i40e_aqc_update_tag *)&desc.params.raw;
3651 struct i40e_aqc_update_tag_completion *resp =
3652 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3653 enum i40e_status_code status;
3656 return I40E_ERR_PARAM;
3658 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3660 cmd->seid = CPU_TO_LE16(vsi_seid);
3661 cmd->old_tag = CPU_TO_LE16(old_tag);
3662 cmd->new_tag = CPU_TO_LE16(new_tag);
3664 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3667 if (tags_used != NULL)
3668 *tags_used = LE16_TO_CPU(resp->tags_used);
3669 if (tags_free != NULL)
3670 *tags_free = LE16_TO_CPU(resp->tags_free);
3677 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3678 * @hw: pointer to the hw struct
3679 * @tcmap: TC map for request/release any ignore PFC condition
3680 * @request: request or release ignore PFC condition
3681 * @tcmap_ret: return TCs for which PFC is currently ignored
3682 * @cmd_details: pointer to command details structure or NULL
3684 * This sends out request/release to ignore PFC condition for a TC.
3685 * It will return the TCs for which PFC is currently ignored.
3687 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3688 bool request, u8 *tcmap_ret,
3689 struct i40e_asq_cmd_details *cmd_details)
3691 struct i40e_aq_desc desc;
3692 struct i40e_aqc_pfc_ignore *cmd_resp =
3693 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3694 enum i40e_status_code status;
3696 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3699 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3701 cmd_resp->tc_bitmap = tcmap;
3703 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3706 if (tcmap_ret != NULL)
3707 *tcmap_ret = cmd_resp->tc_bitmap;
3714 * i40e_aq_dcb_updated - DCB Updated Command
3715 * @hw: pointer to the hw struct
3716 * @cmd_details: pointer to command details structure or NULL
3718 * When LLDP is handled in PF this command is used by the PF
3719 * to notify EMP that a DCB setting is modified.
3720 * When LLDP is handled in EMP this command is used by the PF
3721 * to notify EMP whenever one of the following parameters get
3723 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3724 * - PCIRTT in PRTDCB_GENC.PCIRTT
3725 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3726 * EMP will return when the shared RPB settings have been
3727 * recomputed and modified. The retval field in the descriptor
3728 * will be set to 0 when RPB is modified.
3730 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3731 struct i40e_asq_cmd_details *cmd_details)
3733 struct i40e_aq_desc desc;
3734 enum i40e_status_code status;
3736 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3744 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3745 * @hw: pointer to the hw struct
3746 * @seid: defines the SEID of the switch for which the stats are requested
3747 * @vlan_id: the VLAN ID for which the statistics are requested
3748 * @stat_index: index of the statistics counters block assigned to this VLAN
3749 * @cmd_details: pointer to command details structure or NULL
3751 * XL710 supports 128 smonVlanStats counters.This command is used to
3752 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3755 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3756 u16 vlan_id, u16 *stat_index,
3757 struct i40e_asq_cmd_details *cmd_details)
3759 struct i40e_aq_desc desc;
3760 struct i40e_aqc_add_remove_statistics *cmd_resp =
3761 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3762 enum i40e_status_code status;
3764 if ((seid == 0) || (stat_index == NULL))
3765 return I40E_ERR_PARAM;
3767 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3769 cmd_resp->seid = CPU_TO_LE16(seid);
3770 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3775 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3781 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3782 * @hw: pointer to the hw struct
3783 * @seid: defines the SEID of the switch for which the stats are requested
3784 * @vlan_id: the VLAN ID for which the statistics are requested
3785 * @stat_index: index of the statistics counters block assigned to this VLAN
3786 * @cmd_details: pointer to command details structure or NULL
3788 * XL710 supports 128 smonVlanStats counters.This command is used to
3789 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3792 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3793 u16 vlan_id, u16 stat_index,
3794 struct i40e_asq_cmd_details *cmd_details)
3796 struct i40e_aq_desc desc;
3797 struct i40e_aqc_add_remove_statistics *cmd =
3798 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3799 enum i40e_status_code status;
3802 return I40E_ERR_PARAM;
3804 i40e_fill_default_direct_cmd_desc(&desc,
3805 i40e_aqc_opc_remove_statistics);
3807 cmd->seid = CPU_TO_LE16(seid);
3808 cmd->vlan = CPU_TO_LE16(vlan_id);
3809 cmd->stat_index = CPU_TO_LE16(stat_index);
3811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3817 * i40e_aq_set_port_parameters - set physical port parameters.
3818 * @hw: pointer to the hw struct
3819 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3820 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3821 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3822 * @double_vlan: if set double VLAN is enabled
3823 * @cmd_details: pointer to command details structure or NULL
3825 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3826 u16 bad_frame_vsi, bool save_bad_pac,
3827 bool pad_short_pac, bool double_vlan,
3828 struct i40e_asq_cmd_details *cmd_details)
3830 struct i40e_aqc_set_port_parameters *cmd;
3831 enum i40e_status_code status;
3832 struct i40e_aq_desc desc;
3833 u16 command_flags = 0;
3835 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3837 i40e_fill_default_direct_cmd_desc(&desc,
3838 i40e_aqc_opc_set_port_parameters);
3840 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3842 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3844 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3846 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3847 cmd->command_flags = CPU_TO_LE16(command_flags);
3849 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3855 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3856 * @hw: pointer to the hw struct
3857 * @seid: seid for the physical port/switching component/vsi
3858 * @buff: Indirect buffer to hold data parameters and response
3859 * @buff_size: Indirect buffer size
3860 * @opcode: Tx scheduler AQ command opcode
3861 * @cmd_details: pointer to command details structure or NULL
3863 * Generic command handler for Tx scheduler AQ commands
3865 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3866 void *buff, u16 buff_size,
3867 enum i40e_admin_queue_opc opcode,
3868 struct i40e_asq_cmd_details *cmd_details)
3870 struct i40e_aq_desc desc;
3871 struct i40e_aqc_tx_sched_ind *cmd =
3872 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3873 enum i40e_status_code status;
3874 bool cmd_param_flag = false;
3877 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3878 case i40e_aqc_opc_configure_vsi_tc_bw:
3879 case i40e_aqc_opc_enable_switching_comp_ets:
3880 case i40e_aqc_opc_modify_switching_comp_ets:
3881 case i40e_aqc_opc_disable_switching_comp_ets:
3882 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3883 case i40e_aqc_opc_configure_switching_comp_bw_config:
3884 cmd_param_flag = true;
3886 case i40e_aqc_opc_query_vsi_bw_config:
3887 case i40e_aqc_opc_query_vsi_ets_sla_config:
3888 case i40e_aqc_opc_query_switching_comp_ets_config:
3889 case i40e_aqc_opc_query_port_ets_config:
3890 case i40e_aqc_opc_query_switching_comp_bw_config:
3891 cmd_param_flag = false;
3894 return I40E_ERR_PARAM;
3897 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3899 /* Indirect command */
3900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3902 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3903 if (buff_size > I40E_AQ_LARGE_BUF)
3904 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3906 desc.datalen = CPU_TO_LE16(buff_size);
3908 cmd->vsi_seid = CPU_TO_LE16(seid);
3910 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3916 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3917 * @hw: pointer to the hw struct
3919 * @credit: BW limit credits (0 = disabled)
3920 * @max_credit: Max BW limit credits
3921 * @cmd_details: pointer to command details structure or NULL
3923 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3924 u16 seid, u16 credit, u8 max_credit,
3925 struct i40e_asq_cmd_details *cmd_details)
3927 struct i40e_aq_desc desc;
3928 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3929 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3930 enum i40e_status_code status;
3932 i40e_fill_default_direct_cmd_desc(&desc,
3933 i40e_aqc_opc_configure_vsi_bw_limit);
3935 cmd->vsi_seid = CPU_TO_LE16(seid);
3936 cmd->credit = CPU_TO_LE16(credit);
3937 cmd->max_credit = max_credit;
3939 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3945 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3946 * @hw: pointer to the hw struct
3947 * @seid: switching component seid
3948 * @credit: BW limit credits (0 = disabled)
3949 * @max_bw: Max BW limit credits
3950 * @cmd_details: pointer to command details structure or NULL
3952 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3953 u16 seid, u16 credit, u8 max_bw,
3954 struct i40e_asq_cmd_details *cmd_details)
3956 struct i40e_aq_desc desc;
3957 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3958 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3959 enum i40e_status_code status;
3961 i40e_fill_default_direct_cmd_desc(&desc,
3962 i40e_aqc_opc_configure_switching_comp_bw_limit);
3964 cmd->seid = CPU_TO_LE16(seid);
3965 cmd->credit = CPU_TO_LE16(credit);
3966 cmd->max_bw = max_bw;
3968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3974 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3975 * @hw: pointer to the hw struct
3977 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3978 * @cmd_details: pointer to command details structure or NULL
3980 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3982 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3983 struct i40e_asq_cmd_details *cmd_details)
3985 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3986 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3991 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3992 * @hw: pointer to the hw struct
3994 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3995 * @cmd_details: pointer to command details structure or NULL
3997 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3999 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4000 struct i40e_asq_cmd_details *cmd_details)
4002 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4003 i40e_aqc_opc_configure_vsi_tc_bw,
4008 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4009 * @hw: pointer to the hw struct
4010 * @seid: seid of the switching component
4011 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4012 * @cmd_details: pointer to command details structure or NULL
4014 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4015 struct i40e_hw *hw, u16 seid,
4016 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4017 struct i40e_asq_cmd_details *cmd_details)
4019 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4020 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4025 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4026 * @hw: pointer to the hw struct
4027 * @seid: seid of the VSI
4028 * @bw_data: Buffer to hold VSI BW configuration
4029 * @cmd_details: pointer to command details structure or NULL
4031 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4033 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4034 struct i40e_asq_cmd_details *cmd_details)
4036 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4037 i40e_aqc_opc_query_vsi_bw_config,
4042 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4043 * @hw: pointer to the hw struct
4044 * @seid: seid of the VSI
4045 * @bw_data: Buffer to hold VSI BW configuration per TC
4046 * @cmd_details: pointer to command details structure or NULL
4048 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4050 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4051 struct i40e_asq_cmd_details *cmd_details)
4053 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4054 i40e_aqc_opc_query_vsi_ets_sla_config,
4059 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4060 * @hw: pointer to the hw struct
4061 * @seid: seid of the switching component
4062 * @bw_data: Buffer to hold switching component's per TC BW config
4063 * @cmd_details: pointer to command details structure or NULL
4065 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4067 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4068 struct i40e_asq_cmd_details *cmd_details)
4070 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4071 i40e_aqc_opc_query_switching_comp_ets_config,
4076 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4077 * @hw: pointer to the hw struct
4078 * @seid: seid of the VSI or switching component connected to Physical Port
4079 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4080 * @cmd_details: pointer to command details structure or NULL
4082 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4084 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4085 struct i40e_asq_cmd_details *cmd_details)
4087 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4088 i40e_aqc_opc_query_port_ets_config,
4093 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4094 * @hw: pointer to the hw struct
4095 * @seid: seid of the switching component
4096 * @bw_data: Buffer to hold switching component's BW configuration
4097 * @cmd_details: pointer to command details structure or NULL
4099 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4101 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4102 struct i40e_asq_cmd_details *cmd_details)
4104 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4105 i40e_aqc_opc_query_switching_comp_bw_config,
4110 * i40e_validate_filter_settings
4111 * @hw: pointer to the hardware structure
4112 * @settings: Filter control settings
4114 * Check and validate the filter control settings passed.
4115 * The function checks for the valid filter/context sizes being
4116 * passed for FCoE and PE.
4118 * Returns I40E_SUCCESS if the values passed are valid and within
4119 * range else returns an error.
4121 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4122 struct i40e_filter_control_settings *settings)
4124 u32 fcoe_cntx_size, fcoe_filt_size;
4125 u32 pe_cntx_size, pe_filt_size;
4130 /* Validate FCoE settings passed */
4131 switch (settings->fcoe_filt_num) {
4132 case I40E_HASH_FILTER_SIZE_1K:
4133 case I40E_HASH_FILTER_SIZE_2K:
4134 case I40E_HASH_FILTER_SIZE_4K:
4135 case I40E_HASH_FILTER_SIZE_8K:
4136 case I40E_HASH_FILTER_SIZE_16K:
4137 case I40E_HASH_FILTER_SIZE_32K:
4138 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4139 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4142 return I40E_ERR_PARAM;
4145 switch (settings->fcoe_cntx_num) {
4146 case I40E_DMA_CNTX_SIZE_512:
4147 case I40E_DMA_CNTX_SIZE_1K:
4148 case I40E_DMA_CNTX_SIZE_2K:
4149 case I40E_DMA_CNTX_SIZE_4K:
4150 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4151 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4154 return I40E_ERR_PARAM;
4157 /* Validate PE settings passed */
4158 switch (settings->pe_filt_num) {
4159 case I40E_HASH_FILTER_SIZE_1K:
4160 case I40E_HASH_FILTER_SIZE_2K:
4161 case I40E_HASH_FILTER_SIZE_4K:
4162 case I40E_HASH_FILTER_SIZE_8K:
4163 case I40E_HASH_FILTER_SIZE_16K:
4164 case I40E_HASH_FILTER_SIZE_32K:
4165 case I40E_HASH_FILTER_SIZE_64K:
4166 case I40E_HASH_FILTER_SIZE_128K:
4167 case I40E_HASH_FILTER_SIZE_256K:
4168 case I40E_HASH_FILTER_SIZE_512K:
4169 case I40E_HASH_FILTER_SIZE_1M:
4170 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4171 pe_filt_size <<= (u32)settings->pe_filt_num;
4174 return I40E_ERR_PARAM;
4177 switch (settings->pe_cntx_num) {
4178 case I40E_DMA_CNTX_SIZE_512:
4179 case I40E_DMA_CNTX_SIZE_1K:
4180 case I40E_DMA_CNTX_SIZE_2K:
4181 case I40E_DMA_CNTX_SIZE_4K:
4182 case I40E_DMA_CNTX_SIZE_8K:
4183 case I40E_DMA_CNTX_SIZE_16K:
4184 case I40E_DMA_CNTX_SIZE_32K:
4185 case I40E_DMA_CNTX_SIZE_64K:
4186 case I40E_DMA_CNTX_SIZE_128K:
4187 case I40E_DMA_CNTX_SIZE_256K:
4188 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4189 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4192 return I40E_ERR_PARAM;
4195 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4196 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4197 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4198 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4199 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4200 return I40E_ERR_INVALID_SIZE;
4202 return I40E_SUCCESS;
4206 * i40e_set_filter_control
4207 * @hw: pointer to the hardware structure
4208 * @settings: Filter control settings
4210 * Set the Queue Filters for PE/FCoE and enable filters required
4211 * for a single PF. It is expected that these settings are programmed
4212 * at the driver initialization time.
4214 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4215 struct i40e_filter_control_settings *settings)
4217 enum i40e_status_code ret = I40E_SUCCESS;
4218 u32 hash_lut_size = 0;
4222 return I40E_ERR_PARAM;
4224 /* Validate the input settings */
4225 ret = i40e_validate_filter_settings(hw, settings);
4229 /* Read the PF Queue Filter control register */
4230 val = rd32(hw, I40E_PFQF_CTL_0);
4232 /* Program required PE hash buckets for the PF */
4233 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4234 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4235 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4236 /* Program required PE contexts for the PF */
4237 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4238 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4239 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4241 /* Program required FCoE hash buckets for the PF */
4242 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4243 val |= ((u32)settings->fcoe_filt_num <<
4244 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4245 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4246 /* Program required FCoE DDP contexts for the PF */
4247 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4248 val |= ((u32)settings->fcoe_cntx_num <<
4249 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4250 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4252 /* Program Hash LUT size for the PF */
4253 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4254 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4256 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4257 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4259 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4260 if (settings->enable_fdir)
4261 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4262 if (settings->enable_ethtype)
4263 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4264 if (settings->enable_macvlan)
4265 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4267 wr32(hw, I40E_PFQF_CTL_0, val);
4269 return I40E_SUCCESS;
4273 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4274 * @hw: pointer to the hw struct
4275 * @mac_addr: MAC address to use in the filter
4276 * @ethtype: Ethertype to use in the filter
4277 * @flags: Flags that needs to be applied to the filter
4278 * @vsi_seid: seid of the control VSI
4279 * @queue: VSI queue number to send the packet to
4280 * @is_add: Add control packet filter if True else remove
4281 * @stats: Structure to hold information on control filter counts
4282 * @cmd_details: pointer to command details structure or NULL
4284 * This command will Add or Remove control packet filter for a control VSI.
4285 * In return it will update the total number of perfect filter count in
4288 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4289 u8 *mac_addr, u16 ethtype, u16 flags,
4290 u16 vsi_seid, u16 queue, bool is_add,
4291 struct i40e_control_filter_stats *stats,
4292 struct i40e_asq_cmd_details *cmd_details)
4294 struct i40e_aq_desc desc;
4295 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4296 (struct i40e_aqc_add_remove_control_packet_filter *)
4298 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4299 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4301 enum i40e_status_code status;
4304 return I40E_ERR_PARAM;
4307 i40e_fill_default_direct_cmd_desc(&desc,
4308 i40e_aqc_opc_add_control_packet_filter);
4309 cmd->queue = CPU_TO_LE16(queue);
4311 i40e_fill_default_direct_cmd_desc(&desc,
4312 i40e_aqc_opc_remove_control_packet_filter);
4316 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4317 I40E_NONDMA_TO_NONDMA);
4319 cmd->etype = CPU_TO_LE16(ethtype);
4320 cmd->flags = CPU_TO_LE16(flags);
4321 cmd->seid = CPU_TO_LE16(vsi_seid);
4323 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4325 if (!status && stats) {
4326 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4327 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4328 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4329 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4336 * i40e_aq_add_cloud_filters
4337 * @hw: pointer to the hardware structure
4338 * @seid: VSI seid to add cloud filters from
4339 * @filters: Buffer which contains the filters to be added
4340 * @filter_count: number of filters contained in the buffer
4342 * Set the cloud filters for a given VSI. The contents of the
4343 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4344 * in by the caller of the function.
4347 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4349 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4352 struct i40e_aq_desc desc;
4353 struct i40e_aqc_add_remove_cloud_filters *cmd =
4354 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4356 enum i40e_status_code status;
4358 i40e_fill_default_direct_cmd_desc(&desc,
4359 i40e_aqc_opc_add_cloud_filters);
4361 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4363 desc.datalen = CPU_TO_LE16(buff_len);
4364 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4365 cmd->num_filters = filter_count;
4366 cmd->seid = CPU_TO_LE16(seid);
4368 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4374 * i40e_aq_remove_cloud_filters
4375 * @hw: pointer to the hardware structure
4376 * @seid: VSI seid to remove cloud filters from
4377 * @filters: Buffer which contains the filters to be removed
4378 * @filter_count: number of filters contained in the buffer
4380 * Remove the cloud filters for a given VSI. The contents of the
4381 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4382 * in by the caller of the function.
4385 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4387 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4390 struct i40e_aq_desc desc;
4391 struct i40e_aqc_add_remove_cloud_filters *cmd =
4392 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4393 enum i40e_status_code status;
4396 i40e_fill_default_direct_cmd_desc(&desc,
4397 i40e_aqc_opc_remove_cloud_filters);
4399 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4401 desc.datalen = CPU_TO_LE16(buff_len);
4402 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4403 cmd->num_filters = filter_count;
4404 cmd->seid = CPU_TO_LE16(seid);
4406 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4412 * i40e_aq_alternate_write
4413 * @hw: pointer to the hardware structure
4414 * @reg_addr0: address of first dword to be read
4415 * @reg_val0: value to be written under 'reg_addr0'
4416 * @reg_addr1: address of second dword to be read
4417 * @reg_val1: value to be written under 'reg_addr1'
4419 * Write one or two dwords to alternate structure. Fields are indicated
4420 * by 'reg_addr0' and 'reg_addr1' register numbers.
4423 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4424 u32 reg_addr0, u32 reg_val0,
4425 u32 reg_addr1, u32 reg_val1)
4427 struct i40e_aq_desc desc;
4428 struct i40e_aqc_alternate_write *cmd_resp =
4429 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4430 enum i40e_status_code status;
4432 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4433 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4434 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4435 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4436 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4438 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4444 * i40e_aq_alternate_write_indirect
4445 * @hw: pointer to the hardware structure
4446 * @addr: address of a first register to be modified
4447 * @dw_count: number of alternate structure fields to write
4448 * @buffer: pointer to the command buffer
4450 * Write 'dw_count' dwords from 'buffer' to alternate structure
4451 * starting at 'addr'.
4454 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4455 u32 addr, u32 dw_count, void *buffer)
4457 struct i40e_aq_desc desc;
4458 struct i40e_aqc_alternate_ind_write *cmd_resp =
4459 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4460 enum i40e_status_code status;
4463 return I40E_ERR_PARAM;
4465 /* Indirect command */
4466 i40e_fill_default_direct_cmd_desc(&desc,
4467 i40e_aqc_opc_alternate_write_indirect);
4469 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4470 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4471 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4472 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4474 cmd_resp->address = CPU_TO_LE32(addr);
4475 cmd_resp->length = CPU_TO_LE32(dw_count);
4476 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4477 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4479 status = i40e_asq_send_command(hw, &desc, buffer,
4480 I40E_LO_DWORD(4*dw_count), NULL);
4486 * i40e_aq_alternate_read
4487 * @hw: pointer to the hardware structure
4488 * @reg_addr0: address of first dword to be read
4489 * @reg_val0: pointer for data read from 'reg_addr0'
4490 * @reg_addr1: address of second dword to be read
4491 * @reg_val1: pointer for data read from 'reg_addr1'
4493 * Read one or two dwords from alternate structure. Fields are indicated
4494 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4495 * is not passed then only register at 'reg_addr0' is read.
4498 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4499 u32 reg_addr0, u32 *reg_val0,
4500 u32 reg_addr1, u32 *reg_val1)
4502 struct i40e_aq_desc desc;
4503 struct i40e_aqc_alternate_write *cmd_resp =
4504 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4505 enum i40e_status_code status;
4507 if (reg_val0 == NULL)
4508 return I40E_ERR_PARAM;
4510 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4511 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4512 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4514 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4516 if (status == I40E_SUCCESS) {
4517 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4519 if (reg_val1 != NULL)
4520 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4527 * i40e_aq_alternate_read_indirect
4528 * @hw: pointer to the hardware structure
4529 * @addr: address of the alternate structure field
4530 * @dw_count: number of alternate structure fields to read
4531 * @buffer: pointer to the command buffer
4533 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4534 * place them in 'buffer'. The buffer should be allocated by caller.
4537 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4538 u32 addr, u32 dw_count, void *buffer)
4540 struct i40e_aq_desc desc;
4541 struct i40e_aqc_alternate_ind_write *cmd_resp =
4542 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4543 enum i40e_status_code status;
4546 return I40E_ERR_PARAM;
4548 /* Indirect command */
4549 i40e_fill_default_direct_cmd_desc(&desc,
4550 i40e_aqc_opc_alternate_read_indirect);
4552 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4553 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4554 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4555 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4557 cmd_resp->address = CPU_TO_LE32(addr);
4558 cmd_resp->length = CPU_TO_LE32(dw_count);
4559 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4560 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4562 status = i40e_asq_send_command(hw, &desc, buffer,
4563 I40E_LO_DWORD(4*dw_count), NULL);
4569 * i40e_aq_alternate_clear
4570 * @hw: pointer to the HW structure.
4572 * Clear the alternate structures of the port from which the function
4576 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4578 struct i40e_aq_desc desc;
4579 enum i40e_status_code status;
4581 i40e_fill_default_direct_cmd_desc(&desc,
4582 i40e_aqc_opc_alternate_clear_port);
4584 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4590 * i40e_aq_alternate_write_done
4591 * @hw: pointer to the HW structure.
4592 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4593 * @reset_needed: indicates the SW should trigger GLOBAL reset
4595 * Indicates to the FW that alternate structures have been changed.
4598 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4599 u8 bios_mode, bool *reset_needed)
4601 struct i40e_aq_desc desc;
4602 struct i40e_aqc_alternate_write_done *cmd =
4603 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4604 enum i40e_status_code status;
4606 if (reset_needed == NULL)
4607 return I40E_ERR_PARAM;
4609 i40e_fill_default_direct_cmd_desc(&desc,
4610 i40e_aqc_opc_alternate_write_done);
4612 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4614 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4616 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4617 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4623 * i40e_aq_set_oem_mode
4624 * @hw: pointer to the HW structure.
4625 * @oem_mode: the OEM mode to be used
4627 * Sets the device to a specific operating mode. Currently the only supported
4628 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4631 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4634 struct i40e_aq_desc desc;
4635 struct i40e_aqc_alternate_write_done *cmd =
4636 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4637 enum i40e_status_code status;
4639 i40e_fill_default_direct_cmd_desc(&desc,
4640 i40e_aqc_opc_alternate_set_mode);
4642 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4644 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4650 * i40e_aq_resume_port_tx
4651 * @hw: pointer to the hardware structure
4652 * @cmd_details: pointer to command details structure or NULL
4654 * Resume port's Tx traffic
4656 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4657 struct i40e_asq_cmd_details *cmd_details)
4659 struct i40e_aq_desc desc;
4660 enum i40e_status_code status;
4662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4664 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4670 * i40e_set_pci_config_data - store PCI bus info
4671 * @hw: pointer to hardware structure
4672 * @link_status: the link status word from PCI config space
4674 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4676 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4678 hw->bus.type = i40e_bus_type_pci_express;
4680 switch (link_status & I40E_PCI_LINK_WIDTH) {
4681 case I40E_PCI_LINK_WIDTH_1:
4682 hw->bus.width = i40e_bus_width_pcie_x1;
4684 case I40E_PCI_LINK_WIDTH_2:
4685 hw->bus.width = i40e_bus_width_pcie_x2;
4687 case I40E_PCI_LINK_WIDTH_4:
4688 hw->bus.width = i40e_bus_width_pcie_x4;
4690 case I40E_PCI_LINK_WIDTH_8:
4691 hw->bus.width = i40e_bus_width_pcie_x8;
4694 hw->bus.width = i40e_bus_width_unknown;
4698 switch (link_status & I40E_PCI_LINK_SPEED) {
4699 case I40E_PCI_LINK_SPEED_2500:
4700 hw->bus.speed = i40e_bus_speed_2500;
4702 case I40E_PCI_LINK_SPEED_5000:
4703 hw->bus.speed = i40e_bus_speed_5000;
4705 case I40E_PCI_LINK_SPEED_8000:
4706 hw->bus.speed = i40e_bus_speed_8000;
4709 hw->bus.speed = i40e_bus_speed_unknown;
4715 * i40e_read_bw_from_alt_ram
4716 * @hw: pointer to the hardware structure
4717 * @max_bw: pointer for max_bw read
4718 * @min_bw: pointer for min_bw read
4719 * @min_valid: pointer for bool that is true if min_bw is a valid value
4720 * @max_valid: pointer for bool that is true if max_bw is a valid value
4722 * Read bw from the alternate ram for the given pf
4724 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4725 u32 *max_bw, u32 *min_bw,
4726 bool *min_valid, bool *max_valid)
4728 enum i40e_status_code status;
4729 u32 max_bw_addr, min_bw_addr;
4731 /* Calculate the address of the min/max bw registers */
4732 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4733 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4734 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4735 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4736 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4737 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4739 /* Read the bandwidths from alt ram */
4740 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4741 min_bw_addr, min_bw);
4743 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4748 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4757 * i40e_aq_configure_partition_bw
4758 * @hw: pointer to the hardware structure
4759 * @bw_data: Buffer holding valid pfs and bw limits
4760 * @cmd_details: pointer to command details
4762 * Configure partitions guaranteed/max bw
4764 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4765 struct i40e_aqc_configure_partition_bw_data *bw_data,
4766 struct i40e_asq_cmd_details *cmd_details)
4768 enum i40e_status_code status;
4769 struct i40e_aq_desc desc;
4770 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4772 i40e_fill_default_direct_cmd_desc(&desc,
4773 i40e_aqc_opc_configure_partition_bw);
4775 /* Indirect command */
4776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4779 if (bwd_size > I40E_AQ_LARGE_BUF)
4780 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4782 desc.datalen = CPU_TO_LE16(bwd_size);
4784 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4788 #endif /* PF_DRIVER */
4792 * i40e_aq_send_msg_to_pf
4793 * @hw: pointer to the hardware structure
4794 * @v_opcode: opcodes for VF-PF communication
4795 * @v_retval: return error code
4796 * @msg: pointer to the msg buffer
4797 * @msglen: msg length
4798 * @cmd_details: pointer to command details
4800 * Send message to PF driver using admin queue. By default, this message
4801 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4802 * completion before returning.
4804 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4805 enum i40e_virtchnl_ops v_opcode,
4806 enum i40e_status_code v_retval,
4807 u8 *msg, u16 msglen,
4808 struct i40e_asq_cmd_details *cmd_details)
4810 struct i40e_aq_desc desc;
4811 struct i40e_asq_cmd_details details;
4812 enum i40e_status_code status;
4814 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4815 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4816 desc.cookie_high = CPU_TO_LE32(v_opcode);
4817 desc.cookie_low = CPU_TO_LE32(v_retval);
4819 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4820 | I40E_AQ_FLAG_RD));
4821 if (msglen > I40E_AQ_LARGE_BUF)
4822 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4823 desc.datalen = CPU_TO_LE16(msglen);
4826 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4827 details.async = true;
4828 cmd_details = &details;
4830 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4831 msglen, cmd_details);
4836 * i40e_vf_parse_hw_config
4837 * @hw: pointer to the hardware structure
4838 * @msg: pointer to the virtual channel VF resource structure
4840 * Given a VF resource message from the PF, populate the hw struct
4841 * with appropriate information.
4843 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4844 struct i40e_virtchnl_vf_resource *msg)
4846 struct i40e_virtchnl_vsi_resource *vsi_res;
4849 vsi_res = &msg->vsi_res[0];
4851 hw->dev_caps.num_vsis = msg->num_vsis;
4852 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4853 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4854 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4855 hw->dev_caps.dcb = msg->vf_offload_flags &
4856 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4857 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4858 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4859 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4860 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4861 for (i = 0; i < msg->num_vsis; i++) {
4862 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4863 i40e_memcpy(hw->mac.perm_addr,
4864 vsi_res->default_mac_addr,
4865 I40E_ETH_LENGTH_OF_ADDRESS,
4866 I40E_NONDMA_TO_NONDMA);
4867 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4868 I40E_ETH_LENGTH_OF_ADDRESS,
4869 I40E_NONDMA_TO_NONDMA);
4877 * @hw: pointer to the hardware structure
4879 * Send a VF_RESET message to the PF. Does not wait for response from PF
4880 * as none will be forthcoming. Immediately after calling this function,
4881 * the admin queue should be shut down and (optionally) reinitialized.
4883 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4885 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4886 I40E_SUCCESS, NULL, 0, NULL);
4888 #endif /* VF_DRIVER */