1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *buf = (u8 *)buffer;
104 if ((!(mask & hw->debug_mask)) || (desc == NULL))
108 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
109 LE16_TO_CPU(aq_desc->opcode),
110 LE16_TO_CPU(aq_desc->flags),
111 LE16_TO_CPU(aq_desc->datalen),
112 LE16_TO_CPU(aq_desc->retval));
113 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
114 LE32_TO_CPU(aq_desc->cookie_high),
115 LE32_TO_CPU(aq_desc->cookie_low));
116 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
117 LE32_TO_CPU(aq_desc->params.internal.param0),
118 LE32_TO_CPU(aq_desc->params.internal.param1));
119 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
120 LE32_TO_CPU(aq_desc->params.external.addr_high),
121 LE32_TO_CPU(aq_desc->params.external.addr_low));
123 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
124 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
127 /* write the full 16-byte chunks */
128 for (i = 0; i < (len - 16); i += 16)
130 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
131 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
132 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
133 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
134 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
135 /* write whatever's left over without overrunning the buffer */
140 memset(d_buf, 0, sizeof(d_buf));
141 j += sprintf(d_buf, "\t0x%04X ", i);
143 j += sprintf(&d_buf[j], " %02X", buf[i++]);
144 i40e_debug(hw, mask, "%s\n", d_buf);
150 * i40e_check_asq_alive
151 * @hw: pointer to the hw struct
153 * Returns true if Queue is enabled else false.
155 bool i40e_check_asq_alive(struct i40e_hw *hw)
158 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
164 * i40e_aq_queue_shutdown
165 * @hw: pointer to the hw struct
166 * @unloading: is the driver unloading itself
168 * Tell the Firmware that we're shutting down the AdminQ and whether
169 * or not the driver is unloading as well.
171 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
174 struct i40e_aq_desc desc;
175 struct i40e_aqc_queue_shutdown *cmd =
176 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
177 enum i40e_status_code status;
179 i40e_fill_default_direct_cmd_desc(&desc,
180 i40e_aqc_opc_queue_shutdown);
183 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
189 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
190 * hardware to a bit-field that can be used by SW to more easily determine the
193 * Macros are used to shorten the table lines and make this table human
196 * We store the PTYPE in the top byte of the bit field - this is just so that
197 * we can check that the table doesn't have a row missing, as the index into
198 * the table should be the PTYPE.
202 * IF NOT i40e_ptype_lookup[ptype].known
205 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
206 * Use the rest of the fields to look at the tunnels, inner protocols, etc
208 * Use the enum i40e_rx_l2_ptype to decode the packet type
212 /* macro to make the table lines short */
213 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
216 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
217 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
218 I40E_RX_PTYPE_##OUTER_FRAG, \
219 I40E_RX_PTYPE_TUNNEL_##T, \
220 I40E_RX_PTYPE_TUNNEL_END_##TE, \
221 I40E_RX_PTYPE_##TEF, \
222 I40E_RX_PTYPE_INNER_PROT_##I, \
223 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
225 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
226 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
228 /* shorter macros makes the table fit but are terse */
229 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
230 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
231 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
233 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
234 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
235 /* L2 Packet types */
236 I40E_PTT_UNUSED_ENTRY(0),
237 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
239 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(4),
241 I40E_PTT_UNUSED_ENTRY(5),
242 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(8),
245 I40E_PTT_UNUSED_ENTRY(9),
246 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
248 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 /* Non Tunneled IPv4 */
260 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(25),
264 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
265 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
266 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
269 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
270 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
271 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(32),
273 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
274 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
275 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
278 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
279 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
280 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
281 I40E_PTT_UNUSED_ENTRY(39),
282 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
283 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
284 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
286 /* IPv4 --> GRE/NAT */
287 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
289 /* IPv4 --> GRE/NAT --> IPv4 */
290 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
291 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
292 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(47),
294 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
295 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
296 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> IPv6 */
299 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
300 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
301 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
302 I40E_PTT_UNUSED_ENTRY(54),
303 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
304 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
305 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
307 /* IPv4 --> GRE/NAT --> MAC */
308 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
310 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
311 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
312 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
313 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(62),
315 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
316 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
317 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
320 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
321 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
322 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
323 I40E_PTT_UNUSED_ENTRY(69),
324 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
325 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
326 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
328 /* IPv4 --> GRE/NAT --> MAC/VLAN */
329 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
331 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
332 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
333 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
334 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(77),
336 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
337 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
338 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
340 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
341 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
342 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
343 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(84),
345 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
346 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
347 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
349 /* Non Tunneled IPv6 */
350 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
353 I40E_PTT_UNUSED_ENTRY(91),
354 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
355 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
356 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
359 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
360 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
361 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(98),
363 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
364 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
365 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
368 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
369 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
370 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
371 I40E_PTT_UNUSED_ENTRY(105),
372 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
373 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
374 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
376 /* IPv6 --> GRE/NAT */
377 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
379 /* IPv6 --> GRE/NAT -> IPv4 */
380 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
381 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
382 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(113),
384 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
385 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
386 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> IPv6 */
389 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
390 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
391 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
392 I40E_PTT_UNUSED_ENTRY(120),
393 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
394 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
395 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
397 /* IPv6 --> GRE/NAT -> MAC */
398 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
401 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
402 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
403 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(128),
405 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
406 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
407 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
410 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
411 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
412 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
413 I40E_PTT_UNUSED_ENTRY(135),
414 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
415 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
416 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
418 /* IPv6 --> GRE/NAT -> MAC/VLAN */
419 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
422 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
423 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
424 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(143),
426 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
427 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
428 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
430 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
431 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
432 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
433 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
434 I40E_PTT_UNUSED_ENTRY(150),
435 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
436 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
437 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
440 I40E_PTT_UNUSED_ENTRY(154),
441 I40E_PTT_UNUSED_ENTRY(155),
442 I40E_PTT_UNUSED_ENTRY(156),
443 I40E_PTT_UNUSED_ENTRY(157),
444 I40E_PTT_UNUSED_ENTRY(158),
445 I40E_PTT_UNUSED_ENTRY(159),
447 I40E_PTT_UNUSED_ENTRY(160),
448 I40E_PTT_UNUSED_ENTRY(161),
449 I40E_PTT_UNUSED_ENTRY(162),
450 I40E_PTT_UNUSED_ENTRY(163),
451 I40E_PTT_UNUSED_ENTRY(164),
452 I40E_PTT_UNUSED_ENTRY(165),
453 I40E_PTT_UNUSED_ENTRY(166),
454 I40E_PTT_UNUSED_ENTRY(167),
455 I40E_PTT_UNUSED_ENTRY(168),
456 I40E_PTT_UNUSED_ENTRY(169),
458 I40E_PTT_UNUSED_ENTRY(170),
459 I40E_PTT_UNUSED_ENTRY(171),
460 I40E_PTT_UNUSED_ENTRY(172),
461 I40E_PTT_UNUSED_ENTRY(173),
462 I40E_PTT_UNUSED_ENTRY(174),
463 I40E_PTT_UNUSED_ENTRY(175),
464 I40E_PTT_UNUSED_ENTRY(176),
465 I40E_PTT_UNUSED_ENTRY(177),
466 I40E_PTT_UNUSED_ENTRY(178),
467 I40E_PTT_UNUSED_ENTRY(179),
469 I40E_PTT_UNUSED_ENTRY(180),
470 I40E_PTT_UNUSED_ENTRY(181),
471 I40E_PTT_UNUSED_ENTRY(182),
472 I40E_PTT_UNUSED_ENTRY(183),
473 I40E_PTT_UNUSED_ENTRY(184),
474 I40E_PTT_UNUSED_ENTRY(185),
475 I40E_PTT_UNUSED_ENTRY(186),
476 I40E_PTT_UNUSED_ENTRY(187),
477 I40E_PTT_UNUSED_ENTRY(188),
478 I40E_PTT_UNUSED_ENTRY(189),
480 I40E_PTT_UNUSED_ENTRY(190),
481 I40E_PTT_UNUSED_ENTRY(191),
482 I40E_PTT_UNUSED_ENTRY(192),
483 I40E_PTT_UNUSED_ENTRY(193),
484 I40E_PTT_UNUSED_ENTRY(194),
485 I40E_PTT_UNUSED_ENTRY(195),
486 I40E_PTT_UNUSED_ENTRY(196),
487 I40E_PTT_UNUSED_ENTRY(197),
488 I40E_PTT_UNUSED_ENTRY(198),
489 I40E_PTT_UNUSED_ENTRY(199),
491 I40E_PTT_UNUSED_ENTRY(200),
492 I40E_PTT_UNUSED_ENTRY(201),
493 I40E_PTT_UNUSED_ENTRY(202),
494 I40E_PTT_UNUSED_ENTRY(203),
495 I40E_PTT_UNUSED_ENTRY(204),
496 I40E_PTT_UNUSED_ENTRY(205),
497 I40E_PTT_UNUSED_ENTRY(206),
498 I40E_PTT_UNUSED_ENTRY(207),
499 I40E_PTT_UNUSED_ENTRY(208),
500 I40E_PTT_UNUSED_ENTRY(209),
502 I40E_PTT_UNUSED_ENTRY(210),
503 I40E_PTT_UNUSED_ENTRY(211),
504 I40E_PTT_UNUSED_ENTRY(212),
505 I40E_PTT_UNUSED_ENTRY(213),
506 I40E_PTT_UNUSED_ENTRY(214),
507 I40E_PTT_UNUSED_ENTRY(215),
508 I40E_PTT_UNUSED_ENTRY(216),
509 I40E_PTT_UNUSED_ENTRY(217),
510 I40E_PTT_UNUSED_ENTRY(218),
511 I40E_PTT_UNUSED_ENTRY(219),
513 I40E_PTT_UNUSED_ENTRY(220),
514 I40E_PTT_UNUSED_ENTRY(221),
515 I40E_PTT_UNUSED_ENTRY(222),
516 I40E_PTT_UNUSED_ENTRY(223),
517 I40E_PTT_UNUSED_ENTRY(224),
518 I40E_PTT_UNUSED_ENTRY(225),
519 I40E_PTT_UNUSED_ENTRY(226),
520 I40E_PTT_UNUSED_ENTRY(227),
521 I40E_PTT_UNUSED_ENTRY(228),
522 I40E_PTT_UNUSED_ENTRY(229),
524 I40E_PTT_UNUSED_ENTRY(230),
525 I40E_PTT_UNUSED_ENTRY(231),
526 I40E_PTT_UNUSED_ENTRY(232),
527 I40E_PTT_UNUSED_ENTRY(233),
528 I40E_PTT_UNUSED_ENTRY(234),
529 I40E_PTT_UNUSED_ENTRY(235),
530 I40E_PTT_UNUSED_ENTRY(236),
531 I40E_PTT_UNUSED_ENTRY(237),
532 I40E_PTT_UNUSED_ENTRY(238),
533 I40E_PTT_UNUSED_ENTRY(239),
535 I40E_PTT_UNUSED_ENTRY(240),
536 I40E_PTT_UNUSED_ENTRY(241),
537 I40E_PTT_UNUSED_ENTRY(242),
538 I40E_PTT_UNUSED_ENTRY(243),
539 I40E_PTT_UNUSED_ENTRY(244),
540 I40E_PTT_UNUSED_ENTRY(245),
541 I40E_PTT_UNUSED_ENTRY(246),
542 I40E_PTT_UNUSED_ENTRY(247),
543 I40E_PTT_UNUSED_ENTRY(248),
544 I40E_PTT_UNUSED_ENTRY(249),
546 I40E_PTT_UNUSED_ENTRY(250),
547 I40E_PTT_UNUSED_ENTRY(251),
548 I40E_PTT_UNUSED_ENTRY(252),
549 I40E_PTT_UNUSED_ENTRY(253),
550 I40E_PTT_UNUSED_ENTRY(254),
551 I40E_PTT_UNUSED_ENTRY(255)
557 * i40e_init_shared_code - Initialize the shared code
558 * @hw: pointer to hardware structure
560 * This assigns the MAC type and PHY code and inits the NVM.
561 * Does not touch the hardware. This function must be called prior to any
562 * other function in the shared code. The i40e_hw structure should be
563 * memset to 0 prior to calling this function. The following fields in
564 * hw structure should be filled in prior to calling this function:
565 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
566 * subsystem_vendor_id, and revision_id
568 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
570 enum i40e_status_code status = I40E_SUCCESS;
571 u32 port, ari, func_rid;
573 DEBUGFUNC("i40e_init_shared_code");
575 i40e_set_mac_type(hw);
577 switch (hw->mac.type) {
581 return I40E_ERR_DEVICE_NOT_SUPPORTED;
584 hw->phy.get_link_info = true;
586 /* Determine port number and PF number*/
587 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
588 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
590 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
591 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
592 func_rid = rd32(hw, I40E_PF_FUNC_RID);
594 hw->pf_id = (u8)(func_rid & 0xff);
596 hw->pf_id = (u8)(func_rid & 0x7);
598 status = i40e_init_nvm(hw);
603 * i40e_aq_mac_address_read - Retrieve the MAC addresses
604 * @hw: pointer to the hw struct
605 * @flags: a return indicator of what addresses were added to the addr store
606 * @addrs: the requestor's mac addr store
607 * @cmd_details: pointer to command details structure or NULL
609 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
611 struct i40e_aqc_mac_address_read_data *addrs,
612 struct i40e_asq_cmd_details *cmd_details)
614 struct i40e_aq_desc desc;
615 struct i40e_aqc_mac_address_read *cmd_data =
616 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
617 enum i40e_status_code status;
619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
620 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
622 status = i40e_asq_send_command(hw, &desc, addrs,
623 sizeof(*addrs), cmd_details);
624 *flags = LE16_TO_CPU(cmd_data->command_flags);
630 * i40e_aq_mac_address_write - Change the MAC addresses
631 * @hw: pointer to the hw struct
632 * @flags: indicates which MAC to be written
633 * @mac_addr: address to write
634 * @cmd_details: pointer to command details structure or NULL
636 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
637 u16 flags, u8 *mac_addr,
638 struct i40e_asq_cmd_details *cmd_details)
640 struct i40e_aq_desc desc;
641 struct i40e_aqc_mac_address_write *cmd_data =
642 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
643 enum i40e_status_code status;
645 i40e_fill_default_direct_cmd_desc(&desc,
646 i40e_aqc_opc_mac_address_write);
647 cmd_data->command_flags = CPU_TO_LE16(flags);
648 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
649 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
650 ((u32)mac_addr[3] << 16) |
651 ((u32)mac_addr[4] << 8) |
654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
660 * i40e_get_mac_addr - get MAC address
661 * @hw: pointer to the HW structure
662 * @mac_addr: pointer to MAC address
664 * Reads the adapter's MAC address from register
666 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668 struct i40e_aqc_mac_address_read_data addrs;
669 enum i40e_status_code status;
672 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (flags & I40E_AQC_LAN_ADDR_VALID)
675 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
681 * i40e_get_port_mac_addr - get Port MAC address
682 * @hw: pointer to the HW structure
683 * @mac_addr: pointer to Port MAC address
685 * Reads the adapter's Port MAC address
687 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
689 struct i40e_aqc_mac_address_read_data addrs;
690 enum i40e_status_code status;
693 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
697 if (flags & I40E_AQC_PORT_ADDR_VALID)
698 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
700 status = I40E_ERR_INVALID_MAC_ADDR;
706 * i40e_pre_tx_queue_cfg - pre tx queue configure
707 * @hw: pointer to the HW structure
708 * @queue: target pf queue index
709 * @enable: state change request
711 * Handles hw requirement to indicate intention to enable
712 * or disable target queue.
714 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
716 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
720 if (abs_queue_idx >= 128) {
721 reg_block = abs_queue_idx / 128;
722 abs_queue_idx %= 128;
725 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
726 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
727 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
730 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
732 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
734 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
738 * i40e_validate_mac_addr - Validate unicast MAC address
739 * @mac_addr: pointer to MAC address
741 * Tests a MAC address to ensure it is a valid Individual Address
743 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
745 enum i40e_status_code status = I40E_SUCCESS;
747 DEBUGFUNC("i40e_validate_mac_addr");
749 /* Broadcast addresses ARE multicast addresses
750 * Make sure it is not a multicast address
751 * Reject the zero address
753 if (I40E_IS_MULTICAST(mac_addr) ||
754 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
755 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
756 status = I40E_ERR_INVALID_MAC_ADDR;
762 * i40e_get_media_type - Gets media type
763 * @hw: pointer to the hardware structure
765 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
767 enum i40e_media_type media;
769 switch (hw->phy.link_info.phy_type) {
770 case I40E_PHY_TYPE_10GBASE_SR:
771 case I40E_PHY_TYPE_10GBASE_LR:
772 case I40E_PHY_TYPE_1000BASE_SX:
773 case I40E_PHY_TYPE_1000BASE_LX:
774 case I40E_PHY_TYPE_40GBASE_SR4:
775 case I40E_PHY_TYPE_40GBASE_LR4:
776 media = I40E_MEDIA_TYPE_FIBER;
778 case I40E_PHY_TYPE_100BASE_TX:
779 case I40E_PHY_TYPE_1000BASE_T:
780 case I40E_PHY_TYPE_10GBASE_T:
781 media = I40E_MEDIA_TYPE_BASET;
783 case I40E_PHY_TYPE_10GBASE_CR1_CU:
784 case I40E_PHY_TYPE_40GBASE_CR4_CU:
785 case I40E_PHY_TYPE_10GBASE_CR1:
786 case I40E_PHY_TYPE_40GBASE_CR4:
787 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
788 media = I40E_MEDIA_TYPE_DA;
790 case I40E_PHY_TYPE_1000BASE_KX:
791 case I40E_PHY_TYPE_10GBASE_KX4:
792 case I40E_PHY_TYPE_10GBASE_KR:
793 case I40E_PHY_TYPE_40GBASE_KR4:
794 media = I40E_MEDIA_TYPE_BACKPLANE;
796 case I40E_PHY_TYPE_SGMII:
797 case I40E_PHY_TYPE_XAUI:
798 case I40E_PHY_TYPE_XFI:
799 case I40E_PHY_TYPE_XLAUI:
800 case I40E_PHY_TYPE_XLPPI:
802 media = I40E_MEDIA_TYPE_UNKNOWN;
809 #define I40E_PF_RESET_WAIT_COUNT 100
811 * i40e_pf_reset - Reset the PF
812 * @hw: pointer to the hardware structure
814 * Assuming someone else has triggered a global reset,
815 * assure the global reset is complete and then reset the PF
817 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
824 /* Poll for Global Reset steady state in case of recent GRST.
825 * The grst delay value is in 100ms units, and we'll wait a
826 * couple counts longer to be sure we don't just miss the end.
828 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
829 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
830 for (cnt = 0; cnt < grst_del + 2; cnt++) {
831 reg = rd32(hw, I40E_GLGEN_RSTAT);
832 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
834 i40e_msec_delay(100);
836 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
837 DEBUGOUT("Global reset polling failed to complete.\n");
838 return I40E_ERR_RESET_FAILED;
841 /* Now Wait for the FW to be ready */
842 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
843 reg = rd32(hw, I40E_GLNVM_ULD);
844 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
845 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
846 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
847 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
848 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
853 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
854 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
855 DEBUGOUT("wait for FW Reset complete timedout\n");
856 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
857 return I40E_ERR_RESET_FAILED;
860 /* If there was a Global Reset in progress when we got here,
861 * we don't need to do the PF Reset
864 reg = rd32(hw, I40E_PFGEN_CTRL);
865 wr32(hw, I40E_PFGEN_CTRL,
866 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
867 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
868 reg = rd32(hw, I40E_PFGEN_CTRL);
869 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
873 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
874 DEBUGOUT("PF reset polling failed to complete.\n");
875 return I40E_ERR_RESET_FAILED;
879 i40e_clear_pxe_mode(hw);
886 * i40e_clear_hw - clear out any left over hw state
887 * @hw: pointer to the hw struct
889 * Clear queues and interrupts, typically called at init time,
890 * but after the capabilities have been found so we know how many
891 * queues and msix vectors have been allocated.
893 void i40e_clear_hw(struct i40e_hw *hw)
895 u32 num_queues, base_queue;
903 /* get number of interrupts, queues, and vfs */
904 val = rd32(hw, I40E_GLPCI_CNF2);
905 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
906 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
907 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
908 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
910 val = rd32(hw, I40E_PFLAN_QALLOC);
911 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
912 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
913 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
914 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
915 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
916 num_queues = (j - base_queue) + 1;
920 val = rd32(hw, I40E_PF_VT_PFALLOC);
921 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
922 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
923 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
924 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
925 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
926 num_vfs = (j - i) + 1;
930 /* stop all the interrupts */
931 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
932 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
933 for (i = 0; i < num_pf_int - 2; i++)
934 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
936 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
937 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
938 wr32(hw, I40E_PFINT_LNKLST0, val);
939 for (i = 0; i < num_pf_int - 2; i++)
940 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
941 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
942 for (i = 0; i < num_vfs; i++)
943 wr32(hw, I40E_VPINT_LNKLST0(i), val);
944 for (i = 0; i < num_vf_int - 2; i++)
945 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
947 /* warn the HW of the coming Tx disables */
948 for (i = 0; i < num_queues; i++) {
949 u32 abs_queue_idx = base_queue + i;
952 if (abs_queue_idx >= 128) {
953 reg_block = abs_queue_idx / 128;
954 abs_queue_idx %= 128;
957 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
958 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
959 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
960 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
962 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
964 i40e_usec_delay(400);
966 /* stop all the queues */
967 for (i = 0; i < num_queues; i++) {
968 wr32(hw, I40E_QINT_TQCTL(i), 0);
969 wr32(hw, I40E_QTX_ENA(i), 0);
970 wr32(hw, I40E_QINT_RQCTL(i), 0);
971 wr32(hw, I40E_QRX_ENA(i), 0);
974 /* short wait for all queue disables to settle */
979 * i40e_clear_pxe_mode - clear pxe operations mode
980 * @hw: pointer to the hw struct
982 * Make sure all PXE mode settings are cleared, including things
983 * like descriptor fetch/write-back mode.
985 void i40e_clear_pxe_mode(struct i40e_hw *hw)
987 if (i40e_check_asq_alive(hw))
988 i40e_aq_clear_pxe_mode(hw, NULL);
992 * i40e_led_is_mine - helper to find matching led
993 * @hw: pointer to the hw struct
994 * @idx: index into GPIO registers
996 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
998 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1003 if (!hw->func_caps.led[idx])
1006 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1007 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1008 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1010 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1011 * if it is not our port then ignore
1013 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1020 #define I40E_COMBINED_ACTIVITY 0xA
1021 #define I40E_FILTER_ACTIVITY 0xE
1022 #define I40E_LINK_ACTIVITY 0xC
1023 #define I40E_MAC_ACTIVITY 0xD
1024 #define I40E_LED0 22
1027 * i40e_led_get - return current on/off mode
1028 * @hw: pointer to the hw struct
1030 * The value returned is the 'mode' field as defined in the
1031 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1032 * values are variations of possible behaviors relating to
1033 * blink, link, and wire.
1035 u32 i40e_led_get(struct i40e_hw *hw)
1037 u32 current_mode = 0;
1041 /* as per the documentation GPIO 22-29 are the LED
1042 * GPIO pins named LED0..LED7
1044 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1045 u32 gpio_val = i40e_led_is_mine(hw, i);
1050 /* ignore gpio LED src mode entries related to the activity LEDs */
1051 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1052 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1053 switch (current_mode) {
1054 case I40E_COMBINED_ACTIVITY:
1055 case I40E_FILTER_ACTIVITY:
1056 case I40E_MAC_ACTIVITY:
1062 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1063 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1071 * i40e_led_set - set new on/off mode
1072 * @hw: pointer to the hw struct
1073 * @mode: 0=off, 0xf=on (else see manual for mode details)
1074 * @blink: true if the LED should blink when on, false if steady
1076 * if this function is used to turn on the blink it should
1077 * be used to disable the blink when restoring the original state.
1079 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1081 u32 current_mode = 0;
1084 if (mode & 0xfffffff0)
1085 DEBUGOUT1("invalid mode passed in %X\n", mode);
1087 /* as per the documentation GPIO 22-29 are the LED
1088 * GPIO pins named LED0..LED7
1090 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1091 u32 gpio_val = i40e_led_is_mine(hw, i);
1096 /* ignore gpio LED src mode entries related to the activity LEDs */
1097 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1098 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1099 switch (current_mode) {
1100 case I40E_COMBINED_ACTIVITY:
1101 case I40E_FILTER_ACTIVITY:
1102 case I40E_MAC_ACTIVITY:
1108 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1109 /* this & is a bit of paranoia, but serves as a range check */
1110 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1111 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1113 if (mode == I40E_LINK_ACTIVITY)
1117 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1119 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1121 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1126 /* Admin command wrappers */
1129 * i40e_aq_get_phy_capabilities
1130 * @hw: pointer to the hw struct
1131 * @abilities: structure for PHY capabilities to be filled
1132 * @qualified_modules: report Qualified Modules
1133 * @report_init: report init capabilities (active are default)
1134 * @cmd_details: pointer to command details structure or NULL
1136 * Returns the various PHY abilities supported on the Port.
1138 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1139 bool qualified_modules, bool report_init,
1140 struct i40e_aq_get_phy_abilities_resp *abilities,
1141 struct i40e_asq_cmd_details *cmd_details)
1143 struct i40e_aq_desc desc;
1144 enum i40e_status_code status;
1145 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1148 return I40E_ERR_PARAM;
1150 i40e_fill_default_direct_cmd_desc(&desc,
1151 i40e_aqc_opc_get_phy_abilities);
1153 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1154 if (abilities_size > I40E_AQ_LARGE_BUF)
1155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1157 if (qualified_modules)
1158 desc.params.external.param0 |=
1159 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1162 desc.params.external.param0 |=
1163 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1165 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1168 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1169 status = I40E_ERR_UNKNOWN_PHY;
1175 * i40e_aq_set_phy_config
1176 * @hw: pointer to the hw struct
1177 * @config: structure with PHY configuration to be set
1178 * @cmd_details: pointer to command details structure or NULL
1180 * Set the various PHY configuration parameters
1181 * supported on the Port.One or more of the Set PHY config parameters may be
1182 * ignored in an MFP mode as the PF may not have the privilege to set some
1183 * of the PHY Config parameters. This status will be indicated by the
1186 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1187 struct i40e_aq_set_phy_config *config,
1188 struct i40e_asq_cmd_details *cmd_details)
1190 struct i40e_aq_desc desc;
1191 struct i40e_aq_set_phy_config *cmd =
1192 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1193 enum i40e_status_code status;
1196 return I40E_ERR_PARAM;
1198 i40e_fill_default_direct_cmd_desc(&desc,
1199 i40e_aqc_opc_set_phy_config);
1203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1210 * @hw: pointer to the hw struct
1212 * Set the requested flow control mode using set_phy_config.
1214 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1215 bool atomic_restart)
1217 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1218 struct i40e_aq_get_phy_abilities_resp abilities;
1219 struct i40e_aq_set_phy_config config;
1220 enum i40e_status_code status;
1221 u8 pause_mask = 0x0;
1227 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1228 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1230 case I40E_FC_RX_PAUSE:
1231 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1233 case I40E_FC_TX_PAUSE:
1234 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1240 /* Get the current phy config */
1241 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1244 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1248 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1249 /* clear the old pause settings */
1250 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1251 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1252 /* set the new abilities */
1253 config.abilities |= pause_mask;
1254 /* If the abilities have changed, then set the new config */
1255 if (config.abilities != abilities.abilities) {
1256 /* Auto restart link so settings take effect */
1258 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1259 /* Copy over all the old settings */
1260 config.phy_type = abilities.phy_type;
1261 config.link_speed = abilities.link_speed;
1262 config.eee_capability = abilities.eee_capability;
1263 config.eeer = abilities.eeer_val;
1264 config.low_power_ctrl = abilities.d3_lpan;
1265 status = i40e_aq_set_phy_config(hw, &config, NULL);
1268 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1270 /* Update the link info */
1271 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1273 /* Wait a little bit (on 40G cards it sometimes takes a really
1274 * long time for link to come back from the atomic reset)
1277 i40e_msec_delay(1000);
1278 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1281 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1287 * i40e_aq_set_mac_config
1288 * @hw: pointer to the hw struct
1289 * @max_frame_size: Maximum Frame Size to be supported by the port
1290 * @crc_en: Tell HW to append a CRC to outgoing frames
1291 * @pacing: Pacing configurations
1292 * @cmd_details: pointer to command details structure or NULL
1294 * Configure MAC settings for frame size, jumbo frame support and the
1295 * addition of a CRC by the hardware.
1297 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1299 bool crc_en, u16 pacing,
1300 struct i40e_asq_cmd_details *cmd_details)
1302 struct i40e_aq_desc desc;
1303 struct i40e_aq_set_mac_config *cmd =
1304 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1305 enum i40e_status_code status;
1307 if (max_frame_size == 0)
1308 return I40E_ERR_PARAM;
1310 i40e_fill_default_direct_cmd_desc(&desc,
1311 i40e_aqc_opc_set_mac_config);
1313 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1314 cmd->params = ((u8)pacing & 0x0F) << 3;
1316 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1318 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1324 * i40e_aq_clear_pxe_mode
1325 * @hw: pointer to the hw struct
1326 * @cmd_details: pointer to command details structure or NULL
1328 * Tell the firmware that the driver is taking over from PXE
1330 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1331 struct i40e_asq_cmd_details *cmd_details)
1333 enum i40e_status_code status;
1334 struct i40e_aq_desc desc;
1335 struct i40e_aqc_clear_pxe *cmd =
1336 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1338 i40e_fill_default_direct_cmd_desc(&desc,
1339 i40e_aqc_opc_clear_pxe_mode);
1343 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1345 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1351 * i40e_aq_set_link_restart_an
1352 * @hw: pointer to the hw struct
1353 * @enable_link: if true: enable link, if false: disable link
1354 * @cmd_details: pointer to command details structure or NULL
1356 * Sets up the link and restarts the Auto-Negotiation over the link.
1358 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1359 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1361 struct i40e_aq_desc desc;
1362 struct i40e_aqc_set_link_restart_an *cmd =
1363 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1364 enum i40e_status_code status;
1366 i40e_fill_default_direct_cmd_desc(&desc,
1367 i40e_aqc_opc_set_link_restart_an);
1369 cmd->command = I40E_AQ_PHY_RESTART_AN;
1371 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1373 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1381 * i40e_aq_get_link_info
1382 * @hw: pointer to the hw struct
1383 * @enable_lse: enable/disable LinkStatusEvent reporting
1384 * @link: pointer to link status structure - optional
1385 * @cmd_details: pointer to command details structure or NULL
1387 * Returns the link status of the adapter.
1389 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1390 bool enable_lse, struct i40e_link_status *link,
1391 struct i40e_asq_cmd_details *cmd_details)
1393 struct i40e_aq_desc desc;
1394 struct i40e_aqc_get_link_status *resp =
1395 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1396 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1397 enum i40e_status_code status;
1398 bool tx_pause, rx_pause;
1401 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1404 command_flags = I40E_AQ_LSE_ENABLE;
1406 command_flags = I40E_AQ_LSE_DISABLE;
1407 resp->command_flags = CPU_TO_LE16(command_flags);
1409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1411 if (status != I40E_SUCCESS)
1412 goto aq_get_link_info_exit;
1414 /* save off old link status information */
1415 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1416 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1418 /* update link status */
1419 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1420 hw->phy.media_type = i40e_get_media_type(hw);
1421 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1422 hw_link_info->link_info = resp->link_info;
1423 hw_link_info->an_info = resp->an_info;
1424 hw_link_info->ext_info = resp->ext_info;
1425 hw_link_info->loopback = resp->loopback;
1426 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1427 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1429 /* update fc info */
1430 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1431 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1432 if (tx_pause & rx_pause)
1433 hw->fc.current_mode = I40E_FC_FULL;
1435 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1437 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1439 hw->fc.current_mode = I40E_FC_NONE;
1441 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1442 hw_link_info->crc_enable = true;
1444 hw_link_info->crc_enable = false;
1446 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1447 hw_link_info->lse_enable = true;
1449 hw_link_info->lse_enable = false;
1451 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1452 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1453 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1455 /* save link status information */
1457 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1458 I40E_NONDMA_TO_NONDMA);
1460 /* flag cleared so helper functions don't call AQ again */
1461 hw->phy.get_link_info = false;
1463 aq_get_link_info_exit:
1468 * i40e_aq_set_phy_int_mask
1469 * @hw: pointer to the hw struct
1470 * @mask: interrupt mask to be set
1471 * @cmd_details: pointer to command details structure or NULL
1473 * Set link interrupt mask.
1475 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1477 struct i40e_asq_cmd_details *cmd_details)
1479 struct i40e_aq_desc desc;
1480 struct i40e_aqc_set_phy_int_mask *cmd =
1481 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1482 enum i40e_status_code status;
1484 i40e_fill_default_direct_cmd_desc(&desc,
1485 i40e_aqc_opc_set_phy_int_mask);
1487 cmd->event_mask = CPU_TO_LE16(mask);
1489 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1495 * i40e_aq_get_local_advt_reg
1496 * @hw: pointer to the hw struct
1497 * @advt_reg: local AN advertisement register value
1498 * @cmd_details: pointer to command details structure or NULL
1500 * Get the Local AN advertisement register value.
1502 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1504 struct i40e_asq_cmd_details *cmd_details)
1506 struct i40e_aq_desc desc;
1507 struct i40e_aqc_an_advt_reg *resp =
1508 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1509 enum i40e_status_code status;
1511 i40e_fill_default_direct_cmd_desc(&desc,
1512 i40e_aqc_opc_get_local_advt_reg);
1514 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1516 if (status != I40E_SUCCESS)
1517 goto aq_get_local_advt_reg_exit;
1519 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1520 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1522 aq_get_local_advt_reg_exit:
1527 * i40e_aq_set_local_advt_reg
1528 * @hw: pointer to the hw struct
1529 * @advt_reg: local AN advertisement register value
1530 * @cmd_details: pointer to command details structure or NULL
1532 * Get the Local AN advertisement register value.
1534 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1536 struct i40e_asq_cmd_details *cmd_details)
1538 struct i40e_aq_desc desc;
1539 struct i40e_aqc_an_advt_reg *cmd =
1540 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1541 enum i40e_status_code status;
1543 i40e_fill_default_direct_cmd_desc(&desc,
1544 i40e_aqc_opc_get_local_advt_reg);
1546 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1547 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1549 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1555 * i40e_aq_get_partner_advt
1556 * @hw: pointer to the hw struct
1557 * @advt_reg: AN partner advertisement register value
1558 * @cmd_details: pointer to command details structure or NULL
1560 * Get the link partner AN advertisement register value.
1562 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1564 struct i40e_asq_cmd_details *cmd_details)
1566 struct i40e_aq_desc desc;
1567 struct i40e_aqc_an_advt_reg *resp =
1568 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1569 enum i40e_status_code status;
1571 i40e_fill_default_direct_cmd_desc(&desc,
1572 i40e_aqc_opc_get_partner_advt);
1574 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1576 if (status != I40E_SUCCESS)
1577 goto aq_get_partner_advt_exit;
1579 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1580 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1582 aq_get_partner_advt_exit:
1587 * i40e_aq_set_lb_modes
1588 * @hw: pointer to the hw struct
1589 * @lb_modes: loopback mode to be set
1590 * @cmd_details: pointer to command details structure or NULL
1592 * Sets loopback modes.
1594 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1596 struct i40e_asq_cmd_details *cmd_details)
1598 struct i40e_aq_desc desc;
1599 struct i40e_aqc_set_lb_mode *cmd =
1600 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1601 enum i40e_status_code status;
1603 i40e_fill_default_direct_cmd_desc(&desc,
1604 i40e_aqc_opc_set_lb_modes);
1606 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1608 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1614 * i40e_aq_set_phy_debug
1615 * @hw: pointer to the hw struct
1616 * @cmd_flags: debug command flags
1617 * @cmd_details: pointer to command details structure or NULL
1619 * Reset the external PHY.
1621 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1622 struct i40e_asq_cmd_details *cmd_details)
1624 struct i40e_aq_desc desc;
1625 struct i40e_aqc_set_phy_debug *cmd =
1626 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1627 enum i40e_status_code status;
1629 i40e_fill_default_direct_cmd_desc(&desc,
1630 i40e_aqc_opc_set_phy_debug);
1632 cmd->command_flags = cmd_flags;
1634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1641 * @hw: pointer to the hw struct
1642 * @vsi_ctx: pointer to a vsi context struct
1643 * @cmd_details: pointer to command details structure or NULL
1645 * Add a VSI context to the hardware.
1647 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1648 struct i40e_vsi_context *vsi_ctx,
1649 struct i40e_asq_cmd_details *cmd_details)
1651 struct i40e_aq_desc desc;
1652 struct i40e_aqc_add_get_update_vsi *cmd =
1653 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1654 struct i40e_aqc_add_get_update_vsi_completion *resp =
1655 (struct i40e_aqc_add_get_update_vsi_completion *)
1657 enum i40e_status_code status;
1659 i40e_fill_default_direct_cmd_desc(&desc,
1660 i40e_aqc_opc_add_vsi);
1662 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1663 cmd->connection_type = vsi_ctx->connection_type;
1664 cmd->vf_id = vsi_ctx->vf_num;
1665 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1667 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1669 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1670 sizeof(vsi_ctx->info), cmd_details);
1672 if (status != I40E_SUCCESS)
1673 goto aq_add_vsi_exit;
1675 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1676 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1677 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1678 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1685 * i40e_aq_set_default_vsi
1686 * @hw: pointer to the hw struct
1688 * @cmd_details: pointer to command details structure or NULL
1690 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1692 struct i40e_asq_cmd_details *cmd_details)
1694 struct i40e_aq_desc desc;
1695 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1696 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1698 enum i40e_status_code status;
1700 i40e_fill_default_direct_cmd_desc(&desc,
1701 i40e_aqc_opc_set_vsi_promiscuous_modes);
1703 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1704 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1705 cmd->seid = CPU_TO_LE16(seid);
1707 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1713 * i40e_aq_set_vsi_unicast_promiscuous
1714 * @hw: pointer to the hw struct
1716 * @set: set unicast promiscuous enable/disable
1717 * @cmd_details: pointer to command details structure or NULL
1719 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1721 struct i40e_asq_cmd_details *cmd_details)
1723 struct i40e_aq_desc desc;
1724 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1725 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1726 enum i40e_status_code status;
1729 i40e_fill_default_direct_cmd_desc(&desc,
1730 i40e_aqc_opc_set_vsi_promiscuous_modes);
1733 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1735 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1737 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1739 cmd->seid = CPU_TO_LE16(seid);
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1746 * i40e_aq_set_vsi_multicast_promiscuous
1747 * @hw: pointer to the hw struct
1749 * @set: set multicast promiscuous enable/disable
1750 * @cmd_details: pointer to command details structure or NULL
1752 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1753 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1755 struct i40e_aq_desc desc;
1756 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1757 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1758 enum i40e_status_code status;
1761 i40e_fill_default_direct_cmd_desc(&desc,
1762 i40e_aqc_opc_set_vsi_promiscuous_modes);
1765 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1767 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1769 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1771 cmd->seid = CPU_TO_LE16(seid);
1772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1778 * i40e_aq_set_vsi_broadcast
1779 * @hw: pointer to the hw struct
1781 * @set_filter: true to set filter, false to clear filter
1782 * @cmd_details: pointer to command details structure or NULL
1784 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1786 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1787 u16 seid, bool set_filter,
1788 struct i40e_asq_cmd_details *cmd_details)
1790 struct i40e_aq_desc desc;
1791 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1792 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1793 enum i40e_status_code status;
1795 i40e_fill_default_direct_cmd_desc(&desc,
1796 i40e_aqc_opc_set_vsi_promiscuous_modes);
1799 cmd->promiscuous_flags
1800 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1802 cmd->promiscuous_flags
1803 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1805 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1806 cmd->seid = CPU_TO_LE16(seid);
1807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1813 * i40e_get_vsi_params - get VSI configuration info
1814 * @hw: pointer to the hw struct
1815 * @vsi_ctx: pointer to a vsi context struct
1816 * @cmd_details: pointer to command details structure or NULL
1818 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1819 struct i40e_vsi_context *vsi_ctx,
1820 struct i40e_asq_cmd_details *cmd_details)
1822 struct i40e_aq_desc desc;
1823 struct i40e_aqc_add_get_update_vsi *cmd =
1824 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1825 struct i40e_aqc_add_get_update_vsi_completion *resp =
1826 (struct i40e_aqc_add_get_update_vsi_completion *)
1828 enum i40e_status_code status;
1830 UNREFERENCED_1PARAMETER(cmd_details);
1831 i40e_fill_default_direct_cmd_desc(&desc,
1832 i40e_aqc_opc_get_vsi_parameters);
1834 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1836 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1838 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1839 sizeof(vsi_ctx->info), NULL);
1841 if (status != I40E_SUCCESS)
1842 goto aq_get_vsi_params_exit;
1844 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1845 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1846 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1847 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1849 aq_get_vsi_params_exit:
1854 * i40e_aq_update_vsi_params
1855 * @hw: pointer to the hw struct
1856 * @vsi_ctx: pointer to a vsi context struct
1857 * @cmd_details: pointer to command details structure or NULL
1859 * Update a VSI context.
1861 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1862 struct i40e_vsi_context *vsi_ctx,
1863 struct i40e_asq_cmd_details *cmd_details)
1865 struct i40e_aq_desc desc;
1866 struct i40e_aqc_add_get_update_vsi *cmd =
1867 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1868 enum i40e_status_code status;
1870 i40e_fill_default_direct_cmd_desc(&desc,
1871 i40e_aqc_opc_update_vsi_parameters);
1872 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1874 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1876 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1877 sizeof(vsi_ctx->info), cmd_details);
1883 * i40e_aq_get_switch_config
1884 * @hw: pointer to the hardware structure
1885 * @buf: pointer to the result buffer
1886 * @buf_size: length of input buffer
1887 * @start_seid: seid to start for the report, 0 == beginning
1888 * @cmd_details: pointer to command details structure or NULL
1890 * Fill the buf with switch configuration returned from AdminQ command
1892 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1893 struct i40e_aqc_get_switch_config_resp *buf,
1894 u16 buf_size, u16 *start_seid,
1895 struct i40e_asq_cmd_details *cmd_details)
1897 struct i40e_aq_desc desc;
1898 struct i40e_aqc_switch_seid *scfg =
1899 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1900 enum i40e_status_code status;
1902 i40e_fill_default_direct_cmd_desc(&desc,
1903 i40e_aqc_opc_get_switch_config);
1904 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1905 if (buf_size > I40E_AQ_LARGE_BUF)
1906 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1907 scfg->seid = CPU_TO_LE16(*start_seid);
1909 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1910 *start_seid = LE16_TO_CPU(scfg->seid);
1916 * i40e_aq_get_firmware_version
1917 * @hw: pointer to the hw struct
1918 * @fw_major_version: firmware major version
1919 * @fw_minor_version: firmware minor version
1920 * @fw_build: firmware build number
1921 * @api_major_version: major queue version
1922 * @api_minor_version: minor queue version
1923 * @cmd_details: pointer to command details structure or NULL
1925 * Get the firmware version from the admin queue commands
1927 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1928 u16 *fw_major_version, u16 *fw_minor_version,
1930 u16 *api_major_version, u16 *api_minor_version,
1931 struct i40e_asq_cmd_details *cmd_details)
1933 struct i40e_aq_desc desc;
1934 struct i40e_aqc_get_version *resp =
1935 (struct i40e_aqc_get_version *)&desc.params.raw;
1936 enum i40e_status_code status;
1938 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1942 if (status == I40E_SUCCESS) {
1943 if (fw_major_version != NULL)
1944 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1945 if (fw_minor_version != NULL)
1946 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1947 if (fw_build != NULL)
1948 *fw_build = LE32_TO_CPU(resp->fw_build);
1949 if (api_major_version != NULL)
1950 *api_major_version = LE16_TO_CPU(resp->api_major);
1951 if (api_minor_version != NULL)
1952 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1954 /* A workaround to fix the API version in SW */
1955 if (api_major_version && api_minor_version &&
1956 fw_major_version && fw_minor_version &&
1957 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1958 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1959 (*fw_major_version > 4)))
1960 *api_minor_version = 2;
1967 * i40e_aq_send_driver_version
1968 * @hw: pointer to the hw struct
1969 * @dv: driver's major, minor version
1970 * @cmd_details: pointer to command details structure or NULL
1972 * Send the driver version to the firmware
1974 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1975 struct i40e_driver_version *dv,
1976 struct i40e_asq_cmd_details *cmd_details)
1978 struct i40e_aq_desc desc;
1979 struct i40e_aqc_driver_version *cmd =
1980 (struct i40e_aqc_driver_version *)&desc.params.raw;
1981 enum i40e_status_code status;
1985 return I40E_ERR_PARAM;
1987 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1989 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1990 cmd->driver_major_ver = dv->major_version;
1991 cmd->driver_minor_ver = dv->minor_version;
1992 cmd->driver_build_ver = dv->build_version;
1993 cmd->driver_subbuild_ver = dv->subbuild_version;
1996 while (len < sizeof(dv->driver_string) &&
1997 (dv->driver_string[len] < 0x80) &&
1998 dv->driver_string[len])
2000 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2007 * i40e_get_link_status - get status of the HW network link
2008 * @hw: pointer to the hw struct
2010 * Returns true if link is up, false if link is down.
2012 * Side effect: LinkStatusEvent reporting becomes enabled
2014 bool i40e_get_link_status(struct i40e_hw *hw)
2016 enum i40e_status_code status = I40E_SUCCESS;
2017 bool link_status = false;
2019 if (hw->phy.get_link_info) {
2020 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2022 if (status != I40E_SUCCESS)
2023 goto i40e_get_link_status_exit;
2026 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2028 i40e_get_link_status_exit:
2033 * i40e_get_link_speed
2034 * @hw: pointer to the hw struct
2036 * Returns the link speed of the adapter.
2038 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2040 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2041 enum i40e_status_code status = I40E_SUCCESS;
2043 if (hw->phy.get_link_info) {
2044 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2046 if (status != I40E_SUCCESS)
2047 goto i40e_link_speed_exit;
2050 speed = hw->phy.link_info.link_speed;
2052 i40e_link_speed_exit:
2057 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2058 * @hw: pointer to the hw struct
2059 * @uplink_seid: the MAC or other gizmo SEID
2060 * @downlink_seid: the VSI SEID
2061 * @enabled_tc: bitmap of TCs to be enabled
2062 * @default_port: true for default port VSI, false for control port
2063 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2064 * @veb_seid: pointer to where to put the resulting VEB SEID
2065 * @cmd_details: pointer to command details structure or NULL
2067 * This asks the FW to add a VEB between the uplink and downlink
2068 * elements. If the uplink SEID is 0, this will be a floating VEB.
2070 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2071 u16 downlink_seid, u8 enabled_tc,
2072 bool default_port, bool enable_l2_filtering,
2074 struct i40e_asq_cmd_details *cmd_details)
2076 struct i40e_aq_desc desc;
2077 struct i40e_aqc_add_veb *cmd =
2078 (struct i40e_aqc_add_veb *)&desc.params.raw;
2079 struct i40e_aqc_add_veb_completion *resp =
2080 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2081 enum i40e_status_code status;
2084 /* SEIDs need to either both be set or both be 0 for floating VEB */
2085 if (!!uplink_seid != !!downlink_seid)
2086 return I40E_ERR_PARAM;
2088 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2090 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2091 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2092 cmd->enable_tcs = enabled_tc;
2094 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2096 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2098 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2100 if (enable_l2_filtering)
2101 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2103 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2105 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2107 if (!status && veb_seid)
2108 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2114 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2115 * @hw: pointer to the hw struct
2116 * @veb_seid: the SEID of the VEB to query
2117 * @switch_id: the uplink switch id
2118 * @floating: set to true if the VEB is floating
2119 * @statistic_index: index of the stats counter block for this VEB
2120 * @vebs_used: number of VEB's used by function
2121 * @vebs_free: total VEB's not reserved by any function
2122 * @cmd_details: pointer to command details structure or NULL
2124 * This retrieves the parameters for a particular VEB, specified by
2125 * uplink_seid, and returns them to the caller.
2127 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2128 u16 veb_seid, u16 *switch_id,
2129 bool *floating, u16 *statistic_index,
2130 u16 *vebs_used, u16 *vebs_free,
2131 struct i40e_asq_cmd_details *cmd_details)
2133 struct i40e_aq_desc desc;
2134 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2135 (struct i40e_aqc_get_veb_parameters_completion *)
2137 enum i40e_status_code status;
2140 return I40E_ERR_PARAM;
2142 i40e_fill_default_direct_cmd_desc(&desc,
2143 i40e_aqc_opc_get_veb_parameters);
2144 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2146 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2151 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2152 if (statistic_index)
2153 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2155 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2157 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2159 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2160 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2171 * i40e_aq_add_macvlan
2172 * @hw: pointer to the hw struct
2173 * @seid: VSI for the mac address
2174 * @mv_list: list of macvlans to be added
2175 * @count: length of the list
2176 * @cmd_details: pointer to command details structure or NULL
2178 * Add MAC/VLAN addresses to the HW filtering
2180 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2181 struct i40e_aqc_add_macvlan_element_data *mv_list,
2182 u16 count, struct i40e_asq_cmd_details *cmd_details)
2184 struct i40e_aq_desc desc;
2185 struct i40e_aqc_macvlan *cmd =
2186 (struct i40e_aqc_macvlan *)&desc.params.raw;
2187 enum i40e_status_code status;
2190 if (count == 0 || !mv_list || !hw)
2191 return I40E_ERR_PARAM;
2193 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2195 /* prep the rest of the request */
2196 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2197 cmd->num_addresses = CPU_TO_LE16(count);
2198 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2202 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2203 if (buf_size > I40E_AQ_LARGE_BUF)
2204 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2206 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2213 * i40e_aq_remove_macvlan
2214 * @hw: pointer to the hw struct
2215 * @seid: VSI for the mac address
2216 * @mv_list: list of macvlans to be removed
2217 * @count: length of the list
2218 * @cmd_details: pointer to command details structure or NULL
2220 * Remove MAC/VLAN addresses from the HW filtering
2222 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2223 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2224 u16 count, struct i40e_asq_cmd_details *cmd_details)
2226 struct i40e_aq_desc desc;
2227 struct i40e_aqc_macvlan *cmd =
2228 (struct i40e_aqc_macvlan *)&desc.params.raw;
2229 enum i40e_status_code status;
2232 if (count == 0 || !mv_list || !hw)
2233 return I40E_ERR_PARAM;
2235 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2237 /* prep the rest of the request */
2238 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2239 cmd->num_addresses = CPU_TO_LE16(count);
2240 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2244 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2245 if (buf_size > I40E_AQ_LARGE_BUF)
2246 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2248 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2255 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2256 * @hw: pointer to the hw struct
2257 * @seid: VSI for the vlan filters
2258 * @v_list: list of vlan filters to be added
2259 * @count: length of the list
2260 * @cmd_details: pointer to command details structure or NULL
2262 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2263 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2264 u8 count, struct i40e_asq_cmd_details *cmd_details)
2266 struct i40e_aq_desc desc;
2267 struct i40e_aqc_macvlan *cmd =
2268 (struct i40e_aqc_macvlan *)&desc.params.raw;
2269 enum i40e_status_code status;
2272 if (count == 0 || !v_list || !hw)
2273 return I40E_ERR_PARAM;
2275 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2277 /* prep the rest of the request */
2278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2279 cmd->num_addresses = CPU_TO_LE16(count);
2280 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2284 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2285 if (buf_size > I40E_AQ_LARGE_BUF)
2286 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2288 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2295 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2296 * @hw: pointer to the hw struct
2297 * @seid: VSI for the vlan filters
2298 * @v_list: list of macvlans to be removed
2299 * @count: length of the list
2300 * @cmd_details: pointer to command details structure or NULL
2302 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2303 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2304 u8 count, struct i40e_asq_cmd_details *cmd_details)
2306 struct i40e_aq_desc desc;
2307 struct i40e_aqc_macvlan *cmd =
2308 (struct i40e_aqc_macvlan *)&desc.params.raw;
2309 enum i40e_status_code status;
2312 if (count == 0 || !v_list || !hw)
2313 return I40E_ERR_PARAM;
2315 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2317 /* prep the rest of the request */
2318 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2319 cmd->num_addresses = CPU_TO_LE16(count);
2320 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2324 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2325 if (buf_size > I40E_AQ_LARGE_BUF)
2326 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2328 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2335 * i40e_aq_send_msg_to_vf
2336 * @hw: pointer to the hardware structure
2337 * @vfid: vf id to send msg
2338 * @v_opcode: opcodes for VF-PF communication
2339 * @v_retval: return error code
2340 * @msg: pointer to the msg buffer
2341 * @msglen: msg length
2342 * @cmd_details: pointer to command details
2346 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2347 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2348 struct i40e_asq_cmd_details *cmd_details)
2350 struct i40e_aq_desc desc;
2351 struct i40e_aqc_pf_vf_message *cmd =
2352 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2353 enum i40e_status_code status;
2355 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2356 cmd->id = CPU_TO_LE32(vfid);
2357 desc.cookie_high = CPU_TO_LE32(v_opcode);
2358 desc.cookie_low = CPU_TO_LE32(v_retval);
2359 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2361 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2363 if (msglen > I40E_AQ_LARGE_BUF)
2364 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2365 desc.datalen = CPU_TO_LE16(msglen);
2367 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2373 * i40e_aq_debug_read_register
2374 * @hw: pointer to the hw struct
2375 * @reg_addr: register address
2376 * @reg_val: register value
2377 * @cmd_details: pointer to command details structure or NULL
2379 * Read the register using the admin queue commands
2381 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2382 u32 reg_addr, u64 *reg_val,
2383 struct i40e_asq_cmd_details *cmd_details)
2385 struct i40e_aq_desc desc;
2386 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2387 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2388 enum i40e_status_code status;
2390 if (reg_val == NULL)
2391 return I40E_ERR_PARAM;
2393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2395 cmd_resp->address = CPU_TO_LE32(reg_addr);
2397 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2399 if (status == I40E_SUCCESS) {
2400 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2401 (u64)LE32_TO_CPU(cmd_resp->value_low);
2408 * i40e_aq_debug_write_register
2409 * @hw: pointer to the hw struct
2410 * @reg_addr: register address
2411 * @reg_val: register value
2412 * @cmd_details: pointer to command details structure or NULL
2414 * Write to a register using the admin queue commands
2416 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2417 u32 reg_addr, u64 reg_val,
2418 struct i40e_asq_cmd_details *cmd_details)
2420 struct i40e_aq_desc desc;
2421 struct i40e_aqc_debug_reg_read_write *cmd =
2422 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2423 enum i40e_status_code status;
2425 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2427 cmd->address = CPU_TO_LE32(reg_addr);
2428 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2429 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2431 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2437 * i40e_aq_get_hmc_resource_profile
2438 * @hw: pointer to the hw struct
2439 * @profile: type of profile the HMC is to be set as
2440 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2441 * @cmd_details: pointer to command details structure or NULL
2443 * query the HMC profile of the device.
2445 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2446 enum i40e_aq_hmc_profile *profile,
2447 u8 *pe_vf_enabled_count,
2448 struct i40e_asq_cmd_details *cmd_details)
2450 struct i40e_aq_desc desc;
2451 struct i40e_aq_get_set_hmc_resource_profile *resp =
2452 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2453 enum i40e_status_code status;
2455 i40e_fill_default_direct_cmd_desc(&desc,
2456 i40e_aqc_opc_query_hmc_resource_profile);
2457 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2459 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2460 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2461 *pe_vf_enabled_count = resp->pe_vf_enabled &
2462 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2468 * i40e_aq_set_hmc_resource_profile
2469 * @hw: pointer to the hw struct
2470 * @profile: type of profile the HMC is to be set as
2471 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2472 * @cmd_details: pointer to command details structure or NULL
2474 * set the HMC profile of the device.
2476 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2477 enum i40e_aq_hmc_profile profile,
2478 u8 pe_vf_enabled_count,
2479 struct i40e_asq_cmd_details *cmd_details)
2481 struct i40e_aq_desc desc;
2482 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2483 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2484 enum i40e_status_code status;
2486 i40e_fill_default_direct_cmd_desc(&desc,
2487 i40e_aqc_opc_set_hmc_resource_profile);
2489 cmd->pm_profile = (u8)profile;
2490 cmd->pe_vf_enabled = pe_vf_enabled_count;
2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 * i40e_aq_request_resource
2499 * @hw: pointer to the hw struct
2500 * @resource: resource id
2501 * @access: access type
2502 * @sdp_number: resource number
2503 * @timeout: the maximum time in ms that the driver may hold the resource
2504 * @cmd_details: pointer to command details structure or NULL
2506 * requests common resource using the admin queue commands
2508 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2509 enum i40e_aq_resources_ids resource,
2510 enum i40e_aq_resource_access_type access,
2511 u8 sdp_number, u64 *timeout,
2512 struct i40e_asq_cmd_details *cmd_details)
2514 struct i40e_aq_desc desc;
2515 struct i40e_aqc_request_resource *cmd_resp =
2516 (struct i40e_aqc_request_resource *)&desc.params.raw;
2517 enum i40e_status_code status;
2519 DEBUGFUNC("i40e_aq_request_resource");
2521 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2523 cmd_resp->resource_id = CPU_TO_LE16(resource);
2524 cmd_resp->access_type = CPU_TO_LE16(access);
2525 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2527 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2528 /* The completion specifies the maximum time in ms that the driver
2529 * may hold the resource in the Timeout field.
2530 * If the resource is held by someone else, the command completes with
2531 * busy return value and the timeout field indicates the maximum time
2532 * the current owner of the resource has to free it.
2534 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2535 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2541 * i40e_aq_release_resource
2542 * @hw: pointer to the hw struct
2543 * @resource: resource id
2544 * @sdp_number: resource number
2545 * @cmd_details: pointer to command details structure or NULL
2547 * release common resource using the admin queue commands
2549 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2550 enum i40e_aq_resources_ids resource,
2552 struct i40e_asq_cmd_details *cmd_details)
2554 struct i40e_aq_desc desc;
2555 struct i40e_aqc_request_resource *cmd =
2556 (struct i40e_aqc_request_resource *)&desc.params.raw;
2557 enum i40e_status_code status;
2559 DEBUGFUNC("i40e_aq_release_resource");
2561 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2563 cmd->resource_id = CPU_TO_LE16(resource);
2564 cmd->resource_number = CPU_TO_LE32(sdp_number);
2566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2573 * @hw: pointer to the hw struct
2574 * @module_pointer: module pointer location in words from the NVM beginning
2575 * @offset: byte offset from the module beginning
2576 * @length: length of the section to be read (in bytes from the offset)
2577 * @data: command buffer (size [bytes] = length)
2578 * @last_command: tells if this is the last command in a series
2579 * @cmd_details: pointer to command details structure or NULL
2581 * Read the NVM using the admin queue commands
2583 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2584 u32 offset, u16 length, void *data,
2586 struct i40e_asq_cmd_details *cmd_details)
2588 struct i40e_aq_desc desc;
2589 struct i40e_aqc_nvm_update *cmd =
2590 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2591 enum i40e_status_code status;
2593 DEBUGFUNC("i40e_aq_read_nvm");
2595 /* In offset the highest byte must be zeroed. */
2596 if (offset & 0xFF000000) {
2597 status = I40E_ERR_PARAM;
2598 goto i40e_aq_read_nvm_exit;
2601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2603 /* If this is the last command in a series, set the proper flag. */
2605 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2606 cmd->module_pointer = module_pointer;
2607 cmd->offset = CPU_TO_LE32(offset);
2608 cmd->length = CPU_TO_LE16(length);
2610 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2611 if (length > I40E_AQ_LARGE_BUF)
2612 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2614 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2616 i40e_aq_read_nvm_exit:
2622 * @hw: pointer to the hw struct
2623 * @module_pointer: module pointer location in words from the NVM beginning
2624 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2625 * @length: length of the section to be erased (expressed in 4 KB)
2626 * @last_command: tells if this is the last command in a series
2627 * @cmd_details: pointer to command details structure or NULL
2629 * Erase the NVM sector using the admin queue commands
2631 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2632 u32 offset, u16 length, bool last_command,
2633 struct i40e_asq_cmd_details *cmd_details)
2635 struct i40e_aq_desc desc;
2636 struct i40e_aqc_nvm_update *cmd =
2637 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2638 enum i40e_status_code status;
2640 DEBUGFUNC("i40e_aq_erase_nvm");
2642 /* In offset the highest byte must be zeroed. */
2643 if (offset & 0xFF000000) {
2644 status = I40E_ERR_PARAM;
2645 goto i40e_aq_erase_nvm_exit;
2648 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2650 /* If this is the last command in a series, set the proper flag. */
2652 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2653 cmd->module_pointer = module_pointer;
2654 cmd->offset = CPU_TO_LE32(offset);
2655 cmd->length = CPU_TO_LE16(length);
2657 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2659 i40e_aq_erase_nvm_exit:
2663 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2664 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2665 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2666 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2667 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2668 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2669 #define I40E_DEV_FUNC_CAP_VF 0x13
2670 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2671 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2672 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2673 #define I40E_DEV_FUNC_CAP_VSI 0x17
2674 #define I40E_DEV_FUNC_CAP_DCB 0x18
2675 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2676 #define I40E_DEV_FUNC_CAP_RSS 0x40
2677 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2678 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2679 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2680 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2681 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2682 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2683 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2684 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2685 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2686 #define I40E_DEV_FUNC_CAP_LED 0x61
2687 #define I40E_DEV_FUNC_CAP_SDP 0x62
2688 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2691 * i40e_parse_discover_capabilities
2692 * @hw: pointer to the hw struct
2693 * @buff: pointer to a buffer containing device/function capability records
2694 * @cap_count: number of capability records in the list
2695 * @list_type_opc: type of capabilities list to parse
2697 * Parse the device/function capabilities list.
2699 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2701 enum i40e_admin_queue_opc list_type_opc)
2703 struct i40e_aqc_list_capabilities_element_resp *cap;
2704 u32 valid_functions, num_functions;
2705 u32 number, logical_id, phys_id;
2706 struct i40e_hw_capabilities *p;
2710 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2712 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2713 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2714 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2715 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2719 for (i = 0; i < cap_count; i++, cap++) {
2720 id = LE16_TO_CPU(cap->id);
2721 number = LE32_TO_CPU(cap->number);
2722 logical_id = LE32_TO_CPU(cap->logical_id);
2723 phys_id = LE32_TO_CPU(cap->phys_id);
2726 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2727 p->switch_mode = number;
2729 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2730 p->management_mode = number;
2732 case I40E_DEV_FUNC_CAP_NPAR:
2733 p->npar_enable = number;
2735 case I40E_DEV_FUNC_CAP_OS2BMC:
2738 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2739 p->valid_functions = number;
2741 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2743 p->sr_iov_1_1 = true;
2745 case I40E_DEV_FUNC_CAP_VF:
2746 p->num_vfs = number;
2747 p->vf_base_id = logical_id;
2749 case I40E_DEV_FUNC_CAP_VMDQ:
2753 case I40E_DEV_FUNC_CAP_802_1_QBG:
2755 p->evb_802_1_qbg = true;
2757 case I40E_DEV_FUNC_CAP_802_1_QBH:
2759 p->evb_802_1_qbh = true;
2761 case I40E_DEV_FUNC_CAP_VSI:
2762 p->num_vsis = number;
2764 case I40E_DEV_FUNC_CAP_DCB:
2767 p->enabled_tcmap = logical_id;
2771 case I40E_DEV_FUNC_CAP_FCOE:
2775 case I40E_DEV_FUNC_CAP_RSS:
2777 p->rss_table_size = number;
2778 p->rss_table_entry_width = logical_id;
2780 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2781 p->num_rx_qp = number;
2782 p->base_queue = phys_id;
2784 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2785 p->num_tx_qp = number;
2786 p->base_queue = phys_id;
2788 case I40E_DEV_FUNC_CAP_MSIX:
2789 p->num_msix_vectors = number;
2791 case I40E_DEV_FUNC_CAP_MSIX_VF:
2792 p->num_msix_vectors_vf = number;
2794 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2796 p->mfp_mode_1 = true;
2798 case I40E_DEV_FUNC_CAP_CEM:
2802 case I40E_DEV_FUNC_CAP_IWARP:
2806 case I40E_DEV_FUNC_CAP_LED:
2807 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2808 p->led[phys_id] = true;
2810 case I40E_DEV_FUNC_CAP_SDP:
2811 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2812 p->sdp[phys_id] = true;
2814 case I40E_DEV_FUNC_CAP_MDIO:
2816 p->mdio_port_num = phys_id;
2817 p->mdio_port_mode = logical_id;
2820 case I40E_DEV_FUNC_CAP_IEEE_1588:
2822 p->ieee_1588 = true;
2824 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2826 p->fd_filters_guaranteed = number;
2827 p->fd_filters_best_effort = logical_id;
2834 #ifdef I40E_FCOE_ENA
2835 /* Software override ensuring FCoE is disabled if npar or mfp
2836 * mode because it is not supported in these modes.
2838 if (p->npar_enable || p->mfp_mode_1)
2841 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2845 /* count the enabled ports (aka the "not disabled" ports) */
2847 for (i = 0; i < 4; i++) {
2848 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2851 /* use AQ read to get the physical register offset instead
2852 * of the port relative offset
2854 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2855 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2859 valid_functions = p->valid_functions;
2861 while (valid_functions) {
2862 if (valid_functions & 1)
2864 valid_functions >>= 1;
2867 /* partition id is 1-based, and functions are evenly spread
2868 * across the ports as partitions
2870 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2871 hw->num_partitions = num_functions / hw->num_ports;
2873 /* additional HW specific goodies that might
2874 * someday be HW version specific
2876 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2880 * i40e_aq_discover_capabilities
2881 * @hw: pointer to the hw struct
2882 * @buff: a virtual buffer to hold the capabilities
2883 * @buff_size: Size of the virtual buffer
2884 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2885 * @list_type_opc: capabilities type to discover - pass in the command opcode
2886 * @cmd_details: pointer to command details structure or NULL
2888 * Get the device capabilities descriptions from the firmware
2890 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2891 void *buff, u16 buff_size, u16 *data_size,
2892 enum i40e_admin_queue_opc list_type_opc,
2893 struct i40e_asq_cmd_details *cmd_details)
2895 struct i40e_aqc_list_capabilites *cmd;
2896 struct i40e_aq_desc desc;
2897 enum i40e_status_code status = I40E_SUCCESS;
2899 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2901 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2902 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2903 status = I40E_ERR_PARAM;
2907 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2909 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2910 if (buff_size > I40E_AQ_LARGE_BUF)
2911 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2913 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2914 *data_size = LE16_TO_CPU(desc.datalen);
2919 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2927 * i40e_aq_update_nvm
2928 * @hw: pointer to the hw struct
2929 * @module_pointer: module pointer location in words from the NVM beginning
2930 * @offset: byte offset from the module beginning
2931 * @length: length of the section to be written (in bytes from the offset)
2932 * @data: command buffer (size [bytes] = length)
2933 * @last_command: tells if this is the last command in a series
2934 * @cmd_details: pointer to command details structure or NULL
2936 * Update the NVM using the admin queue commands
2938 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2939 u32 offset, u16 length, void *data,
2941 struct i40e_asq_cmd_details *cmd_details)
2943 struct i40e_aq_desc desc;
2944 struct i40e_aqc_nvm_update *cmd =
2945 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2946 enum i40e_status_code status;
2948 DEBUGFUNC("i40e_aq_update_nvm");
2950 /* In offset the highest byte must be zeroed. */
2951 if (offset & 0xFF000000) {
2952 status = I40E_ERR_PARAM;
2953 goto i40e_aq_update_nvm_exit;
2956 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2958 /* If this is the last command in a series, set the proper flag. */
2960 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2961 cmd->module_pointer = module_pointer;
2962 cmd->offset = CPU_TO_LE32(offset);
2963 cmd->length = CPU_TO_LE16(length);
2965 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2966 if (length > I40E_AQ_LARGE_BUF)
2967 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2969 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2971 i40e_aq_update_nvm_exit:
2976 * i40e_aq_get_lldp_mib
2977 * @hw: pointer to the hw struct
2978 * @bridge_type: type of bridge requested
2979 * @mib_type: Local, Remote or both Local and Remote MIBs
2980 * @buff: pointer to a user supplied buffer to store the MIB block
2981 * @buff_size: size of the buffer (in bytes)
2982 * @local_len : length of the returned Local LLDP MIB
2983 * @remote_len: length of the returned Remote LLDP MIB
2984 * @cmd_details: pointer to command details structure or NULL
2986 * Requests the complete LLDP MIB (entire packet).
2988 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2989 u8 mib_type, void *buff, u16 buff_size,
2990 u16 *local_len, u16 *remote_len,
2991 struct i40e_asq_cmd_details *cmd_details)
2993 struct i40e_aq_desc desc;
2994 struct i40e_aqc_lldp_get_mib *cmd =
2995 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2996 struct i40e_aqc_lldp_get_mib *resp =
2997 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2998 enum i40e_status_code status;
3000 if (buff_size == 0 || !buff)
3001 return I40E_ERR_PARAM;
3003 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3004 /* Indirect Command */
3005 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3007 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3008 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3009 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3011 desc.datalen = CPU_TO_LE16(buff_size);
3013 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3014 if (buff_size > I40E_AQ_LARGE_BUF)
3015 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3017 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3019 if (local_len != NULL)
3020 *local_len = LE16_TO_CPU(resp->local_len);
3021 if (remote_len != NULL)
3022 *remote_len = LE16_TO_CPU(resp->remote_len);
3029 * i40e_aq_cfg_lldp_mib_change_event
3030 * @hw: pointer to the hw struct
3031 * @enable_update: Enable or Disable event posting
3032 * @cmd_details: pointer to command details structure or NULL
3034 * Enable or Disable posting of an event on ARQ when LLDP MIB
3035 * associated with the interface changes
3037 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3039 struct i40e_asq_cmd_details *cmd_details)
3041 struct i40e_aq_desc desc;
3042 struct i40e_aqc_lldp_update_mib *cmd =
3043 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3044 enum i40e_status_code status;
3046 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3049 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3057 * i40e_aq_add_lldp_tlv
3058 * @hw: pointer to the hw struct
3059 * @bridge_type: type of bridge
3060 * @buff: buffer with TLV to add
3061 * @buff_size: length of the buffer
3062 * @tlv_len: length of the TLV to be added
3063 * @mib_len: length of the LLDP MIB returned in response
3064 * @cmd_details: pointer to command details structure or NULL
3066 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3067 * it is responsibility of the caller to make sure that the TLV is not
3068 * already present in the LLDPDU.
3069 * In return firmware will write the complete LLDP MIB with the newly
3070 * added TLV in the response buffer.
3072 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3073 void *buff, u16 buff_size, u16 tlv_len,
3075 struct i40e_asq_cmd_details *cmd_details)
3077 struct i40e_aq_desc desc;
3078 struct i40e_aqc_lldp_add_tlv *cmd =
3079 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3080 enum i40e_status_code status;
3082 if (buff_size == 0 || !buff || tlv_len == 0)
3083 return I40E_ERR_PARAM;
3085 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3087 /* Indirect Command */
3088 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3089 if (buff_size > I40E_AQ_LARGE_BUF)
3090 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3091 desc.datalen = CPU_TO_LE16(buff_size);
3093 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3094 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3095 cmd->len = CPU_TO_LE16(tlv_len);
3097 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3099 if (mib_len != NULL)
3100 *mib_len = LE16_TO_CPU(desc.datalen);
3107 * i40e_aq_update_lldp_tlv
3108 * @hw: pointer to the hw struct
3109 * @bridge_type: type of bridge
3110 * @buff: buffer with TLV to update
3111 * @buff_size: size of the buffer holding original and updated TLVs
3112 * @old_len: Length of the Original TLV
3113 * @new_len: Length of the Updated TLV
3114 * @offset: offset of the updated TLV in the buff
3115 * @mib_len: length of the returned LLDP MIB
3116 * @cmd_details: pointer to command details structure or NULL
3118 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3119 * Firmware will place the complete LLDP MIB in response buffer with the
3122 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3123 u8 bridge_type, void *buff, u16 buff_size,
3124 u16 old_len, u16 new_len, u16 offset,
3126 struct i40e_asq_cmd_details *cmd_details)
3128 struct i40e_aq_desc desc;
3129 struct i40e_aqc_lldp_update_tlv *cmd =
3130 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3131 enum i40e_status_code status;
3133 if (buff_size == 0 || !buff || offset == 0 ||
3134 old_len == 0 || new_len == 0)
3135 return I40E_ERR_PARAM;
3137 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3139 /* Indirect Command */
3140 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3141 if (buff_size > I40E_AQ_LARGE_BUF)
3142 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3143 desc.datalen = CPU_TO_LE16(buff_size);
3145 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3146 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3147 cmd->old_len = CPU_TO_LE16(old_len);
3148 cmd->new_offset = CPU_TO_LE16(offset);
3149 cmd->new_len = CPU_TO_LE16(new_len);
3151 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3153 if (mib_len != NULL)
3154 *mib_len = LE16_TO_CPU(desc.datalen);
3161 * i40e_aq_delete_lldp_tlv
3162 * @hw: pointer to the hw struct
3163 * @bridge_type: type of bridge
3164 * @buff: pointer to a user supplied buffer that has the TLV
3165 * @buff_size: length of the buffer
3166 * @tlv_len: length of the TLV to be deleted
3167 * @mib_len: length of the returned LLDP MIB
3168 * @cmd_details: pointer to command details structure or NULL
3170 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3171 * The firmware places the entire LLDP MIB in the response buffer.
3173 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3174 u8 bridge_type, void *buff, u16 buff_size,
3175 u16 tlv_len, u16 *mib_len,
3176 struct i40e_asq_cmd_details *cmd_details)
3178 struct i40e_aq_desc desc;
3179 struct i40e_aqc_lldp_add_tlv *cmd =
3180 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3181 enum i40e_status_code status;
3183 if (buff_size == 0 || !buff)
3184 return I40E_ERR_PARAM;
3186 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3188 /* Indirect Command */
3189 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3190 if (buff_size > I40E_AQ_LARGE_BUF)
3191 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3192 desc.datalen = CPU_TO_LE16(buff_size);
3193 cmd->len = CPU_TO_LE16(tlv_len);
3194 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3195 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3197 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3199 if (mib_len != NULL)
3200 *mib_len = LE16_TO_CPU(desc.datalen);
3208 * @hw: pointer to the hw struct
3209 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3210 * @cmd_details: pointer to command details structure or NULL
3212 * Stop or Shutdown the embedded LLDP Agent
3214 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3215 struct i40e_asq_cmd_details *cmd_details)
3217 struct i40e_aq_desc desc;
3218 struct i40e_aqc_lldp_stop *cmd =
3219 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3220 enum i40e_status_code status;
3222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3225 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3227 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3233 * i40e_aq_start_lldp
3234 * @hw: pointer to the hw struct
3235 * @cmd_details: pointer to command details structure or NULL
3237 * Start the embedded LLDP Agent on all ports.
3239 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3240 struct i40e_asq_cmd_details *cmd_details)
3242 struct i40e_aq_desc desc;
3243 struct i40e_aqc_lldp_start *cmd =
3244 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3245 enum i40e_status_code status;
3247 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3249 cmd->command = I40E_AQ_LLDP_AGENT_START;
3251 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3257 * i40e_aq_get_cee_dcb_config
3258 * @hw: pointer to the hw struct
3259 * @buff: response buffer that stores CEE operational configuration
3260 * @buff_size: size of the buffer passed
3261 * @cmd_details: pointer to command details structure or NULL
3263 * Get CEE DCBX mode operational configuration from firmware
3265 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3266 void *buff, u16 buff_size,
3267 struct i40e_asq_cmd_details *cmd_details)
3269 struct i40e_aq_desc desc;
3270 enum i40e_status_code status;
3272 if (buff_size == 0 || !buff)
3273 return I40E_ERR_PARAM;
3275 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3277 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3278 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3285 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3286 * @hw: pointer to the hw struct
3287 * @start_agent: True if DCBx Agent needs to be Started
3288 * False if DCBx Agent needs to be Stopped
3289 * @cmd_details: pointer to command details structure or NULL
3291 * Start/Stop the embedded dcbx Agent
3293 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3295 struct i40e_asq_cmd_details *cmd_details)
3297 struct i40e_aq_desc desc;
3298 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3299 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3301 enum i40e_status_code status;
3303 i40e_fill_default_direct_cmd_desc(&desc,
3304 i40e_aqc_opc_lldp_stop_start_spec_agent);
3307 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3315 * i40e_aq_add_udp_tunnel
3316 * @hw: pointer to the hw struct
3317 * @udp_port: the UDP port to add
3318 * @header_len: length of the tunneling header length in DWords
3319 * @protocol_index: protocol index type
3320 * @filter_index: pointer to filter index
3321 * @cmd_details: pointer to command details structure or NULL
3323 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3324 u16 udp_port, u8 protocol_index,
3326 struct i40e_asq_cmd_details *cmd_details)
3328 struct i40e_aq_desc desc;
3329 struct i40e_aqc_add_udp_tunnel *cmd =
3330 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3331 struct i40e_aqc_del_udp_tunnel_completion *resp =
3332 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3333 enum i40e_status_code status;
3335 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3337 cmd->udp_port = CPU_TO_LE16(udp_port);
3338 cmd->protocol_type = protocol_index;
3340 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3343 *filter_index = resp->index;
3349 * i40e_aq_del_udp_tunnel
3350 * @hw: pointer to the hw struct
3351 * @index: filter index
3352 * @cmd_details: pointer to command details structure or NULL
3354 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3355 struct i40e_asq_cmd_details *cmd_details)
3357 struct i40e_aq_desc desc;
3358 struct i40e_aqc_remove_udp_tunnel *cmd =
3359 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3360 enum i40e_status_code status;
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3372 * i40e_aq_get_switch_resource_alloc (0x0204)
3373 * @hw: pointer to the hw struct
3374 * @num_entries: pointer to u8 to store the number of resource entries returned
3375 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3376 * to store the resource information for all resource types. Each
3377 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3378 * @count: size, in bytes, of the buffer provided
3379 * @cmd_details: pointer to command details structure or NULL
3381 * Query the resources allocated to a function.
3383 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3385 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3387 struct i40e_asq_cmd_details *cmd_details)
3389 struct i40e_aq_desc desc;
3390 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3391 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3392 enum i40e_status_code status;
3394 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3396 i40e_fill_default_direct_cmd_desc(&desc,
3397 i40e_aqc_opc_get_switch_resource_alloc);
3399 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3400 if (length > I40E_AQ_LARGE_BUF)
3401 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3403 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3406 *num_entries = cmd_resp->num_entries;
3412 * i40e_aq_delete_element - Delete switch element
3413 * @hw: pointer to the hw struct
3414 * @seid: the SEID to delete from the switch
3415 * @cmd_details: pointer to command details structure or NULL
3417 * This deletes a switch element from the switch.
3419 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3420 struct i40e_asq_cmd_details *cmd_details)
3422 struct i40e_aq_desc desc;
3423 struct i40e_aqc_switch_seid *cmd =
3424 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3425 enum i40e_status_code status;
3428 return I40E_ERR_PARAM;
3430 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3432 cmd->seid = CPU_TO_LE16(seid);
3434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3440 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3441 * @hw: pointer to the hw struct
3442 * @flags: component flags
3443 * @mac_seid: uplink seid (MAC SEID)
3444 * @vsi_seid: connected vsi seid
3445 * @ret_seid: seid of create pv component
3447 * This instantiates an i40e port virtualizer with specified flags.
3448 * Depending on specified flags the port virtualizer can act as a
3449 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3451 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3452 u16 mac_seid, u16 vsi_seid,
3455 struct i40e_aq_desc desc;
3456 struct i40e_aqc_add_update_pv *cmd =
3457 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3458 struct i40e_aqc_add_update_pv_completion *resp =
3459 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3460 enum i40e_status_code status;
3463 return I40E_ERR_PARAM;
3465 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3466 cmd->command_flags = CPU_TO_LE16(flags);
3467 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3468 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3470 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3471 if (!status && ret_seid)
3472 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3478 * i40e_aq_add_tag - Add an S/E-tag
3479 * @hw: pointer to the hw struct
3480 * @direct_to_queue: should s-tag direct flow to a specific queue
3481 * @vsi_seid: VSI SEID to use this tag
3482 * @tag: value of the tag
3483 * @queue_num: queue number, only valid is direct_to_queue is true
3484 * @tags_used: return value, number of tags in use by this PF
3485 * @tags_free: return value, number of unallocated tags
3486 * @cmd_details: pointer to command details structure or NULL
3488 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3489 * the number of tags allocated by the PF, and the number of unallocated
3492 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3493 u16 vsi_seid, u16 tag, u16 queue_num,
3494 u16 *tags_used, u16 *tags_free,
3495 struct i40e_asq_cmd_details *cmd_details)
3497 struct i40e_aq_desc desc;
3498 struct i40e_aqc_add_tag *cmd =
3499 (struct i40e_aqc_add_tag *)&desc.params.raw;
3500 struct i40e_aqc_add_remove_tag_completion *resp =
3501 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3502 enum i40e_status_code status;
3505 return I40E_ERR_PARAM;
3507 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3509 cmd->seid = CPU_TO_LE16(vsi_seid);
3510 cmd->tag = CPU_TO_LE16(tag);
3511 if (direct_to_queue) {
3512 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3513 cmd->queue_number = CPU_TO_LE16(queue_num);
3516 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3519 if (tags_used != NULL)
3520 *tags_used = LE16_TO_CPU(resp->tags_used);
3521 if (tags_free != NULL)
3522 *tags_free = LE16_TO_CPU(resp->tags_free);
3529 * i40e_aq_remove_tag - Remove an S- or E-tag
3530 * @hw: pointer to the hw struct
3531 * @vsi_seid: VSI SEID this tag is associated with
3532 * @tag: value of the S-tag to delete
3533 * @tags_used: return value, number of tags in use by this PF
3534 * @tags_free: return value, number of unallocated tags
3535 * @cmd_details: pointer to command details structure or NULL
3537 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3538 * the number of tags allocated by the PF, and the number of unallocated
3541 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3542 u16 tag, u16 *tags_used, u16 *tags_free,
3543 struct i40e_asq_cmd_details *cmd_details)
3545 struct i40e_aq_desc desc;
3546 struct i40e_aqc_remove_tag *cmd =
3547 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3548 struct i40e_aqc_add_remove_tag_completion *resp =
3549 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3550 enum i40e_status_code status;
3553 return I40E_ERR_PARAM;
3555 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3557 cmd->seid = CPU_TO_LE16(vsi_seid);
3558 cmd->tag = CPU_TO_LE16(tag);
3560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3563 if (tags_used != NULL)
3564 *tags_used = LE16_TO_CPU(resp->tags_used);
3565 if (tags_free != NULL)
3566 *tags_free = LE16_TO_CPU(resp->tags_free);
3573 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3574 * @hw: pointer to the hw struct
3575 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3576 * @etag: value of E-tag to add
3577 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3578 * @buf: address of indirect buffer
3579 * @tags_used: return value, number of E-tags in use by this port
3580 * @tags_free: return value, number of unallocated M-tags
3581 * @cmd_details: pointer to command details structure or NULL
3583 * This associates a multicast E-tag to a port virtualizer. It will return
3584 * the number of tags allocated by the PF, and the number of unallocated
3587 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3588 * num_tags_in_buf long.
3590 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3591 u16 etag, u8 num_tags_in_buf, void *buf,
3592 u16 *tags_used, u16 *tags_free,
3593 struct i40e_asq_cmd_details *cmd_details)
3595 struct i40e_aq_desc desc;
3596 struct i40e_aqc_add_remove_mcast_etag *cmd =
3597 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3598 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3599 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3600 enum i40e_status_code status;
3601 u16 length = sizeof(u16) * num_tags_in_buf;
3603 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3604 return I40E_ERR_PARAM;
3606 i40e_fill_default_direct_cmd_desc(&desc,
3607 i40e_aqc_opc_add_multicast_etag);
3609 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3610 cmd->etag = CPU_TO_LE16(etag);
3611 cmd->num_unicast_etags = num_tags_in_buf;
3613 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3614 if (length > I40E_AQ_LARGE_BUF)
3615 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3617 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3620 if (tags_used != NULL)
3621 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3622 if (tags_free != NULL)
3623 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3630 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3631 * @hw: pointer to the hw struct
3632 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3633 * @etag: value of the E-tag to remove
3634 * @tags_used: return value, number of tags in use by this port
3635 * @tags_free: return value, number of unallocated tags
3636 * @cmd_details: pointer to command details structure or NULL
3638 * This deletes an E-tag from the port virtualizer. It will return
3639 * the number of tags allocated by the port, and the number of unallocated
3642 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3643 u16 etag, u16 *tags_used, u16 *tags_free,
3644 struct i40e_asq_cmd_details *cmd_details)
3646 struct i40e_aq_desc desc;
3647 struct i40e_aqc_add_remove_mcast_etag *cmd =
3648 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3649 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3650 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3651 enum i40e_status_code status;
3655 return I40E_ERR_PARAM;
3657 i40e_fill_default_direct_cmd_desc(&desc,
3658 i40e_aqc_opc_remove_multicast_etag);
3660 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3661 cmd->etag = CPU_TO_LE16(etag);
3663 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3666 if (tags_used != NULL)
3667 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3668 if (tags_free != NULL)
3669 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3676 * i40e_aq_update_tag - Update an S/E-tag
3677 * @hw: pointer to the hw struct
3678 * @vsi_seid: VSI SEID using this S-tag
3679 * @old_tag: old tag value
3680 * @new_tag: new tag value
3681 * @tags_used: return value, number of tags in use by this PF
3682 * @tags_free: return value, number of unallocated tags
3683 * @cmd_details: pointer to command details structure or NULL
3685 * This updates the value of the tag currently attached to this VSI
3686 * in the switch complex. It will return the number of tags allocated
3687 * by the PF, and the number of unallocated tags available.
3689 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3690 u16 old_tag, u16 new_tag, u16 *tags_used,
3692 struct i40e_asq_cmd_details *cmd_details)
3694 struct i40e_aq_desc desc;
3695 struct i40e_aqc_update_tag *cmd =
3696 (struct i40e_aqc_update_tag *)&desc.params.raw;
3697 struct i40e_aqc_update_tag_completion *resp =
3698 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3699 enum i40e_status_code status;
3702 return I40E_ERR_PARAM;
3704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3706 cmd->seid = CPU_TO_LE16(vsi_seid);
3707 cmd->old_tag = CPU_TO_LE16(old_tag);
3708 cmd->new_tag = CPU_TO_LE16(new_tag);
3710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3713 if (tags_used != NULL)
3714 *tags_used = LE16_TO_CPU(resp->tags_used);
3715 if (tags_free != NULL)
3716 *tags_free = LE16_TO_CPU(resp->tags_free);
3723 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3724 * @hw: pointer to the hw struct
3725 * @tcmap: TC map for request/release any ignore PFC condition
3726 * @request: request or release ignore PFC condition
3727 * @tcmap_ret: return TCs for which PFC is currently ignored
3728 * @cmd_details: pointer to command details structure or NULL
3730 * This sends out request/release to ignore PFC condition for a TC.
3731 * It will return the TCs for which PFC is currently ignored.
3733 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3734 bool request, u8 *tcmap_ret,
3735 struct i40e_asq_cmd_details *cmd_details)
3737 struct i40e_aq_desc desc;
3738 struct i40e_aqc_pfc_ignore *cmd_resp =
3739 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3740 enum i40e_status_code status;
3742 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3745 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3747 cmd_resp->tc_bitmap = tcmap;
3749 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3752 if (tcmap_ret != NULL)
3753 *tcmap_ret = cmd_resp->tc_bitmap;
3760 * i40e_aq_dcb_updated - DCB Updated Command
3761 * @hw: pointer to the hw struct
3762 * @cmd_details: pointer to command details structure or NULL
3764 * When LLDP is handled in PF this command is used by the PF
3765 * to notify EMP that a DCB setting is modified.
3766 * When LLDP is handled in EMP this command is used by the PF
3767 * to notify EMP whenever one of the following parameters get
3769 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3770 * - PCIRTT in PRTDCB_GENC.PCIRTT
3771 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3772 * EMP will return when the shared RPB settings have been
3773 * recomputed and modified. The retval field in the descriptor
3774 * will be set to 0 when RPB is modified.
3776 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3777 struct i40e_asq_cmd_details *cmd_details)
3779 struct i40e_aq_desc desc;
3780 enum i40e_status_code status;
3782 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3784 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3790 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3791 * @hw: pointer to the hw struct
3792 * @seid: defines the SEID of the switch for which the stats are requested
3793 * @vlan_id: the VLAN ID for which the statistics are requested
3794 * @stat_index: index of the statistics counters block assigned to this VLAN
3795 * @cmd_details: pointer to command details structure or NULL
3797 * XL710 supports 128 smonVlanStats counters.This command is used to
3798 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3801 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3802 u16 vlan_id, u16 *stat_index,
3803 struct i40e_asq_cmd_details *cmd_details)
3805 struct i40e_aq_desc desc;
3806 struct i40e_aqc_add_remove_statistics *cmd_resp =
3807 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3808 enum i40e_status_code status;
3810 if ((seid == 0) || (stat_index == NULL))
3811 return I40E_ERR_PARAM;
3813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3815 cmd_resp->seid = CPU_TO_LE16(seid);
3816 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3821 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3827 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3828 * @hw: pointer to the hw struct
3829 * @seid: defines the SEID of the switch for which the stats are requested
3830 * @vlan_id: the VLAN ID for which the statistics are requested
3831 * @stat_index: index of the statistics counters block assigned to this VLAN
3832 * @cmd_details: pointer to command details structure or NULL
3834 * XL710 supports 128 smonVlanStats counters.This command is used to
3835 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3838 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3839 u16 vlan_id, u16 stat_index,
3840 struct i40e_asq_cmd_details *cmd_details)
3842 struct i40e_aq_desc desc;
3843 struct i40e_aqc_add_remove_statistics *cmd =
3844 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3845 enum i40e_status_code status;
3848 return I40E_ERR_PARAM;
3850 i40e_fill_default_direct_cmd_desc(&desc,
3851 i40e_aqc_opc_remove_statistics);
3853 cmd->seid = CPU_TO_LE16(seid);
3854 cmd->vlan = CPU_TO_LE16(vlan_id);
3855 cmd->stat_index = CPU_TO_LE16(stat_index);
3857 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3863 * i40e_aq_set_port_parameters - set physical port parameters.
3864 * @hw: pointer to the hw struct
3865 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3866 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3867 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3868 * @double_vlan: if set double VLAN is enabled
3869 * @cmd_details: pointer to command details structure or NULL
3871 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3872 u16 bad_frame_vsi, bool save_bad_pac,
3873 bool pad_short_pac, bool double_vlan,
3874 struct i40e_asq_cmd_details *cmd_details)
3876 struct i40e_aqc_set_port_parameters *cmd;
3877 enum i40e_status_code status;
3878 struct i40e_aq_desc desc;
3879 u16 command_flags = 0;
3881 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3883 i40e_fill_default_direct_cmd_desc(&desc,
3884 i40e_aqc_opc_set_port_parameters);
3886 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3888 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3890 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3892 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3893 cmd->command_flags = CPU_TO_LE16(command_flags);
3895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3901 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3902 * @hw: pointer to the hw struct
3903 * @seid: seid for the physical port/switching component/vsi
3904 * @buff: Indirect buffer to hold data parameters and response
3905 * @buff_size: Indirect buffer size
3906 * @opcode: Tx scheduler AQ command opcode
3907 * @cmd_details: pointer to command details structure or NULL
3909 * Generic command handler for Tx scheduler AQ commands
3911 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3912 void *buff, u16 buff_size,
3913 enum i40e_admin_queue_opc opcode,
3914 struct i40e_asq_cmd_details *cmd_details)
3916 struct i40e_aq_desc desc;
3917 struct i40e_aqc_tx_sched_ind *cmd =
3918 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3919 enum i40e_status_code status;
3920 bool cmd_param_flag = false;
3923 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3924 case i40e_aqc_opc_configure_vsi_tc_bw:
3925 case i40e_aqc_opc_enable_switching_comp_ets:
3926 case i40e_aqc_opc_modify_switching_comp_ets:
3927 case i40e_aqc_opc_disable_switching_comp_ets:
3928 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3929 case i40e_aqc_opc_configure_switching_comp_bw_config:
3930 cmd_param_flag = true;
3932 case i40e_aqc_opc_query_vsi_bw_config:
3933 case i40e_aqc_opc_query_vsi_ets_sla_config:
3934 case i40e_aqc_opc_query_switching_comp_ets_config:
3935 case i40e_aqc_opc_query_port_ets_config:
3936 case i40e_aqc_opc_query_switching_comp_bw_config:
3937 cmd_param_flag = false;
3940 return I40E_ERR_PARAM;
3943 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3945 /* Indirect command */
3946 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3948 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3949 if (buff_size > I40E_AQ_LARGE_BUF)
3950 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3952 desc.datalen = CPU_TO_LE16(buff_size);
3954 cmd->vsi_seid = CPU_TO_LE16(seid);
3956 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3962 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3963 * @hw: pointer to the hw struct
3965 * @credit: BW limit credits (0 = disabled)
3966 * @max_credit: Max BW limit credits
3967 * @cmd_details: pointer to command details structure or NULL
3969 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3970 u16 seid, u16 credit, u8 max_credit,
3971 struct i40e_asq_cmd_details *cmd_details)
3973 struct i40e_aq_desc desc;
3974 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3975 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3976 enum i40e_status_code status;
3978 i40e_fill_default_direct_cmd_desc(&desc,
3979 i40e_aqc_opc_configure_vsi_bw_limit);
3981 cmd->vsi_seid = CPU_TO_LE16(seid);
3982 cmd->credit = CPU_TO_LE16(credit);
3983 cmd->max_credit = max_credit;
3985 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3991 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3992 * @hw: pointer to the hw struct
3993 * @seid: switching component seid
3994 * @credit: BW limit credits (0 = disabled)
3995 * @max_bw: Max BW limit credits
3996 * @cmd_details: pointer to command details structure or NULL
3998 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3999 u16 seid, u16 credit, u8 max_bw,
4000 struct i40e_asq_cmd_details *cmd_details)
4002 struct i40e_aq_desc desc;
4003 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4004 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4005 enum i40e_status_code status;
4007 i40e_fill_default_direct_cmd_desc(&desc,
4008 i40e_aqc_opc_configure_switching_comp_bw_limit);
4010 cmd->seid = CPU_TO_LE16(seid);
4011 cmd->credit = CPU_TO_LE16(credit);
4012 cmd->max_bw = max_bw;
4014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4020 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4021 * @hw: pointer to the hw struct
4023 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4024 * @cmd_details: pointer to command details structure or NULL
4026 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4028 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4029 struct i40e_asq_cmd_details *cmd_details)
4031 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4032 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4037 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4038 * @hw: pointer to the hw struct
4040 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4041 * @cmd_details: pointer to command details structure or NULL
4043 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4045 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4046 struct i40e_asq_cmd_details *cmd_details)
4048 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4049 i40e_aqc_opc_configure_vsi_tc_bw,
4054 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4055 * @hw: pointer to the hw struct
4056 * @seid: seid of the switching component
4057 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4058 * @cmd_details: pointer to command details structure or NULL
4060 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4061 struct i40e_hw *hw, u16 seid,
4062 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4063 struct i40e_asq_cmd_details *cmd_details)
4065 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4066 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4071 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4072 * @hw: pointer to the hw struct
4073 * @seid: seid of the VSI
4074 * @bw_data: Buffer to hold VSI BW configuration
4075 * @cmd_details: pointer to command details structure or NULL
4077 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4079 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4080 struct i40e_asq_cmd_details *cmd_details)
4082 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4083 i40e_aqc_opc_query_vsi_bw_config,
4088 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4089 * @hw: pointer to the hw struct
4090 * @seid: seid of the VSI
4091 * @bw_data: Buffer to hold VSI BW configuration per TC
4092 * @cmd_details: pointer to command details structure or NULL
4094 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4096 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4097 struct i40e_asq_cmd_details *cmd_details)
4099 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4100 i40e_aqc_opc_query_vsi_ets_sla_config,
4105 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4106 * @hw: pointer to the hw struct
4107 * @seid: seid of the switching component
4108 * @bw_data: Buffer to hold switching component's per TC BW config
4109 * @cmd_details: pointer to command details structure or NULL
4111 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4113 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4114 struct i40e_asq_cmd_details *cmd_details)
4116 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4117 i40e_aqc_opc_query_switching_comp_ets_config,
4122 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4123 * @hw: pointer to the hw struct
4124 * @seid: seid of the VSI or switching component connected to Physical Port
4125 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4126 * @cmd_details: pointer to command details structure or NULL
4128 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4130 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4131 struct i40e_asq_cmd_details *cmd_details)
4133 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4134 i40e_aqc_opc_query_port_ets_config,
4139 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4140 * @hw: pointer to the hw struct
4141 * @seid: seid of the switching component
4142 * @bw_data: Buffer to hold switching component's BW configuration
4143 * @cmd_details: pointer to command details structure or NULL
4145 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4147 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4148 struct i40e_asq_cmd_details *cmd_details)
4150 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4151 i40e_aqc_opc_query_switching_comp_bw_config,
4156 * i40e_validate_filter_settings
4157 * @hw: pointer to the hardware structure
4158 * @settings: Filter control settings
4160 * Check and validate the filter control settings passed.
4161 * The function checks for the valid filter/context sizes being
4162 * passed for FCoE and PE.
4164 * Returns I40E_SUCCESS if the values passed are valid and within
4165 * range else returns an error.
4167 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4168 struct i40e_filter_control_settings *settings)
4170 u32 fcoe_cntx_size, fcoe_filt_size;
4171 u32 pe_cntx_size, pe_filt_size;
4176 /* Validate FCoE settings passed */
4177 switch (settings->fcoe_filt_num) {
4178 case I40E_HASH_FILTER_SIZE_1K:
4179 case I40E_HASH_FILTER_SIZE_2K:
4180 case I40E_HASH_FILTER_SIZE_4K:
4181 case I40E_HASH_FILTER_SIZE_8K:
4182 case I40E_HASH_FILTER_SIZE_16K:
4183 case I40E_HASH_FILTER_SIZE_32K:
4184 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4185 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4188 return I40E_ERR_PARAM;
4191 switch (settings->fcoe_cntx_num) {
4192 case I40E_DMA_CNTX_SIZE_512:
4193 case I40E_DMA_CNTX_SIZE_1K:
4194 case I40E_DMA_CNTX_SIZE_2K:
4195 case I40E_DMA_CNTX_SIZE_4K:
4196 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4197 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4200 return I40E_ERR_PARAM;
4203 /* Validate PE settings passed */
4204 switch (settings->pe_filt_num) {
4205 case I40E_HASH_FILTER_SIZE_1K:
4206 case I40E_HASH_FILTER_SIZE_2K:
4207 case I40E_HASH_FILTER_SIZE_4K:
4208 case I40E_HASH_FILTER_SIZE_8K:
4209 case I40E_HASH_FILTER_SIZE_16K:
4210 case I40E_HASH_FILTER_SIZE_32K:
4211 case I40E_HASH_FILTER_SIZE_64K:
4212 case I40E_HASH_FILTER_SIZE_128K:
4213 case I40E_HASH_FILTER_SIZE_256K:
4214 case I40E_HASH_FILTER_SIZE_512K:
4215 case I40E_HASH_FILTER_SIZE_1M:
4216 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4217 pe_filt_size <<= (u32)settings->pe_filt_num;
4220 return I40E_ERR_PARAM;
4223 switch (settings->pe_cntx_num) {
4224 case I40E_DMA_CNTX_SIZE_512:
4225 case I40E_DMA_CNTX_SIZE_1K:
4226 case I40E_DMA_CNTX_SIZE_2K:
4227 case I40E_DMA_CNTX_SIZE_4K:
4228 case I40E_DMA_CNTX_SIZE_8K:
4229 case I40E_DMA_CNTX_SIZE_16K:
4230 case I40E_DMA_CNTX_SIZE_32K:
4231 case I40E_DMA_CNTX_SIZE_64K:
4232 case I40E_DMA_CNTX_SIZE_128K:
4233 case I40E_DMA_CNTX_SIZE_256K:
4234 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4235 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4238 return I40E_ERR_PARAM;
4241 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4242 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4243 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4244 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4245 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4246 return I40E_ERR_INVALID_SIZE;
4248 return I40E_SUCCESS;
4252 * i40e_set_filter_control
4253 * @hw: pointer to the hardware structure
4254 * @settings: Filter control settings
4256 * Set the Queue Filters for PE/FCoE and enable filters required
4257 * for a single PF. It is expected that these settings are programmed
4258 * at the driver initialization time.
4260 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4261 struct i40e_filter_control_settings *settings)
4263 enum i40e_status_code ret = I40E_SUCCESS;
4264 u32 hash_lut_size = 0;
4268 return I40E_ERR_PARAM;
4270 /* Validate the input settings */
4271 ret = i40e_validate_filter_settings(hw, settings);
4275 /* Read the PF Queue Filter control register */
4276 val = rd32(hw, I40E_PFQF_CTL_0);
4278 /* Program required PE hash buckets for the PF */
4279 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4280 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4281 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4282 /* Program required PE contexts for the PF */
4283 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4284 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4285 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4287 /* Program required FCoE hash buckets for the PF */
4288 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4289 val |= ((u32)settings->fcoe_filt_num <<
4290 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4291 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4292 /* Program required FCoE DDP contexts for the PF */
4293 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4294 val |= ((u32)settings->fcoe_cntx_num <<
4295 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4296 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4298 /* Program Hash LUT size for the PF */
4299 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4300 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4302 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4303 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4305 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4306 if (settings->enable_fdir)
4307 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4308 if (settings->enable_ethtype)
4309 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4310 if (settings->enable_macvlan)
4311 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4313 wr32(hw, I40E_PFQF_CTL_0, val);
4315 return I40E_SUCCESS;
4319 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4320 * @hw: pointer to the hw struct
4321 * @mac_addr: MAC address to use in the filter
4322 * @ethtype: Ethertype to use in the filter
4323 * @flags: Flags that needs to be applied to the filter
4324 * @vsi_seid: seid of the control VSI
4325 * @queue: VSI queue number to send the packet to
4326 * @is_add: Add control packet filter if True else remove
4327 * @stats: Structure to hold information on control filter counts
4328 * @cmd_details: pointer to command details structure or NULL
4330 * This command will Add or Remove control packet filter for a control VSI.
4331 * In return it will update the total number of perfect filter count in
4334 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4335 u8 *mac_addr, u16 ethtype, u16 flags,
4336 u16 vsi_seid, u16 queue, bool is_add,
4337 struct i40e_control_filter_stats *stats,
4338 struct i40e_asq_cmd_details *cmd_details)
4340 struct i40e_aq_desc desc;
4341 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4342 (struct i40e_aqc_add_remove_control_packet_filter *)
4344 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4345 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4347 enum i40e_status_code status;
4350 return I40E_ERR_PARAM;
4353 i40e_fill_default_direct_cmd_desc(&desc,
4354 i40e_aqc_opc_add_control_packet_filter);
4355 cmd->queue = CPU_TO_LE16(queue);
4357 i40e_fill_default_direct_cmd_desc(&desc,
4358 i40e_aqc_opc_remove_control_packet_filter);
4362 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4363 I40E_NONDMA_TO_NONDMA);
4365 cmd->etype = CPU_TO_LE16(ethtype);
4366 cmd->flags = CPU_TO_LE16(flags);
4367 cmd->seid = CPU_TO_LE16(vsi_seid);
4369 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4371 if (!status && stats) {
4372 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4373 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4374 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4375 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4382 * i40e_aq_add_cloud_filters
4383 * @hw: pointer to the hardware structure
4384 * @seid: VSI seid to add cloud filters from
4385 * @filters: Buffer which contains the filters to be added
4386 * @filter_count: number of filters contained in the buffer
4388 * Set the cloud filters for a given VSI. The contents of the
4389 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4390 * in by the caller of the function.
4393 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4395 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4398 struct i40e_aq_desc desc;
4399 struct i40e_aqc_add_remove_cloud_filters *cmd =
4400 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4402 enum i40e_status_code status;
4404 i40e_fill_default_direct_cmd_desc(&desc,
4405 i40e_aqc_opc_add_cloud_filters);
4407 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4409 desc.datalen = CPU_TO_LE16(buff_len);
4410 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4411 cmd->num_filters = filter_count;
4412 cmd->seid = CPU_TO_LE16(seid);
4414 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4420 * i40e_aq_remove_cloud_filters
4421 * @hw: pointer to the hardware structure
4422 * @seid: VSI seid to remove cloud filters from
4423 * @filters: Buffer which contains the filters to be removed
4424 * @filter_count: number of filters contained in the buffer
4426 * Remove the cloud filters for a given VSI. The contents of the
4427 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4428 * in by the caller of the function.
4431 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4433 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4436 struct i40e_aq_desc desc;
4437 struct i40e_aqc_add_remove_cloud_filters *cmd =
4438 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4439 enum i40e_status_code status;
4442 i40e_fill_default_direct_cmd_desc(&desc,
4443 i40e_aqc_opc_remove_cloud_filters);
4445 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4447 desc.datalen = CPU_TO_LE16(buff_len);
4448 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4449 cmd->num_filters = filter_count;
4450 cmd->seid = CPU_TO_LE16(seid);
4452 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4458 * i40e_aq_alternate_write
4459 * @hw: pointer to the hardware structure
4460 * @reg_addr0: address of first dword to be read
4461 * @reg_val0: value to be written under 'reg_addr0'
4462 * @reg_addr1: address of second dword to be read
4463 * @reg_val1: value to be written under 'reg_addr1'
4465 * Write one or two dwords to alternate structure. Fields are indicated
4466 * by 'reg_addr0' and 'reg_addr1' register numbers.
4469 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4470 u32 reg_addr0, u32 reg_val0,
4471 u32 reg_addr1, u32 reg_val1)
4473 struct i40e_aq_desc desc;
4474 struct i40e_aqc_alternate_write *cmd_resp =
4475 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4476 enum i40e_status_code status;
4478 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4479 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4480 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4481 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4482 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4484 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4490 * i40e_aq_alternate_write_indirect
4491 * @hw: pointer to the hardware structure
4492 * @addr: address of a first register to be modified
4493 * @dw_count: number of alternate structure fields to write
4494 * @buffer: pointer to the command buffer
4496 * Write 'dw_count' dwords from 'buffer' to alternate structure
4497 * starting at 'addr'.
4500 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4501 u32 addr, u32 dw_count, void *buffer)
4503 struct i40e_aq_desc desc;
4504 struct i40e_aqc_alternate_ind_write *cmd_resp =
4505 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4506 enum i40e_status_code status;
4509 return I40E_ERR_PARAM;
4511 /* Indirect command */
4512 i40e_fill_default_direct_cmd_desc(&desc,
4513 i40e_aqc_opc_alternate_write_indirect);
4515 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4516 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4517 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4518 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4520 cmd_resp->address = CPU_TO_LE32(addr);
4521 cmd_resp->length = CPU_TO_LE32(dw_count);
4522 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4523 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4525 status = i40e_asq_send_command(hw, &desc, buffer,
4526 I40E_LO_DWORD(4*dw_count), NULL);
4532 * i40e_aq_alternate_read
4533 * @hw: pointer to the hardware structure
4534 * @reg_addr0: address of first dword to be read
4535 * @reg_val0: pointer for data read from 'reg_addr0'
4536 * @reg_addr1: address of second dword to be read
4537 * @reg_val1: pointer for data read from 'reg_addr1'
4539 * Read one or two dwords from alternate structure. Fields are indicated
4540 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4541 * is not passed then only register at 'reg_addr0' is read.
4544 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4545 u32 reg_addr0, u32 *reg_val0,
4546 u32 reg_addr1, u32 *reg_val1)
4548 struct i40e_aq_desc desc;
4549 struct i40e_aqc_alternate_write *cmd_resp =
4550 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4551 enum i40e_status_code status;
4553 if (reg_val0 == NULL)
4554 return I40E_ERR_PARAM;
4556 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4557 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4558 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4560 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4562 if (status == I40E_SUCCESS) {
4563 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4565 if (reg_val1 != NULL)
4566 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4573 * i40e_aq_alternate_read_indirect
4574 * @hw: pointer to the hardware structure
4575 * @addr: address of the alternate structure field
4576 * @dw_count: number of alternate structure fields to read
4577 * @buffer: pointer to the command buffer
4579 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4580 * place them in 'buffer'. The buffer should be allocated by caller.
4583 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4584 u32 addr, u32 dw_count, void *buffer)
4586 struct i40e_aq_desc desc;
4587 struct i40e_aqc_alternate_ind_write *cmd_resp =
4588 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4589 enum i40e_status_code status;
4592 return I40E_ERR_PARAM;
4594 /* Indirect command */
4595 i40e_fill_default_direct_cmd_desc(&desc,
4596 i40e_aqc_opc_alternate_read_indirect);
4598 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4599 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4600 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4601 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4603 cmd_resp->address = CPU_TO_LE32(addr);
4604 cmd_resp->length = CPU_TO_LE32(dw_count);
4605 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4606 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4608 status = i40e_asq_send_command(hw, &desc, buffer,
4609 I40E_LO_DWORD(4*dw_count), NULL);
4615 * i40e_aq_alternate_clear
4616 * @hw: pointer to the HW structure.
4618 * Clear the alternate structures of the port from which the function
4622 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4624 struct i40e_aq_desc desc;
4625 enum i40e_status_code status;
4627 i40e_fill_default_direct_cmd_desc(&desc,
4628 i40e_aqc_opc_alternate_clear_port);
4630 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4636 * i40e_aq_alternate_write_done
4637 * @hw: pointer to the HW structure.
4638 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4639 * @reset_needed: indicates the SW should trigger GLOBAL reset
4641 * Indicates to the FW that alternate structures have been changed.
4644 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4645 u8 bios_mode, bool *reset_needed)
4647 struct i40e_aq_desc desc;
4648 struct i40e_aqc_alternate_write_done *cmd =
4649 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4650 enum i40e_status_code status;
4652 if (reset_needed == NULL)
4653 return I40E_ERR_PARAM;
4655 i40e_fill_default_direct_cmd_desc(&desc,
4656 i40e_aqc_opc_alternate_write_done);
4658 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4660 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4662 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4663 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4669 * i40e_aq_set_oem_mode
4670 * @hw: pointer to the HW structure.
4671 * @oem_mode: the OEM mode to be used
4673 * Sets the device to a specific operating mode. Currently the only supported
4674 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4677 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4680 struct i40e_aq_desc desc;
4681 struct i40e_aqc_alternate_write_done *cmd =
4682 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4683 enum i40e_status_code status;
4685 i40e_fill_default_direct_cmd_desc(&desc,
4686 i40e_aqc_opc_alternate_set_mode);
4688 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4690 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4696 * i40e_aq_resume_port_tx
4697 * @hw: pointer to the hardware structure
4698 * @cmd_details: pointer to command details structure or NULL
4700 * Resume port's Tx traffic
4702 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4703 struct i40e_asq_cmd_details *cmd_details)
4705 struct i40e_aq_desc desc;
4706 enum i40e_status_code status;
4708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4716 * i40e_set_pci_config_data - store PCI bus info
4717 * @hw: pointer to hardware structure
4718 * @link_status: the link status word from PCI config space
4720 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4722 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4724 hw->bus.type = i40e_bus_type_pci_express;
4726 switch (link_status & I40E_PCI_LINK_WIDTH) {
4727 case I40E_PCI_LINK_WIDTH_1:
4728 hw->bus.width = i40e_bus_width_pcie_x1;
4730 case I40E_PCI_LINK_WIDTH_2:
4731 hw->bus.width = i40e_bus_width_pcie_x2;
4733 case I40E_PCI_LINK_WIDTH_4:
4734 hw->bus.width = i40e_bus_width_pcie_x4;
4736 case I40E_PCI_LINK_WIDTH_8:
4737 hw->bus.width = i40e_bus_width_pcie_x8;
4740 hw->bus.width = i40e_bus_width_unknown;
4744 switch (link_status & I40E_PCI_LINK_SPEED) {
4745 case I40E_PCI_LINK_SPEED_2500:
4746 hw->bus.speed = i40e_bus_speed_2500;
4748 case I40E_PCI_LINK_SPEED_5000:
4749 hw->bus.speed = i40e_bus_speed_5000;
4751 case I40E_PCI_LINK_SPEED_8000:
4752 hw->bus.speed = i40e_bus_speed_8000;
4755 hw->bus.speed = i40e_bus_speed_unknown;
4761 * i40e_read_bw_from_alt_ram
4762 * @hw: pointer to the hardware structure
4763 * @max_bw: pointer for max_bw read
4764 * @min_bw: pointer for min_bw read
4765 * @min_valid: pointer for bool that is true if min_bw is a valid value
4766 * @max_valid: pointer for bool that is true if max_bw is a valid value
4768 * Read bw from the alternate ram for the given pf
4770 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4771 u32 *max_bw, u32 *min_bw,
4772 bool *min_valid, bool *max_valid)
4774 enum i40e_status_code status;
4775 u32 max_bw_addr, min_bw_addr;
4777 /* Calculate the address of the min/max bw registers */
4778 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4779 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4780 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4781 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4782 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4783 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4785 /* Read the bandwidths from alt ram */
4786 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4787 min_bw_addr, min_bw);
4789 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4794 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4803 * i40e_aq_configure_partition_bw
4804 * @hw: pointer to the hardware structure
4805 * @bw_data: Buffer holding valid pfs and bw limits
4806 * @cmd_details: pointer to command details
4808 * Configure partitions guaranteed/max bw
4810 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4811 struct i40e_aqc_configure_partition_bw_data *bw_data,
4812 struct i40e_asq_cmd_details *cmd_details)
4814 enum i40e_status_code status;
4815 struct i40e_aq_desc desc;
4816 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4818 i40e_fill_default_direct_cmd_desc(&desc,
4819 i40e_aqc_opc_configure_partition_bw);
4821 /* Indirect command */
4822 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4823 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4825 if (bwd_size > I40E_AQ_LARGE_BUF)
4826 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4828 desc.datalen = CPU_TO_LE16(bwd_size);
4830 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4834 #endif /* PF_DRIVER */
4838 * i40e_aq_send_msg_to_pf
4839 * @hw: pointer to the hardware structure
4840 * @v_opcode: opcodes for VF-PF communication
4841 * @v_retval: return error code
4842 * @msg: pointer to the msg buffer
4843 * @msglen: msg length
4844 * @cmd_details: pointer to command details
4846 * Send message to PF driver using admin queue. By default, this message
4847 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4848 * completion before returning.
4850 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4851 enum i40e_virtchnl_ops v_opcode,
4852 enum i40e_status_code v_retval,
4853 u8 *msg, u16 msglen,
4854 struct i40e_asq_cmd_details *cmd_details)
4856 struct i40e_aq_desc desc;
4857 struct i40e_asq_cmd_details details;
4858 enum i40e_status_code status;
4860 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4861 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4862 desc.cookie_high = CPU_TO_LE32(v_opcode);
4863 desc.cookie_low = CPU_TO_LE32(v_retval);
4865 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4866 | I40E_AQ_FLAG_RD));
4867 if (msglen > I40E_AQ_LARGE_BUF)
4868 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4869 desc.datalen = CPU_TO_LE16(msglen);
4872 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4873 details.async = true;
4874 cmd_details = &details;
4876 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4877 msglen, cmd_details);
4882 * i40e_vf_parse_hw_config
4883 * @hw: pointer to the hardware structure
4884 * @msg: pointer to the virtual channel VF resource structure
4886 * Given a VF resource message from the PF, populate the hw struct
4887 * with appropriate information.
4889 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4890 struct i40e_virtchnl_vf_resource *msg)
4892 struct i40e_virtchnl_vsi_resource *vsi_res;
4895 vsi_res = &msg->vsi_res[0];
4897 hw->dev_caps.num_vsis = msg->num_vsis;
4898 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4899 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4900 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4901 hw->dev_caps.dcb = msg->vf_offload_flags &
4902 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4903 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4904 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4905 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4906 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4907 for (i = 0; i < msg->num_vsis; i++) {
4908 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4909 i40e_memcpy(hw->mac.perm_addr,
4910 vsi_res->default_mac_addr,
4911 I40E_ETH_LENGTH_OF_ADDRESS,
4912 I40E_NONDMA_TO_NONDMA);
4913 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4914 I40E_ETH_LENGTH_OF_ADDRESS,
4915 I40E_NONDMA_TO_NONDMA);
4923 * @hw: pointer to the hardware structure
4925 * Send a VF_RESET message to the PF. Does not wait for response from PF
4926 * as none will be forthcoming. Immediately after calling this function,
4927 * the admin queue should be shut down and (optionally) reinitialized.
4929 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4931 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4932 I40E_SUCCESS, NULL, 0, NULL);
4934 #endif /* VF_DRIVER */