1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
40 * i40e_set_mac_type - Sets MAC type
41 * @hw: pointer to the HW structure
43 * This function sets the mac type of the adapter based on the
44 * vendor ID and device ID stored in the hw structure.
46 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
52 enum i40e_status_code status = I40E_SUCCESS;
54 DEBUGFUNC("i40e_set_mac_type\n");
56 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
57 switch (hw->device_id) {
58 case I40E_DEV_ID_SFP_XL710:
59 case I40E_DEV_ID_QEMU:
60 case I40E_DEV_ID_KX_A:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 hw->mac.type = I40E_MAC_XL710;
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
74 hw->mac.type = I40E_MAC_GENERIC;
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
88 * @hw: debug mask related to admin queue
90 * @desc: pointer to admin queue descriptor
91 * @buffer: pointer to command buffer
92 * @buf_len: max length of buffer
94 * Dumps debug log about adminq command with descriptor contents.
96 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
97 void *buffer, u16 buf_len)
99 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
100 u16 len = LE16_TO_CPU(aq_desc->datalen);
101 u8 *buf = (u8 *)buffer;
104 if ((!(mask & hw->debug_mask)) || (desc == NULL))
108 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
109 LE16_TO_CPU(aq_desc->opcode),
110 LE16_TO_CPU(aq_desc->flags),
111 LE16_TO_CPU(aq_desc->datalen),
112 LE16_TO_CPU(aq_desc->retval));
113 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
114 LE32_TO_CPU(aq_desc->cookie_high),
115 LE32_TO_CPU(aq_desc->cookie_low));
116 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
117 LE32_TO_CPU(aq_desc->params.internal.param0),
118 LE32_TO_CPU(aq_desc->params.internal.param1));
119 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
120 LE32_TO_CPU(aq_desc->params.external.addr_high),
121 LE32_TO_CPU(aq_desc->params.external.addr_low));
123 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
124 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
127 /* write the full 16-byte chunks */
128 for (i = 0; i < (len - 16); i += 16)
130 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
131 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
132 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
133 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
134 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
135 /* write whatever's left over without overrunning the buffer */
140 memset(d_buf, 0, sizeof(d_buf));
141 j += sprintf(d_buf, "\t0x%04X ", i);
143 j += sprintf(&d_buf[j], " %02X", buf[i++]);
144 i40e_debug(hw, mask, "%s\n", d_buf);
150 * i40e_check_asq_alive
151 * @hw: pointer to the hw struct
153 * Returns true if Queue is enabled else false.
155 bool i40e_check_asq_alive(struct i40e_hw *hw)
158 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
164 * i40e_aq_queue_shutdown
165 * @hw: pointer to the hw struct
166 * @unloading: is the driver unloading itself
168 * Tell the Firmware that we're shutting down the AdminQ and whether
169 * or not the driver is unloading as well.
171 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
174 struct i40e_aq_desc desc;
175 struct i40e_aqc_queue_shutdown *cmd =
176 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
177 enum i40e_status_code status;
179 i40e_fill_default_direct_cmd_desc(&desc,
180 i40e_aqc_opc_queue_shutdown);
183 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
184 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
189 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
190 * hardware to a bit-field that can be used by SW to more easily determine the
193 * Macros are used to shorten the table lines and make this table human
196 * We store the PTYPE in the top byte of the bit field - this is just so that
197 * we can check that the table doesn't have a row missing, as the index into
198 * the table should be the PTYPE.
202 * IF NOT i40e_ptype_lookup[ptype].known
205 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
206 * Use the rest of the fields to look at the tunnels, inner protocols, etc
208 * Use the enum i40e_rx_l2_ptype to decode the packet type
212 /* macro to make the table lines short */
213 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
216 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
217 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
218 I40E_RX_PTYPE_##OUTER_FRAG, \
219 I40E_RX_PTYPE_TUNNEL_##T, \
220 I40E_RX_PTYPE_TUNNEL_END_##TE, \
221 I40E_RX_PTYPE_##TEF, \
222 I40E_RX_PTYPE_INNER_PROT_##I, \
223 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
225 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
226 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
228 /* shorter macros makes the table fit but are terse */
229 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
230 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
231 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
233 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
234 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
235 /* L2 Packet types */
236 I40E_PTT_UNUSED_ENTRY(0),
237 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
239 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
240 I40E_PTT_UNUSED_ENTRY(4),
241 I40E_PTT_UNUSED_ENTRY(5),
242 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(8),
245 I40E_PTT_UNUSED_ENTRY(9),
246 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
248 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 /* Non Tunneled IPv4 */
260 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
262 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(25),
264 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
265 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
266 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
269 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
270 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
271 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
272 I40E_PTT_UNUSED_ENTRY(32),
273 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
274 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
275 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
278 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
279 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
280 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
281 I40E_PTT_UNUSED_ENTRY(39),
282 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
283 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
284 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
286 /* IPv4 --> GRE/NAT */
287 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
289 /* IPv4 --> GRE/NAT --> IPv4 */
290 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
291 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
292 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
293 I40E_PTT_UNUSED_ENTRY(47),
294 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
295 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
296 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
298 /* IPv4 --> GRE/NAT --> IPv6 */
299 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
300 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
301 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
302 I40E_PTT_UNUSED_ENTRY(54),
303 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
304 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
305 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
307 /* IPv4 --> GRE/NAT --> MAC */
308 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
310 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
311 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
312 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
313 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
314 I40E_PTT_UNUSED_ENTRY(62),
315 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
316 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
317 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
319 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
320 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
321 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
322 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
323 I40E_PTT_UNUSED_ENTRY(69),
324 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
325 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
326 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
328 /* IPv4 --> GRE/NAT --> MAC/VLAN */
329 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
331 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
332 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
333 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
334 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
335 I40E_PTT_UNUSED_ENTRY(77),
336 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
337 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
338 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
340 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
341 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
342 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
343 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(84),
345 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
346 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
347 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
349 /* Non Tunneled IPv6 */
350 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
352 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
353 I40E_PTT_UNUSED_ENTRY(91),
354 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
355 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
356 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
359 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
360 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
361 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
362 I40E_PTT_UNUSED_ENTRY(98),
363 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
364 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
365 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
368 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
369 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
370 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
371 I40E_PTT_UNUSED_ENTRY(105),
372 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
373 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
374 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
376 /* IPv6 --> GRE/NAT */
377 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
379 /* IPv6 --> GRE/NAT -> IPv4 */
380 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
381 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
382 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
383 I40E_PTT_UNUSED_ENTRY(113),
384 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
385 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
386 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
388 /* IPv6 --> GRE/NAT -> IPv6 */
389 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
390 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
391 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
392 I40E_PTT_UNUSED_ENTRY(120),
393 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
394 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
395 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
397 /* IPv6 --> GRE/NAT -> MAC */
398 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
400 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
401 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
402 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
403 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
404 I40E_PTT_UNUSED_ENTRY(128),
405 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
406 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
407 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
409 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
410 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
411 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
412 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
413 I40E_PTT_UNUSED_ENTRY(135),
414 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
415 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
416 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
418 /* IPv6 --> GRE/NAT -> MAC/VLAN */
419 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
421 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
422 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
423 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
424 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
425 I40E_PTT_UNUSED_ENTRY(143),
426 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
427 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
428 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
430 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
431 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
432 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
433 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
434 I40E_PTT_UNUSED_ENTRY(150),
435 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
436 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
437 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
440 I40E_PTT_UNUSED_ENTRY(154),
441 I40E_PTT_UNUSED_ENTRY(155),
442 I40E_PTT_UNUSED_ENTRY(156),
443 I40E_PTT_UNUSED_ENTRY(157),
444 I40E_PTT_UNUSED_ENTRY(158),
445 I40E_PTT_UNUSED_ENTRY(159),
447 I40E_PTT_UNUSED_ENTRY(160),
448 I40E_PTT_UNUSED_ENTRY(161),
449 I40E_PTT_UNUSED_ENTRY(162),
450 I40E_PTT_UNUSED_ENTRY(163),
451 I40E_PTT_UNUSED_ENTRY(164),
452 I40E_PTT_UNUSED_ENTRY(165),
453 I40E_PTT_UNUSED_ENTRY(166),
454 I40E_PTT_UNUSED_ENTRY(167),
455 I40E_PTT_UNUSED_ENTRY(168),
456 I40E_PTT_UNUSED_ENTRY(169),
458 I40E_PTT_UNUSED_ENTRY(170),
459 I40E_PTT_UNUSED_ENTRY(171),
460 I40E_PTT_UNUSED_ENTRY(172),
461 I40E_PTT_UNUSED_ENTRY(173),
462 I40E_PTT_UNUSED_ENTRY(174),
463 I40E_PTT_UNUSED_ENTRY(175),
464 I40E_PTT_UNUSED_ENTRY(176),
465 I40E_PTT_UNUSED_ENTRY(177),
466 I40E_PTT_UNUSED_ENTRY(178),
467 I40E_PTT_UNUSED_ENTRY(179),
469 I40E_PTT_UNUSED_ENTRY(180),
470 I40E_PTT_UNUSED_ENTRY(181),
471 I40E_PTT_UNUSED_ENTRY(182),
472 I40E_PTT_UNUSED_ENTRY(183),
473 I40E_PTT_UNUSED_ENTRY(184),
474 I40E_PTT_UNUSED_ENTRY(185),
475 I40E_PTT_UNUSED_ENTRY(186),
476 I40E_PTT_UNUSED_ENTRY(187),
477 I40E_PTT_UNUSED_ENTRY(188),
478 I40E_PTT_UNUSED_ENTRY(189),
480 I40E_PTT_UNUSED_ENTRY(190),
481 I40E_PTT_UNUSED_ENTRY(191),
482 I40E_PTT_UNUSED_ENTRY(192),
483 I40E_PTT_UNUSED_ENTRY(193),
484 I40E_PTT_UNUSED_ENTRY(194),
485 I40E_PTT_UNUSED_ENTRY(195),
486 I40E_PTT_UNUSED_ENTRY(196),
487 I40E_PTT_UNUSED_ENTRY(197),
488 I40E_PTT_UNUSED_ENTRY(198),
489 I40E_PTT_UNUSED_ENTRY(199),
491 I40E_PTT_UNUSED_ENTRY(200),
492 I40E_PTT_UNUSED_ENTRY(201),
493 I40E_PTT_UNUSED_ENTRY(202),
494 I40E_PTT_UNUSED_ENTRY(203),
495 I40E_PTT_UNUSED_ENTRY(204),
496 I40E_PTT_UNUSED_ENTRY(205),
497 I40E_PTT_UNUSED_ENTRY(206),
498 I40E_PTT_UNUSED_ENTRY(207),
499 I40E_PTT_UNUSED_ENTRY(208),
500 I40E_PTT_UNUSED_ENTRY(209),
502 I40E_PTT_UNUSED_ENTRY(210),
503 I40E_PTT_UNUSED_ENTRY(211),
504 I40E_PTT_UNUSED_ENTRY(212),
505 I40E_PTT_UNUSED_ENTRY(213),
506 I40E_PTT_UNUSED_ENTRY(214),
507 I40E_PTT_UNUSED_ENTRY(215),
508 I40E_PTT_UNUSED_ENTRY(216),
509 I40E_PTT_UNUSED_ENTRY(217),
510 I40E_PTT_UNUSED_ENTRY(218),
511 I40E_PTT_UNUSED_ENTRY(219),
513 I40E_PTT_UNUSED_ENTRY(220),
514 I40E_PTT_UNUSED_ENTRY(221),
515 I40E_PTT_UNUSED_ENTRY(222),
516 I40E_PTT_UNUSED_ENTRY(223),
517 I40E_PTT_UNUSED_ENTRY(224),
518 I40E_PTT_UNUSED_ENTRY(225),
519 I40E_PTT_UNUSED_ENTRY(226),
520 I40E_PTT_UNUSED_ENTRY(227),
521 I40E_PTT_UNUSED_ENTRY(228),
522 I40E_PTT_UNUSED_ENTRY(229),
524 I40E_PTT_UNUSED_ENTRY(230),
525 I40E_PTT_UNUSED_ENTRY(231),
526 I40E_PTT_UNUSED_ENTRY(232),
527 I40E_PTT_UNUSED_ENTRY(233),
528 I40E_PTT_UNUSED_ENTRY(234),
529 I40E_PTT_UNUSED_ENTRY(235),
530 I40E_PTT_UNUSED_ENTRY(236),
531 I40E_PTT_UNUSED_ENTRY(237),
532 I40E_PTT_UNUSED_ENTRY(238),
533 I40E_PTT_UNUSED_ENTRY(239),
535 I40E_PTT_UNUSED_ENTRY(240),
536 I40E_PTT_UNUSED_ENTRY(241),
537 I40E_PTT_UNUSED_ENTRY(242),
538 I40E_PTT_UNUSED_ENTRY(243),
539 I40E_PTT_UNUSED_ENTRY(244),
540 I40E_PTT_UNUSED_ENTRY(245),
541 I40E_PTT_UNUSED_ENTRY(246),
542 I40E_PTT_UNUSED_ENTRY(247),
543 I40E_PTT_UNUSED_ENTRY(248),
544 I40E_PTT_UNUSED_ENTRY(249),
546 I40E_PTT_UNUSED_ENTRY(250),
547 I40E_PTT_UNUSED_ENTRY(251),
548 I40E_PTT_UNUSED_ENTRY(252),
549 I40E_PTT_UNUSED_ENTRY(253),
550 I40E_PTT_UNUSED_ENTRY(254),
551 I40E_PTT_UNUSED_ENTRY(255)
557 * i40e_init_shared_code - Initialize the shared code
558 * @hw: pointer to hardware structure
560 * This assigns the MAC type and PHY code and inits the NVM.
561 * Does not touch the hardware. This function must be called prior to any
562 * other function in the shared code. The i40e_hw structure should be
563 * memset to 0 prior to calling this function. The following fields in
564 * hw structure should be filled in prior to calling this function:
565 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
566 * subsystem_vendor_id, and revision_id
568 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
570 enum i40e_status_code status = I40E_SUCCESS;
573 DEBUGFUNC("i40e_init_shared_code");
575 i40e_set_mac_type(hw);
577 switch (hw->mac.type) {
581 return I40E_ERR_DEVICE_NOT_SUPPORTED;
584 hw->phy.get_link_info = true;
586 /* Determine port number */
587 reg = rd32(hw, I40E_PFGEN_PORTNUM);
588 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
589 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
592 /* Determine the PF number based on the PCI fn */
593 reg = rd32(hw, I40E_GLPCI_CAPSUP);
594 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
595 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
597 hw->pf_id = (u8)hw->bus.func;
599 status = i40e_init_nvm(hw);
604 * i40e_aq_mac_address_read - Retrieve the MAC addresses
605 * @hw: pointer to the hw struct
606 * @flags: a return indicator of what addresses were added to the addr store
607 * @addrs: the requestor's mac addr store
608 * @cmd_details: pointer to command details structure or NULL
610 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
612 struct i40e_aqc_mac_address_read_data *addrs,
613 struct i40e_asq_cmd_details *cmd_details)
615 struct i40e_aq_desc desc;
616 struct i40e_aqc_mac_address_read *cmd_data =
617 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
618 enum i40e_status_code status;
620 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
621 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
623 status = i40e_asq_send_command(hw, &desc, addrs,
624 sizeof(*addrs), cmd_details);
625 *flags = LE16_TO_CPU(cmd_data->command_flags);
631 * i40e_aq_mac_address_write - Change the MAC addresses
632 * @hw: pointer to the hw struct
633 * @flags: indicates which MAC to be written
634 * @mac_addr: address to write
635 * @cmd_details: pointer to command details structure or NULL
637 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
638 u16 flags, u8 *mac_addr,
639 struct i40e_asq_cmd_details *cmd_details)
641 struct i40e_aq_desc desc;
642 struct i40e_aqc_mac_address_write *cmd_data =
643 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
644 enum i40e_status_code status;
646 i40e_fill_default_direct_cmd_desc(&desc,
647 i40e_aqc_opc_mac_address_write);
648 cmd_data->command_flags = CPU_TO_LE16(flags);
649 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
650 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
651 ((u32)mac_addr[3] << 16) |
652 ((u32)mac_addr[4] << 8) |
655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
661 * i40e_get_mac_addr - get MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to MAC address
665 * Reads the adapter's MAC address from register
667 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
669 struct i40e_aqc_mac_address_read_data addrs;
670 enum i40e_status_code status;
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
675 if (flags & I40E_AQC_LAN_ADDR_VALID)
676 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
682 * i40e_get_port_mac_addr - get Port MAC address
683 * @hw: pointer to the HW structure
684 * @mac_addr: pointer to Port MAC address
686 * Reads the adapter's Port MAC address
688 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
690 struct i40e_aqc_mac_address_read_data addrs;
691 enum i40e_status_code status;
694 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
698 if (flags & I40E_AQC_PORT_ADDR_VALID)
699 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
701 status = I40E_ERR_INVALID_MAC_ADDR;
707 * i40e_pre_tx_queue_cfg - pre tx queue configure
708 * @hw: pointer to the HW structure
709 * @queue: target pf queue index
710 * @enable: state change request
712 * Handles hw requirement to indicate intention to enable
713 * or disable target queue.
715 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
717 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
721 if (abs_queue_idx >= 128) {
722 reg_block = abs_queue_idx / 128;
723 abs_queue_idx %= 128;
726 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
727 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
728 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
731 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
733 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
735 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
739 * i40e_validate_mac_addr - Validate unicast MAC address
740 * @mac_addr: pointer to MAC address
742 * Tests a MAC address to ensure it is a valid Individual Address
744 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
746 enum i40e_status_code status = I40E_SUCCESS;
748 DEBUGFUNC("i40e_validate_mac_addr");
750 /* Broadcast addresses ARE multicast addresses
751 * Make sure it is not a multicast address
752 * Reject the zero address
754 if (I40E_IS_MULTICAST(mac_addr) ||
755 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
756 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
757 status = I40E_ERR_INVALID_MAC_ADDR;
763 * i40e_get_media_type - Gets media type
764 * @hw: pointer to the hardware structure
766 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
768 enum i40e_media_type media;
770 switch (hw->phy.link_info.phy_type) {
771 case I40E_PHY_TYPE_10GBASE_SR:
772 case I40E_PHY_TYPE_10GBASE_LR:
773 case I40E_PHY_TYPE_1000BASE_SX:
774 case I40E_PHY_TYPE_1000BASE_LX:
775 case I40E_PHY_TYPE_40GBASE_SR4:
776 case I40E_PHY_TYPE_40GBASE_LR4:
777 media = I40E_MEDIA_TYPE_FIBER;
779 case I40E_PHY_TYPE_100BASE_TX:
780 case I40E_PHY_TYPE_1000BASE_T:
781 case I40E_PHY_TYPE_10GBASE_T:
782 media = I40E_MEDIA_TYPE_BASET;
784 case I40E_PHY_TYPE_10GBASE_CR1_CU:
785 case I40E_PHY_TYPE_40GBASE_CR4_CU:
786 case I40E_PHY_TYPE_10GBASE_CR1:
787 case I40E_PHY_TYPE_40GBASE_CR4:
788 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
789 media = I40E_MEDIA_TYPE_DA;
791 case I40E_PHY_TYPE_1000BASE_KX:
792 case I40E_PHY_TYPE_10GBASE_KX4:
793 case I40E_PHY_TYPE_10GBASE_KR:
794 case I40E_PHY_TYPE_40GBASE_KR4:
795 media = I40E_MEDIA_TYPE_BACKPLANE;
797 case I40E_PHY_TYPE_SGMII:
798 case I40E_PHY_TYPE_XAUI:
799 case I40E_PHY_TYPE_XFI:
800 case I40E_PHY_TYPE_XLAUI:
801 case I40E_PHY_TYPE_XLPPI:
803 media = I40E_MEDIA_TYPE_UNKNOWN;
810 #define I40E_PF_RESET_WAIT_COUNT 100
812 * i40e_pf_reset - Reset the PF
813 * @hw: pointer to the hardware structure
815 * Assuming someone else has triggered a global reset,
816 * assure the global reset is complete and then reset the PF
818 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
825 /* Poll for Global Reset steady state in case of recent GRST.
826 * The grst delay value is in 100ms units, and we'll wait a
827 * couple counts longer to be sure we don't just miss the end.
829 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
830 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
831 for (cnt = 0; cnt < grst_del + 2; cnt++) {
832 reg = rd32(hw, I40E_GLGEN_RSTAT);
833 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
835 i40e_msec_delay(100);
837 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
838 DEBUGOUT("Global reset polling failed to complete.\n");
839 return I40E_ERR_RESET_FAILED;
842 /* Now Wait for the FW to be ready */
843 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
844 reg = rd32(hw, I40E_GLNVM_ULD);
845 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
846 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
847 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
848 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
849 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
854 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
855 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
856 DEBUGOUT("wait for FW Reset complete timedout\n");
857 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
858 return I40E_ERR_RESET_FAILED;
861 /* If there was a Global Reset in progress when we got here,
862 * we don't need to do the PF Reset
865 reg = rd32(hw, I40E_PFGEN_CTRL);
866 wr32(hw, I40E_PFGEN_CTRL,
867 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
868 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
869 reg = rd32(hw, I40E_PFGEN_CTRL);
870 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
874 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
875 DEBUGOUT("PF reset polling failed to complete.\n");
876 return I40E_ERR_RESET_FAILED;
880 i40e_clear_pxe_mode(hw);
887 * i40e_clear_hw - clear out any left over hw state
888 * @hw: pointer to the hw struct
890 * Clear queues and interrupts, typically called at init time,
891 * but after the capabilities have been found so we know how many
892 * queues and msix vectors have been allocated.
894 void i40e_clear_hw(struct i40e_hw *hw)
896 u32 num_queues, base_queue;
904 /* get number of interrupts, queues, and vfs */
905 val = rd32(hw, I40E_GLPCI_CNF2);
906 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
907 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
908 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
909 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
911 val = rd32(hw, I40E_PFLAN_QALLOC);
912 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
913 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
914 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
915 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
916 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
917 num_queues = (j - base_queue) + 1;
921 val = rd32(hw, I40E_PF_VT_PFALLOC);
922 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
923 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
924 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
925 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
926 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
927 num_vfs = (j - i) + 1;
931 /* stop all the interrupts */
932 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
933 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
934 for (i = 0; i < num_pf_int - 2; i++)
935 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
937 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
938 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
939 wr32(hw, I40E_PFINT_LNKLST0, val);
940 for (i = 0; i < num_pf_int - 2; i++)
941 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
942 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
943 for (i = 0; i < num_vfs; i++)
944 wr32(hw, I40E_VPINT_LNKLST0(i), val);
945 for (i = 0; i < num_vf_int - 2; i++)
946 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
948 /* warn the HW of the coming Tx disables */
949 for (i = 0; i < num_queues; i++) {
950 u32 abs_queue_idx = base_queue + i;
953 if (abs_queue_idx >= 128) {
954 reg_block = abs_queue_idx / 128;
955 abs_queue_idx %= 128;
958 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
959 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
960 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
961 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
963 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
965 i40e_usec_delay(400);
967 /* stop all the queues */
968 for (i = 0; i < num_queues; i++) {
969 wr32(hw, I40E_QINT_TQCTL(i), 0);
970 wr32(hw, I40E_QTX_ENA(i), 0);
971 wr32(hw, I40E_QINT_RQCTL(i), 0);
972 wr32(hw, I40E_QRX_ENA(i), 0);
975 /* short wait for all queue disables to settle */
980 * i40e_clear_pxe_mode - clear pxe operations mode
981 * @hw: pointer to the hw struct
983 * Make sure all PXE mode settings are cleared, including things
984 * like descriptor fetch/write-back mode.
986 void i40e_clear_pxe_mode(struct i40e_hw *hw)
988 if (i40e_check_asq_alive(hw))
989 i40e_aq_clear_pxe_mode(hw, NULL);
993 * i40e_led_is_mine - helper to find matching led
994 * @hw: pointer to the hw struct
995 * @idx: index into GPIO registers
997 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
999 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1004 if (!hw->func_caps.led[idx])
1007 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1008 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1009 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1011 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1012 * if it is not our port then ignore
1014 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1021 #define I40E_LED0 22
1022 #define I40E_LINK_ACTIVITY 0xC
1025 * i40e_led_get - return current on/off mode
1026 * @hw: pointer to the hw struct
1028 * The value returned is the 'mode' field as defined in the
1029 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1030 * values are variations of possible behaviors relating to
1031 * blink, link, and wire.
1033 u32 i40e_led_get(struct i40e_hw *hw)
1038 /* as per the documentation GPIO 22-29 are the LED
1039 * GPIO pins named LED0..LED7
1041 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1042 u32 gpio_val = i40e_led_is_mine(hw, i);
1047 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1048 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1056 * i40e_led_set - set new on/off mode
1057 * @hw: pointer to the hw struct
1058 * @mode: 0=off, 0xf=on (else see manual for mode details)
1059 * @blink: true if the LED should blink when on, false if steady
1061 * if this function is used to turn on the blink it should
1062 * be used to disable the blink when restoring the original state.
1064 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1068 if (mode & 0xfffffff0)
1069 DEBUGOUT1("invalid mode passed in %X\n", mode);
1071 /* as per the documentation GPIO 22-29 are the LED
1072 * GPIO pins named LED0..LED7
1074 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1075 u32 gpio_val = i40e_led_is_mine(hw, i);
1080 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1081 /* this & is a bit of paranoia, but serves as a range check */
1082 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1083 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1085 if (mode == I40E_LINK_ACTIVITY)
1088 gpio_val |= (blink ? 1 : 0) <<
1089 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1091 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1096 /* Admin command wrappers */
1099 * i40e_aq_get_phy_capabilities
1100 * @hw: pointer to the hw struct
1101 * @abilities: structure for PHY capabilities to be filled
1102 * @qualified_modules: report Qualified Modules
1103 * @report_init: report init capabilities (active are default)
1104 * @cmd_details: pointer to command details structure or NULL
1106 * Returns the various PHY abilities supported on the Port.
1108 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1109 bool qualified_modules, bool report_init,
1110 struct i40e_aq_get_phy_abilities_resp *abilities,
1111 struct i40e_asq_cmd_details *cmd_details)
1113 struct i40e_aq_desc desc;
1114 enum i40e_status_code status;
1115 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1118 return I40E_ERR_PARAM;
1120 i40e_fill_default_direct_cmd_desc(&desc,
1121 i40e_aqc_opc_get_phy_abilities);
1123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1124 if (abilities_size > I40E_AQ_LARGE_BUF)
1125 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1127 if (qualified_modules)
1128 desc.params.external.param0 |=
1129 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1132 desc.params.external.param0 |=
1133 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1135 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1138 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1139 status = I40E_ERR_UNKNOWN_PHY;
1145 * i40e_aq_set_phy_config
1146 * @hw: pointer to the hw struct
1147 * @config: structure with PHY configuration to be set
1148 * @cmd_details: pointer to command details structure or NULL
1150 * Set the various PHY configuration parameters
1151 * supported on the Port.One or more of the Set PHY config parameters may be
1152 * ignored in an MFP mode as the PF may not have the privilege to set some
1153 * of the PHY Config parameters. This status will be indicated by the
1156 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1157 struct i40e_aq_set_phy_config *config,
1158 struct i40e_asq_cmd_details *cmd_details)
1160 struct i40e_aq_desc desc;
1161 struct i40e_aq_set_phy_config *cmd =
1162 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1163 enum i40e_status_code status;
1166 return I40E_ERR_PARAM;
1168 i40e_fill_default_direct_cmd_desc(&desc,
1169 i40e_aqc_opc_set_phy_config);
1173 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1180 * @hw: pointer to the hw struct
1182 * Set the requested flow control mode using set_phy_config.
1184 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1185 bool atomic_restart)
1187 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1188 struct i40e_aq_get_phy_abilities_resp abilities;
1189 struct i40e_aq_set_phy_config config;
1190 enum i40e_status_code status;
1191 u8 pause_mask = 0x0;
1197 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1198 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1200 case I40E_FC_RX_PAUSE:
1201 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1203 case I40E_FC_TX_PAUSE:
1204 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1210 /* Get the current phy config */
1211 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1214 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1218 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1219 /* clear the old pause settings */
1220 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1221 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1222 /* set the new abilities */
1223 config.abilities |= pause_mask;
1224 /* If the abilities have changed, then set the new config */
1225 if (config.abilities != abilities.abilities) {
1226 /* Auto restart link so settings take effect */
1228 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1229 /* Copy over all the old settings */
1230 config.phy_type = abilities.phy_type;
1231 config.link_speed = abilities.link_speed;
1232 config.eee_capability = abilities.eee_capability;
1233 config.eeer = abilities.eeer_val;
1234 config.low_power_ctrl = abilities.d3_lpan;
1235 status = i40e_aq_set_phy_config(hw, &config, NULL);
1238 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1240 /* Update the link info */
1241 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1243 /* Wait a little bit (on 40G cards it sometimes takes a really
1244 * long time for link to come back from the atomic reset)
1247 i40e_msec_delay(1000);
1248 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1251 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1257 * i40e_aq_set_mac_config
1258 * @hw: pointer to the hw struct
1259 * @max_frame_size: Maximum Frame Size to be supported by the port
1260 * @crc_en: Tell HW to append a CRC to outgoing frames
1261 * @pacing: Pacing configurations
1262 * @cmd_details: pointer to command details structure or NULL
1264 * Configure MAC settings for frame size, jumbo frame support and the
1265 * addition of a CRC by the hardware.
1267 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1269 bool crc_en, u16 pacing,
1270 struct i40e_asq_cmd_details *cmd_details)
1272 struct i40e_aq_desc desc;
1273 struct i40e_aq_set_mac_config *cmd =
1274 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1275 enum i40e_status_code status;
1277 if (max_frame_size == 0)
1278 return I40E_ERR_PARAM;
1280 i40e_fill_default_direct_cmd_desc(&desc,
1281 i40e_aqc_opc_set_mac_config);
1283 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1284 cmd->params = ((u8)pacing & 0x0F) << 3;
1286 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1288 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1294 * i40e_aq_clear_pxe_mode
1295 * @hw: pointer to the hw struct
1296 * @cmd_details: pointer to command details structure or NULL
1298 * Tell the firmware that the driver is taking over from PXE
1300 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1301 struct i40e_asq_cmd_details *cmd_details)
1303 enum i40e_status_code status;
1304 struct i40e_aq_desc desc;
1305 struct i40e_aqc_clear_pxe *cmd =
1306 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1308 i40e_fill_default_direct_cmd_desc(&desc,
1309 i40e_aqc_opc_clear_pxe_mode);
1313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1315 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1321 * i40e_aq_set_link_restart_an
1322 * @hw: pointer to the hw struct
1323 * @enable_link: if true: enable link, if false: disable link
1324 * @cmd_details: pointer to command details structure or NULL
1326 * Sets up the link and restarts the Auto-Negotiation over the link.
1328 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1329 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1331 struct i40e_aq_desc desc;
1332 struct i40e_aqc_set_link_restart_an *cmd =
1333 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1334 enum i40e_status_code status;
1336 i40e_fill_default_direct_cmd_desc(&desc,
1337 i40e_aqc_opc_set_link_restart_an);
1339 cmd->command = I40E_AQ_PHY_RESTART_AN;
1341 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1343 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1351 * i40e_aq_get_link_info
1352 * @hw: pointer to the hw struct
1353 * @enable_lse: enable/disable LinkStatusEvent reporting
1354 * @link: pointer to link status structure - optional
1355 * @cmd_details: pointer to command details structure or NULL
1357 * Returns the link status of the adapter.
1359 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1360 bool enable_lse, struct i40e_link_status *link,
1361 struct i40e_asq_cmd_details *cmd_details)
1363 struct i40e_aq_desc desc;
1364 struct i40e_aqc_get_link_status *resp =
1365 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1366 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1367 enum i40e_status_code status;
1368 bool tx_pause, rx_pause;
1371 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1374 command_flags = I40E_AQ_LSE_ENABLE;
1376 command_flags = I40E_AQ_LSE_DISABLE;
1377 resp->command_flags = CPU_TO_LE16(command_flags);
1379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1381 if (status != I40E_SUCCESS)
1382 goto aq_get_link_info_exit;
1384 /* save off old link status information */
1385 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1386 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA);
1388 /* update link status */
1389 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1390 hw->phy.media_type = i40e_get_media_type(hw);
1391 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1392 hw_link_info->link_info = resp->link_info;
1393 hw_link_info->an_info = resp->an_info;
1394 hw_link_info->ext_info = resp->ext_info;
1395 hw_link_info->loopback = resp->loopback;
1396 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1397 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1399 /* update fc info */
1400 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1401 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1402 if (tx_pause & rx_pause)
1403 hw->fc.current_mode = I40E_FC_FULL;
1405 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1407 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1409 hw->fc.current_mode = I40E_FC_NONE;
1411 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1412 hw_link_info->crc_enable = true;
1414 hw_link_info->crc_enable = false;
1416 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1417 hw_link_info->lse_enable = true;
1419 hw_link_info->lse_enable = false;
1421 /* save link status information */
1423 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status),
1424 I40E_NONDMA_TO_NONDMA);
1426 /* flag cleared so helper functions don't call AQ again */
1427 hw->phy.get_link_info = false;
1429 aq_get_link_info_exit:
1434 * i40e_aq_set_phy_int_mask
1435 * @hw: pointer to the hw struct
1436 * @mask: interrupt mask to be set
1437 * @cmd_details: pointer to command details structure or NULL
1439 * Set link interrupt mask.
1441 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1443 struct i40e_asq_cmd_details *cmd_details)
1445 struct i40e_aq_desc desc;
1446 struct i40e_aqc_set_phy_int_mask *cmd =
1447 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1448 enum i40e_status_code status;
1450 i40e_fill_default_direct_cmd_desc(&desc,
1451 i40e_aqc_opc_set_phy_int_mask);
1453 cmd->event_mask = CPU_TO_LE16(mask);
1455 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1461 * i40e_aq_get_local_advt_reg
1462 * @hw: pointer to the hw struct
1463 * @advt_reg: local AN advertisement register value
1464 * @cmd_details: pointer to command details structure or NULL
1466 * Get the Local AN advertisement register value.
1468 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1470 struct i40e_asq_cmd_details *cmd_details)
1472 struct i40e_aq_desc desc;
1473 struct i40e_aqc_an_advt_reg *resp =
1474 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1475 enum i40e_status_code status;
1477 i40e_fill_default_direct_cmd_desc(&desc,
1478 i40e_aqc_opc_get_local_advt_reg);
1480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1482 if (status != I40E_SUCCESS)
1483 goto aq_get_local_advt_reg_exit;
1485 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1486 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1488 aq_get_local_advt_reg_exit:
1493 * i40e_aq_set_local_advt_reg
1494 * @hw: pointer to the hw struct
1495 * @advt_reg: local AN advertisement register value
1496 * @cmd_details: pointer to command details structure or NULL
1498 * Get the Local AN advertisement register value.
1500 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1502 struct i40e_asq_cmd_details *cmd_details)
1504 struct i40e_aq_desc desc;
1505 struct i40e_aqc_an_advt_reg *cmd =
1506 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1507 enum i40e_status_code status;
1509 i40e_fill_default_direct_cmd_desc(&desc,
1510 i40e_aqc_opc_get_local_advt_reg);
1512 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1513 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1515 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1521 * i40e_aq_get_partner_advt
1522 * @hw: pointer to the hw struct
1523 * @advt_reg: AN partner advertisement register value
1524 * @cmd_details: pointer to command details structure or NULL
1526 * Get the link partner AN advertisement register value.
1528 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1530 struct i40e_asq_cmd_details *cmd_details)
1532 struct i40e_aq_desc desc;
1533 struct i40e_aqc_an_advt_reg *resp =
1534 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1535 enum i40e_status_code status;
1537 i40e_fill_default_direct_cmd_desc(&desc,
1538 i40e_aqc_opc_get_partner_advt);
1540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1542 if (status != I40E_SUCCESS)
1543 goto aq_get_partner_advt_exit;
1545 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1546 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1548 aq_get_partner_advt_exit:
1553 * i40e_aq_set_lb_modes
1554 * @hw: pointer to the hw struct
1555 * @lb_modes: loopback mode to be set
1556 * @cmd_details: pointer to command details structure or NULL
1558 * Sets loopback modes.
1560 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1562 struct i40e_asq_cmd_details *cmd_details)
1564 struct i40e_aq_desc desc;
1565 struct i40e_aqc_set_lb_mode *cmd =
1566 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1567 enum i40e_status_code status;
1569 i40e_fill_default_direct_cmd_desc(&desc,
1570 i40e_aqc_opc_set_lb_modes);
1572 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1574 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1580 * i40e_aq_set_phy_debug
1581 * @hw: pointer to the hw struct
1582 * @cmd_flags: debug command flags
1583 * @cmd_details: pointer to command details structure or NULL
1585 * Reset the external PHY.
1587 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1588 struct i40e_asq_cmd_details *cmd_details)
1590 struct i40e_aq_desc desc;
1591 struct i40e_aqc_set_phy_debug *cmd =
1592 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1593 enum i40e_status_code status;
1595 i40e_fill_default_direct_cmd_desc(&desc,
1596 i40e_aqc_opc_set_phy_debug);
1598 cmd->command_flags = cmd_flags;
1600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1607 * @hw: pointer to the hw struct
1608 * @vsi_ctx: pointer to a vsi context struct
1609 * @cmd_details: pointer to command details structure or NULL
1611 * Add a VSI context to the hardware.
1613 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1614 struct i40e_vsi_context *vsi_ctx,
1615 struct i40e_asq_cmd_details *cmd_details)
1617 struct i40e_aq_desc desc;
1618 struct i40e_aqc_add_get_update_vsi *cmd =
1619 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1620 struct i40e_aqc_add_get_update_vsi_completion *resp =
1621 (struct i40e_aqc_add_get_update_vsi_completion *)
1623 enum i40e_status_code status;
1625 i40e_fill_default_direct_cmd_desc(&desc,
1626 i40e_aqc_opc_add_vsi);
1628 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1629 cmd->connection_type = vsi_ctx->connection_type;
1630 cmd->vf_id = vsi_ctx->vf_num;
1631 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1633 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1635 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1636 sizeof(vsi_ctx->info), cmd_details);
1638 if (status != I40E_SUCCESS)
1639 goto aq_add_vsi_exit;
1641 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1642 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1643 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1644 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1651 * i40e_aq_set_default_vsi
1652 * @hw: pointer to the hw struct
1654 * @cmd_details: pointer to command details structure or NULL
1656 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1658 struct i40e_asq_cmd_details *cmd_details)
1660 struct i40e_aq_desc desc;
1661 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1662 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1664 enum i40e_status_code status;
1666 i40e_fill_default_direct_cmd_desc(&desc,
1667 i40e_aqc_opc_set_vsi_promiscuous_modes);
1669 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1670 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1671 cmd->seid = CPU_TO_LE16(seid);
1673 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1679 * i40e_aq_set_vsi_unicast_promiscuous
1680 * @hw: pointer to the hw struct
1682 * @set: set unicast promiscuous enable/disable
1683 * @cmd_details: pointer to command details structure or NULL
1685 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1687 struct i40e_asq_cmd_details *cmd_details)
1689 struct i40e_aq_desc desc;
1690 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1691 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1692 enum i40e_status_code status;
1695 i40e_fill_default_direct_cmd_desc(&desc,
1696 i40e_aqc_opc_set_vsi_promiscuous_modes);
1699 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1701 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1703 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1705 cmd->seid = CPU_TO_LE16(seid);
1706 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1712 * i40e_aq_set_vsi_multicast_promiscuous
1713 * @hw: pointer to the hw struct
1715 * @set: set multicast promiscuous enable/disable
1716 * @cmd_details: pointer to command details structure or NULL
1718 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1719 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1721 struct i40e_aq_desc desc;
1722 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1723 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1724 enum i40e_status_code status;
1727 i40e_fill_default_direct_cmd_desc(&desc,
1728 i40e_aqc_opc_set_vsi_promiscuous_modes);
1731 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1733 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1735 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1737 cmd->seid = CPU_TO_LE16(seid);
1738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1744 * i40e_aq_set_vsi_broadcast
1745 * @hw: pointer to the hw struct
1747 * @set_filter: true to set filter, false to clear filter
1748 * @cmd_details: pointer to command details structure or NULL
1750 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1752 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1753 u16 seid, bool set_filter,
1754 struct i40e_asq_cmd_details *cmd_details)
1756 struct i40e_aq_desc desc;
1757 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1758 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1759 enum i40e_status_code status;
1761 i40e_fill_default_direct_cmd_desc(&desc,
1762 i40e_aqc_opc_set_vsi_promiscuous_modes);
1765 cmd->promiscuous_flags
1766 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1768 cmd->promiscuous_flags
1769 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1771 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1772 cmd->seid = CPU_TO_LE16(seid);
1773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1779 * i40e_get_vsi_params - get VSI configuration info
1780 * @hw: pointer to the hw struct
1781 * @vsi_ctx: pointer to a vsi context struct
1782 * @cmd_details: pointer to command details structure or NULL
1784 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1785 struct i40e_vsi_context *vsi_ctx,
1786 struct i40e_asq_cmd_details *cmd_details)
1788 struct i40e_aq_desc desc;
1789 struct i40e_aqc_add_get_update_vsi *cmd =
1790 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1791 struct i40e_aqc_add_get_update_vsi_completion *resp =
1792 (struct i40e_aqc_add_get_update_vsi_completion *)
1794 enum i40e_status_code status;
1796 UNREFERENCED_1PARAMETER(cmd_details);
1797 i40e_fill_default_direct_cmd_desc(&desc,
1798 i40e_aqc_opc_get_vsi_parameters);
1800 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1802 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1804 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1805 sizeof(vsi_ctx->info), NULL);
1807 if (status != I40E_SUCCESS)
1808 goto aq_get_vsi_params_exit;
1810 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1811 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1812 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1813 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1815 aq_get_vsi_params_exit:
1820 * i40e_aq_update_vsi_params
1821 * @hw: pointer to the hw struct
1822 * @vsi_ctx: pointer to a vsi context struct
1823 * @cmd_details: pointer to command details structure or NULL
1825 * Update a VSI context.
1827 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1828 struct i40e_vsi_context *vsi_ctx,
1829 struct i40e_asq_cmd_details *cmd_details)
1831 struct i40e_aq_desc desc;
1832 struct i40e_aqc_add_get_update_vsi *cmd =
1833 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1834 enum i40e_status_code status;
1836 i40e_fill_default_direct_cmd_desc(&desc,
1837 i40e_aqc_opc_update_vsi_parameters);
1838 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1840 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1842 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1843 sizeof(vsi_ctx->info), cmd_details);
1849 * i40e_aq_get_switch_config
1850 * @hw: pointer to the hardware structure
1851 * @buf: pointer to the result buffer
1852 * @buf_size: length of input buffer
1853 * @start_seid: seid to start for the report, 0 == beginning
1854 * @cmd_details: pointer to command details structure or NULL
1856 * Fill the buf with switch configuration returned from AdminQ command
1858 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1859 struct i40e_aqc_get_switch_config_resp *buf,
1860 u16 buf_size, u16 *start_seid,
1861 struct i40e_asq_cmd_details *cmd_details)
1863 struct i40e_aq_desc desc;
1864 struct i40e_aqc_switch_seid *scfg =
1865 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1866 enum i40e_status_code status;
1868 i40e_fill_default_direct_cmd_desc(&desc,
1869 i40e_aqc_opc_get_switch_config);
1870 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1871 if (buf_size > I40E_AQ_LARGE_BUF)
1872 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1873 scfg->seid = CPU_TO_LE16(*start_seid);
1875 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1876 *start_seid = LE16_TO_CPU(scfg->seid);
1882 * i40e_aq_get_firmware_version
1883 * @hw: pointer to the hw struct
1884 * @fw_major_version: firmware major version
1885 * @fw_minor_version: firmware minor version
1886 * @fw_build: firmware build number
1887 * @api_major_version: major queue version
1888 * @api_minor_version: minor queue version
1889 * @cmd_details: pointer to command details structure or NULL
1891 * Get the firmware version from the admin queue commands
1893 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1894 u16 *fw_major_version, u16 *fw_minor_version,
1896 u16 *api_major_version, u16 *api_minor_version,
1897 struct i40e_asq_cmd_details *cmd_details)
1899 struct i40e_aq_desc desc;
1900 struct i40e_aqc_get_version *resp =
1901 (struct i40e_aqc_get_version *)&desc.params.raw;
1902 enum i40e_status_code status;
1904 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1906 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1908 if (status == I40E_SUCCESS) {
1909 if (fw_major_version != NULL)
1910 *fw_major_version = LE16_TO_CPU(resp->fw_major);
1911 if (fw_minor_version != NULL)
1912 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
1913 if (fw_build != NULL)
1914 *fw_build = LE32_TO_CPU(resp->fw_build);
1915 if (api_major_version != NULL)
1916 *api_major_version = LE16_TO_CPU(resp->api_major);
1917 if (api_minor_version != NULL)
1918 *api_minor_version = LE16_TO_CPU(resp->api_minor);
1920 /* A workaround to fix the API version in SW */
1921 if (api_major_version && api_minor_version &&
1922 fw_major_version && fw_minor_version &&
1923 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
1924 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
1925 (*fw_major_version > 4)))
1926 *api_minor_version = 2;
1933 * i40e_aq_send_driver_version
1934 * @hw: pointer to the hw struct
1935 * @dv: driver's major, minor version
1936 * @cmd_details: pointer to command details structure or NULL
1938 * Send the driver version to the firmware
1940 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
1941 struct i40e_driver_version *dv,
1942 struct i40e_asq_cmd_details *cmd_details)
1944 struct i40e_aq_desc desc;
1945 struct i40e_aqc_driver_version *cmd =
1946 (struct i40e_aqc_driver_version *)&desc.params.raw;
1947 enum i40e_status_code status;
1951 return I40E_ERR_PARAM;
1953 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1955 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1956 cmd->driver_major_ver = dv->major_version;
1957 cmd->driver_minor_ver = dv->minor_version;
1958 cmd->driver_build_ver = dv->build_version;
1959 cmd->driver_subbuild_ver = dv->subbuild_version;
1962 while (len < sizeof(dv->driver_string) &&
1963 (dv->driver_string[len] < 0x80) &&
1964 dv->driver_string[len])
1966 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1973 * i40e_get_link_status - get status of the HW network link
1974 * @hw: pointer to the hw struct
1976 * Returns true if link is up, false if link is down.
1978 * Side effect: LinkStatusEvent reporting becomes enabled
1980 bool i40e_get_link_status(struct i40e_hw *hw)
1982 enum i40e_status_code status = I40E_SUCCESS;
1983 bool link_status = false;
1985 if (hw->phy.get_link_info) {
1986 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1988 if (status != I40E_SUCCESS)
1989 goto i40e_get_link_status_exit;
1992 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1994 i40e_get_link_status_exit:
1999 * i40e_get_link_speed
2000 * @hw: pointer to the hw struct
2002 * Returns the link speed of the adapter.
2004 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2006 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2007 enum i40e_status_code status = I40E_SUCCESS;
2009 if (hw->phy.get_link_info) {
2010 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2012 if (status != I40E_SUCCESS)
2013 goto i40e_link_speed_exit;
2016 speed = hw->phy.link_info.link_speed;
2018 i40e_link_speed_exit:
2023 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2024 * @hw: pointer to the hw struct
2025 * @uplink_seid: the MAC or other gizmo SEID
2026 * @downlink_seid: the VSI SEID
2027 * @enabled_tc: bitmap of TCs to be enabled
2028 * @default_port: true for default port VSI, false for control port
2029 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2030 * @veb_seid: pointer to where to put the resulting VEB SEID
2031 * @cmd_details: pointer to command details structure or NULL
2033 * This asks the FW to add a VEB between the uplink and downlink
2034 * elements. If the uplink SEID is 0, this will be a floating VEB.
2036 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2037 u16 downlink_seid, u8 enabled_tc,
2038 bool default_port, bool enable_l2_filtering,
2040 struct i40e_asq_cmd_details *cmd_details)
2042 struct i40e_aq_desc desc;
2043 struct i40e_aqc_add_veb *cmd =
2044 (struct i40e_aqc_add_veb *)&desc.params.raw;
2045 struct i40e_aqc_add_veb_completion *resp =
2046 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2047 enum i40e_status_code status;
2050 /* SEIDs need to either both be set or both be 0 for floating VEB */
2051 if (!!uplink_seid != !!downlink_seid)
2052 return I40E_ERR_PARAM;
2054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2056 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2057 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2058 cmd->enable_tcs = enabled_tc;
2060 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2062 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2064 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2066 if (enable_l2_filtering)
2067 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2069 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2073 if (!status && veb_seid)
2074 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2080 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2081 * @hw: pointer to the hw struct
2082 * @veb_seid: the SEID of the VEB to query
2083 * @switch_id: the uplink switch id
2084 * @floating: set to true if the VEB is floating
2085 * @statistic_index: index of the stats counter block for this VEB
2086 * @vebs_used: number of VEB's used by function
2087 * @vebs_free: total VEB's not reserved by any function
2088 * @cmd_details: pointer to command details structure or NULL
2090 * This retrieves the parameters for a particular VEB, specified by
2091 * uplink_seid, and returns them to the caller.
2093 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2094 u16 veb_seid, u16 *switch_id,
2095 bool *floating, u16 *statistic_index,
2096 u16 *vebs_used, u16 *vebs_free,
2097 struct i40e_asq_cmd_details *cmd_details)
2099 struct i40e_aq_desc desc;
2100 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2101 (struct i40e_aqc_get_veb_parameters_completion *)
2103 enum i40e_status_code status;
2106 return I40E_ERR_PARAM;
2108 i40e_fill_default_direct_cmd_desc(&desc,
2109 i40e_aqc_opc_get_veb_parameters);
2110 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2117 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2118 if (statistic_index)
2119 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2121 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2123 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2125 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2126 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2137 * i40e_aq_add_macvlan
2138 * @hw: pointer to the hw struct
2139 * @seid: VSI for the mac address
2140 * @mv_list: list of macvlans to be added
2141 * @count: length of the list
2142 * @cmd_details: pointer to command details structure or NULL
2144 * Add MAC/VLAN addresses to the HW filtering
2146 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2147 struct i40e_aqc_add_macvlan_element_data *mv_list,
2148 u16 count, struct i40e_asq_cmd_details *cmd_details)
2150 struct i40e_aq_desc desc;
2151 struct i40e_aqc_macvlan *cmd =
2152 (struct i40e_aqc_macvlan *)&desc.params.raw;
2153 enum i40e_status_code status;
2156 if (count == 0 || !mv_list || !hw)
2157 return I40E_ERR_PARAM;
2159 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2161 /* prep the rest of the request */
2162 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2163 cmd->num_addresses = CPU_TO_LE16(count);
2164 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2168 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2169 if (buf_size > I40E_AQ_LARGE_BUF)
2170 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2172 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2179 * i40e_aq_remove_macvlan
2180 * @hw: pointer to the hw struct
2181 * @seid: VSI for the mac address
2182 * @mv_list: list of macvlans to be removed
2183 * @count: length of the list
2184 * @cmd_details: pointer to command details structure or NULL
2186 * Remove MAC/VLAN addresses from the HW filtering
2188 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2189 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2190 u16 count, struct i40e_asq_cmd_details *cmd_details)
2192 struct i40e_aq_desc desc;
2193 struct i40e_aqc_macvlan *cmd =
2194 (struct i40e_aqc_macvlan *)&desc.params.raw;
2195 enum i40e_status_code status;
2198 if (count == 0 || !mv_list || !hw)
2199 return I40E_ERR_PARAM;
2201 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2203 /* prep the rest of the request */
2204 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2205 cmd->num_addresses = CPU_TO_LE16(count);
2206 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2210 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2211 if (buf_size > I40E_AQ_LARGE_BUF)
2212 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2214 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2221 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2222 * @hw: pointer to the hw struct
2223 * @seid: VSI for the vlan filters
2224 * @v_list: list of vlan filters to be added
2225 * @count: length of the list
2226 * @cmd_details: pointer to command details structure or NULL
2228 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2229 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2230 u8 count, struct i40e_asq_cmd_details *cmd_details)
2232 struct i40e_aq_desc desc;
2233 struct i40e_aqc_macvlan *cmd =
2234 (struct i40e_aqc_macvlan *)&desc.params.raw;
2235 enum i40e_status_code status;
2238 if (count == 0 || !v_list || !hw)
2239 return I40E_ERR_PARAM;
2241 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2243 /* prep the rest of the request */
2244 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2245 cmd->num_addresses = CPU_TO_LE16(count);
2246 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2250 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2251 if (buf_size > I40E_AQ_LARGE_BUF)
2252 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2254 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2261 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2262 * @hw: pointer to the hw struct
2263 * @seid: VSI for the vlan filters
2264 * @v_list: list of macvlans to be removed
2265 * @count: length of the list
2266 * @cmd_details: pointer to command details structure or NULL
2268 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2269 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2270 u8 count, struct i40e_asq_cmd_details *cmd_details)
2272 struct i40e_aq_desc desc;
2273 struct i40e_aqc_macvlan *cmd =
2274 (struct i40e_aqc_macvlan *)&desc.params.raw;
2275 enum i40e_status_code status;
2278 if (count == 0 || !v_list || !hw)
2279 return I40E_ERR_PARAM;
2281 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
2283 /* prep the rest of the request */
2284 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2285 cmd->num_addresses = CPU_TO_LE16(count);
2286 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2290 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2291 if (buf_size > I40E_AQ_LARGE_BUF)
2292 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2294 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2301 * i40e_aq_send_msg_to_vf
2302 * @hw: pointer to the hardware structure
2303 * @vfid: vf id to send msg
2304 * @v_opcode: opcodes for VF-PF communication
2305 * @v_retval: return error code
2306 * @msg: pointer to the msg buffer
2307 * @msglen: msg length
2308 * @cmd_details: pointer to command details
2312 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2313 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2314 struct i40e_asq_cmd_details *cmd_details)
2316 struct i40e_aq_desc desc;
2317 struct i40e_aqc_pf_vf_message *cmd =
2318 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2319 enum i40e_status_code status;
2321 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2322 cmd->id = CPU_TO_LE32(vfid);
2323 desc.cookie_high = CPU_TO_LE32(v_opcode);
2324 desc.cookie_low = CPU_TO_LE32(v_retval);
2325 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2327 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2329 if (msglen > I40E_AQ_LARGE_BUF)
2330 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2331 desc.datalen = CPU_TO_LE16(msglen);
2333 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2339 * i40e_aq_debug_read_register
2340 * @hw: pointer to the hw struct
2341 * @reg_addr: register address
2342 * @reg_val: register value
2343 * @cmd_details: pointer to command details structure or NULL
2345 * Read the register using the admin queue commands
2347 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2348 u32 reg_addr, u64 *reg_val,
2349 struct i40e_asq_cmd_details *cmd_details)
2351 struct i40e_aq_desc desc;
2352 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2353 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2354 enum i40e_status_code status;
2356 if (reg_val == NULL)
2357 return I40E_ERR_PARAM;
2359 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2361 cmd_resp->address = CPU_TO_LE32(reg_addr);
2363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2365 if (status == I40E_SUCCESS) {
2366 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2367 (u64)LE32_TO_CPU(cmd_resp->value_low);
2374 * i40e_aq_debug_write_register
2375 * @hw: pointer to the hw struct
2376 * @reg_addr: register address
2377 * @reg_val: register value
2378 * @cmd_details: pointer to command details structure or NULL
2380 * Write to a register using the admin queue commands
2382 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2383 u32 reg_addr, u64 reg_val,
2384 struct i40e_asq_cmd_details *cmd_details)
2386 struct i40e_aq_desc desc;
2387 struct i40e_aqc_debug_reg_read_write *cmd =
2388 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2389 enum i40e_status_code status;
2391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2393 cmd->address = CPU_TO_LE32(reg_addr);
2394 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2395 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2397 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2403 * i40e_aq_get_hmc_resource_profile
2404 * @hw: pointer to the hw struct
2405 * @profile: type of profile the HMC is to be set as
2406 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2407 * @cmd_details: pointer to command details structure or NULL
2409 * query the HMC profile of the device.
2411 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2412 enum i40e_aq_hmc_profile *profile,
2413 u8 *pe_vf_enabled_count,
2414 struct i40e_asq_cmd_details *cmd_details)
2416 struct i40e_aq_desc desc;
2417 struct i40e_aq_get_set_hmc_resource_profile *resp =
2418 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2419 enum i40e_status_code status;
2421 i40e_fill_default_direct_cmd_desc(&desc,
2422 i40e_aqc_opc_query_hmc_resource_profile);
2423 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2425 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2426 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2427 *pe_vf_enabled_count = resp->pe_vf_enabled &
2428 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2434 * i40e_aq_set_hmc_resource_profile
2435 * @hw: pointer to the hw struct
2436 * @profile: type of profile the HMC is to be set as
2437 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2438 * @cmd_details: pointer to command details structure or NULL
2440 * set the HMC profile of the device.
2442 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2443 enum i40e_aq_hmc_profile profile,
2444 u8 pe_vf_enabled_count,
2445 struct i40e_asq_cmd_details *cmd_details)
2447 struct i40e_aq_desc desc;
2448 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2449 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2450 enum i40e_status_code status;
2452 i40e_fill_default_direct_cmd_desc(&desc,
2453 i40e_aqc_opc_set_hmc_resource_profile);
2455 cmd->pm_profile = (u8)profile;
2456 cmd->pe_vf_enabled = pe_vf_enabled_count;
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2464 * i40e_aq_request_resource
2465 * @hw: pointer to the hw struct
2466 * @resource: resource id
2467 * @access: access type
2468 * @sdp_number: resource number
2469 * @timeout: the maximum time in ms that the driver may hold the resource
2470 * @cmd_details: pointer to command details structure or NULL
2472 * requests common resource using the admin queue commands
2474 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2475 enum i40e_aq_resources_ids resource,
2476 enum i40e_aq_resource_access_type access,
2477 u8 sdp_number, u64 *timeout,
2478 struct i40e_asq_cmd_details *cmd_details)
2480 struct i40e_aq_desc desc;
2481 struct i40e_aqc_request_resource *cmd_resp =
2482 (struct i40e_aqc_request_resource *)&desc.params.raw;
2483 enum i40e_status_code status;
2485 DEBUGFUNC("i40e_aq_request_resource");
2487 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2489 cmd_resp->resource_id = CPU_TO_LE16(resource);
2490 cmd_resp->access_type = CPU_TO_LE16(access);
2491 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2494 /* The completion specifies the maximum time in ms that the driver
2495 * may hold the resource in the Timeout field.
2496 * If the resource is held by someone else, the command completes with
2497 * busy return value and the timeout field indicates the maximum time
2498 * the current owner of the resource has to free it.
2500 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2501 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2507 * i40e_aq_release_resource
2508 * @hw: pointer to the hw struct
2509 * @resource: resource id
2510 * @sdp_number: resource number
2511 * @cmd_details: pointer to command details structure or NULL
2513 * release common resource using the admin queue commands
2515 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2516 enum i40e_aq_resources_ids resource,
2518 struct i40e_asq_cmd_details *cmd_details)
2520 struct i40e_aq_desc desc;
2521 struct i40e_aqc_request_resource *cmd =
2522 (struct i40e_aqc_request_resource *)&desc.params.raw;
2523 enum i40e_status_code status;
2525 DEBUGFUNC("i40e_aq_release_resource");
2527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2529 cmd->resource_id = CPU_TO_LE16(resource);
2530 cmd->resource_number = CPU_TO_LE32(sdp_number);
2532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2539 * @hw: pointer to the hw struct
2540 * @module_pointer: module pointer location in words from the NVM beginning
2541 * @offset: byte offset from the module beginning
2542 * @length: length of the section to be read (in bytes from the offset)
2543 * @data: command buffer (size [bytes] = length)
2544 * @last_command: tells if this is the last command in a series
2545 * @cmd_details: pointer to command details structure or NULL
2547 * Read the NVM using the admin queue commands
2549 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2550 u32 offset, u16 length, void *data,
2552 struct i40e_asq_cmd_details *cmd_details)
2554 struct i40e_aq_desc desc;
2555 struct i40e_aqc_nvm_update *cmd =
2556 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2557 enum i40e_status_code status;
2559 DEBUGFUNC("i40e_aq_read_nvm");
2561 /* In offset the highest byte must be zeroed. */
2562 if (offset & 0xFF000000) {
2563 status = I40E_ERR_PARAM;
2564 goto i40e_aq_read_nvm_exit;
2567 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2569 /* If this is the last command in a series, set the proper flag. */
2571 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2572 cmd->module_pointer = module_pointer;
2573 cmd->offset = CPU_TO_LE32(offset);
2574 cmd->length = CPU_TO_LE16(length);
2576 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2577 if (length > I40E_AQ_LARGE_BUF)
2578 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2580 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2582 i40e_aq_read_nvm_exit:
2588 * @hw: pointer to the hw struct
2589 * @module_pointer: module pointer location in words from the NVM beginning
2590 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2591 * @length: length of the section to be erased (expressed in 4 KB)
2592 * @last_command: tells if this is the last command in a series
2593 * @cmd_details: pointer to command details structure or NULL
2595 * Erase the NVM sector using the admin queue commands
2597 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2598 u32 offset, u16 length, bool last_command,
2599 struct i40e_asq_cmd_details *cmd_details)
2601 struct i40e_aq_desc desc;
2602 struct i40e_aqc_nvm_update *cmd =
2603 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2604 enum i40e_status_code status;
2606 DEBUGFUNC("i40e_aq_erase_nvm");
2608 /* In offset the highest byte must be zeroed. */
2609 if (offset & 0xFF000000) {
2610 status = I40E_ERR_PARAM;
2611 goto i40e_aq_erase_nvm_exit;
2614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2616 /* If this is the last command in a series, set the proper flag. */
2618 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2619 cmd->module_pointer = module_pointer;
2620 cmd->offset = CPU_TO_LE32(offset);
2621 cmd->length = CPU_TO_LE16(length);
2623 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2625 i40e_aq_erase_nvm_exit:
2629 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2630 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2631 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2632 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2633 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2634 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2635 #define I40E_DEV_FUNC_CAP_VF 0x13
2636 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2637 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2638 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2639 #define I40E_DEV_FUNC_CAP_VSI 0x17
2640 #define I40E_DEV_FUNC_CAP_DCB 0x18
2641 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2642 #define I40E_DEV_FUNC_CAP_RSS 0x40
2643 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2644 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2645 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2646 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2647 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2648 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2649 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2650 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2651 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2652 #define I40E_DEV_FUNC_CAP_LED 0x61
2653 #define I40E_DEV_FUNC_CAP_SDP 0x62
2654 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2657 * i40e_parse_discover_capabilities
2658 * @hw: pointer to the hw struct
2659 * @buff: pointer to a buffer containing device/function capability records
2660 * @cap_count: number of capability records in the list
2661 * @list_type_opc: type of capabilities list to parse
2663 * Parse the device/function capabilities list.
2665 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2667 enum i40e_admin_queue_opc list_type_opc)
2669 struct i40e_aqc_list_capabilities_element_resp *cap;
2670 u32 number, logical_id, phys_id;
2671 struct i40e_hw_capabilities *p;
2675 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2677 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2678 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2679 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2680 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2684 for (i = 0; i < cap_count; i++, cap++) {
2685 id = LE16_TO_CPU(cap->id);
2686 number = LE32_TO_CPU(cap->number);
2687 logical_id = LE32_TO_CPU(cap->logical_id);
2688 phys_id = LE32_TO_CPU(cap->phys_id);
2691 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2692 p->switch_mode = number;
2694 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2695 p->management_mode = number;
2697 case I40E_DEV_FUNC_CAP_NPAR:
2698 p->npar_enable = number;
2700 case I40E_DEV_FUNC_CAP_OS2BMC:
2703 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2704 p->valid_functions = number;
2706 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2708 p->sr_iov_1_1 = true;
2710 case I40E_DEV_FUNC_CAP_VF:
2711 p->num_vfs = number;
2712 p->vf_base_id = logical_id;
2714 case I40E_DEV_FUNC_CAP_VMDQ:
2718 case I40E_DEV_FUNC_CAP_802_1_QBG:
2720 p->evb_802_1_qbg = true;
2722 case I40E_DEV_FUNC_CAP_802_1_QBH:
2724 p->evb_802_1_qbh = true;
2726 case I40E_DEV_FUNC_CAP_VSI:
2727 p->num_vsis = number;
2729 case I40E_DEV_FUNC_CAP_DCB:
2732 p->enabled_tcmap = logical_id;
2736 case I40E_DEV_FUNC_CAP_FCOE:
2740 case I40E_DEV_FUNC_CAP_RSS:
2742 p->rss_table_size = number;
2743 p->rss_table_entry_width = logical_id;
2745 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2746 p->num_rx_qp = number;
2747 p->base_queue = phys_id;
2749 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2750 p->num_tx_qp = number;
2751 p->base_queue = phys_id;
2753 case I40E_DEV_FUNC_CAP_MSIX:
2754 p->num_msix_vectors = number;
2756 case I40E_DEV_FUNC_CAP_MSIX_VF:
2757 p->num_msix_vectors_vf = number;
2759 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2761 p->mfp_mode_1 = true;
2763 case I40E_DEV_FUNC_CAP_CEM:
2767 case I40E_DEV_FUNC_CAP_IWARP:
2771 case I40E_DEV_FUNC_CAP_LED:
2772 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2773 p->led[phys_id] = true;
2775 case I40E_DEV_FUNC_CAP_SDP:
2776 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2777 p->sdp[phys_id] = true;
2779 case I40E_DEV_FUNC_CAP_MDIO:
2781 p->mdio_port_num = phys_id;
2782 p->mdio_port_mode = logical_id;
2785 case I40E_DEV_FUNC_CAP_IEEE_1588:
2787 p->ieee_1588 = true;
2789 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2791 p->fd_filters_guaranteed = number;
2792 p->fd_filters_best_effort = logical_id;
2799 /* Software override ensuring FCoE is disabled if npar or mfp
2800 * mode because it is not supported in these modes.
2802 if (p->npar_enable || p->mfp_mode_1)
2805 /* additional HW specific goodies that might
2806 * someday be HW version specific
2808 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2812 * i40e_aq_discover_capabilities
2813 * @hw: pointer to the hw struct
2814 * @buff: a virtual buffer to hold the capabilities
2815 * @buff_size: Size of the virtual buffer
2816 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2817 * @list_type_opc: capabilities type to discover - pass in the command opcode
2818 * @cmd_details: pointer to command details structure or NULL
2820 * Get the device capabilities descriptions from the firmware
2822 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
2823 void *buff, u16 buff_size, u16 *data_size,
2824 enum i40e_admin_queue_opc list_type_opc,
2825 struct i40e_asq_cmd_details *cmd_details)
2827 struct i40e_aqc_list_capabilites *cmd;
2828 struct i40e_aq_desc desc;
2829 enum i40e_status_code status = I40E_SUCCESS;
2831 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2833 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2834 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2835 status = I40E_ERR_PARAM;
2839 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2841 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2842 if (buff_size > I40E_AQ_LARGE_BUF)
2843 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2845 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2846 *data_size = LE16_TO_CPU(desc.datalen);
2851 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
2859 * i40e_aq_update_nvm
2860 * @hw: pointer to the hw struct
2861 * @module_pointer: module pointer location in words from the NVM beginning
2862 * @offset: byte offset from the module beginning
2863 * @length: length of the section to be written (in bytes from the offset)
2864 * @data: command buffer (size [bytes] = length)
2865 * @last_command: tells if this is the last command in a series
2866 * @cmd_details: pointer to command details structure or NULL
2868 * Update the NVM using the admin queue commands
2870 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2871 u32 offset, u16 length, void *data,
2873 struct i40e_asq_cmd_details *cmd_details)
2875 struct i40e_aq_desc desc;
2876 struct i40e_aqc_nvm_update *cmd =
2877 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2878 enum i40e_status_code status;
2880 DEBUGFUNC("i40e_aq_update_nvm");
2882 /* In offset the highest byte must be zeroed. */
2883 if (offset & 0xFF000000) {
2884 status = I40E_ERR_PARAM;
2885 goto i40e_aq_update_nvm_exit;
2888 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2890 /* If this is the last command in a series, set the proper flag. */
2892 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2893 cmd->module_pointer = module_pointer;
2894 cmd->offset = CPU_TO_LE32(offset);
2895 cmd->length = CPU_TO_LE16(length);
2897 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2898 if (length > I40E_AQ_LARGE_BUF)
2899 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2901 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2903 i40e_aq_update_nvm_exit:
2908 * i40e_aq_get_lldp_mib
2909 * @hw: pointer to the hw struct
2910 * @bridge_type: type of bridge requested
2911 * @mib_type: Local, Remote or both Local and Remote MIBs
2912 * @buff: pointer to a user supplied buffer to store the MIB block
2913 * @buff_size: size of the buffer (in bytes)
2914 * @local_len : length of the returned Local LLDP MIB
2915 * @remote_len: length of the returned Remote LLDP MIB
2916 * @cmd_details: pointer to command details structure or NULL
2918 * Requests the complete LLDP MIB (entire packet).
2920 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2921 u8 mib_type, void *buff, u16 buff_size,
2922 u16 *local_len, u16 *remote_len,
2923 struct i40e_asq_cmd_details *cmd_details)
2925 struct i40e_aq_desc desc;
2926 struct i40e_aqc_lldp_get_mib *cmd =
2927 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2928 struct i40e_aqc_lldp_get_mib *resp =
2929 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2930 enum i40e_status_code status;
2932 if (buff_size == 0 || !buff)
2933 return I40E_ERR_PARAM;
2935 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2936 /* Indirect Command */
2937 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2939 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2940 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2941 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2943 desc.datalen = CPU_TO_LE16(buff_size);
2945 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2946 if (buff_size > I40E_AQ_LARGE_BUF)
2947 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2949 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2951 if (local_len != NULL)
2952 *local_len = LE16_TO_CPU(resp->local_len);
2953 if (remote_len != NULL)
2954 *remote_len = LE16_TO_CPU(resp->remote_len);
2961 * i40e_aq_cfg_lldp_mib_change_event
2962 * @hw: pointer to the hw struct
2963 * @enable_update: Enable or Disable event posting
2964 * @cmd_details: pointer to command details structure or NULL
2966 * Enable or Disable posting of an event on ARQ when LLDP MIB
2967 * associated with the interface changes
2969 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2971 struct i40e_asq_cmd_details *cmd_details)
2973 struct i40e_aq_desc desc;
2974 struct i40e_aqc_lldp_update_mib *cmd =
2975 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2976 enum i40e_status_code status;
2978 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2981 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2983 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2989 * i40e_aq_add_lldp_tlv
2990 * @hw: pointer to the hw struct
2991 * @bridge_type: type of bridge
2992 * @buff: buffer with TLV to add
2993 * @buff_size: length of the buffer
2994 * @tlv_len: length of the TLV to be added
2995 * @mib_len: length of the LLDP MIB returned in response
2996 * @cmd_details: pointer to command details structure or NULL
2998 * Add the specified TLV to LLDP Local MIB for the given bridge type,
2999 * it is responsibility of the caller to make sure that the TLV is not
3000 * already present in the LLDPDU.
3001 * In return firmware will write the complete LLDP MIB with the newly
3002 * added TLV in the response buffer.
3004 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3005 void *buff, u16 buff_size, u16 tlv_len,
3007 struct i40e_asq_cmd_details *cmd_details)
3009 struct i40e_aq_desc desc;
3010 struct i40e_aqc_lldp_add_tlv *cmd =
3011 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3012 enum i40e_status_code status;
3014 if (buff_size == 0 || !buff || tlv_len == 0)
3015 return I40E_ERR_PARAM;
3017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3019 /* Indirect Command */
3020 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3021 if (buff_size > I40E_AQ_LARGE_BUF)
3022 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3023 desc.datalen = CPU_TO_LE16(buff_size);
3025 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3026 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3027 cmd->len = CPU_TO_LE16(tlv_len);
3029 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3031 if (mib_len != NULL)
3032 *mib_len = LE16_TO_CPU(desc.datalen);
3039 * i40e_aq_update_lldp_tlv
3040 * @hw: pointer to the hw struct
3041 * @bridge_type: type of bridge
3042 * @buff: buffer with TLV to update
3043 * @buff_size: size of the buffer holding original and updated TLVs
3044 * @old_len: Length of the Original TLV
3045 * @new_len: Length of the Updated TLV
3046 * @offset: offset of the updated TLV in the buff
3047 * @mib_len: length of the returned LLDP MIB
3048 * @cmd_details: pointer to command details structure or NULL
3050 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3051 * Firmware will place the complete LLDP MIB in response buffer with the
3054 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3055 u8 bridge_type, void *buff, u16 buff_size,
3056 u16 old_len, u16 new_len, u16 offset,
3058 struct i40e_asq_cmd_details *cmd_details)
3060 struct i40e_aq_desc desc;
3061 struct i40e_aqc_lldp_update_tlv *cmd =
3062 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3063 enum i40e_status_code status;
3065 if (buff_size == 0 || !buff || offset == 0 ||
3066 old_len == 0 || new_len == 0)
3067 return I40E_ERR_PARAM;
3069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3071 /* Indirect Command */
3072 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3073 if (buff_size > I40E_AQ_LARGE_BUF)
3074 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3075 desc.datalen = CPU_TO_LE16(buff_size);
3077 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3078 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3079 cmd->old_len = CPU_TO_LE16(old_len);
3080 cmd->new_offset = CPU_TO_LE16(offset);
3081 cmd->new_len = CPU_TO_LE16(new_len);
3083 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3085 if (mib_len != NULL)
3086 *mib_len = LE16_TO_CPU(desc.datalen);
3093 * i40e_aq_delete_lldp_tlv
3094 * @hw: pointer to the hw struct
3095 * @bridge_type: type of bridge
3096 * @buff: pointer to a user supplied buffer that has the TLV
3097 * @buff_size: length of the buffer
3098 * @tlv_len: length of the TLV to be deleted
3099 * @mib_len: length of the returned LLDP MIB
3100 * @cmd_details: pointer to command details structure or NULL
3102 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3103 * The firmware places the entire LLDP MIB in the response buffer.
3105 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3106 u8 bridge_type, void *buff, u16 buff_size,
3107 u16 tlv_len, u16 *mib_len,
3108 struct i40e_asq_cmd_details *cmd_details)
3110 struct i40e_aq_desc desc;
3111 struct i40e_aqc_lldp_add_tlv *cmd =
3112 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3113 enum i40e_status_code status;
3115 if (buff_size == 0 || !buff)
3116 return I40E_ERR_PARAM;
3118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3120 /* Indirect Command */
3121 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3122 if (buff_size > I40E_AQ_LARGE_BUF)
3123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3124 desc.datalen = CPU_TO_LE16(buff_size);
3125 cmd->len = CPU_TO_LE16(tlv_len);
3126 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3127 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3129 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3131 if (mib_len != NULL)
3132 *mib_len = LE16_TO_CPU(desc.datalen);
3140 * @hw: pointer to the hw struct
3141 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3142 * @cmd_details: pointer to command details structure or NULL
3144 * Stop or Shutdown the embedded LLDP Agent
3146 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3147 struct i40e_asq_cmd_details *cmd_details)
3149 struct i40e_aq_desc desc;
3150 struct i40e_aqc_lldp_stop *cmd =
3151 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3152 enum i40e_status_code status;
3154 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3157 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3159 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3165 * i40e_aq_start_lldp
3166 * @hw: pointer to the hw struct
3167 * @cmd_details: pointer to command details structure or NULL
3169 * Start the embedded LLDP Agent on all ports.
3171 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3172 struct i40e_asq_cmd_details *cmd_details)
3174 struct i40e_aq_desc desc;
3175 struct i40e_aqc_lldp_start *cmd =
3176 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3177 enum i40e_status_code status;
3179 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3181 cmd->command = I40E_AQ_LLDP_AGENT_START;
3183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3189 * i40e_aq_get_cee_dcb_config
3190 * @hw: pointer to the hw struct
3191 * @buff: response buffer that stores CEE operational configuration
3192 * @buff_size: size of the buffer passed
3193 * @cmd_details: pointer to command details structure or NULL
3195 * Get CEE DCBX mode operational configuration from firmware
3197 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3198 void *buff, u16 buff_size,
3199 struct i40e_asq_cmd_details *cmd_details)
3201 struct i40e_aq_desc desc;
3202 enum i40e_status_code status;
3204 if (buff_size == 0 || !buff)
3205 return I40E_ERR_PARAM;
3207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3209 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3210 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3217 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3218 * @hw: pointer to the hw struct
3219 * @start_agent: True if DCBx Agent needs to be Started
3220 * False if DCBx Agent needs to be Stopped
3221 * @cmd_details: pointer to command details structure or NULL
3223 * Start/Stop the embedded dcbx Agent
3225 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3227 struct i40e_asq_cmd_details *cmd_details)
3229 struct i40e_aq_desc desc;
3230 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3231 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3233 enum i40e_status_code status;
3235 i40e_fill_default_direct_cmd_desc(&desc,
3236 i40e_aqc_opc_lldp_stop_start_spec_agent);
3239 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3241 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3247 * i40e_aq_add_udp_tunnel
3248 * @hw: pointer to the hw struct
3249 * @udp_port: the UDP port to add
3250 * @header_len: length of the tunneling header length in DWords
3251 * @protocol_index: protocol index type
3252 * @filter_index: pointer to filter index
3253 * @cmd_details: pointer to command details structure or NULL
3255 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3256 u16 udp_port, u8 protocol_index,
3258 struct i40e_asq_cmd_details *cmd_details)
3260 struct i40e_aq_desc desc;
3261 struct i40e_aqc_add_udp_tunnel *cmd =
3262 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3263 struct i40e_aqc_del_udp_tunnel_completion *resp =
3264 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3265 enum i40e_status_code status;
3267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3269 cmd->udp_port = CPU_TO_LE16(udp_port);
3270 cmd->protocol_type = protocol_index;
3272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3275 *filter_index = resp->index;
3281 * i40e_aq_del_udp_tunnel
3282 * @hw: pointer to the hw struct
3283 * @index: filter index
3284 * @cmd_details: pointer to command details structure or NULL
3286 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3287 struct i40e_asq_cmd_details *cmd_details)
3289 struct i40e_aq_desc desc;
3290 struct i40e_aqc_remove_udp_tunnel *cmd =
3291 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3292 enum i40e_status_code status;
3294 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3304 * i40e_aq_get_switch_resource_alloc (0x0204)
3305 * @hw: pointer to the hw struct
3306 * @num_entries: pointer to u8 to store the number of resource entries returned
3307 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3308 * to store the resource information for all resource types. Each
3309 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3310 * @count: size, in bytes, of the buffer provided
3311 * @cmd_details: pointer to command details structure or NULL
3313 * Query the resources allocated to a function.
3315 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3317 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3319 struct i40e_asq_cmd_details *cmd_details)
3321 struct i40e_aq_desc desc;
3322 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3323 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3324 enum i40e_status_code status;
3326 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp);
3328 i40e_fill_default_direct_cmd_desc(&desc,
3329 i40e_aqc_opc_get_switch_resource_alloc);
3331 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3332 if (length > I40E_AQ_LARGE_BUF)
3333 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3335 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3338 *num_entries = cmd_resp->num_entries;
3344 * i40e_aq_delete_element - Delete switch element
3345 * @hw: pointer to the hw struct
3346 * @seid: the SEID to delete from the switch
3347 * @cmd_details: pointer to command details structure or NULL
3349 * This deletes a switch element from the switch.
3351 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3352 struct i40e_asq_cmd_details *cmd_details)
3354 struct i40e_aq_desc desc;
3355 struct i40e_aqc_switch_seid *cmd =
3356 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3357 enum i40e_status_code status;
3360 return I40E_ERR_PARAM;
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3364 cmd->seid = CPU_TO_LE16(seid);
3366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3372 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3373 * @hw: pointer to the hw struct
3374 * @flags: component flags
3375 * @mac_seid: uplink seid (MAC SEID)
3376 * @vsi_seid: connected vsi seid
3377 * @ret_seid: seid of create pv component
3379 * This instantiates an i40e port virtualizer with specified flags.
3380 * Depending on specified flags the port virtualizer can act as a
3381 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3383 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3384 u16 mac_seid, u16 vsi_seid,
3387 struct i40e_aq_desc desc;
3388 struct i40e_aqc_add_update_pv *cmd =
3389 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3390 struct i40e_aqc_add_update_pv_completion *resp =
3391 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3392 enum i40e_status_code status;
3395 return I40E_ERR_PARAM;
3397 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3398 cmd->command_flags = CPU_TO_LE16(flags);
3399 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3400 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3402 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3403 if (!status && ret_seid)
3404 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3410 * i40e_aq_add_tag - Add an S/E-tag
3411 * @hw: pointer to the hw struct
3412 * @direct_to_queue: should s-tag direct flow to a specific queue
3413 * @vsi_seid: VSI SEID to use this tag
3414 * @tag: value of the tag
3415 * @queue_num: queue number, only valid is direct_to_queue is true
3416 * @tags_used: return value, number of tags in use by this PF
3417 * @tags_free: return value, number of unallocated tags
3418 * @cmd_details: pointer to command details structure or NULL
3420 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3421 * the number of tags allocated by the PF, and the number of unallocated
3424 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3425 u16 vsi_seid, u16 tag, u16 queue_num,
3426 u16 *tags_used, u16 *tags_free,
3427 struct i40e_asq_cmd_details *cmd_details)
3429 struct i40e_aq_desc desc;
3430 struct i40e_aqc_add_tag *cmd =
3431 (struct i40e_aqc_add_tag *)&desc.params.raw;
3432 struct i40e_aqc_add_remove_tag_completion *resp =
3433 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3434 enum i40e_status_code status;
3437 return I40E_ERR_PARAM;
3439 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3441 cmd->seid = CPU_TO_LE16(vsi_seid);
3442 cmd->tag = CPU_TO_LE16(tag);
3443 if (direct_to_queue) {
3444 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3445 cmd->queue_number = CPU_TO_LE16(queue_num);
3448 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3451 if (tags_used != NULL)
3452 *tags_used = LE16_TO_CPU(resp->tags_used);
3453 if (tags_free != NULL)
3454 *tags_free = LE16_TO_CPU(resp->tags_free);
3461 * i40e_aq_remove_tag - Remove an S- or E-tag
3462 * @hw: pointer to the hw struct
3463 * @vsi_seid: VSI SEID this tag is associated with
3464 * @tag: value of the S-tag to delete
3465 * @tags_used: return value, number of tags in use by this PF
3466 * @tags_free: return value, number of unallocated tags
3467 * @cmd_details: pointer to command details structure or NULL
3469 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3470 * the number of tags allocated by the PF, and the number of unallocated
3473 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3474 u16 tag, u16 *tags_used, u16 *tags_free,
3475 struct i40e_asq_cmd_details *cmd_details)
3477 struct i40e_aq_desc desc;
3478 struct i40e_aqc_remove_tag *cmd =
3479 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3480 struct i40e_aqc_add_remove_tag_completion *resp =
3481 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3482 enum i40e_status_code status;
3485 return I40E_ERR_PARAM;
3487 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3489 cmd->seid = CPU_TO_LE16(vsi_seid);
3490 cmd->tag = CPU_TO_LE16(tag);
3492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3495 if (tags_used != NULL)
3496 *tags_used = LE16_TO_CPU(resp->tags_used);
3497 if (tags_free != NULL)
3498 *tags_free = LE16_TO_CPU(resp->tags_free);
3505 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3506 * @hw: pointer to the hw struct
3507 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3508 * @etag: value of E-tag to add
3509 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3510 * @buf: address of indirect buffer
3511 * @tags_used: return value, number of E-tags in use by this port
3512 * @tags_free: return value, number of unallocated M-tags
3513 * @cmd_details: pointer to command details structure or NULL
3515 * This associates a multicast E-tag to a port virtualizer. It will return
3516 * the number of tags allocated by the PF, and the number of unallocated
3519 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3520 * num_tags_in_buf long.
3522 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3523 u16 etag, u8 num_tags_in_buf, void *buf,
3524 u16 *tags_used, u16 *tags_free,
3525 struct i40e_asq_cmd_details *cmd_details)
3527 struct i40e_aq_desc desc;
3528 struct i40e_aqc_add_remove_mcast_etag *cmd =
3529 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3530 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3531 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3532 enum i40e_status_code status;
3533 u16 length = sizeof(u16) * num_tags_in_buf;
3535 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3536 return I40E_ERR_PARAM;
3538 i40e_fill_default_direct_cmd_desc(&desc,
3539 i40e_aqc_opc_add_multicast_etag);
3541 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3542 cmd->etag = CPU_TO_LE16(etag);
3543 cmd->num_unicast_etags = num_tags_in_buf;
3545 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3546 if (length > I40E_AQ_LARGE_BUF)
3547 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3549 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3552 if (tags_used != NULL)
3553 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3554 if (tags_free != NULL)
3555 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3562 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3563 * @hw: pointer to the hw struct
3564 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3565 * @etag: value of the E-tag to remove
3566 * @tags_used: return value, number of tags in use by this port
3567 * @tags_free: return value, number of unallocated tags
3568 * @cmd_details: pointer to command details structure or NULL
3570 * This deletes an E-tag from the port virtualizer. It will return
3571 * the number of tags allocated by the port, and the number of unallocated
3574 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3575 u16 etag, u16 *tags_used, u16 *tags_free,
3576 struct i40e_asq_cmd_details *cmd_details)
3578 struct i40e_aq_desc desc;
3579 struct i40e_aqc_add_remove_mcast_etag *cmd =
3580 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3581 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3582 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3583 enum i40e_status_code status;
3587 return I40E_ERR_PARAM;
3589 i40e_fill_default_direct_cmd_desc(&desc,
3590 i40e_aqc_opc_remove_multicast_etag);
3592 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3593 cmd->etag = CPU_TO_LE16(etag);
3595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3598 if (tags_used != NULL)
3599 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3600 if (tags_free != NULL)
3601 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3608 * i40e_aq_update_tag - Update an S/E-tag
3609 * @hw: pointer to the hw struct
3610 * @vsi_seid: VSI SEID using this S-tag
3611 * @old_tag: old tag value
3612 * @new_tag: new tag value
3613 * @tags_used: return value, number of tags in use by this PF
3614 * @tags_free: return value, number of unallocated tags
3615 * @cmd_details: pointer to command details structure or NULL
3617 * This updates the value of the tag currently attached to this VSI
3618 * in the switch complex. It will return the number of tags allocated
3619 * by the PF, and the number of unallocated tags available.
3621 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3622 u16 old_tag, u16 new_tag, u16 *tags_used,
3624 struct i40e_asq_cmd_details *cmd_details)
3626 struct i40e_aq_desc desc;
3627 struct i40e_aqc_update_tag *cmd =
3628 (struct i40e_aqc_update_tag *)&desc.params.raw;
3629 struct i40e_aqc_update_tag_completion *resp =
3630 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3631 enum i40e_status_code status;
3634 return I40E_ERR_PARAM;
3636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3638 cmd->seid = CPU_TO_LE16(vsi_seid);
3639 cmd->old_tag = CPU_TO_LE16(old_tag);
3640 cmd->new_tag = CPU_TO_LE16(new_tag);
3642 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3645 if (tags_used != NULL)
3646 *tags_used = LE16_TO_CPU(resp->tags_used);
3647 if (tags_free != NULL)
3648 *tags_free = LE16_TO_CPU(resp->tags_free);
3655 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3656 * @hw: pointer to the hw struct
3657 * @tcmap: TC map for request/release any ignore PFC condition
3658 * @request: request or release ignore PFC condition
3659 * @tcmap_ret: return TCs for which PFC is currently ignored
3660 * @cmd_details: pointer to command details structure or NULL
3662 * This sends out request/release to ignore PFC condition for a TC.
3663 * It will return the TCs for which PFC is currently ignored.
3665 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3666 bool request, u8 *tcmap_ret,
3667 struct i40e_asq_cmd_details *cmd_details)
3669 struct i40e_aq_desc desc;
3670 struct i40e_aqc_pfc_ignore *cmd_resp =
3671 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3672 enum i40e_status_code status;
3674 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3677 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3679 cmd_resp->tc_bitmap = tcmap;
3681 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3684 if (tcmap_ret != NULL)
3685 *tcmap_ret = cmd_resp->tc_bitmap;
3692 * i40e_aq_dcb_updated - DCB Updated Command
3693 * @hw: pointer to the hw struct
3694 * @cmd_details: pointer to command details structure or NULL
3696 * When LLDP is handled in PF this command is used by the PF
3697 * to notify EMP that a DCB setting is modified.
3698 * When LLDP is handled in EMP this command is used by the PF
3699 * to notify EMP whenever one of the following parameters get
3701 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3702 * - PCIRTT in PRTDCB_GENC.PCIRTT
3703 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3704 * EMP will return when the shared RPB settings have been
3705 * recomputed and modified. The retval field in the descriptor
3706 * will be set to 0 when RPB is modified.
3708 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3709 struct i40e_asq_cmd_details *cmd_details)
3711 struct i40e_aq_desc desc;
3712 enum i40e_status_code status;
3714 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3716 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3722 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3723 * @hw: pointer to the hw struct
3724 * @seid: defines the SEID of the switch for which the stats are requested
3725 * @vlan_id: the VLAN ID for which the statistics are requested
3726 * @stat_index: index of the statistics counters block assigned to this VLAN
3727 * @cmd_details: pointer to command details structure or NULL
3729 * XL710 supports 128 smonVlanStats counters.This command is used to
3730 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3733 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3734 u16 vlan_id, u16 *stat_index,
3735 struct i40e_asq_cmd_details *cmd_details)
3737 struct i40e_aq_desc desc;
3738 struct i40e_aqc_add_remove_statistics *cmd_resp =
3739 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3740 enum i40e_status_code status;
3742 if ((seid == 0) || (stat_index == NULL))
3743 return I40E_ERR_PARAM;
3745 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3747 cmd_resp->seid = CPU_TO_LE16(seid);
3748 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3750 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3753 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3759 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3760 * @hw: pointer to the hw struct
3761 * @seid: defines the SEID of the switch for which the stats are requested
3762 * @vlan_id: the VLAN ID for which the statistics are requested
3763 * @stat_index: index of the statistics counters block assigned to this VLAN
3764 * @cmd_details: pointer to command details structure or NULL
3766 * XL710 supports 128 smonVlanStats counters.This command is used to
3767 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
3770 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
3771 u16 vlan_id, u16 stat_index,
3772 struct i40e_asq_cmd_details *cmd_details)
3774 struct i40e_aq_desc desc;
3775 struct i40e_aqc_add_remove_statistics *cmd =
3776 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3777 enum i40e_status_code status;
3780 return I40E_ERR_PARAM;
3782 i40e_fill_default_direct_cmd_desc(&desc,
3783 i40e_aqc_opc_remove_statistics);
3785 cmd->seid = CPU_TO_LE16(seid);
3786 cmd->vlan = CPU_TO_LE16(vlan_id);
3787 cmd->stat_index = CPU_TO_LE16(stat_index);
3789 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3795 * i40e_aq_set_port_parameters - set physical port parameters.
3796 * @hw: pointer to the hw struct
3797 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
3798 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
3799 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
3800 * @double_vlan: if set double VLAN is enabled
3801 * @cmd_details: pointer to command details structure or NULL
3803 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
3804 u16 bad_frame_vsi, bool save_bad_pac,
3805 bool pad_short_pac, bool double_vlan,
3806 struct i40e_asq_cmd_details *cmd_details)
3808 struct i40e_aqc_set_port_parameters *cmd;
3809 enum i40e_status_code status;
3810 struct i40e_aq_desc desc;
3811 u16 command_flags = 0;
3813 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
3815 i40e_fill_default_direct_cmd_desc(&desc,
3816 i40e_aqc_opc_set_port_parameters);
3818 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3820 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
3822 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
3824 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3825 cmd->command_flags = CPU_TO_LE16(command_flags);
3827 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3833 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3834 * @hw: pointer to the hw struct
3835 * @seid: seid for the physical port/switching component/vsi
3836 * @buff: Indirect buffer to hold data parameters and response
3837 * @buff_size: Indirect buffer size
3838 * @opcode: Tx scheduler AQ command opcode
3839 * @cmd_details: pointer to command details structure or NULL
3841 * Generic command handler for Tx scheduler AQ commands
3843 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3844 void *buff, u16 buff_size,
3845 enum i40e_admin_queue_opc opcode,
3846 struct i40e_asq_cmd_details *cmd_details)
3848 struct i40e_aq_desc desc;
3849 struct i40e_aqc_tx_sched_ind *cmd =
3850 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3851 enum i40e_status_code status;
3852 bool cmd_param_flag = false;
3855 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3856 case i40e_aqc_opc_configure_vsi_tc_bw:
3857 case i40e_aqc_opc_enable_switching_comp_ets:
3858 case i40e_aqc_opc_modify_switching_comp_ets:
3859 case i40e_aqc_opc_disable_switching_comp_ets:
3860 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3861 case i40e_aqc_opc_configure_switching_comp_bw_config:
3862 cmd_param_flag = true;
3864 case i40e_aqc_opc_query_vsi_bw_config:
3865 case i40e_aqc_opc_query_vsi_ets_sla_config:
3866 case i40e_aqc_opc_query_switching_comp_ets_config:
3867 case i40e_aqc_opc_query_port_ets_config:
3868 case i40e_aqc_opc_query_switching_comp_bw_config:
3869 cmd_param_flag = false;
3872 return I40E_ERR_PARAM;
3875 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3877 /* Indirect command */
3878 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3880 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
3881 if (buff_size > I40E_AQ_LARGE_BUF)
3882 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3884 desc.datalen = CPU_TO_LE16(buff_size);
3886 cmd->vsi_seid = CPU_TO_LE16(seid);
3888 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3894 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3895 * @hw: pointer to the hw struct
3897 * @credit: BW limit credits (0 = disabled)
3898 * @max_credit: Max BW limit credits
3899 * @cmd_details: pointer to command details structure or NULL
3901 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3902 u16 seid, u16 credit, u8 max_credit,
3903 struct i40e_asq_cmd_details *cmd_details)
3905 struct i40e_aq_desc desc;
3906 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3907 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3908 enum i40e_status_code status;
3910 i40e_fill_default_direct_cmd_desc(&desc,
3911 i40e_aqc_opc_configure_vsi_bw_limit);
3913 cmd->vsi_seid = CPU_TO_LE16(seid);
3914 cmd->credit = CPU_TO_LE16(credit);
3915 cmd->max_credit = max_credit;
3917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3923 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
3924 * @hw: pointer to the hw struct
3925 * @seid: switching component seid
3926 * @credit: BW limit credits (0 = disabled)
3927 * @max_bw: Max BW limit credits
3928 * @cmd_details: pointer to command details structure or NULL
3930 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
3931 u16 seid, u16 credit, u8 max_bw,
3932 struct i40e_asq_cmd_details *cmd_details)
3934 struct i40e_aq_desc desc;
3935 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
3936 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
3937 enum i40e_status_code status;
3939 i40e_fill_default_direct_cmd_desc(&desc,
3940 i40e_aqc_opc_configure_switching_comp_bw_limit);
3942 cmd->seid = CPU_TO_LE16(seid);
3943 cmd->credit = CPU_TO_LE16(credit);
3944 cmd->max_bw = max_bw;
3946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3952 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
3953 * @hw: pointer to the hw struct
3955 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3956 * @cmd_details: pointer to command details structure or NULL
3958 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
3960 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
3961 struct i40e_asq_cmd_details *cmd_details)
3963 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3964 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
3969 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3970 * @hw: pointer to the hw struct
3972 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3973 * @cmd_details: pointer to command details structure or NULL
3975 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3977 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3978 struct i40e_asq_cmd_details *cmd_details)
3980 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3981 i40e_aqc_opc_configure_vsi_tc_bw,
3986 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
3987 * @hw: pointer to the hw struct
3988 * @seid: seid of the switching component
3989 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
3990 * @cmd_details: pointer to command details structure or NULL
3992 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
3993 struct i40e_hw *hw, u16 seid,
3994 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
3995 struct i40e_asq_cmd_details *cmd_details)
3997 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3998 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4003 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4004 * @hw: pointer to the hw struct
4005 * @seid: seid of the VSI
4006 * @bw_data: Buffer to hold VSI BW configuration
4007 * @cmd_details: pointer to command details structure or NULL
4009 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4011 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4012 struct i40e_asq_cmd_details *cmd_details)
4014 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4015 i40e_aqc_opc_query_vsi_bw_config,
4020 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4021 * @hw: pointer to the hw struct
4022 * @seid: seid of the VSI
4023 * @bw_data: Buffer to hold VSI BW configuration per TC
4024 * @cmd_details: pointer to command details structure or NULL
4026 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4028 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4029 struct i40e_asq_cmd_details *cmd_details)
4031 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4032 i40e_aqc_opc_query_vsi_ets_sla_config,
4037 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4038 * @hw: pointer to the hw struct
4039 * @seid: seid of the switching component
4040 * @bw_data: Buffer to hold switching component's per TC BW config
4041 * @cmd_details: pointer to command details structure or NULL
4043 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4045 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4046 struct i40e_asq_cmd_details *cmd_details)
4048 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4049 i40e_aqc_opc_query_switching_comp_ets_config,
4054 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4055 * @hw: pointer to the hw struct
4056 * @seid: seid of the VSI or switching component connected to Physical Port
4057 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4058 * @cmd_details: pointer to command details structure or NULL
4060 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4062 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4063 struct i40e_asq_cmd_details *cmd_details)
4065 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4066 i40e_aqc_opc_query_port_ets_config,
4071 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4072 * @hw: pointer to the hw struct
4073 * @seid: seid of the switching component
4074 * @bw_data: Buffer to hold switching component's BW configuration
4075 * @cmd_details: pointer to command details structure or NULL
4077 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4079 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4080 struct i40e_asq_cmd_details *cmd_details)
4082 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4083 i40e_aqc_opc_query_switching_comp_bw_config,
4088 * i40e_validate_filter_settings
4089 * @hw: pointer to the hardware structure
4090 * @settings: Filter control settings
4092 * Check and validate the filter control settings passed.
4093 * The function checks for the valid filter/context sizes being
4094 * passed for FCoE and PE.
4096 * Returns I40E_SUCCESS if the values passed are valid and within
4097 * range else returns an error.
4099 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4100 struct i40e_filter_control_settings *settings)
4102 u32 fcoe_cntx_size, fcoe_filt_size;
4103 u32 pe_cntx_size, pe_filt_size;
4108 /* Validate FCoE settings passed */
4109 switch (settings->fcoe_filt_num) {
4110 case I40E_HASH_FILTER_SIZE_1K:
4111 case I40E_HASH_FILTER_SIZE_2K:
4112 case I40E_HASH_FILTER_SIZE_4K:
4113 case I40E_HASH_FILTER_SIZE_8K:
4114 case I40E_HASH_FILTER_SIZE_16K:
4115 case I40E_HASH_FILTER_SIZE_32K:
4116 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4117 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4120 return I40E_ERR_PARAM;
4123 switch (settings->fcoe_cntx_num) {
4124 case I40E_DMA_CNTX_SIZE_512:
4125 case I40E_DMA_CNTX_SIZE_1K:
4126 case I40E_DMA_CNTX_SIZE_2K:
4127 case I40E_DMA_CNTX_SIZE_4K:
4128 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4129 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4132 return I40E_ERR_PARAM;
4135 /* Validate PE settings passed */
4136 switch (settings->pe_filt_num) {
4137 case I40E_HASH_FILTER_SIZE_1K:
4138 case I40E_HASH_FILTER_SIZE_2K:
4139 case I40E_HASH_FILTER_SIZE_4K:
4140 case I40E_HASH_FILTER_SIZE_8K:
4141 case I40E_HASH_FILTER_SIZE_16K:
4142 case I40E_HASH_FILTER_SIZE_32K:
4143 case I40E_HASH_FILTER_SIZE_64K:
4144 case I40E_HASH_FILTER_SIZE_128K:
4145 case I40E_HASH_FILTER_SIZE_256K:
4146 case I40E_HASH_FILTER_SIZE_512K:
4147 case I40E_HASH_FILTER_SIZE_1M:
4148 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4149 pe_filt_size <<= (u32)settings->pe_filt_num;
4152 return I40E_ERR_PARAM;
4155 switch (settings->pe_cntx_num) {
4156 case I40E_DMA_CNTX_SIZE_512:
4157 case I40E_DMA_CNTX_SIZE_1K:
4158 case I40E_DMA_CNTX_SIZE_2K:
4159 case I40E_DMA_CNTX_SIZE_4K:
4160 case I40E_DMA_CNTX_SIZE_8K:
4161 case I40E_DMA_CNTX_SIZE_16K:
4162 case I40E_DMA_CNTX_SIZE_32K:
4163 case I40E_DMA_CNTX_SIZE_64K:
4164 case I40E_DMA_CNTX_SIZE_128K:
4165 case I40E_DMA_CNTX_SIZE_256K:
4166 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4167 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4170 return I40E_ERR_PARAM;
4173 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4174 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4175 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4176 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4177 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4178 return I40E_ERR_INVALID_SIZE;
4180 return I40E_SUCCESS;
4184 * i40e_set_filter_control
4185 * @hw: pointer to the hardware structure
4186 * @settings: Filter control settings
4188 * Set the Queue Filters for PE/FCoE and enable filters required
4189 * for a single PF. It is expected that these settings are programmed
4190 * at the driver initialization time.
4192 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4193 struct i40e_filter_control_settings *settings)
4195 enum i40e_status_code ret = I40E_SUCCESS;
4196 u32 hash_lut_size = 0;
4200 return I40E_ERR_PARAM;
4202 /* Validate the input settings */
4203 ret = i40e_validate_filter_settings(hw, settings);
4207 /* Read the PF Queue Filter control register */
4208 val = rd32(hw, I40E_PFQF_CTL_0);
4210 /* Program required PE hash buckets for the PF */
4211 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4212 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4213 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4214 /* Program required PE contexts for the PF */
4215 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4216 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4217 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4219 /* Program required FCoE hash buckets for the PF */
4220 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4221 val |= ((u32)settings->fcoe_filt_num <<
4222 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4223 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4224 /* Program required FCoE DDP contexts for the PF */
4225 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4226 val |= ((u32)settings->fcoe_cntx_num <<
4227 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4228 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4230 /* Program Hash LUT size for the PF */
4231 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4232 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4234 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4235 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4237 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4238 if (settings->enable_fdir)
4239 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4240 if (settings->enable_ethtype)
4241 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4242 if (settings->enable_macvlan)
4243 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4245 wr32(hw, I40E_PFQF_CTL_0, val);
4247 return I40E_SUCCESS;
4251 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4252 * @hw: pointer to the hw struct
4253 * @mac_addr: MAC address to use in the filter
4254 * @ethtype: Ethertype to use in the filter
4255 * @flags: Flags that needs to be applied to the filter
4256 * @vsi_seid: seid of the control VSI
4257 * @queue: VSI queue number to send the packet to
4258 * @is_add: Add control packet filter if True else remove
4259 * @stats: Structure to hold information on control filter counts
4260 * @cmd_details: pointer to command details structure or NULL
4262 * This command will Add or Remove control packet filter for a control VSI.
4263 * In return it will update the total number of perfect filter count in
4266 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4267 u8 *mac_addr, u16 ethtype, u16 flags,
4268 u16 vsi_seid, u16 queue, bool is_add,
4269 struct i40e_control_filter_stats *stats,
4270 struct i40e_asq_cmd_details *cmd_details)
4272 struct i40e_aq_desc desc;
4273 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4274 (struct i40e_aqc_add_remove_control_packet_filter *)
4276 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4277 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4279 enum i40e_status_code status;
4282 return I40E_ERR_PARAM;
4285 i40e_fill_default_direct_cmd_desc(&desc,
4286 i40e_aqc_opc_add_control_packet_filter);
4287 cmd->queue = CPU_TO_LE16(queue);
4289 i40e_fill_default_direct_cmd_desc(&desc,
4290 i40e_aqc_opc_remove_control_packet_filter);
4294 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4295 I40E_NONDMA_TO_NONDMA);
4297 cmd->etype = CPU_TO_LE16(ethtype);
4298 cmd->flags = CPU_TO_LE16(flags);
4299 cmd->seid = CPU_TO_LE16(vsi_seid);
4301 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4303 if (!status && stats) {
4304 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4305 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4306 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4307 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4314 * i40e_aq_add_cloud_filters
4315 * @hw: pointer to the hardware structure
4316 * @seid: VSI seid to add cloud filters from
4317 * @filters: Buffer which contains the filters to be added
4318 * @filter_count: number of filters contained in the buffer
4320 * Set the cloud filters for a given VSI. The contents of the
4321 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4322 * in by the caller of the function.
4325 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4327 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4330 struct i40e_aq_desc desc;
4331 struct i40e_aqc_add_remove_cloud_filters *cmd =
4332 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4334 enum i40e_status_code status;
4336 i40e_fill_default_direct_cmd_desc(&desc,
4337 i40e_aqc_opc_add_cloud_filters);
4339 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4341 desc.datalen = CPU_TO_LE16(buff_len);
4342 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4343 cmd->num_filters = filter_count;
4344 cmd->seid = CPU_TO_LE16(seid);
4346 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4352 * i40e_aq_remove_cloud_filters
4353 * @hw: pointer to the hardware structure
4354 * @seid: VSI seid to remove cloud filters from
4355 * @filters: Buffer which contains the filters to be removed
4356 * @filter_count: number of filters contained in the buffer
4358 * Remove the cloud filters for a given VSI. The contents of the
4359 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4360 * in by the caller of the function.
4363 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4365 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4368 struct i40e_aq_desc desc;
4369 struct i40e_aqc_add_remove_cloud_filters *cmd =
4370 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4371 enum i40e_status_code status;
4374 i40e_fill_default_direct_cmd_desc(&desc,
4375 i40e_aqc_opc_remove_cloud_filters);
4377 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) *
4379 desc.datalen = CPU_TO_LE16(buff_len);
4380 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4381 cmd->num_filters = filter_count;
4382 cmd->seid = CPU_TO_LE16(seid);
4384 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4390 * i40e_aq_alternate_write
4391 * @hw: pointer to the hardware structure
4392 * @reg_addr0: address of first dword to be read
4393 * @reg_val0: value to be written under 'reg_addr0'
4394 * @reg_addr1: address of second dword to be read
4395 * @reg_val1: value to be written under 'reg_addr1'
4397 * Write one or two dwords to alternate structure. Fields are indicated
4398 * by 'reg_addr0' and 'reg_addr1' register numbers.
4401 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4402 u32 reg_addr0, u32 reg_val0,
4403 u32 reg_addr1, u32 reg_val1)
4405 struct i40e_aq_desc desc;
4406 struct i40e_aqc_alternate_write *cmd_resp =
4407 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4408 enum i40e_status_code status;
4410 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4411 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4412 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4413 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4414 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4416 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4422 * i40e_aq_alternate_write_indirect
4423 * @hw: pointer to the hardware structure
4424 * @addr: address of a first register to be modified
4425 * @dw_count: number of alternate structure fields to write
4426 * @buffer: pointer to the command buffer
4428 * Write 'dw_count' dwords from 'buffer' to alternate structure
4429 * starting at 'addr'.
4432 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4433 u32 addr, u32 dw_count, void *buffer)
4435 struct i40e_aq_desc desc;
4436 struct i40e_aqc_alternate_ind_write *cmd_resp =
4437 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4438 enum i40e_status_code status;
4441 return I40E_ERR_PARAM;
4443 /* Indirect command */
4444 i40e_fill_default_direct_cmd_desc(&desc,
4445 i40e_aqc_opc_alternate_write_indirect);
4447 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4448 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4449 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4452 cmd_resp->address = CPU_TO_LE32(addr);
4453 cmd_resp->length = CPU_TO_LE32(dw_count);
4454 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4455 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4457 status = i40e_asq_send_command(hw, &desc, buffer,
4458 I40E_LO_DWORD(4*dw_count), NULL);
4464 * i40e_aq_alternate_read
4465 * @hw: pointer to the hardware structure
4466 * @reg_addr0: address of first dword to be read
4467 * @reg_val0: pointer for data read from 'reg_addr0'
4468 * @reg_addr1: address of second dword to be read
4469 * @reg_val1: pointer for data read from 'reg_addr1'
4471 * Read one or two dwords from alternate structure. Fields are indicated
4472 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4473 * is not passed then only register at 'reg_addr0' is read.
4476 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4477 u32 reg_addr0, u32 *reg_val0,
4478 u32 reg_addr1, u32 *reg_val1)
4480 struct i40e_aq_desc desc;
4481 struct i40e_aqc_alternate_write *cmd_resp =
4482 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4483 enum i40e_status_code status;
4485 if (reg_val0 == NULL)
4486 return I40E_ERR_PARAM;
4488 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4489 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4490 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4492 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4494 if (status == I40E_SUCCESS) {
4495 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4497 if (reg_val1 != NULL)
4498 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4505 * i40e_aq_alternate_read_indirect
4506 * @hw: pointer to the hardware structure
4507 * @addr: address of the alternate structure field
4508 * @dw_count: number of alternate structure fields to read
4509 * @buffer: pointer to the command buffer
4511 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4512 * place them in 'buffer'. The buffer should be allocated by caller.
4515 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4516 u32 addr, u32 dw_count, void *buffer)
4518 struct i40e_aq_desc desc;
4519 struct i40e_aqc_alternate_ind_write *cmd_resp =
4520 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4521 enum i40e_status_code status;
4524 return I40E_ERR_PARAM;
4526 /* Indirect command */
4527 i40e_fill_default_direct_cmd_desc(&desc,
4528 i40e_aqc_opc_alternate_read_indirect);
4530 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4531 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4532 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4533 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4535 cmd_resp->address = CPU_TO_LE32(addr);
4536 cmd_resp->length = CPU_TO_LE32(dw_count);
4537 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4538 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4540 status = i40e_asq_send_command(hw, &desc, buffer,
4541 I40E_LO_DWORD(4*dw_count), NULL);
4547 * i40e_aq_alternate_clear
4548 * @hw: pointer to the HW structure.
4550 * Clear the alternate structures of the port from which the function
4554 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4556 struct i40e_aq_desc desc;
4557 enum i40e_status_code status;
4559 i40e_fill_default_direct_cmd_desc(&desc,
4560 i40e_aqc_opc_alternate_clear_port);
4562 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4568 * i40e_aq_alternate_write_done
4569 * @hw: pointer to the HW structure.
4570 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4571 * @reset_needed: indicates the SW should trigger GLOBAL reset
4573 * Indicates to the FW that alternate structures have been changed.
4576 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4577 u8 bios_mode, bool *reset_needed)
4579 struct i40e_aq_desc desc;
4580 struct i40e_aqc_alternate_write_done *cmd =
4581 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4582 enum i40e_status_code status;
4584 if (reset_needed == NULL)
4585 return I40E_ERR_PARAM;
4587 i40e_fill_default_direct_cmd_desc(&desc,
4588 i40e_aqc_opc_alternate_write_done);
4590 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4592 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4594 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4595 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4601 * i40e_aq_set_oem_mode
4602 * @hw: pointer to the HW structure.
4603 * @oem_mode: the OEM mode to be used
4605 * Sets the device to a specific operating mode. Currently the only supported
4606 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4609 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4612 struct i40e_aq_desc desc;
4613 struct i40e_aqc_alternate_write_done *cmd =
4614 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4615 enum i40e_status_code status;
4617 i40e_fill_default_direct_cmd_desc(&desc,
4618 i40e_aqc_opc_alternate_set_mode);
4620 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4622 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4628 * i40e_aq_resume_port_tx
4629 * @hw: pointer to the hardware structure
4630 * @cmd_details: pointer to command details structure or NULL
4632 * Resume port's Tx traffic
4634 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4635 struct i40e_asq_cmd_details *cmd_details)
4637 struct i40e_aq_desc desc;
4638 enum i40e_status_code status;
4640 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4642 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4648 * i40e_set_pci_config_data - store PCI bus info
4649 * @hw: pointer to hardware structure
4650 * @link_status: the link status word from PCI config space
4652 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4654 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4656 hw->bus.type = i40e_bus_type_pci_express;
4658 switch (link_status & I40E_PCI_LINK_WIDTH) {
4659 case I40E_PCI_LINK_WIDTH_1:
4660 hw->bus.width = i40e_bus_width_pcie_x1;
4662 case I40E_PCI_LINK_WIDTH_2:
4663 hw->bus.width = i40e_bus_width_pcie_x2;
4665 case I40E_PCI_LINK_WIDTH_4:
4666 hw->bus.width = i40e_bus_width_pcie_x4;
4668 case I40E_PCI_LINK_WIDTH_8:
4669 hw->bus.width = i40e_bus_width_pcie_x8;
4672 hw->bus.width = i40e_bus_width_unknown;
4676 switch (link_status & I40E_PCI_LINK_SPEED) {
4677 case I40E_PCI_LINK_SPEED_2500:
4678 hw->bus.speed = i40e_bus_speed_2500;
4680 case I40E_PCI_LINK_SPEED_5000:
4681 hw->bus.speed = i40e_bus_speed_5000;
4683 case I40E_PCI_LINK_SPEED_8000:
4684 hw->bus.speed = i40e_bus_speed_8000;
4687 hw->bus.speed = i40e_bus_speed_unknown;
4693 * i40e_read_bw_from_alt_ram
4694 * @hw: pointer to the hardware structure
4695 * @max_bw: pointer for max_bw read
4696 * @min_bw: pointer for min_bw read
4697 * @min_valid: pointer for bool that is true if min_bw is a valid value
4698 * @max_valid: pointer for bool that is true if max_bw is a valid value
4700 * Read bw from the alternate ram for the given pf
4702 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4703 u32 *max_bw, u32 *min_bw,
4704 bool *min_valid, bool *max_valid)
4706 enum i40e_status_code status;
4707 u32 max_bw_addr, min_bw_addr;
4709 /* Calculate the address of the min/max bw registers */
4710 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4711 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4712 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4713 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4714 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4715 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4717 /* Read the bandwidths from alt ram */
4718 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4719 min_bw_addr, min_bw);
4721 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4726 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4735 * i40e_aq_configure_partition_bw
4736 * @hw: pointer to the hardware structure
4737 * @bw_data: Buffer holding valid pfs and bw limits
4738 * @cmd_details: pointer to command details
4740 * Configure partitions guaranteed/max bw
4742 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4743 struct i40e_aqc_configure_partition_bw_data *bw_data,
4744 struct i40e_asq_cmd_details *cmd_details)
4746 enum i40e_status_code status;
4747 struct i40e_aq_desc desc;
4748 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data);
4750 i40e_fill_default_direct_cmd_desc(&desc,
4751 i40e_aqc_opc_configure_partition_bw);
4753 /* Indirect command */
4754 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4755 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4757 if (bwd_size > I40E_AQ_LARGE_BUF)
4758 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4760 desc.datalen = CPU_TO_LE16(bwd_size);
4762 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
4766 #endif /* PF_DRIVER */
4770 * i40e_aq_send_msg_to_pf
4771 * @hw: pointer to the hardware structure
4772 * @v_opcode: opcodes for VF-PF communication
4773 * @v_retval: return error code
4774 * @msg: pointer to the msg buffer
4775 * @msglen: msg length
4776 * @cmd_details: pointer to command details
4778 * Send message to PF driver using admin queue. By default, this message
4779 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
4780 * completion before returning.
4782 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
4783 enum i40e_virtchnl_ops v_opcode,
4784 enum i40e_status_code v_retval,
4785 u8 *msg, u16 msglen,
4786 struct i40e_asq_cmd_details *cmd_details)
4788 struct i40e_aq_desc desc;
4789 struct i40e_asq_cmd_details details;
4790 enum i40e_status_code status;
4792 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
4793 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
4794 desc.cookie_high = CPU_TO_LE32(v_opcode);
4795 desc.cookie_low = CPU_TO_LE32(v_retval);
4797 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
4798 | I40E_AQ_FLAG_RD));
4799 if (msglen > I40E_AQ_LARGE_BUF)
4800 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4801 desc.datalen = CPU_TO_LE16(msglen);
4804 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
4805 details.async = true;
4806 cmd_details = &details;
4808 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
4809 msglen, cmd_details);
4814 * i40e_vf_parse_hw_config
4815 * @hw: pointer to the hardware structure
4816 * @msg: pointer to the virtual channel VF resource structure
4818 * Given a VF resource message from the PF, populate the hw struct
4819 * with appropriate information.
4821 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
4822 struct i40e_virtchnl_vf_resource *msg)
4824 struct i40e_virtchnl_vsi_resource *vsi_res;
4827 vsi_res = &msg->vsi_res[0];
4829 hw->dev_caps.num_vsis = msg->num_vsis;
4830 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
4831 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
4832 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
4833 hw->dev_caps.dcb = msg->vf_offload_flags &
4834 I40E_VIRTCHNL_VF_OFFLOAD_L2;
4835 hw->dev_caps.fcoe = (msg->vf_offload_flags &
4836 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
4837 hw->dev_caps.iwarp = (msg->vf_offload_flags &
4838 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
4839 for (i = 0; i < msg->num_vsis; i++) {
4840 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
4841 i40e_memcpy(hw->mac.perm_addr,
4842 vsi_res->default_mac_addr,
4843 I40E_ETH_LENGTH_OF_ADDRESS,
4844 I40E_NONDMA_TO_NONDMA);
4845 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
4846 I40E_ETH_LENGTH_OF_ADDRESS,
4847 I40E_NONDMA_TO_NONDMA);
4855 * @hw: pointer to the hardware structure
4857 * Send a VF_RESET message to the PF. Does not wait for response from PF
4858 * as none will be forthcoming. Immediately after calling this function,
4859 * the admin queue should be shut down and (optionally) reinitialized.
4861 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
4863 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
4864 I40E_SUCCESS, NULL, 0, NULL);
4866 #endif /* VF_DRIVER */