1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
31 ******************************************************************************/
33 #ifndef _I40E_OSDEP_H_
34 #define _I40E_OSDEP_H_
41 #include <rte_common.h>
42 #include <rte_memcpy.h>
43 #include <rte_byteorder.h>
44 #include <rte_cycles.h>
45 #include <rte_spinlock.h>
48 #include "../i40e_logs.h"
61 typedef enum i40e_status_code i40e_status;
63 #define hw_dbg(hw, S, A...) do {} while (0)
64 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
65 #define lower_32_bits(n) ((u32)(n))
66 #define low_16_bits(x) ((x) & 0xFFFF)
67 #define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)
70 #define ETH_ADDR_LEN 6
74 #define __le16 uint16_t
77 #define __le32 uint32_t
80 #define __le64 uint64_t
83 #define __be16 uint16_t
86 #define __be32 uint32_t
89 #define __be64 uint64_t
97 #define min(a,b) RTE_MIN(a,b)
98 #define max(a,b) RTE_MAX(a,b)
100 #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
101 #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
103 #define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S)
104 #define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)
106 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
107 #define DEBUGOUT2 DEBUGOUT1
108 #define DEBUGOUT3 DEBUGOUT2
109 #define DEBUGOUT6 DEBUGOUT3
110 #define DEBUGOUT7 DEBUGOUT6
112 #define i40e_debug(h, m, s, ...) \
114 if (((m) & (h)->debug_mask)) \
115 PMD_DRV_LOG_RAW(DEBUG, "i40e %02x.%x " s, \
116 (h)->bus.device, (h)->bus.func, \
120 #define I40E_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
121 #define I40E_PCI_REG_ADDR(a, reg) \
122 ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
123 static inline uint32_t i40e_read_addr(volatile void *addr)
125 return I40E_PCI_REG(addr);
127 #define I40E_PCI_REG_WRITE(reg, value) \
128 do {I40E_PCI_REG((reg)) = (value);} while(0)
130 #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
131 #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)
133 #define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))
134 #define I40E_WRITE_REG(hw, reg, value) \
135 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))
137 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))
138 #define wr32(a, reg, value) \
139 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))
140 #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)))
142 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
144 /* memory allocation tracking */
145 struct i40e_dma_mem {
150 } __attribute__((packed));
152 #define i40e_allocate_dma_mem(h, m, unused, s, a) \
153 i40e_allocate_dma_mem_d(h, m, s, a)
154 #define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m)
156 struct i40e_virt_mem {
159 } __attribute__((packed));
161 #define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s)
162 #define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m)
164 #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
165 #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
166 #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
167 #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
168 #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
169 #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
172 struct i40e_spinlock {
173 rte_spinlock_t spinlock;
176 #define i40e_init_spinlock(_sp) i40e_init_spinlock_d(_sp)
177 #define i40e_acquire_spinlock(_sp) i40e_acquire_spinlock_d(_sp)
178 #define i40e_release_spinlock(_sp) i40e_release_spinlock_d(_sp)
179 #define i40e_destroy_spinlock(_sp) i40e_destroy_spinlock_d(_sp)
181 #define I40E_NTOHS(a) rte_be_to_cpu_16(a)
182 #define I40E_NTOHL(a) rte_be_to_cpu_32(a)
183 #define I40E_HTONS(a) rte_cpu_to_be_16(a)
184 #define I40E_HTONL(a) rte_cpu_to_be_32(a)
186 #define i40e_memset(a, b, c, d) memset((a), (b), (c))
187 #define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
189 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
190 #define DELAY(x) rte_delay_us(x)
191 #define i40e_usec_delay(x) rte_delay_us(x)
192 #define i40e_msec_delay(x) rte_delay_us(1000*(x))
193 #define udelay(x) DELAY(x)
194 #define msleep(x) DELAY(1000*(x))
195 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
197 #endif /* _I40E_OSDEP_H_ */