lib/librte_pmd_i40e/i40e/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43
  44 #define UNREFERENCED_XPARAMETER
  45 #define UNREFERENCED_1PARAMETER(_p) (_p);
  46 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  47 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  48 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  49 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  50
  51 /* Vendor ID */
  52 #define I40E_INTEL_VENDOR_ID            0x8086
  53
  54 /* Device IDs */
  55 #define I40E_DEV_ID_SFP_XL710           0x1572
  56 #define I40E_DEV_ID_QEMU                0x1574
  57 #define I40E_DEV_ID_KX_A                0x157F
  58 #define I40E_DEV_ID_KX_B                0x1580
  59 #define I40E_DEV_ID_KX_C                0x1581
  60 #define I40E_DEV_ID_QSFP_A              0x1583
  61 #define I40E_DEV_ID_QSFP_B              0x1584
  62 #define I40E_DEV_ID_QSFP_C              0x1585
  63 #define I40E_DEV_ID_10G_BASE_T          0x1586
  64 #define I40E_DEV_ID_VF                  0x154C
  65 #define I40E_DEV_ID_VF_HV               0x1571
  66
  67 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  68                                          (d) == I40E_DEV_ID_QSFP_B  || \
  69                                          (d) == I40E_DEV_ID_QSFP_C)
  70
  71 #ifndef I40E_MASK
  72 /* I40E_MASK is a macro used on 32 bit registers */
  73 #define I40E_MASK(mask, shift) (mask << shift)
  74 #endif
  75
  76 #define I40E_MAX_PF                     16
  77 #define I40E_MAX_PF_VSI                 64
  78 #define I40E_MAX_PF_QP                  128
  79 #define I40E_MAX_VSI_QP                 16
  80 #define I40E_MAX_VF_VSI                 3
  81 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  82 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  83
  84 /* something less than 1 minute */
  85 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  86
  87 /* Max default timeout in ms, */
  88 #define I40E_MAX_NVM_TIMEOUT            18000
  89
  90 /* Check whether address is multicast. */
  91 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  92
  93 /* Check whether an address is broadcast. */
  94 #define I40E_IS_BROADCAST(address)      \
  95         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  96         (((u8 *)(address))[1] == ((u8)0xff)))
  97
  98 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  99 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
 100
 101 /* forward declaration */
 102 struct i40e_hw;
 103 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
 104
 105 #define I40E_ETH_LENGTH_OF_ADDRESS      6
 106 /* Data type manipulation macros. */
 107 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 108 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 109
 110 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 111 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 112
 113 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 114 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 115
 116 /* Number of Transmit Descriptors must be a multiple of 8. */
 117 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 118 /* Number of Receive Descriptors must be a multiple of 32 if
 119  * the number of descriptors is greater than 32.
 120  */
 121 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 122
 123 #define I40E_DESC_UNUSED(R)     \
 124         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 125         (R)->next_to_clean - (R)->next_to_use - 1)
 126
 127 /* bitfields for Tx queue mapping in QTX_CTL */
 128 #define I40E_QTX_CTL_VF_QUEUE   0x0
 129 #define I40E_QTX_CTL_VM_QUEUE   0x1
 130 #define I40E_QTX_CTL_PF_QUEUE   0x2
 131
 132 /* debug masks - set these bits in hw->debug_mask to control output */
 133 enum i40e_debug_mask {
 134         I40E_DEBUG_INIT                 = 0x00000001,
 135         I40E_DEBUG_RELEASE              = 0x00000002,
 136
 137         I40E_DEBUG_LINK                 = 0x00000010,
 138         I40E_DEBUG_PHY                  = 0x00000020,
 139         I40E_DEBUG_HMC                  = 0x00000040,
 140         I40E_DEBUG_NVM                  = 0x00000080,
 141         I40E_DEBUG_LAN                  = 0x00000100,
 142         I40E_DEBUG_FLOW                 = 0x00000200,
 143         I40E_DEBUG_DCB                  = 0x00000400,
 144         I40E_DEBUG_DIAG                 = 0x00000800,
 145         I40E_DEBUG_FD                   = 0x00001000,
 146
 147         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 148         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 149         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 150         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 151         I40E_DEBUG_AQ                   = 0x0F000000,
 152
 153         I40E_DEBUG_USER                 = 0xF0000000,
 154
 155         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 156 };
 157
 158 /* PCI Bus Info */
 159 #define I40E_PCI_LINK_STATUS            0xB2
 160 #define I40E_PCI_LINK_WIDTH             0x3F0
 161 #define I40E_PCI_LINK_WIDTH_1           0x10
 162 #define I40E_PCI_LINK_WIDTH_2           0x20
 163 #define I40E_PCI_LINK_WIDTH_4           0x40
 164 #define I40E_PCI_LINK_WIDTH_8           0x80
 165 #define I40E_PCI_LINK_SPEED             0xF
 166 #define I40E_PCI_LINK_SPEED_2500        0x1
 167 #define I40E_PCI_LINK_SPEED_5000        0x2
 168 #define I40E_PCI_LINK_SPEED_8000        0x3
 169
 170 /* Memory types */
 171 enum i40e_memset_type {
 172         I40E_NONDMA_MEM = 0,
 173         I40E_DMA_MEM
 174 };
 175
 176 /* Memcpy types */
 177 enum i40e_memcpy_type {
 178         I40E_NONDMA_TO_NONDMA = 0,
 179         I40E_NONDMA_TO_DMA,
 180         I40E_DMA_TO_DMA,
 181         I40E_DMA_TO_NONDMA
 182 };
 183
 184 /* These are structs for managing the hardware information and the operations.
 185  * The structures of function pointers are filled out at init time when we
 186  * know for sure exactly which hardware we're working with.  This gives us the
 187  * flexibility of using the same main driver code but adapting to slightly
 188  * different hardware needs as new parts are developed.  For this architecture,
 189  * the Firmware and AdminQ are intended to insulate the driver from most of the
 190  * future changes, but these structures will also do part of the job.
 191  */
 192 enum i40e_mac_type {
 193         I40E_MAC_UNKNOWN = 0,
 194         I40E_MAC_X710,
 195         I40E_MAC_XL710,
 196         I40E_MAC_VF,
 197         I40E_MAC_GENERIC,
 198 };
 199
 200 enum i40e_media_type {
 201         I40E_MEDIA_TYPE_UNKNOWN = 0,
 202         I40E_MEDIA_TYPE_FIBER,
 203         I40E_MEDIA_TYPE_BASET,
 204         I40E_MEDIA_TYPE_BACKPLANE,
 205         I40E_MEDIA_TYPE_CX4,
 206         I40E_MEDIA_TYPE_DA,
 207         I40E_MEDIA_TYPE_VIRTUAL
 208 };
 209
 210 enum i40e_fc_mode {
 211         I40E_FC_NONE = 0,
 212         I40E_FC_RX_PAUSE,
 213         I40E_FC_TX_PAUSE,
 214         I40E_FC_FULL,
 215         I40E_FC_PFC,
 216         I40E_FC_DEFAULT
 217 };
 218
 219 enum i40e_set_fc_aq_failures {
 220         I40E_SET_FC_AQ_FAIL_NONE = 0,
 221         I40E_SET_FC_AQ_FAIL_GET = 1,
 222         I40E_SET_FC_AQ_FAIL_SET = 2,
 223         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 224         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 225 };
 226
 227 enum i40e_vsi_type {
 228         I40E_VSI_MAIN = 0,
 229         I40E_VSI_VMDQ1,
 230         I40E_VSI_VMDQ2,
 231         I40E_VSI_CTRL,
 232         I40E_VSI_FCOE,
 233         I40E_VSI_MIRROR,
 234         I40E_VSI_SRIOV,
 235         I40E_VSI_FDIR,
 236         I40E_VSI_TYPE_UNKNOWN
 237 };
 238
 239 enum i40e_queue_type {
 240         I40E_QUEUE_TYPE_RX = 0,
 241         I40E_QUEUE_TYPE_TX,
 242         I40E_QUEUE_TYPE_PE_CEQ,
 243         I40E_QUEUE_TYPE_UNKNOWN
 244 };
 245
 246 struct i40e_link_status {
 247         enum i40e_aq_phy_type phy_type;
 248         enum i40e_aq_link_speed link_speed;
 249         u8 link_info;
 250         u8 an_info;
 251         u8 ext_info;
 252         u8 loopback;
 253         bool an_enabled;
 254         /* is Link Status Event notification to SW enabled */
 255         bool lse_enable;
 256         u16 max_frame_size;
 257         bool crc_enable;
 258         u8 pacing;
 259 };
 260
 261 struct i40e_phy_info {
 262         struct i40e_link_status link_info;
 263         struct i40e_link_status link_info_old;
 264         u32 autoneg_advertised;
 265         u32 phy_id;
 266         u32 module_type;
 267         bool get_link_info;
 268         enum i40e_media_type media_type;
 269 };
 270
 271 #define I40E_HW_CAP_MAX_GPIO                    30
 272 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 273 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 274
 275 /* Capabilities of a PF or a VF or the whole device */
 276 struct i40e_hw_capabilities {
 277         u32  switch_mode;
 278 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 279 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 280 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 281
 282         u32  management_mode;
 283         u32  npar_enable;
 284         u32  os2bmc;
 285         u32  valid_functions;
 286         bool sr_iov_1_1;
 287         bool vmdq;
 288         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 289         bool evb_802_1_qbh; /* Bridge Port Extension */
 290         bool dcb;
 291         bool fcoe;
 292         bool mfp_mode_1;
 293         bool mgmt_cem;
 294         bool ieee_1588;
 295         bool iwarp;
 296         bool fd;
 297         u32 fd_filters_guaranteed;
 298         u32 fd_filters_best_effort;
 299         bool rss;
 300         u32 rss_table_size;
 301         u32 rss_table_entry_width;
 302         bool led[I40E_HW_CAP_MAX_GPIO];
 303         bool sdp[I40E_HW_CAP_MAX_GPIO];
 304         u32 nvm_image_type;
 305         u32 num_flow_director_filters;
 306         u32 num_vfs;
 307         u32 vf_base_id;
 308         u32 num_vsis;
 309         u32 num_rx_qp;
 310         u32 num_tx_qp;
 311         u32 base_queue;
 312         u32 num_msix_vectors;
 313         u32 num_msix_vectors_vf;
 314         u32 led_pin_num;
 315         u32 sdp_pin_num;
 316         u32 mdio_port_num;
 317         u32 mdio_port_mode;
 318         u8 rx_buf_chain_len;
 319         u32 enabled_tcmap;
 320         u32 maxtc;
 321 };
 322
 323 struct i40e_mac_info {
 324         enum i40e_mac_type type;
 325         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 326         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 327         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 328         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 329         u16 max_fcoeq;
 330 };
 331
 332 enum i40e_aq_resources_ids {
 333         I40E_NVM_RESOURCE_ID = 1
 334 };
 335
 336 enum i40e_aq_resource_access_type {
 337         I40E_RESOURCE_READ = 1,
 338         I40E_RESOURCE_WRITE
 339 };
 340
 341 struct i40e_nvm_info {
 342         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 343         u64 hw_semaphore_wait;    /* - || - */
 344         u32 timeout;              /* [ms] */
 345         u16 sr_size;              /* Shadow RAM size in words */
 346         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 347         u16 version;              /* NVM package version */
 348         u32 eetrack;              /* NVM data version */
 349 };
 350
 351 /* definitions used in NVM update support */
 352
 353 enum i40e_nvmupd_cmd {
 354         I40E_NVMUPD_INVALID,
 355         I40E_NVMUPD_READ_CON,
 356         I40E_NVMUPD_READ_SNT,
 357         I40E_NVMUPD_READ_LCB,
 358         I40E_NVMUPD_READ_SA,
 359         I40E_NVMUPD_WRITE_ERA,
 360         I40E_NVMUPD_WRITE_CON,
 361         I40E_NVMUPD_WRITE_SNT,
 362         I40E_NVMUPD_WRITE_LCB,
 363         I40E_NVMUPD_WRITE_SA,
 364         I40E_NVMUPD_CSUM_CON,
 365         I40E_NVMUPD_CSUM_SA,
 366         I40E_NVMUPD_CSUM_LCB,
 367 };
 368
 369 enum i40e_nvmupd_state {
 370         I40E_NVMUPD_STATE_INIT,
 371         I40E_NVMUPD_STATE_READING,
 372         I40E_NVMUPD_STATE_WRITING
 373 };
 374
 375 /* nvm_access definition and its masks/shifts need to be accessible to
 376  * application, core driver, and shared code.  Where is the right file?
 377  */
 378 #define I40E_NVM_READ   0xB
 379 #define I40E_NVM_WRITE  0xC
 380
 381 #define I40E_NVM_MOD_PNT_MASK 0xFF
 382
 383 #define I40E_NVM_TRANS_SHIFT    8
 384 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 385 #define I40E_NVM_CON            0x0
 386 #define I40E_NVM_SNT            0x1
 387 #define I40E_NVM_LCB            0x2
 388 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 389 #define I40E_NVM_ERA            0x4
 390 #define I40E_NVM_CSUM           0x8
 391
 392 #define I40E_NVM_ADAPT_SHIFT    16
 393 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 394
 395 #define I40E_NVMUPD_MAX_DATA    4096
 396 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 397
 398 struct i40e_nvm_access {
 399         u32 command;
 400         u32 config;
 401         u32 offset;     /* in bytes */
 402         u32 data_size;  /* in bytes */
 403         u8 data[1];
 404 };
 405
 406 /* PCI bus types */
 407 enum i40e_bus_type {
 408         i40e_bus_type_unknown = 0,
 409         i40e_bus_type_pci,
 410         i40e_bus_type_pcix,
 411         i40e_bus_type_pci_express,
 412         i40e_bus_type_reserved
 413 };
 414
 415 /* PCI bus speeds */
 416 enum i40e_bus_speed {
 417         i40e_bus_speed_unknown  = 0,
 418         i40e_bus_speed_33       = 33,
 419         i40e_bus_speed_66       = 66,
 420         i40e_bus_speed_100      = 100,
 421         i40e_bus_speed_120      = 120,
 422         i40e_bus_speed_133      = 133,
 423         i40e_bus_speed_2500     = 2500,
 424         i40e_bus_speed_5000     = 5000,
 425         i40e_bus_speed_8000     = 8000,
 426         i40e_bus_speed_reserved
 427 };
 428
 429 /* PCI bus widths */
 430 enum i40e_bus_width {
 431         i40e_bus_width_unknown  = 0,
 432         i40e_bus_width_pcie_x1  = 1,
 433         i40e_bus_width_pcie_x2  = 2,
 434         i40e_bus_width_pcie_x4  = 4,
 435         i40e_bus_width_pcie_x8  = 8,
 436         i40e_bus_width_32       = 32,
 437         i40e_bus_width_64       = 64,
 438         i40e_bus_width_reserved
 439 };
 440
 441 /* Bus parameters */
 442 struct i40e_bus_info {
 443         enum i40e_bus_speed speed;
 444         enum i40e_bus_width width;
 445         enum i40e_bus_type type;
 446
 447         u16 func;
 448         u16 device;
 449         u16 lan_id;
 450 };
 451
 452 /* Flow control (FC) parameters */
 453 struct i40e_fc_info {
 454         enum i40e_fc_mode current_mode; /* FC mode in effect */
 455         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 456 };
 457
 458 #define I40E_MAX_TRAFFIC_CLASS          8
 459 #define I40E_MAX_USER_PRIORITY          8
 460 #define I40E_DCBX_MAX_APPS              32
 461 #define I40E_LLDPDU_SIZE                1500
 462
 463 /* IEEE 802.1Qaz ETS Configuration data */
 464 struct i40e_ieee_ets_config {
 465         u8 willing;
 466         u8 cbs;
 467         u8 maxtcs;
 468         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 469         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 470         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 471 };
 472
 473 /* IEEE 802.1Qaz ETS Recommendation data */
 474 struct i40e_ieee_ets_recommend {
 475         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 476         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 477         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 478 };
 479
 480 /* IEEE 802.1Qaz PFC Configuration data */
 481 struct i40e_ieee_pfc_config {
 482         u8 willing;
 483         u8 mbc;
 484         u8 pfccap;
 485         u8 pfcenable;
 486 };
 487
 488 /* IEEE 802.1Qaz Application Priority data */
 489 struct i40e_ieee_app_priority_table {
 490         u8  priority;
 491         u8  selector;
 492         u16 protocolid;
 493 };
 494
 495 struct i40e_dcbx_config {
 496         u32 numapps;
 497         struct i40e_ieee_ets_config etscfg;
 498         struct i40e_ieee_ets_recommend etsrec;
 499         struct i40e_ieee_pfc_config pfc;
 500         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 501 };
 502
 503 /* Port hardware description */
 504 struct i40e_hw {
 505         u8 *hw_addr;
 506         void *back;
 507
 508         /* function pointer structs */
 509         struct i40e_phy_info phy;
 510         struct i40e_mac_info mac;
 511         struct i40e_bus_info bus;
 512         struct i40e_nvm_info nvm;
 513         struct i40e_fc_info fc;
 514
 515         /* pci info */
 516         u16 device_id;
 517         u16 vendor_id;
 518         u16 subsystem_device_id;
 519         u16 subsystem_vendor_id;
 520         u8 revision_id;
 521         u8 port;
 522         bool adapter_stopped;
 523
 524         /* capabilities for entire device and PCI func */
 525         struct i40e_hw_capabilities dev_caps;
 526         struct i40e_hw_capabilities func_caps;
 527
 528         /* Flow Director shared filter space */
 529         u16 fdir_shared_filter_count;
 530
 531         /* device profile info */
 532         u8  pf_id;
 533         u16 main_vsi_seid;
 534
 535         /* Closest numa node to the device */
 536         u16 numa_node;
 537
 538         /* Admin Queue info */
 539         struct i40e_adminq_info aq;
 540
 541         /* state of nvm update process */
 542         enum i40e_nvmupd_state nvmupd_state;
 543
 544         /* HMC info */
 545         struct i40e_hmc_info hmc; /* HMC info struct */
 546
 547         /* LLDP/DCBX Status */
 548         u16 dcbx_status;
 549
 550         /* DCBX info */
 551         struct i40e_dcbx_config local_dcbx_config;
 552         struct i40e_dcbx_config remote_dcbx_config;
 553
 554         /* debug mask */
 555         u32 debug_mask;
 556 };
 557
 558 struct i40e_driver_version {
 559         u8 major_version;
 560         u8 minor_version;
 561         u8 build_version;
 562         u8 subbuild_version;
 563         u8 driver_string[32];
 564 };
 565
 566 /* RX Descriptors */
 567 union i40e_16byte_rx_desc {
 568         struct {
 569                 __le64 pkt_addr; /* Packet buffer address */
 570                 __le64 hdr_addr; /* Header buffer address */
 571         } read;
 572         struct {
 573                 struct {
 574                         struct {
 575                                 union {
 576                                         __le16 mirroring_status;
 577                                         __le16 fcoe_ctx_id;
 578                                 } mirr_fcoe;
 579                                 __le16 l2tag1;
 580                         } lo_dword;
 581                         union {
 582                                 __le32 rss; /* RSS Hash */
 583                                 __le32 fd_id; /* Flow director filter id */
 584                                 __le32 fcoe_param; /* FCoE DDP Context id */
 585                         } hi_dword;
 586                 } qword0;
 587                 struct {
 588                         /* ext status/error/pktype/length */
 589                         __le64 status_error_len;
 590                 } qword1;
 591         } wb;  /* writeback */
 592 };
 593
 594 union i40e_32byte_rx_desc {
 595         struct {
 596                 __le64  pkt_addr; /* Packet buffer address */
 597                 __le64  hdr_addr; /* Header buffer address */
 598                         /* bit 0 of hdr_buffer_addr is DD bit */
 599                 __le64  rsvd1;
 600                 __le64  rsvd2;
 601         } read;
 602         struct {
 603                 struct {
 604                         struct {
 605                                 union {
 606                                         __le16 mirroring_status;
 607                                         __le16 fcoe_ctx_id;
 608                                 } mirr_fcoe;
 609                                 __le16 l2tag1;
 610                         } lo_dword;
 611                         union {
 612                                 __le32 rss; /* RSS Hash */
 613                                 __le32 fcoe_param; /* FCoE DDP Context id */
 614                                 /* Flow director filter id in case of
 615                                  * Programming status desc WB
 616                                  */
 617                                 __le32 fd_id;
 618                         } hi_dword;
 619                 } qword0;
 620                 struct {
 621                         /* status/error/pktype/length */
 622                         __le64 status_error_len;
 623                 } qword1;
 624                 struct {
 625                         __le16 ext_status; /* extended status */
 626                         __le16 rsvd;
 627                         __le16 l2tag2_1;
 628                         __le16 l2tag2_2;
 629                 } qword2;
 630                 struct {
 631                         union {
 632                                 __le32 flex_bytes_lo;
 633                                 __le32 pe_status;
 634                         } lo_dword;
 635                         union {
 636                                 __le32 flex_bytes_hi;
 637                                 __le32 fd_id;
 638                         } hi_dword;
 639                 } qword3;
 640         } wb;  /* writeback */
 641 };
 642
 643 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 644 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 645                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 646 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 647 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 648                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 649
 650 enum i40e_rx_desc_status_bits {
 651         /* Note: These are predefined bit offsets */
 652         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 653         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 654         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 655         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 656         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 657         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 658         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 659         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 660         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 661         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 662         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 663         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 664         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 665         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 666         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 667         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 668 };
 669
 670 #define I40E_RXD_QW1_STATUS_SHIFT       0
 671 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 672                                          I40E_RXD_QW1_STATUS_SHIFT)
 673
 674 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 675 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 676                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 677
 678 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 679 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 680                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 681
 682 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 683 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 684                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 685
 686 enum i40e_rx_desc_fltstat_values {
 687         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 688         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 689         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 690         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 691 };
 692
 693 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 694 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 695 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 696 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 697
 698 #define I40E_RXD_QW1_ERROR_SHIFT        19
 699 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 700
 701 enum i40e_rx_desc_error_bits {
 702         /* Note: These are predefined bit offsets */
 703         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 704         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 705         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 706         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 707         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 708         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 709         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 710         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 711         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 712 };
 713
 714 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 715         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 716         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 717         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 718         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 719         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 720 };
 721
 722 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 723 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 724
 725 /* Packet type non-ip values */
 726 enum i40e_rx_l2_ptype {
 727         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 728         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 729         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 730         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 731         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 732         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 733         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 734         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 735         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 736         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 737         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 738         I40E_RX_PTYPE_L2_ARP                            = 11,
 739         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 740         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 741         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 742         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 743         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 744         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 745         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 746         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 747         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 748         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 749         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 750         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 751         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 752         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 753 };
 754
 755 struct i40e_rx_ptype_decoded {
 756         u32 ptype:8;
 757         u32 known:1;
 758         u32 outer_ip:1;
 759         u32 outer_ip_ver:1;
 760         u32 outer_frag:1;
 761         u32 tunnel_type:3;
 762         u32 tunnel_end_prot:2;
 763         u32 tunnel_end_frag:1;
 764         u32 inner_prot:4;
 765         u32 payload_layer:3;
 766 };
 767
 768 enum i40e_rx_ptype_outer_ip {
 769         I40E_RX_PTYPE_OUTER_L2  = 0,
 770         I40E_RX_PTYPE_OUTER_IP  = 1
 771 };
 772
 773 enum i40e_rx_ptype_outer_ip_ver {
 774         I40E_RX_PTYPE_OUTER_NONE        = 0,
 775         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 776         I40E_RX_PTYPE_OUTER_IPV6        = 1
 777 };
 778
 779 enum i40e_rx_ptype_outer_fragmented {
 780         I40E_RX_PTYPE_NOT_FRAG  = 0,
 781         I40E_RX_PTYPE_FRAG      = 1
 782 };
 783
 784 enum i40e_rx_ptype_tunnel_type {
 785         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 786         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 787         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 788         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 789         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 790 };
 791
 792 enum i40e_rx_ptype_tunnel_end_prot {
 793         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 794         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 795         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 796 };
 797
 798 enum i40e_rx_ptype_inner_prot {
 799         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 800         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 801         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 802         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 803         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 804         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 805 };
 806
 807 enum i40e_rx_ptype_payload_layer {
 808         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 809         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 810         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 811         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 812 };
 813
 814 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 815 #define I40E_RX_PTYPE_SHIFT             56
 816
 817 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 818 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 819                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 820
 821 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 822 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 823                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 824
 825 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 826 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 827                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 828
 829 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 830 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 831
 832 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 833 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 834                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 835
 836 enum i40e_rx_desc_ext_status_bits {
 837         /* Note: These are predefined bit offsets */
 838         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 839         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 840         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 841         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 842         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 843         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 844         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 845 };
 846
 847 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 848 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 849
 850 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 851 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 852
 853 enum i40e_rx_desc_pe_status_bits {
 854         /* Note: These are predefined bit offsets */
 855         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 856         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 857         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 858         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 859         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 860         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 861         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 862         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 863         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 864 };
 865
 866 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 867 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 868
 869 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 870 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 871                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 872
 873 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 874 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 875                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 876
 877 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 878 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 879                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 880
 881 enum i40e_rx_prog_status_desc_status_bits {
 882         /* Note: These are predefined bit offsets */
 883         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 884         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 885 };
 886
 887 enum i40e_rx_prog_status_desc_prog_id_masks {
 888         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 889         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 890         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 891 };
 892
 893 enum i40e_rx_prog_status_desc_error_bits {
 894         /* Note: These are predefined bit offsets */
 895         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 896         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 897         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 898         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 899 };
 900
 901 #define I40E_TWO_BIT_MASK       0x3
 902 #define I40E_THREE_BIT_MASK     0x7
 903 #define I40E_FOUR_BIT_MASK      0xF
 904 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 905
 906 /* TX Descriptor */
 907 struct i40e_tx_desc {
 908         __le64 buffer_addr; /* Address of descriptor's data buf */
 909         __le64 cmd_type_offset_bsz;
 910 };
 911
 912 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 913 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 914
 915 enum i40e_tx_desc_dtype_value {
 916         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 917         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 918         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 919         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 920         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 921         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 922         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 923         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 924         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 925         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 926 };
 927
 928 #define I40E_TXD_QW1_CMD_SHIFT  4
 929 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 930
 931 enum i40e_tx_desc_cmd_bits {
 932         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 933         I40E_TX_DESC_CMD_RS                     = 0x0002,
 934         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 935         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 936         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 937         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 938         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 939         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 940         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 941         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 942         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 943         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 944         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 945         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 946         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 947         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 948         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 949         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 950 };
 951
 952 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 953 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 954                                          I40E_TXD_QW1_OFFSET_SHIFT)
 955
 956 enum i40e_tx_desc_length_fields {
 957         /* Note: These are predefined bit offsets */
 958         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 959         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 960         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 961 };
 962
 963 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 964 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 965 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 966 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 967
 968 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 969 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 970                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 971
 972 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 973 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 974
 975 /* Context descriptors */
 976 struct i40e_tx_context_desc {
 977         __le32 tunneling_params;
 978         __le16 l2tag2;
 979         __le16 rsvd;
 980         __le64 type_cmd_tso_mss;
 981 };
 982
 983 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 984 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 985
 986 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 987 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 988
 989 enum i40e_tx_ctx_desc_cmd_bits {
 990         I40E_TX_CTX_DESC_TSO            = 0x01,
 991         I40E_TX_CTX_DESC_TSYN           = 0x02,
 992         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 993         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 994         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 995         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 996         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 997         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 998         I40E_TX_CTX_DESC_SWPE           = 0x40
 999 };
1000
1001 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1002 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1003                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1004
1005 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1006 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1007                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1008
1009 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1010 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1011
1012 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1013 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1014                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1015
1016 enum i40e_tx_ctx_desc_eipt_offload {
1017         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1018         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1019         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1020         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1021 };
1022
1023 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1024 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1025                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1026
1027 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1028 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1029
1030 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1031 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1032
1033 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1034 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1035                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1036
1037 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1038
1039 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1040 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1041                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1042
1043 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1044 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1045                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1046
1047 struct i40e_nop_desc {
1048         __le64 rsvd;
1049         __le64 dtype_cmd;
1050 };
1051
1052 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1053 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1054
1055 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1056 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1057
1058 enum i40e_tx_nop_desc_cmd_bits {
1059         /* Note: These are predefined bit offsets */
1060         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1061         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1062         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1063 };
1064
1065 struct i40e_filter_program_desc {
1066         __le32 qindex_flex_ptype_vsi;
1067         __le32 rsvd;
1068         __le32 dtype_cmd_cntindex;
1069         __le32 fd_id;
1070 };
1071 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1072 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1073                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1074 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1075 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1076                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1077 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1078 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1079                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1080
1081 /* Packet Classifier Types for filters */
1082 enum i40e_filter_pctype {
1083         /* Note: Values 0-30 are reserved for future use */
1084         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1085         /* Note: Value 32 is reserved for future use */
1086         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1087         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1088         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1089         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1090         /* Note: Values 37-40 are reserved for future use */
1091         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1092         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1093         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1094         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1095         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1096         /* Note: Value 47 is reserved for future use */
1097         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1098         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1099         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1100         /* Note: Values 51-62 are reserved for future use */
1101         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1102 };
1103
1104 enum i40e_filter_program_desc_dest {
1105         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1106         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1107         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1108 };
1109
1110 enum i40e_filter_program_desc_fd_status {
1111         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1112         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1113         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1114         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1115 };
1116
1117 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1118 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1119                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1120
1121 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1122 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1123
1124 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1125 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1126                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1127
1128 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1129 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1130
1131 enum i40e_filter_program_desc_pcmd {
1132         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1133         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1134 };
1135
1136 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1137 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1138
1139 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1140 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1141                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1142
1143 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1144                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1145 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1146                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1147
1148 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1149 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1150                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1151
1152 enum i40e_filter_type {
1153         I40E_FLOW_DIRECTOR_FLTR = 0,
1154         I40E_PE_QUAD_HASH_FLTR = 1,
1155         I40E_ETHERTYPE_FLTR,
1156         I40E_FCOE_CTX_FLTR,
1157         I40E_MAC_VLAN_FLTR,
1158         I40E_HASH_FLTR
1159 };
1160
1161 struct i40e_vsi_context {
1162         u16 seid;
1163         u16 uplink_seid;
1164         u16 vsi_number;
1165         u16 vsis_allocated;
1166         u16 vsis_unallocated;
1167         u16 flags;
1168         u8 pf_num;
1169         u8 vf_num;
1170         u8 connection_type;
1171         struct i40e_aqc_vsi_properties_data info;
1172 };
1173
1174 struct i40e_veb_context {
1175         u16 seid;
1176         u16 uplink_seid;
1177         u16 veb_number;
1178         u16 vebs_allocated;
1179         u16 vebs_unallocated;
1180         u16 flags;
1181         struct i40e_aqc_get_veb_parameters_completion info;
1182 };
1183
1184 /* Statistics collected by each port, VSI, VEB, and S-channel */
1185 struct i40e_eth_stats {
1186         u64 rx_bytes;                   /* gorc */
1187         u64 rx_unicast;                 /* uprc */
1188         u64 rx_multicast;               /* mprc */
1189         u64 rx_broadcast;               /* bprc */
1190         u64 rx_discards;                /* rdpc */
1191         u64 rx_unknown_protocol;        /* rupp */
1192         u64 tx_bytes;                   /* gotc */
1193         u64 tx_unicast;                 /* uptc */
1194         u64 tx_multicast;               /* mptc */
1195         u64 tx_broadcast;               /* bptc */
1196         u64 tx_discards;                /* tdpc */
1197         u64 tx_errors;                  /* tepc */
1198 };
1199
1200 /* Statistics collected by the MAC */
1201 struct i40e_hw_port_stats {
1202         /* eth stats collected by the port */
1203         struct i40e_eth_stats eth;
1204
1205         /* additional port specific stats */
1206         u64 tx_dropped_link_down;       /* tdold */
1207         u64 crc_errors;                 /* crcerrs */
1208         u64 illegal_bytes;              /* illerrc */
1209         u64 error_bytes;                /* errbc */
1210         u64 mac_local_faults;           /* mlfc */
1211         u64 mac_remote_faults;          /* mrfc */
1212         u64 rx_length_errors;           /* rlec */
1213         u64 link_xon_rx;                /* lxonrxc */
1214         u64 link_xoff_rx;               /* lxoffrxc */
1215         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1216         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1217         u64 link_xon_tx;                /* lxontxc */
1218         u64 link_xoff_tx;               /* lxofftxc */
1219         u64 priority_xon_tx[8];         /* pxontxc[8] */
1220         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1221         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1222         u64 rx_size_64;                 /* prc64 */
1223         u64 rx_size_127;                /* prc127 */
1224         u64 rx_size_255;                /* prc255 */
1225         u64 rx_size_511;                /* prc511 */
1226         u64 rx_size_1023;               /* prc1023 */
1227         u64 rx_size_1522;               /* prc1522 */
1228         u64 rx_size_big;                /* prc9522 */
1229         u64 rx_undersize;               /* ruc */
1230         u64 rx_fragments;               /* rfc */
1231         u64 rx_oversize;                /* roc */
1232         u64 rx_jabber;                  /* rjc */
1233         u64 tx_size_64;                 /* ptc64 */
1234         u64 tx_size_127;                /* ptc127 */
1235         u64 tx_size_255;                /* ptc255 */
1236         u64 tx_size_511;                /* ptc511 */
1237         u64 tx_size_1023;               /* ptc1023 */
1238         u64 tx_size_1522;               /* ptc1522 */
1239         u64 tx_size_big;                /* ptc9522 */
1240         u64 mac_short_packet_dropped;   /* mspdc */
1241         u64 checksum_error;             /* xec */
1242         /* flow director stats */
1243         u64 fd_atr_match;
1244         u64 fd_sb_match;
1245         /* EEE LPI */
1246         u32 tx_lpi_status;
1247         u32 rx_lpi_status;
1248         u64 tx_lpi_count;               /* etlpic */
1249         u64 rx_lpi_count;               /* erlpic */
1250 };
1251
1252 /* Checksum and Shadow RAM pointers */
1253 #define I40E_SR_NVM_CONTROL_WORD                0x00
1254 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1255 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1256 #define I40E_SR_OPTION_ROM_PTR                  0x05
1257 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1258 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1259 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1260 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1261 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1262 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1263 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1264 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1265 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1266 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1267 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1268 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1269 #define I40E_SR_NVM_IMAGE_VERSION               0x18
1270 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1271 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1272 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1273 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1274 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1275 #define I40E_SR_VPD_PTR                         0x2F
1276 #define I40E_SR_PXE_SETUP_PTR                   0x30
1277 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1278 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1279 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1280 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1281 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1282 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1283 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1284 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1285 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1286 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1287 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1288 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1289 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1290
1291 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1292 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1293 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1294 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1295 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1296
1297 /* Shadow RAM related */
1298 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1299 #define I40E_SR_BUF_ALIGNMENT           4096
1300 #define I40E_SR_WORDS_IN_1KB            512
1301 /* Checksum should be calculated such that after adding all the words,
1302  * including the checksum word itself, the sum should be 0xBABA.
1303  */
1304 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1305
1306 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1307
1308 enum i40e_switch_element_types {
1309         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1310         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1311         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1312         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1313         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1314         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1315         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1316         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1317         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1318 };
1319
1320 /* Supported EtherType filters */
1321 enum i40e_ether_type_index {
1322         I40E_ETHER_TYPE_1588            = 0,
1323         I40E_ETHER_TYPE_FIP             = 1,
1324         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1325         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1326         I40E_ETHER_TYPE_LLDP            = 4,
1327         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1328         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1329         I40E_ETHER_TYPE_QCN_CNM         = 7,
1330         I40E_ETHER_TYPE_8021X           = 8,
1331         I40E_ETHER_TYPE_ARP             = 9,
1332         I40E_ETHER_TYPE_RSV1            = 10,
1333         I40E_ETHER_TYPE_RSV2            = 11,
1334 };
1335
1336 /* Filter context base size is 1K */
1337 #define I40E_HASH_FILTER_BASE_SIZE      1024
1338 /* Supported Hash filter values */
1339 enum i40e_hash_filter_size {
1340         I40E_HASH_FILTER_SIZE_1K        = 0,
1341         I40E_HASH_FILTER_SIZE_2K        = 1,
1342         I40E_HASH_FILTER_SIZE_4K        = 2,
1343         I40E_HASH_FILTER_SIZE_8K        = 3,
1344         I40E_HASH_FILTER_SIZE_16K       = 4,
1345         I40E_HASH_FILTER_SIZE_32K       = 5,
1346         I40E_HASH_FILTER_SIZE_64K       = 6,
1347         I40E_HASH_FILTER_SIZE_128K      = 7,
1348         I40E_HASH_FILTER_SIZE_256K      = 8,
1349         I40E_HASH_FILTER_SIZE_512K      = 9,
1350         I40E_HASH_FILTER_SIZE_1M        = 10,
1351 };
1352
1353 /* DMA context base size is 0.5K */
1354 #define I40E_DMA_CNTX_BASE_SIZE         512
1355 /* Supported DMA context values */
1356 enum i40e_dma_cntx_size {
1357         I40E_DMA_CNTX_SIZE_512          = 0,
1358         I40E_DMA_CNTX_SIZE_1K           = 1,
1359         I40E_DMA_CNTX_SIZE_2K           = 2,
1360         I40E_DMA_CNTX_SIZE_4K           = 3,
1361         I40E_DMA_CNTX_SIZE_8K           = 4,
1362         I40E_DMA_CNTX_SIZE_16K          = 5,
1363         I40E_DMA_CNTX_SIZE_32K          = 6,
1364         I40E_DMA_CNTX_SIZE_64K          = 7,
1365         I40E_DMA_CNTX_SIZE_128K         = 8,
1366         I40E_DMA_CNTX_SIZE_256K         = 9,
1367 };
1368
1369 /* Supported Hash look up table (LUT) sizes */
1370 enum i40e_hash_lut_size {
1371         I40E_HASH_LUT_SIZE_128          = 0,
1372         I40E_HASH_LUT_SIZE_512          = 1,
1373 };
1374
1375 /* Structure to hold a per PF filter control settings */
1376 struct i40e_filter_control_settings {
1377         /* number of PE Quad Hash filter buckets */
1378         enum i40e_hash_filter_size pe_filt_num;
1379         /* number of PE Quad Hash contexts */
1380         enum i40e_dma_cntx_size pe_cntx_num;
1381         /* number of FCoE filter buckets */
1382         enum i40e_hash_filter_size fcoe_filt_num;
1383         /* number of FCoE DDP contexts */
1384         enum i40e_dma_cntx_size fcoe_cntx_num;
1385         /* size of the Hash LUT */
1386         enum i40e_hash_lut_size hash_lut_size;
1387         /* enable FDIR filters for PF and its VFs */
1388         bool enable_fdir;
1389         /* enable Ethertype filters for PF and its VFs */
1390         bool enable_ethtype;
1391         /* enable MAC/VLAN filters for PF and its VFs */
1392         bool enable_macvlan;
1393 };
1394
1395 /* Structure to hold device level control filter counts */
1396 struct i40e_control_filter_stats {
1397         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1398         u16 etype_used;       /* Used perfect EtherType filters */
1399         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1400         u16 etype_free;       /* Un-used perfect EtherType filters */
1401 };
1402
1403 enum i40e_reset_type {
1404         I40E_RESET_POR          = 0,
1405         I40E_RESET_CORER        = 1,
1406         I40E_RESET_GLOBR        = 2,
1407         I40E_RESET_EMPR         = 3,
1408 };
1409
1410 /* Offsets into Alternate Ram */
1411 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1412 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1413 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1414 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1415 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1416 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1417
1418 /* Alternate Ram Bandwidth Masks */
1419 #define I40E_ALT_BW_VALUE_MASK          0xFF
1420 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1421 #define I40E_ALT_BW_VALID_MASK          0x80000000
1422
1423 /* RSS Hash Table Size */
1424 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1425 #endif /* _I40E_TYPE_H_ */