lib/librte_pmd_i40e/i40e/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43
  44 #define UNREFERENCED_XPARAMETER
  45 #define UNREFERENCED_1PARAMETER(_p) (_p);
  46 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  47 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  48 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  49 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  50
  51 /* Vendor ID */
  52 #define I40E_INTEL_VENDOR_ID            0x8086
  53
  54 /* Device IDs */
  55 #define I40E_DEV_ID_SFP_XL710           0x1572
  56 #define I40E_DEV_ID_QEMU                0x1574
  57 #define I40E_DEV_ID_KX_A                0x157F
  58 #define I40E_DEV_ID_KX_B                0x1580
  59 #define I40E_DEV_ID_KX_C                0x1581
  60 #define I40E_DEV_ID_QSFP_A              0x1583
  61 #define I40E_DEV_ID_QSFP_B              0x1584
  62 #define I40E_DEV_ID_QSFP_C              0x1585
  63 #define I40E_DEV_ID_10G_BASE_T          0x1586
  64 #define I40E_DEV_ID_VF                  0x154C
  65 #define I40E_DEV_ID_VF_HV               0x1571
  66
  67 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  68                                          (d) == I40E_DEV_ID_QSFP_B  || \
  69                                          (d) == I40E_DEV_ID_QSFP_C)
  70
  71 #ifndef I40E_MASK
  72 /* I40E_MASK is a macro used on 32 bit registers */
  73 #define I40E_MASK(mask, shift) (mask << shift)
  74 #endif
  75
  76 #define I40E_MAX_PF                     16
  77 #define I40E_MAX_PF_VSI                 64
  78 #define I40E_MAX_PF_QP                  128
  79 #define I40E_MAX_VSI_QP                 16
  80 #define I40E_MAX_VF_VSI                 3
  81 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  82 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  83
  84 /* something less than 1 minute */
  85 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  86
  87 /* Max default timeout in ms, */
  88 #define I40E_MAX_NVM_TIMEOUT            18000
  89
  90 /* Check whether address is multicast. */
  91 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  92
  93 /* Check whether an address is broadcast. */
  94 #define I40E_IS_BROADCAST(address)      \
  95         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  96         (((u8 *)(address))[1] == ((u8)0xff)))
  97
  98 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  99 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
 100
 101 /* forward declaration */
 102 struct i40e_hw;
 103 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
 104
 105 #define I40E_ETH_LENGTH_OF_ADDRESS      6
 106 /* Data type manipulation macros. */
 107 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 108 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 109
 110 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 111 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 112
 113 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 114 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 115
 116 /* Number of Transmit Descriptors must be a multiple of 8. */
 117 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 118 /* Number of Receive Descriptors must be a multiple of 32 if
 119  * the number of descriptors is greater than 32.
 120  */
 121 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 122
 123 #define I40E_DESC_UNUSED(R)     \
 124         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 125         (R)->next_to_clean - (R)->next_to_use - 1)
 126
 127 /* bitfields for Tx queue mapping in QTX_CTL */
 128 #define I40E_QTX_CTL_VF_QUEUE   0x0
 129 #define I40E_QTX_CTL_VM_QUEUE   0x1
 130 #define I40E_QTX_CTL_PF_QUEUE   0x2
 131
 132 /* debug masks - set these bits in hw->debug_mask to control output */
 133 enum i40e_debug_mask {
 134         I40E_DEBUG_INIT                 = 0x00000001,
 135         I40E_DEBUG_RELEASE              = 0x00000002,
 136
 137         I40E_DEBUG_LINK                 = 0x00000010,
 138         I40E_DEBUG_PHY                  = 0x00000020,
 139         I40E_DEBUG_HMC                  = 0x00000040,
 140         I40E_DEBUG_NVM                  = 0x00000080,
 141         I40E_DEBUG_LAN                  = 0x00000100,
 142         I40E_DEBUG_FLOW                 = 0x00000200,
 143         I40E_DEBUG_DCB                  = 0x00000400,
 144         I40E_DEBUG_DIAG                 = 0x00000800,
 145         I40E_DEBUG_FD                   = 0x00001000,
 146
 147         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 148         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 149         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 150         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 151         I40E_DEBUG_AQ                   = 0x0F000000,
 152
 153         I40E_DEBUG_USER                 = 0xF0000000,
 154
 155         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 156 };
 157
 158 /* PCI Bus Info */
 159 #define I40E_PCI_LINK_STATUS            0xB2
 160 #define I40E_PCI_LINK_WIDTH             0x3F0
 161 #define I40E_PCI_LINK_WIDTH_1           0x10
 162 #define I40E_PCI_LINK_WIDTH_2           0x20
 163 #define I40E_PCI_LINK_WIDTH_4           0x40
 164 #define I40E_PCI_LINK_WIDTH_8           0x80
 165 #define I40E_PCI_LINK_SPEED             0xF
 166 #define I40E_PCI_LINK_SPEED_2500        0x1
 167 #define I40E_PCI_LINK_SPEED_5000        0x2
 168 #define I40E_PCI_LINK_SPEED_8000        0x3
 169
 170 /* Memory types */
 171 enum i40e_memset_type {
 172         I40E_NONDMA_MEM = 0,
 173         I40E_DMA_MEM
 174 };
 175
 176 /* Memcpy types */
 177 enum i40e_memcpy_type {
 178         I40E_NONDMA_TO_NONDMA = 0,
 179         I40E_NONDMA_TO_DMA,
 180         I40E_DMA_TO_DMA,
 181         I40E_DMA_TO_NONDMA
 182 };
 183
 184 /* These are structs for managing the hardware information and the operations.
 185  * The structures of function pointers are filled out at init time when we
 186  * know for sure exactly which hardware we're working with.  This gives us the
 187  * flexibility of using the same main driver code but adapting to slightly
 188  * different hardware needs as new parts are developed.  For this architecture,
 189  * the Firmware and AdminQ are intended to insulate the driver from most of the
 190  * future changes, but these structures will also do part of the job.
 191  */
 192 enum i40e_mac_type {
 193         I40E_MAC_UNKNOWN = 0,
 194         I40E_MAC_X710,
 195         I40E_MAC_XL710,
 196         I40E_MAC_VF,
 197         I40E_MAC_GENERIC,
 198 };
 199
 200 enum i40e_media_type {
 201         I40E_MEDIA_TYPE_UNKNOWN = 0,
 202         I40E_MEDIA_TYPE_FIBER,
 203         I40E_MEDIA_TYPE_BASET,
 204         I40E_MEDIA_TYPE_BACKPLANE,
 205         I40E_MEDIA_TYPE_CX4,
 206         I40E_MEDIA_TYPE_DA,
 207         I40E_MEDIA_TYPE_VIRTUAL
 208 };
 209
 210 enum i40e_fc_mode {
 211         I40E_FC_NONE = 0,
 212         I40E_FC_RX_PAUSE,
 213         I40E_FC_TX_PAUSE,
 214         I40E_FC_FULL,
 215         I40E_FC_PFC,
 216         I40E_FC_DEFAULT
 217 };
 218
 219 enum i40e_set_fc_aq_failures {
 220         I40E_SET_FC_AQ_FAIL_NONE = 0,
 221         I40E_SET_FC_AQ_FAIL_GET = 1,
 222         I40E_SET_FC_AQ_FAIL_SET = 2,
 223         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 224         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 225 };
 226
 227 enum i40e_vsi_type {
 228         I40E_VSI_MAIN = 0,
 229         I40E_VSI_VMDQ1,
 230         I40E_VSI_VMDQ2,
 231         I40E_VSI_CTRL,
 232         I40E_VSI_FCOE,
 233         I40E_VSI_MIRROR,
 234         I40E_VSI_SRIOV,
 235         I40E_VSI_FDIR,
 236         I40E_VSI_TYPE_UNKNOWN
 237 };
 238
 239 enum i40e_queue_type {
 240         I40E_QUEUE_TYPE_RX = 0,
 241         I40E_QUEUE_TYPE_TX,
 242         I40E_QUEUE_TYPE_PE_CEQ,
 243         I40E_QUEUE_TYPE_UNKNOWN
 244 };
 245
 246 struct i40e_link_status {
 247         enum i40e_aq_phy_type phy_type;
 248         enum i40e_aq_link_speed link_speed;
 249         u8 link_info;
 250         u8 an_info;
 251         u8 ext_info;
 252         u8 loopback;
 253         bool an_enabled;
 254         /* is Link Status Event notification to SW enabled */
 255         bool lse_enable;
 256         u16 max_frame_size;
 257         bool crc_enable;
 258         u8 pacing;
 259 };
 260
 261 struct i40e_phy_info {
 262         struct i40e_link_status link_info;
 263         struct i40e_link_status link_info_old;
 264         u32 autoneg_advertised;
 265         u32 phy_id;
 266         u32 module_type;
 267         bool get_link_info;
 268         enum i40e_media_type media_type;
 269 };
 270
 271 #define I40E_HW_CAP_MAX_GPIO                    30
 272 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 273 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 274
 275 /* Capabilities of a PF or a VF or the whole device */
 276 struct i40e_hw_capabilities {
 277         u32  switch_mode;
 278 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 279 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 280 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 281
 282         u32  management_mode;
 283         u32  npar_enable;
 284         u32  os2bmc;
 285         u32  valid_functions;
 286         bool sr_iov_1_1;
 287         bool vmdq;
 288         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 289         bool evb_802_1_qbh; /* Bridge Port Extension */
 290         bool dcb;
 291         bool fcoe;
 292         bool mfp_mode_1;
 293         bool mgmt_cem;
 294         bool ieee_1588;
 295         bool iwarp;
 296         bool fd;
 297         u32 fd_filters_guaranteed;
 298         u32 fd_filters_best_effort;
 299         bool rss;
 300         u32 rss_table_size;
 301         u32 rss_table_entry_width;
 302         bool led[I40E_HW_CAP_MAX_GPIO];
 303         bool sdp[I40E_HW_CAP_MAX_GPIO];
 304         u32 nvm_image_type;
 305         u32 num_flow_director_filters;
 306         u32 num_vfs;
 307         u32 vf_base_id;
 308         u32 num_vsis;
 309         u32 num_rx_qp;
 310         u32 num_tx_qp;
 311         u32 base_queue;
 312         u32 num_msix_vectors;
 313         u32 num_msix_vectors_vf;
 314         u32 led_pin_num;
 315         u32 sdp_pin_num;
 316         u32 mdio_port_num;
 317         u32 mdio_port_mode;
 318         u8 rx_buf_chain_len;
 319         u32 enabled_tcmap;
 320         u32 maxtc;
 321 };
 322
 323 struct i40e_mac_info {
 324         enum i40e_mac_type type;
 325         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 326         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 327         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 328         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 329         u16 max_fcoeq;
 330 };
 331
 332 enum i40e_aq_resources_ids {
 333         I40E_NVM_RESOURCE_ID = 1
 334 };
 335
 336 enum i40e_aq_resource_access_type {
 337         I40E_RESOURCE_READ = 1,
 338         I40E_RESOURCE_WRITE
 339 };
 340
 341 struct i40e_nvm_info {
 342         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 343         u64 hw_semaphore_wait;    /* - || - */
 344         u32 timeout;              /* [ms] */
 345         u16 sr_size;              /* Shadow RAM size in words */
 346         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 347         u16 version;              /* NVM package version */
 348         u32 eetrack;              /* NVM data version */
 349 };
 350
 351 /* definitions used in NVM update support */
 352
 353 enum i40e_nvmupd_cmd {
 354         I40E_NVMUPD_INVALID,
 355         I40E_NVMUPD_READ_CON,
 356         I40E_NVMUPD_READ_SNT,
 357         I40E_NVMUPD_READ_LCB,
 358         I40E_NVMUPD_READ_SA,
 359         I40E_NVMUPD_WRITE_ERA,
 360         I40E_NVMUPD_WRITE_CON,
 361         I40E_NVMUPD_WRITE_SNT,
 362         I40E_NVMUPD_WRITE_LCB,
 363         I40E_NVMUPD_WRITE_SA,
 364         I40E_NVMUPD_CSUM_CON,
 365         I40E_NVMUPD_CSUM_SA,
 366         I40E_NVMUPD_CSUM_LCB,
 367 };
 368
 369 enum i40e_nvmupd_state {
 370         I40E_NVMUPD_STATE_INIT,
 371         I40E_NVMUPD_STATE_READING,
 372         I40E_NVMUPD_STATE_WRITING
 373 };
 374
 375 /* nvm_access definition and its masks/shifts need to be accessible to
 376  * application, core driver, and shared code.  Where is the right file?
 377  */
 378 #define I40E_NVM_READ   0xB
 379 #define I40E_NVM_WRITE  0xC
 380
 381 #define I40E_NVM_MOD_PNT_MASK 0xFF
 382
 383 #define I40E_NVM_TRANS_SHIFT    8
 384 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 385 #define I40E_NVM_CON            0x0
 386 #define I40E_NVM_SNT            0x1
 387 #define I40E_NVM_LCB            0x2
 388 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 389 #define I40E_NVM_ERA            0x4
 390 #define I40E_NVM_CSUM           0x8
 391
 392 #define I40E_NVM_ADAPT_SHIFT    16
 393 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 394
 395 #define I40E_NVMUPD_MAX_DATA    4096
 396 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 397
 398 struct i40e_nvm_access {
 399         u32 command;
 400         u32 config;
 401         u32 offset;     /* in bytes */
 402         u32 data_size;  /* in bytes */
 403         u8 data[1];
 404 };
 405
 406 /* PCI bus types */
 407 enum i40e_bus_type {
 408         i40e_bus_type_unknown = 0,
 409         i40e_bus_type_pci,
 410         i40e_bus_type_pcix,
 411         i40e_bus_type_pci_express,
 412         i40e_bus_type_reserved
 413 };
 414
 415 /* PCI bus speeds */
 416 enum i40e_bus_speed {
 417         i40e_bus_speed_unknown  = 0,
 418         i40e_bus_speed_33       = 33,
 419         i40e_bus_speed_66       = 66,
 420         i40e_bus_speed_100      = 100,
 421         i40e_bus_speed_120      = 120,
 422         i40e_bus_speed_133      = 133,
 423         i40e_bus_speed_2500     = 2500,
 424         i40e_bus_speed_5000     = 5000,
 425         i40e_bus_speed_8000     = 8000,
 426         i40e_bus_speed_reserved
 427 };
 428
 429 /* PCI bus widths */
 430 enum i40e_bus_width {
 431         i40e_bus_width_unknown  = 0,
 432         i40e_bus_width_pcie_x1  = 1,
 433         i40e_bus_width_pcie_x2  = 2,
 434         i40e_bus_width_pcie_x4  = 4,
 435         i40e_bus_width_pcie_x8  = 8,
 436         i40e_bus_width_32       = 32,
 437         i40e_bus_width_64       = 64,
 438         i40e_bus_width_reserved
 439 };
 440
 441 /* Bus parameters */
 442 struct i40e_bus_info {
 443         enum i40e_bus_speed speed;
 444         enum i40e_bus_width width;
 445         enum i40e_bus_type type;
 446
 447         u16 func;
 448         u16 device;
 449         u16 lan_id;
 450 };
 451
 452 /* Flow control (FC) parameters */
 453 struct i40e_fc_info {
 454         enum i40e_fc_mode current_mode; /* FC mode in effect */
 455         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 456 };
 457
 458 #define I40E_MAX_TRAFFIC_CLASS          8
 459 #define I40E_MAX_USER_PRIORITY          8
 460 #define I40E_DCBX_MAX_APPS              32
 461 #define I40E_LLDPDU_SIZE                1500
 462 #define I40E_TLV_STATUS_OPER            0x1
 463 #define I40E_TLV_STATUS_SYNC            0x2
 464 #define I40E_TLV_STATUS_ERR             0x4
 465 #define I40E_CEE_OPER_MAX_APPS          3
 466 #define I40E_APP_PROTOID_FCOE           0x8906
 467 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 468 #define I40E_APP_PROTOID_FIP            0x8914
 469 #define I40E_APP_SEL_ETHTYPE            0x1
 470 #define I40E_APP_SEL_TCPIP              0x2
 471
 472 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 473 struct i40e_dcb_ets_config {
 474         u8 willing;
 475         u8 cbs;
 476         u8 maxtcs;
 477         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 478         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 479         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 480 };
 481
 482 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 483 struct i40e_dcb_pfc_config {
 484         u8 willing;
 485         u8 mbc;
 486         u8 pfccap;
 487         u8 pfcenable;
 488 };
 489
 490 /* CEE or IEEE 802.1Qaz Application Priority data */
 491 struct i40e_dcb_app_priority_table {
 492         u8  priority;
 493         u8  selector;
 494         u16 protocolid;
 495 };
 496
 497 struct i40e_dcbx_config {
 498         u8  dcbx_mode;
 499 #define I40E_DCBX_MODE_CEE      0x1
 500 #define I40E_DCBX_MODE_IEEE     0x2
 501         u32 numapps;
 502         struct i40e_dcb_ets_config etscfg;
 503         struct i40e_dcb_ets_config etsrec;
 504         struct i40e_dcb_pfc_config pfc;
 505         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 506 };
 507
 508 /* Port hardware description */
 509 struct i40e_hw {
 510         u8 *hw_addr;
 511         void *back;
 512
 513         /* function pointer structs */
 514         struct i40e_phy_info phy;
 515         struct i40e_mac_info mac;
 516         struct i40e_bus_info bus;
 517         struct i40e_nvm_info nvm;
 518         struct i40e_fc_info fc;
 519
 520         /* pci info */
 521         u16 device_id;
 522         u16 vendor_id;
 523         u16 subsystem_device_id;
 524         u16 subsystem_vendor_id;
 525         u8 revision_id;
 526         u8 port;
 527         bool adapter_stopped;
 528
 529         /* capabilities for entire device and PCI func */
 530         struct i40e_hw_capabilities dev_caps;
 531         struct i40e_hw_capabilities func_caps;
 532
 533         /* Flow Director shared filter space */
 534         u16 fdir_shared_filter_count;
 535
 536         /* device profile info */
 537         u8  pf_id;
 538         u16 main_vsi_seid;
 539
 540         /* Closest numa node to the device */
 541         u16 numa_node;
 542
 543         /* Admin Queue info */
 544         struct i40e_adminq_info aq;
 545
 546         /* state of nvm update process */
 547         enum i40e_nvmupd_state nvmupd_state;
 548
 549         /* HMC info */
 550         struct i40e_hmc_info hmc; /* HMC info struct */
 551
 552         /* LLDP/DCBX Status */
 553         u16 dcbx_status;
 554
 555         /* DCBX info */
 556         struct i40e_dcbx_config local_dcbx_config;
 557         struct i40e_dcbx_config remote_dcbx_config;
 558
 559         /* debug mask */
 560         u32 debug_mask;
 561 };
 562
 563 static inline bool i40e_is_vf(struct i40e_hw *hw)
 564 {
 565         return hw->mac.type == I40E_MAC_VF;
 566 }
 567
 568 struct i40e_driver_version {
 569         u8 major_version;
 570         u8 minor_version;
 571         u8 build_version;
 572         u8 subbuild_version;
 573         u8 driver_string[32];
 574 };
 575
 576 /* RX Descriptors */
 577 union i40e_16byte_rx_desc {
 578         struct {
 579                 __le64 pkt_addr; /* Packet buffer address */
 580                 __le64 hdr_addr; /* Header buffer address */
 581         } read;
 582         struct {
 583                 struct {
 584                         struct {
 585                                 union {
 586                                         __le16 mirroring_status;
 587                                         __le16 fcoe_ctx_id;
 588                                 } mirr_fcoe;
 589                                 __le16 l2tag1;
 590                         } lo_dword;
 591                         union {
 592                                 __le32 rss; /* RSS Hash */
 593                                 __le32 fd_id; /* Flow director filter id */
 594                                 __le32 fcoe_param; /* FCoE DDP Context id */
 595                         } hi_dword;
 596                 } qword0;
 597                 struct {
 598                         /* ext status/error/pktype/length */
 599                         __le64 status_error_len;
 600                 } qword1;
 601         } wb;  /* writeback */
 602 };
 603
 604 union i40e_32byte_rx_desc {
 605         struct {
 606                 __le64  pkt_addr; /* Packet buffer address */
 607                 __le64  hdr_addr; /* Header buffer address */
 608                         /* bit 0 of hdr_buffer_addr is DD bit */
 609                 __le64  rsvd1;
 610                 __le64  rsvd2;
 611         } read;
 612         struct {
 613                 struct {
 614                         struct {
 615                                 union {
 616                                         __le16 mirroring_status;
 617                                         __le16 fcoe_ctx_id;
 618                                 } mirr_fcoe;
 619                                 __le16 l2tag1;
 620                         } lo_dword;
 621                         union {
 622                                 __le32 rss; /* RSS Hash */
 623                                 __le32 fcoe_param; /* FCoE DDP Context id */
 624                                 /* Flow director filter id in case of
 625                                  * Programming status desc WB
 626                                  */
 627                                 __le32 fd_id;
 628                         } hi_dword;
 629                 } qword0;
 630                 struct {
 631                         /* status/error/pktype/length */
 632                         __le64 status_error_len;
 633                 } qword1;
 634                 struct {
 635                         __le16 ext_status; /* extended status */
 636                         __le16 rsvd;
 637                         __le16 l2tag2_1;
 638                         __le16 l2tag2_2;
 639                 } qword2;
 640                 struct {
 641                         union {
 642                                 __le32 flex_bytes_lo;
 643                                 __le32 pe_status;
 644                         } lo_dword;
 645                         union {
 646                                 __le32 flex_bytes_hi;
 647                                 __le32 fd_id;
 648                         } hi_dword;
 649                 } qword3;
 650         } wb;  /* writeback */
 651 };
 652
 653 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 654 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 655                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 656 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 657 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 658                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 659
 660 enum i40e_rx_desc_status_bits {
 661         /* Note: These are predefined bit offsets */
 662         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 663         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 664         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 665         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 666         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 667         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 668         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 669         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 670         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 671         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 672         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 673         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 674         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 675         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 676         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 677         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 678 };
 679
 680 #define I40E_RXD_QW1_STATUS_SHIFT       0
 681 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 682                                          I40E_RXD_QW1_STATUS_SHIFT)
 683
 684 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 685 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 686                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 687
 688 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 689 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 690                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 691
 692 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 693 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 694                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 695
 696 enum i40e_rx_desc_fltstat_values {
 697         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 698         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 699         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 700         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 701 };
 702
 703 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 704 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 705 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 706 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 707
 708 #define I40E_RXD_QW1_ERROR_SHIFT        19
 709 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 710
 711 enum i40e_rx_desc_error_bits {
 712         /* Note: These are predefined bit offsets */
 713         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 714         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 715         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 716         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 717         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 718         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 719         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 720         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 721         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 722 };
 723
 724 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 725         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 726         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 727         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 728         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 729         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 730 };
 731
 732 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 733 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 734
 735 /* Packet type non-ip values */
 736 enum i40e_rx_l2_ptype {
 737         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 738         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 739         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 740         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 741         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 742         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 743         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 744         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 745         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 746         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 747         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 748         I40E_RX_PTYPE_L2_ARP                            = 11,
 749         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 750         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 751         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 752         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 753         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 754         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 755         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 756         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 757         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 758         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 759         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 760         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 761         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 762         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 763 };
 764
 765 struct i40e_rx_ptype_decoded {
 766         u32 ptype:8;
 767         u32 known:1;
 768         u32 outer_ip:1;
 769         u32 outer_ip_ver:1;
 770         u32 outer_frag:1;
 771         u32 tunnel_type:3;
 772         u32 tunnel_end_prot:2;
 773         u32 tunnel_end_frag:1;
 774         u32 inner_prot:4;
 775         u32 payload_layer:3;
 776 };
 777
 778 enum i40e_rx_ptype_outer_ip {
 779         I40E_RX_PTYPE_OUTER_L2  = 0,
 780         I40E_RX_PTYPE_OUTER_IP  = 1
 781 };
 782
 783 enum i40e_rx_ptype_outer_ip_ver {
 784         I40E_RX_PTYPE_OUTER_NONE        = 0,
 785         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 786         I40E_RX_PTYPE_OUTER_IPV6        = 1
 787 };
 788
 789 enum i40e_rx_ptype_outer_fragmented {
 790         I40E_RX_PTYPE_NOT_FRAG  = 0,
 791         I40E_RX_PTYPE_FRAG      = 1
 792 };
 793
 794 enum i40e_rx_ptype_tunnel_type {
 795         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 796         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 797         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 798         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 799         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 800 };
 801
 802 enum i40e_rx_ptype_tunnel_end_prot {
 803         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 804         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 805         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 806 };
 807
 808 enum i40e_rx_ptype_inner_prot {
 809         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 810         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 811         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 812         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 813         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 814         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 815 };
 816
 817 enum i40e_rx_ptype_payload_layer {
 818         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 819         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 820         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 821         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 822 };
 823
 824 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 825 #define I40E_RX_PTYPE_SHIFT             56
 826
 827 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 828 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 829                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 830
 831 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 832 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 833                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 834
 835 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 836 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 837                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 838
 839 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 840 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 841
 842 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 843 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 844                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 845
 846 enum i40e_rx_desc_ext_status_bits {
 847         /* Note: These are predefined bit offsets */
 848         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 849         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 850         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 851         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 852         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 853         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 854         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 855 };
 856
 857 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 858 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 859
 860 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 861 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 862
 863 enum i40e_rx_desc_pe_status_bits {
 864         /* Note: These are predefined bit offsets */
 865         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 866         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 867         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 868         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 869         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 870         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 871         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 872         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 873         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 874 };
 875
 876 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 877 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 878
 879 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 880 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 881                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 882
 883 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 884 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 885                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 886
 887 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 888 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 889                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 890
 891 enum i40e_rx_prog_status_desc_status_bits {
 892         /* Note: These are predefined bit offsets */
 893         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 894         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 895 };
 896
 897 enum i40e_rx_prog_status_desc_prog_id_masks {
 898         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 899         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 900         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 901 };
 902
 903 enum i40e_rx_prog_status_desc_error_bits {
 904         /* Note: These are predefined bit offsets */
 905         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 906         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 907         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 908         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 909 };
 910
 911 #define I40E_TWO_BIT_MASK       0x3
 912 #define I40E_THREE_BIT_MASK     0x7
 913 #define I40E_FOUR_BIT_MASK      0xF
 914 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 915
 916 /* TX Descriptor */
 917 struct i40e_tx_desc {
 918         __le64 buffer_addr; /* Address of descriptor's data buf */
 919         __le64 cmd_type_offset_bsz;
 920 };
 921
 922 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 923 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 924
 925 enum i40e_tx_desc_dtype_value {
 926         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 927         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 928         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 929         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 930         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 931         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 932         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 933         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 934         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 935         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 936 };
 937
 938 #define I40E_TXD_QW1_CMD_SHIFT  4
 939 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 940
 941 enum i40e_tx_desc_cmd_bits {
 942         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 943         I40E_TX_DESC_CMD_RS                     = 0x0002,
 944         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 945         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 946         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 947         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 948         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 949         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 950         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 951         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 952         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 953         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 954         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 955         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 956         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 957         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 958         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 959         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 960 };
 961
 962 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 963 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 964                                          I40E_TXD_QW1_OFFSET_SHIFT)
 965
 966 enum i40e_tx_desc_length_fields {
 967         /* Note: These are predefined bit offsets */
 968         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 969         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 970         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 971 };
 972
 973 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 974 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 975 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 976 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 977
 978 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 979 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 980                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 981
 982 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 983 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 984
 985 /* Context descriptors */
 986 struct i40e_tx_context_desc {
 987         __le32 tunneling_params;
 988         __le16 l2tag2;
 989         __le16 rsvd;
 990         __le64 type_cmd_tso_mss;
 991 };
 992
 993 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 994 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 995
 996 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 997 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 998
 999 enum i40e_tx_ctx_desc_cmd_bits {
1000         I40E_TX_CTX_DESC_TSO            = 0x01,
1001         I40E_TX_CTX_DESC_TSYN           = 0x02,
1002         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1003         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1004         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1005         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1006         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1007         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1008         I40E_TX_CTX_DESC_SWPE           = 0x40
1009 };
1010
1011 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1012 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1013                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1014
1015 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1016 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1017                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1018
1019 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1020 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1021
1022 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1023 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1024                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1025
1026 enum i40e_tx_ctx_desc_eipt_offload {
1027         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1028         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1029         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1030         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1031 };
1032
1033 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1034 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1035                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1036
1037 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1038 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1039
1040 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1041 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1042
1043 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1044 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1045                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1046
1047 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1048
1049 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1050 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1051                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1052
1053 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1054 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1055                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1056
1057 struct i40e_nop_desc {
1058         __le64 rsvd;
1059         __le64 dtype_cmd;
1060 };
1061
1062 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1063 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1064
1065 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1066 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1067
1068 enum i40e_tx_nop_desc_cmd_bits {
1069         /* Note: These are predefined bit offsets */
1070         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1071         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1072         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1073 };
1074
1075 struct i40e_filter_program_desc {
1076         __le32 qindex_flex_ptype_vsi;
1077         __le32 rsvd;
1078         __le32 dtype_cmd_cntindex;
1079         __le32 fd_id;
1080 };
1081 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1082 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1083                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1084 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1085 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1086                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1087 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1088 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1089                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1090
1091 /* Packet Classifier Types for filters */
1092 enum i40e_filter_pctype {
1093         /* Note: Values 0-30 are reserved for future use */
1094         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1095         /* Note: Value 32 is reserved for future use */
1096         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1097         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1098         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1099         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1100         /* Note: Values 37-40 are reserved for future use */
1101         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1102         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1103         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1104         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1105         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1106         /* Note: Value 47 is reserved for future use */
1107         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1108         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1109         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1110         /* Note: Values 51-62 are reserved for future use */
1111         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1112 };
1113
1114 enum i40e_filter_program_desc_dest {
1115         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1116         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1117         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1118 };
1119
1120 enum i40e_filter_program_desc_fd_status {
1121         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1122         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1123         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1124         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1125 };
1126
1127 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1128 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1129                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1130
1131 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1132 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1133
1134 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1135 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1136                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1137
1138 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1139 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1140
1141 enum i40e_filter_program_desc_pcmd {
1142         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1143         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1144 };
1145
1146 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1147 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1148
1149 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1150 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1151                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1152
1153 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1154                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1155 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1156                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1157
1158 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1159 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1160                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1161
1162 enum i40e_filter_type {
1163         I40E_FLOW_DIRECTOR_FLTR = 0,
1164         I40E_PE_QUAD_HASH_FLTR = 1,
1165         I40E_ETHERTYPE_FLTR,
1166         I40E_FCOE_CTX_FLTR,
1167         I40E_MAC_VLAN_FLTR,
1168         I40E_HASH_FLTR
1169 };
1170
1171 struct i40e_vsi_context {
1172         u16 seid;
1173         u16 uplink_seid;
1174         u16 vsi_number;
1175         u16 vsis_allocated;
1176         u16 vsis_unallocated;
1177         u16 flags;
1178         u8 pf_num;
1179         u8 vf_num;
1180         u8 connection_type;
1181         struct i40e_aqc_vsi_properties_data info;
1182 };
1183
1184 struct i40e_veb_context {
1185         u16 seid;
1186         u16 uplink_seid;
1187         u16 veb_number;
1188         u16 vebs_allocated;
1189         u16 vebs_unallocated;
1190         u16 flags;
1191         struct i40e_aqc_get_veb_parameters_completion info;
1192 };
1193
1194 /* Statistics collected by each port, VSI, VEB, and S-channel */
1195 struct i40e_eth_stats {
1196         u64 rx_bytes;                   /* gorc */
1197         u64 rx_unicast;                 /* uprc */
1198         u64 rx_multicast;               /* mprc */
1199         u64 rx_broadcast;               /* bprc */
1200         u64 rx_discards;                /* rdpc */
1201         u64 rx_unknown_protocol;        /* rupp */
1202         u64 tx_bytes;                   /* gotc */
1203         u64 tx_unicast;                 /* uptc */
1204         u64 tx_multicast;               /* mptc */
1205         u64 tx_broadcast;               /* bptc */
1206         u64 tx_discards;                /* tdpc */
1207         u64 tx_errors;                  /* tepc */
1208 };
1209
1210 /* Statistics collected by the MAC */
1211 struct i40e_hw_port_stats {
1212         /* eth stats collected by the port */
1213         struct i40e_eth_stats eth;
1214
1215         /* additional port specific stats */
1216         u64 tx_dropped_link_down;       /* tdold */
1217         u64 crc_errors;                 /* crcerrs */
1218         u64 illegal_bytes;              /* illerrc */
1219         u64 error_bytes;                /* errbc */
1220         u64 mac_local_faults;           /* mlfc */
1221         u64 mac_remote_faults;          /* mrfc */
1222         u64 rx_length_errors;           /* rlec */
1223         u64 link_xon_rx;                /* lxonrxc */
1224         u64 link_xoff_rx;               /* lxoffrxc */
1225         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1226         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1227         u64 link_xon_tx;                /* lxontxc */
1228         u64 link_xoff_tx;               /* lxofftxc */
1229         u64 priority_xon_tx[8];         /* pxontxc[8] */
1230         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1231         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1232         u64 rx_size_64;                 /* prc64 */
1233         u64 rx_size_127;                /* prc127 */
1234         u64 rx_size_255;                /* prc255 */
1235         u64 rx_size_511;                /* prc511 */
1236         u64 rx_size_1023;               /* prc1023 */
1237         u64 rx_size_1522;               /* prc1522 */
1238         u64 rx_size_big;                /* prc9522 */
1239         u64 rx_undersize;               /* ruc */
1240         u64 rx_fragments;               /* rfc */
1241         u64 rx_oversize;                /* roc */
1242         u64 rx_jabber;                  /* rjc */
1243         u64 tx_size_64;                 /* ptc64 */
1244         u64 tx_size_127;                /* ptc127 */
1245         u64 tx_size_255;                /* ptc255 */
1246         u64 tx_size_511;                /* ptc511 */
1247         u64 tx_size_1023;               /* ptc1023 */
1248         u64 tx_size_1522;               /* ptc1522 */
1249         u64 tx_size_big;                /* ptc9522 */
1250         u64 mac_short_packet_dropped;   /* mspdc */
1251         u64 checksum_error;             /* xec */
1252         /* flow director stats */
1253         u64 fd_atr_match;
1254         u64 fd_sb_match;
1255         /* EEE LPI */
1256         u32 tx_lpi_status;
1257         u32 rx_lpi_status;
1258         u64 tx_lpi_count;               /* etlpic */
1259         u64 rx_lpi_count;               /* erlpic */
1260 };
1261
1262 /* Checksum and Shadow RAM pointers */
1263 #define I40E_SR_NVM_CONTROL_WORD                0x00
1264 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1265 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1266 #define I40E_SR_OPTION_ROM_PTR                  0x05
1267 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1268 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1269 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1270 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1271 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1272 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1273 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1274 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1275 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1276 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1277 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1278 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1279 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1280 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1281 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1282 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1283 #define I40E_SR_NVM_MAP_VERSION                 0x29
1284 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1285 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1286 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1287 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1288 #define I40E_SR_VPD_PTR                         0x2F
1289 #define I40E_SR_PXE_SETUP_PTR                   0x30
1290 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1291 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1292 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1293 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1294 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1295 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1296 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1297 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1298 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1299 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1300 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1301 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1302 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1303
1304 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1305 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1306 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1307 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1308 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1309
1310 /* Shadow RAM related */
1311 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1312 #define I40E_SR_BUF_ALIGNMENT           4096
1313 #define I40E_SR_WORDS_IN_1KB            512
1314 /* Checksum should be calculated such that after adding all the words,
1315  * including the checksum word itself, the sum should be 0xBABA.
1316  */
1317 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1318
1319 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1320
1321 enum i40e_switch_element_types {
1322         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1323         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1324         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1325         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1326         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1327         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1328         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1329         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1330         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1331 };
1332
1333 /* Supported EtherType filters */
1334 enum i40e_ether_type_index {
1335         I40E_ETHER_TYPE_1588            = 0,
1336         I40E_ETHER_TYPE_FIP             = 1,
1337         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1338         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1339         I40E_ETHER_TYPE_LLDP            = 4,
1340         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1341         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1342         I40E_ETHER_TYPE_QCN_CNM         = 7,
1343         I40E_ETHER_TYPE_8021X           = 8,
1344         I40E_ETHER_TYPE_ARP             = 9,
1345         I40E_ETHER_TYPE_RSV1            = 10,
1346         I40E_ETHER_TYPE_RSV2            = 11,
1347 };
1348
1349 /* Filter context base size is 1K */
1350 #define I40E_HASH_FILTER_BASE_SIZE      1024
1351 /* Supported Hash filter values */
1352 enum i40e_hash_filter_size {
1353         I40E_HASH_FILTER_SIZE_1K        = 0,
1354         I40E_HASH_FILTER_SIZE_2K        = 1,
1355         I40E_HASH_FILTER_SIZE_4K        = 2,
1356         I40E_HASH_FILTER_SIZE_8K        = 3,
1357         I40E_HASH_FILTER_SIZE_16K       = 4,
1358         I40E_HASH_FILTER_SIZE_32K       = 5,
1359         I40E_HASH_FILTER_SIZE_64K       = 6,
1360         I40E_HASH_FILTER_SIZE_128K      = 7,
1361         I40E_HASH_FILTER_SIZE_256K      = 8,
1362         I40E_HASH_FILTER_SIZE_512K      = 9,
1363         I40E_HASH_FILTER_SIZE_1M        = 10,
1364 };
1365
1366 /* DMA context base size is 0.5K */
1367 #define I40E_DMA_CNTX_BASE_SIZE         512
1368 /* Supported DMA context values */
1369 enum i40e_dma_cntx_size {
1370         I40E_DMA_CNTX_SIZE_512          = 0,
1371         I40E_DMA_CNTX_SIZE_1K           = 1,
1372         I40E_DMA_CNTX_SIZE_2K           = 2,
1373         I40E_DMA_CNTX_SIZE_4K           = 3,
1374         I40E_DMA_CNTX_SIZE_8K           = 4,
1375         I40E_DMA_CNTX_SIZE_16K          = 5,
1376         I40E_DMA_CNTX_SIZE_32K          = 6,
1377         I40E_DMA_CNTX_SIZE_64K          = 7,
1378         I40E_DMA_CNTX_SIZE_128K         = 8,
1379         I40E_DMA_CNTX_SIZE_256K         = 9,
1380 };
1381
1382 /* Supported Hash look up table (LUT) sizes */
1383 enum i40e_hash_lut_size {
1384         I40E_HASH_LUT_SIZE_128          = 0,
1385         I40E_HASH_LUT_SIZE_512          = 1,
1386 };
1387
1388 /* Structure to hold a per PF filter control settings */
1389 struct i40e_filter_control_settings {
1390         /* number of PE Quad Hash filter buckets */
1391         enum i40e_hash_filter_size pe_filt_num;
1392         /* number of PE Quad Hash contexts */
1393         enum i40e_dma_cntx_size pe_cntx_num;
1394         /* number of FCoE filter buckets */
1395         enum i40e_hash_filter_size fcoe_filt_num;
1396         /* number of FCoE DDP contexts */
1397         enum i40e_dma_cntx_size fcoe_cntx_num;
1398         /* size of the Hash LUT */
1399         enum i40e_hash_lut_size hash_lut_size;
1400         /* enable FDIR filters for PF and its VFs */
1401         bool enable_fdir;
1402         /* enable Ethertype filters for PF and its VFs */
1403         bool enable_ethtype;
1404         /* enable MAC/VLAN filters for PF and its VFs */
1405         bool enable_macvlan;
1406 };
1407
1408 /* Structure to hold device level control filter counts */
1409 struct i40e_control_filter_stats {
1410         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1411         u16 etype_used;       /* Used perfect EtherType filters */
1412         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1413         u16 etype_free;       /* Un-used perfect EtherType filters */
1414 };
1415
1416 enum i40e_reset_type {
1417         I40E_RESET_POR          = 0,
1418         I40E_RESET_CORER        = 1,
1419         I40E_RESET_GLOBR        = 2,
1420         I40E_RESET_EMPR         = 3,
1421 };
1422
1423 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1424 #define I40E_NVM_LLDP_CFG_PTR           0xD
1425 struct i40e_lldp_variables {
1426         u16 length;
1427         u16 adminstatus;
1428         u16 msgfasttx;
1429         u16 msgtxinterval;
1430         u16 txparams;
1431         u16 timers;
1432         u16 crc8;
1433 };
1434
1435 /* Offsets into Alternate Ram */
1436 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1437 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1438 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1439 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1440 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1441 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1442
1443 /* Alternate Ram Bandwidth Masks */
1444 #define I40E_ALT_BW_VALUE_MASK          0xFF
1445 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1446 #define I40E_ALT_BW_VALID_MASK          0x80000000
1447
1448 /* RSS Hash Table Size */
1449 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1450 #endif /* _I40E_TYPE_H_ */