4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds*/
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 static int eth_i40e_dev_init(\
97 __attribute__((unused)) struct eth_driver *eth_drv,
98 struct rte_eth_dev *eth_dev);
99 static int i40e_dev_configure(struct rte_eth_dev *dev);
100 static int i40e_dev_start(struct rte_eth_dev *dev);
101 static void i40e_dev_stop(struct rte_eth_dev *dev);
102 static void i40e_dev_close(struct rte_eth_dev *dev);
103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
110 struct rte_eth_stats *stats);
111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
117 struct rte_eth_dev_info *dev_info);
118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
130 struct rte_eth_fc_conf *fc_conf);
131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_pfc_conf *pfc_conf);
133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
134 struct ether_addr *mac_addr,
137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
139 struct rte_eth_rss_reta_entry64 *reta_conf,
141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
142 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40e_get_cap(struct i40e_hw *hw);
146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
147 static int i40e_pf_setup(struct i40e_pf *pf);
148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
151 bool offset_loaded, uint64_t *offset, uint64_t *stat);
152 static void i40e_stat_update_48(struct i40e_hw *hw,
158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
159 static void i40e_dev_interrupt_handler(
160 __rte_unused struct rte_intr_handle *handle, void *param);
161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
162 uint32_t base, uint32_t num);
163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
169 static int i40e_veb_release(struct i40e_veb *veb);
170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
171 struct i40e_vsi *vsi);
172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
175 struct i40e_macvlan_filter *mv_f,
177 struct ether_addr *addr);
178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
179 struct i40e_macvlan_filter *mv_f,
182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
184 struct rte_eth_rss_conf *rss_conf);
185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
186 struct rte_eth_rss_conf *rss_conf);
187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
188 struct rte_eth_udp_tunnel *udp_tunnel);
189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
190 struct rte_eth_udp_tunnel *udp_tunnel);
191 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
192 struct rte_eth_ethertype_filter *filter,
194 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
195 enum rte_filter_op filter_op,
197 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
198 enum rte_filter_type filter_type,
199 enum rte_filter_op filter_op,
202 /* Default hash key buffer for RSS */
203 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
205 static struct rte_pci_id pci_id_i40e_map[] = {
206 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
207 #include "rte_pci_dev_ids.h"
208 { .vendor_id = 0, /* sentinel */ },
211 static struct eth_dev_ops i40e_eth_dev_ops = {
212 .dev_configure = i40e_dev_configure,
213 .dev_start = i40e_dev_start,
214 .dev_stop = i40e_dev_stop,
215 .dev_close = i40e_dev_close,
216 .promiscuous_enable = i40e_dev_promiscuous_enable,
217 .promiscuous_disable = i40e_dev_promiscuous_disable,
218 .allmulticast_enable = i40e_dev_allmulticast_enable,
219 .allmulticast_disable = i40e_dev_allmulticast_disable,
220 .dev_set_link_up = i40e_dev_set_link_up,
221 .dev_set_link_down = i40e_dev_set_link_down,
222 .link_update = i40e_dev_link_update,
223 .stats_get = i40e_dev_stats_get,
224 .stats_reset = i40e_dev_stats_reset,
225 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
226 .dev_infos_get = i40e_dev_info_get,
227 .vlan_filter_set = i40e_vlan_filter_set,
228 .vlan_tpid_set = i40e_vlan_tpid_set,
229 .vlan_offload_set = i40e_vlan_offload_set,
230 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
231 .vlan_pvid_set = i40e_vlan_pvid_set,
232 .rx_queue_start = i40e_dev_rx_queue_start,
233 .rx_queue_stop = i40e_dev_rx_queue_stop,
234 .tx_queue_start = i40e_dev_tx_queue_start,
235 .tx_queue_stop = i40e_dev_tx_queue_stop,
236 .rx_queue_setup = i40e_dev_rx_queue_setup,
237 .rx_queue_release = i40e_dev_rx_queue_release,
238 .rx_queue_count = i40e_dev_rx_queue_count,
239 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
240 .tx_queue_setup = i40e_dev_tx_queue_setup,
241 .tx_queue_release = i40e_dev_tx_queue_release,
242 .dev_led_on = i40e_dev_led_on,
243 .dev_led_off = i40e_dev_led_off,
244 .flow_ctrl_set = i40e_flow_ctrl_set,
245 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
246 .mac_addr_add = i40e_macaddr_add,
247 .mac_addr_remove = i40e_macaddr_remove,
248 .reta_update = i40e_dev_rss_reta_update,
249 .reta_query = i40e_dev_rss_reta_query,
250 .rss_hash_update = i40e_dev_rss_hash_update,
251 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
252 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
253 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
254 .filter_ctrl = i40e_dev_filter_ctrl,
257 static struct eth_driver rte_i40e_pmd = {
259 .name = "rte_i40e_pmd",
260 .id_table = pci_id_i40e_map,
261 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
263 .eth_dev_init = eth_i40e_dev_init,
264 .dev_private_size = sizeof(struct i40e_adapter),
268 i40e_align_floor(int n)
272 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
276 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
277 struct rte_eth_link *link)
279 struct rte_eth_link *dst = link;
280 struct rte_eth_link *src = &(dev->data->dev_link);
282 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
283 *(uint64_t *)src) == 0)
290 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
291 struct rte_eth_link *link)
293 struct rte_eth_link *dst = &(dev->data->dev_link);
294 struct rte_eth_link *src = link;
296 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
297 *(uint64_t *)src) == 0)
304 * Driver initialization routine.
305 * Invoked once at EAL init time.
306 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
309 rte_i40e_pmd_init(const char *name __rte_unused,
310 const char *params __rte_unused)
312 PMD_INIT_FUNC_TRACE();
313 rte_eth_driver_register(&rte_i40e_pmd);
318 static struct rte_driver rte_i40e_driver = {
320 .init = rte_i40e_pmd_init,
323 PMD_REGISTER_DRIVER(rte_i40e_driver);
326 * Initialize registers for flexible payload, which should be set by NVM.
327 * This should be removed from code once it is fixed in NVM.
329 #ifndef I40E_GLQF_ORT
330 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
332 #ifndef I40E_GLQF_PIT
333 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
336 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
338 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
339 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
340 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
341 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
342 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
343 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
344 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
345 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
346 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
347 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
349 /* GLQF_PIT Registers */
350 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
351 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
355 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
356 struct rte_eth_dev *dev)
358 struct rte_pci_device *pci_dev;
359 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
360 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
361 struct i40e_vsi *vsi;
366 PMD_INIT_FUNC_TRACE();
368 dev->dev_ops = &i40e_eth_dev_ops;
369 dev->rx_pkt_burst = i40e_recv_pkts;
370 dev->tx_pkt_burst = i40e_xmit_pkts;
372 /* for secondary processes, we don't initialise any further as primary
373 * has already done this work. Only check we don't need a different
375 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
376 if (dev->data->scattered_rx)
377 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
380 pci_dev = dev->pci_dev;
381 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
382 pf->adapter->eth_dev = dev;
383 pf->dev_data = dev->data;
385 hw->back = I40E_PF_TO_ADAPTER(pf);
386 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
388 PMD_INIT_LOG(ERR, "Hardware is not available, "
389 "as address is NULL");
393 hw->vendor_id = pci_dev->id.vendor_id;
394 hw->device_id = pci_dev->id.device_id;
395 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
396 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
397 hw->bus.device = pci_dev->addr.devid;
398 hw->bus.func = pci_dev->addr.function;
400 /* Make sure all is clean before doing PF reset */
403 /* Reset here to make sure all is clean for each PF */
404 ret = i40e_pf_reset(hw);
406 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
410 /* Initialize the shared code (base driver) */
411 ret = i40e_init_shared_code(hw);
413 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
418 * To work around the NVM issue,initialize registers
419 * for flexible payload by software.
420 * It should be removed once issues are fixed in NVM.
422 i40e_flex_payload_reg_init(hw);
424 /* Initialize the parameters for adminq */
425 i40e_init_adminq_parameter(hw);
426 ret = i40e_init_adminq(hw);
427 if (ret != I40E_SUCCESS) {
428 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
431 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
432 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
433 hw->aq.api_maj_ver, hw->aq.api_min_ver,
434 ((hw->nvm.version >> 12) & 0xf),
435 ((hw->nvm.version >> 4) & 0xff),
436 (hw->nvm.version & 0xf), hw->nvm.eetrack);
439 ret = i40e_aq_stop_lldp(hw, true, NULL);
440 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
441 PMD_INIT_LOG(INFO, "Failed to stop lldp");
444 i40e_clear_pxe_mode(hw);
446 /* Get hw capabilities */
447 ret = i40e_get_cap(hw);
448 if (ret != I40E_SUCCESS) {
449 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
450 goto err_get_capabilities;
453 /* Initialize parameters for PF */
454 ret = i40e_pf_parameter_init(dev);
456 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
457 goto err_parameter_init;
460 /* Initialize the queue management */
461 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
463 PMD_INIT_LOG(ERR, "Failed to init queue pool");
464 goto err_qp_pool_init;
466 ret = i40e_res_pool_init(&pf->msix_pool, 1,
467 hw->func_caps.num_msix_vectors - 1);
469 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
470 goto err_msix_pool_init;
473 /* Initialize lan hmc */
474 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
475 hw->func_caps.num_rx_qp, 0, 0);
476 if (ret != I40E_SUCCESS) {
477 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
478 goto err_init_lan_hmc;
481 /* Configure lan hmc */
482 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
483 if (ret != I40E_SUCCESS) {
484 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
485 goto err_configure_lan_hmc;
488 /* Get and check the mac address */
489 i40e_get_mac_addr(hw, hw->mac.addr);
490 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
491 PMD_INIT_LOG(ERR, "mac address is not valid");
493 goto err_get_mac_addr;
495 /* Copy the permanent MAC address */
496 ether_addr_copy((struct ether_addr *) hw->mac.addr,
497 (struct ether_addr *) hw->mac.perm_addr);
499 /* Disable flow control */
500 hw->fc.requested_mode = I40E_FC_NONE;
501 i40e_set_fc(hw, &aq_fail, TRUE);
503 /* PF setup, which includes VSI setup */
504 ret = i40e_pf_setup(pf);
506 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
507 goto err_setup_pf_switch;
512 /* Disable double vlan by default */
513 i40e_vsi_config_double_vlan(vsi, FALSE);
515 if (!vsi->max_macaddrs)
516 len = ETHER_ADDR_LEN;
518 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
520 /* Should be after VSI initialized */
521 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
522 if (!dev->data->mac_addrs) {
523 PMD_INIT_LOG(ERR, "Failed to allocated memory "
524 "for storing mac address");
527 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
528 &dev->data->mac_addrs[0]);
530 /* initialize pf host driver to setup SRIOV resource if applicable */
531 i40e_pf_host_init(dev);
533 /* register callback func to eal lib */
534 rte_intr_callback_register(&(pci_dev->intr_handle),
535 i40e_dev_interrupt_handler, (void *)dev);
537 /* configure and enable device interrupt */
538 i40e_pf_config_irq0(hw);
539 i40e_pf_enable_irq0(hw);
541 /* enable uio intr after callback register */
542 rte_intr_enable(&(pci_dev->intr_handle));
547 i40e_vsi_release(pf->main_vsi);
550 err_configure_lan_hmc:
551 (void)i40e_shutdown_lan_hmc(hw);
553 i40e_res_pool_destroy(&pf->msix_pool);
555 i40e_res_pool_destroy(&pf->qp_pool);
558 err_get_capabilities:
559 (void)i40e_shutdown_adminq(hw);
565 i40e_dev_configure(struct rte_eth_dev *dev)
567 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
568 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
571 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
572 ret = i40e_fdir_setup(pf);
573 if (ret != I40E_SUCCESS) {
574 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
577 ret = i40e_fdir_configure(dev);
579 PMD_DRV_LOG(ERR, "failed to configure fdir.");
583 i40e_fdir_teardown(pf);
585 ret = i40e_dev_init_vlan(dev);
590 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
591 * RSS setting have different requirements.
592 * General PMD driver call sequence are NIC init, configure,
593 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
594 * will try to lookup the VSI that specific queue belongs to if VMDQ
595 * applicable. So, VMDQ setting has to be done before
596 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
597 * For RSS setting, it will try to calculate actual configured RX queue
598 * number, which will be available after rx_queue_setup(). dev_start()
599 * function is good to place RSS setup.
601 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
602 ret = i40e_vmdq_setup(dev);
608 i40e_fdir_teardown(pf);
613 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
615 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
616 uint16_t msix_vect = vsi->msix_intr;
619 for (i = 0; i < vsi->nb_qps; i++) {
620 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
621 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
625 if (vsi->type != I40E_VSI_SRIOV) {
626 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
627 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
631 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
632 vsi->user_param + (msix_vect - 1);
634 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
636 I40E_WRITE_FLUSH(hw);
639 static inline uint16_t
640 i40e_calc_itr_interval(int16_t interval)
642 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
643 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
645 /* Convert to hardware count, as writing each 1 represents 2 us */
650 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
653 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
654 uint16_t msix_vect = vsi->msix_intr;
657 for (i = 0; i < vsi->nb_qps; i++)
658 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
660 /* Bind all RX queues to allocated MSIX interrupt */
661 for (i = 0; i < vsi->nb_qps; i++) {
662 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
663 I40E_QINT_RQCTL_ITR_INDX_MASK |
664 ((vsi->base_queue + i + 1) <<
665 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
666 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
667 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
669 if (i == vsi->nb_qps - 1)
670 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
671 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
674 /* Write first RX queue to Link list register as the head element */
675 if (vsi->type != I40E_VSI_SRIOV) {
677 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
679 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
681 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
682 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
684 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
685 msix_vect - 1), interval);
687 #ifndef I40E_GLINT_CTL
688 #define I40E_GLINT_CTL 0x0003F800
689 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
691 /* Disable auto-mask on enabling of all none-zero interrupt */
692 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
693 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
697 /* num_msix_vectors_vf needs to minus irq0 */
698 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
699 vsi->user_param + (msix_vect - 1);
701 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
702 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
703 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
706 I40E_WRITE_FLUSH(hw);
710 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
712 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
713 uint16_t interval = i40e_calc_itr_interval(\
714 RTE_LIBRTE_I40E_ITR_INTERVAL);
716 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
717 I40E_PFINT_DYN_CTLN_INTENA_MASK |
718 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
719 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
720 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
724 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
726 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
728 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
731 static inline uint8_t
732 i40e_parse_link_speed(uint16_t eth_link_speed)
734 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
736 switch (eth_link_speed) {
737 case ETH_LINK_SPEED_40G:
738 link_speed = I40E_LINK_SPEED_40GB;
740 case ETH_LINK_SPEED_20G:
741 link_speed = I40E_LINK_SPEED_20GB;
743 case ETH_LINK_SPEED_10G:
744 link_speed = I40E_LINK_SPEED_10GB;
746 case ETH_LINK_SPEED_1000:
747 link_speed = I40E_LINK_SPEED_1GB;
749 case ETH_LINK_SPEED_100:
750 link_speed = I40E_LINK_SPEED_100MB;
758 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
760 enum i40e_status_code status;
761 struct i40e_aq_get_phy_abilities_resp phy_ab;
762 struct i40e_aq_set_phy_config phy_conf;
763 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
764 I40E_AQ_PHY_FLAG_PAUSE_RX |
765 I40E_AQ_PHY_FLAG_LOW_POWER;
766 const uint8_t advt = I40E_LINK_SPEED_40GB |
767 I40E_LINK_SPEED_10GB |
768 I40E_LINK_SPEED_1GB |
769 I40E_LINK_SPEED_100MB;
772 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
777 memset(&phy_conf, 0, sizeof(phy_conf));
779 /* bits 0-2 use the values from get_phy_abilities_resp */
781 abilities |= phy_ab.abilities & mask;
783 /* update ablities and speed */
784 if (abilities & I40E_AQ_PHY_AN_ENABLED)
785 phy_conf.link_speed = advt;
787 phy_conf.link_speed = force_speed;
789 phy_conf.abilities = abilities;
791 /* use get_phy_abilities_resp value for the rest */
792 phy_conf.phy_type = phy_ab.phy_type;
793 phy_conf.eee_capability = phy_ab.eee_capability;
794 phy_conf.eeer = phy_ab.eeer_val;
795 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
797 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
798 phy_ab.abilities, phy_ab.link_speed);
799 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
800 phy_conf.abilities, phy_conf.link_speed);
802 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
810 i40e_apply_link_speed(struct rte_eth_dev *dev)
813 uint8_t abilities = 0;
814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
815 struct rte_eth_conf *conf = &dev->data->dev_conf;
817 speed = i40e_parse_link_speed(conf->link_speed);
818 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
819 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
820 abilities |= I40E_AQ_PHY_AN_ENABLED;
822 abilities |= I40E_AQ_PHY_LINK_ENABLED;
824 return i40e_phy_conf_link(hw, abilities, speed);
828 i40e_dev_start(struct rte_eth_dev *dev)
830 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
832 struct i40e_vsi *main_vsi = pf->main_vsi;
835 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
836 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
837 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
838 dev->data->dev_conf.link_duplex,
844 ret = i40e_dev_rxtx_init(pf);
845 if (ret != I40E_SUCCESS) {
846 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
850 /* Map queues with MSIX interrupt */
851 i40e_vsi_queues_bind_intr(main_vsi);
852 i40e_vsi_enable_queues_intr(main_vsi);
854 /* Map VMDQ VSI queues with MSIX interrupt */
855 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
856 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
857 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
860 /* enable FDIR MSIX interrupt */
861 if (pf->fdir.fdir_vsi) {
862 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
863 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
866 /* Enable all queues which have been configured */
867 ret = i40e_dev_switch_queues(pf, TRUE);
868 if (ret != I40E_SUCCESS) {
869 PMD_DRV_LOG(ERR, "Failed to enable VSI");
873 /* Enable receiving broadcast packets */
874 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
875 if (ret != I40E_SUCCESS)
876 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
878 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
879 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
881 if (ret != I40E_SUCCESS)
882 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
885 /* Apply link configure */
886 ret = i40e_apply_link_speed(dev);
887 if (I40E_SUCCESS != ret) {
888 PMD_DRV_LOG(ERR, "Fail to apply link setting");
895 i40e_dev_switch_queues(pf, FALSE);
896 i40e_dev_clear_queues(dev);
902 i40e_dev_stop(struct rte_eth_dev *dev)
904 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
905 struct i40e_vsi *main_vsi = pf->main_vsi;
908 /* Disable all queues */
909 i40e_dev_switch_queues(pf, FALSE);
911 /* un-map queues with interrupt registers */
912 i40e_vsi_disable_queues_intr(main_vsi);
913 i40e_vsi_queues_unbind_intr(main_vsi);
915 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
916 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
917 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
920 if (pf->fdir.fdir_vsi) {
921 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
922 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
924 /* Clear all queues and release memory */
925 i40e_dev_clear_queues(dev);
928 i40e_dev_set_link_down(dev);
933 i40e_dev_close(struct rte_eth_dev *dev)
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
939 PMD_INIT_FUNC_TRACE();
943 /* Disable interrupt */
944 i40e_pf_disable_irq0(hw);
945 rte_intr_disable(&(dev->pci_dev->intr_handle));
947 /* shutdown and destroy the HMC */
948 i40e_shutdown_lan_hmc(hw);
950 /* release all the existing VSIs and VEBs */
951 i40e_fdir_teardown(pf);
952 i40e_vsi_release(pf->main_vsi);
954 /* shutdown the adminq */
955 i40e_aq_queue_shutdown(hw, true);
956 i40e_shutdown_adminq(hw);
958 i40e_res_pool_destroy(&pf->qp_pool);
959 i40e_res_pool_destroy(&pf->msix_pool);
961 /* force a PF reset to clean anything leftover */
962 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
963 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
964 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
965 I40E_WRITE_FLUSH(hw);
969 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
971 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
972 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 struct i40e_vsi *vsi = pf->main_vsi;
976 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
978 if (status != I40E_SUCCESS)
979 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
981 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
983 if (status != I40E_SUCCESS)
984 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
989 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
991 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
992 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
993 struct i40e_vsi *vsi = pf->main_vsi;
996 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
998 if (status != I40E_SUCCESS)
999 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1001 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1003 if (status != I40E_SUCCESS)
1004 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1008 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1010 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1011 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1012 struct i40e_vsi *vsi = pf->main_vsi;
1015 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1016 if (ret != I40E_SUCCESS)
1017 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1021 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025 struct i40e_vsi *vsi = pf->main_vsi;
1028 if (dev->data->promiscuous == 1)
1029 return; /* must remain in all_multicast mode */
1031 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1032 vsi->seid, FALSE, NULL);
1033 if (ret != I40E_SUCCESS)
1034 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1038 * Set device link up.
1041 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1043 /* re-apply link speed setting */
1044 return i40e_apply_link_speed(dev);
1048 * Set device link down.
1051 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1053 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1054 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1055 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057 return i40e_phy_conf_link(hw, abilities, speed);
1061 i40e_dev_link_update(struct rte_eth_dev *dev,
1062 __rte_unused int wait_to_complete)
1064 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065 struct i40e_link_status link_status;
1066 struct rte_eth_link link, old;
1069 memset(&link, 0, sizeof(link));
1070 memset(&old, 0, sizeof(old));
1071 memset(&link_status, 0, sizeof(link_status));
1072 rte_i40e_dev_atomic_read_link_status(dev, &old);
1074 /* Get link status information from hardware */
1075 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1076 if (status != I40E_SUCCESS) {
1077 link.link_speed = ETH_LINK_SPEED_100;
1078 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1079 PMD_DRV_LOG(ERR, "Failed to get link info");
1083 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1085 if (!link.link_status)
1088 /* i40e uses full duplex only */
1089 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1091 /* Parse the link status */
1092 switch (link_status.link_speed) {
1093 case I40E_LINK_SPEED_100MB:
1094 link.link_speed = ETH_LINK_SPEED_100;
1096 case I40E_LINK_SPEED_1GB:
1097 link.link_speed = ETH_LINK_SPEED_1000;
1099 case I40E_LINK_SPEED_10GB:
1100 link.link_speed = ETH_LINK_SPEED_10G;
1102 case I40E_LINK_SPEED_20GB:
1103 link.link_speed = ETH_LINK_SPEED_20G;
1105 case I40E_LINK_SPEED_40GB:
1106 link.link_speed = ETH_LINK_SPEED_40G;
1109 link.link_speed = ETH_LINK_SPEED_100;
1114 rte_i40e_dev_atomic_write_link_status(dev, &link);
1115 if (link.link_status == old.link_status)
1121 /* Get all the statistics of a VSI */
1123 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1125 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1126 struct i40e_eth_stats *nes = &vsi->eth_stats;
1127 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1128 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1130 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1131 vsi->offset_loaded, &oes->rx_bytes,
1133 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1134 vsi->offset_loaded, &oes->rx_unicast,
1136 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1137 vsi->offset_loaded, &oes->rx_multicast,
1138 &nes->rx_multicast);
1139 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1140 vsi->offset_loaded, &oes->rx_broadcast,
1141 &nes->rx_broadcast);
1142 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1143 &oes->rx_discards, &nes->rx_discards);
1144 /* GLV_REPC not supported */
1145 /* GLV_RMPC not supported */
1146 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1147 &oes->rx_unknown_protocol,
1148 &nes->rx_unknown_protocol);
1149 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1150 vsi->offset_loaded, &oes->tx_bytes,
1152 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1153 vsi->offset_loaded, &oes->tx_unicast,
1155 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1156 vsi->offset_loaded, &oes->tx_multicast,
1157 &nes->tx_multicast);
1158 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1159 vsi->offset_loaded, &oes->tx_broadcast,
1160 &nes->tx_broadcast);
1161 /* GLV_TDPC not supported */
1162 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1163 &oes->tx_errors, &nes->tx_errors);
1164 vsi->offset_loaded = true;
1166 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1168 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1169 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1170 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1171 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1172 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1173 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1174 nes->rx_unknown_protocol);
1175 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1176 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1177 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1178 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1179 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1180 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1181 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1185 /* Get all statistics of a port */
1187 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1190 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1191 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1193 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1195 /* Get statistics of struct i40e_eth_stats */
1196 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1197 I40E_GLPRT_GORCL(hw->port),
1198 pf->offset_loaded, &os->eth.rx_bytes,
1200 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1201 I40E_GLPRT_UPRCL(hw->port),
1202 pf->offset_loaded, &os->eth.rx_unicast,
1203 &ns->eth.rx_unicast);
1204 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1205 I40E_GLPRT_MPRCL(hw->port),
1206 pf->offset_loaded, &os->eth.rx_multicast,
1207 &ns->eth.rx_multicast);
1208 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1209 I40E_GLPRT_BPRCL(hw->port),
1210 pf->offset_loaded, &os->eth.rx_broadcast,
1211 &ns->eth.rx_broadcast);
1212 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1213 pf->offset_loaded, &os->eth.rx_discards,
1214 &ns->eth.rx_discards);
1215 /* GLPRT_REPC not supported */
1216 /* GLPRT_RMPC not supported */
1217 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1219 &os->eth.rx_unknown_protocol,
1220 &ns->eth.rx_unknown_protocol);
1221 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1222 I40E_GLPRT_GOTCL(hw->port),
1223 pf->offset_loaded, &os->eth.tx_bytes,
1225 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1226 I40E_GLPRT_UPTCL(hw->port),
1227 pf->offset_loaded, &os->eth.tx_unicast,
1228 &ns->eth.tx_unicast);
1229 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1230 I40E_GLPRT_MPTCL(hw->port),
1231 pf->offset_loaded, &os->eth.tx_multicast,
1232 &ns->eth.tx_multicast);
1233 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1234 I40E_GLPRT_BPTCL(hw->port),
1235 pf->offset_loaded, &os->eth.tx_broadcast,
1236 &ns->eth.tx_broadcast);
1237 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1238 pf->offset_loaded, &os->eth.tx_discards,
1239 &ns->eth.tx_discards);
1240 /* GLPRT_TEPC not supported */
1242 /* additional port specific stats */
1243 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1244 pf->offset_loaded, &os->tx_dropped_link_down,
1245 &ns->tx_dropped_link_down);
1246 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1247 pf->offset_loaded, &os->crc_errors,
1249 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1250 pf->offset_loaded, &os->illegal_bytes,
1251 &ns->illegal_bytes);
1252 /* GLPRT_ERRBC not supported */
1253 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1254 pf->offset_loaded, &os->mac_local_faults,
1255 &ns->mac_local_faults);
1256 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1257 pf->offset_loaded, &os->mac_remote_faults,
1258 &ns->mac_remote_faults);
1259 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1260 pf->offset_loaded, &os->rx_length_errors,
1261 &ns->rx_length_errors);
1262 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1263 pf->offset_loaded, &os->link_xon_rx,
1265 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1266 pf->offset_loaded, &os->link_xoff_rx,
1268 for (i = 0; i < 8; i++) {
1269 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1271 &os->priority_xon_rx[i],
1272 &ns->priority_xon_rx[i]);
1273 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1275 &os->priority_xoff_rx[i],
1276 &ns->priority_xoff_rx[i]);
1278 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1279 pf->offset_loaded, &os->link_xon_tx,
1281 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1282 pf->offset_loaded, &os->link_xoff_tx,
1284 for (i = 0; i < 8; i++) {
1285 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1287 &os->priority_xon_tx[i],
1288 &ns->priority_xon_tx[i]);
1289 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1291 &os->priority_xoff_tx[i],
1292 &ns->priority_xoff_tx[i]);
1293 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1295 &os->priority_xon_2_xoff[i],
1296 &ns->priority_xon_2_xoff[i]);
1298 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1299 I40E_GLPRT_PRC64L(hw->port),
1300 pf->offset_loaded, &os->rx_size_64,
1302 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1303 I40E_GLPRT_PRC127L(hw->port),
1304 pf->offset_loaded, &os->rx_size_127,
1306 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1307 I40E_GLPRT_PRC255L(hw->port),
1308 pf->offset_loaded, &os->rx_size_255,
1310 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1311 I40E_GLPRT_PRC511L(hw->port),
1312 pf->offset_loaded, &os->rx_size_511,
1314 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1315 I40E_GLPRT_PRC1023L(hw->port),
1316 pf->offset_loaded, &os->rx_size_1023,
1318 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1319 I40E_GLPRT_PRC1522L(hw->port),
1320 pf->offset_loaded, &os->rx_size_1522,
1322 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1323 I40E_GLPRT_PRC9522L(hw->port),
1324 pf->offset_loaded, &os->rx_size_big,
1326 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1327 pf->offset_loaded, &os->rx_undersize,
1329 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1330 pf->offset_loaded, &os->rx_fragments,
1332 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1333 pf->offset_loaded, &os->rx_oversize,
1335 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1336 pf->offset_loaded, &os->rx_jabber,
1338 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1339 I40E_GLPRT_PTC64L(hw->port),
1340 pf->offset_loaded, &os->tx_size_64,
1342 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1343 I40E_GLPRT_PTC127L(hw->port),
1344 pf->offset_loaded, &os->tx_size_127,
1346 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1347 I40E_GLPRT_PTC255L(hw->port),
1348 pf->offset_loaded, &os->tx_size_255,
1350 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1351 I40E_GLPRT_PTC511L(hw->port),
1352 pf->offset_loaded, &os->tx_size_511,
1354 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1355 I40E_GLPRT_PTC1023L(hw->port),
1356 pf->offset_loaded, &os->tx_size_1023,
1358 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1359 I40E_GLPRT_PTC1522L(hw->port),
1360 pf->offset_loaded, &os->tx_size_1522,
1362 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1363 I40E_GLPRT_PTC9522L(hw->port),
1364 pf->offset_loaded, &os->tx_size_big,
1366 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1368 &os->fd_sb_match, &ns->fd_sb_match);
1369 /* GLPRT_MSPDC not supported */
1370 /* GLPRT_XEC not supported */
1372 pf->offset_loaded = true;
1375 i40e_update_vsi_stats(pf->main_vsi);
1377 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1378 ns->eth.rx_broadcast;
1379 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1380 ns->eth.tx_broadcast;
1381 stats->ibytes = ns->eth.rx_bytes;
1382 stats->obytes = ns->eth.tx_bytes;
1383 stats->oerrors = ns->eth.tx_errors;
1384 stats->imcasts = ns->eth.rx_multicast;
1385 stats->fdirmatch = ns->fd_sb_match;
1388 stats->ibadcrc = ns->crc_errors;
1389 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1390 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1391 stats->imissed = ns->eth.rx_discards;
1392 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1394 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1395 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1396 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1397 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1398 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1399 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1400 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1401 ns->eth.rx_unknown_protocol);
1402 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1403 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1404 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1405 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1406 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1407 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1409 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1410 ns->tx_dropped_link_down);
1411 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1412 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1414 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1415 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1416 ns->mac_local_faults);
1417 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1418 ns->mac_remote_faults);
1419 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1420 ns->rx_length_errors);
1421 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1422 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1423 for (i = 0; i < 8; i++) {
1424 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1425 i, ns->priority_xon_rx[i]);
1426 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1427 i, ns->priority_xoff_rx[i]);
1429 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1430 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1431 for (i = 0; i < 8; i++) {
1432 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1433 i, ns->priority_xon_tx[i]);
1434 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1435 i, ns->priority_xoff_tx[i]);
1436 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1437 i, ns->priority_xon_2_xoff[i]);
1439 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1440 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1441 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1442 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1443 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1444 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1445 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1446 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1447 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1448 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1449 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1450 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1451 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1452 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1453 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1454 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1455 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1456 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1457 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1458 ns->mac_short_packet_dropped);
1459 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1460 ns->checksum_error);
1461 PMD_DRV_LOG(DEBUG, "fdir_match: %lu", ns->fd_sb_match);
1462 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1465 /* Reset the statistics */
1467 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1469 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1471 /* It results in reloading the start point of each counter */
1472 pf->offset_loaded = false;
1476 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1477 __rte_unused uint16_t queue_id,
1478 __rte_unused uint8_t stat_idx,
1479 __rte_unused uint8_t is_rx)
1481 PMD_INIT_FUNC_TRACE();
1487 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1490 struct i40e_vsi *vsi = pf->main_vsi;
1492 dev_info->max_rx_queues = vsi->nb_qps;
1493 dev_info->max_tx_queues = vsi->nb_qps;
1494 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1495 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1496 dev_info->max_mac_addrs = vsi->max_macaddrs;
1497 dev_info->max_vfs = dev->pci_dev->max_vfs;
1498 dev_info->rx_offload_capa =
1499 DEV_RX_OFFLOAD_VLAN_STRIP |
1500 DEV_RX_OFFLOAD_IPV4_CKSUM |
1501 DEV_RX_OFFLOAD_UDP_CKSUM |
1502 DEV_RX_OFFLOAD_TCP_CKSUM;
1503 dev_info->tx_offload_capa =
1504 DEV_TX_OFFLOAD_VLAN_INSERT |
1505 DEV_TX_OFFLOAD_IPV4_CKSUM |
1506 DEV_TX_OFFLOAD_UDP_CKSUM |
1507 DEV_TX_OFFLOAD_TCP_CKSUM |
1508 DEV_TX_OFFLOAD_SCTP_CKSUM;
1509 dev_info->reta_size = pf->hash_lut_size;
1511 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1513 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1514 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1515 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1517 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1521 dev_info->default_txconf = (struct rte_eth_txconf) {
1523 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1524 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1525 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1527 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1528 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1529 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1530 ETH_TXQ_FLAGS_NOOFFLOADS,
1533 if (pf->flags | I40E_FLAG_VMDQ) {
1534 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1535 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1536 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1537 pf->max_nb_vmdq_vsi;
1538 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1539 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1540 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1545 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1548 struct i40e_vsi *vsi = pf->main_vsi;
1549 PMD_INIT_FUNC_TRACE();
1552 return i40e_vsi_add_vlan(vsi, vlan_id);
1554 return i40e_vsi_delete_vlan(vsi, vlan_id);
1558 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1559 __rte_unused uint16_t tpid)
1561 PMD_INIT_FUNC_TRACE();
1565 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1567 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1568 struct i40e_vsi *vsi = pf->main_vsi;
1570 if (mask & ETH_VLAN_STRIP_MASK) {
1571 /* Enable or disable VLAN stripping */
1572 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1573 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1575 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1578 if (mask & ETH_VLAN_EXTEND_MASK) {
1579 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1580 i40e_vsi_config_double_vlan(vsi, TRUE);
1582 i40e_vsi_config_double_vlan(vsi, FALSE);
1587 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1588 __rte_unused uint16_t queue,
1589 __rte_unused int on)
1591 PMD_INIT_FUNC_TRACE();
1595 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1597 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1598 struct i40e_vsi *vsi = pf->main_vsi;
1599 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1600 struct i40e_vsi_vlan_pvid_info info;
1602 memset(&info, 0, sizeof(info));
1605 info.config.pvid = pvid;
1607 info.config.reject.tagged =
1608 data->dev_conf.txmode.hw_vlan_reject_tagged;
1609 info.config.reject.untagged =
1610 data->dev_conf.txmode.hw_vlan_reject_untagged;
1613 return i40e_vsi_vlan_pvid_set(vsi, &info);
1617 i40e_dev_led_on(struct rte_eth_dev *dev)
1619 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620 uint32_t mode = i40e_led_get(hw);
1623 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1629 i40e_dev_led_off(struct rte_eth_dev *dev)
1631 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632 uint32_t mode = i40e_led_get(hw);
1635 i40e_led_set(hw, 0, false);
1641 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1642 __rte_unused struct rte_eth_fc_conf *fc_conf)
1644 PMD_INIT_FUNC_TRACE();
1650 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1651 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1653 PMD_INIT_FUNC_TRACE();
1658 /* Add a MAC address, and update filters */
1660 i40e_macaddr_add(struct rte_eth_dev *dev,
1661 struct ether_addr *mac_addr,
1662 __rte_unused uint32_t index,
1665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666 struct i40e_mac_filter_info mac_filter;
1667 struct i40e_vsi *vsi;
1670 /* If VMDQ not enabled or configured, return */
1671 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1672 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1673 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1678 if (pool > pf->nb_cfg_vmdq_vsi) {
1679 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1680 pool, pf->nb_cfg_vmdq_vsi);
1684 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1685 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1690 vsi = pf->vmdq[pool - 1].vsi;
1692 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1693 if (ret != I40E_SUCCESS) {
1694 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1699 /* Remove a MAC address, and update filters */
1701 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1704 struct i40e_vsi *vsi;
1705 struct rte_eth_dev_data *data = dev->data;
1706 struct ether_addr *macaddr;
1711 macaddr = &(data->mac_addrs[index]);
1713 pool_sel = dev->data->mac_pool_sel[index];
1715 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1716 if (pool_sel & (1ULL << i)) {
1720 /* No VMDQ pool enabled or configured */
1721 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1722 (i > pf->nb_cfg_vmdq_vsi)) {
1723 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1727 vsi = pf->vmdq[i - 1].vsi;
1729 ret = i40e_vsi_delete_mac(vsi, macaddr);
1732 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1739 /* Set perfect match or hash match of MAC and VLAN for a VF */
1741 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1742 struct rte_eth_mac_filter *filter,
1746 struct i40e_mac_filter_info mac_filter;
1747 struct ether_addr old_mac;
1748 struct ether_addr *new_mac;
1749 struct i40e_pf_vf *vf = NULL;
1754 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1757 hw = I40E_PF_TO_HW(pf);
1759 if (filter == NULL) {
1760 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1764 new_mac = &filter->mac_addr;
1766 if (is_zero_ether_addr(new_mac)) {
1767 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1771 vf_id = filter->dst_id;
1773 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1774 PMD_DRV_LOG(ERR, "Invalid argument.");
1777 vf = &pf->vfs[vf_id];
1779 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1780 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1785 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1786 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1788 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1791 mac_filter.filter_type = filter->filter_type;
1792 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1793 if (ret != I40E_SUCCESS) {
1794 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1797 ether_addr_copy(new_mac, &pf->dev_addr);
1799 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1801 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1802 if (ret != I40E_SUCCESS) {
1803 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1807 /* Clear device address as it has been removed */
1808 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1809 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1815 /* MAC filter handle */
1817 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1820 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1821 struct rte_eth_mac_filter *filter;
1822 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1823 int ret = I40E_NOT_SUPPORTED;
1825 filter = (struct rte_eth_mac_filter *)(arg);
1827 switch (filter_op) {
1828 case RTE_ETH_FILTER_NOP:
1831 case RTE_ETH_FILTER_ADD:
1832 i40e_pf_disable_irq0(hw);
1834 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1835 i40e_pf_enable_irq0(hw);
1837 case RTE_ETH_FILTER_DELETE:
1838 i40e_pf_disable_irq0(hw);
1840 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1841 i40e_pf_enable_irq0(hw);
1844 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1845 ret = I40E_ERR_PARAM;
1853 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1854 struct rte_eth_rss_reta_entry64 *reta_conf,
1857 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860 uint16_t i, j, lut_size = pf->hash_lut_size;
1861 uint16_t idx, shift;
1864 if (reta_size != lut_size ||
1865 reta_size > ETH_RSS_RETA_SIZE_512) {
1866 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1867 "(%d) doesn't match the number hardware can supported "
1868 "(%d)\n", reta_size, lut_size);
1872 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1873 idx = i / RTE_RETA_GROUP_SIZE;
1874 shift = i % RTE_RETA_GROUP_SIZE;
1875 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1879 if (mask == I40E_4_BIT_MASK)
1882 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1883 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1884 if (mask & (0x1 << j))
1885 lut |= reta_conf[idx].reta[shift + j] <<
1888 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1890 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1897 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1898 struct rte_eth_rss_reta_entry64 *reta_conf,
1901 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1902 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904 uint16_t i, j, lut_size = pf->hash_lut_size;
1905 uint16_t idx, shift;
1908 if (reta_size != lut_size ||
1909 reta_size > ETH_RSS_RETA_SIZE_512) {
1910 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1911 "(%d) doesn't match the number hardware can supported "
1912 "(%d)\n", reta_size, lut_size);
1916 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1917 idx = i / RTE_RETA_GROUP_SIZE;
1918 shift = i % RTE_RETA_GROUP_SIZE;
1919 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1924 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1925 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1926 if (mask & (0x1 << j))
1927 reta_conf[idx].reta[shift + j] = ((lut >>
1928 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1936 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1937 * @hw: pointer to the HW structure
1938 * @mem: pointer to mem struct to fill out
1939 * @size: size of memory requested
1940 * @alignment: what to align the allocation to
1942 enum i40e_status_code
1943 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1944 struct i40e_dma_mem *mem,
1948 static uint64_t id = 0;
1949 const struct rte_memzone *mz = NULL;
1950 char z_name[RTE_MEMZONE_NAMESIZE];
1953 return I40E_ERR_PARAM;
1956 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1957 #ifdef RTE_LIBRTE_XEN_DOM0
1958 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1961 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1964 return I40E_ERR_NO_MEMORY;
1969 #ifdef RTE_LIBRTE_XEN_DOM0
1970 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1972 mem->pa = mz->phys_addr;
1975 return I40E_SUCCESS;
1979 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1980 * @hw: pointer to the HW structure
1981 * @mem: ptr to mem struct to free
1983 enum i40e_status_code
1984 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1985 struct i40e_dma_mem *mem)
1987 if (!mem || !mem->va)
1988 return I40E_ERR_PARAM;
1993 return I40E_SUCCESS;
1997 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1998 * @hw: pointer to the HW structure
1999 * @mem: pointer to mem struct to fill out
2000 * @size: size of memory requested
2002 enum i40e_status_code
2003 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2004 struct i40e_virt_mem *mem,
2008 return I40E_ERR_PARAM;
2011 mem->va = rte_zmalloc("i40e", size, 0);
2014 return I40E_SUCCESS;
2016 return I40E_ERR_NO_MEMORY;
2020 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2021 * @hw: pointer to the HW structure
2022 * @mem: pointer to mem struct to free
2024 enum i40e_status_code
2025 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2026 struct i40e_virt_mem *mem)
2029 return I40E_ERR_PARAM;
2034 return I40E_SUCCESS;
2038 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2040 rte_spinlock_init(&sp->spinlock);
2044 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2046 rte_spinlock_lock(&sp->spinlock);
2050 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2052 rte_spinlock_unlock(&sp->spinlock);
2056 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2062 * Get the hardware capabilities, which will be parsed
2063 * and saved into struct i40e_hw.
2066 i40e_get_cap(struct i40e_hw *hw)
2068 struct i40e_aqc_list_capabilities_element_resp *buf;
2069 uint16_t len, size = 0;
2072 /* Calculate a huge enough buff for saving response data temporarily */
2073 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2074 I40E_MAX_CAP_ELE_NUM;
2075 buf = rte_zmalloc("i40e", len, 0);
2077 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2078 return I40E_ERR_NO_MEMORY;
2081 /* Get, parse the capabilities and save it to hw */
2082 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2083 i40e_aqc_opc_list_func_capabilities, NULL);
2084 if (ret != I40E_SUCCESS)
2085 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2087 /* Free the temporary buffer after being used */
2094 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2096 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2097 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2098 uint16_t sum_queues = 0, sum_vsis, left_queues;
2100 /* First check if FW support SRIOV */
2101 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2102 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2106 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2107 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2108 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2109 /* Allocate queues for pf */
2110 if (hw->func_caps.rss) {
2111 pf->flags |= I40E_FLAG_RSS;
2112 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2113 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2114 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2117 sum_queues = pf->lan_nb_qps;
2118 /* Default VSI is not counted in */
2120 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2122 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2123 pf->flags |= I40E_FLAG_SRIOV;
2124 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2125 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2126 PMD_INIT_LOG(ERR, "Config VF number %u, "
2127 "max supported %u.",
2128 dev->pci_dev->max_vfs,
2129 hw->func_caps.num_vfs);
2132 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2133 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2134 "max support %u queues.",
2135 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2138 pf->vf_num = dev->pci_dev->max_vfs;
2139 sum_queues += pf->vf_nb_qps * pf->vf_num;
2140 sum_vsis += pf->vf_num;
2141 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2142 pf->vf_num, pf->vf_nb_qps);
2146 if (hw->func_caps.vmdq) {
2147 pf->flags |= I40E_FLAG_VMDQ;
2148 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2149 pf->max_nb_vmdq_vsi = 1;
2151 * If VMDQ available, assume a single VSI can be created. Will adjust
2154 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2155 sum_vsis += pf->max_nb_vmdq_vsi;
2157 pf->vmdq_nb_qps = 0;
2158 pf->max_nb_vmdq_vsi = 0;
2160 pf->nb_cfg_vmdq_vsi = 0;
2162 if (hw->func_caps.fd) {
2163 pf->flags |= I40E_FLAG_FDIR;
2164 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2166 * Each flow director consumes one VSI and one queue,
2167 * but can't calculate out predictably here.
2171 if (sum_vsis > pf->max_num_vsi ||
2172 sum_queues > hw->func_caps.num_rx_qp) {
2173 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2174 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2175 pf->max_num_vsi, sum_vsis);
2176 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2177 hw->func_caps.num_rx_qp, sum_queues);
2181 /* Adjust VMDQ setting to support as many VMs as possible */
2182 if (pf->flags & I40E_FLAG_VMDQ) {
2183 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2185 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2186 pf->max_num_vsi - sum_vsis);
2188 /* Limit the max VMDQ number that rte_ether that can support */
2189 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2192 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2193 pf->max_nb_vmdq_vsi);
2194 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2197 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2199 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2200 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2201 sum_vsis, hw->func_caps.num_msix_vectors);
2204 return I40E_SUCCESS;
2208 i40e_pf_get_switch_config(struct i40e_pf *pf)
2210 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2211 struct i40e_aqc_get_switch_config_resp *switch_config;
2212 struct i40e_aqc_switch_config_element_resp *element;
2213 uint16_t start_seid = 0, num_reported;
2216 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2217 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2218 if (!switch_config) {
2219 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2223 /* Get the switch configurations */
2224 ret = i40e_aq_get_switch_config(hw, switch_config,
2225 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2226 if (ret != I40E_SUCCESS) {
2227 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2230 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2231 if (num_reported != 1) { /* The number should be 1 */
2232 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2236 /* Parse the switch configuration elements */
2237 element = &(switch_config->element[0]);
2238 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2239 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2240 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2242 PMD_DRV_LOG(INFO, "Unknown element type");
2245 rte_free(switch_config);
2251 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2254 struct pool_entry *entry;
2256 if (pool == NULL || num == 0)
2259 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2260 if (entry == NULL) {
2261 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2265 /* queue heap initialize */
2266 pool->num_free = num;
2267 pool->num_alloc = 0;
2269 LIST_INIT(&pool->alloc_list);
2270 LIST_INIT(&pool->free_list);
2272 /* Initialize element */
2276 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2281 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2283 struct pool_entry *entry;
2288 LIST_FOREACH(entry, &pool->alloc_list, next) {
2289 LIST_REMOVE(entry, next);
2293 LIST_FOREACH(entry, &pool->free_list, next) {
2294 LIST_REMOVE(entry, next);
2299 pool->num_alloc = 0;
2301 LIST_INIT(&pool->alloc_list);
2302 LIST_INIT(&pool->free_list);
2306 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2309 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2310 uint32_t pool_offset;
2314 PMD_DRV_LOG(ERR, "Invalid parameter");
2318 pool_offset = base - pool->base;
2319 /* Lookup in alloc list */
2320 LIST_FOREACH(entry, &pool->alloc_list, next) {
2321 if (entry->base == pool_offset) {
2322 valid_entry = entry;
2323 LIST_REMOVE(entry, next);
2328 /* Not find, return */
2329 if (valid_entry == NULL) {
2330 PMD_DRV_LOG(ERR, "Failed to find entry");
2335 * Found it, move it to free list and try to merge.
2336 * In order to make merge easier, always sort it by qbase.
2337 * Find adjacent prev and last entries.
2340 LIST_FOREACH(entry, &pool->free_list, next) {
2341 if (entry->base > valid_entry->base) {
2349 /* Try to merge with next one*/
2351 /* Merge with next one */
2352 if (valid_entry->base + valid_entry->len == next->base) {
2353 next->base = valid_entry->base;
2354 next->len += valid_entry->len;
2355 rte_free(valid_entry);
2362 /* Merge with previous one */
2363 if (prev->base + prev->len == valid_entry->base) {
2364 prev->len += valid_entry->len;
2365 /* If it merge with next one, remove next node */
2367 LIST_REMOVE(valid_entry, next);
2368 rte_free(valid_entry);
2370 rte_free(valid_entry);
2376 /* Not find any entry to merge, insert */
2379 LIST_INSERT_AFTER(prev, valid_entry, next);
2380 else if (next != NULL)
2381 LIST_INSERT_BEFORE(next, valid_entry, next);
2382 else /* It's empty list, insert to head */
2383 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2386 pool->num_free += valid_entry->len;
2387 pool->num_alloc -= valid_entry->len;
2393 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2396 struct pool_entry *entry, *valid_entry;
2398 if (pool == NULL || num == 0) {
2399 PMD_DRV_LOG(ERR, "Invalid parameter");
2403 if (pool->num_free < num) {
2404 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2405 num, pool->num_free);
2410 /* Lookup in free list and find most fit one */
2411 LIST_FOREACH(entry, &pool->free_list, next) {
2412 if (entry->len >= num) {
2414 if (entry->len == num) {
2415 valid_entry = entry;
2418 if (valid_entry == NULL || valid_entry->len > entry->len)
2419 valid_entry = entry;
2423 /* Not find one to satisfy the request, return */
2424 if (valid_entry == NULL) {
2425 PMD_DRV_LOG(ERR, "No valid entry found");
2429 * The entry have equal queue number as requested,
2430 * remove it from alloc_list.
2432 if (valid_entry->len == num) {
2433 LIST_REMOVE(valid_entry, next);
2436 * The entry have more numbers than requested,
2437 * create a new entry for alloc_list and minus its
2438 * queue base and number in free_list.
2440 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2441 if (entry == NULL) {
2442 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2446 entry->base = valid_entry->base;
2448 valid_entry->base += num;
2449 valid_entry->len -= num;
2450 valid_entry = entry;
2453 /* Insert it into alloc list, not sorted */
2454 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2456 pool->num_free -= valid_entry->len;
2457 pool->num_alloc += valid_entry->len;
2459 return (valid_entry->base + pool->base);
2463 * bitmap_is_subset - Check whether src2 is subset of src1
2466 bitmap_is_subset(uint8_t src1, uint8_t src2)
2468 return !((src1 ^ src2) & src2);
2472 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2474 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2476 /* If DCB is not supported, only default TC is supported */
2477 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2478 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2482 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2483 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2484 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2488 return I40E_SUCCESS;
2492 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2493 struct i40e_vsi_vlan_pvid_info *info)
2496 struct i40e_vsi_context ctxt;
2497 uint8_t vlan_flags = 0;
2500 if (vsi == NULL || info == NULL) {
2501 PMD_DRV_LOG(ERR, "invalid parameters");
2502 return I40E_ERR_PARAM;
2506 vsi->info.pvid = info->config.pvid;
2508 * If insert pvid is enabled, only tagged pkts are
2509 * allowed to be sent out.
2511 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2512 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2515 if (info->config.reject.tagged == 0)
2516 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2518 if (info->config.reject.untagged == 0)
2519 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2521 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2522 I40E_AQ_VSI_PVLAN_MODE_MASK);
2523 vsi->info.port_vlan_flags |= vlan_flags;
2524 vsi->info.valid_sections =
2525 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2526 memset(&ctxt, 0, sizeof(ctxt));
2527 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2528 ctxt.seid = vsi->seid;
2530 hw = I40E_VSI_TO_HW(vsi);
2531 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2532 if (ret != I40E_SUCCESS)
2533 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2539 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2541 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2543 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2545 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2546 if (ret != I40E_SUCCESS)
2550 PMD_DRV_LOG(ERR, "seid not valid");
2554 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2555 tc_bw_data.tc_valid_bits = enabled_tcmap;
2556 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2557 tc_bw_data.tc_bw_credits[i] =
2558 (enabled_tcmap & (1 << i)) ? 1 : 0;
2560 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2561 if (ret != I40E_SUCCESS) {
2562 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2566 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2567 sizeof(vsi->info.qs_handle));
2568 return I40E_SUCCESS;
2572 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2573 struct i40e_aqc_vsi_properties_data *info,
2574 uint8_t enabled_tcmap)
2576 int ret, total_tc = 0, i;
2577 uint16_t qpnum_per_tc, bsf, qp_idx;
2579 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2580 if (ret != I40E_SUCCESS)
2583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2584 if (enabled_tcmap & (1 << i))
2586 vsi->enabled_tc = enabled_tcmap;
2588 /* Number of queues per enabled TC */
2589 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2590 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2591 bsf = rte_bsf32(qpnum_per_tc);
2593 /* Adjust the queue number to actual queues that can be applied */
2594 vsi->nb_qps = qpnum_per_tc * total_tc;
2597 * Configure TC and queue mapping parameters, for enabled TC,
2598 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2599 * default queue will serve it.
2602 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2603 if (vsi->enabled_tc & (1 << i)) {
2604 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2605 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2606 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2607 qp_idx += qpnum_per_tc;
2609 info->tc_mapping[i] = 0;
2612 /* Associate queue number with VSI */
2613 if (vsi->type == I40E_VSI_SRIOV) {
2614 info->mapping_flags |=
2615 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2616 for (i = 0; i < vsi->nb_qps; i++)
2617 info->queue_mapping[i] =
2618 rte_cpu_to_le_16(vsi->base_queue + i);
2620 info->mapping_flags |=
2621 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2622 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2624 info->valid_sections =
2625 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2627 return I40E_SUCCESS;
2631 i40e_veb_release(struct i40e_veb *veb)
2633 struct i40e_vsi *vsi;
2636 if (veb == NULL || veb->associate_vsi == NULL)
2639 if (!TAILQ_EMPTY(&veb->head)) {
2640 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2644 vsi = veb->associate_vsi;
2645 hw = I40E_VSI_TO_HW(vsi);
2647 vsi->uplink_seid = veb->uplink_seid;
2648 i40e_aq_delete_element(hw, veb->seid, NULL);
2651 return I40E_SUCCESS;
2655 static struct i40e_veb *
2656 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2658 struct i40e_veb *veb;
2662 if (NULL == pf || vsi == NULL) {
2663 PMD_DRV_LOG(ERR, "veb setup failed, "
2664 "associated VSI shouldn't null");
2667 hw = I40E_PF_TO_HW(pf);
2669 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2671 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2675 veb->associate_vsi = vsi;
2676 TAILQ_INIT(&veb->head);
2677 veb->uplink_seid = vsi->uplink_seid;
2679 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2680 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2682 if (ret != I40E_SUCCESS) {
2683 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2684 hw->aq.asq_last_status);
2688 /* get statistics index */
2689 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2690 &veb->stats_idx, NULL, NULL, NULL);
2691 if (ret != I40E_SUCCESS) {
2692 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2693 hw->aq.asq_last_status);
2697 /* Get VEB bandwidth, to be implemented */
2698 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2699 vsi->uplink_seid = veb->seid;
2708 i40e_vsi_release(struct i40e_vsi *vsi)
2712 struct i40e_vsi_list *vsi_list;
2714 struct i40e_mac_filter *f;
2717 return I40E_SUCCESS;
2719 pf = I40E_VSI_TO_PF(vsi);
2720 hw = I40E_VSI_TO_HW(vsi);
2722 /* VSI has child to attach, release child first */
2724 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2725 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2727 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2729 i40e_veb_release(vsi->veb);
2732 /* Remove all macvlan filters of the VSI */
2733 i40e_vsi_remove_all_macvlan_filter(vsi);
2734 TAILQ_FOREACH(f, &vsi->mac_list, next)
2737 if (vsi->type != I40E_VSI_MAIN) {
2738 /* Remove vsi from parent's sibling list */
2739 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2740 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2741 return I40E_ERR_PARAM;
2743 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2744 &vsi->sib_vsi_list, list);
2746 /* Remove all switch element of the VSI */
2747 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2748 if (ret != I40E_SUCCESS)
2749 PMD_DRV_LOG(ERR, "Failed to delete element");
2751 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2753 if (vsi->type != I40E_VSI_SRIOV)
2754 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2757 return I40E_SUCCESS;
2761 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2763 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2764 struct i40e_aqc_remove_macvlan_element_data def_filter;
2765 struct i40e_mac_filter_info filter;
2768 if (vsi->type != I40E_VSI_MAIN)
2769 return I40E_ERR_CONFIG;
2770 memset(&def_filter, 0, sizeof(def_filter));
2771 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2773 def_filter.vlan_tag = 0;
2774 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2775 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2776 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2777 if (ret != I40E_SUCCESS) {
2778 struct i40e_mac_filter *f;
2779 struct ether_addr *mac;
2781 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2783 /* It needs to add the permanent mac into mac list */
2784 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2786 PMD_DRV_LOG(ERR, "failed to allocate memory");
2787 return I40E_ERR_NO_MEMORY;
2789 mac = &f->mac_info.mac_addr;
2790 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2792 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2793 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2798 (void)rte_memcpy(&filter.mac_addr,
2799 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2800 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2801 return i40e_vsi_add_mac(vsi, &filter);
2805 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2807 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2808 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2809 struct i40e_hw *hw = &vsi->adapter->hw;
2813 memset(&bw_config, 0, sizeof(bw_config));
2814 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2815 if (ret != I40E_SUCCESS) {
2816 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2817 hw->aq.asq_last_status);
2821 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2822 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2823 &ets_sla_config, NULL);
2824 if (ret != I40E_SUCCESS) {
2825 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2826 "configuration %u", hw->aq.asq_last_status);
2830 /* Not store the info yet, just print out */
2831 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2832 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2833 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2834 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2835 ets_sla_config.share_credits[i]);
2836 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2837 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2838 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2839 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2848 i40e_vsi_setup(struct i40e_pf *pf,
2849 enum i40e_vsi_type type,
2850 struct i40e_vsi *uplink_vsi,
2851 uint16_t user_param)
2853 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2854 struct i40e_vsi *vsi;
2855 struct i40e_mac_filter_info filter;
2857 struct i40e_vsi_context ctxt;
2858 struct ether_addr broadcast =
2859 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2861 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2862 PMD_DRV_LOG(ERR, "VSI setup failed, "
2863 "VSI link shouldn't be NULL");
2867 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2868 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2869 "uplink VSI should be NULL");
2873 /* If uplink vsi didn't setup VEB, create one first */
2874 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2875 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2877 if (NULL == uplink_vsi->veb) {
2878 PMD_DRV_LOG(ERR, "VEB setup failed");
2883 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2885 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2888 TAILQ_INIT(&vsi->mac_list);
2890 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2891 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2892 vsi->parent_vsi = uplink_vsi;
2893 vsi->user_param = user_param;
2894 /* Allocate queues */
2895 switch (vsi->type) {
2896 case I40E_VSI_MAIN :
2897 vsi->nb_qps = pf->lan_nb_qps;
2899 case I40E_VSI_SRIOV :
2900 vsi->nb_qps = pf->vf_nb_qps;
2902 case I40E_VSI_VMDQ2:
2903 vsi->nb_qps = pf->vmdq_nb_qps;
2906 vsi->nb_qps = pf->fdir_nb_qps;
2912 * The filter status descriptor is reported in rx queue 0,
2913 * while the tx queue for fdir filter programming has no
2914 * such constraints, can be non-zero queues.
2915 * To simplify it, choose FDIR vsi use queue 0 pair.
2916 * To make sure it will use queue 0 pair, queue allocation
2917 * need be done before this function is called
2919 if (type != I40E_VSI_FDIR) {
2920 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2922 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2926 vsi->base_queue = ret;
2928 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2930 /* VF has MSIX interrupt in VF range, don't allocate here */
2931 if (type != I40E_VSI_SRIOV) {
2932 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2934 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2935 goto fail_queue_alloc;
2937 vsi->msix_intr = ret;
2941 if (type == I40E_VSI_MAIN) {
2942 /* For main VSI, no need to add since it's default one */
2943 vsi->uplink_seid = pf->mac_seid;
2944 vsi->seid = pf->main_vsi_seid;
2945 /* Bind queues with specific MSIX interrupt */
2947 * Needs 2 interrupt at least, one for misc cause which will
2948 * enabled from OS side, Another for queues binding the
2949 * interrupt from device side only.
2952 /* Get default VSI parameters from hardware */
2953 memset(&ctxt, 0, sizeof(ctxt));
2954 ctxt.seid = vsi->seid;
2955 ctxt.pf_num = hw->pf_id;
2956 ctxt.uplink_seid = vsi->uplink_seid;
2958 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2959 if (ret != I40E_SUCCESS) {
2960 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2961 goto fail_msix_alloc;
2963 (void)rte_memcpy(&vsi->info, &ctxt.info,
2964 sizeof(struct i40e_aqc_vsi_properties_data));
2965 vsi->vsi_id = ctxt.vsi_number;
2966 vsi->info.valid_sections = 0;
2968 /* Configure tc, enabled TC0 only */
2969 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2971 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2972 goto fail_msix_alloc;
2975 /* TC, queue mapping */
2976 memset(&ctxt, 0, sizeof(ctxt));
2977 vsi->info.valid_sections |=
2978 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2979 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2980 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2981 (void)rte_memcpy(&ctxt.info, &vsi->info,
2982 sizeof(struct i40e_aqc_vsi_properties_data));
2983 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2984 I40E_DEFAULT_TCMAP);
2985 if (ret != I40E_SUCCESS) {
2986 PMD_DRV_LOG(ERR, "Failed to configure "
2987 "TC queue mapping");
2988 goto fail_msix_alloc;
2990 ctxt.seid = vsi->seid;
2991 ctxt.pf_num = hw->pf_id;
2992 ctxt.uplink_seid = vsi->uplink_seid;
2995 /* Update VSI parameters */
2996 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2997 if (ret != I40E_SUCCESS) {
2998 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2999 goto fail_msix_alloc;
3002 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3003 sizeof(vsi->info.tc_mapping));
3004 (void)rte_memcpy(&vsi->info.queue_mapping,
3005 &ctxt.info.queue_mapping,
3006 sizeof(vsi->info.queue_mapping));
3007 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3008 vsi->info.valid_sections = 0;
3010 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3014 * Updating default filter settings are necessary to prevent
3015 * reception of tagged packets.
3016 * Some old firmware configurations load a default macvlan
3017 * filter which accepts both tagged and untagged packets.
3018 * The updating is to use a normal filter instead if needed.
3019 * For NVM 4.2.2 or after, the updating is not needed anymore.
3020 * The firmware with correct configurations load the default
3021 * macvlan filter which is expected and cannot be removed.
3023 i40e_update_default_filter_setting(vsi);
3024 } else if (type == I40E_VSI_SRIOV) {
3025 memset(&ctxt, 0, sizeof(ctxt));
3027 * For other VSI, the uplink_seid equals to uplink VSI's
3028 * uplink_seid since they share same VEB
3030 vsi->uplink_seid = uplink_vsi->uplink_seid;
3031 ctxt.pf_num = hw->pf_id;
3032 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3033 ctxt.uplink_seid = vsi->uplink_seid;
3034 ctxt.connection_type = 0x1;
3035 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3037 /* Configure switch ID */
3038 ctxt.info.valid_sections |=
3039 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3040 ctxt.info.switch_id =
3041 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3042 /* Configure port/vlan */
3043 ctxt.info.valid_sections |=
3044 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3045 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3046 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3047 I40E_DEFAULT_TCMAP);
3048 if (ret != I40E_SUCCESS) {
3049 PMD_DRV_LOG(ERR, "Failed to configure "
3050 "TC queue mapping");
3051 goto fail_msix_alloc;
3053 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3054 ctxt.info.valid_sections |=
3055 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3057 * Since VSI is not created yet, only configure parameter,
3058 * will add vsi below.
3060 } else if (type == I40E_VSI_VMDQ2) {
3061 memset(&ctxt, 0, sizeof(ctxt));
3063 * For other VSI, the uplink_seid equals to uplink VSI's
3064 * uplink_seid since they share same VEB
3066 vsi->uplink_seid = uplink_vsi->uplink_seid;
3067 ctxt.pf_num = hw->pf_id;
3069 ctxt.uplink_seid = vsi->uplink_seid;
3070 ctxt.connection_type = 0x1;
3071 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3073 ctxt.info.valid_sections |=
3074 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3075 /* user_param carries flag to enable loop back */
3077 ctxt.info.switch_id =
3078 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3079 ctxt.info.switch_id |=
3080 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3083 /* Configure port/vlan */
3084 ctxt.info.valid_sections |=
3085 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3086 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3087 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3088 I40E_DEFAULT_TCMAP);
3089 if (ret != I40E_SUCCESS) {
3090 PMD_DRV_LOG(ERR, "Failed to configure "
3091 "TC queue mapping");
3092 goto fail_msix_alloc;
3094 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3095 ctxt.info.valid_sections |=
3096 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3097 } else if (type == I40E_VSI_FDIR) {
3098 vsi->uplink_seid = uplink_vsi->uplink_seid;
3099 ctxt.pf_num = hw->pf_id;
3101 ctxt.uplink_seid = vsi->uplink_seid;
3102 ctxt.connection_type = 0x1; /* regular data port */
3103 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3104 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3105 I40E_DEFAULT_TCMAP);
3106 if (ret != I40E_SUCCESS) {
3107 PMD_DRV_LOG(ERR, "Failed to configure "
3108 "TC queue mapping.");
3109 goto fail_msix_alloc;
3111 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3112 ctxt.info.valid_sections |=
3113 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3115 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3116 goto fail_msix_alloc;
3119 if (vsi->type != I40E_VSI_MAIN) {
3120 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3122 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3123 hw->aq.asq_last_status);
3124 goto fail_msix_alloc;
3126 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3127 vsi->info.valid_sections = 0;
3128 vsi->seid = ctxt.seid;
3129 vsi->vsi_id = ctxt.vsi_number;
3130 vsi->sib_vsi_list.vsi = vsi;
3131 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3132 &vsi->sib_vsi_list, list);
3135 /* MAC/VLAN configuration */
3136 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3137 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3139 ret = i40e_vsi_add_mac(vsi, &filter);
3140 if (ret != I40E_SUCCESS) {
3141 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3142 goto fail_msix_alloc;
3145 /* Get VSI BW information */
3146 i40e_vsi_dump_bw_config(vsi);
3149 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3151 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3157 /* Configure vlan stripping on or off */
3159 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3161 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3162 struct i40e_vsi_context ctxt;
3164 int ret = I40E_SUCCESS;
3166 /* Check if it has been already on or off */
3167 if (vsi->info.valid_sections &
3168 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3170 if ((vsi->info.port_vlan_flags &
3171 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3172 return 0; /* already on */
3174 if ((vsi->info.port_vlan_flags &
3175 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3176 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3177 return 0; /* already off */
3182 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3184 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3185 vsi->info.valid_sections =
3186 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3187 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3188 vsi->info.port_vlan_flags |= vlan_flags;
3189 ctxt.seid = vsi->seid;
3190 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3191 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3193 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3194 on ? "enable" : "disable");
3200 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3202 struct rte_eth_dev_data *data = dev->data;
3205 /* Apply vlan offload setting */
3206 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3208 /* Apply double-vlan setting, not implemented yet */
3210 /* Apply pvid setting */
3211 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3212 data->dev_conf.txmode.hw_vlan_insert_pvid);
3214 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3220 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3222 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3224 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3228 i40e_update_flow_control(struct i40e_hw *hw)
3230 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3231 struct i40e_link_status link_status;
3232 uint32_t rxfc = 0, txfc = 0, reg;
3236 memset(&link_status, 0, sizeof(link_status));
3237 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3238 if (ret != I40E_SUCCESS) {
3239 PMD_DRV_LOG(ERR, "Failed to get link status information");
3240 goto write_reg; /* Disable flow control */
3243 an_info = hw->phy.link_info.an_info;
3244 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3245 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3246 ret = I40E_ERR_NOT_READY;
3247 goto write_reg; /* Disable flow control */
3250 * If link auto negotiation is enabled, flow control needs to
3251 * be configured according to it
3253 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3254 case I40E_LINK_PAUSE_RXTX:
3257 hw->fc.current_mode = I40E_FC_FULL;
3259 case I40E_AQ_LINK_PAUSE_RX:
3261 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3263 case I40E_AQ_LINK_PAUSE_TX:
3265 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3268 hw->fc.current_mode = I40E_FC_NONE;
3273 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3274 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3275 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3276 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3277 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3278 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3285 i40e_pf_setup(struct i40e_pf *pf)
3287 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3288 struct i40e_filter_control_settings settings;
3289 struct i40e_vsi *vsi;
3292 /* Clear all stats counters */
3293 pf->offset_loaded = FALSE;
3294 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3295 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3297 ret = i40e_pf_get_switch_config(pf);
3298 if (ret != I40E_SUCCESS) {
3299 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3302 if (pf->flags & I40E_FLAG_FDIR) {
3303 /* make queue allocated first, let FDIR use queue pair 0*/
3304 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3305 if (ret != I40E_FDIR_QUEUE_ID) {
3306 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3308 pf->flags &= ~I40E_FLAG_FDIR;
3311 /* main VSI setup */
3312 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3314 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3315 return I40E_ERR_NOT_READY;
3319 /* Configure filter control */
3320 memset(&settings, 0, sizeof(settings));
3321 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3322 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3323 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3324 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3326 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3327 hw->func_caps.rss_table_size);
3328 return I40E_ERR_PARAM;
3330 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3331 "size: %u\n", hw->func_caps.rss_table_size);
3332 pf->hash_lut_size = hw->func_caps.rss_table_size;
3334 /* Enable ethtype and macvlan filters */
3335 settings.enable_ethtype = TRUE;
3336 settings.enable_macvlan = TRUE;
3337 ret = i40e_set_filter_control(hw, &settings);
3339 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3342 /* Update flow control according to the auto negotiation */
3343 i40e_update_flow_control(hw);
3345 return I40E_SUCCESS;
3349 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3355 * Set or clear TX Queue Disable flags,
3356 * which is required by hardware.
3358 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3359 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3361 /* Wait until the request is finished */
3362 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3363 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3364 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3365 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3366 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3372 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3373 return I40E_SUCCESS; /* already on, skip next steps */
3375 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3376 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3378 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3379 return I40E_SUCCESS; /* already off, skip next steps */
3380 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3382 /* Write the register */
3383 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3384 /* Check the result */
3385 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3386 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3387 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3389 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3390 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3393 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3394 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3398 /* Check if it is timeout */
3399 if (j >= I40E_CHK_Q_ENA_COUNT) {
3400 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3401 (on ? "enable" : "disable"), q_idx);
3402 return I40E_ERR_TIMEOUT;
3405 return I40E_SUCCESS;
3408 /* Swith on or off the tx queues */
3410 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3412 struct rte_eth_dev_data *dev_data = pf->dev_data;
3413 struct i40e_tx_queue *txq;
3414 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3418 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3419 txq = dev_data->tx_queues[i];
3420 /* Don't operate the queue if not configured or
3421 * if starting only per queue */
3422 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3425 ret = i40e_dev_tx_queue_start(dev, i);
3427 ret = i40e_dev_tx_queue_stop(dev, i);
3428 if ( ret != I40E_SUCCESS)
3432 return I40E_SUCCESS;
3436 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3441 /* Wait until the request is finished */
3442 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3443 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3444 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3445 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3446 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3451 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3452 return I40E_SUCCESS; /* Already on, skip next steps */
3453 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3455 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3456 return I40E_SUCCESS; /* Already off, skip next steps */
3457 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3460 /* Write the register */
3461 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3462 /* Check the result */
3463 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3464 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3465 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3467 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3468 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3471 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3472 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3477 /* Check if it is timeout */
3478 if (j >= I40E_CHK_Q_ENA_COUNT) {
3479 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3480 (on ? "enable" : "disable"), q_idx);
3481 return I40E_ERR_TIMEOUT;
3484 return I40E_SUCCESS;
3486 /* Switch on or off the rx queues */
3488 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3490 struct rte_eth_dev_data *dev_data = pf->dev_data;
3491 struct i40e_rx_queue *rxq;
3492 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3496 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3497 rxq = dev_data->rx_queues[i];
3498 /* Don't operate the queue if not configured or
3499 * if starting only per queue */
3500 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3503 ret = i40e_dev_rx_queue_start(dev, i);
3505 ret = i40e_dev_rx_queue_stop(dev, i);
3506 if (ret != I40E_SUCCESS)
3510 return I40E_SUCCESS;
3513 /* Switch on or off all the rx/tx queues */
3515 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3520 /* enable rx queues before enabling tx queues */
3521 ret = i40e_dev_switch_rx_queues(pf, on);
3523 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3526 ret = i40e_dev_switch_tx_queues(pf, on);
3528 /* Stop tx queues before stopping rx queues */
3529 ret = i40e_dev_switch_tx_queues(pf, on);
3531 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3534 ret = i40e_dev_switch_rx_queues(pf, on);
3540 /* Initialize VSI for TX */
3542 i40e_dev_tx_init(struct i40e_pf *pf)
3544 struct rte_eth_dev_data *data = pf->dev_data;
3546 uint32_t ret = I40E_SUCCESS;
3547 struct i40e_tx_queue *txq;
3549 for (i = 0; i < data->nb_tx_queues; i++) {
3550 txq = data->tx_queues[i];
3551 if (!txq || !txq->q_set)
3553 ret = i40e_tx_queue_init(txq);
3554 if (ret != I40E_SUCCESS)
3561 /* Initialize VSI for RX */
3563 i40e_dev_rx_init(struct i40e_pf *pf)
3565 struct rte_eth_dev_data *data = pf->dev_data;
3566 int ret = I40E_SUCCESS;
3568 struct i40e_rx_queue *rxq;
3570 i40e_pf_config_mq_rx(pf);
3571 for (i = 0; i < data->nb_rx_queues; i++) {
3572 rxq = data->rx_queues[i];
3573 if (!rxq || !rxq->q_set)
3576 ret = i40e_rx_queue_init(rxq);
3577 if (ret != I40E_SUCCESS) {
3578 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3588 i40e_dev_rxtx_init(struct i40e_pf *pf)
3592 err = i40e_dev_tx_init(pf);
3594 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3597 err = i40e_dev_rx_init(pf);
3599 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3607 i40e_vmdq_setup(struct rte_eth_dev *dev)
3609 struct rte_eth_conf *conf = &dev->data->dev_conf;
3610 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3611 int i, err, conf_vsis, j, loop;
3612 struct i40e_vsi *vsi;
3613 struct i40e_vmdq_info *vmdq_info;
3614 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3615 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3618 * Disable interrupt to avoid message from VF. Furthermore, it will
3619 * avoid race condition in VSI creation/destroy.
3621 i40e_pf_disable_irq0(hw);
3623 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3624 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3628 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3629 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3630 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3631 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3632 pf->max_nb_vmdq_vsi);
3636 if (pf->vmdq != NULL) {
3637 PMD_INIT_LOG(INFO, "VMDQ already configured");
3641 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3642 sizeof(*vmdq_info) * conf_vsis, 0);
3644 if (pf->vmdq == NULL) {
3645 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3649 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3651 /* Create VMDQ VSI */
3652 for (i = 0; i < conf_vsis; i++) {
3653 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3654 vmdq_conf->enable_loop_back);
3656 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3660 vmdq_info = &pf->vmdq[i];
3662 vmdq_info->vsi = vsi;
3664 pf->nb_cfg_vmdq_vsi = conf_vsis;
3666 /* Configure Vlan */
3667 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3668 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3669 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3670 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3671 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3672 vmdq_conf->pool_map[i].vlan_id, j);
3674 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3675 vmdq_conf->pool_map[i].vlan_id);
3677 PMD_INIT_LOG(ERR, "Failed to add vlan");
3685 i40e_pf_enable_irq0(hw);
3690 for (i = 0; i < conf_vsis; i++)
3691 if (pf->vmdq[i].vsi == NULL)
3694 i40e_vsi_release(pf->vmdq[i].vsi);
3698 i40e_pf_enable_irq0(hw);
3703 i40e_stat_update_32(struct i40e_hw *hw,
3711 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3715 if (new_data >= *offset)
3716 *stat = (uint64_t)(new_data - *offset);
3718 *stat = (uint64_t)((new_data +
3719 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3723 i40e_stat_update_48(struct i40e_hw *hw,
3732 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3733 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3734 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3739 if (new_data >= *offset)
3740 *stat = new_data - *offset;
3742 *stat = (uint64_t)((new_data +
3743 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3745 *stat &= I40E_48_BIT_MASK;
3750 i40e_pf_disable_irq0(struct i40e_hw *hw)
3752 /* Disable all interrupt types */
3753 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3754 I40E_WRITE_FLUSH(hw);
3759 i40e_pf_enable_irq0(struct i40e_hw *hw)
3761 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3762 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3763 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3764 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3765 I40E_WRITE_FLUSH(hw);
3769 i40e_pf_config_irq0(struct i40e_hw *hw)
3771 /* read pending request and disable first */
3772 i40e_pf_disable_irq0(hw);
3773 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3774 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3775 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3777 /* Link no queues with irq0 */
3778 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3779 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3783 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3785 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3789 uint32_t index, offset, val;
3794 * Try to find which VF trigger a reset, use absolute VF id to access
3795 * since the reg is global register.
3797 for (i = 0; i < pf->vf_num; i++) {
3798 abs_vf_id = hw->func_caps.vf_base_id + i;
3799 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3800 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3801 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3802 /* VFR event occured */
3803 if (val & (0x1 << offset)) {
3806 /* Clear the event first */
3807 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3809 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3811 * Only notify a VF reset event occured,
3812 * don't trigger another SW reset
3814 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3815 if (ret != I40E_SUCCESS)
3816 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3822 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825 struct i40e_arq_event_info info;
3826 uint16_t pending, opcode;
3829 info.buf_len = I40E_AQ_BUF_SZ;
3830 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3831 if (!info.msg_buf) {
3832 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3838 ret = i40e_clean_arq_element(hw, &info, &pending);
3840 if (ret != I40E_SUCCESS) {
3841 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3842 "aq_err: %u", hw->aq.asq_last_status);
3845 opcode = rte_le_to_cpu_16(info.desc.opcode);
3848 case i40e_aqc_opc_send_msg_to_pf:
3849 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3850 i40e_pf_host_handle_vf_msg(dev,
3851 rte_le_to_cpu_16(info.desc.retval),
3852 rte_le_to_cpu_32(info.desc.cookie_high),
3853 rte_le_to_cpu_32(info.desc.cookie_low),
3858 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3863 rte_free(info.msg_buf);
3867 * Interrupt handler is registered as the alarm callback for handling LSC
3868 * interrupt in a definite of time, in order to wait the NIC into a stable
3869 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3870 * no need for link down interrupt.
3873 i40e_dev_interrupt_delayed_handler(void *param)
3875 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3876 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879 /* read interrupt causes again */
3880 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3882 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3883 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3884 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3885 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3886 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3887 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3888 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3889 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3890 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3891 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3892 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3894 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3895 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3896 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3897 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3898 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3900 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3901 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3902 i40e_dev_handle_vfr_event(dev);
3904 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3905 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3906 i40e_dev_handle_aq_msg(dev);
3909 /* handle the link up interrupt in an alarm callback */
3910 i40e_dev_link_update(dev, 0);
3911 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3913 i40e_pf_enable_irq0(hw);
3914 rte_intr_enable(&(dev->pci_dev->intr_handle));
3918 * Interrupt handler triggered by NIC for handling
3919 * specific interrupt.
3922 * Pointer to interrupt handle.
3924 * The address of parameter (struct rte_eth_dev *) regsitered before.
3930 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3933 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937 /* Disable interrupt */
3938 i40e_pf_disable_irq0(hw);
3940 /* read out interrupt causes */
3941 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3943 /* No interrupt event indicated */
3944 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3945 PMD_DRV_LOG(INFO, "No interrupt event");
3948 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3949 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3950 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3951 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3952 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3953 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3954 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3955 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3956 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3957 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3958 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3959 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3960 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3961 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3962 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3963 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3965 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3966 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3967 i40e_dev_handle_vfr_event(dev);
3969 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3970 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3971 i40e_dev_handle_aq_msg(dev);
3974 /* Link Status Change interrupt */
3975 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3976 #define I40E_US_PER_SECOND 1000000
3977 struct rte_eth_link link;
3979 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3980 memset(&link, 0, sizeof(link));
3981 rte_i40e_dev_atomic_read_link_status(dev, &link);
3982 i40e_dev_link_update(dev, 0);
3985 * For link up interrupt, it needs to wait 1 second to let the
3986 * hardware be a stable state. Otherwise several consecutive
3987 * interrupts can be observed.
3988 * For link down interrupt, no need to wait.
3990 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3991 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3994 _rte_eth_dev_callback_process(dev,
3995 RTE_ETH_EVENT_INTR_LSC);
3999 /* Enable interrupt */
4000 i40e_pf_enable_irq0(hw);
4001 rte_intr_enable(&(dev->pci_dev->intr_handle));
4005 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4006 struct i40e_macvlan_filter *filter,
4009 int ele_num, ele_buff_size;
4010 int num, actual_num, i;
4012 int ret = I40E_SUCCESS;
4013 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4014 struct i40e_aqc_add_macvlan_element_data *req_list;
4016 if (filter == NULL || total == 0)
4017 return I40E_ERR_PARAM;
4018 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4019 ele_buff_size = hw->aq.asq_buf_size;
4021 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4022 if (req_list == NULL) {
4023 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4024 return I40E_ERR_NO_MEMORY;
4029 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4030 memset(req_list, 0, ele_buff_size);
4032 for (i = 0; i < actual_num; i++) {
4033 (void)rte_memcpy(req_list[i].mac_addr,
4034 &filter[num + i].macaddr, ETH_ADDR_LEN);
4035 req_list[i].vlan_tag =
4036 rte_cpu_to_le_16(filter[num + i].vlan_id);
4038 switch (filter[num + i].filter_type) {
4039 case RTE_MAC_PERFECT_MATCH:
4040 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4041 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4043 case RTE_MACVLAN_PERFECT_MATCH:
4044 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4046 case RTE_MAC_HASH_MATCH:
4047 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4048 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4050 case RTE_MACVLAN_HASH_MATCH:
4051 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4054 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4055 ret = I40E_ERR_PARAM;
4059 req_list[i].queue_number = 0;
4061 req_list[i].flags = rte_cpu_to_le_16(flags);
4064 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4066 if (ret != I40E_SUCCESS) {
4067 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4071 } while (num < total);
4079 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4080 struct i40e_macvlan_filter *filter,
4083 int ele_num, ele_buff_size;
4084 int num, actual_num, i;
4086 int ret = I40E_SUCCESS;
4087 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4088 struct i40e_aqc_remove_macvlan_element_data *req_list;
4090 if (filter == NULL || total == 0)
4091 return I40E_ERR_PARAM;
4093 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4094 ele_buff_size = hw->aq.asq_buf_size;
4096 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4097 if (req_list == NULL) {
4098 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4099 return I40E_ERR_NO_MEMORY;
4104 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4105 memset(req_list, 0, ele_buff_size);
4107 for (i = 0; i < actual_num; i++) {
4108 (void)rte_memcpy(req_list[i].mac_addr,
4109 &filter[num + i].macaddr, ETH_ADDR_LEN);
4110 req_list[i].vlan_tag =
4111 rte_cpu_to_le_16(filter[num + i].vlan_id);
4113 switch (filter[num + i].filter_type) {
4114 case RTE_MAC_PERFECT_MATCH:
4115 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4116 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4118 case RTE_MACVLAN_PERFECT_MATCH:
4119 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4121 case RTE_MAC_HASH_MATCH:
4122 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4123 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4125 case RTE_MACVLAN_HASH_MATCH:
4126 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4129 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4130 ret = I40E_ERR_PARAM;
4133 req_list[i].flags = rte_cpu_to_le_16(flags);
4136 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4138 if (ret != I40E_SUCCESS) {
4139 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4143 } while (num < total);
4150 /* Find out specific MAC filter */
4151 static struct i40e_mac_filter *
4152 i40e_find_mac_filter(struct i40e_vsi *vsi,
4153 struct ether_addr *macaddr)
4155 struct i40e_mac_filter *f;
4157 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4158 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4166 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4169 uint32_t vid_idx, vid_bit;
4171 if (vlan_id > ETH_VLAN_ID_MAX)
4174 vid_idx = I40E_VFTA_IDX(vlan_id);
4175 vid_bit = I40E_VFTA_BIT(vlan_id);
4177 if (vsi->vfta[vid_idx] & vid_bit)
4184 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4185 uint16_t vlan_id, bool on)
4187 uint32_t vid_idx, vid_bit;
4189 if (vlan_id > ETH_VLAN_ID_MAX)
4192 vid_idx = I40E_VFTA_IDX(vlan_id);
4193 vid_bit = I40E_VFTA_BIT(vlan_id);
4196 vsi->vfta[vid_idx] |= vid_bit;
4198 vsi->vfta[vid_idx] &= ~vid_bit;
4202 * Find all vlan options for specific mac addr,
4203 * return with actual vlan found.
4206 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4207 struct i40e_macvlan_filter *mv_f,
4208 int num, struct ether_addr *addr)
4214 * Not to use i40e_find_vlan_filter to decrease the loop time,
4215 * although the code looks complex.
4217 if (num < vsi->vlan_num)
4218 return I40E_ERR_PARAM;
4221 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4223 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4224 if (vsi->vfta[j] & (1 << k)) {
4226 PMD_DRV_LOG(ERR, "vlan number "
4228 return I40E_ERR_PARAM;
4230 (void)rte_memcpy(&mv_f[i].macaddr,
4231 addr, ETH_ADDR_LEN);
4233 j * I40E_UINT32_BIT_SIZE + k;
4239 return I40E_SUCCESS;
4243 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4244 struct i40e_macvlan_filter *mv_f,
4249 struct i40e_mac_filter *f;
4251 if (num < vsi->mac_num)
4252 return I40E_ERR_PARAM;
4254 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4256 PMD_DRV_LOG(ERR, "buffer number not match");
4257 return I40E_ERR_PARAM;
4259 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4261 mv_f[i].vlan_id = vlan;
4262 mv_f[i].filter_type = f->mac_info.filter_type;
4266 return I40E_SUCCESS;
4270 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4273 struct i40e_mac_filter *f;
4274 struct i40e_macvlan_filter *mv_f;
4275 int ret = I40E_SUCCESS;
4277 if (vsi == NULL || vsi->mac_num == 0)
4278 return I40E_ERR_PARAM;
4280 /* Case that no vlan is set */
4281 if (vsi->vlan_num == 0)
4284 num = vsi->mac_num * vsi->vlan_num;
4286 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4288 PMD_DRV_LOG(ERR, "failed to allocate memory");
4289 return I40E_ERR_NO_MEMORY;
4293 if (vsi->vlan_num == 0) {
4294 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4295 (void)rte_memcpy(&mv_f[i].macaddr,
4296 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4297 mv_f[i].vlan_id = 0;
4301 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4302 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4303 vsi->vlan_num, &f->mac_info.mac_addr);
4304 if (ret != I40E_SUCCESS)
4310 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4318 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4320 struct i40e_macvlan_filter *mv_f;
4322 int ret = I40E_SUCCESS;
4324 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4325 return I40E_ERR_PARAM;
4327 /* If it's already set, just return */
4328 if (i40e_find_vlan_filter(vsi,vlan))
4329 return I40E_SUCCESS;
4331 mac_num = vsi->mac_num;
4334 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4335 return I40E_ERR_PARAM;
4338 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4341 PMD_DRV_LOG(ERR, "failed to allocate memory");
4342 return I40E_ERR_NO_MEMORY;
4345 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4347 if (ret != I40E_SUCCESS)
4350 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4352 if (ret != I40E_SUCCESS)
4355 i40e_set_vlan_filter(vsi, vlan, 1);
4365 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4367 struct i40e_macvlan_filter *mv_f;
4369 int ret = I40E_SUCCESS;
4372 * Vlan 0 is the generic filter for untagged packets
4373 * and can't be removed.
4375 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4376 return I40E_ERR_PARAM;
4378 /* If can't find it, just return */
4379 if (!i40e_find_vlan_filter(vsi, vlan))
4380 return I40E_ERR_PARAM;
4382 mac_num = vsi->mac_num;
4385 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4386 return I40E_ERR_PARAM;
4389 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4392 PMD_DRV_LOG(ERR, "failed to allocate memory");
4393 return I40E_ERR_NO_MEMORY;
4396 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4398 if (ret != I40E_SUCCESS)
4401 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4403 if (ret != I40E_SUCCESS)
4406 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4407 if (vsi->vlan_num == 1) {
4408 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4409 if (ret != I40E_SUCCESS)
4412 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4413 if (ret != I40E_SUCCESS)
4417 i40e_set_vlan_filter(vsi, vlan, 0);
4427 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4429 struct i40e_mac_filter *f;
4430 struct i40e_macvlan_filter *mv_f;
4431 int i, vlan_num = 0;
4432 int ret = I40E_SUCCESS;
4434 /* If it's add and we've config it, return */
4435 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4437 return I40E_SUCCESS;
4438 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4439 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4442 * If vlan_num is 0, that's the first time to add mac,
4443 * set mask for vlan_id 0.
4445 if (vsi->vlan_num == 0) {
4446 i40e_set_vlan_filter(vsi, 0, 1);
4449 vlan_num = vsi->vlan_num;
4450 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4451 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4454 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4456 PMD_DRV_LOG(ERR, "failed to allocate memory");
4457 return I40E_ERR_NO_MEMORY;
4460 for (i = 0; i < vlan_num; i++) {
4461 mv_f[i].filter_type = mac_filter->filter_type;
4462 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4466 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4467 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4468 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4469 &mac_filter->mac_addr);
4470 if (ret != I40E_SUCCESS)
4474 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4475 if (ret != I40E_SUCCESS)
4478 /* Add the mac addr into mac list */
4479 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4481 PMD_DRV_LOG(ERR, "failed to allocate memory");
4482 ret = I40E_ERR_NO_MEMORY;
4485 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4487 f->mac_info.filter_type = mac_filter->filter_type;
4488 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4499 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4501 struct i40e_mac_filter *f;
4502 struct i40e_macvlan_filter *mv_f;
4504 enum rte_mac_filter_type filter_type;
4505 int ret = I40E_SUCCESS;
4507 /* Can't find it, return an error */
4508 f = i40e_find_mac_filter(vsi, addr);
4510 return I40E_ERR_PARAM;
4512 vlan_num = vsi->vlan_num;
4513 filter_type = f->mac_info.filter_type;
4514 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4515 filter_type == RTE_MACVLAN_HASH_MATCH) {
4516 if (vlan_num == 0) {
4517 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4518 return I40E_ERR_PARAM;
4520 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4521 filter_type == RTE_MAC_HASH_MATCH)
4524 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4526 PMD_DRV_LOG(ERR, "failed to allocate memory");
4527 return I40E_ERR_NO_MEMORY;
4530 for (i = 0; i < vlan_num; i++) {
4531 mv_f[i].filter_type = filter_type;
4532 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4535 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4536 filter_type == RTE_MACVLAN_HASH_MATCH) {
4537 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4538 if (ret != I40E_SUCCESS)
4542 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4543 if (ret != I40E_SUCCESS)
4546 /* Remove the mac addr into mac list */
4547 TAILQ_REMOVE(&vsi->mac_list, f, next);
4557 /* Configure hash enable flags for RSS */
4559 i40e_config_hena(uint64_t flags)
4566 if (flags & ETH_RSS_NONF_IPV4_UDP)
4567 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4568 if (flags & ETH_RSS_NONF_IPV4_TCP)
4569 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4570 if (flags & ETH_RSS_NONF_IPV4_SCTP)
4571 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4572 if (flags & ETH_RSS_NONF_IPV4_OTHER)
4573 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4574 if (flags & ETH_RSS_FRAG_IPV4)
4575 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4576 if (flags & ETH_RSS_NONF_IPV6_UDP)
4577 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4578 if (flags & ETH_RSS_NONF_IPV6_TCP)
4579 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4580 if (flags & ETH_RSS_NONF_IPV6_SCTP)
4581 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4582 if (flags & ETH_RSS_NONF_IPV6_OTHER)
4583 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4584 if (flags & ETH_RSS_FRAG_IPV6)
4585 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4586 if (flags & ETH_RSS_L2_PAYLOAD)
4587 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4592 /* Parse the hash enable flags */
4594 i40e_parse_hena(uint64_t flags)
4596 uint64_t rss_hf = 0;
4601 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4602 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4603 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4604 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4605 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4606 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4607 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4608 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4609 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4610 rss_hf |= ETH_RSS_FRAG_IPV4;
4611 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4612 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4613 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4614 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4615 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4616 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4617 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4618 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4619 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4620 rss_hf |= ETH_RSS_FRAG_IPV6;
4621 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4622 rss_hf |= ETH_RSS_L2_PAYLOAD;
4629 i40e_pf_disable_rss(struct i40e_pf *pf)
4631 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4634 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4635 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4636 hena &= ~I40E_RSS_HENA_ALL;
4637 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4638 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4639 I40E_WRITE_FLUSH(hw);
4643 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4646 uint8_t hash_key_len;
4651 hash_key = (uint32_t *)(rss_conf->rss_key);
4652 hash_key_len = rss_conf->rss_key_len;
4653 if (hash_key != NULL && hash_key_len >=
4654 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4655 /* Fill in RSS hash key */
4656 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4657 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4660 rss_hf = rss_conf->rss_hf;
4661 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4662 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4663 hena &= ~I40E_RSS_HENA_ALL;
4664 hena |= i40e_config_hena(rss_hf);
4665 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4666 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4667 I40E_WRITE_FLUSH(hw);
4673 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4674 struct rte_eth_rss_conf *rss_conf)
4676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4680 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4681 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4682 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4683 if (rss_hf != 0) /* Enable RSS */
4685 return 0; /* Nothing to do */
4688 if (rss_hf == 0) /* Disable RSS */
4691 return i40e_hw_rss_hash_set(hw, rss_conf);
4695 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4696 struct rte_eth_rss_conf *rss_conf)
4698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4703 if (hash_key != NULL) {
4704 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4705 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4706 rss_conf->rss_key_len = i * sizeof(uint32_t);
4708 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4709 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4710 rss_conf->rss_hf = i40e_parse_hena(hena);
4716 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4718 switch (filter_type) {
4719 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4720 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4722 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4723 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4725 case RTE_TUNNEL_FILTER_IMAC_TENID:
4726 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4728 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4729 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4731 case ETH_TUNNEL_FILTER_IMAC:
4732 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4735 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4743 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4744 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4748 uint8_t tun_type = 0;
4750 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4751 struct i40e_vsi *vsi = pf->main_vsi;
4752 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4753 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4755 cld_filter = rte_zmalloc("tunnel_filter",
4756 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4759 if (NULL == cld_filter) {
4760 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4763 pfilter = cld_filter;
4765 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4766 sizeof(struct ether_addr));
4767 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4768 sizeof(struct ether_addr));
4770 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4771 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4772 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4773 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4774 &tunnel_filter->ip_addr,
4775 sizeof(pfilter->ipaddr.v4.data));
4777 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4778 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4779 &tunnel_filter->ip_addr,
4780 sizeof(pfilter->ipaddr.v6.data));
4783 /* check tunneled type */
4784 switch (tunnel_filter->tunnel_type) {
4785 case RTE_TUNNEL_TYPE_VXLAN:
4786 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4789 /* Other tunnel types is not supported. */
4790 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4791 rte_free(cld_filter);
4795 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4798 rte_free(cld_filter);
4802 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4803 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4804 pfilter->tenant_id = tunnel_filter->tenant_id;
4805 pfilter->queue_number = tunnel_filter->queue_id;
4808 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4810 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4813 rte_free(cld_filter);
4818 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4822 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4823 if (pf->vxlan_ports[i] == port)
4831 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4835 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4837 idx = i40e_get_vxlan_port_idx(pf, port);
4839 /* Check if port already exists */
4841 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4845 /* Now check if there is space to add the new port */
4846 idx = i40e_get_vxlan_port_idx(pf, 0);
4848 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4849 "not adding port %d", port);
4853 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4856 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4860 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4863 /* New port: add it and mark its index in the bitmap */
4864 pf->vxlan_ports[idx] = port;
4865 pf->vxlan_bitmap |= (1 << idx);
4867 if (!(pf->flags & I40E_FLAG_VXLAN))
4868 pf->flags |= I40E_FLAG_VXLAN;
4874 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4877 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4879 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4880 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4884 idx = i40e_get_vxlan_port_idx(pf, port);
4887 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4891 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4892 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4896 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4899 pf->vxlan_ports[idx] = 0;
4900 pf->vxlan_bitmap &= ~(1 << idx);
4902 if (!pf->vxlan_bitmap)
4903 pf->flags &= ~I40E_FLAG_VXLAN;
4908 /* Add UDP tunneling port */
4910 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4911 struct rte_eth_udp_tunnel *udp_tunnel)
4914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4916 if (udp_tunnel == NULL)
4919 switch (udp_tunnel->prot_type) {
4920 case RTE_TUNNEL_TYPE_VXLAN:
4921 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4924 case RTE_TUNNEL_TYPE_GENEVE:
4925 case RTE_TUNNEL_TYPE_TEREDO:
4926 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4931 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4939 /* Remove UDP tunneling port */
4941 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4942 struct rte_eth_udp_tunnel *udp_tunnel)
4945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4947 if (udp_tunnel == NULL)
4950 switch (udp_tunnel->prot_type) {
4951 case RTE_TUNNEL_TYPE_VXLAN:
4952 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4954 case RTE_TUNNEL_TYPE_GENEVE:
4955 case RTE_TUNNEL_TYPE_TEREDO:
4956 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4960 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4968 /* Calculate the maximum number of contiguous PF queues that are configured */
4970 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4972 struct rte_eth_dev_data *data = pf->dev_data;
4974 struct i40e_rx_queue *rxq;
4977 for (i = 0; i < pf->lan_nb_qps; i++) {
4978 rxq = data->rx_queues[i];
4979 if (rxq && rxq->q_set)
4990 i40e_pf_config_rss(struct i40e_pf *pf)
4992 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4993 struct rte_eth_rss_conf rss_conf;
4994 uint32_t i, lut = 0;
4998 * If both VMDQ and RSS enabled, not all of PF queues are configured.
4999 * It's necessary to calulate the actual PF queues that are configured.
5001 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5002 num = i40e_pf_calc_configured_queues_num(pf);
5003 num = i40e_align_floor(num);
5005 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5007 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5011 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5015 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5018 lut = (lut << 8) | (j & ((0x1 <<
5019 hw->func_caps.rss_table_entry_width) - 1));
5021 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5024 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5025 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5026 i40e_pf_disable_rss(pf);
5029 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5030 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5031 /* Calculate the default hash key */
5032 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5033 rss_key_default[i] = (uint32_t)rte_rand();
5034 rss_conf.rss_key = (uint8_t *)rss_key_default;
5035 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5039 return i40e_hw_rss_hash_set(hw, &rss_conf);
5043 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5044 struct rte_eth_tunnel_filter_conf *filter)
5046 if (pf == NULL || filter == NULL) {
5047 PMD_DRV_LOG(ERR, "Invalid parameter");
5051 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5052 PMD_DRV_LOG(ERR, "Invalid queue ID");
5056 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5057 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5061 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5062 (is_zero_ether_addr(filter->outer_mac))) {
5063 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5067 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5068 (is_zero_ether_addr(filter->inner_mac))) {
5069 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5077 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5080 struct rte_eth_tunnel_filter_conf *filter;
5081 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5082 int ret = I40E_SUCCESS;
5084 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5086 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5087 return I40E_ERR_PARAM;
5089 switch (filter_op) {
5090 case RTE_ETH_FILTER_NOP:
5091 if (!(pf->flags & I40E_FLAG_VXLAN))
5092 ret = I40E_NOT_SUPPORTED;
5093 case RTE_ETH_FILTER_ADD:
5094 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5096 case RTE_ETH_FILTER_DELETE:
5097 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5100 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5101 ret = I40E_ERR_PARAM;
5109 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5112 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5114 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5115 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5120 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5121 ret = i40e_pf_config_rss(pf);
5123 i40e_pf_disable_rss(pf);
5129 * Configure ethertype filter, which can director packet by filtering
5130 * with mac address and ether_type or only ether_type
5133 i40e_ethertype_filter_set(struct i40e_pf *pf,
5134 struct rte_eth_ethertype_filter *filter,
5137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5138 struct i40e_control_filter_stats stats;
5142 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5143 PMD_DRV_LOG(ERR, "Invalid queue ID");
5146 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5147 filter->ether_type == ETHER_TYPE_IPv6) {
5148 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5149 " control packet filter.", filter->ether_type);
5152 if (filter->ether_type == ETHER_TYPE_VLAN)
5153 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5156 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5157 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5158 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5159 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5160 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5162 memset(&stats, 0, sizeof(stats));
5163 ret = i40e_aq_add_rem_control_packet_filter(hw,
5164 filter->mac_addr.addr_bytes,
5165 filter->ether_type, flags,
5167 filter->queue, add, &stats, NULL);
5169 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5170 " mac_etype_used = %u, etype_used = %u,"
5171 " mac_etype_free = %u, etype_free = %u\n",
5172 ret, stats.mac_etype_used, stats.etype_used,
5173 stats.mac_etype_free, stats.etype_free);
5180 * Handle operations for ethertype filter.
5183 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5184 enum rte_filter_op filter_op,
5187 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5190 if (filter_op == RTE_ETH_FILTER_NOP)
5194 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5199 switch (filter_op) {
5200 case RTE_ETH_FILTER_ADD:
5201 ret = i40e_ethertype_filter_set(pf,
5202 (struct rte_eth_ethertype_filter *)arg,
5205 case RTE_ETH_FILTER_DELETE:
5206 ret = i40e_ethertype_filter_set(pf,
5207 (struct rte_eth_ethertype_filter *)arg,
5211 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5219 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5220 enum rte_filter_type filter_type,
5221 enum rte_filter_op filter_op,
5229 switch (filter_type) {
5230 case RTE_ETH_FILTER_MACVLAN:
5231 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5233 case RTE_ETH_FILTER_ETHERTYPE:
5234 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5236 case RTE_ETH_FILTER_TUNNEL:
5237 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5239 case RTE_ETH_FILTER_FDIR:
5240 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5243 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5252 enum i40e_filter_pctype
5253 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5255 static const enum i40e_filter_pctype pctype_table[] = {
5256 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5257 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5258 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5259 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5260 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5261 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5262 I40E_FILTER_PCTYPE_FRAG_IPV4,
5263 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5264 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5265 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5266 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5267 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5268 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5269 I40E_FILTER_PCTYPE_FRAG_IPV6,
5272 return pctype_table[flow_type];
5275 enum rte_eth_flow_type
5276 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5278 static const enum rte_eth_flow_type flowtype_table[] = {
5279 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5280 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5281 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5282 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5283 RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5284 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5285 RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5286 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5287 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5288 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5289 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5290 RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5291 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5292 RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5295 return flowtype_table[pctype];