lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds*/
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 static int eth_i40e_dev_init(\
  97                         __attribute__((unused)) struct eth_driver *eth_drv,
  98                         struct rte_eth_dev *eth_dev);
  99 static int i40e_dev_configure(struct rte_eth_dev *dev);
 100 static int i40e_dev_start(struct rte_eth_dev *dev);
 101 static void i40e_dev_stop(struct rte_eth_dev *dev);
 102 static void i40e_dev_close(struct rte_eth_dev *dev);
 103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 110                                struct rte_eth_stats *stats);
 111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 113                                             uint16_t queue_id,
 114                                             uint8_t stat_idx,
 115                                             uint8_t is_rx);
 116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_dev_info *dev_info);
 118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 119                                 uint16_t vlan_id,
 120                                 int on);
 121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 124                                       uint16_t queue,
 125                                       int on);
 126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 130                               struct rte_eth_fc_conf *fc_conf);
 131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 132                                        struct rte_eth_pfc_conf *pfc_conf);
 133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 134                           struct ether_addr *mac_addr,
 135                           uint32_t index,
 136                           uint32_t pool);
 137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 139                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 140                                     uint16_t reta_size);
 141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 142                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 143                                    uint16_t reta_size);
 144
 145 static int i40e_get_cap(struct i40e_hw *hw);
 146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 147 static int i40e_pf_setup(struct i40e_pf *pf);
 148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 151                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 152 static void i40e_stat_update_48(struct i40e_hw *hw,
 153                                uint32_t hireg,
 154                                uint32_t loreg,
 155                                bool offset_loaded,
 156                                uint64_t *offset,
 157                                uint64_t *stat);
 158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 159 static void i40e_dev_interrupt_handler(
 160                 __rte_unused struct rte_intr_handle *handle, void *param);
 161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 162                                 uint32_t base, uint32_t num);
 163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 165                         uint32_t base);
 166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 167                         uint16_t num);
 168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 169 static int i40e_veb_release(struct i40e_veb *veb);
 170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 171                                                 struct i40e_vsi *vsi);
 172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 175                                              struct i40e_macvlan_filter *mv_f,
 176                                              int num,
 177                                              struct ether_addr *addr);
 178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 179                                              struct i40e_macvlan_filter *mv_f,
 180                                              int num,
 181                                              uint16_t vlan);
 182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 184                                     struct rte_eth_rss_conf *rss_conf);
 185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 186                                       struct rte_eth_rss_conf *rss_conf);
 187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 188                                 struct rte_eth_udp_tunnel *udp_tunnel);
 189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 190                                 struct rte_eth_udp_tunnel *udp_tunnel);
 191 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 192                                 enum rte_filter_type filter_type,
 193                                 enum rte_filter_op filter_op,
 194                                 void *arg);
 195
 196 /* Default hash key buffer for RSS */
 197 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 198
 199 static struct rte_pci_id pci_id_i40e_map[] = {
 200 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 201 #include "rte_pci_dev_ids.h"
 202 { .vendor_id = 0, /* sentinel */ },
 203 };
 204
 205 static struct eth_dev_ops i40e_eth_dev_ops = {
 206         .dev_configure                = i40e_dev_configure,
 207         .dev_start                    = i40e_dev_start,
 208         .dev_stop                     = i40e_dev_stop,
 209         .dev_close                    = i40e_dev_close,
 210         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 211         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 212         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 213         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 214         .dev_set_link_up              = i40e_dev_set_link_up,
 215         .dev_set_link_down            = i40e_dev_set_link_down,
 216         .link_update                  = i40e_dev_link_update,
 217         .stats_get                    = i40e_dev_stats_get,
 218         .stats_reset                  = i40e_dev_stats_reset,
 219         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 220         .dev_infos_get                = i40e_dev_info_get,
 221         .vlan_filter_set              = i40e_vlan_filter_set,
 222         .vlan_tpid_set                = i40e_vlan_tpid_set,
 223         .vlan_offload_set             = i40e_vlan_offload_set,
 224         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 225         .vlan_pvid_set                = i40e_vlan_pvid_set,
 226         .rx_queue_start               = i40e_dev_rx_queue_start,
 227         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 228         .tx_queue_start               = i40e_dev_tx_queue_start,
 229         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 230         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 231         .rx_queue_release             = i40e_dev_rx_queue_release,
 232         .rx_queue_count               = i40e_dev_rx_queue_count,
 233         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 234         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 235         .tx_queue_release             = i40e_dev_tx_queue_release,
 236         .dev_led_on                   = i40e_dev_led_on,
 237         .dev_led_off                  = i40e_dev_led_off,
 238         .flow_ctrl_set                = i40e_flow_ctrl_set,
 239         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 240         .mac_addr_add                 = i40e_macaddr_add,
 241         .mac_addr_remove              = i40e_macaddr_remove,
 242         .reta_update                  = i40e_dev_rss_reta_update,
 243         .reta_query                   = i40e_dev_rss_reta_query,
 244         .rss_hash_update              = i40e_dev_rss_hash_update,
 245         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 246         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 247         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 248         .filter_ctrl                  = i40e_dev_filter_ctrl,
 249 };
 250
 251 static struct eth_driver rte_i40e_pmd = {
 252         {
 253                 .name = "rte_i40e_pmd",
 254                 .id_table = pci_id_i40e_map,
 255                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 256         },
 257         .eth_dev_init = eth_i40e_dev_init,
 258         .dev_private_size = sizeof(struct i40e_adapter),
 259 };
 260
 261 static inline int
 262 i40e_align_floor(int n)
 263 {
 264         if (n == 0)
 265                 return 0;
 266         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 267 }
 268
 269 static inline int
 270 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 271                                      struct rte_eth_link *link)
 272 {
 273         struct rte_eth_link *dst = link;
 274         struct rte_eth_link *src = &(dev->data->dev_link);
 275
 276         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 277                                         *(uint64_t *)src) == 0)
 278                 return -1;
 279
 280         return 0;
 281 }
 282
 283 static inline int
 284 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 285                                       struct rte_eth_link *link)
 286 {
 287         struct rte_eth_link *dst = &(dev->data->dev_link);
 288         struct rte_eth_link *src = link;
 289
 290         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 291                                         *(uint64_t *)src) == 0)
 292                 return -1;
 293
 294         return 0;
 295 }
 296
 297 /*
 298  * Driver initialization routine.
 299  * Invoked once at EAL init time.
 300  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 301  */
 302 static int
 303 rte_i40e_pmd_init(const char *name __rte_unused,
 304                   const char *params __rte_unused)
 305 {
 306         PMD_INIT_FUNC_TRACE();
 307         rte_eth_driver_register(&rte_i40e_pmd);
 308
 309         return 0;
 310 }
 311
 312 static struct rte_driver rte_i40e_driver = {
 313         .type = PMD_PDEV,
 314         .init = rte_i40e_pmd_init,
 315 };
 316
 317 PMD_REGISTER_DRIVER(rte_i40e_driver);
 318
 319 static int
 320 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 321                   struct rte_eth_dev *dev)
 322 {
 323         struct rte_pci_device *pci_dev;
 324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 325         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 326         struct i40e_vsi *vsi;
 327         int ret;
 328         uint32_t len;
 329         uint8_t aq_fail = 0;
 330
 331         PMD_INIT_FUNC_TRACE();
 332
 333         dev->dev_ops = &i40e_eth_dev_ops;
 334         dev->rx_pkt_burst = i40e_recv_pkts;
 335         dev->tx_pkt_burst = i40e_xmit_pkts;
 336
 337         /* for secondary processes, we don't initialise any further as primary
 338          * has already done this work. Only check we don't need a different
 339          * RX function */
 340         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 341                 if (dev->data->scattered_rx)
 342                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 343                 return 0;
 344         }
 345         pci_dev = dev->pci_dev;
 346         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 347         pf->adapter->eth_dev = dev;
 348         pf->dev_data = dev->data;
 349
 350         hw->back = I40E_PF_TO_ADAPTER(pf);
 351         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 352         if (!hw->hw_addr) {
 353                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 354                              "as address is NULL");
 355                 return -ENODEV;
 356         }
 357
 358         hw->vendor_id = pci_dev->id.vendor_id;
 359         hw->device_id = pci_dev->id.device_id;
 360         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 361         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 362         hw->bus.device = pci_dev->addr.devid;
 363         hw->bus.func = pci_dev->addr.function;
 364
 365         /* Make sure all is clean before doing PF reset */
 366         i40e_clear_hw(hw);
 367
 368         /* Reset here to make sure all is clean for each PF */
 369         ret = i40e_pf_reset(hw);
 370         if (ret) {
 371                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 372                 return ret;
 373         }
 374
 375         /* Initialize the shared code (base driver) */
 376         ret = i40e_init_shared_code(hw);
 377         if (ret) {
 378                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 379                 return ret;
 380         }
 381
 382         /* Initialize the parameters for adminq */
 383         i40e_init_adminq_parameter(hw);
 384         ret = i40e_init_adminq(hw);
 385         if (ret != I40E_SUCCESS) {
 386                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 387                 return -EIO;
 388         }
 389         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 390                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 391                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 392                      ((hw->nvm.version >> 12) & 0xf),
 393                      ((hw->nvm.version >> 4) & 0xff),
 394                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 395
 396         /* Disable LLDP */
 397         ret = i40e_aq_stop_lldp(hw, true, NULL);
 398         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 399                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 400
 401         /* Clear PXE mode */
 402         i40e_clear_pxe_mode(hw);
 403
 404         /* Get hw capabilities */
 405         ret = i40e_get_cap(hw);
 406         if (ret != I40E_SUCCESS) {
 407                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 408                 goto err_get_capabilities;
 409         }
 410
 411         /* Initialize parameters for PF */
 412         ret = i40e_pf_parameter_init(dev);
 413         if (ret != 0) {
 414                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 415                 goto err_parameter_init;
 416         }
 417
 418         /* Initialize the queue management */
 419         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 420         if (ret < 0) {
 421                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 422                 goto err_qp_pool_init;
 423         }
 424         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 425                                 hw->func_caps.num_msix_vectors - 1);
 426         if (ret < 0) {
 427                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 428                 goto err_msix_pool_init;
 429         }
 430
 431         /* Initialize lan hmc */
 432         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 433                                 hw->func_caps.num_rx_qp, 0, 0);
 434         if (ret != I40E_SUCCESS) {
 435                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 436                 goto err_init_lan_hmc;
 437         }
 438
 439         /* Configure lan hmc */
 440         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 441         if (ret != I40E_SUCCESS) {
 442                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 443                 goto err_configure_lan_hmc;
 444         }
 445
 446         /* Get and check the mac address */
 447         i40e_get_mac_addr(hw, hw->mac.addr);
 448         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 449                 PMD_INIT_LOG(ERR, "mac address is not valid");
 450                 ret = -EIO;
 451                 goto err_get_mac_addr;
 452         }
 453         /* Copy the permanent MAC address */
 454         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 455                         (struct ether_addr *) hw->mac.perm_addr);
 456
 457         /* Disable flow control */
 458         hw->fc.requested_mode = I40E_FC_NONE;
 459         i40e_set_fc(hw, &aq_fail, TRUE);
 460
 461         /* PF setup, which includes VSI setup */
 462         ret = i40e_pf_setup(pf);
 463         if (ret) {
 464                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 465                 goto err_setup_pf_switch;
 466         }
 467
 468         vsi = pf->main_vsi;
 469
 470         /* Disable double vlan by default */
 471         i40e_vsi_config_double_vlan(vsi, FALSE);
 472
 473         if (!vsi->max_macaddrs)
 474                 len = ETHER_ADDR_LEN;
 475         else
 476                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 477
 478         /* Should be after VSI initialized */
 479         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 480         if (!dev->data->mac_addrs) {
 481                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 482                                         "for storing mac address");
 483                 goto err_mac_alloc;
 484         }
 485         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 486                                         &dev->data->mac_addrs[0]);
 487
 488         /* initialize pf host driver to setup SRIOV resource if applicable */
 489         i40e_pf_host_init(dev);
 490
 491         /* register callback func to eal lib */
 492         rte_intr_callback_register(&(pci_dev->intr_handle),
 493                 i40e_dev_interrupt_handler, (void *)dev);
 494
 495         /* configure and enable device interrupt */
 496         i40e_pf_config_irq0(hw);
 497         i40e_pf_enable_irq0(hw);
 498
 499         /* enable uio intr after callback register */
 500         rte_intr_enable(&(pci_dev->intr_handle));
 501
 502         return 0;
 503
 504 err_mac_alloc:
 505         i40e_vsi_release(pf->main_vsi);
 506 err_setup_pf_switch:
 507 err_get_mac_addr:
 508 err_configure_lan_hmc:
 509         (void)i40e_shutdown_lan_hmc(hw);
 510 err_init_lan_hmc:
 511         i40e_res_pool_destroy(&pf->msix_pool);
 512 err_msix_pool_init:
 513         i40e_res_pool_destroy(&pf->qp_pool);
 514 err_qp_pool_init:
 515 err_parameter_init:
 516 err_get_capabilities:
 517         (void)i40e_shutdown_adminq(hw);
 518
 519         return ret;
 520 }
 521
 522 static int
 523 i40e_dev_configure(struct rte_eth_dev *dev)
 524 {
 525         int ret;
 526         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 527
 528         /* VMDQ setup.
 529          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 530          *  RSS setting have different requirements.
 531          *  General PMD driver call sequence are NIC init, configure,
 532          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 533          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 534          *  applicable. So, VMDQ setting has to be done before
 535          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 536          *  For RSS setting, it will try to calculate actual configured RX queue
 537          *  number, which will be available after rx_queue_setup(). dev_start()
 538          *  function is good to place RSS setup.
 539          */
 540         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 541                 ret = i40e_vmdq_setup(dev);
 542                 if (ret)
 543                         return ret;
 544         }
 545
 546         return i40e_dev_init_vlan(dev);
 547 }
 548
 549 void
 550 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 551 {
 552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 553         uint16_t msix_vect = vsi->msix_intr;
 554         uint16_t i;
 555
 556         for (i = 0; i < vsi->nb_qps; i++) {
 557                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 558                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 559                 rte_wmb();
 560         }
 561
 562         if (vsi->type != I40E_VSI_SRIOV) {
 563                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 564                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 565                                 msix_vect - 1), 0);
 566         } else {
 567                 uint32_t reg;
 568                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 569                         vsi->user_param + (msix_vect - 1);
 570
 571                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 572         }
 573         I40E_WRITE_FLUSH(hw);
 574 }
 575
 576 static inline uint16_t
 577 i40e_calc_itr_interval(int16_t interval)
 578 {
 579         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 580                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 581
 582         /* Convert to hardware count, as writing each 1 represents 2 us */
 583         return (interval/2);
 584 }
 585
 586 void
 587 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 588 {
 589         uint32_t val;
 590         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 591         uint16_t msix_vect = vsi->msix_intr;
 592         int i;
 593
 594         for (i = 0; i < vsi->nb_qps; i++)
 595                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 596
 597         /* Bind all RX queues to allocated MSIX interrupt */
 598         for (i = 0; i < vsi->nb_qps; i++) {
 599                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 600                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 601                         ((vsi->base_queue + i + 1) <<
 602                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 603                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 604                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 605
 606                 if (i == vsi->nb_qps - 1)
 607                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 608                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 609         }
 610
 611         /* Write first RX queue to Link list register as the head element */
 612         if (vsi->type != I40E_VSI_SRIOV) {
 613                 uint16_t interval =
 614                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 615
 616                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 617                                                 (vsi->base_queue <<
 618                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 619                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 620
 621                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 622                                                 msix_vect - 1), interval);
 623
 624 #ifndef I40E_GLINT_CTL
 625 #define I40E_GLINT_CTL                     0x0003F800
 626 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 627 #endif
 628                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 629                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 630                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 631         } else {
 632                 uint32_t reg;
 633
 634                 /* num_msix_vectors_vf needs to minus irq0 */
 635                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 636                         vsi->user_param + (msix_vect - 1);
 637
 638                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 639                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 640                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 641         }
 642
 643         I40E_WRITE_FLUSH(hw);
 644 }
 645
 646 static void
 647 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 648 {
 649         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 650         uint16_t interval = i40e_calc_itr_interval(\
 651                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 652
 653         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 654                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 655                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 656                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 657                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 658 }
 659
 660 static void
 661 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 662 {
 663         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 664
 665         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 666 }
 667
 668 static inline uint8_t
 669 i40e_parse_link_speed(uint16_t eth_link_speed)
 670 {
 671         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 672
 673         switch (eth_link_speed) {
 674         case ETH_LINK_SPEED_40G:
 675                 link_speed = I40E_LINK_SPEED_40GB;
 676                 break;
 677         case ETH_LINK_SPEED_20G:
 678                 link_speed = I40E_LINK_SPEED_20GB;
 679                 break;
 680         case ETH_LINK_SPEED_10G:
 681                 link_speed = I40E_LINK_SPEED_10GB;
 682                 break;
 683         case ETH_LINK_SPEED_1000:
 684                 link_speed = I40E_LINK_SPEED_1GB;
 685                 break;
 686         case ETH_LINK_SPEED_100:
 687                 link_speed = I40E_LINK_SPEED_100MB;
 688                 break;
 689         }
 690
 691         return link_speed;
 692 }
 693
 694 static int
 695 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 696 {
 697         enum i40e_status_code status;
 698         struct i40e_aq_get_phy_abilities_resp phy_ab;
 699         struct i40e_aq_set_phy_config phy_conf;
 700         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 701                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 702                         I40E_AQ_PHY_FLAG_LOW_POWER;
 703         const uint8_t advt = I40E_LINK_SPEED_40GB |
 704                         I40E_LINK_SPEED_10GB |
 705                         I40E_LINK_SPEED_1GB |
 706                         I40E_LINK_SPEED_100MB;
 707         int ret = -ENOTSUP;
 708
 709         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 710                                               NULL);
 711         if (status)
 712                 return ret;
 713
 714         memset(&phy_conf, 0, sizeof(phy_conf));
 715
 716         /* bits 0-2 use the values from get_phy_abilities_resp */
 717         abilities &= ~mask;
 718         abilities |= phy_ab.abilities & mask;
 719
 720         /* update ablities and speed */
 721         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 722                 phy_conf.link_speed = advt;
 723         else
 724                 phy_conf.link_speed = force_speed;
 725
 726         phy_conf.abilities = abilities;
 727
 728         /* use get_phy_abilities_resp value for the rest */
 729         phy_conf.phy_type = phy_ab.phy_type;
 730         phy_conf.eee_capability = phy_ab.eee_capability;
 731         phy_conf.eeer = phy_ab.eeer_val;
 732         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 733
 734         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 735                     phy_ab.abilities, phy_ab.link_speed);
 736         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 737                     phy_conf.abilities, phy_conf.link_speed);
 738
 739         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 740         if (status)
 741                 return ret;
 742
 743         return I40E_SUCCESS;
 744 }
 745
 746 static int
 747 i40e_apply_link_speed(struct rte_eth_dev *dev)
 748 {
 749         uint8_t speed;
 750         uint8_t abilities = 0;
 751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 752         struct rte_eth_conf *conf = &dev->data->dev_conf;
 753
 754         speed = i40e_parse_link_speed(conf->link_speed);
 755         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 756         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 757                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 758         else
 759                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 760
 761         return i40e_phy_conf_link(hw, abilities, speed);
 762 }
 763
 764 static int
 765 i40e_dev_start(struct rte_eth_dev *dev)
 766 {
 767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 769         struct i40e_vsi *main_vsi = pf->main_vsi;
 770         int ret, i;
 771
 772         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 773                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 774                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 775                              dev->data->dev_conf.link_duplex,
 776                              dev->data->port_id);
 777                 return -EINVAL;
 778         }
 779
 780         /* Initialize VSI */
 781         ret = i40e_dev_rxtx_init(pf);
 782         if (ret != I40E_SUCCESS) {
 783                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 784                 goto err_up;
 785         }
 786
 787         /* Map queues with MSIX interrupt */
 788         i40e_vsi_queues_bind_intr(main_vsi);
 789         i40e_vsi_enable_queues_intr(main_vsi);
 790
 791         /* Map VMDQ VSI queues with MSIX interrupt */
 792         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 793                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 794                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 795         }
 796
 797         ret = i40e_fdir_configure(dev);
 798         if (ret < 0) {
 799                 PMD_DRV_LOG(ERR, "failed to configure fdir.");
 800                 goto err_up;
 801         }
 802
 803         /* enable FDIR MSIX interrupt */
 804         if (pf->flags & I40E_FLAG_FDIR) {
 805                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 806                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 807         }
 808
 809         /* Enable all queues which have been configured */
 810         ret = i40e_dev_switch_queues(pf, TRUE);
 811         if (ret != I40E_SUCCESS) {
 812                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 813                 goto err_up;
 814         }
 815
 816         /* Enable receiving broadcast packets */
 817         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 818         if (ret != I40E_SUCCESS)
 819                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 820
 821         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 822                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 823                                                 true, NULL);
 824                 if (ret != I40E_SUCCESS)
 825                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 826         }
 827
 828         /* Apply link configure */
 829         ret = i40e_apply_link_speed(dev);
 830         if (I40E_SUCCESS != ret) {
 831                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 832                 goto err_up;
 833         }
 834
 835         return I40E_SUCCESS;
 836
 837 err_up:
 838         i40e_dev_switch_queues(pf, FALSE);
 839         i40e_dev_clear_queues(dev);
 840
 841         return ret;
 842 }
 843
 844 static void
 845 i40e_dev_stop(struct rte_eth_dev *dev)
 846 {
 847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 848         struct i40e_vsi *main_vsi = pf->main_vsi;
 849         int i;
 850
 851         /* Disable all queues */
 852         i40e_dev_switch_queues(pf, FALSE);
 853
 854         /* un-map queues with interrupt registers */
 855         i40e_vsi_disable_queues_intr(main_vsi);
 856         i40e_vsi_queues_unbind_intr(main_vsi);
 857
 858         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 859                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 860                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 861         }
 862
 863         /* Clear all queues and release memory */
 864         i40e_dev_clear_queues(dev);
 865
 866         /* Set link down */
 867         i40e_dev_set_link_down(dev);
 868 }
 869
 870 static void
 871 i40e_dev_close(struct rte_eth_dev *dev)
 872 {
 873         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 875         uint32_t reg;
 876
 877         PMD_INIT_FUNC_TRACE();
 878
 879         i40e_dev_stop(dev);
 880
 881         /* Disable interrupt */
 882         i40e_pf_disable_irq0(hw);
 883         rte_intr_disable(&(dev->pci_dev->intr_handle));
 884
 885         /* shutdown and destroy the HMC */
 886         i40e_shutdown_lan_hmc(hw);
 887
 888         /* release all the existing VSIs and VEBs */
 889         i40e_vsi_release(pf->main_vsi);
 890
 891         /* shutdown the adminq */
 892         i40e_aq_queue_shutdown(hw, true);
 893         i40e_shutdown_adminq(hw);
 894
 895         i40e_res_pool_destroy(&pf->qp_pool);
 896         i40e_res_pool_destroy(&pf->msix_pool);
 897
 898         /* force a PF reset to clean anything leftover */
 899         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 900         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 901                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 902         I40E_WRITE_FLUSH(hw);
 903 }
 904
 905 static void
 906 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 907 {
 908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 910         struct i40e_vsi *vsi = pf->main_vsi;
 911         int status;
 912
 913         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 914                                                         true, NULL);
 915         if (status != I40E_SUCCESS)
 916                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 917
 918         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 919                                                         TRUE, NULL);
 920         if (status != I40E_SUCCESS)
 921                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 922
 923 }
 924
 925 static void
 926 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 927 {
 928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 929         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 930         struct i40e_vsi *vsi = pf->main_vsi;
 931         int status;
 932
 933         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 934                                                         false, NULL);
 935         if (status != I40E_SUCCESS)
 936                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 937
 938         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 939                                                         false, NULL);
 940         if (status != I40E_SUCCESS)
 941                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 942 }
 943
 944 static void
 945 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 946 {
 947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949         struct i40e_vsi *vsi = pf->main_vsi;
 950         int ret;
 951
 952         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 953         if (ret != I40E_SUCCESS)
 954                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 955 }
 956
 957 static void
 958 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         struct i40e_vsi *vsi = pf->main_vsi;
 963         int ret;
 964
 965         if (dev->data->promiscuous == 1)
 966                 return; /* must remain in all_multicast mode */
 967
 968         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 969                                 vsi->seid, FALSE, NULL);
 970         if (ret != I40E_SUCCESS)
 971                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 972 }
 973
 974 /*
 975  * Set device link up.
 976  */
 977 static int
 978 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 979 {
 980         /* re-apply link speed setting */
 981         return i40e_apply_link_speed(dev);
 982 }
 983
 984 /*
 985  * Set device link down.
 986  */
 987 static int
 988 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 989 {
 990         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 991         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 992         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 993
 994         return i40e_phy_conf_link(hw, abilities, speed);
 995 }
 996
 997 int
 998 i40e_dev_link_update(struct rte_eth_dev *dev,
 999                      __rte_unused int wait_to_complete)
1000 {
1001         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002         struct i40e_link_status link_status;
1003         struct rte_eth_link link, old;
1004         int status;
1005
1006         memset(&link, 0, sizeof(link));
1007         memset(&old, 0, sizeof(old));
1008         memset(&link_status, 0, sizeof(link_status));
1009         rte_i40e_dev_atomic_read_link_status(dev, &old);
1010
1011         /* Get link status information from hardware */
1012         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1013         if (status != I40E_SUCCESS) {
1014                 link.link_speed = ETH_LINK_SPEED_100;
1015                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1016                 PMD_DRV_LOG(ERR, "Failed to get link info");
1017                 goto out;
1018         }
1019
1020         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1021
1022         if (!link.link_status)
1023                 goto out;
1024
1025         /* i40e uses full duplex only */
1026         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1027
1028         /* Parse the link status */
1029         switch (link_status.link_speed) {
1030         case I40E_LINK_SPEED_100MB:
1031                 link.link_speed = ETH_LINK_SPEED_100;
1032                 break;
1033         case I40E_LINK_SPEED_1GB:
1034                 link.link_speed = ETH_LINK_SPEED_1000;
1035                 break;
1036         case I40E_LINK_SPEED_10GB:
1037                 link.link_speed = ETH_LINK_SPEED_10G;
1038                 break;
1039         case I40E_LINK_SPEED_20GB:
1040                 link.link_speed = ETH_LINK_SPEED_20G;
1041                 break;
1042         case I40E_LINK_SPEED_40GB:
1043                 link.link_speed = ETH_LINK_SPEED_40G;
1044                 break;
1045         default:
1046                 link.link_speed = ETH_LINK_SPEED_100;
1047                 break;
1048         }
1049
1050 out:
1051         rte_i40e_dev_atomic_write_link_status(dev, &link);
1052         if (link.link_status == old.link_status)
1053                 return -1;
1054
1055         return 0;
1056 }
1057
1058 /* Get all the statistics of a VSI */
1059 void
1060 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1061 {
1062         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1063         struct i40e_eth_stats *nes = &vsi->eth_stats;
1064         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1065         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1066
1067         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1068                             vsi->offset_loaded, &oes->rx_bytes,
1069                             &nes->rx_bytes);
1070         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1071                             vsi->offset_loaded, &oes->rx_unicast,
1072                             &nes->rx_unicast);
1073         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1074                             vsi->offset_loaded, &oes->rx_multicast,
1075                             &nes->rx_multicast);
1076         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1077                             vsi->offset_loaded, &oes->rx_broadcast,
1078                             &nes->rx_broadcast);
1079         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1080                             &oes->rx_discards, &nes->rx_discards);
1081         /* GLV_REPC not supported */
1082         /* GLV_RMPC not supported */
1083         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1084                             &oes->rx_unknown_protocol,
1085                             &nes->rx_unknown_protocol);
1086         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1087                             vsi->offset_loaded, &oes->tx_bytes,
1088                             &nes->tx_bytes);
1089         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1090                             vsi->offset_loaded, &oes->tx_unicast,
1091                             &nes->tx_unicast);
1092         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1093                             vsi->offset_loaded, &oes->tx_multicast,
1094                             &nes->tx_multicast);
1095         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1096                             vsi->offset_loaded,  &oes->tx_broadcast,
1097                             &nes->tx_broadcast);
1098         /* GLV_TDPC not supported */
1099         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1100                             &oes->tx_errors, &nes->tx_errors);
1101         vsi->offset_loaded = true;
1102
1103         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1104                     vsi->vsi_id);
1105         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1106         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1107         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1108         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1109         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1110         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1111                     nes->rx_unknown_protocol);
1112         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1113         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1114         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1115         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1116         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1117         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1118         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1119                     vsi->vsi_id);
1120 }
1121
1122 /* Get all statistics of a port */
1123 static void
1124 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1125 {
1126         uint32_t i;
1127         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1130         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1131
1132         /* Get statistics of struct i40e_eth_stats */
1133         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1134                             I40E_GLPRT_GORCL(hw->port),
1135                             pf->offset_loaded, &os->eth.rx_bytes,
1136                             &ns->eth.rx_bytes);
1137         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1138                             I40E_GLPRT_UPRCL(hw->port),
1139                             pf->offset_loaded, &os->eth.rx_unicast,
1140                             &ns->eth.rx_unicast);
1141         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1142                             I40E_GLPRT_MPRCL(hw->port),
1143                             pf->offset_loaded, &os->eth.rx_multicast,
1144                             &ns->eth.rx_multicast);
1145         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1146                             I40E_GLPRT_BPRCL(hw->port),
1147                             pf->offset_loaded, &os->eth.rx_broadcast,
1148                             &ns->eth.rx_broadcast);
1149         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1150                             pf->offset_loaded, &os->eth.rx_discards,
1151                             &ns->eth.rx_discards);
1152         /* GLPRT_REPC not supported */
1153         /* GLPRT_RMPC not supported */
1154         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1155                             pf->offset_loaded,
1156                             &os->eth.rx_unknown_protocol,
1157                             &ns->eth.rx_unknown_protocol);
1158         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1159                             I40E_GLPRT_GOTCL(hw->port),
1160                             pf->offset_loaded, &os->eth.tx_bytes,
1161                             &ns->eth.tx_bytes);
1162         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1163                             I40E_GLPRT_UPTCL(hw->port),
1164                             pf->offset_loaded, &os->eth.tx_unicast,
1165                             &ns->eth.tx_unicast);
1166         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1167                             I40E_GLPRT_MPTCL(hw->port),
1168                             pf->offset_loaded, &os->eth.tx_multicast,
1169                             &ns->eth.tx_multicast);
1170         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1171                             I40E_GLPRT_BPTCL(hw->port),
1172                             pf->offset_loaded, &os->eth.tx_broadcast,
1173                             &ns->eth.tx_broadcast);
1174         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1175                             pf->offset_loaded, &os->eth.tx_discards,
1176                             &ns->eth.tx_discards);
1177         /* GLPRT_TEPC not supported */
1178
1179         /* additional port specific stats */
1180         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1181                             pf->offset_loaded, &os->tx_dropped_link_down,
1182                             &ns->tx_dropped_link_down);
1183         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1184                             pf->offset_loaded, &os->crc_errors,
1185                             &ns->crc_errors);
1186         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1187                             pf->offset_loaded, &os->illegal_bytes,
1188                             &ns->illegal_bytes);
1189         /* GLPRT_ERRBC not supported */
1190         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1191                             pf->offset_loaded, &os->mac_local_faults,
1192                             &ns->mac_local_faults);
1193         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1194                             pf->offset_loaded, &os->mac_remote_faults,
1195                             &ns->mac_remote_faults);
1196         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1197                             pf->offset_loaded, &os->rx_length_errors,
1198                             &ns->rx_length_errors);
1199         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1200                             pf->offset_loaded, &os->link_xon_rx,
1201                             &ns->link_xon_rx);
1202         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1203                             pf->offset_loaded, &os->link_xoff_rx,
1204                             &ns->link_xoff_rx);
1205         for (i = 0; i < 8; i++) {
1206                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1207                                     pf->offset_loaded,
1208                                     &os->priority_xon_rx[i],
1209                                     &ns->priority_xon_rx[i]);
1210                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1211                                     pf->offset_loaded,
1212                                     &os->priority_xoff_rx[i],
1213                                     &ns->priority_xoff_rx[i]);
1214         }
1215         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1216                             pf->offset_loaded, &os->link_xon_tx,
1217                             &ns->link_xon_tx);
1218         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1219                             pf->offset_loaded, &os->link_xoff_tx,
1220                             &ns->link_xoff_tx);
1221         for (i = 0; i < 8; i++) {
1222                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1223                                     pf->offset_loaded,
1224                                     &os->priority_xon_tx[i],
1225                                     &ns->priority_xon_tx[i]);
1226                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1227                                     pf->offset_loaded,
1228                                     &os->priority_xoff_tx[i],
1229                                     &ns->priority_xoff_tx[i]);
1230                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1231                                     pf->offset_loaded,
1232                                     &os->priority_xon_2_xoff[i],
1233                                     &ns->priority_xon_2_xoff[i]);
1234         }
1235         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1236                             I40E_GLPRT_PRC64L(hw->port),
1237                             pf->offset_loaded, &os->rx_size_64,
1238                             &ns->rx_size_64);
1239         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1240                             I40E_GLPRT_PRC127L(hw->port),
1241                             pf->offset_loaded, &os->rx_size_127,
1242                             &ns->rx_size_127);
1243         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1244                             I40E_GLPRT_PRC255L(hw->port),
1245                             pf->offset_loaded, &os->rx_size_255,
1246                             &ns->rx_size_255);
1247         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1248                             I40E_GLPRT_PRC511L(hw->port),
1249                             pf->offset_loaded, &os->rx_size_511,
1250                             &ns->rx_size_511);
1251         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1252                             I40E_GLPRT_PRC1023L(hw->port),
1253                             pf->offset_loaded, &os->rx_size_1023,
1254                             &ns->rx_size_1023);
1255         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1256                             I40E_GLPRT_PRC1522L(hw->port),
1257                             pf->offset_loaded, &os->rx_size_1522,
1258                             &ns->rx_size_1522);
1259         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1260                             I40E_GLPRT_PRC9522L(hw->port),
1261                             pf->offset_loaded, &os->rx_size_big,
1262                             &ns->rx_size_big);
1263         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1264                             pf->offset_loaded, &os->rx_undersize,
1265                             &ns->rx_undersize);
1266         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1267                             pf->offset_loaded, &os->rx_fragments,
1268                             &ns->rx_fragments);
1269         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1270                             pf->offset_loaded, &os->rx_oversize,
1271                             &ns->rx_oversize);
1272         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1273                             pf->offset_loaded, &os->rx_jabber,
1274                             &ns->rx_jabber);
1275         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1276                             I40E_GLPRT_PTC64L(hw->port),
1277                             pf->offset_loaded, &os->tx_size_64,
1278                             &ns->tx_size_64);
1279         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1280                             I40E_GLPRT_PTC127L(hw->port),
1281                             pf->offset_loaded, &os->tx_size_127,
1282                             &ns->tx_size_127);
1283         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1284                             I40E_GLPRT_PTC255L(hw->port),
1285                             pf->offset_loaded, &os->tx_size_255,
1286                             &ns->tx_size_255);
1287         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1288                             I40E_GLPRT_PTC511L(hw->port),
1289                             pf->offset_loaded, &os->tx_size_511,
1290                             &ns->tx_size_511);
1291         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1292                             I40E_GLPRT_PTC1023L(hw->port),
1293                             pf->offset_loaded, &os->tx_size_1023,
1294                             &ns->tx_size_1023);
1295         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1296                             I40E_GLPRT_PTC1522L(hw->port),
1297                             pf->offset_loaded, &os->tx_size_1522,
1298                             &ns->tx_size_1522);
1299         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1300                             I40E_GLPRT_PTC9522L(hw->port),
1301                             pf->offset_loaded, &os->tx_size_big,
1302                             &ns->tx_size_big);
1303         /* GLPRT_MSPDC not supported */
1304         /* GLPRT_XEC not supported */
1305
1306         pf->offset_loaded = true;
1307
1308         if (pf->main_vsi)
1309                 i40e_update_vsi_stats(pf->main_vsi);
1310
1311         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1312                                                 ns->eth.rx_broadcast;
1313         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1314                                                 ns->eth.tx_broadcast;
1315         stats->ibytes   = ns->eth.rx_bytes;
1316         stats->obytes   = ns->eth.tx_bytes;
1317         stats->oerrors  = ns->eth.tx_errors;
1318         stats->imcasts  = ns->eth.rx_multicast;
1319
1320         /* Rx Errors */
1321         stats->ibadcrc  = ns->crc_errors;
1322         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1323                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1324         stats->imissed  = ns->eth.rx_discards;
1325         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1326
1327         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1328         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1329         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1330         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1331         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1332         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1333         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1334                     ns->eth.rx_unknown_protocol);
1335         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1336         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1337         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1338         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1339         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1340         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1341
1342         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1343                     ns->tx_dropped_link_down);
1344         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1345         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1346                     ns->illegal_bytes);
1347         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1348         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1349                     ns->mac_local_faults);
1350         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1351                     ns->mac_remote_faults);
1352         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1353                     ns->rx_length_errors);
1354         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1355         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1356         for (i = 0; i < 8; i++) {
1357                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1358                                 i, ns->priority_xon_rx[i]);
1359                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1360                                 i, ns->priority_xoff_rx[i]);
1361         }
1362         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1363         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1364         for (i = 0; i < 8; i++) {
1365                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1366                                 i, ns->priority_xon_tx[i]);
1367                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1368                                 i, ns->priority_xoff_tx[i]);
1369                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1370                                 i, ns->priority_xon_2_xoff[i]);
1371         }
1372         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1373         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1374         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1375         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1376         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1377         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1378         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1379         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1380         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1381         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1382         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1383         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1384         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1385         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1386         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1387         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1388         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1389         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1390         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1391                         ns->mac_short_packet_dropped);
1392         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1393                     ns->checksum_error);
1394         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1395 }
1396
1397 /* Reset the statistics */
1398 static void
1399 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1402
1403         /* It results in reloading the start point of each counter */
1404         pf->offset_loaded = false;
1405 }
1406
1407 static int
1408 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1409                                  __rte_unused uint16_t queue_id,
1410                                  __rte_unused uint8_t stat_idx,
1411                                  __rte_unused uint8_t is_rx)
1412 {
1413         PMD_INIT_FUNC_TRACE();
1414
1415         return -ENOSYS;
1416 }
1417
1418 static void
1419 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1420 {
1421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1422         struct i40e_vsi *vsi = pf->main_vsi;
1423
1424         dev_info->max_rx_queues = vsi->nb_qps;
1425         dev_info->max_tx_queues = vsi->nb_qps;
1426         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1427         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1428         dev_info->max_mac_addrs = vsi->max_macaddrs;
1429         dev_info->max_vfs = dev->pci_dev->max_vfs;
1430         dev_info->rx_offload_capa =
1431                 DEV_RX_OFFLOAD_VLAN_STRIP |
1432                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1433                 DEV_RX_OFFLOAD_UDP_CKSUM |
1434                 DEV_RX_OFFLOAD_TCP_CKSUM;
1435         dev_info->tx_offload_capa =
1436                 DEV_TX_OFFLOAD_VLAN_INSERT |
1437                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1438                 DEV_TX_OFFLOAD_UDP_CKSUM |
1439                 DEV_TX_OFFLOAD_TCP_CKSUM |
1440                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1441         dev_info->reta_size = pf->hash_lut_size;
1442
1443         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1444                 .rx_thresh = {
1445                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1446                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1447                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1448                 },
1449                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1450                 .rx_drop_en = 0,
1451         };
1452
1453         dev_info->default_txconf = (struct rte_eth_txconf) {
1454                 .tx_thresh = {
1455                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1456                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1457                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1458                 },
1459                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1460                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1461                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1462                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1463         };
1464
1465         if (pf->flags | I40E_FLAG_VMDQ) {
1466                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1467                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1468                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1469                                                 pf->max_nb_vmdq_vsi;
1470                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1471                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1472                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1473         }
1474 }
1475
1476 static int
1477 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1478 {
1479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1480         struct i40e_vsi *vsi = pf->main_vsi;
1481         PMD_INIT_FUNC_TRACE();
1482
1483         if (on)
1484                 return i40e_vsi_add_vlan(vsi, vlan_id);
1485         else
1486                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1487 }
1488
1489 static void
1490 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1491                    __rte_unused uint16_t tpid)
1492 {
1493         PMD_INIT_FUNC_TRACE();
1494 }
1495
1496 static void
1497 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1498 {
1499         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1500         struct i40e_vsi *vsi = pf->main_vsi;
1501
1502         if (mask & ETH_VLAN_STRIP_MASK) {
1503                 /* Enable or disable VLAN stripping */
1504                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1505                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1506                 else
1507                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1508         }
1509
1510         if (mask & ETH_VLAN_EXTEND_MASK) {
1511                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1512                         i40e_vsi_config_double_vlan(vsi, TRUE);
1513                 else
1514                         i40e_vsi_config_double_vlan(vsi, FALSE);
1515         }
1516 }
1517
1518 static void
1519 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1520                           __rte_unused uint16_t queue,
1521                           __rte_unused int on)
1522 {
1523         PMD_INIT_FUNC_TRACE();
1524 }
1525
1526 static int
1527 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1528 {
1529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1530         struct i40e_vsi *vsi = pf->main_vsi;
1531         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1532         struct i40e_vsi_vlan_pvid_info info;
1533
1534         memset(&info, 0, sizeof(info));
1535         info.on = on;
1536         if (info.on)
1537                 info.config.pvid = pvid;
1538         else {
1539                 info.config.reject.tagged =
1540                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1541                 info.config.reject.untagged =
1542                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1543         }
1544
1545         return i40e_vsi_vlan_pvid_set(vsi, &info);
1546 }
1547
1548 static int
1549 i40e_dev_led_on(struct rte_eth_dev *dev)
1550 {
1551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1552         uint32_t mode = i40e_led_get(hw);
1553
1554         if (mode == 0)
1555                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1556
1557         return 0;
1558 }
1559
1560 static int
1561 i40e_dev_led_off(struct rte_eth_dev *dev)
1562 {
1563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1564         uint32_t mode = i40e_led_get(hw);
1565
1566         if (mode != 0)
1567                 i40e_led_set(hw, 0, false);
1568
1569         return 0;
1570 }
1571
1572 static int
1573 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1574                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1575 {
1576         PMD_INIT_FUNC_TRACE();
1577
1578         return -ENOSYS;
1579 }
1580
1581 static int
1582 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1583                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1584 {
1585         PMD_INIT_FUNC_TRACE();
1586
1587         return -ENOSYS;
1588 }
1589
1590 /* Add a MAC address, and update filters */
1591 static void
1592 i40e_macaddr_add(struct rte_eth_dev *dev,
1593                  struct ether_addr *mac_addr,
1594                  __rte_unused uint32_t index,
1595                  uint32_t pool)
1596 {
1597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1598         struct i40e_mac_filter_info mac_filter;
1599         struct i40e_vsi *vsi;
1600         int ret;
1601
1602         /* If VMDQ not enabled or configured, return */
1603         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1604                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1605                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1606                         pool);
1607                 return;
1608         }
1609
1610         if (pool > pf->nb_cfg_vmdq_vsi) {
1611                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1612                                 pool, pf->nb_cfg_vmdq_vsi);
1613                 return;
1614         }
1615
1616         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1617         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1618
1619         if (pool == 0)
1620                 vsi = pf->main_vsi;
1621         else
1622                 vsi = pf->vmdq[pool - 1].vsi;
1623
1624         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1625         if (ret != I40E_SUCCESS) {
1626                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1627                 return;
1628         }
1629 }
1630
1631 /* Remove a MAC address, and update filters */
1632 static void
1633 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1634 {
1635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1636         struct i40e_vsi *vsi;
1637         struct rte_eth_dev_data *data = dev->data;
1638         struct ether_addr *macaddr;
1639         int ret;
1640         uint32_t i;
1641         uint64_t pool_sel;
1642
1643         macaddr = &(data->mac_addrs[index]);
1644
1645         pool_sel = dev->data->mac_pool_sel[index];
1646
1647         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1648                 if (pool_sel & (1ULL << i)) {
1649                         if (i == 0)
1650                                 vsi = pf->main_vsi;
1651                         else {
1652                                 /* No VMDQ pool enabled or configured */
1653                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1654                                         (i > pf->nb_cfg_vmdq_vsi)) {
1655                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1656                                                         "/configured");
1657                                         return;
1658                                 }
1659                                 vsi = pf->vmdq[i - 1].vsi;
1660                         }
1661                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1662
1663                         if (ret) {
1664                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1665                                 return;
1666                         }
1667                 }
1668         }
1669 }
1670
1671 /* Set perfect match or hash match of MAC and VLAN for a VF */
1672 static int
1673 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1674                  struct rte_eth_mac_filter *filter,
1675                  bool add)
1676 {
1677         struct i40e_hw *hw;
1678         struct i40e_mac_filter_info mac_filter;
1679         struct ether_addr old_mac;
1680         struct ether_addr *new_mac;
1681         struct i40e_pf_vf *vf = NULL;
1682         uint16_t vf_id;
1683         int ret;
1684
1685         if (pf == NULL) {
1686                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1687                 return -EINVAL;
1688         }
1689         hw = I40E_PF_TO_HW(pf);
1690
1691         if (filter == NULL) {
1692                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1693                 return -EINVAL;
1694         }
1695
1696         new_mac = &filter->mac_addr;
1697
1698         if (is_zero_ether_addr(new_mac)) {
1699                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1700                 return -EINVAL;
1701         }
1702
1703         vf_id = filter->dst_id;
1704
1705         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1706                 PMD_DRV_LOG(ERR, "Invalid argument.");
1707                 return -EINVAL;
1708         }
1709         vf = &pf->vfs[vf_id];
1710
1711         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1712                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1713                 return -EINVAL;
1714         }
1715
1716         if (add) {
1717                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1718                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1719                                 ETHER_ADDR_LEN);
1720                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1721                                  ETHER_ADDR_LEN);
1722
1723                 mac_filter.filter_type = filter->filter_type;
1724                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1725                 if (ret != I40E_SUCCESS) {
1726                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1727                         return -1;
1728                 }
1729                 ether_addr_copy(new_mac, &pf->dev_addr);
1730         } else {
1731                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1732                                 ETHER_ADDR_LEN);
1733                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1734                 if (ret != I40E_SUCCESS) {
1735                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1736                         return -1;
1737                 }
1738
1739                 /* Clear device address as it has been removed */
1740                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1741                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1742         }
1743
1744         return 0;
1745 }
1746
1747 /* MAC filter handle */
1748 static int
1749 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1750                 void *arg)
1751 {
1752         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1753         struct rte_eth_mac_filter *filter;
1754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1755         int ret = I40E_NOT_SUPPORTED;
1756
1757         filter = (struct rte_eth_mac_filter *)(arg);
1758
1759         switch (filter_op) {
1760         case RTE_ETH_FILTER_NOP:
1761                 ret = I40E_SUCCESS;
1762                 break;
1763         case RTE_ETH_FILTER_ADD:
1764                 i40e_pf_disable_irq0(hw);
1765                 if (filter->is_vf)
1766                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1767                 i40e_pf_enable_irq0(hw);
1768                 break;
1769         case RTE_ETH_FILTER_DELETE:
1770                 i40e_pf_disable_irq0(hw);
1771                 if (filter->is_vf)
1772                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1773                 i40e_pf_enable_irq0(hw);
1774                 break;
1775         default:
1776                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1777                 ret = I40E_ERR_PARAM;
1778                 break;
1779         }
1780
1781         return ret;
1782 }
1783
1784 static int
1785 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1786                          struct rte_eth_rss_reta_entry64 *reta_conf,
1787                          uint16_t reta_size)
1788 {
1789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1791         uint32_t lut, l;
1792         uint16_t i, j, lut_size = pf->hash_lut_size;
1793         uint16_t idx, shift;
1794         uint8_t mask;
1795
1796         if (reta_size != lut_size ||
1797                 reta_size > ETH_RSS_RETA_SIZE_512) {
1798                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1799                         "(%d) doesn't match the number hardware can supported "
1800                                         "(%d)\n", reta_size, lut_size);
1801                 return -EINVAL;
1802         }
1803
1804         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1805                 idx = i / RTE_RETA_GROUP_SIZE;
1806                 shift = i % RTE_RETA_GROUP_SIZE;
1807                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1808                                                 I40E_4_BIT_MASK);
1809                 if (!mask)
1810                         continue;
1811                 if (mask == I40E_4_BIT_MASK)
1812                         l = 0;
1813                 else
1814                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1815                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1816                         if (mask & (0x1 << j))
1817                                 lut |= reta_conf[idx].reta[shift + j] <<
1818                                                         (CHAR_BIT * j);
1819                         else
1820                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1821                 }
1822                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1823         }
1824
1825         return 0;
1826 }
1827
1828 static int
1829 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1830                         struct rte_eth_rss_reta_entry64 *reta_conf,
1831                         uint16_t reta_size)
1832 {
1833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         uint32_t lut;
1836         uint16_t i, j, lut_size = pf->hash_lut_size;
1837         uint16_t idx, shift;
1838         uint8_t mask;
1839
1840         if (reta_size != lut_size ||
1841                 reta_size > ETH_RSS_RETA_SIZE_512) {
1842                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1843                         "(%d) doesn't match the number hardware can supported "
1844                                         "(%d)\n", reta_size, lut_size);
1845                 return -EINVAL;
1846         }
1847
1848         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1849                 idx = i / RTE_RETA_GROUP_SIZE;
1850                 shift = i % RTE_RETA_GROUP_SIZE;
1851                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1852                                                 I40E_4_BIT_MASK);
1853                 if (!mask)
1854                         continue;
1855
1856                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1857                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1858                         if (mask & (0x1 << j))
1859                                 reta_conf[idx].reta[shift] = ((lut >>
1860                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1861                 }
1862         }
1863
1864         return 0;
1865 }
1866
1867 /**
1868  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1869  * @hw:   pointer to the HW structure
1870  * @mem:  pointer to mem struct to fill out
1871  * @size: size of memory requested
1872  * @alignment: what to align the allocation to
1873  **/
1874 enum i40e_status_code
1875 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1876                         struct i40e_dma_mem *mem,
1877                         u64 size,
1878                         u32 alignment)
1879 {
1880         static uint64_t id = 0;
1881         const struct rte_memzone *mz = NULL;
1882         char z_name[RTE_MEMZONE_NAMESIZE];
1883
1884         if (!mem)
1885                 return I40E_ERR_PARAM;
1886
1887         id++;
1888         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1889 #ifdef RTE_LIBRTE_XEN_DOM0
1890         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1891                                                         RTE_PGSIZE_2M);
1892 #else
1893         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1894 #endif
1895         if (!mz)
1896                 return I40E_ERR_NO_MEMORY;
1897
1898         mem->id = id;
1899         mem->size = size;
1900         mem->va = mz->addr;
1901 #ifdef RTE_LIBRTE_XEN_DOM0
1902         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1903 #else
1904         mem->pa = mz->phys_addr;
1905 #endif
1906
1907         return I40E_SUCCESS;
1908 }
1909
1910 /**
1911  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1912  * @hw:   pointer to the HW structure
1913  * @mem:  ptr to mem struct to free
1914  **/
1915 enum i40e_status_code
1916 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1917                     struct i40e_dma_mem *mem)
1918 {
1919         if (!mem || !mem->va)
1920                 return I40E_ERR_PARAM;
1921
1922         mem->va = NULL;
1923         mem->pa = (u64)0;
1924
1925         return I40E_SUCCESS;
1926 }
1927
1928 /**
1929  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1930  * @hw:   pointer to the HW structure
1931  * @mem:  pointer to mem struct to fill out
1932  * @size: size of memory requested
1933  **/
1934 enum i40e_status_code
1935 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1936                          struct i40e_virt_mem *mem,
1937                          u32 size)
1938 {
1939         if (!mem)
1940                 return I40E_ERR_PARAM;
1941
1942         mem->size = size;
1943         mem->va = rte_zmalloc("i40e", size, 0);
1944
1945         if (mem->va)
1946                 return I40E_SUCCESS;
1947         else
1948                 return I40E_ERR_NO_MEMORY;
1949 }
1950
1951 /**
1952  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1953  * @hw:   pointer to the HW structure
1954  * @mem:  pointer to mem struct to free
1955  **/
1956 enum i40e_status_code
1957 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1958                      struct i40e_virt_mem *mem)
1959 {
1960         if (!mem)
1961                 return I40E_ERR_PARAM;
1962
1963         rte_free(mem->va);
1964         mem->va = NULL;
1965
1966         return I40E_SUCCESS;
1967 }
1968
1969 void
1970 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1971 {
1972         rte_spinlock_init(&sp->spinlock);
1973 }
1974
1975 void
1976 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1977 {
1978         rte_spinlock_lock(&sp->spinlock);
1979 }
1980
1981 void
1982 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1983 {
1984         rte_spinlock_unlock(&sp->spinlock);
1985 }
1986
1987 void
1988 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1989 {
1990         return;
1991 }
1992
1993 /**
1994  * Get the hardware capabilities, which will be parsed
1995  * and saved into struct i40e_hw.
1996  */
1997 static int
1998 i40e_get_cap(struct i40e_hw *hw)
1999 {
2000         struct i40e_aqc_list_capabilities_element_resp *buf;
2001         uint16_t len, size = 0;
2002         int ret;
2003
2004         /* Calculate a huge enough buff for saving response data temporarily */
2005         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2006                                                 I40E_MAX_CAP_ELE_NUM;
2007         buf = rte_zmalloc("i40e", len, 0);
2008         if (!buf) {
2009                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2010                 return I40E_ERR_NO_MEMORY;
2011         }
2012
2013         /* Get, parse the capabilities and save it to hw */
2014         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2015                         i40e_aqc_opc_list_func_capabilities, NULL);
2016         if (ret != I40E_SUCCESS)
2017                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2018
2019         /* Free the temporary buffer after being used */
2020         rte_free(buf);
2021
2022         return ret;
2023 }
2024
2025 static int
2026 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2027 {
2028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2029         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2030         uint16_t sum_queues = 0, sum_vsis, left_queues;
2031
2032         /* First check if FW support SRIOV */
2033         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2034                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2035                 return -EINVAL;
2036         }
2037
2038         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2039         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2040         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2041         /* Allocate queues for pf */
2042         if (hw->func_caps.rss) {
2043                 pf->flags |= I40E_FLAG_RSS;
2044                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2045                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2046                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2047         } else
2048                 pf->lan_nb_qps = 1;
2049         sum_queues = pf->lan_nb_qps;
2050         /* Default VSI is not counted in */
2051         sum_vsis = 0;
2052         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2053
2054         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2055                 pf->flags |= I40E_FLAG_SRIOV;
2056                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2057                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2058                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2059                                      "max supported %u.",
2060                                      dev->pci_dev->max_vfs,
2061                                      hw->func_caps.num_vfs);
2062                         return -EINVAL;
2063                 }
2064                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2065                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2066                                      "max support %u queues.",
2067                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2068                         return -EINVAL;
2069                 }
2070                 pf->vf_num = dev->pci_dev->max_vfs;
2071                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2072                 sum_vsis   += pf->vf_num;
2073                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2074                              pf->vf_num, pf->vf_nb_qps);
2075         } else
2076                 pf->vf_num = 0;
2077
2078         if (hw->func_caps.vmdq) {
2079                 pf->flags |= I40E_FLAG_VMDQ;
2080                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2081                 pf->max_nb_vmdq_vsi = 1;
2082                 /*
2083                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2084                  * later.
2085                  */
2086                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2087                 sum_vsis += pf->max_nb_vmdq_vsi;
2088         } else {
2089                 pf->vmdq_nb_qps = 0;
2090                 pf->max_nb_vmdq_vsi = 0;
2091         }
2092         pf->nb_cfg_vmdq_vsi = 0;
2093
2094         if (hw->func_caps.fd) {
2095                 pf->flags |= I40E_FLAG_FDIR;
2096                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2097                 /**
2098                  * Each flow director consumes one VSI and one queue,
2099                  * but can't calculate out predictably here.
2100                  */
2101         }
2102
2103         if (sum_vsis > pf->max_num_vsi ||
2104                 sum_queues > hw->func_caps.num_rx_qp) {
2105                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2106                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2107                              pf->max_num_vsi, sum_vsis);
2108                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2109                              hw->func_caps.num_rx_qp, sum_queues);
2110                 return -EINVAL;
2111         }
2112
2113         /* Adjust VMDQ setting to support as many VMs as possible */
2114         if (pf->flags & I40E_FLAG_VMDQ) {
2115                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2116
2117                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2118                                         pf->max_num_vsi - sum_vsis);
2119
2120                 /* Limit the max VMDQ number that rte_ether that can support  */
2121                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2122                                         ETH_64_POOLS - 1);
2123
2124                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2125                                 pf->max_nb_vmdq_vsi);
2126                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2127         }
2128
2129         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2130          * cause */
2131         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2132                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2133                              sum_vsis, hw->func_caps.num_msix_vectors);
2134                 return -EINVAL;
2135         }
2136         return I40E_SUCCESS;
2137 }
2138
2139 static int
2140 i40e_pf_get_switch_config(struct i40e_pf *pf)
2141 {
2142         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2143         struct i40e_aqc_get_switch_config_resp *switch_config;
2144         struct i40e_aqc_switch_config_element_resp *element;
2145         uint16_t start_seid = 0, num_reported;
2146         int ret;
2147
2148         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2149                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2150         if (!switch_config) {
2151                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2152                 return -ENOMEM;
2153         }
2154
2155         /* Get the switch configurations */
2156         ret = i40e_aq_get_switch_config(hw, switch_config,
2157                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2158         if (ret != I40E_SUCCESS) {
2159                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2160                 goto fail;
2161         }
2162         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2163         if (num_reported != 1) { /* The number should be 1 */
2164                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2165                 goto fail;
2166         }
2167
2168         /* Parse the switch configuration elements */
2169         element = &(switch_config->element[0]);
2170         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2171                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2172                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2173         } else
2174                 PMD_DRV_LOG(INFO, "Unknown element type");
2175
2176 fail:
2177         rte_free(switch_config);
2178
2179         return ret;
2180 }
2181
2182 static int
2183 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2184                         uint32_t num)
2185 {
2186         struct pool_entry *entry;
2187
2188         if (pool == NULL || num == 0)
2189                 return -EINVAL;
2190
2191         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2192         if (entry == NULL) {
2193                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2194                 return -ENOMEM;
2195         }
2196
2197         /* queue heap initialize */
2198         pool->num_free = num;
2199         pool->num_alloc = 0;
2200         pool->base = base;
2201         LIST_INIT(&pool->alloc_list);
2202         LIST_INIT(&pool->free_list);
2203
2204         /* Initialize element  */
2205         entry->base = 0;
2206         entry->len = num;
2207
2208         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2209         return 0;
2210 }
2211
2212 static void
2213 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2214 {
2215         struct pool_entry *entry;
2216
2217         if (pool == NULL)
2218                 return;
2219
2220         LIST_FOREACH(entry, &pool->alloc_list, next) {
2221                 LIST_REMOVE(entry, next);
2222                 rte_free(entry);
2223         }
2224
2225         LIST_FOREACH(entry, &pool->free_list, next) {
2226                 LIST_REMOVE(entry, next);
2227                 rte_free(entry);
2228         }
2229
2230         pool->num_free = 0;
2231         pool->num_alloc = 0;
2232         pool->base = 0;
2233         LIST_INIT(&pool->alloc_list);
2234         LIST_INIT(&pool->free_list);
2235 }
2236
2237 static int
2238 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2239                        uint32_t base)
2240 {
2241         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2242         uint32_t pool_offset;
2243         int insert;
2244
2245         if (pool == NULL) {
2246                 PMD_DRV_LOG(ERR, "Invalid parameter");
2247                 return -EINVAL;
2248         }
2249
2250         pool_offset = base - pool->base;
2251         /* Lookup in alloc list */
2252         LIST_FOREACH(entry, &pool->alloc_list, next) {
2253                 if (entry->base == pool_offset) {
2254                         valid_entry = entry;
2255                         LIST_REMOVE(entry, next);
2256                         break;
2257                 }
2258         }
2259
2260         /* Not find, return */
2261         if (valid_entry == NULL) {
2262                 PMD_DRV_LOG(ERR, "Failed to find entry");
2263                 return -EINVAL;
2264         }
2265
2266         /**
2267          * Found it, move it to free list  and try to merge.
2268          * In order to make merge easier, always sort it by qbase.
2269          * Find adjacent prev and last entries.
2270          */
2271         prev = next = NULL;
2272         LIST_FOREACH(entry, &pool->free_list, next) {
2273                 if (entry->base > valid_entry->base) {
2274                         next = entry;
2275                         break;
2276                 }
2277                 prev = entry;
2278         }
2279
2280         insert = 0;
2281         /* Try to merge with next one*/
2282         if (next != NULL) {
2283                 /* Merge with next one */
2284                 if (valid_entry->base + valid_entry->len == next->base) {
2285                         next->base = valid_entry->base;
2286                         next->len += valid_entry->len;
2287                         rte_free(valid_entry);
2288                         valid_entry = next;
2289                         insert = 1;
2290                 }
2291         }
2292
2293         if (prev != NULL) {
2294                 /* Merge with previous one */
2295                 if (prev->base + prev->len == valid_entry->base) {
2296                         prev->len += valid_entry->len;
2297                         /* If it merge with next one, remove next node */
2298                         if (insert == 1) {
2299                                 LIST_REMOVE(valid_entry, next);
2300                                 rte_free(valid_entry);
2301                         } else {
2302                                 rte_free(valid_entry);
2303                                 insert = 1;
2304                         }
2305                 }
2306         }
2307
2308         /* Not find any entry to merge, insert */
2309         if (insert == 0) {
2310                 if (prev != NULL)
2311                         LIST_INSERT_AFTER(prev, valid_entry, next);
2312                 else if (next != NULL)
2313                         LIST_INSERT_BEFORE(next, valid_entry, next);
2314                 else /* It's empty list, insert to head */
2315                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2316         }
2317
2318         pool->num_free += valid_entry->len;
2319         pool->num_alloc -= valid_entry->len;
2320
2321         return 0;
2322 }
2323
2324 static int
2325 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2326                        uint16_t num)
2327 {
2328         struct pool_entry *entry, *valid_entry;
2329
2330         if (pool == NULL || num == 0) {
2331                 PMD_DRV_LOG(ERR, "Invalid parameter");
2332                 return -EINVAL;
2333         }
2334
2335         if (pool->num_free < num) {
2336                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2337                             num, pool->num_free);
2338                 return -ENOMEM;
2339         }
2340
2341         valid_entry = NULL;
2342         /* Lookup  in free list and find most fit one */
2343         LIST_FOREACH(entry, &pool->free_list, next) {
2344                 if (entry->len >= num) {
2345                         /* Find best one */
2346                         if (entry->len == num) {
2347                                 valid_entry = entry;
2348                                 break;
2349                         }
2350                         if (valid_entry == NULL || valid_entry->len > entry->len)
2351                                 valid_entry = entry;
2352                 }
2353         }
2354
2355         /* Not find one to satisfy the request, return */
2356         if (valid_entry == NULL) {
2357                 PMD_DRV_LOG(ERR, "No valid entry found");
2358                 return -ENOMEM;
2359         }
2360         /**
2361          * The entry have equal queue number as requested,
2362          * remove it from alloc_list.
2363          */
2364         if (valid_entry->len == num) {
2365                 LIST_REMOVE(valid_entry, next);
2366         } else {
2367                 /**
2368                  * The entry have more numbers than requested,
2369                  * create a new entry for alloc_list and minus its
2370                  * queue base and number in free_list.
2371                  */
2372                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2373                 if (entry == NULL) {
2374                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2375                                     "resource pool");
2376                         return -ENOMEM;
2377                 }
2378                 entry->base = valid_entry->base;
2379                 entry->len = num;
2380                 valid_entry->base += num;
2381                 valid_entry->len -= num;
2382                 valid_entry = entry;
2383         }
2384
2385         /* Insert it into alloc list, not sorted */
2386         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2387
2388         pool->num_free -= valid_entry->len;
2389         pool->num_alloc += valid_entry->len;
2390
2391         return (valid_entry->base + pool->base);
2392 }
2393
2394 /**
2395  * bitmap_is_subset - Check whether src2 is subset of src1
2396  **/
2397 static inline int
2398 bitmap_is_subset(uint8_t src1, uint8_t src2)
2399 {
2400         return !((src1 ^ src2) & src2);
2401 }
2402
2403 static int
2404 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2405 {
2406         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2407
2408         /* If DCB is not supported, only default TC is supported */
2409         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2410                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2411                 return -EINVAL;
2412         }
2413
2414         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2415                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2416                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2417                             enabled_tcmap);
2418                 return -EINVAL;
2419         }
2420         return I40E_SUCCESS;
2421 }
2422
2423 int
2424 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2425                                 struct i40e_vsi_vlan_pvid_info *info)
2426 {
2427         struct i40e_hw *hw;
2428         struct i40e_vsi_context ctxt;
2429         uint8_t vlan_flags = 0;
2430         int ret;
2431
2432         if (vsi == NULL || info == NULL) {
2433                 PMD_DRV_LOG(ERR, "invalid parameters");
2434                 return I40E_ERR_PARAM;
2435         }
2436
2437         if (info->on) {
2438                 vsi->info.pvid = info->config.pvid;
2439                 /**
2440                  * If insert pvid is enabled, only tagged pkts are
2441                  * allowed to be sent out.
2442                  */
2443                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2444                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2445         } else {
2446                 vsi->info.pvid = 0;
2447                 if (info->config.reject.tagged == 0)
2448                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2449
2450                 if (info->config.reject.untagged == 0)
2451                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2452         }
2453         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2454                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2455         vsi->info.port_vlan_flags |= vlan_flags;
2456         vsi->info.valid_sections =
2457                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2458         memset(&ctxt, 0, sizeof(ctxt));
2459         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2460         ctxt.seid = vsi->seid;
2461
2462         hw = I40E_VSI_TO_HW(vsi);
2463         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2464         if (ret != I40E_SUCCESS)
2465                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2466
2467         return ret;
2468 }
2469
2470 static int
2471 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2472 {
2473         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2474         int i, ret;
2475         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2476
2477         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2478         if (ret != I40E_SUCCESS)
2479                 return ret;
2480
2481         if (!vsi->seid) {
2482                 PMD_DRV_LOG(ERR, "seid not valid");
2483                 return -EINVAL;
2484         }
2485
2486         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2487         tc_bw_data.tc_valid_bits = enabled_tcmap;
2488         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2489                 tc_bw_data.tc_bw_credits[i] =
2490                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2491
2492         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2493         if (ret != I40E_SUCCESS) {
2494                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2495                 return ret;
2496         }
2497
2498         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2499                                         sizeof(vsi->info.qs_handle));
2500         return I40E_SUCCESS;
2501 }
2502
2503 static int
2504 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2505                                  struct i40e_aqc_vsi_properties_data *info,
2506                                  uint8_t enabled_tcmap)
2507 {
2508         int ret, total_tc = 0, i;
2509         uint16_t qpnum_per_tc, bsf, qp_idx;
2510
2511         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2512         if (ret != I40E_SUCCESS)
2513                 return ret;
2514
2515         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2516                 if (enabled_tcmap & (1 << i))
2517                         total_tc++;
2518         vsi->enabled_tc = enabled_tcmap;
2519
2520         /* Number of queues per enabled TC */
2521         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2522         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2523         bsf = rte_bsf32(qpnum_per_tc);
2524
2525         /* Adjust the queue number to actual queues that can be applied */
2526         vsi->nb_qps = qpnum_per_tc * total_tc;
2527
2528         /**
2529          * Configure TC and queue mapping parameters, for enabled TC,
2530          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2531          * default queue will serve it.
2532          */
2533         qp_idx = 0;
2534         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2535                 if (vsi->enabled_tc & (1 << i)) {
2536                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2537                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2538                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2539                         qp_idx += qpnum_per_tc;
2540                 } else
2541                         info->tc_mapping[i] = 0;
2542         }
2543
2544         /* Associate queue number with VSI */
2545         if (vsi->type == I40E_VSI_SRIOV) {
2546                 info->mapping_flags |=
2547                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2548                 for (i = 0; i < vsi->nb_qps; i++)
2549                         info->queue_mapping[i] =
2550                                 rte_cpu_to_le_16(vsi->base_queue + i);
2551         } else {
2552                 info->mapping_flags |=
2553                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2554                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2555         }
2556         info->valid_sections =
2557                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2558
2559         return I40E_SUCCESS;
2560 }
2561
2562 static int
2563 i40e_veb_release(struct i40e_veb *veb)
2564 {
2565         struct i40e_vsi *vsi;
2566         struct i40e_hw *hw;
2567
2568         if (veb == NULL || veb->associate_vsi == NULL)
2569                 return -EINVAL;
2570
2571         if (!TAILQ_EMPTY(&veb->head)) {
2572                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2573                 return -EACCES;
2574         }
2575
2576         vsi = veb->associate_vsi;
2577         hw = I40E_VSI_TO_HW(vsi);
2578
2579         vsi->uplink_seid = veb->uplink_seid;
2580         i40e_aq_delete_element(hw, veb->seid, NULL);
2581         rte_free(veb);
2582         vsi->veb = NULL;
2583         return I40E_SUCCESS;
2584 }
2585
2586 /* Setup a veb */
2587 static struct i40e_veb *
2588 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2589 {
2590         struct i40e_veb *veb;
2591         int ret;
2592         struct i40e_hw *hw;
2593
2594         if (NULL == pf || vsi == NULL) {
2595                 PMD_DRV_LOG(ERR, "veb setup failed, "
2596                             "associated VSI shouldn't null");
2597                 return NULL;
2598         }
2599         hw = I40E_PF_TO_HW(pf);
2600
2601         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2602         if (!veb) {
2603                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2604                 goto fail;
2605         }
2606
2607         veb->associate_vsi = vsi;
2608         TAILQ_INIT(&veb->head);
2609         veb->uplink_seid = vsi->uplink_seid;
2610
2611         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2612                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2613
2614         if (ret != I40E_SUCCESS) {
2615                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2616                             hw->aq.asq_last_status);
2617                 goto fail;
2618         }
2619
2620         /* get statistics index */
2621         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2622                                 &veb->stats_idx, NULL, NULL, NULL);
2623         if (ret != I40E_SUCCESS) {
2624                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2625                             hw->aq.asq_last_status);
2626                 goto fail;
2627         }
2628
2629         /* Get VEB bandwidth, to be implemented */
2630         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2631         vsi->uplink_seid = veb->seid;
2632
2633         return veb;
2634 fail:
2635         rte_free(veb);
2636         return NULL;
2637 }
2638
2639 int
2640 i40e_vsi_release(struct i40e_vsi *vsi)
2641 {
2642         struct i40e_pf *pf;
2643         struct i40e_hw *hw;
2644         struct i40e_vsi_list *vsi_list;
2645         int ret;
2646         struct i40e_mac_filter *f;
2647
2648         if (!vsi)
2649                 return I40E_SUCCESS;
2650
2651         pf = I40E_VSI_TO_PF(vsi);
2652         hw = I40E_VSI_TO_HW(vsi);
2653
2654         /* VSI has child to attach, release child first */
2655         if (vsi->veb) {
2656                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2657                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2658                                 return -1;
2659                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2660                 }
2661                 i40e_veb_release(vsi->veb);
2662         }
2663
2664         /* Remove all macvlan filters of the VSI */
2665         i40e_vsi_remove_all_macvlan_filter(vsi);
2666         TAILQ_FOREACH(f, &vsi->mac_list, next)
2667                 rte_free(f);
2668
2669         if (vsi->type != I40E_VSI_MAIN) {
2670                 /* Remove vsi from parent's sibling list */
2671                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2672                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2673                         return I40E_ERR_PARAM;
2674                 }
2675                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2676                                 &vsi->sib_vsi_list, list);
2677
2678                 /* Remove all switch element of the VSI */
2679                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2680                 if (ret != I40E_SUCCESS)
2681                         PMD_DRV_LOG(ERR, "Failed to delete element");
2682         }
2683         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2684
2685         if (vsi->type != I40E_VSI_SRIOV)
2686                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2687         rte_free(vsi);
2688
2689         return I40E_SUCCESS;
2690 }
2691
2692 static int
2693 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2694 {
2695         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2696         struct i40e_aqc_remove_macvlan_element_data def_filter;
2697         struct i40e_mac_filter_info filter;
2698         int ret;
2699
2700         if (vsi->type != I40E_VSI_MAIN)
2701                 return I40E_ERR_CONFIG;
2702         memset(&def_filter, 0, sizeof(def_filter));
2703         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2704                                         ETH_ADDR_LEN);
2705         def_filter.vlan_tag = 0;
2706         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2707                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2708         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2709         if (ret != I40E_SUCCESS) {
2710                 struct i40e_mac_filter *f;
2711                 struct ether_addr *mac;
2712
2713                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2714                             "macvlan filter");
2715                 /* It needs to add the permanent mac into mac list */
2716                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2717                 if (f == NULL) {
2718                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2719                         return I40E_ERR_NO_MEMORY;
2720                 }
2721                 mac = &f->mac_info.mac_addr;
2722                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2723                                 ETH_ADDR_LEN);
2724                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2725                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2726                 vsi->mac_num++;
2727
2728                 return ret;
2729         }
2730         (void)rte_memcpy(&filter.mac_addr,
2731                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2732         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2733         return i40e_vsi_add_mac(vsi, &filter);
2734 }
2735
2736 static int
2737 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2738 {
2739         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2740         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2741         struct i40e_hw *hw = &vsi->adapter->hw;
2742         i40e_status ret;
2743         int i;
2744
2745         memset(&bw_config, 0, sizeof(bw_config));
2746         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2747         if (ret != I40E_SUCCESS) {
2748                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2749                             hw->aq.asq_last_status);
2750                 return ret;
2751         }
2752
2753         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2754         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2755                                         &ets_sla_config, NULL);
2756         if (ret != I40E_SUCCESS) {
2757                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2758                             "configuration %u", hw->aq.asq_last_status);
2759                 return ret;
2760         }
2761
2762         /* Not store the info yet, just print out */
2763         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2764         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2765         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2766                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2767                             ets_sla_config.share_credits[i]);
2768                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2769                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2770                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2771                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2772                             (i * 4));
2773         }
2774
2775         return 0;
2776 }
2777
2778 /* Setup a VSI */
2779 struct i40e_vsi *
2780 i40e_vsi_setup(struct i40e_pf *pf,
2781                enum i40e_vsi_type type,
2782                struct i40e_vsi *uplink_vsi,
2783                uint16_t user_param)
2784 {
2785         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2786         struct i40e_vsi *vsi;
2787         struct i40e_mac_filter_info filter;
2788         int ret;
2789         struct i40e_vsi_context ctxt;
2790         struct ether_addr broadcast =
2791                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2792
2793         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2794                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2795                             "VSI link shouldn't be NULL");
2796                 return NULL;
2797         }
2798
2799         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2800                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2801                             "uplink VSI should be NULL");
2802                 return NULL;
2803         }
2804
2805         /* If uplink vsi didn't setup VEB, create one first */
2806         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2807                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2808
2809                 if (NULL == uplink_vsi->veb) {
2810                         PMD_DRV_LOG(ERR, "VEB setup failed");
2811                         return NULL;
2812                 }
2813         }
2814
2815         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2816         if (!vsi) {
2817                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2818                 return NULL;
2819         }
2820         TAILQ_INIT(&vsi->mac_list);
2821         vsi->type = type;
2822         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2823         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2824         vsi->parent_vsi = uplink_vsi;
2825         vsi->user_param = user_param;
2826         /* Allocate queues */
2827         switch (vsi->type) {
2828         case I40E_VSI_MAIN  :
2829                 vsi->nb_qps = pf->lan_nb_qps;
2830                 break;
2831         case I40E_VSI_SRIOV :
2832                 vsi->nb_qps = pf->vf_nb_qps;
2833                 break;
2834         case I40E_VSI_VMDQ2:
2835                 vsi->nb_qps = pf->vmdq_nb_qps;
2836                 break;
2837         case I40E_VSI_FDIR:
2838                 vsi->nb_qps = pf->fdir_nb_qps;
2839                 break;
2840         default:
2841                 goto fail_mem;
2842         }
2843         /*
2844          * The filter status descriptor is reported in rx queue 0,
2845          * while the tx queue for fdir filter programming has no
2846          * such constraints, can be non-zero queues.
2847          * To simplify it, choose FDIR vsi use queue 0 pair.
2848          * To make sure it will use queue 0 pair, queue allocation
2849          * need be done before this function is called
2850          */
2851         if (type != I40E_VSI_FDIR) {
2852                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2853                         if (ret < 0) {
2854                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2855                                                 vsi->seid, ret);
2856                                 goto fail_mem;
2857                         }
2858                         vsi->base_queue = ret;
2859         } else
2860                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2861
2862         /* VF has MSIX interrupt in VF range, don't allocate here */
2863         if (type != I40E_VSI_SRIOV) {
2864                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2865                 if (ret < 0) {
2866                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2867                         goto fail_queue_alloc;
2868                 }
2869                 vsi->msix_intr = ret;
2870         } else
2871                 vsi->msix_intr = 0;
2872         /* Add VSI */
2873         if (type == I40E_VSI_MAIN) {
2874                 /* For main VSI, no need to add since it's default one */
2875                 vsi->uplink_seid = pf->mac_seid;
2876                 vsi->seid = pf->main_vsi_seid;
2877                 /* Bind queues with specific MSIX interrupt */
2878                 /**
2879                  * Needs 2 interrupt at least, one for misc cause which will
2880                  * enabled from OS side, Another for queues binding the
2881                  * interrupt from device side only.
2882                  */
2883
2884                 /* Get default VSI parameters from hardware */
2885                 memset(&ctxt, 0, sizeof(ctxt));
2886                 ctxt.seid = vsi->seid;
2887                 ctxt.pf_num = hw->pf_id;
2888                 ctxt.uplink_seid = vsi->uplink_seid;
2889                 ctxt.vf_num = 0;
2890                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2891                 if (ret != I40E_SUCCESS) {
2892                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2893                         goto fail_msix_alloc;
2894                 }
2895                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2896                         sizeof(struct i40e_aqc_vsi_properties_data));
2897                 vsi->vsi_id = ctxt.vsi_number;
2898                 vsi->info.valid_sections = 0;
2899
2900                 /* Configure tc, enabled TC0 only */
2901                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2902                         I40E_SUCCESS) {
2903                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2904                         goto fail_msix_alloc;
2905                 }
2906
2907                 /* TC, queue mapping */
2908                 memset(&ctxt, 0, sizeof(ctxt));
2909                 vsi->info.valid_sections |=
2910                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2911                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2912                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2913                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2914                         sizeof(struct i40e_aqc_vsi_properties_data));
2915                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2916                                                 I40E_DEFAULT_TCMAP);
2917                 if (ret != I40E_SUCCESS) {
2918                         PMD_DRV_LOG(ERR, "Failed to configure "
2919                                     "TC queue mapping");
2920                         goto fail_msix_alloc;
2921                 }
2922                 ctxt.seid = vsi->seid;
2923                 ctxt.pf_num = hw->pf_id;
2924                 ctxt.uplink_seid = vsi->uplink_seid;
2925                 ctxt.vf_num = 0;
2926
2927                 /* Update VSI parameters */
2928                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2929                 if (ret != I40E_SUCCESS) {
2930                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2931                         goto fail_msix_alloc;
2932                 }
2933
2934                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2935                                                 sizeof(vsi->info.tc_mapping));
2936                 (void)rte_memcpy(&vsi->info.queue_mapping,
2937                                 &ctxt.info.queue_mapping,
2938                         sizeof(vsi->info.queue_mapping));
2939                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2940                 vsi->info.valid_sections = 0;
2941
2942                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2943                                 ETH_ADDR_LEN);
2944
2945                 /**
2946                  * Updating default filter settings are necessary to prevent
2947                  * reception of tagged packets.
2948                  * Some old firmware configurations load a default macvlan
2949                  * filter which accepts both tagged and untagged packets.
2950                  * The updating is to use a normal filter instead if needed.
2951                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2952                  * The firmware with correct configurations load the default
2953                  * macvlan filter which is expected and cannot be removed.
2954                  */
2955                 i40e_update_default_filter_setting(vsi);
2956         } else if (type == I40E_VSI_SRIOV) {
2957                 memset(&ctxt, 0, sizeof(ctxt));
2958                 /**
2959                  * For other VSI, the uplink_seid equals to uplink VSI's
2960                  * uplink_seid since they share same VEB
2961                  */
2962                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2963                 ctxt.pf_num = hw->pf_id;
2964                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2965                 ctxt.uplink_seid = vsi->uplink_seid;
2966                 ctxt.connection_type = 0x1;
2967                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2968
2969                 /* Configure switch ID */
2970                 ctxt.info.valid_sections |=
2971                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2972                 ctxt.info.switch_id =
2973                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2974                 /* Configure port/vlan */
2975                 ctxt.info.valid_sections |=
2976                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2977                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2978                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2979                                                 I40E_DEFAULT_TCMAP);
2980                 if (ret != I40E_SUCCESS) {
2981                         PMD_DRV_LOG(ERR, "Failed to configure "
2982                                     "TC queue mapping");
2983                         goto fail_msix_alloc;
2984                 }
2985                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2986                 ctxt.info.valid_sections |=
2987                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2988                 /**
2989                  * Since VSI is not created yet, only configure parameter,
2990                  * will add vsi below.
2991                  */
2992         } else if (type == I40E_VSI_VMDQ2) {
2993                 memset(&ctxt, 0, sizeof(ctxt));
2994                 /*
2995                  * For other VSI, the uplink_seid equals to uplink VSI's
2996                  * uplink_seid since they share same VEB
2997                  */
2998                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2999                 ctxt.pf_num = hw->pf_id;
3000                 ctxt.vf_num = 0;
3001                 ctxt.uplink_seid = vsi->uplink_seid;
3002                 ctxt.connection_type = 0x1;
3003                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3004
3005                 ctxt.info.valid_sections |=
3006                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3007                 /* user_param carries flag to enable loop back */
3008                 if (user_param) {
3009                         ctxt.info.switch_id =
3010                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3011                         ctxt.info.switch_id |=
3012                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3013                 }
3014
3015                 /* Configure port/vlan */
3016                 ctxt.info.valid_sections |=
3017                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3018                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3019                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3020                                                 I40E_DEFAULT_TCMAP);
3021                 if (ret != I40E_SUCCESS) {
3022                         PMD_DRV_LOG(ERR, "Failed to configure "
3023                                         "TC queue mapping");
3024                         goto fail_msix_alloc;
3025                 }
3026                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3027                 ctxt.info.valid_sections |=
3028                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3029         } else if (type == I40E_VSI_FDIR) {
3030                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3031                 ctxt.pf_num = hw->pf_id;
3032                 ctxt.vf_num = 0;
3033                 ctxt.uplink_seid = vsi->uplink_seid;
3034                 ctxt.connection_type = 0x1;     /* regular data port */
3035                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3036                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3037                                                 I40E_DEFAULT_TCMAP);
3038                 if (ret != I40E_SUCCESS) {
3039                         PMD_DRV_LOG(ERR, "Failed to configure "
3040                                         "TC queue mapping.");
3041                         goto fail_msix_alloc;
3042                 }
3043                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3044                 ctxt.info.valid_sections |=
3045                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3046         } else {
3047                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3048                 goto fail_msix_alloc;
3049         }
3050
3051         if (vsi->type != I40E_VSI_MAIN) {
3052                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3053                 if (ret) {
3054                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3055                                     hw->aq.asq_last_status);
3056                         goto fail_msix_alloc;
3057                 }
3058                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3059                 vsi->info.valid_sections = 0;
3060                 vsi->seid = ctxt.seid;
3061                 vsi->vsi_id = ctxt.vsi_number;
3062                 vsi->sib_vsi_list.vsi = vsi;
3063                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3064                                 &vsi->sib_vsi_list, list);
3065         }
3066
3067         /* MAC/VLAN configuration */
3068         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3069         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3070
3071         ret = i40e_vsi_add_mac(vsi, &filter);
3072         if (ret != I40E_SUCCESS) {
3073                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3074                 goto fail_msix_alloc;
3075         }
3076
3077         /* Get VSI BW information */
3078         i40e_vsi_dump_bw_config(vsi);
3079         return vsi;
3080 fail_msix_alloc:
3081         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3082 fail_queue_alloc:
3083         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3084 fail_mem:
3085         rte_free(vsi);
3086         return NULL;
3087 }
3088
3089 /* Configure vlan stripping on or off */
3090 int
3091 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3092 {
3093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3094         struct i40e_vsi_context ctxt;
3095         uint8_t vlan_flags;
3096         int ret = I40E_SUCCESS;
3097
3098         /* Check if it has been already on or off */
3099         if (vsi->info.valid_sections &
3100                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3101                 if (on) {
3102                         if ((vsi->info.port_vlan_flags &
3103                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3104                                 return 0; /* already on */
3105                 } else {
3106                         if ((vsi->info.port_vlan_flags &
3107                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3108                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3109                                 return 0; /* already off */
3110                 }
3111         }
3112
3113         if (on)
3114                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3115         else
3116                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3117         vsi->info.valid_sections =
3118                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3119         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3120         vsi->info.port_vlan_flags |= vlan_flags;
3121         ctxt.seid = vsi->seid;
3122         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3123         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3124         if (ret)
3125                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3126                             on ? "enable" : "disable");
3127
3128         return ret;
3129 }
3130
3131 static int
3132 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3133 {
3134         struct rte_eth_dev_data *data = dev->data;
3135         int ret;
3136
3137         /* Apply vlan offload setting */
3138         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3139
3140         /* Apply double-vlan setting, not implemented yet */
3141
3142         /* Apply pvid setting */
3143         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3144                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3145         if (ret)
3146                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3147
3148         return ret;
3149 }
3150
3151 static int
3152 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3153 {
3154         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3155
3156         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3157 }
3158
3159 static int
3160 i40e_update_flow_control(struct i40e_hw *hw)
3161 {
3162 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3163         struct i40e_link_status link_status;
3164         uint32_t rxfc = 0, txfc = 0, reg;
3165         uint8_t an_info;
3166         int ret;
3167
3168         memset(&link_status, 0, sizeof(link_status));
3169         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3170         if (ret != I40E_SUCCESS) {
3171                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3172                 goto write_reg; /* Disable flow control */
3173         }
3174
3175         an_info = hw->phy.link_info.an_info;
3176         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3177                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3178                 ret = I40E_ERR_NOT_READY;
3179                 goto write_reg; /* Disable flow control */
3180         }
3181         /**
3182          * If link auto negotiation is enabled, flow control needs to
3183          * be configured according to it
3184          */
3185         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3186         case I40E_LINK_PAUSE_RXTX:
3187                 rxfc = 1;
3188                 txfc = 1;
3189                 hw->fc.current_mode = I40E_FC_FULL;
3190                 break;
3191         case I40E_AQ_LINK_PAUSE_RX:
3192                 rxfc = 1;
3193                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3194                 break;
3195         case I40E_AQ_LINK_PAUSE_TX:
3196                 txfc = 1;
3197                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3198                 break;
3199         default:
3200                 hw->fc.current_mode = I40E_FC_NONE;
3201                 break;
3202         }
3203
3204 write_reg:
3205         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3206                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3207         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3208         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3209         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3210         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3211
3212         return ret;
3213 }
3214
3215 /* PF setup */
3216 static int
3217 i40e_pf_setup(struct i40e_pf *pf)
3218 {
3219         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3220         struct i40e_filter_control_settings settings;
3221         struct i40e_vsi *vsi;
3222         int ret;
3223
3224         /* Clear all stats counters */
3225         pf->offset_loaded = FALSE;
3226         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3227         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3228
3229         ret = i40e_pf_get_switch_config(pf);
3230         if (ret != I40E_SUCCESS) {
3231                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3232                 return ret;
3233         }
3234         if (pf->flags & I40E_FLAG_FDIR) {
3235                 /* make queue allocated first, let FDIR use queue pair 0*/
3236                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3237                 if (ret != I40E_FDIR_QUEUE_ID) {
3238                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3239                                     " ret =%d", ret);
3240                         pf->flags &= ~I40E_FLAG_FDIR;
3241                 }
3242         }
3243         /*  main VSI setup */
3244         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3245         if (!vsi) {
3246                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3247                 return I40E_ERR_NOT_READY;
3248         }
3249         pf->main_vsi = vsi;
3250
3251         /* setup FDIR after main vsi created.*/
3252         if (pf->flags & I40E_FLAG_FDIR) {
3253                 ret = i40e_fdir_setup(pf);
3254                 if (ret != I40E_SUCCESS) {
3255                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
3256                         pf->flags &= ~I40E_FLAG_FDIR;
3257                 }
3258         }
3259
3260         /* Configure filter control */
3261         memset(&settings, 0, sizeof(settings));
3262         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3263                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3264         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3265                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3266         else {
3267                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3268                                                 hw->func_caps.rss_table_size);
3269                 return I40E_ERR_PARAM;
3270         }
3271         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3272                         "size: %u\n", hw->func_caps.rss_table_size);
3273         pf->hash_lut_size = hw->func_caps.rss_table_size;
3274
3275         /* Enable ethtype and macvlan filters */
3276         settings.enable_ethtype = TRUE;
3277         settings.enable_macvlan = TRUE;
3278         ret = i40e_set_filter_control(hw, &settings);
3279         if (ret)
3280                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3281                                                                 ret);
3282
3283         /* Update flow control according to the auto negotiation */
3284         i40e_update_flow_control(hw);
3285
3286         return I40E_SUCCESS;
3287 }
3288
3289 int
3290 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3291 {
3292         uint32_t reg;
3293         uint16_t j;
3294
3295         /**
3296          * Set or clear TX Queue Disable flags,
3297          * which is required by hardware.
3298          */
3299         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3300         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3301
3302         /* Wait until the request is finished */
3303         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3304                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3305                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3306                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3307                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3308                                                         & 0x1))) {
3309                         break;
3310                 }
3311         }
3312         if (on) {
3313                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3314                         return I40E_SUCCESS; /* already on, skip next steps */
3315
3316                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3317                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3318         } else {
3319                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3320                         return I40E_SUCCESS; /* already off, skip next steps */
3321                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3322         }
3323         /* Write the register */
3324         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3325         /* Check the result */
3326         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3327                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3328                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3329                 if (on) {
3330                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3331                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3332                                 break;
3333                 } else {
3334                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3335                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3336                                 break;
3337                 }
3338         }
3339         /* Check if it is timeout */
3340         if (j >= I40E_CHK_Q_ENA_COUNT) {
3341                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3342                             (on ? "enable" : "disable"), q_idx);
3343                 return I40E_ERR_TIMEOUT;
3344         }
3345
3346         return I40E_SUCCESS;
3347 }
3348
3349 /* Swith on or off the tx queues */
3350 static int
3351 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3352 {
3353         struct rte_eth_dev_data *dev_data = pf->dev_data;
3354         struct i40e_tx_queue *txq;
3355         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3356         uint16_t i;
3357         int ret;
3358
3359         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3360                 txq = dev_data->tx_queues[i];
3361                 /* Don't operate the queue if not configured or
3362                  * if starting only per queue */
3363                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3364                         continue;
3365                 if (on)
3366                         ret = i40e_dev_tx_queue_start(dev, i);
3367                 else
3368                         ret = i40e_dev_tx_queue_stop(dev, i);
3369                 if ( ret != I40E_SUCCESS)
3370                         return ret;
3371         }
3372
3373         return I40E_SUCCESS;
3374 }
3375
3376 int
3377 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3378 {
3379         uint32_t reg;
3380         uint16_t j;
3381
3382         /* Wait until the request is finished */
3383         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3384                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3385                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3386                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3387                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3388                         break;
3389         }
3390
3391         if (on) {
3392                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3393                         return I40E_SUCCESS; /* Already on, skip next steps */
3394                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3395         } else {
3396                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3397                         return I40E_SUCCESS; /* Already off, skip next steps */
3398                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3399         }
3400
3401         /* Write the register */
3402         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3403         /* Check the result */
3404         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3405                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3406                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3407                 if (on) {
3408                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3409                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3410                                 break;
3411                 } else {
3412                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3413                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3414                                 break;
3415                 }
3416         }
3417
3418         /* Check if it is timeout */
3419         if (j >= I40E_CHK_Q_ENA_COUNT) {
3420                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3421                             (on ? "enable" : "disable"), q_idx);
3422                 return I40E_ERR_TIMEOUT;
3423         }
3424
3425         return I40E_SUCCESS;
3426 }
3427 /* Switch on or off the rx queues */
3428 static int
3429 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3430 {
3431         struct rte_eth_dev_data *dev_data = pf->dev_data;
3432         struct i40e_rx_queue *rxq;
3433         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3434         uint16_t i;
3435         int ret;
3436
3437         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3438                 rxq = dev_data->rx_queues[i];
3439                 /* Don't operate the queue if not configured or
3440                  * if starting only per queue */
3441                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3442                         continue;
3443                 if (on)
3444                         ret = i40e_dev_rx_queue_start(dev, i);
3445                 else
3446                         ret = i40e_dev_rx_queue_stop(dev, i);
3447                 if (ret != I40E_SUCCESS)
3448                         return ret;
3449         }
3450
3451         return I40E_SUCCESS;
3452 }
3453
3454 /* Switch on or off all the rx/tx queues */
3455 int
3456 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3457 {
3458         int ret;
3459
3460         if (on) {
3461                 /* enable rx queues before enabling tx queues */
3462                 ret = i40e_dev_switch_rx_queues(pf, on);
3463                 if (ret) {
3464                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3465                         return ret;
3466                 }
3467                 ret = i40e_dev_switch_tx_queues(pf, on);
3468         } else {
3469                 /* Stop tx queues before stopping rx queues */
3470                 ret = i40e_dev_switch_tx_queues(pf, on);
3471                 if (ret) {
3472                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3473                         return ret;
3474                 }
3475                 ret = i40e_dev_switch_rx_queues(pf, on);
3476         }
3477
3478         return ret;
3479 }
3480
3481 /* Initialize VSI for TX */
3482 static int
3483 i40e_dev_tx_init(struct i40e_pf *pf)
3484 {
3485         struct rte_eth_dev_data *data = pf->dev_data;
3486         uint16_t i;
3487         uint32_t ret = I40E_SUCCESS;
3488         struct i40e_tx_queue *txq;
3489
3490         for (i = 0; i < data->nb_tx_queues; i++) {
3491                 txq = data->tx_queues[i];
3492                 if (!txq || !txq->q_set)
3493                         continue;
3494                 ret = i40e_tx_queue_init(txq);
3495                 if (ret != I40E_SUCCESS)
3496                         break;
3497         }
3498
3499         return ret;
3500 }
3501
3502 /* Initialize VSI for RX */
3503 static int
3504 i40e_dev_rx_init(struct i40e_pf *pf)
3505 {
3506         struct rte_eth_dev_data *data = pf->dev_data;
3507         int ret = I40E_SUCCESS;
3508         uint16_t i;
3509         struct i40e_rx_queue *rxq;
3510
3511         i40e_pf_config_mq_rx(pf);
3512         for (i = 0; i < data->nb_rx_queues; i++) {
3513                 rxq = data->rx_queues[i];
3514                 if (!rxq || !rxq->q_set)
3515                         continue;
3516
3517                 ret = i40e_rx_queue_init(rxq);
3518                 if (ret != I40E_SUCCESS) {
3519                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3520                                     "initialization");
3521                         break;
3522                 }
3523         }
3524
3525         return ret;
3526 }
3527
3528 static int
3529 i40e_dev_rxtx_init(struct i40e_pf *pf)
3530 {
3531         int err;
3532
3533         err = i40e_dev_tx_init(pf);
3534         if (err) {
3535                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3536                 return err;
3537         }
3538         err = i40e_dev_rx_init(pf);
3539         if (err) {
3540                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3541                 return err;
3542         }
3543
3544         return err;
3545 }
3546
3547 static int
3548 i40e_vmdq_setup(struct rte_eth_dev *dev)
3549 {
3550         struct rte_eth_conf *conf = &dev->data->dev_conf;
3551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3552         int i, err, conf_vsis, j, loop;
3553         struct i40e_vsi *vsi;
3554         struct i40e_vmdq_info *vmdq_info;
3555         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3556         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3557
3558         /*
3559          * Disable interrupt to avoid message from VF. Furthermore, it will
3560          * avoid race condition in VSI creation/destroy.
3561          */
3562         i40e_pf_disable_irq0(hw);
3563
3564         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3565                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3566                 return -ENOTSUP;
3567         }
3568
3569         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3570         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3571                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3572                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3573                         pf->max_nb_vmdq_vsi);
3574                 return -ENOTSUP;
3575         }
3576
3577         if (pf->vmdq != NULL) {
3578                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3579                 return 0;
3580         }
3581
3582         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3583                                 sizeof(*vmdq_info) * conf_vsis, 0);
3584
3585         if (pf->vmdq == NULL) {
3586                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3587                 return -ENOMEM;
3588         }
3589
3590         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3591
3592         /* Create VMDQ VSI */
3593         for (i = 0; i < conf_vsis; i++) {
3594                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3595                                 vmdq_conf->enable_loop_back);
3596                 if (vsi == NULL) {
3597                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3598                         err = -1;
3599                         goto err_vsi_setup;
3600                 }
3601                 vmdq_info = &pf->vmdq[i];
3602                 vmdq_info->pf = pf;
3603                 vmdq_info->vsi = vsi;
3604         }
3605         pf->nb_cfg_vmdq_vsi = conf_vsis;
3606
3607         /* Configure Vlan */
3608         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3609         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3610                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3611                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3612                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3613                                         vmdq_conf->pool_map[i].vlan_id, j);
3614
3615                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3616                                                 vmdq_conf->pool_map[i].vlan_id);
3617                                 if (err) {
3618                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3619                                         err = -1;
3620                                         goto err_vsi_setup;
3621                                 }
3622                         }
3623                 }
3624         }
3625
3626         i40e_pf_enable_irq0(hw);
3627
3628         return 0;
3629
3630 err_vsi_setup:
3631         for (i = 0; i < conf_vsis; i++)
3632                 if (pf->vmdq[i].vsi == NULL)
3633                         break;
3634                 else
3635                         i40e_vsi_release(pf->vmdq[i].vsi);
3636
3637         rte_free(pf->vmdq);
3638         pf->vmdq = NULL;
3639         i40e_pf_enable_irq0(hw);
3640         return err;
3641 }
3642
3643 static void
3644 i40e_stat_update_32(struct i40e_hw *hw,
3645                    uint32_t reg,
3646                    bool offset_loaded,
3647                    uint64_t *offset,
3648                    uint64_t *stat)
3649 {
3650         uint64_t new_data;
3651
3652         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3653         if (!offset_loaded)
3654                 *offset = new_data;
3655
3656         if (new_data >= *offset)
3657                 *stat = (uint64_t)(new_data - *offset);
3658         else
3659                 *stat = (uint64_t)((new_data +
3660                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3661 }
3662
3663 static void
3664 i40e_stat_update_48(struct i40e_hw *hw,
3665                    uint32_t hireg,
3666                    uint32_t loreg,
3667                    bool offset_loaded,
3668                    uint64_t *offset,
3669                    uint64_t *stat)
3670 {
3671         uint64_t new_data;
3672
3673         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3674         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3675                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3676
3677         if (!offset_loaded)
3678                 *offset = new_data;
3679
3680         if (new_data >= *offset)
3681                 *stat = new_data - *offset;
3682         else
3683                 *stat = (uint64_t)((new_data +
3684                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3685
3686         *stat &= I40E_48_BIT_MASK;
3687 }
3688
3689 /* Disable IRQ0 */
3690 void
3691 i40e_pf_disable_irq0(struct i40e_hw *hw)
3692 {
3693         /* Disable all interrupt types */
3694         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3695         I40E_WRITE_FLUSH(hw);
3696 }
3697
3698 /* Enable IRQ0 */
3699 void
3700 i40e_pf_enable_irq0(struct i40e_hw *hw)
3701 {
3702         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3703                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3704                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3705                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3706         I40E_WRITE_FLUSH(hw);
3707 }
3708
3709 static void
3710 i40e_pf_config_irq0(struct i40e_hw *hw)
3711 {
3712         /* read pending request and disable first */
3713         i40e_pf_disable_irq0(hw);
3714         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3715         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3716                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3717
3718         /* Link no queues with irq0 */
3719         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3720                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3721 }
3722
3723 static void
3724 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3725 {
3726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3728         int i;
3729         uint16_t abs_vf_id;
3730         uint32_t index, offset, val;
3731
3732         if (!pf->vfs)
3733                 return;
3734         /**
3735          * Try to find which VF trigger a reset, use absolute VF id to access
3736          * since the reg is global register.
3737          */
3738         for (i = 0; i < pf->vf_num; i++) {
3739                 abs_vf_id = hw->func_caps.vf_base_id + i;
3740                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3741                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3742                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3743                 /* VFR event occured */
3744                 if (val & (0x1 << offset)) {
3745                         int ret;
3746
3747                         /* Clear the event first */
3748                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3749                                                         (0x1 << offset));
3750                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3751                         /**
3752                          * Only notify a VF reset event occured,
3753                          * don't trigger another SW reset
3754                          */
3755                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3756                         if (ret != I40E_SUCCESS)
3757                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3758                 }
3759         }
3760 }
3761
3762 static void
3763 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3764 {
3765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766         struct i40e_arq_event_info info;
3767         uint16_t pending, opcode;
3768         int ret;
3769
3770         info.buf_len = I40E_AQ_BUF_SZ;
3771         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3772         if (!info.msg_buf) {
3773                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3774                 return;
3775         }
3776
3777         pending = 1;
3778         while (pending) {
3779                 ret = i40e_clean_arq_element(hw, &info, &pending);
3780
3781                 if (ret != I40E_SUCCESS) {
3782                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3783                                     "aq_err: %u", hw->aq.asq_last_status);
3784                         break;
3785                 }
3786                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3787
3788                 switch (opcode) {
3789                 case i40e_aqc_opc_send_msg_to_pf:
3790                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3791                         i40e_pf_host_handle_vf_msg(dev,
3792                                         rte_le_to_cpu_16(info.desc.retval),
3793                                         rte_le_to_cpu_32(info.desc.cookie_high),
3794                                         rte_le_to_cpu_32(info.desc.cookie_low),
3795                                         info.msg_buf,
3796                                         info.msg_len);
3797                         break;
3798                 default:
3799                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3800                                     opcode);
3801                         break;
3802                 }
3803         }
3804         rte_free(info.msg_buf);
3805 }
3806
3807 /*
3808  * Interrupt handler is registered as the alarm callback for handling LSC
3809  * interrupt in a definite of time, in order to wait the NIC into a stable
3810  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3811  * no need for link down interrupt.
3812  */
3813 static void
3814 i40e_dev_interrupt_delayed_handler(void *param)
3815 {
3816         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818         uint32_t icr0;
3819
3820         /* read interrupt causes again */
3821         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3822
3823 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3824         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3825                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3826         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3827                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3828         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3829                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3830         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3831                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3832         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3833                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3834                                                                 "state\n");
3835         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3836                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3837         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3838                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3839 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3840
3841         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3842                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3843                 i40e_dev_handle_vfr_event(dev);
3844         }
3845         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3846                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3847                 i40e_dev_handle_aq_msg(dev);
3848         }
3849
3850         /* handle the link up interrupt in an alarm callback */
3851         i40e_dev_link_update(dev, 0);
3852         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3853
3854         i40e_pf_enable_irq0(hw);
3855         rte_intr_enable(&(dev->pci_dev->intr_handle));
3856 }
3857
3858 /**
3859  * Interrupt handler triggered by NIC  for handling
3860  * specific interrupt.
3861  *
3862  * @param handle
3863  *  Pointer to interrupt handle.
3864  * @param param
3865  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3866  *
3867  * @return
3868  *  void
3869  */
3870 static void
3871 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3872                            void *param)
3873 {
3874         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3875         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876         uint32_t icr0;
3877
3878         /* Disable interrupt */
3879         i40e_pf_disable_irq0(hw);
3880
3881         /* read out interrupt causes */
3882         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3883
3884         /* No interrupt event indicated */
3885         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3886                 PMD_DRV_LOG(INFO, "No interrupt event");
3887                 goto done;
3888         }
3889 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3890         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3891                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3892         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3893                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3894         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3895                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3896         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3897                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3898         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3899                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3900         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3901                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3902         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3903                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3904 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3905
3906         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3907                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3908                 i40e_dev_handle_vfr_event(dev);
3909         }
3910         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3911                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3912                 i40e_dev_handle_aq_msg(dev);
3913         }
3914
3915         /* Link Status Change interrupt */
3916         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3917 #define I40E_US_PER_SECOND 1000000
3918                 struct rte_eth_link link;
3919
3920                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3921                 memset(&link, 0, sizeof(link));
3922                 rte_i40e_dev_atomic_read_link_status(dev, &link);
3923                 i40e_dev_link_update(dev, 0);
3924
3925                 /*
3926                  * For link up interrupt, it needs to wait 1 second to let the
3927                  * hardware be a stable state. Otherwise several consecutive
3928                  * interrupts can be observed.
3929                  * For link down interrupt, no need to wait.
3930                  */
3931                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3932                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3933                         return;
3934                 else
3935                         _rte_eth_dev_callback_process(dev,
3936                                 RTE_ETH_EVENT_INTR_LSC);
3937         }
3938
3939 done:
3940         /* Enable interrupt */
3941         i40e_pf_enable_irq0(hw);
3942         rte_intr_enable(&(dev->pci_dev->intr_handle));
3943 }
3944
3945 static int
3946 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3947                          struct i40e_macvlan_filter *filter,
3948                          int total)
3949 {
3950         int ele_num, ele_buff_size;
3951         int num, actual_num, i;
3952         uint16_t flags;
3953         int ret = I40E_SUCCESS;
3954         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3955         struct i40e_aqc_add_macvlan_element_data *req_list;
3956
3957         if (filter == NULL  || total == 0)
3958                 return I40E_ERR_PARAM;
3959         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3960         ele_buff_size = hw->aq.asq_buf_size;
3961
3962         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3963         if (req_list == NULL) {
3964                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3965                 return I40E_ERR_NO_MEMORY;
3966         }
3967
3968         num = 0;
3969         do {
3970                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3971                 memset(req_list, 0, ele_buff_size);
3972
3973                 for (i = 0; i < actual_num; i++) {
3974                         (void)rte_memcpy(req_list[i].mac_addr,
3975                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3976                         req_list[i].vlan_tag =
3977                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3978
3979                         switch (filter[num + i].filter_type) {
3980                         case RTE_MAC_PERFECT_MATCH:
3981                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3982                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3983                                 break;
3984                         case RTE_MACVLAN_PERFECT_MATCH:
3985                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3986                                 break;
3987                         case RTE_MAC_HASH_MATCH:
3988                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3989                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3990                                 break;
3991                         case RTE_MACVLAN_HASH_MATCH:
3992                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
3993                                 break;
3994                         default:
3995                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
3996                                 ret = I40E_ERR_PARAM;
3997                                 goto DONE;
3998                         }
3999
4000                         req_list[i].queue_number = 0;
4001
4002                         req_list[i].flags = rte_cpu_to_le_16(flags);
4003                 }
4004
4005                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4006                                                 actual_num, NULL);
4007                 if (ret != I40E_SUCCESS) {
4008                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4009                         goto DONE;
4010                 }
4011                 num += actual_num;
4012         } while (num < total);
4013
4014 DONE:
4015         rte_free(req_list);
4016         return ret;
4017 }
4018
4019 static int
4020 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4021                             struct i40e_macvlan_filter *filter,
4022                             int total)
4023 {
4024         int ele_num, ele_buff_size;
4025         int num, actual_num, i;
4026         uint16_t flags;
4027         int ret = I40E_SUCCESS;
4028         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4029         struct i40e_aqc_remove_macvlan_element_data *req_list;
4030
4031         if (filter == NULL  || total == 0)
4032                 return I40E_ERR_PARAM;
4033
4034         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4035         ele_buff_size = hw->aq.asq_buf_size;
4036
4037         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4038         if (req_list == NULL) {
4039                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4040                 return I40E_ERR_NO_MEMORY;
4041         }
4042
4043         num = 0;
4044         do {
4045                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4046                 memset(req_list, 0, ele_buff_size);
4047
4048                 for (i = 0; i < actual_num; i++) {
4049                         (void)rte_memcpy(req_list[i].mac_addr,
4050                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4051                         req_list[i].vlan_tag =
4052                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4053
4054                         switch (filter[num + i].filter_type) {
4055                         case RTE_MAC_PERFECT_MATCH:
4056                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4057                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4058                                 break;
4059                         case RTE_MACVLAN_PERFECT_MATCH:
4060                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4061                                 break;
4062                         case RTE_MAC_HASH_MATCH:
4063                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4064                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4065                                 break;
4066                         case RTE_MACVLAN_HASH_MATCH:
4067                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4068                                 break;
4069                         default:
4070                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4071                                 ret = I40E_ERR_PARAM;
4072                                 goto DONE;
4073                         }
4074                         req_list[i].flags = rte_cpu_to_le_16(flags);
4075                 }
4076
4077                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4078                                                 actual_num, NULL);
4079                 if (ret != I40E_SUCCESS) {
4080                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4081                         goto DONE;
4082                 }
4083                 num += actual_num;
4084         } while (num < total);
4085
4086 DONE:
4087         rte_free(req_list);
4088         return ret;
4089 }
4090
4091 /* Find out specific MAC filter */
4092 static struct i40e_mac_filter *
4093 i40e_find_mac_filter(struct i40e_vsi *vsi,
4094                          struct ether_addr *macaddr)
4095 {
4096         struct i40e_mac_filter *f;
4097
4098         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4099                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4100                         return f;
4101         }
4102
4103         return NULL;
4104 }
4105
4106 static bool
4107 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4108                          uint16_t vlan_id)
4109 {
4110         uint32_t vid_idx, vid_bit;
4111
4112         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4113         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4114
4115         if (vsi->vfta[vid_idx] & vid_bit)
4116                 return 1;
4117         else
4118                 return 0;
4119 }
4120
4121 static void
4122 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4123                          uint16_t vlan_id, bool on)
4124 {
4125         uint32_t vid_idx, vid_bit;
4126
4127 #define UINT32_BIT_MASK      0x1F
4128 #define VALID_VLAN_BIT_MASK  0xFFF
4129         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4130          *  element first, then find the bits it belongs to
4131          */
4132         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4133                   sizeof(uint32_t));
4134         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4135
4136         if (on)
4137                 vsi->vfta[vid_idx] |= vid_bit;
4138         else
4139                 vsi->vfta[vid_idx] &= ~vid_bit;
4140 }
4141
4142 /**
4143  * Find all vlan options for specific mac addr,
4144  * return with actual vlan found.
4145  */
4146 static inline int
4147 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4148                            struct i40e_macvlan_filter *mv_f,
4149                            int num, struct ether_addr *addr)
4150 {
4151         int i;
4152         uint32_t j, k;
4153
4154         /**
4155          * Not to use i40e_find_vlan_filter to decrease the loop time,
4156          * although the code looks complex.
4157           */
4158         if (num < vsi->vlan_num)
4159                 return I40E_ERR_PARAM;
4160
4161         i = 0;
4162         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4163                 if (vsi->vfta[j]) {
4164                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4165                                 if (vsi->vfta[j] & (1 << k)) {
4166                                         if (i > num - 1) {
4167                                                 PMD_DRV_LOG(ERR, "vlan number "
4168                                                             "not match");
4169                                                 return I40E_ERR_PARAM;
4170                                         }
4171                                         (void)rte_memcpy(&mv_f[i].macaddr,
4172                                                         addr, ETH_ADDR_LEN);
4173                                         mv_f[i].vlan_id =
4174                                                 j * I40E_UINT32_BIT_SIZE + k;
4175                                         i++;
4176                                 }
4177                         }
4178                 }
4179         }
4180         return I40E_SUCCESS;
4181 }
4182
4183 static inline int
4184 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4185                            struct i40e_macvlan_filter *mv_f,
4186                            int num,
4187                            uint16_t vlan)
4188 {
4189         int i = 0;
4190         struct i40e_mac_filter *f;
4191
4192         if (num < vsi->mac_num)
4193                 return I40E_ERR_PARAM;
4194
4195         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4196                 if (i > num - 1) {
4197                         PMD_DRV_LOG(ERR, "buffer number not match");
4198                         return I40E_ERR_PARAM;
4199                 }
4200                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4201                                 ETH_ADDR_LEN);
4202                 mv_f[i].vlan_id = vlan;
4203                 mv_f[i].filter_type = f->mac_info.filter_type;
4204                 i++;
4205         }
4206
4207         return I40E_SUCCESS;
4208 }
4209
4210 static int
4211 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4212 {
4213         int i, num;
4214         struct i40e_mac_filter *f;
4215         struct i40e_macvlan_filter *mv_f;
4216         int ret = I40E_SUCCESS;
4217
4218         if (vsi == NULL || vsi->mac_num == 0)
4219                 return I40E_ERR_PARAM;
4220
4221         /* Case that no vlan is set */
4222         if (vsi->vlan_num == 0)
4223                 num = vsi->mac_num;
4224         else
4225                 num = vsi->mac_num * vsi->vlan_num;
4226
4227         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4228         if (mv_f == NULL) {
4229                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4230                 return I40E_ERR_NO_MEMORY;
4231         }
4232
4233         i = 0;
4234         if (vsi->vlan_num == 0) {
4235                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4236                         (void)rte_memcpy(&mv_f[i].macaddr,
4237                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4238                         mv_f[i].vlan_id = 0;
4239                         i++;
4240                 }
4241         } else {
4242                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4243                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4244                                         vsi->vlan_num, &f->mac_info.mac_addr);
4245                         if (ret != I40E_SUCCESS)
4246                                 goto DONE;
4247                         i += vsi->vlan_num;
4248                 }
4249         }
4250
4251         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4252 DONE:
4253         rte_free(mv_f);
4254
4255         return ret;
4256 }
4257
4258 int
4259 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4260 {
4261         struct i40e_macvlan_filter *mv_f;
4262         int mac_num;
4263         int ret = I40E_SUCCESS;
4264
4265         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4266                 return I40E_ERR_PARAM;
4267
4268         /* If it's already set, just return */
4269         if (i40e_find_vlan_filter(vsi,vlan))
4270                 return I40E_SUCCESS;
4271
4272         mac_num = vsi->mac_num;
4273
4274         if (mac_num == 0) {
4275                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4276                 return I40E_ERR_PARAM;
4277         }
4278
4279         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4280
4281         if (mv_f == NULL) {
4282                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4283                 return I40E_ERR_NO_MEMORY;
4284         }
4285
4286         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4287
4288         if (ret != I40E_SUCCESS)
4289                 goto DONE;
4290
4291         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4292
4293         if (ret != I40E_SUCCESS)
4294                 goto DONE;
4295
4296         i40e_set_vlan_filter(vsi, vlan, 1);
4297
4298         vsi->vlan_num++;
4299         ret = I40E_SUCCESS;
4300 DONE:
4301         rte_free(mv_f);
4302         return ret;
4303 }
4304
4305 int
4306 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4307 {
4308         struct i40e_macvlan_filter *mv_f;
4309         int mac_num;
4310         int ret = I40E_SUCCESS;
4311
4312         /**
4313          * Vlan 0 is the generic filter for untagged packets
4314          * and can't be removed.
4315          */
4316         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4317                 return I40E_ERR_PARAM;
4318
4319         /* If can't find it, just return */
4320         if (!i40e_find_vlan_filter(vsi, vlan))
4321                 return I40E_ERR_PARAM;
4322
4323         mac_num = vsi->mac_num;
4324
4325         if (mac_num == 0) {
4326                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4327                 return I40E_ERR_PARAM;
4328         }
4329
4330         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4331
4332         if (mv_f == NULL) {
4333                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4334                 return I40E_ERR_NO_MEMORY;
4335         }
4336
4337         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4338
4339         if (ret != I40E_SUCCESS)
4340                 goto DONE;
4341
4342         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4343
4344         if (ret != I40E_SUCCESS)
4345                 goto DONE;
4346
4347         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4348         if (vsi->vlan_num == 1) {
4349                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4350                 if (ret != I40E_SUCCESS)
4351                         goto DONE;
4352
4353                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4354                 if (ret != I40E_SUCCESS)
4355                         goto DONE;
4356         }
4357
4358         i40e_set_vlan_filter(vsi, vlan, 0);
4359
4360         vsi->vlan_num--;
4361         ret = I40E_SUCCESS;
4362 DONE:
4363         rte_free(mv_f);
4364         return ret;
4365 }
4366
4367 int
4368 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4369 {
4370         struct i40e_mac_filter *f;
4371         struct i40e_macvlan_filter *mv_f;
4372         int i, vlan_num = 0;
4373         int ret = I40E_SUCCESS;
4374
4375         /* If it's add and we've config it, return */
4376         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4377         if (f != NULL)
4378                 return I40E_SUCCESS;
4379         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4380                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4381
4382                 /**
4383                  * If vlan_num is 0, that's the first time to add mac,
4384                  * set mask for vlan_id 0.
4385                  */
4386                 if (vsi->vlan_num == 0) {
4387                         i40e_set_vlan_filter(vsi, 0, 1);
4388                         vsi->vlan_num = 1;
4389                 }
4390                 vlan_num = vsi->vlan_num;
4391         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4392                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4393                 vlan_num = 1;
4394
4395         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4396         if (mv_f == NULL) {
4397                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4398                 return I40E_ERR_NO_MEMORY;
4399         }
4400
4401         for (i = 0; i < vlan_num; i++) {
4402                 mv_f[i].filter_type = mac_filter->filter_type;
4403                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4404                                 ETH_ADDR_LEN);
4405         }
4406
4407         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4408                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4409                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4410                                         &mac_filter->mac_addr);
4411                 if (ret != I40E_SUCCESS)
4412                         goto DONE;
4413         }
4414
4415         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4416         if (ret != I40E_SUCCESS)
4417                 goto DONE;
4418
4419         /* Add the mac addr into mac list */
4420         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4421         if (f == NULL) {
4422                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4423                 ret = I40E_ERR_NO_MEMORY;
4424                 goto DONE;
4425         }
4426         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4427                         ETH_ADDR_LEN);
4428         f->mac_info.filter_type = mac_filter->filter_type;
4429         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4430         vsi->mac_num++;
4431
4432         ret = I40E_SUCCESS;
4433 DONE:
4434         rte_free(mv_f);
4435
4436         return ret;
4437 }
4438
4439 int
4440 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4441 {
4442         struct i40e_mac_filter *f;
4443         struct i40e_macvlan_filter *mv_f;
4444         int i, vlan_num;
4445         enum rte_mac_filter_type filter_type;
4446         int ret = I40E_SUCCESS;
4447
4448         /* Can't find it, return an error */
4449         f = i40e_find_mac_filter(vsi, addr);
4450         if (f == NULL)
4451                 return I40E_ERR_PARAM;
4452
4453         vlan_num = vsi->vlan_num;
4454         filter_type = f->mac_info.filter_type;
4455         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4456                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4457                 if (vlan_num == 0) {
4458                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4459                         return I40E_ERR_PARAM;
4460                 }
4461         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4462                         filter_type == RTE_MAC_HASH_MATCH)
4463                 vlan_num = 1;
4464
4465         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4466         if (mv_f == NULL) {
4467                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4468                 return I40E_ERR_NO_MEMORY;
4469         }
4470
4471         for (i = 0; i < vlan_num; i++) {
4472                 mv_f[i].filter_type = filter_type;
4473                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4474                                 ETH_ADDR_LEN);
4475         }
4476         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4477                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4478                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4479                 if (ret != I40E_SUCCESS)
4480                         goto DONE;
4481         }
4482
4483         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4484         if (ret != I40E_SUCCESS)
4485                 goto DONE;
4486
4487         /* Remove the mac addr into mac list */
4488         TAILQ_REMOVE(&vsi->mac_list, f, next);
4489         rte_free(f);
4490         vsi->mac_num--;
4491
4492         ret = I40E_SUCCESS;
4493 DONE:
4494         rte_free(mv_f);
4495         return ret;
4496 }
4497
4498 /* Configure hash enable flags for RSS */
4499 uint64_t
4500 i40e_config_hena(uint64_t flags)
4501 {
4502         uint64_t hena = 0;
4503
4504         if (!flags)
4505                 return hena;
4506
4507         if (flags & ETH_RSS_NONF_IPV4_UDP)
4508                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4509         if (flags & ETH_RSS_NONF_IPV4_TCP)
4510                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4511         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4512                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4513         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4514                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4515         if (flags & ETH_RSS_FRAG_IPV4)
4516                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4517         if (flags & ETH_RSS_NONF_IPV6_UDP)
4518                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4519         if (flags & ETH_RSS_NONF_IPV6_TCP)
4520                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4521         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4522                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4523         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4524                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4525         if (flags & ETH_RSS_FRAG_IPV6)
4526                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4527         if (flags & ETH_RSS_L2_PAYLOAD)
4528                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4529
4530         return hena;
4531 }
4532
4533 /* Parse the hash enable flags */
4534 uint64_t
4535 i40e_parse_hena(uint64_t flags)
4536 {
4537         uint64_t rss_hf = 0;
4538
4539         if (!flags)
4540                 return rss_hf;
4541
4542         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4543                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4544         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4545                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4546         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4547                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4548         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4549                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4550         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4551                 rss_hf |= ETH_RSS_FRAG_IPV4;
4552         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4553                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4554         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4555                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4556         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4557                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4558         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4559                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4560         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4561                 rss_hf |= ETH_RSS_FRAG_IPV6;
4562         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4563                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4564
4565         return rss_hf;
4566 }
4567
4568 /* Disable RSS */
4569 static void
4570 i40e_pf_disable_rss(struct i40e_pf *pf)
4571 {
4572         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4573         uint64_t hena;
4574
4575         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4576         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4577         hena &= ~I40E_RSS_HENA_ALL;
4578         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4579         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4580         I40E_WRITE_FLUSH(hw);
4581 }
4582
4583 static int
4584 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4585 {
4586         uint32_t *hash_key;
4587         uint8_t hash_key_len;
4588         uint64_t rss_hf;
4589         uint16_t i;
4590         uint64_t hena;
4591
4592         hash_key = (uint32_t *)(rss_conf->rss_key);
4593         hash_key_len = rss_conf->rss_key_len;
4594         if (hash_key != NULL && hash_key_len >=
4595                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4596                 /* Fill in RSS hash key */
4597                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4598                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4599         }
4600
4601         rss_hf = rss_conf->rss_hf;
4602         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4603         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4604         hena &= ~I40E_RSS_HENA_ALL;
4605         hena |= i40e_config_hena(rss_hf);
4606         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4607         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4608         I40E_WRITE_FLUSH(hw);
4609
4610         return 0;
4611 }
4612
4613 static int
4614 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4615                          struct rte_eth_rss_conf *rss_conf)
4616 {
4617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4619         uint64_t hena;
4620
4621         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4622         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4623         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4624                 if (rss_hf != 0) /* Enable RSS */
4625                         return -EINVAL;
4626                 return 0; /* Nothing to do */
4627         }
4628         /* RSS enabled */
4629         if (rss_hf == 0) /* Disable RSS */
4630                 return -EINVAL;
4631
4632         return i40e_hw_rss_hash_set(hw, rss_conf);
4633 }
4634
4635 static int
4636 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4637                            struct rte_eth_rss_conf *rss_conf)
4638 {
4639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4640         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4641         uint64_t hena;
4642         uint16_t i;
4643
4644         if (hash_key != NULL) {
4645                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4646                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4647                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4648         }
4649         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4650         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4651         rss_conf->rss_hf = i40e_parse_hena(hena);
4652
4653         return 0;
4654 }
4655
4656 static int
4657 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4658 {
4659         switch (filter_type) {
4660         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4661                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4662                 break;
4663         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4664                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4665                 break;
4666         case RTE_TUNNEL_FILTER_IMAC_TENID:
4667                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4668                 break;
4669         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4670                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4671                 break;
4672         case ETH_TUNNEL_FILTER_IMAC:
4673                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4674                 break;
4675         default:
4676                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4677                 return -EINVAL;
4678         }
4679
4680         return 0;
4681 }
4682
4683 static int
4684 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4685                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4686                         uint8_t add)
4687 {
4688         uint16_t ip_type;
4689         uint8_t tun_type = 0;
4690         int val, ret = 0;
4691         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4692         struct i40e_vsi *vsi = pf->main_vsi;
4693         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4694         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4695
4696         cld_filter = rte_zmalloc("tunnel_filter",
4697                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4698                 0);
4699
4700         if (NULL == cld_filter) {
4701                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4702                 return -EINVAL;
4703         }
4704         pfilter = cld_filter;
4705
4706         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4707                         sizeof(struct ether_addr));
4708         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4709                         sizeof(struct ether_addr));
4710
4711         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4712         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4713                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4714                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4715                                 &tunnel_filter->ip_addr,
4716                                 sizeof(pfilter->ipaddr.v4.data));
4717         } else {
4718                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4719                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4720                                 &tunnel_filter->ip_addr,
4721                                 sizeof(pfilter->ipaddr.v6.data));
4722         }
4723
4724         /* check tunneled type */
4725         switch (tunnel_filter->tunnel_type) {
4726         case RTE_TUNNEL_TYPE_VXLAN:
4727                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4728                 break;
4729         default:
4730                 /* Other tunnel types is not supported. */
4731                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4732                 rte_free(cld_filter);
4733                 return -EINVAL;
4734         }
4735
4736         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4737                                                 &pfilter->flags);
4738         if (val < 0) {
4739                 rte_free(cld_filter);
4740                 return -EINVAL;
4741         }
4742
4743         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4744                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4745         pfilter->tenant_id = tunnel_filter->tenant_id;
4746         pfilter->queue_number = tunnel_filter->queue_id;
4747
4748         if (add)
4749                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4750         else
4751                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4752                                                 cld_filter, 1);
4753
4754         rte_free(cld_filter);
4755         return ret;
4756 }
4757
4758 static int
4759 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4760 {
4761         uint8_t i;
4762
4763         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4764                 if (pf->vxlan_ports[i] == port)
4765                         return i;
4766         }
4767
4768         return -1;
4769 }
4770
4771 static int
4772 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4773 {
4774         int  idx, ret;
4775         uint8_t filter_idx;
4776         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4777
4778         idx = i40e_get_vxlan_port_idx(pf, port);
4779
4780         /* Check if port already exists */
4781         if (idx >= 0) {
4782                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4783                 return -EINVAL;
4784         }
4785
4786         /* Now check if there is space to add the new port */
4787         idx = i40e_get_vxlan_port_idx(pf, 0);
4788         if (idx < 0) {
4789                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4790                         "not adding port %d", port);
4791                 return -ENOSPC;
4792         }
4793
4794         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4795                                         &filter_idx, NULL);
4796         if (ret < 0) {
4797                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4798                 return -1;
4799         }
4800
4801         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4802                          port,  filter_idx);
4803
4804         /* New port: add it and mark its index in the bitmap */
4805         pf->vxlan_ports[idx] = port;
4806         pf->vxlan_bitmap |= (1 << idx);
4807
4808         if (!(pf->flags & I40E_FLAG_VXLAN))
4809                 pf->flags |= I40E_FLAG_VXLAN;
4810
4811         return 0;
4812 }
4813
4814 static int
4815 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4816 {
4817         int idx;
4818         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4819
4820         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4821                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4822                 return -EINVAL;
4823         }
4824
4825         idx = i40e_get_vxlan_port_idx(pf, port);
4826
4827         if (idx < 0) {
4828                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4829                 return -EINVAL;
4830         }
4831
4832         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4833                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4834                 return -1;
4835         }
4836
4837         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4838                         port, idx);
4839
4840         pf->vxlan_ports[idx] = 0;
4841         pf->vxlan_bitmap &= ~(1 << idx);
4842
4843         if (!pf->vxlan_bitmap)
4844                 pf->flags &= ~I40E_FLAG_VXLAN;
4845
4846         return 0;
4847 }
4848
4849 /* Add UDP tunneling port */
4850 static int
4851 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4852                         struct rte_eth_udp_tunnel *udp_tunnel)
4853 {
4854         int ret = 0;
4855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4856
4857         if (udp_tunnel == NULL)
4858                 return -EINVAL;
4859
4860         switch (udp_tunnel->prot_type) {
4861         case RTE_TUNNEL_TYPE_VXLAN:
4862                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4863                 break;
4864
4865         case RTE_TUNNEL_TYPE_GENEVE:
4866         case RTE_TUNNEL_TYPE_TEREDO:
4867                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4868                 ret = -1;
4869                 break;
4870
4871         default:
4872                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4873                 ret = -1;
4874                 break;
4875         }
4876
4877         return ret;
4878 }
4879
4880 /* Remove UDP tunneling port */
4881 static int
4882 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4883                         struct rte_eth_udp_tunnel *udp_tunnel)
4884 {
4885         int ret = 0;
4886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4887
4888         if (udp_tunnel == NULL)
4889                 return -EINVAL;
4890
4891         switch (udp_tunnel->prot_type) {
4892         case RTE_TUNNEL_TYPE_VXLAN:
4893                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4894                 break;
4895         case RTE_TUNNEL_TYPE_GENEVE:
4896         case RTE_TUNNEL_TYPE_TEREDO:
4897                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4898                 ret = -1;
4899                 break;
4900         default:
4901                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4902                 ret = -1;
4903                 break;
4904         }
4905
4906         return ret;
4907 }
4908
4909 /* Calculate the maximum number of contiguous PF queues that are configured */
4910 static int
4911 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4912 {
4913         struct rte_eth_dev_data *data = pf->dev_data;
4914         int i, num;
4915         struct i40e_rx_queue *rxq;
4916
4917         num = 0;
4918         for (i = 0; i < pf->lan_nb_qps; i++) {
4919                 rxq = data->rx_queues[i];
4920                 if (rxq && rxq->q_set)
4921                         num++;
4922                 else
4923                         break;
4924         }
4925
4926         return num;
4927 }
4928
4929 /* Configure RSS */
4930 static int
4931 i40e_pf_config_rss(struct i40e_pf *pf)
4932 {
4933         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4934         struct rte_eth_rss_conf rss_conf;
4935         uint32_t i, lut = 0;
4936         uint16_t j, num;
4937
4938         /*
4939          * If both VMDQ and RSS enabled, not all of PF queues are configured.
4940          * It's necessary to calulate the actual PF queues that are configured.
4941          */
4942         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4943                 num = i40e_pf_calc_configured_queues_num(pf);
4944                 num = i40e_align_floor(num);
4945         } else
4946                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4947
4948         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
4949                         num);
4950
4951         if (num == 0) {
4952                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
4953                 return -ENOTSUP;
4954         }
4955
4956         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4957                 if (j == num)
4958                         j = 0;
4959                 lut = (lut << 8) | (j & ((0x1 <<
4960                         hw->func_caps.rss_table_entry_width) - 1));
4961                 if ((i & 3) == 3)
4962                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4963         }
4964
4965         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4966         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4967                 i40e_pf_disable_rss(pf);
4968                 return 0;
4969         }
4970         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4971                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4972                 /* Calculate the default hash key */
4973                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4974                         rss_key_default[i] = (uint32_t)rte_rand();
4975                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4976                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4977                                                         sizeof(uint32_t);
4978         }
4979
4980         return i40e_hw_rss_hash_set(hw, &rss_conf);
4981 }
4982
4983 static int
4984 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4985                         struct rte_eth_tunnel_filter_conf *filter)
4986 {
4987         if (pf == NULL || filter == NULL) {
4988                 PMD_DRV_LOG(ERR, "Invalid parameter");
4989                 return -EINVAL;
4990         }
4991
4992         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4993                 PMD_DRV_LOG(ERR, "Invalid queue ID");
4994                 return -EINVAL;
4995         }
4996
4997         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4998                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4999                 return -EINVAL;
5000         }
5001
5002         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5003                 (is_zero_ether_addr(filter->outer_mac))) {
5004                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5005                 return -EINVAL;
5006         }
5007
5008         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5009                 (is_zero_ether_addr(filter->inner_mac))) {
5010                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5011                 return -EINVAL;
5012         }
5013
5014         return 0;
5015 }
5016
5017 static int
5018 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5019                         void *arg)
5020 {
5021         struct rte_eth_tunnel_filter_conf *filter;
5022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5023         int ret = I40E_SUCCESS;
5024
5025         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5026
5027         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5028                 return I40E_ERR_PARAM;
5029
5030         switch (filter_op) {
5031         case RTE_ETH_FILTER_NOP:
5032                 if (!(pf->flags & I40E_FLAG_VXLAN))
5033                         ret = I40E_NOT_SUPPORTED;
5034         case RTE_ETH_FILTER_ADD:
5035                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5036                 break;
5037         case RTE_ETH_FILTER_DELETE:
5038                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5039                 break;
5040         default:
5041                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5042                 ret = I40E_ERR_PARAM;
5043                 break;
5044         }
5045
5046         return ret;
5047 }
5048
5049 static int
5050 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5051 {
5052         int ret = 0;
5053         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5054
5055         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5056                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5057                 return -ENOTSUP;
5058         }
5059
5060         /* RSS setup */
5061         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5062                 ret = i40e_pf_config_rss(pf);
5063         else
5064                 i40e_pf_disable_rss(pf);
5065
5066         return ret;
5067 }
5068
5069 static int
5070 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5071                      enum rte_filter_type filter_type,
5072                      enum rte_filter_op filter_op,
5073                      void *arg)
5074 {
5075         int ret = 0;
5076
5077         if (dev == NULL)
5078                 return -EINVAL;
5079
5080         switch (filter_type) {
5081         case RTE_ETH_FILTER_MACVLAN:
5082                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5083                 break;
5084         case RTE_ETH_FILTER_TUNNEL:
5085                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5086                 break;
5087         default:
5088                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5089                                                         filter_type);
5090                 ret = -EINVAL;
5091                 break;
5092         }
5093
5094         return ret;
5095 }