4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds */
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
110 static int i40e_dev_configure(struct rte_eth_dev *dev);
111 static int i40e_dev_start(struct rte_eth_dev *dev);
112 static void i40e_dev_stop(struct rte_eth_dev *dev);
113 static void i40e_dev_close(struct rte_eth_dev *dev);
114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
121 struct rte_eth_stats *stats);
122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
128 struct rte_eth_dev_info *dev_info);
129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
141 struct rte_eth_fc_conf *fc_conf);
142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
143 struct rte_eth_pfc_conf *pfc_conf);
144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
145 struct ether_addr *mac_addr,
148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_reta_entry64 *reta_conf,
152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
153 struct rte_eth_rss_reta_entry64 *reta_conf,
156 static int i40e_get_cap(struct i40e_hw *hw);
157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
158 static int i40e_pf_setup(struct i40e_pf *pf);
159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
162 bool offset_loaded, uint64_t *offset, uint64_t *stat);
163 static void i40e_stat_update_48(struct i40e_hw *hw,
169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
170 static void i40e_dev_interrupt_handler(
171 __rte_unused struct rte_intr_handle *handle, void *param);
172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
173 uint32_t base, uint32_t num);
174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
180 static int i40e_veb_release(struct i40e_veb *veb);
181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
182 struct i40e_vsi *vsi);
183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
186 struct i40e_macvlan_filter *mv_f,
188 struct ether_addr *addr);
189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
190 struct i40e_macvlan_filter *mv_f,
193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
195 struct rte_eth_rss_conf *rss_conf);
196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
197 struct rte_eth_rss_conf *rss_conf);
198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
199 struct rte_eth_udp_tunnel *udp_tunnel);
200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
201 struct rte_eth_udp_tunnel *udp_tunnel);
202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
203 struct rte_eth_ethertype_filter *filter,
205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
206 enum rte_filter_op filter_op,
208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
209 enum rte_filter_type filter_type,
210 enum rte_filter_op filter_op,
212 static void i40e_configure_registers(struct i40e_hw *hw);
213 static void i40e_hw_init(struct i40e_hw *hw);
215 static const struct rte_pci_id pci_id_i40e_map[] = {
216 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
217 #include "rte_pci_dev_ids.h"
218 { .vendor_id = 0, /* sentinel */ },
221 static const struct eth_dev_ops i40e_eth_dev_ops = {
222 .dev_configure = i40e_dev_configure,
223 .dev_start = i40e_dev_start,
224 .dev_stop = i40e_dev_stop,
225 .dev_close = i40e_dev_close,
226 .promiscuous_enable = i40e_dev_promiscuous_enable,
227 .promiscuous_disable = i40e_dev_promiscuous_disable,
228 .allmulticast_enable = i40e_dev_allmulticast_enable,
229 .allmulticast_disable = i40e_dev_allmulticast_disable,
230 .dev_set_link_up = i40e_dev_set_link_up,
231 .dev_set_link_down = i40e_dev_set_link_down,
232 .link_update = i40e_dev_link_update,
233 .stats_get = i40e_dev_stats_get,
234 .stats_reset = i40e_dev_stats_reset,
235 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
236 .dev_infos_get = i40e_dev_info_get,
237 .vlan_filter_set = i40e_vlan_filter_set,
238 .vlan_tpid_set = i40e_vlan_tpid_set,
239 .vlan_offload_set = i40e_vlan_offload_set,
240 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
241 .vlan_pvid_set = i40e_vlan_pvid_set,
242 .rx_queue_start = i40e_dev_rx_queue_start,
243 .rx_queue_stop = i40e_dev_rx_queue_stop,
244 .tx_queue_start = i40e_dev_tx_queue_start,
245 .tx_queue_stop = i40e_dev_tx_queue_stop,
246 .rx_queue_setup = i40e_dev_rx_queue_setup,
247 .rx_queue_release = i40e_dev_rx_queue_release,
248 .rx_queue_count = i40e_dev_rx_queue_count,
249 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
250 .tx_queue_setup = i40e_dev_tx_queue_setup,
251 .tx_queue_release = i40e_dev_tx_queue_release,
252 .dev_led_on = i40e_dev_led_on,
253 .dev_led_off = i40e_dev_led_off,
254 .flow_ctrl_set = i40e_flow_ctrl_set,
255 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
256 .mac_addr_add = i40e_macaddr_add,
257 .mac_addr_remove = i40e_macaddr_remove,
258 .reta_update = i40e_dev_rss_reta_update,
259 .reta_query = i40e_dev_rss_reta_query,
260 .rss_hash_update = i40e_dev_rss_hash_update,
261 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
262 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
263 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
264 .filter_ctrl = i40e_dev_filter_ctrl,
267 static struct eth_driver rte_i40e_pmd = {
269 .name = "rte_i40e_pmd",
270 .id_table = pci_id_i40e_map,
271 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
273 .eth_dev_init = eth_i40e_dev_init,
274 .dev_private_size = sizeof(struct i40e_adapter),
278 i40e_align_floor(int n)
282 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
286 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
287 struct rte_eth_link *link)
289 struct rte_eth_link *dst = link;
290 struct rte_eth_link *src = &(dev->data->dev_link);
292 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
293 *(uint64_t *)src) == 0)
300 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
301 struct rte_eth_link *link)
303 struct rte_eth_link *dst = &(dev->data->dev_link);
304 struct rte_eth_link *src = link;
306 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
307 *(uint64_t *)src) == 0)
314 * Driver initialization routine.
315 * Invoked once at EAL init time.
316 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
319 rte_i40e_pmd_init(const char *name __rte_unused,
320 const char *params __rte_unused)
322 PMD_INIT_FUNC_TRACE();
323 rte_eth_driver_register(&rte_i40e_pmd);
328 static struct rte_driver rte_i40e_driver = {
330 .init = rte_i40e_pmd_init,
333 PMD_REGISTER_DRIVER(rte_i40e_driver);
336 * Initialize registers for flexible payload, which should be set by NVM.
337 * This should be removed from code once it is fixed in NVM.
339 #ifndef I40E_GLQF_ORT
340 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
342 #ifndef I40E_GLQF_PIT
343 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
346 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
348 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
349 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
350 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
351 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
352 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
353 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
354 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
355 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
356 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
357 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
359 /* GLQF_PIT Registers */
360 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
361 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
365 eth_i40e_dev_init(struct rte_eth_dev *dev)
367 struct rte_pci_device *pci_dev;
368 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
369 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
370 struct i40e_vsi *vsi;
375 PMD_INIT_FUNC_TRACE();
377 dev->dev_ops = &i40e_eth_dev_ops;
378 dev->rx_pkt_burst = i40e_recv_pkts;
379 dev->tx_pkt_burst = i40e_xmit_pkts;
381 /* for secondary processes, we don't initialise any further as primary
382 * has already done this work. Only check we don't need a different
384 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
385 if (dev->data->scattered_rx)
386 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
389 pci_dev = dev->pci_dev;
390 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
391 pf->adapter->eth_dev = dev;
392 pf->dev_data = dev->data;
394 hw->back = I40E_PF_TO_ADAPTER(pf);
395 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
397 PMD_INIT_LOG(ERR, "Hardware is not available, "
398 "as address is NULL");
402 hw->vendor_id = pci_dev->id.vendor_id;
403 hw->device_id = pci_dev->id.device_id;
404 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
405 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
406 hw->bus.device = pci_dev->addr.devid;
407 hw->bus.func = pci_dev->addr.function;
409 /* Make sure all is clean before doing PF reset */
412 /* Initialize the hardware */
415 /* Reset here to make sure all is clean for each PF */
416 ret = i40e_pf_reset(hw);
418 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
422 /* Initialize the shared code (base driver) */
423 ret = i40e_init_shared_code(hw);
425 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
430 * To work around the NVM issue,initialize registers
431 * for flexible payload by software.
432 * It should be removed once issues are fixed in NVM.
434 i40e_flex_payload_reg_init(hw);
436 /* Initialize the parameters for adminq */
437 i40e_init_adminq_parameter(hw);
438 ret = i40e_init_adminq(hw);
439 if (ret != I40E_SUCCESS) {
440 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
443 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
444 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
445 hw->aq.api_maj_ver, hw->aq.api_min_ver,
446 ((hw->nvm.version >> 12) & 0xf),
447 ((hw->nvm.version >> 4) & 0xff),
448 (hw->nvm.version & 0xf), hw->nvm.eetrack);
451 ret = i40e_aq_stop_lldp(hw, true, NULL);
452 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
453 PMD_INIT_LOG(INFO, "Failed to stop lldp");
456 i40e_clear_pxe_mode(hw);
459 * On X710, performance number is far from the expectation on recent
460 * firmware versions. The fix for this issue may not be integrated in
461 * the following firmware version. So the workaround in software driver
462 * is needed. It needs to modify the initial values of 3 internal only
463 * registers. Note that the workaround can be removed when it is fixed
464 * in firmware in the future.
466 i40e_configure_registers(hw);
468 /* Get hw capabilities */
469 ret = i40e_get_cap(hw);
470 if (ret != I40E_SUCCESS) {
471 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
472 goto err_get_capabilities;
475 /* Initialize parameters for PF */
476 ret = i40e_pf_parameter_init(dev);
478 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
479 goto err_parameter_init;
482 /* Initialize the queue management */
483 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
485 PMD_INIT_LOG(ERR, "Failed to init queue pool");
486 goto err_qp_pool_init;
488 ret = i40e_res_pool_init(&pf->msix_pool, 1,
489 hw->func_caps.num_msix_vectors - 1);
491 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
492 goto err_msix_pool_init;
495 /* Initialize lan hmc */
496 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
497 hw->func_caps.num_rx_qp, 0, 0);
498 if (ret != I40E_SUCCESS) {
499 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
500 goto err_init_lan_hmc;
503 /* Configure lan hmc */
504 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
505 if (ret != I40E_SUCCESS) {
506 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
507 goto err_configure_lan_hmc;
510 /* Get and check the mac address */
511 i40e_get_mac_addr(hw, hw->mac.addr);
512 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
513 PMD_INIT_LOG(ERR, "mac address is not valid");
515 goto err_get_mac_addr;
517 /* Copy the permanent MAC address */
518 ether_addr_copy((struct ether_addr *) hw->mac.addr,
519 (struct ether_addr *) hw->mac.perm_addr);
521 /* Disable flow control */
522 hw->fc.requested_mode = I40E_FC_NONE;
523 i40e_set_fc(hw, &aq_fail, TRUE);
525 /* PF setup, which includes VSI setup */
526 ret = i40e_pf_setup(pf);
528 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
529 goto err_setup_pf_switch;
534 /* Disable double vlan by default */
535 i40e_vsi_config_double_vlan(vsi, FALSE);
537 if (!vsi->max_macaddrs)
538 len = ETHER_ADDR_LEN;
540 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
542 /* Should be after VSI initialized */
543 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
544 if (!dev->data->mac_addrs) {
545 PMD_INIT_LOG(ERR, "Failed to allocated memory "
546 "for storing mac address");
549 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
550 &dev->data->mac_addrs[0]);
552 /* initialize pf host driver to setup SRIOV resource if applicable */
553 i40e_pf_host_init(dev);
555 /* register callback func to eal lib */
556 rte_intr_callback_register(&(pci_dev->intr_handle),
557 i40e_dev_interrupt_handler, (void *)dev);
559 /* configure and enable device interrupt */
560 i40e_pf_config_irq0(hw);
561 i40e_pf_enable_irq0(hw);
563 /* enable uio intr after callback register */
564 rte_intr_enable(&(pci_dev->intr_handle));
569 i40e_vsi_release(pf->main_vsi);
572 err_configure_lan_hmc:
573 (void)i40e_shutdown_lan_hmc(hw);
575 i40e_res_pool_destroy(&pf->msix_pool);
577 i40e_res_pool_destroy(&pf->qp_pool);
580 err_get_capabilities:
581 (void)i40e_shutdown_adminq(hw);
587 i40e_dev_configure(struct rte_eth_dev *dev)
589 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
590 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
593 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
594 ret = i40e_fdir_setup(pf);
595 if (ret != I40E_SUCCESS) {
596 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
599 ret = i40e_fdir_configure(dev);
601 PMD_DRV_LOG(ERR, "failed to configure fdir.");
605 i40e_fdir_teardown(pf);
607 ret = i40e_dev_init_vlan(dev);
612 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
613 * RSS setting have different requirements.
614 * General PMD driver call sequence are NIC init, configure,
615 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
616 * will try to lookup the VSI that specific queue belongs to if VMDQ
617 * applicable. So, VMDQ setting has to be done before
618 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
619 * For RSS setting, it will try to calculate actual configured RX queue
620 * number, which will be available after rx_queue_setup(). dev_start()
621 * function is good to place RSS setup.
623 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
624 ret = i40e_vmdq_setup(dev);
630 i40e_fdir_teardown(pf);
635 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
637 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
638 uint16_t msix_vect = vsi->msix_intr;
641 for (i = 0; i < vsi->nb_qps; i++) {
642 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
643 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
647 if (vsi->type != I40E_VSI_SRIOV) {
648 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
649 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
653 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
654 vsi->user_param + (msix_vect - 1);
656 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
658 I40E_WRITE_FLUSH(hw);
661 static inline uint16_t
662 i40e_calc_itr_interval(int16_t interval)
664 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
665 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
667 /* Convert to hardware count, as writing each 1 represents 2 us */
672 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
675 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
676 uint16_t msix_vect = vsi->msix_intr;
679 for (i = 0; i < vsi->nb_qps; i++)
680 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
682 /* Bind all RX queues to allocated MSIX interrupt */
683 for (i = 0; i < vsi->nb_qps; i++) {
684 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
685 I40E_QINT_RQCTL_ITR_INDX_MASK |
686 ((vsi->base_queue + i + 1) <<
687 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
688 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
689 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
691 if (i == vsi->nb_qps - 1)
692 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
693 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
696 /* Write first RX queue to Link list register as the head element */
697 if (vsi->type != I40E_VSI_SRIOV) {
699 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
701 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
703 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
704 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
706 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
707 msix_vect - 1), interval);
709 #ifndef I40E_GLINT_CTL
710 #define I40E_GLINT_CTL 0x0003F800
711 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
713 /* Disable auto-mask on enabling of all none-zero interrupt */
714 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
715 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
719 /* num_msix_vectors_vf needs to minus irq0 */
720 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
721 vsi->user_param + (msix_vect - 1);
723 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
724 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
725 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
728 I40E_WRITE_FLUSH(hw);
732 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
734 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
735 uint16_t interval = i40e_calc_itr_interval(\
736 RTE_LIBRTE_I40E_ITR_INTERVAL);
738 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
739 I40E_PFINT_DYN_CTLN_INTENA_MASK |
740 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
741 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
742 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
746 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
748 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
750 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
753 static inline uint8_t
754 i40e_parse_link_speed(uint16_t eth_link_speed)
756 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
758 switch (eth_link_speed) {
759 case ETH_LINK_SPEED_40G:
760 link_speed = I40E_LINK_SPEED_40GB;
762 case ETH_LINK_SPEED_20G:
763 link_speed = I40E_LINK_SPEED_20GB;
765 case ETH_LINK_SPEED_10G:
766 link_speed = I40E_LINK_SPEED_10GB;
768 case ETH_LINK_SPEED_1000:
769 link_speed = I40E_LINK_SPEED_1GB;
771 case ETH_LINK_SPEED_100:
772 link_speed = I40E_LINK_SPEED_100MB;
780 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
782 enum i40e_status_code status;
783 struct i40e_aq_get_phy_abilities_resp phy_ab;
784 struct i40e_aq_set_phy_config phy_conf;
785 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
786 I40E_AQ_PHY_FLAG_PAUSE_RX |
787 I40E_AQ_PHY_FLAG_LOW_POWER;
788 const uint8_t advt = I40E_LINK_SPEED_40GB |
789 I40E_LINK_SPEED_10GB |
790 I40E_LINK_SPEED_1GB |
791 I40E_LINK_SPEED_100MB;
794 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
799 memset(&phy_conf, 0, sizeof(phy_conf));
801 /* bits 0-2 use the values from get_phy_abilities_resp */
803 abilities |= phy_ab.abilities & mask;
805 /* update ablities and speed */
806 if (abilities & I40E_AQ_PHY_AN_ENABLED)
807 phy_conf.link_speed = advt;
809 phy_conf.link_speed = force_speed;
811 phy_conf.abilities = abilities;
813 /* use get_phy_abilities_resp value for the rest */
814 phy_conf.phy_type = phy_ab.phy_type;
815 phy_conf.eee_capability = phy_ab.eee_capability;
816 phy_conf.eeer = phy_ab.eeer_val;
817 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
819 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
820 phy_ab.abilities, phy_ab.link_speed);
821 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
822 phy_conf.abilities, phy_conf.link_speed);
824 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
832 i40e_apply_link_speed(struct rte_eth_dev *dev)
835 uint8_t abilities = 0;
836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
837 struct rte_eth_conf *conf = &dev->data->dev_conf;
839 speed = i40e_parse_link_speed(conf->link_speed);
840 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
841 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
842 abilities |= I40E_AQ_PHY_AN_ENABLED;
844 abilities |= I40E_AQ_PHY_LINK_ENABLED;
846 return i40e_phy_conf_link(hw, abilities, speed);
850 i40e_dev_start(struct rte_eth_dev *dev)
852 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
853 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
854 struct i40e_vsi *main_vsi = pf->main_vsi;
857 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
858 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
859 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
860 dev->data->dev_conf.link_duplex,
866 ret = i40e_dev_rxtx_init(pf);
867 if (ret != I40E_SUCCESS) {
868 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
872 /* Map queues with MSIX interrupt */
873 i40e_vsi_queues_bind_intr(main_vsi);
874 i40e_vsi_enable_queues_intr(main_vsi);
876 /* Map VMDQ VSI queues with MSIX interrupt */
877 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
878 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
879 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
882 /* enable FDIR MSIX interrupt */
883 if (pf->fdir.fdir_vsi) {
884 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
885 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
888 /* Enable all queues which have been configured */
889 ret = i40e_dev_switch_queues(pf, TRUE);
890 if (ret != I40E_SUCCESS) {
891 PMD_DRV_LOG(ERR, "Failed to enable VSI");
895 /* Enable receiving broadcast packets */
896 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
897 if (ret != I40E_SUCCESS)
898 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
900 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
901 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
903 if (ret != I40E_SUCCESS)
904 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
907 /* Apply link configure */
908 ret = i40e_apply_link_speed(dev);
909 if (I40E_SUCCESS != ret) {
910 PMD_DRV_LOG(ERR, "Fail to apply link setting");
917 i40e_dev_switch_queues(pf, FALSE);
918 i40e_dev_clear_queues(dev);
924 i40e_dev_stop(struct rte_eth_dev *dev)
926 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
927 struct i40e_vsi *main_vsi = pf->main_vsi;
930 /* Disable all queues */
931 i40e_dev_switch_queues(pf, FALSE);
933 /* un-map queues with interrupt registers */
934 i40e_vsi_disable_queues_intr(main_vsi);
935 i40e_vsi_queues_unbind_intr(main_vsi);
937 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
938 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
939 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
942 if (pf->fdir.fdir_vsi) {
943 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
944 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
946 /* Clear all queues and release memory */
947 i40e_dev_clear_queues(dev);
950 i40e_dev_set_link_down(dev);
955 i40e_dev_close(struct rte_eth_dev *dev)
957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
961 PMD_INIT_FUNC_TRACE();
965 /* Disable interrupt */
966 i40e_pf_disable_irq0(hw);
967 rte_intr_disable(&(dev->pci_dev->intr_handle));
969 /* shutdown and destroy the HMC */
970 i40e_shutdown_lan_hmc(hw);
972 /* release all the existing VSIs and VEBs */
973 i40e_fdir_teardown(pf);
974 i40e_vsi_release(pf->main_vsi);
976 /* shutdown the adminq */
977 i40e_aq_queue_shutdown(hw, true);
978 i40e_shutdown_adminq(hw);
980 i40e_res_pool_destroy(&pf->qp_pool);
981 i40e_res_pool_destroy(&pf->msix_pool);
983 /* force a PF reset to clean anything leftover */
984 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
985 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
986 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
987 I40E_WRITE_FLUSH(hw);
991 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
993 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
994 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
995 struct i40e_vsi *vsi = pf->main_vsi;
998 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1000 if (status != I40E_SUCCESS)
1001 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1003 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1005 if (status != I40E_SUCCESS)
1006 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1011 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1013 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015 struct i40e_vsi *vsi = pf->main_vsi;
1018 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1020 if (status != I40E_SUCCESS)
1021 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1023 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1025 if (status != I40E_SUCCESS)
1026 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1030 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1032 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034 struct i40e_vsi *vsi = pf->main_vsi;
1037 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1038 if (ret != I40E_SUCCESS)
1039 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1043 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047 struct i40e_vsi *vsi = pf->main_vsi;
1050 if (dev->data->promiscuous == 1)
1051 return; /* must remain in all_multicast mode */
1053 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1054 vsi->seid, FALSE, NULL);
1055 if (ret != I40E_SUCCESS)
1056 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1060 * Set device link up.
1063 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1065 /* re-apply link speed setting */
1066 return i40e_apply_link_speed(dev);
1070 * Set device link down.
1073 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1075 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1076 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1077 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1079 return i40e_phy_conf_link(hw, abilities, speed);
1083 i40e_dev_link_update(struct rte_eth_dev *dev,
1084 int wait_to_complete)
1086 #define CHECK_INTERVAL 100 /* 100ms */
1087 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1088 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089 struct i40e_link_status link_status;
1090 struct rte_eth_link link, old;
1092 unsigned rep_cnt = MAX_REPEAT_TIME;
1094 memset(&link, 0, sizeof(link));
1095 memset(&old, 0, sizeof(old));
1096 memset(&link_status, 0, sizeof(link_status));
1097 rte_i40e_dev_atomic_read_link_status(dev, &old);
1100 /* Get link status information from hardware */
1101 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1102 if (status != I40E_SUCCESS) {
1103 link.link_speed = ETH_LINK_SPEED_100;
1104 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1105 PMD_DRV_LOG(ERR, "Failed to get link info");
1109 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1110 if (!wait_to_complete)
1113 rte_delay_ms(CHECK_INTERVAL);
1114 } while (!link.link_status && rep_cnt--);
1116 if (!link.link_status)
1119 /* i40e uses full duplex only */
1120 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1122 /* Parse the link status */
1123 switch (link_status.link_speed) {
1124 case I40E_LINK_SPEED_100MB:
1125 link.link_speed = ETH_LINK_SPEED_100;
1127 case I40E_LINK_SPEED_1GB:
1128 link.link_speed = ETH_LINK_SPEED_1000;
1130 case I40E_LINK_SPEED_10GB:
1131 link.link_speed = ETH_LINK_SPEED_10G;
1133 case I40E_LINK_SPEED_20GB:
1134 link.link_speed = ETH_LINK_SPEED_20G;
1136 case I40E_LINK_SPEED_40GB:
1137 link.link_speed = ETH_LINK_SPEED_40G;
1140 link.link_speed = ETH_LINK_SPEED_100;
1145 rte_i40e_dev_atomic_write_link_status(dev, &link);
1146 if (link.link_status == old.link_status)
1152 /* Get all the statistics of a VSI */
1154 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1156 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1157 struct i40e_eth_stats *nes = &vsi->eth_stats;
1158 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1159 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1161 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1162 vsi->offset_loaded, &oes->rx_bytes,
1164 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1165 vsi->offset_loaded, &oes->rx_unicast,
1167 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1168 vsi->offset_loaded, &oes->rx_multicast,
1169 &nes->rx_multicast);
1170 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1171 vsi->offset_loaded, &oes->rx_broadcast,
1172 &nes->rx_broadcast);
1173 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1174 &oes->rx_discards, &nes->rx_discards);
1175 /* GLV_REPC not supported */
1176 /* GLV_RMPC not supported */
1177 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1178 &oes->rx_unknown_protocol,
1179 &nes->rx_unknown_protocol);
1180 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1181 vsi->offset_loaded, &oes->tx_bytes,
1183 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1184 vsi->offset_loaded, &oes->tx_unicast,
1186 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1187 vsi->offset_loaded, &oes->tx_multicast,
1188 &nes->tx_multicast);
1189 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1190 vsi->offset_loaded, &oes->tx_broadcast,
1191 &nes->tx_broadcast);
1192 /* GLV_TDPC not supported */
1193 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1194 &oes->tx_errors, &nes->tx_errors);
1195 vsi->offset_loaded = true;
1197 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1199 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1200 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1201 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1202 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1203 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1204 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1205 nes->rx_unknown_protocol);
1206 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1207 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1208 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1209 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1210 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1211 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1212 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1216 /* Get all statistics of a port */
1218 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1221 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1222 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1223 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1224 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1226 /* Get statistics of struct i40e_eth_stats */
1227 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1228 I40E_GLPRT_GORCL(hw->port),
1229 pf->offset_loaded, &os->eth.rx_bytes,
1231 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1232 I40E_GLPRT_UPRCL(hw->port),
1233 pf->offset_loaded, &os->eth.rx_unicast,
1234 &ns->eth.rx_unicast);
1235 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1236 I40E_GLPRT_MPRCL(hw->port),
1237 pf->offset_loaded, &os->eth.rx_multicast,
1238 &ns->eth.rx_multicast);
1239 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1240 I40E_GLPRT_BPRCL(hw->port),
1241 pf->offset_loaded, &os->eth.rx_broadcast,
1242 &ns->eth.rx_broadcast);
1243 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1244 pf->offset_loaded, &os->eth.rx_discards,
1245 &ns->eth.rx_discards);
1246 /* GLPRT_REPC not supported */
1247 /* GLPRT_RMPC not supported */
1248 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1250 &os->eth.rx_unknown_protocol,
1251 &ns->eth.rx_unknown_protocol);
1252 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1253 I40E_GLPRT_GOTCL(hw->port),
1254 pf->offset_loaded, &os->eth.tx_bytes,
1256 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1257 I40E_GLPRT_UPTCL(hw->port),
1258 pf->offset_loaded, &os->eth.tx_unicast,
1259 &ns->eth.tx_unicast);
1260 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1261 I40E_GLPRT_MPTCL(hw->port),
1262 pf->offset_loaded, &os->eth.tx_multicast,
1263 &ns->eth.tx_multicast);
1264 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1265 I40E_GLPRT_BPTCL(hw->port),
1266 pf->offset_loaded, &os->eth.tx_broadcast,
1267 &ns->eth.tx_broadcast);
1268 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1269 pf->offset_loaded, &os->eth.tx_discards,
1270 &ns->eth.tx_discards);
1271 /* GLPRT_TEPC not supported */
1273 /* additional port specific stats */
1274 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1275 pf->offset_loaded, &os->tx_dropped_link_down,
1276 &ns->tx_dropped_link_down);
1277 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1278 pf->offset_loaded, &os->crc_errors,
1280 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1281 pf->offset_loaded, &os->illegal_bytes,
1282 &ns->illegal_bytes);
1283 /* GLPRT_ERRBC not supported */
1284 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1285 pf->offset_loaded, &os->mac_local_faults,
1286 &ns->mac_local_faults);
1287 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1288 pf->offset_loaded, &os->mac_remote_faults,
1289 &ns->mac_remote_faults);
1290 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1291 pf->offset_loaded, &os->rx_length_errors,
1292 &ns->rx_length_errors);
1293 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1294 pf->offset_loaded, &os->link_xon_rx,
1296 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1297 pf->offset_loaded, &os->link_xoff_rx,
1299 for (i = 0; i < 8; i++) {
1300 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1302 &os->priority_xon_rx[i],
1303 &ns->priority_xon_rx[i]);
1304 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1306 &os->priority_xoff_rx[i],
1307 &ns->priority_xoff_rx[i]);
1309 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1310 pf->offset_loaded, &os->link_xon_tx,
1312 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1313 pf->offset_loaded, &os->link_xoff_tx,
1315 for (i = 0; i < 8; i++) {
1316 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1318 &os->priority_xon_tx[i],
1319 &ns->priority_xon_tx[i]);
1320 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1322 &os->priority_xoff_tx[i],
1323 &ns->priority_xoff_tx[i]);
1324 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1326 &os->priority_xon_2_xoff[i],
1327 &ns->priority_xon_2_xoff[i]);
1329 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1330 I40E_GLPRT_PRC64L(hw->port),
1331 pf->offset_loaded, &os->rx_size_64,
1333 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1334 I40E_GLPRT_PRC127L(hw->port),
1335 pf->offset_loaded, &os->rx_size_127,
1337 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1338 I40E_GLPRT_PRC255L(hw->port),
1339 pf->offset_loaded, &os->rx_size_255,
1341 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1342 I40E_GLPRT_PRC511L(hw->port),
1343 pf->offset_loaded, &os->rx_size_511,
1345 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1346 I40E_GLPRT_PRC1023L(hw->port),
1347 pf->offset_loaded, &os->rx_size_1023,
1349 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1350 I40E_GLPRT_PRC1522L(hw->port),
1351 pf->offset_loaded, &os->rx_size_1522,
1353 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1354 I40E_GLPRT_PRC9522L(hw->port),
1355 pf->offset_loaded, &os->rx_size_big,
1357 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1358 pf->offset_loaded, &os->rx_undersize,
1360 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1361 pf->offset_loaded, &os->rx_fragments,
1363 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1364 pf->offset_loaded, &os->rx_oversize,
1366 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1367 pf->offset_loaded, &os->rx_jabber,
1369 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1370 I40E_GLPRT_PTC64L(hw->port),
1371 pf->offset_loaded, &os->tx_size_64,
1373 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1374 I40E_GLPRT_PTC127L(hw->port),
1375 pf->offset_loaded, &os->tx_size_127,
1377 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1378 I40E_GLPRT_PTC255L(hw->port),
1379 pf->offset_loaded, &os->tx_size_255,
1381 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1382 I40E_GLPRT_PTC511L(hw->port),
1383 pf->offset_loaded, &os->tx_size_511,
1385 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1386 I40E_GLPRT_PTC1023L(hw->port),
1387 pf->offset_loaded, &os->tx_size_1023,
1389 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1390 I40E_GLPRT_PTC1522L(hw->port),
1391 pf->offset_loaded, &os->tx_size_1522,
1393 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1394 I40E_GLPRT_PTC9522L(hw->port),
1395 pf->offset_loaded, &os->tx_size_big,
1397 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1399 &os->fd_sb_match, &ns->fd_sb_match);
1400 /* GLPRT_MSPDC not supported */
1401 /* GLPRT_XEC not supported */
1403 pf->offset_loaded = true;
1406 i40e_update_vsi_stats(pf->main_vsi);
1408 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1409 ns->eth.rx_broadcast;
1410 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1411 ns->eth.tx_broadcast;
1412 stats->ibytes = ns->eth.rx_bytes;
1413 stats->obytes = ns->eth.tx_bytes;
1414 stats->oerrors = ns->eth.tx_errors;
1415 stats->imcasts = ns->eth.rx_multicast;
1416 stats->fdirmatch = ns->fd_sb_match;
1419 stats->ibadcrc = ns->crc_errors;
1420 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1421 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1422 stats->imissed = ns->eth.rx_discards;
1423 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1425 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1426 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1427 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1428 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1429 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1430 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1431 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1432 ns->eth.rx_unknown_protocol);
1433 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1434 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1435 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1436 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1437 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1438 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1440 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1441 ns->tx_dropped_link_down);
1442 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1443 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1445 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1446 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1447 ns->mac_local_faults);
1448 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1449 ns->mac_remote_faults);
1450 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1451 ns->rx_length_errors);
1452 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1453 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1454 for (i = 0; i < 8; i++) {
1455 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1456 i, ns->priority_xon_rx[i]);
1457 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1458 i, ns->priority_xoff_rx[i]);
1460 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1461 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1462 for (i = 0; i < 8; i++) {
1463 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1464 i, ns->priority_xon_tx[i]);
1465 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1466 i, ns->priority_xoff_tx[i]);
1467 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1468 i, ns->priority_xon_2_xoff[i]);
1470 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1471 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1472 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1473 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1474 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1475 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1476 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1477 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1478 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1479 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1480 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1481 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1482 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1483 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1484 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1485 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1486 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1487 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1488 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1489 ns->mac_short_packet_dropped);
1490 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1491 ns->checksum_error);
1492 PMD_DRV_LOG(DEBUG, "fdir_match: %lu", ns->fd_sb_match);
1493 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1496 /* Reset the statistics */
1498 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1500 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1502 /* It results in reloading the start point of each counter */
1503 pf->offset_loaded = false;
1507 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1508 __rte_unused uint16_t queue_id,
1509 __rte_unused uint8_t stat_idx,
1510 __rte_unused uint8_t is_rx)
1512 PMD_INIT_FUNC_TRACE();
1518 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1520 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1521 struct i40e_vsi *vsi = pf->main_vsi;
1523 dev_info->max_rx_queues = vsi->nb_qps;
1524 dev_info->max_tx_queues = vsi->nb_qps;
1525 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1526 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1527 dev_info->max_mac_addrs = vsi->max_macaddrs;
1528 dev_info->max_vfs = dev->pci_dev->max_vfs;
1529 dev_info->rx_offload_capa =
1530 DEV_RX_OFFLOAD_VLAN_STRIP |
1531 DEV_RX_OFFLOAD_IPV4_CKSUM |
1532 DEV_RX_OFFLOAD_UDP_CKSUM |
1533 DEV_RX_OFFLOAD_TCP_CKSUM;
1534 dev_info->tx_offload_capa =
1535 DEV_TX_OFFLOAD_VLAN_INSERT |
1536 DEV_TX_OFFLOAD_IPV4_CKSUM |
1537 DEV_TX_OFFLOAD_UDP_CKSUM |
1538 DEV_TX_OFFLOAD_TCP_CKSUM |
1539 DEV_TX_OFFLOAD_SCTP_CKSUM |
1540 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1541 DEV_TX_OFFLOAD_TCP_TSO;
1542 dev_info->reta_size = pf->hash_lut_size;
1543 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1545 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1547 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1548 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1549 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1551 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1555 dev_info->default_txconf = (struct rte_eth_txconf) {
1557 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1558 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1559 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1561 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1562 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1563 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1564 ETH_TXQ_FLAGS_NOOFFLOADS,
1567 if (pf->flags | I40E_FLAG_VMDQ) {
1568 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1569 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1570 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1571 pf->max_nb_vmdq_vsi;
1572 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1573 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1574 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1579 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1581 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1582 struct i40e_vsi *vsi = pf->main_vsi;
1583 PMD_INIT_FUNC_TRACE();
1586 return i40e_vsi_add_vlan(vsi, vlan_id);
1588 return i40e_vsi_delete_vlan(vsi, vlan_id);
1592 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1593 __rte_unused uint16_t tpid)
1595 PMD_INIT_FUNC_TRACE();
1599 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1601 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1602 struct i40e_vsi *vsi = pf->main_vsi;
1604 if (mask & ETH_VLAN_STRIP_MASK) {
1605 /* Enable or disable VLAN stripping */
1606 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1607 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1609 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1612 if (mask & ETH_VLAN_EXTEND_MASK) {
1613 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1614 i40e_vsi_config_double_vlan(vsi, TRUE);
1616 i40e_vsi_config_double_vlan(vsi, FALSE);
1621 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1622 __rte_unused uint16_t queue,
1623 __rte_unused int on)
1625 PMD_INIT_FUNC_TRACE();
1629 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1632 struct i40e_vsi *vsi = pf->main_vsi;
1633 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1634 struct i40e_vsi_vlan_pvid_info info;
1636 memset(&info, 0, sizeof(info));
1639 info.config.pvid = pvid;
1641 info.config.reject.tagged =
1642 data->dev_conf.txmode.hw_vlan_reject_tagged;
1643 info.config.reject.untagged =
1644 data->dev_conf.txmode.hw_vlan_reject_untagged;
1647 return i40e_vsi_vlan_pvid_set(vsi, &info);
1651 i40e_dev_led_on(struct rte_eth_dev *dev)
1653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 uint32_t mode = i40e_led_get(hw);
1657 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1663 i40e_dev_led_off(struct rte_eth_dev *dev)
1665 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 uint32_t mode = i40e_led_get(hw);
1669 i40e_led_set(hw, 0, false);
1675 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1676 __rte_unused struct rte_eth_fc_conf *fc_conf)
1678 PMD_INIT_FUNC_TRACE();
1684 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1685 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1687 PMD_INIT_FUNC_TRACE();
1692 /* Add a MAC address, and update filters */
1694 i40e_macaddr_add(struct rte_eth_dev *dev,
1695 struct ether_addr *mac_addr,
1696 __rte_unused uint32_t index,
1699 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1700 struct i40e_mac_filter_info mac_filter;
1701 struct i40e_vsi *vsi;
1704 /* If VMDQ not enabled or configured, return */
1705 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1706 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1707 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1712 if (pool > pf->nb_cfg_vmdq_vsi) {
1713 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1714 pool, pf->nb_cfg_vmdq_vsi);
1718 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1719 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1724 vsi = pf->vmdq[pool - 1].vsi;
1726 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1727 if (ret != I40E_SUCCESS) {
1728 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1733 /* Remove a MAC address, and update filters */
1735 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1737 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1738 struct i40e_vsi *vsi;
1739 struct rte_eth_dev_data *data = dev->data;
1740 struct ether_addr *macaddr;
1745 macaddr = &(data->mac_addrs[index]);
1747 pool_sel = dev->data->mac_pool_sel[index];
1749 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1750 if (pool_sel & (1ULL << i)) {
1754 /* No VMDQ pool enabled or configured */
1755 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1756 (i > pf->nb_cfg_vmdq_vsi)) {
1757 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1761 vsi = pf->vmdq[i - 1].vsi;
1763 ret = i40e_vsi_delete_mac(vsi, macaddr);
1766 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1773 /* Set perfect match or hash match of MAC and VLAN for a VF */
1775 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1776 struct rte_eth_mac_filter *filter,
1780 struct i40e_mac_filter_info mac_filter;
1781 struct ether_addr old_mac;
1782 struct ether_addr *new_mac;
1783 struct i40e_pf_vf *vf = NULL;
1788 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1791 hw = I40E_PF_TO_HW(pf);
1793 if (filter == NULL) {
1794 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1798 new_mac = &filter->mac_addr;
1800 if (is_zero_ether_addr(new_mac)) {
1801 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1805 vf_id = filter->dst_id;
1807 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1808 PMD_DRV_LOG(ERR, "Invalid argument.");
1811 vf = &pf->vfs[vf_id];
1813 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1814 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1819 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1820 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1822 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1825 mac_filter.filter_type = filter->filter_type;
1826 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1827 if (ret != I40E_SUCCESS) {
1828 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1831 ether_addr_copy(new_mac, &pf->dev_addr);
1833 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1835 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1836 if (ret != I40E_SUCCESS) {
1837 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1841 /* Clear device address as it has been removed */
1842 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1843 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1849 /* MAC filter handle */
1851 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1854 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1855 struct rte_eth_mac_filter *filter;
1856 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1857 int ret = I40E_NOT_SUPPORTED;
1859 filter = (struct rte_eth_mac_filter *)(arg);
1861 switch (filter_op) {
1862 case RTE_ETH_FILTER_NOP:
1865 case RTE_ETH_FILTER_ADD:
1866 i40e_pf_disable_irq0(hw);
1868 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1869 i40e_pf_enable_irq0(hw);
1871 case RTE_ETH_FILTER_DELETE:
1872 i40e_pf_disable_irq0(hw);
1874 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1875 i40e_pf_enable_irq0(hw);
1878 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1879 ret = I40E_ERR_PARAM;
1887 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1888 struct rte_eth_rss_reta_entry64 *reta_conf,
1891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894 uint16_t i, j, lut_size = pf->hash_lut_size;
1895 uint16_t idx, shift;
1898 if (reta_size != lut_size ||
1899 reta_size > ETH_RSS_RETA_SIZE_512) {
1900 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1901 "(%d) doesn't match the number hardware can supported "
1902 "(%d)\n", reta_size, lut_size);
1906 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1907 idx = i / RTE_RETA_GROUP_SIZE;
1908 shift = i % RTE_RETA_GROUP_SIZE;
1909 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1913 if (mask == I40E_4_BIT_MASK)
1916 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1917 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1918 if (mask & (0x1 << j))
1919 lut |= reta_conf[idx].reta[shift + j] <<
1922 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1924 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1931 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1932 struct rte_eth_rss_reta_entry64 *reta_conf,
1935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 uint16_t i, j, lut_size = pf->hash_lut_size;
1939 uint16_t idx, shift;
1942 if (reta_size != lut_size ||
1943 reta_size > ETH_RSS_RETA_SIZE_512) {
1944 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1945 "(%d) doesn't match the number hardware can supported "
1946 "(%d)\n", reta_size, lut_size);
1950 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1951 idx = i / RTE_RETA_GROUP_SIZE;
1952 shift = i % RTE_RETA_GROUP_SIZE;
1953 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1958 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1959 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1960 if (mask & (0x1 << j))
1961 reta_conf[idx].reta[shift + j] = ((lut >>
1962 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1970 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1971 * @hw: pointer to the HW structure
1972 * @mem: pointer to mem struct to fill out
1973 * @size: size of memory requested
1974 * @alignment: what to align the allocation to
1976 enum i40e_status_code
1977 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1978 struct i40e_dma_mem *mem,
1982 static uint64_t id = 0;
1983 const struct rte_memzone *mz = NULL;
1984 char z_name[RTE_MEMZONE_NAMESIZE];
1987 return I40E_ERR_PARAM;
1990 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1991 #ifdef RTE_LIBRTE_XEN_DOM0
1992 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1995 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1998 return I40E_ERR_NO_MEMORY;
2003 #ifdef RTE_LIBRTE_XEN_DOM0
2004 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2006 mem->pa = mz->phys_addr;
2009 return I40E_SUCCESS;
2013 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2014 * @hw: pointer to the HW structure
2015 * @mem: ptr to mem struct to free
2017 enum i40e_status_code
2018 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2019 struct i40e_dma_mem *mem)
2021 if (!mem || !mem->va)
2022 return I40E_ERR_PARAM;
2027 return I40E_SUCCESS;
2031 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2032 * @hw: pointer to the HW structure
2033 * @mem: pointer to mem struct to fill out
2034 * @size: size of memory requested
2036 enum i40e_status_code
2037 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2038 struct i40e_virt_mem *mem,
2042 return I40E_ERR_PARAM;
2045 mem->va = rte_zmalloc("i40e", size, 0);
2048 return I40E_SUCCESS;
2050 return I40E_ERR_NO_MEMORY;
2054 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2055 * @hw: pointer to the HW structure
2056 * @mem: pointer to mem struct to free
2058 enum i40e_status_code
2059 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2060 struct i40e_virt_mem *mem)
2063 return I40E_ERR_PARAM;
2068 return I40E_SUCCESS;
2072 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2074 rte_spinlock_init(&sp->spinlock);
2078 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2080 rte_spinlock_lock(&sp->spinlock);
2084 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2086 rte_spinlock_unlock(&sp->spinlock);
2090 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2096 * Get the hardware capabilities, which will be parsed
2097 * and saved into struct i40e_hw.
2100 i40e_get_cap(struct i40e_hw *hw)
2102 struct i40e_aqc_list_capabilities_element_resp *buf;
2103 uint16_t len, size = 0;
2106 /* Calculate a huge enough buff for saving response data temporarily */
2107 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2108 I40E_MAX_CAP_ELE_NUM;
2109 buf = rte_zmalloc("i40e", len, 0);
2111 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2112 return I40E_ERR_NO_MEMORY;
2115 /* Get, parse the capabilities and save it to hw */
2116 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2117 i40e_aqc_opc_list_func_capabilities, NULL);
2118 if (ret != I40E_SUCCESS)
2119 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2121 /* Free the temporary buffer after being used */
2128 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2130 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2132 uint16_t sum_queues = 0, sum_vsis, left_queues;
2134 /* First check if FW support SRIOV */
2135 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2136 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2140 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2141 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2142 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2143 /* Allocate queues for pf */
2144 if (hw->func_caps.rss) {
2145 pf->flags |= I40E_FLAG_RSS;
2146 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2147 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2148 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2151 sum_queues = pf->lan_nb_qps;
2152 /* Default VSI is not counted in */
2154 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2156 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2157 pf->flags |= I40E_FLAG_SRIOV;
2158 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2159 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2160 PMD_INIT_LOG(ERR, "Config VF number %u, "
2161 "max supported %u.",
2162 dev->pci_dev->max_vfs,
2163 hw->func_caps.num_vfs);
2166 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2167 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2168 "max support %u queues.",
2169 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2172 pf->vf_num = dev->pci_dev->max_vfs;
2173 sum_queues += pf->vf_nb_qps * pf->vf_num;
2174 sum_vsis += pf->vf_num;
2175 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2176 pf->vf_num, pf->vf_nb_qps);
2180 if (hw->func_caps.vmdq) {
2181 pf->flags |= I40E_FLAG_VMDQ;
2182 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2183 pf->max_nb_vmdq_vsi = 1;
2185 * If VMDQ available, assume a single VSI can be created. Will adjust
2188 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2189 sum_vsis += pf->max_nb_vmdq_vsi;
2191 pf->vmdq_nb_qps = 0;
2192 pf->max_nb_vmdq_vsi = 0;
2194 pf->nb_cfg_vmdq_vsi = 0;
2196 if (hw->func_caps.fd) {
2197 pf->flags |= I40E_FLAG_FDIR;
2198 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2200 * Each flow director consumes one VSI and one queue,
2201 * but can't calculate out predictably here.
2205 if (sum_vsis > pf->max_num_vsi ||
2206 sum_queues > hw->func_caps.num_rx_qp) {
2207 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2208 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2209 pf->max_num_vsi, sum_vsis);
2210 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2211 hw->func_caps.num_rx_qp, sum_queues);
2215 /* Adjust VMDQ setting to support as many VMs as possible */
2216 if (pf->flags & I40E_FLAG_VMDQ) {
2217 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2219 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2220 pf->max_num_vsi - sum_vsis);
2222 /* Limit the max VMDQ number that rte_ether that can support */
2223 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2226 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2227 pf->max_nb_vmdq_vsi);
2228 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2231 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2233 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2234 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2235 sum_vsis, hw->func_caps.num_msix_vectors);
2238 return I40E_SUCCESS;
2242 i40e_pf_get_switch_config(struct i40e_pf *pf)
2244 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2245 struct i40e_aqc_get_switch_config_resp *switch_config;
2246 struct i40e_aqc_switch_config_element_resp *element;
2247 uint16_t start_seid = 0, num_reported;
2250 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2251 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2252 if (!switch_config) {
2253 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2257 /* Get the switch configurations */
2258 ret = i40e_aq_get_switch_config(hw, switch_config,
2259 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2260 if (ret != I40E_SUCCESS) {
2261 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2264 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2265 if (num_reported != 1) { /* The number should be 1 */
2266 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2270 /* Parse the switch configuration elements */
2271 element = &(switch_config->element[0]);
2272 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2273 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2274 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2276 PMD_DRV_LOG(INFO, "Unknown element type");
2279 rte_free(switch_config);
2285 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2288 struct pool_entry *entry;
2290 if (pool == NULL || num == 0)
2293 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2294 if (entry == NULL) {
2295 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2299 /* queue heap initialize */
2300 pool->num_free = num;
2301 pool->num_alloc = 0;
2303 LIST_INIT(&pool->alloc_list);
2304 LIST_INIT(&pool->free_list);
2306 /* Initialize element */
2310 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2315 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2317 struct pool_entry *entry;
2322 LIST_FOREACH(entry, &pool->alloc_list, next) {
2323 LIST_REMOVE(entry, next);
2327 LIST_FOREACH(entry, &pool->free_list, next) {
2328 LIST_REMOVE(entry, next);
2333 pool->num_alloc = 0;
2335 LIST_INIT(&pool->alloc_list);
2336 LIST_INIT(&pool->free_list);
2340 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2343 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2344 uint32_t pool_offset;
2348 PMD_DRV_LOG(ERR, "Invalid parameter");
2352 pool_offset = base - pool->base;
2353 /* Lookup in alloc list */
2354 LIST_FOREACH(entry, &pool->alloc_list, next) {
2355 if (entry->base == pool_offset) {
2356 valid_entry = entry;
2357 LIST_REMOVE(entry, next);
2362 /* Not find, return */
2363 if (valid_entry == NULL) {
2364 PMD_DRV_LOG(ERR, "Failed to find entry");
2369 * Found it, move it to free list and try to merge.
2370 * In order to make merge easier, always sort it by qbase.
2371 * Find adjacent prev and last entries.
2374 LIST_FOREACH(entry, &pool->free_list, next) {
2375 if (entry->base > valid_entry->base) {
2383 /* Try to merge with next one*/
2385 /* Merge with next one */
2386 if (valid_entry->base + valid_entry->len == next->base) {
2387 next->base = valid_entry->base;
2388 next->len += valid_entry->len;
2389 rte_free(valid_entry);
2396 /* Merge with previous one */
2397 if (prev->base + prev->len == valid_entry->base) {
2398 prev->len += valid_entry->len;
2399 /* If it merge with next one, remove next node */
2401 LIST_REMOVE(valid_entry, next);
2402 rte_free(valid_entry);
2404 rte_free(valid_entry);
2410 /* Not find any entry to merge, insert */
2413 LIST_INSERT_AFTER(prev, valid_entry, next);
2414 else if (next != NULL)
2415 LIST_INSERT_BEFORE(next, valid_entry, next);
2416 else /* It's empty list, insert to head */
2417 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2420 pool->num_free += valid_entry->len;
2421 pool->num_alloc -= valid_entry->len;
2427 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2430 struct pool_entry *entry, *valid_entry;
2432 if (pool == NULL || num == 0) {
2433 PMD_DRV_LOG(ERR, "Invalid parameter");
2437 if (pool->num_free < num) {
2438 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2439 num, pool->num_free);
2444 /* Lookup in free list and find most fit one */
2445 LIST_FOREACH(entry, &pool->free_list, next) {
2446 if (entry->len >= num) {
2448 if (entry->len == num) {
2449 valid_entry = entry;
2452 if (valid_entry == NULL || valid_entry->len > entry->len)
2453 valid_entry = entry;
2457 /* Not find one to satisfy the request, return */
2458 if (valid_entry == NULL) {
2459 PMD_DRV_LOG(ERR, "No valid entry found");
2463 * The entry have equal queue number as requested,
2464 * remove it from alloc_list.
2466 if (valid_entry->len == num) {
2467 LIST_REMOVE(valid_entry, next);
2470 * The entry have more numbers than requested,
2471 * create a new entry for alloc_list and minus its
2472 * queue base and number in free_list.
2474 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2475 if (entry == NULL) {
2476 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2480 entry->base = valid_entry->base;
2482 valid_entry->base += num;
2483 valid_entry->len -= num;
2484 valid_entry = entry;
2487 /* Insert it into alloc list, not sorted */
2488 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2490 pool->num_free -= valid_entry->len;
2491 pool->num_alloc += valid_entry->len;
2493 return (valid_entry->base + pool->base);
2497 * bitmap_is_subset - Check whether src2 is subset of src1
2500 bitmap_is_subset(uint8_t src1, uint8_t src2)
2502 return !((src1 ^ src2) & src2);
2506 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2508 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2510 /* If DCB is not supported, only default TC is supported */
2511 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2512 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2516 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2517 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2518 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2522 return I40E_SUCCESS;
2526 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2527 struct i40e_vsi_vlan_pvid_info *info)
2530 struct i40e_vsi_context ctxt;
2531 uint8_t vlan_flags = 0;
2534 if (vsi == NULL || info == NULL) {
2535 PMD_DRV_LOG(ERR, "invalid parameters");
2536 return I40E_ERR_PARAM;
2540 vsi->info.pvid = info->config.pvid;
2542 * If insert pvid is enabled, only tagged pkts are
2543 * allowed to be sent out.
2545 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2546 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2549 if (info->config.reject.tagged == 0)
2550 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2552 if (info->config.reject.untagged == 0)
2553 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2555 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2556 I40E_AQ_VSI_PVLAN_MODE_MASK);
2557 vsi->info.port_vlan_flags |= vlan_flags;
2558 vsi->info.valid_sections =
2559 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2560 memset(&ctxt, 0, sizeof(ctxt));
2561 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2562 ctxt.seid = vsi->seid;
2564 hw = I40E_VSI_TO_HW(vsi);
2565 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2566 if (ret != I40E_SUCCESS)
2567 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2573 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2575 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2577 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2579 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2580 if (ret != I40E_SUCCESS)
2584 PMD_DRV_LOG(ERR, "seid not valid");
2588 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2589 tc_bw_data.tc_valid_bits = enabled_tcmap;
2590 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2591 tc_bw_data.tc_bw_credits[i] =
2592 (enabled_tcmap & (1 << i)) ? 1 : 0;
2594 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2595 if (ret != I40E_SUCCESS) {
2596 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2600 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2601 sizeof(vsi->info.qs_handle));
2602 return I40E_SUCCESS;
2606 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2607 struct i40e_aqc_vsi_properties_data *info,
2608 uint8_t enabled_tcmap)
2610 int ret, total_tc = 0, i;
2611 uint16_t qpnum_per_tc, bsf, qp_idx;
2613 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2614 if (ret != I40E_SUCCESS)
2617 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2618 if (enabled_tcmap & (1 << i))
2620 vsi->enabled_tc = enabled_tcmap;
2622 /* Number of queues per enabled TC */
2623 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2624 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2625 bsf = rte_bsf32(qpnum_per_tc);
2627 /* Adjust the queue number to actual queues that can be applied */
2628 vsi->nb_qps = qpnum_per_tc * total_tc;
2631 * Configure TC and queue mapping parameters, for enabled TC,
2632 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2633 * default queue will serve it.
2636 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2637 if (vsi->enabled_tc & (1 << i)) {
2638 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2639 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2640 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2641 qp_idx += qpnum_per_tc;
2643 info->tc_mapping[i] = 0;
2646 /* Associate queue number with VSI */
2647 if (vsi->type == I40E_VSI_SRIOV) {
2648 info->mapping_flags |=
2649 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2650 for (i = 0; i < vsi->nb_qps; i++)
2651 info->queue_mapping[i] =
2652 rte_cpu_to_le_16(vsi->base_queue + i);
2654 info->mapping_flags |=
2655 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2656 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2658 info->valid_sections |=
2659 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2661 return I40E_SUCCESS;
2665 i40e_veb_release(struct i40e_veb *veb)
2667 struct i40e_vsi *vsi;
2670 if (veb == NULL || veb->associate_vsi == NULL)
2673 if (!TAILQ_EMPTY(&veb->head)) {
2674 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2678 vsi = veb->associate_vsi;
2679 hw = I40E_VSI_TO_HW(vsi);
2681 vsi->uplink_seid = veb->uplink_seid;
2682 i40e_aq_delete_element(hw, veb->seid, NULL);
2685 return I40E_SUCCESS;
2689 static struct i40e_veb *
2690 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2692 struct i40e_veb *veb;
2696 if (NULL == pf || vsi == NULL) {
2697 PMD_DRV_LOG(ERR, "veb setup failed, "
2698 "associated VSI shouldn't null");
2701 hw = I40E_PF_TO_HW(pf);
2703 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2705 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2709 veb->associate_vsi = vsi;
2710 TAILQ_INIT(&veb->head);
2711 veb->uplink_seid = vsi->uplink_seid;
2713 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2714 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2716 if (ret != I40E_SUCCESS) {
2717 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2718 hw->aq.asq_last_status);
2722 /* get statistics index */
2723 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2724 &veb->stats_idx, NULL, NULL, NULL);
2725 if (ret != I40E_SUCCESS) {
2726 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2727 hw->aq.asq_last_status);
2731 /* Get VEB bandwidth, to be implemented */
2732 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2733 vsi->uplink_seid = veb->seid;
2742 i40e_vsi_release(struct i40e_vsi *vsi)
2746 struct i40e_vsi_list *vsi_list;
2748 struct i40e_mac_filter *f;
2751 return I40E_SUCCESS;
2753 pf = I40E_VSI_TO_PF(vsi);
2754 hw = I40E_VSI_TO_HW(vsi);
2756 /* VSI has child to attach, release child first */
2758 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2759 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2761 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2763 i40e_veb_release(vsi->veb);
2766 /* Remove all macvlan filters of the VSI */
2767 i40e_vsi_remove_all_macvlan_filter(vsi);
2768 TAILQ_FOREACH(f, &vsi->mac_list, next)
2771 if (vsi->type != I40E_VSI_MAIN) {
2772 /* Remove vsi from parent's sibling list */
2773 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2774 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2775 return I40E_ERR_PARAM;
2777 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2778 &vsi->sib_vsi_list, list);
2780 /* Remove all switch element of the VSI */
2781 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2782 if (ret != I40E_SUCCESS)
2783 PMD_DRV_LOG(ERR, "Failed to delete element");
2785 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2787 if (vsi->type != I40E_VSI_SRIOV)
2788 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2791 return I40E_SUCCESS;
2795 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2797 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2798 struct i40e_aqc_remove_macvlan_element_data def_filter;
2799 struct i40e_mac_filter_info filter;
2802 if (vsi->type != I40E_VSI_MAIN)
2803 return I40E_ERR_CONFIG;
2804 memset(&def_filter, 0, sizeof(def_filter));
2805 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2807 def_filter.vlan_tag = 0;
2808 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2809 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2810 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2811 if (ret != I40E_SUCCESS) {
2812 struct i40e_mac_filter *f;
2813 struct ether_addr *mac;
2815 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2817 /* It needs to add the permanent mac into mac list */
2818 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2820 PMD_DRV_LOG(ERR, "failed to allocate memory");
2821 return I40E_ERR_NO_MEMORY;
2823 mac = &f->mac_info.mac_addr;
2824 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2826 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2827 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2832 (void)rte_memcpy(&filter.mac_addr,
2833 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2834 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2835 return i40e_vsi_add_mac(vsi, &filter);
2839 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2841 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2842 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2843 struct i40e_hw *hw = &vsi->adapter->hw;
2847 memset(&bw_config, 0, sizeof(bw_config));
2848 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2849 if (ret != I40E_SUCCESS) {
2850 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2851 hw->aq.asq_last_status);
2855 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2856 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2857 &ets_sla_config, NULL);
2858 if (ret != I40E_SUCCESS) {
2859 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2860 "configuration %u", hw->aq.asq_last_status);
2864 /* Not store the info yet, just print out */
2865 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2866 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2867 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2868 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2869 ets_sla_config.share_credits[i]);
2870 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2871 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2872 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2873 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2882 i40e_vsi_setup(struct i40e_pf *pf,
2883 enum i40e_vsi_type type,
2884 struct i40e_vsi *uplink_vsi,
2885 uint16_t user_param)
2887 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2888 struct i40e_vsi *vsi;
2889 struct i40e_mac_filter_info filter;
2891 struct i40e_vsi_context ctxt;
2892 struct ether_addr broadcast =
2893 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2895 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2896 PMD_DRV_LOG(ERR, "VSI setup failed, "
2897 "VSI link shouldn't be NULL");
2901 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2902 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2903 "uplink VSI should be NULL");
2907 /* If uplink vsi didn't setup VEB, create one first */
2908 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2909 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2911 if (NULL == uplink_vsi->veb) {
2912 PMD_DRV_LOG(ERR, "VEB setup failed");
2917 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2919 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2922 TAILQ_INIT(&vsi->mac_list);
2924 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2925 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2926 vsi->parent_vsi = uplink_vsi;
2927 vsi->user_param = user_param;
2928 /* Allocate queues */
2929 switch (vsi->type) {
2930 case I40E_VSI_MAIN :
2931 vsi->nb_qps = pf->lan_nb_qps;
2933 case I40E_VSI_SRIOV :
2934 vsi->nb_qps = pf->vf_nb_qps;
2936 case I40E_VSI_VMDQ2:
2937 vsi->nb_qps = pf->vmdq_nb_qps;
2940 vsi->nb_qps = pf->fdir_nb_qps;
2946 * The filter status descriptor is reported in rx queue 0,
2947 * while the tx queue for fdir filter programming has no
2948 * such constraints, can be non-zero queues.
2949 * To simplify it, choose FDIR vsi use queue 0 pair.
2950 * To make sure it will use queue 0 pair, queue allocation
2951 * need be done before this function is called
2953 if (type != I40E_VSI_FDIR) {
2954 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2956 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2960 vsi->base_queue = ret;
2962 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2964 /* VF has MSIX interrupt in VF range, don't allocate here */
2965 if (type != I40E_VSI_SRIOV) {
2966 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2968 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2969 goto fail_queue_alloc;
2971 vsi->msix_intr = ret;
2975 if (type == I40E_VSI_MAIN) {
2976 /* For main VSI, no need to add since it's default one */
2977 vsi->uplink_seid = pf->mac_seid;
2978 vsi->seid = pf->main_vsi_seid;
2979 /* Bind queues with specific MSIX interrupt */
2981 * Needs 2 interrupt at least, one for misc cause which will
2982 * enabled from OS side, Another for queues binding the
2983 * interrupt from device side only.
2986 /* Get default VSI parameters from hardware */
2987 memset(&ctxt, 0, sizeof(ctxt));
2988 ctxt.seid = vsi->seid;
2989 ctxt.pf_num = hw->pf_id;
2990 ctxt.uplink_seid = vsi->uplink_seid;
2992 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2993 if (ret != I40E_SUCCESS) {
2994 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2995 goto fail_msix_alloc;
2997 (void)rte_memcpy(&vsi->info, &ctxt.info,
2998 sizeof(struct i40e_aqc_vsi_properties_data));
2999 vsi->vsi_id = ctxt.vsi_number;
3000 vsi->info.valid_sections = 0;
3002 /* Configure tc, enabled TC0 only */
3003 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3005 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3006 goto fail_msix_alloc;
3009 /* TC, queue mapping */
3010 memset(&ctxt, 0, sizeof(ctxt));
3011 vsi->info.valid_sections |=
3012 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3013 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3014 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3015 (void)rte_memcpy(&ctxt.info, &vsi->info,
3016 sizeof(struct i40e_aqc_vsi_properties_data));
3017 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3018 I40E_DEFAULT_TCMAP);
3019 if (ret != I40E_SUCCESS) {
3020 PMD_DRV_LOG(ERR, "Failed to configure "
3021 "TC queue mapping");
3022 goto fail_msix_alloc;
3024 ctxt.seid = vsi->seid;
3025 ctxt.pf_num = hw->pf_id;
3026 ctxt.uplink_seid = vsi->uplink_seid;
3029 /* Update VSI parameters */
3030 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3031 if (ret != I40E_SUCCESS) {
3032 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3033 goto fail_msix_alloc;
3036 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3037 sizeof(vsi->info.tc_mapping));
3038 (void)rte_memcpy(&vsi->info.queue_mapping,
3039 &ctxt.info.queue_mapping,
3040 sizeof(vsi->info.queue_mapping));
3041 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3042 vsi->info.valid_sections = 0;
3044 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3048 * Updating default filter settings are necessary to prevent
3049 * reception of tagged packets.
3050 * Some old firmware configurations load a default macvlan
3051 * filter which accepts both tagged and untagged packets.
3052 * The updating is to use a normal filter instead if needed.
3053 * For NVM 4.2.2 or after, the updating is not needed anymore.
3054 * The firmware with correct configurations load the default
3055 * macvlan filter which is expected and cannot be removed.
3057 i40e_update_default_filter_setting(vsi);
3058 } else if (type == I40E_VSI_SRIOV) {
3059 memset(&ctxt, 0, sizeof(ctxt));
3061 * For other VSI, the uplink_seid equals to uplink VSI's
3062 * uplink_seid since they share same VEB
3064 vsi->uplink_seid = uplink_vsi->uplink_seid;
3065 ctxt.pf_num = hw->pf_id;
3066 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3067 ctxt.uplink_seid = vsi->uplink_seid;
3068 ctxt.connection_type = 0x1;
3069 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3072 * Do not configure switch ID to enable VEB switch by
3073 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3074 * if the source mac address of packet sent from VF is not
3075 * listed in the VEB's mac table, the VEB will switch the
3076 * packet back to the VF. Need to enable it when HW issue
3080 /* Configure port/vlan */
3081 ctxt.info.valid_sections |=
3082 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3083 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3084 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3085 I40E_DEFAULT_TCMAP);
3086 if (ret != I40E_SUCCESS) {
3087 PMD_DRV_LOG(ERR, "Failed to configure "
3088 "TC queue mapping");
3089 goto fail_msix_alloc;
3091 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3092 ctxt.info.valid_sections |=
3093 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3095 * Since VSI is not created yet, only configure parameter,
3096 * will add vsi below.
3098 } else if (type == I40E_VSI_VMDQ2) {
3099 memset(&ctxt, 0, sizeof(ctxt));
3101 * For other VSI, the uplink_seid equals to uplink VSI's
3102 * uplink_seid since they share same VEB
3104 vsi->uplink_seid = uplink_vsi->uplink_seid;
3105 ctxt.pf_num = hw->pf_id;
3107 ctxt.uplink_seid = vsi->uplink_seid;
3108 ctxt.connection_type = 0x1;
3109 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3111 ctxt.info.valid_sections |=
3112 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3113 /* user_param carries flag to enable loop back */
3115 ctxt.info.switch_id =
3116 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3117 ctxt.info.switch_id |=
3118 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3121 /* Configure port/vlan */
3122 ctxt.info.valid_sections |=
3123 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3124 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3125 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3126 I40E_DEFAULT_TCMAP);
3127 if (ret != I40E_SUCCESS) {
3128 PMD_DRV_LOG(ERR, "Failed to configure "
3129 "TC queue mapping");
3130 goto fail_msix_alloc;
3132 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3133 ctxt.info.valid_sections |=
3134 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3135 } else if (type == I40E_VSI_FDIR) {
3136 memset(&ctxt, 0, sizeof(ctxt));
3137 vsi->uplink_seid = uplink_vsi->uplink_seid;
3138 ctxt.pf_num = hw->pf_id;
3140 ctxt.uplink_seid = vsi->uplink_seid;
3141 ctxt.connection_type = 0x1; /* regular data port */
3142 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3143 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3144 I40E_DEFAULT_TCMAP);
3145 if (ret != I40E_SUCCESS) {
3146 PMD_DRV_LOG(ERR, "Failed to configure "
3147 "TC queue mapping.");
3148 goto fail_msix_alloc;
3150 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3151 ctxt.info.valid_sections |=
3152 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3154 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3155 goto fail_msix_alloc;
3158 if (vsi->type != I40E_VSI_MAIN) {
3159 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3160 if (ret != I40E_SUCCESS) {
3161 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3162 hw->aq.asq_last_status);
3163 goto fail_msix_alloc;
3165 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3166 vsi->info.valid_sections = 0;
3167 vsi->seid = ctxt.seid;
3168 vsi->vsi_id = ctxt.vsi_number;
3169 vsi->sib_vsi_list.vsi = vsi;
3170 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3171 &vsi->sib_vsi_list, list);
3174 /* MAC/VLAN configuration */
3175 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3176 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3178 ret = i40e_vsi_add_mac(vsi, &filter);
3179 if (ret != I40E_SUCCESS) {
3180 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3181 goto fail_msix_alloc;
3184 /* Get VSI BW information */
3185 i40e_vsi_dump_bw_config(vsi);
3188 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3190 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3196 /* Configure vlan stripping on or off */
3198 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3200 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3201 struct i40e_vsi_context ctxt;
3203 int ret = I40E_SUCCESS;
3205 /* Check if it has been already on or off */
3206 if (vsi->info.valid_sections &
3207 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3209 if ((vsi->info.port_vlan_flags &
3210 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3211 return 0; /* already on */
3213 if ((vsi->info.port_vlan_flags &
3214 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3215 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3216 return 0; /* already off */
3221 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3223 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3224 vsi->info.valid_sections =
3225 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3226 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3227 vsi->info.port_vlan_flags |= vlan_flags;
3228 ctxt.seid = vsi->seid;
3229 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3230 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3232 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3233 on ? "enable" : "disable");
3239 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3241 struct rte_eth_dev_data *data = dev->data;
3244 /* Apply vlan offload setting */
3245 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3247 /* Apply double-vlan setting, not implemented yet */
3249 /* Apply pvid setting */
3250 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3251 data->dev_conf.txmode.hw_vlan_insert_pvid);
3253 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3259 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3261 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3263 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3267 i40e_update_flow_control(struct i40e_hw *hw)
3269 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3270 struct i40e_link_status link_status;
3271 uint32_t rxfc = 0, txfc = 0, reg;
3275 memset(&link_status, 0, sizeof(link_status));
3276 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3277 if (ret != I40E_SUCCESS) {
3278 PMD_DRV_LOG(ERR, "Failed to get link status information");
3279 goto write_reg; /* Disable flow control */
3282 an_info = hw->phy.link_info.an_info;
3283 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3284 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3285 ret = I40E_ERR_NOT_READY;
3286 goto write_reg; /* Disable flow control */
3289 * If link auto negotiation is enabled, flow control needs to
3290 * be configured according to it
3292 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3293 case I40E_LINK_PAUSE_RXTX:
3296 hw->fc.current_mode = I40E_FC_FULL;
3298 case I40E_AQ_LINK_PAUSE_RX:
3300 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3302 case I40E_AQ_LINK_PAUSE_TX:
3304 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3307 hw->fc.current_mode = I40E_FC_NONE;
3312 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3313 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3314 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3315 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3316 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3317 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3324 i40e_pf_setup(struct i40e_pf *pf)
3326 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3327 struct i40e_filter_control_settings settings;
3328 struct i40e_vsi *vsi;
3331 /* Clear all stats counters */
3332 pf->offset_loaded = FALSE;
3333 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3334 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3336 ret = i40e_pf_get_switch_config(pf);
3337 if (ret != I40E_SUCCESS) {
3338 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3341 if (pf->flags & I40E_FLAG_FDIR) {
3342 /* make queue allocated first, let FDIR use queue pair 0*/
3343 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3344 if (ret != I40E_FDIR_QUEUE_ID) {
3345 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3347 pf->flags &= ~I40E_FLAG_FDIR;
3350 /* main VSI setup */
3351 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3353 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3354 return I40E_ERR_NOT_READY;
3358 /* Configure filter control */
3359 memset(&settings, 0, sizeof(settings));
3360 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3361 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3362 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3363 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3365 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3366 hw->func_caps.rss_table_size);
3367 return I40E_ERR_PARAM;
3369 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3370 "size: %u\n", hw->func_caps.rss_table_size);
3371 pf->hash_lut_size = hw->func_caps.rss_table_size;
3373 /* Enable ethtype and macvlan filters */
3374 settings.enable_ethtype = TRUE;
3375 settings.enable_macvlan = TRUE;
3376 ret = i40e_set_filter_control(hw, &settings);
3378 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3381 /* Update flow control according to the auto negotiation */
3382 i40e_update_flow_control(hw);
3384 return I40E_SUCCESS;
3388 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3394 * Set or clear TX Queue Disable flags,
3395 * which is required by hardware.
3397 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3398 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3400 /* Wait until the request is finished */
3401 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3402 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3403 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3404 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3405 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3411 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3412 return I40E_SUCCESS; /* already on, skip next steps */
3414 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3415 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3417 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3418 return I40E_SUCCESS; /* already off, skip next steps */
3419 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3421 /* Write the register */
3422 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3423 /* Check the result */
3424 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3425 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3426 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3428 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3429 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3432 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3433 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3437 /* Check if it is timeout */
3438 if (j >= I40E_CHK_Q_ENA_COUNT) {
3439 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3440 (on ? "enable" : "disable"), q_idx);
3441 return I40E_ERR_TIMEOUT;
3444 return I40E_SUCCESS;
3447 /* Swith on or off the tx queues */
3449 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3451 struct rte_eth_dev_data *dev_data = pf->dev_data;
3452 struct i40e_tx_queue *txq;
3453 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3457 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3458 txq = dev_data->tx_queues[i];
3459 /* Don't operate the queue if not configured or
3460 * if starting only per queue */
3461 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3464 ret = i40e_dev_tx_queue_start(dev, i);
3466 ret = i40e_dev_tx_queue_stop(dev, i);
3467 if ( ret != I40E_SUCCESS)
3471 return I40E_SUCCESS;
3475 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3480 /* Wait until the request is finished */
3481 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3482 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3483 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3484 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3485 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3490 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3491 return I40E_SUCCESS; /* Already on, skip next steps */
3492 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3494 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3495 return I40E_SUCCESS; /* Already off, skip next steps */
3496 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3499 /* Write the register */
3500 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3501 /* Check the result */
3502 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3503 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3504 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3506 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3507 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3510 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3511 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3516 /* Check if it is timeout */
3517 if (j >= I40E_CHK_Q_ENA_COUNT) {
3518 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3519 (on ? "enable" : "disable"), q_idx);
3520 return I40E_ERR_TIMEOUT;
3523 return I40E_SUCCESS;
3525 /* Switch on or off the rx queues */
3527 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3529 struct rte_eth_dev_data *dev_data = pf->dev_data;
3530 struct i40e_rx_queue *rxq;
3531 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3535 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3536 rxq = dev_data->rx_queues[i];
3537 /* Don't operate the queue if not configured or
3538 * if starting only per queue */
3539 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3542 ret = i40e_dev_rx_queue_start(dev, i);
3544 ret = i40e_dev_rx_queue_stop(dev, i);
3545 if (ret != I40E_SUCCESS)
3549 return I40E_SUCCESS;
3552 /* Switch on or off all the rx/tx queues */
3554 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3559 /* enable rx queues before enabling tx queues */
3560 ret = i40e_dev_switch_rx_queues(pf, on);
3562 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3565 ret = i40e_dev_switch_tx_queues(pf, on);
3567 /* Stop tx queues before stopping rx queues */
3568 ret = i40e_dev_switch_tx_queues(pf, on);
3570 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3573 ret = i40e_dev_switch_rx_queues(pf, on);
3579 /* Initialize VSI for TX */
3581 i40e_dev_tx_init(struct i40e_pf *pf)
3583 struct rte_eth_dev_data *data = pf->dev_data;
3585 uint32_t ret = I40E_SUCCESS;
3586 struct i40e_tx_queue *txq;
3588 for (i = 0; i < data->nb_tx_queues; i++) {
3589 txq = data->tx_queues[i];
3590 if (!txq || !txq->q_set)
3592 ret = i40e_tx_queue_init(txq);
3593 if (ret != I40E_SUCCESS)
3600 /* Initialize VSI for RX */
3602 i40e_dev_rx_init(struct i40e_pf *pf)
3604 struct rte_eth_dev_data *data = pf->dev_data;
3605 int ret = I40E_SUCCESS;
3607 struct i40e_rx_queue *rxq;
3609 i40e_pf_config_mq_rx(pf);
3610 for (i = 0; i < data->nb_rx_queues; i++) {
3611 rxq = data->rx_queues[i];
3612 if (!rxq || !rxq->q_set)
3615 ret = i40e_rx_queue_init(rxq);
3616 if (ret != I40E_SUCCESS) {
3617 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3627 i40e_dev_rxtx_init(struct i40e_pf *pf)
3631 err = i40e_dev_tx_init(pf);
3633 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3636 err = i40e_dev_rx_init(pf);
3638 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3646 i40e_vmdq_setup(struct rte_eth_dev *dev)
3648 struct rte_eth_conf *conf = &dev->data->dev_conf;
3649 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3650 int i, err, conf_vsis, j, loop;
3651 struct i40e_vsi *vsi;
3652 struct i40e_vmdq_info *vmdq_info;
3653 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3654 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3657 * Disable interrupt to avoid message from VF. Furthermore, it will
3658 * avoid race condition in VSI creation/destroy.
3660 i40e_pf_disable_irq0(hw);
3662 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3663 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3667 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3668 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3669 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3670 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3671 pf->max_nb_vmdq_vsi);
3675 if (pf->vmdq != NULL) {
3676 PMD_INIT_LOG(INFO, "VMDQ already configured");
3680 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3681 sizeof(*vmdq_info) * conf_vsis, 0);
3683 if (pf->vmdq == NULL) {
3684 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3688 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3690 /* Create VMDQ VSI */
3691 for (i = 0; i < conf_vsis; i++) {
3692 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3693 vmdq_conf->enable_loop_back);
3695 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3699 vmdq_info = &pf->vmdq[i];
3701 vmdq_info->vsi = vsi;
3703 pf->nb_cfg_vmdq_vsi = conf_vsis;
3705 /* Configure Vlan */
3706 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3707 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3708 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3709 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3710 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3711 vmdq_conf->pool_map[i].vlan_id, j);
3713 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3714 vmdq_conf->pool_map[i].vlan_id);
3716 PMD_INIT_LOG(ERR, "Failed to add vlan");
3724 i40e_pf_enable_irq0(hw);
3729 for (i = 0; i < conf_vsis; i++)
3730 if (pf->vmdq[i].vsi == NULL)
3733 i40e_vsi_release(pf->vmdq[i].vsi);
3737 i40e_pf_enable_irq0(hw);
3742 i40e_stat_update_32(struct i40e_hw *hw,
3750 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3754 if (new_data >= *offset)
3755 *stat = (uint64_t)(new_data - *offset);
3757 *stat = (uint64_t)((new_data +
3758 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3762 i40e_stat_update_48(struct i40e_hw *hw,
3771 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3772 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3773 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3778 if (new_data >= *offset)
3779 *stat = new_data - *offset;
3781 *stat = (uint64_t)((new_data +
3782 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3784 *stat &= I40E_48_BIT_MASK;
3789 i40e_pf_disable_irq0(struct i40e_hw *hw)
3791 /* Disable all interrupt types */
3792 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3793 I40E_WRITE_FLUSH(hw);
3798 i40e_pf_enable_irq0(struct i40e_hw *hw)
3800 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3801 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3802 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3803 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3804 I40E_WRITE_FLUSH(hw);
3808 i40e_pf_config_irq0(struct i40e_hw *hw)
3810 /* read pending request and disable first */
3811 i40e_pf_disable_irq0(hw);
3812 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3813 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3814 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3816 /* Link no queues with irq0 */
3817 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3818 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3822 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3828 uint32_t index, offset, val;
3833 * Try to find which VF trigger a reset, use absolute VF id to access
3834 * since the reg is global register.
3836 for (i = 0; i < pf->vf_num; i++) {
3837 abs_vf_id = hw->func_caps.vf_base_id + i;
3838 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3839 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3840 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3841 /* VFR event occured */
3842 if (val & (0x1 << offset)) {
3845 /* Clear the event first */
3846 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3848 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3850 * Only notify a VF reset event occured,
3851 * don't trigger another SW reset
3853 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3854 if (ret != I40E_SUCCESS)
3855 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3861 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3863 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3864 struct i40e_arq_event_info info;
3865 uint16_t pending, opcode;
3868 info.buf_len = I40E_AQ_BUF_SZ;
3869 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3870 if (!info.msg_buf) {
3871 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3877 ret = i40e_clean_arq_element(hw, &info, &pending);
3879 if (ret != I40E_SUCCESS) {
3880 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3881 "aq_err: %u", hw->aq.asq_last_status);
3884 opcode = rte_le_to_cpu_16(info.desc.opcode);
3887 case i40e_aqc_opc_send_msg_to_pf:
3888 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3889 i40e_pf_host_handle_vf_msg(dev,
3890 rte_le_to_cpu_16(info.desc.retval),
3891 rte_le_to_cpu_32(info.desc.cookie_high),
3892 rte_le_to_cpu_32(info.desc.cookie_low),
3897 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3902 rte_free(info.msg_buf);
3906 * Interrupt handler is registered as the alarm callback for handling LSC
3907 * interrupt in a definite of time, in order to wait the NIC into a stable
3908 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3909 * no need for link down interrupt.
3912 i40e_dev_interrupt_delayed_handler(void *param)
3914 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3918 /* read interrupt causes again */
3919 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3921 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3922 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3923 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3924 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3925 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3926 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3927 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3928 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3929 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3930 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3931 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3933 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3934 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3935 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3936 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3937 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3939 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3940 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3941 i40e_dev_handle_vfr_event(dev);
3943 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3944 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3945 i40e_dev_handle_aq_msg(dev);
3948 /* handle the link up interrupt in an alarm callback */
3949 i40e_dev_link_update(dev, 0);
3950 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3952 i40e_pf_enable_irq0(hw);
3953 rte_intr_enable(&(dev->pci_dev->intr_handle));
3957 * Interrupt handler triggered by NIC for handling
3958 * specific interrupt.
3961 * Pointer to interrupt handle.
3963 * The address of parameter (struct rte_eth_dev *) regsitered before.
3969 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3972 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3973 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3976 /* Disable interrupt */
3977 i40e_pf_disable_irq0(hw);
3979 /* read out interrupt causes */
3980 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3982 /* No interrupt event indicated */
3983 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3984 PMD_DRV_LOG(INFO, "No interrupt event");
3987 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3988 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3989 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3990 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3991 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3992 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3993 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3994 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3995 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3996 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3997 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3998 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3999 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4000 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4001 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4002 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4004 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4005 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4006 i40e_dev_handle_vfr_event(dev);
4008 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4009 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4010 i40e_dev_handle_aq_msg(dev);
4013 /* Link Status Change interrupt */
4014 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4015 #define I40E_US_PER_SECOND 1000000
4016 struct rte_eth_link link;
4018 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4019 memset(&link, 0, sizeof(link));
4020 rte_i40e_dev_atomic_read_link_status(dev, &link);
4021 i40e_dev_link_update(dev, 0);
4024 * For link up interrupt, it needs to wait 1 second to let the
4025 * hardware be a stable state. Otherwise several consecutive
4026 * interrupts can be observed.
4027 * For link down interrupt, no need to wait.
4029 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4030 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4033 _rte_eth_dev_callback_process(dev,
4034 RTE_ETH_EVENT_INTR_LSC);
4038 /* Enable interrupt */
4039 i40e_pf_enable_irq0(hw);
4040 rte_intr_enable(&(dev->pci_dev->intr_handle));
4044 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4045 struct i40e_macvlan_filter *filter,
4048 int ele_num, ele_buff_size;
4049 int num, actual_num, i;
4051 int ret = I40E_SUCCESS;
4052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4053 struct i40e_aqc_add_macvlan_element_data *req_list;
4055 if (filter == NULL || total == 0)
4056 return I40E_ERR_PARAM;
4057 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4058 ele_buff_size = hw->aq.asq_buf_size;
4060 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4061 if (req_list == NULL) {
4062 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4063 return I40E_ERR_NO_MEMORY;
4068 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4069 memset(req_list, 0, ele_buff_size);
4071 for (i = 0; i < actual_num; i++) {
4072 (void)rte_memcpy(req_list[i].mac_addr,
4073 &filter[num + i].macaddr, ETH_ADDR_LEN);
4074 req_list[i].vlan_tag =
4075 rte_cpu_to_le_16(filter[num + i].vlan_id);
4077 switch (filter[num + i].filter_type) {
4078 case RTE_MAC_PERFECT_MATCH:
4079 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4080 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4082 case RTE_MACVLAN_PERFECT_MATCH:
4083 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4085 case RTE_MAC_HASH_MATCH:
4086 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4087 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4089 case RTE_MACVLAN_HASH_MATCH:
4090 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4093 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4094 ret = I40E_ERR_PARAM;
4098 req_list[i].queue_number = 0;
4100 req_list[i].flags = rte_cpu_to_le_16(flags);
4103 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4105 if (ret != I40E_SUCCESS) {
4106 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4110 } while (num < total);
4118 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4119 struct i40e_macvlan_filter *filter,
4122 int ele_num, ele_buff_size;
4123 int num, actual_num, i;
4125 int ret = I40E_SUCCESS;
4126 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4127 struct i40e_aqc_remove_macvlan_element_data *req_list;
4129 if (filter == NULL || total == 0)
4130 return I40E_ERR_PARAM;
4132 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4133 ele_buff_size = hw->aq.asq_buf_size;
4135 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4136 if (req_list == NULL) {
4137 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4138 return I40E_ERR_NO_MEMORY;
4143 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4144 memset(req_list, 0, ele_buff_size);
4146 for (i = 0; i < actual_num; i++) {
4147 (void)rte_memcpy(req_list[i].mac_addr,
4148 &filter[num + i].macaddr, ETH_ADDR_LEN);
4149 req_list[i].vlan_tag =
4150 rte_cpu_to_le_16(filter[num + i].vlan_id);
4152 switch (filter[num + i].filter_type) {
4153 case RTE_MAC_PERFECT_MATCH:
4154 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4155 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4157 case RTE_MACVLAN_PERFECT_MATCH:
4158 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4160 case RTE_MAC_HASH_MATCH:
4161 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4162 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4164 case RTE_MACVLAN_HASH_MATCH:
4165 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4168 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4169 ret = I40E_ERR_PARAM;
4172 req_list[i].flags = rte_cpu_to_le_16(flags);
4175 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4177 if (ret != I40E_SUCCESS) {
4178 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4182 } while (num < total);
4189 /* Find out specific MAC filter */
4190 static struct i40e_mac_filter *
4191 i40e_find_mac_filter(struct i40e_vsi *vsi,
4192 struct ether_addr *macaddr)
4194 struct i40e_mac_filter *f;
4196 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4197 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4205 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4208 uint32_t vid_idx, vid_bit;
4210 if (vlan_id > ETH_VLAN_ID_MAX)
4213 vid_idx = I40E_VFTA_IDX(vlan_id);
4214 vid_bit = I40E_VFTA_BIT(vlan_id);
4216 if (vsi->vfta[vid_idx] & vid_bit)
4223 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4224 uint16_t vlan_id, bool on)
4226 uint32_t vid_idx, vid_bit;
4228 if (vlan_id > ETH_VLAN_ID_MAX)
4231 vid_idx = I40E_VFTA_IDX(vlan_id);
4232 vid_bit = I40E_VFTA_BIT(vlan_id);
4235 vsi->vfta[vid_idx] |= vid_bit;
4237 vsi->vfta[vid_idx] &= ~vid_bit;
4241 * Find all vlan options for specific mac addr,
4242 * return with actual vlan found.
4245 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4246 struct i40e_macvlan_filter *mv_f,
4247 int num, struct ether_addr *addr)
4253 * Not to use i40e_find_vlan_filter to decrease the loop time,
4254 * although the code looks complex.
4256 if (num < vsi->vlan_num)
4257 return I40E_ERR_PARAM;
4260 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4262 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4263 if (vsi->vfta[j] & (1 << k)) {
4265 PMD_DRV_LOG(ERR, "vlan number "
4267 return I40E_ERR_PARAM;
4269 (void)rte_memcpy(&mv_f[i].macaddr,
4270 addr, ETH_ADDR_LEN);
4272 j * I40E_UINT32_BIT_SIZE + k;
4278 return I40E_SUCCESS;
4282 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4283 struct i40e_macvlan_filter *mv_f,
4288 struct i40e_mac_filter *f;
4290 if (num < vsi->mac_num)
4291 return I40E_ERR_PARAM;
4293 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4295 PMD_DRV_LOG(ERR, "buffer number not match");
4296 return I40E_ERR_PARAM;
4298 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4300 mv_f[i].vlan_id = vlan;
4301 mv_f[i].filter_type = f->mac_info.filter_type;
4305 return I40E_SUCCESS;
4309 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4312 struct i40e_mac_filter *f;
4313 struct i40e_macvlan_filter *mv_f;
4314 int ret = I40E_SUCCESS;
4316 if (vsi == NULL || vsi->mac_num == 0)
4317 return I40E_ERR_PARAM;
4319 /* Case that no vlan is set */
4320 if (vsi->vlan_num == 0)
4323 num = vsi->mac_num * vsi->vlan_num;
4325 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4327 PMD_DRV_LOG(ERR, "failed to allocate memory");
4328 return I40E_ERR_NO_MEMORY;
4332 if (vsi->vlan_num == 0) {
4333 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4334 (void)rte_memcpy(&mv_f[i].macaddr,
4335 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4336 mv_f[i].vlan_id = 0;
4340 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4341 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4342 vsi->vlan_num, &f->mac_info.mac_addr);
4343 if (ret != I40E_SUCCESS)
4349 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4357 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4359 struct i40e_macvlan_filter *mv_f;
4361 int ret = I40E_SUCCESS;
4363 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4364 return I40E_ERR_PARAM;
4366 /* If it's already set, just return */
4367 if (i40e_find_vlan_filter(vsi,vlan))
4368 return I40E_SUCCESS;
4370 mac_num = vsi->mac_num;
4373 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4374 return I40E_ERR_PARAM;
4377 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4380 PMD_DRV_LOG(ERR, "failed to allocate memory");
4381 return I40E_ERR_NO_MEMORY;
4384 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4386 if (ret != I40E_SUCCESS)
4389 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4391 if (ret != I40E_SUCCESS)
4394 i40e_set_vlan_filter(vsi, vlan, 1);
4404 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4406 struct i40e_macvlan_filter *mv_f;
4408 int ret = I40E_SUCCESS;
4411 * Vlan 0 is the generic filter for untagged packets
4412 * and can't be removed.
4414 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4415 return I40E_ERR_PARAM;
4417 /* If can't find it, just return */
4418 if (!i40e_find_vlan_filter(vsi, vlan))
4419 return I40E_ERR_PARAM;
4421 mac_num = vsi->mac_num;
4424 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4425 return I40E_ERR_PARAM;
4428 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4431 PMD_DRV_LOG(ERR, "failed to allocate memory");
4432 return I40E_ERR_NO_MEMORY;
4435 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4437 if (ret != I40E_SUCCESS)
4440 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4442 if (ret != I40E_SUCCESS)
4445 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4446 if (vsi->vlan_num == 1) {
4447 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4448 if (ret != I40E_SUCCESS)
4451 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4452 if (ret != I40E_SUCCESS)
4456 i40e_set_vlan_filter(vsi, vlan, 0);
4466 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4468 struct i40e_mac_filter *f;
4469 struct i40e_macvlan_filter *mv_f;
4470 int i, vlan_num = 0;
4471 int ret = I40E_SUCCESS;
4473 /* If it's add and we've config it, return */
4474 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4476 return I40E_SUCCESS;
4477 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4478 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4481 * If vlan_num is 0, that's the first time to add mac,
4482 * set mask for vlan_id 0.
4484 if (vsi->vlan_num == 0) {
4485 i40e_set_vlan_filter(vsi, 0, 1);
4488 vlan_num = vsi->vlan_num;
4489 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4490 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4493 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4495 PMD_DRV_LOG(ERR, "failed to allocate memory");
4496 return I40E_ERR_NO_MEMORY;
4499 for (i = 0; i < vlan_num; i++) {
4500 mv_f[i].filter_type = mac_filter->filter_type;
4501 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4505 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4506 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4507 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4508 &mac_filter->mac_addr);
4509 if (ret != I40E_SUCCESS)
4513 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4514 if (ret != I40E_SUCCESS)
4517 /* Add the mac addr into mac list */
4518 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4520 PMD_DRV_LOG(ERR, "failed to allocate memory");
4521 ret = I40E_ERR_NO_MEMORY;
4524 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4526 f->mac_info.filter_type = mac_filter->filter_type;
4527 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4538 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4540 struct i40e_mac_filter *f;
4541 struct i40e_macvlan_filter *mv_f;
4543 enum rte_mac_filter_type filter_type;
4544 int ret = I40E_SUCCESS;
4546 /* Can't find it, return an error */
4547 f = i40e_find_mac_filter(vsi, addr);
4549 return I40E_ERR_PARAM;
4551 vlan_num = vsi->vlan_num;
4552 filter_type = f->mac_info.filter_type;
4553 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4554 filter_type == RTE_MACVLAN_HASH_MATCH) {
4555 if (vlan_num == 0) {
4556 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4557 return I40E_ERR_PARAM;
4559 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4560 filter_type == RTE_MAC_HASH_MATCH)
4563 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4565 PMD_DRV_LOG(ERR, "failed to allocate memory");
4566 return I40E_ERR_NO_MEMORY;
4569 for (i = 0; i < vlan_num; i++) {
4570 mv_f[i].filter_type = filter_type;
4571 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4574 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4575 filter_type == RTE_MACVLAN_HASH_MATCH) {
4576 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4577 if (ret != I40E_SUCCESS)
4581 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4582 if (ret != I40E_SUCCESS)
4585 /* Remove the mac addr into mac list */
4586 TAILQ_REMOVE(&vsi->mac_list, f, next);
4596 /* Configure hash enable flags for RSS */
4598 i40e_config_hena(uint64_t flags)
4605 if (flags & ETH_RSS_FRAG_IPV4)
4606 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4607 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4608 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4609 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4610 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4611 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4612 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4613 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4614 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4615 if (flags & ETH_RSS_FRAG_IPV6)
4616 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4617 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4618 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4619 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4620 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4621 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4622 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4623 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4624 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4625 if (flags & ETH_RSS_L2_PAYLOAD)
4626 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4631 /* Parse the hash enable flags */
4633 i40e_parse_hena(uint64_t flags)
4635 uint64_t rss_hf = 0;
4639 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4640 rss_hf |= ETH_RSS_FRAG_IPV4;
4641 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4642 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4643 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4644 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4645 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4646 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4647 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4648 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4649 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4650 rss_hf |= ETH_RSS_FRAG_IPV6;
4651 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4652 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4653 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4654 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4655 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4656 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4657 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4658 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4659 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4660 rss_hf |= ETH_RSS_L2_PAYLOAD;
4667 i40e_pf_disable_rss(struct i40e_pf *pf)
4669 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4672 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4673 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4674 hena &= ~I40E_RSS_HENA_ALL;
4675 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4676 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4677 I40E_WRITE_FLUSH(hw);
4681 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4684 uint8_t hash_key_len;
4689 hash_key = (uint32_t *)(rss_conf->rss_key);
4690 hash_key_len = rss_conf->rss_key_len;
4691 if (hash_key != NULL && hash_key_len >=
4692 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4693 /* Fill in RSS hash key */
4694 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4695 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4698 rss_hf = rss_conf->rss_hf;
4699 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4700 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4701 hena &= ~I40E_RSS_HENA_ALL;
4702 hena |= i40e_config_hena(rss_hf);
4703 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4704 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4705 I40E_WRITE_FLUSH(hw);
4711 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4712 struct rte_eth_rss_conf *rss_conf)
4714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4715 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4718 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4719 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4720 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4721 if (rss_hf != 0) /* Enable RSS */
4723 return 0; /* Nothing to do */
4726 if (rss_hf == 0) /* Disable RSS */
4729 return i40e_hw_rss_hash_set(hw, rss_conf);
4733 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4734 struct rte_eth_rss_conf *rss_conf)
4736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4737 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4741 if (hash_key != NULL) {
4742 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4743 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4744 rss_conf->rss_key_len = i * sizeof(uint32_t);
4746 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4747 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4748 rss_conf->rss_hf = i40e_parse_hena(hena);
4754 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4756 switch (filter_type) {
4757 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4758 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4760 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4761 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4763 case RTE_TUNNEL_FILTER_IMAC_TENID:
4764 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4766 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4767 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4769 case ETH_TUNNEL_FILTER_IMAC:
4770 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4773 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4781 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4782 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4786 uint8_t tun_type = 0;
4788 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4789 struct i40e_vsi *vsi = pf->main_vsi;
4790 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4791 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4793 cld_filter = rte_zmalloc("tunnel_filter",
4794 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4797 if (NULL == cld_filter) {
4798 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4801 pfilter = cld_filter;
4803 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4804 sizeof(struct ether_addr));
4805 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4806 sizeof(struct ether_addr));
4808 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4809 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4810 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4811 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4812 &tunnel_filter->ip_addr,
4813 sizeof(pfilter->ipaddr.v4.data));
4815 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4816 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4817 &tunnel_filter->ip_addr,
4818 sizeof(pfilter->ipaddr.v6.data));
4821 /* check tunneled type */
4822 switch (tunnel_filter->tunnel_type) {
4823 case RTE_TUNNEL_TYPE_VXLAN:
4824 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4826 case RTE_TUNNEL_TYPE_NVGRE:
4827 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4830 /* Other tunnel types is not supported. */
4831 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4832 rte_free(cld_filter);
4836 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4839 rte_free(cld_filter);
4843 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4844 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4845 pfilter->tenant_id = tunnel_filter->tenant_id;
4846 pfilter->queue_number = tunnel_filter->queue_id;
4849 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4851 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4854 rte_free(cld_filter);
4859 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4863 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4864 if (pf->vxlan_ports[i] == port)
4872 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4876 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4878 idx = i40e_get_vxlan_port_idx(pf, port);
4880 /* Check if port already exists */
4882 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4886 /* Now check if there is space to add the new port */
4887 idx = i40e_get_vxlan_port_idx(pf, 0);
4889 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4890 "not adding port %d", port);
4894 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4897 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4901 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4904 /* New port: add it and mark its index in the bitmap */
4905 pf->vxlan_ports[idx] = port;
4906 pf->vxlan_bitmap |= (1 << idx);
4908 if (!(pf->flags & I40E_FLAG_VXLAN))
4909 pf->flags |= I40E_FLAG_VXLAN;
4915 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4918 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4920 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4921 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4925 idx = i40e_get_vxlan_port_idx(pf, port);
4928 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4932 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4933 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4937 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4940 pf->vxlan_ports[idx] = 0;
4941 pf->vxlan_bitmap &= ~(1 << idx);
4943 if (!pf->vxlan_bitmap)
4944 pf->flags &= ~I40E_FLAG_VXLAN;
4949 /* Add UDP tunneling port */
4951 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4952 struct rte_eth_udp_tunnel *udp_tunnel)
4955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4957 if (udp_tunnel == NULL)
4960 switch (udp_tunnel->prot_type) {
4961 case RTE_TUNNEL_TYPE_VXLAN:
4962 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4965 case RTE_TUNNEL_TYPE_GENEVE:
4966 case RTE_TUNNEL_TYPE_TEREDO:
4967 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4972 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4980 /* Remove UDP tunneling port */
4982 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4983 struct rte_eth_udp_tunnel *udp_tunnel)
4986 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4988 if (udp_tunnel == NULL)
4991 switch (udp_tunnel->prot_type) {
4992 case RTE_TUNNEL_TYPE_VXLAN:
4993 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4995 case RTE_TUNNEL_TYPE_GENEVE:
4996 case RTE_TUNNEL_TYPE_TEREDO:
4997 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5001 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5009 /* Calculate the maximum number of contiguous PF queues that are configured */
5011 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5013 struct rte_eth_dev_data *data = pf->dev_data;
5015 struct i40e_rx_queue *rxq;
5018 for (i = 0; i < pf->lan_nb_qps; i++) {
5019 rxq = data->rx_queues[i];
5020 if (rxq && rxq->q_set)
5031 i40e_pf_config_rss(struct i40e_pf *pf)
5033 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5034 struct rte_eth_rss_conf rss_conf;
5035 uint32_t i, lut = 0;
5039 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5040 * It's necessary to calulate the actual PF queues that are configured.
5042 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5043 num = i40e_pf_calc_configured_queues_num(pf);
5044 num = i40e_align_floor(num);
5046 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5048 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5052 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5056 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5059 lut = (lut << 8) | (j & ((0x1 <<
5060 hw->func_caps.rss_table_entry_width) - 1));
5062 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5065 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5066 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5067 i40e_pf_disable_rss(pf);
5070 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5071 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5072 /* Random default keys */
5073 static uint32_t rss_key_default[] = {0x6b793944,
5074 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5075 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5076 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5078 rss_conf.rss_key = (uint8_t *)rss_key_default;
5079 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5083 return i40e_hw_rss_hash_set(hw, &rss_conf);
5087 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5088 struct rte_eth_tunnel_filter_conf *filter)
5090 if (pf == NULL || filter == NULL) {
5091 PMD_DRV_LOG(ERR, "Invalid parameter");
5095 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5096 PMD_DRV_LOG(ERR, "Invalid queue ID");
5100 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5101 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5105 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5106 (is_zero_ether_addr(filter->outer_mac))) {
5107 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5111 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5112 (is_zero_ether_addr(filter->inner_mac))) {
5113 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5121 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5124 struct rte_eth_tunnel_filter_conf *filter;
5125 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5126 int ret = I40E_SUCCESS;
5128 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5130 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5131 return I40E_ERR_PARAM;
5133 switch (filter_op) {
5134 case RTE_ETH_FILTER_NOP:
5135 if (!(pf->flags & I40E_FLAG_VXLAN))
5136 ret = I40E_NOT_SUPPORTED;
5137 case RTE_ETH_FILTER_ADD:
5138 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5140 case RTE_ETH_FILTER_DELETE:
5141 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5144 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5145 ret = I40E_ERR_PARAM;
5153 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5156 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5158 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5159 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5164 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5165 ret = i40e_pf_config_rss(pf);
5167 i40e_pf_disable_rss(pf);
5172 /* Get the symmetric hash enable configurations per port */
5174 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5176 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5178 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5181 /* Set the symmetric hash enable configurations per port */
5183 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5185 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5188 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5189 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5193 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5195 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5196 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5200 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5202 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5203 I40E_WRITE_FLUSH(hw);
5207 * Get global configurations of hash function type and symmetric hash enable
5208 * per flow type (pctype). Note that global configuration means it affects all
5209 * the ports on the same NIC.
5212 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5213 struct rte_eth_hash_global_conf *g_cfg)
5215 uint32_t reg, mask = I40E_FLOW_TYPES;
5217 enum i40e_filter_pctype pctype;
5219 memset(g_cfg, 0, sizeof(*g_cfg));
5220 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5221 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5222 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5224 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5225 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5226 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5228 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5229 if (!(mask & (1UL << i)))
5231 mask &= ~(1UL << i);
5232 /* Bit set indicats the coresponding flow type is supported */
5233 g_cfg->valid_bit_mask[0] |= (1UL << i);
5234 pctype = i40e_flowtype_to_pctype(i);
5235 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5236 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5237 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5244 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5247 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5249 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5250 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5251 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5252 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5258 * As i40e supports less than 32 flow types, only first 32 bits need to
5261 mask0 = g_cfg->valid_bit_mask[0];
5262 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5264 /* Check if any unsupported flow type configured */
5265 if ((mask0 | i40e_mask) ^ i40e_mask)
5268 if (g_cfg->valid_bit_mask[i])
5276 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5282 * Set global configurations of hash function type and symmetric hash enable
5283 * per flow type (pctype). Note any modifying global configuration will affect
5284 * all the ports on the same NIC.
5287 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5288 struct rte_eth_hash_global_conf *g_cfg)
5293 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5294 enum i40e_filter_pctype pctype;
5296 /* Check the input parameters */
5297 ret = i40e_hash_global_config_check(g_cfg);
5301 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5302 if (!(mask0 & (1UL << i)))
5304 mask0 &= ~(1UL << i);
5305 pctype = i40e_flowtype_to_pctype(i);
5306 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5307 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5308 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5311 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5312 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5314 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5315 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5319 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5320 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5322 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5323 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5327 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5329 /* Use the default, and keep it as it is */
5332 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5335 I40E_WRITE_FLUSH(hw);
5341 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5346 PMD_DRV_LOG(ERR, "Invalid pointer");
5350 switch (info->info_type) {
5351 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5352 i40e_get_symmetric_hash_enable_per_port(hw,
5353 &(info->info.enable));
5355 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5356 ret = i40e_get_hash_filter_global_config(hw,
5357 &(info->info.global_conf));
5360 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5370 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5375 PMD_DRV_LOG(ERR, "Invalid pointer");
5379 switch (info->info_type) {
5380 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5381 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5383 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5384 ret = i40e_set_hash_filter_global_config(hw,
5385 &(info->info.global_conf));
5388 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5397 /* Operations for hash function */
5399 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5400 enum rte_filter_op filter_op,
5403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406 switch (filter_op) {
5407 case RTE_ETH_FILTER_NOP:
5409 case RTE_ETH_FILTER_GET:
5410 ret = i40e_hash_filter_get(hw,
5411 (struct rte_eth_hash_filter_info *)arg);
5413 case RTE_ETH_FILTER_SET:
5414 ret = i40e_hash_filter_set(hw,
5415 (struct rte_eth_hash_filter_info *)arg);
5418 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5428 * Configure ethertype filter, which can director packet by filtering
5429 * with mac address and ether_type or only ether_type
5432 i40e_ethertype_filter_set(struct i40e_pf *pf,
5433 struct rte_eth_ethertype_filter *filter,
5436 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5437 struct i40e_control_filter_stats stats;
5441 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5442 PMD_DRV_LOG(ERR, "Invalid queue ID");
5445 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5446 filter->ether_type == ETHER_TYPE_IPv6) {
5447 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5448 " control packet filter.", filter->ether_type);
5451 if (filter->ether_type == ETHER_TYPE_VLAN)
5452 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5455 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5456 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5457 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5458 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5459 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5461 memset(&stats, 0, sizeof(stats));
5462 ret = i40e_aq_add_rem_control_packet_filter(hw,
5463 filter->mac_addr.addr_bytes,
5464 filter->ether_type, flags,
5466 filter->queue, add, &stats, NULL);
5468 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5469 " mac_etype_used = %u, etype_used = %u,"
5470 " mac_etype_free = %u, etype_free = %u\n",
5471 ret, stats.mac_etype_used, stats.etype_used,
5472 stats.mac_etype_free, stats.etype_free);
5479 * Handle operations for ethertype filter.
5482 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5483 enum rte_filter_op filter_op,
5486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5489 if (filter_op == RTE_ETH_FILTER_NOP)
5493 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5498 switch (filter_op) {
5499 case RTE_ETH_FILTER_ADD:
5500 ret = i40e_ethertype_filter_set(pf,
5501 (struct rte_eth_ethertype_filter *)arg,
5504 case RTE_ETH_FILTER_DELETE:
5505 ret = i40e_ethertype_filter_set(pf,
5506 (struct rte_eth_ethertype_filter *)arg,
5510 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5518 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5519 enum rte_filter_type filter_type,
5520 enum rte_filter_op filter_op,
5528 switch (filter_type) {
5529 case RTE_ETH_FILTER_HASH:
5530 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5532 case RTE_ETH_FILTER_MACVLAN:
5533 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5535 case RTE_ETH_FILTER_ETHERTYPE:
5536 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5538 case RTE_ETH_FILTER_TUNNEL:
5539 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5541 case RTE_ETH_FILTER_FDIR:
5542 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5545 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5555 * As some registers wouldn't be reset unless a global hardware reset,
5556 * hardware initialization is needed to put those registers into an
5557 * expected initial state.
5560 i40e_hw_init(struct i40e_hw *hw)
5562 /* clear the PF Queue Filter control register */
5563 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5565 /* Disable symmetric hash per port */
5566 i40e_set_symmetric_hash_enable_per_port(hw, 0);
5569 enum i40e_filter_pctype
5570 i40e_flowtype_to_pctype(uint16_t flow_type)
5572 static const enum i40e_filter_pctype pctype_table[] = {
5573 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5574 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5575 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5576 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5577 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5578 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5579 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5580 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5581 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5582 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5583 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5584 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5585 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5586 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5587 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5588 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5589 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5590 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5591 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5594 return pctype_table[flow_type];
5598 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5600 static const uint16_t flowtype_table[] = {
5601 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5602 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5603 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5604 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5605 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5606 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5607 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5608 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5609 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5610 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5611 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5612 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5613 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5614 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5615 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5616 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5617 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5618 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5619 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5622 return flowtype_table[pctype];
5626 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5628 struct i40e_aq_desc desc;
5629 enum i40e_status_code status;
5631 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5632 desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5633 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5637 *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5638 (CHAR_BIT * sizeof(uint32_t))) +
5639 rte_le_to_cpu_32(desc.params.internal.param3);
5645 * On X710, performance number is far from the expectation on recent firmware
5646 * versions; on XL710, performance number is also far from the expectation on
5647 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5648 * mode is enabled and port MAC address is equal to the packet destination MAC
5649 * address. The fix for this issue may not be integrated in the following
5650 * firmware version. So the workaround in software driver is needed. It needs
5651 * to modify the initial values of 3 internal only registers for both X710 and
5652 * XL710. Note that the values for X710 or XL710 could be different, and the
5653 * workaround can be removed when it is fixed in firmware in the future.
5656 /* For both X710 and XL710 */
5657 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5658 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
5660 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5661 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
5664 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
5666 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
5667 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
5670 i40e_configure_registers(struct i40e_hw *hw)
5676 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5677 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5678 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5684 for (i = 0; i < RTE_DIM(reg_table); i++) {
5685 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5686 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5688 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5691 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5694 ret = i40e_debug_read_register(hw, reg_table[i].addr, ®);
5696 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5700 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5701 reg_table[i].addr, reg);
5702 if (reg == reg_table[i].val)
5705 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5706 reg_table[i].val, NULL);
5708 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5709 "address of 0x%"PRIx32, reg_table[i].val,
5713 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5714 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);