lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51 #include <rte_eth_ctrl.h>
  52
  53 #include "i40e_logs.h"
  54 #include "i40e/i40e_register_x710_int.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 #define I40E_DEFAULT_RX_FREE_THRESH  32
  63 #define I40E_DEFAULT_RX_PTHRESH      8
  64 #define I40E_DEFAULT_RX_HTHRESH      8
  65 #define I40E_DEFAULT_RX_WTHRESH      0
  66
  67 #define I40E_DEFAULT_TX_FREE_THRESH  32
  68 #define I40E_DEFAULT_TX_PTHRESH      32
  69 #define I40E_DEFAULT_TX_HTHRESH      0
  70 #define I40E_DEFAULT_TX_WTHRESH      0
  71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  72
  73 /* Maximun number of MAC addresses */
  74 #define I40E_NUM_MACADDR_MAX       64
  75 #define I40E_CLEAR_PXE_WAIT_MS     200
  76
  77 /* Maximun number of capability elements */
  78 #define I40E_MAX_CAP_ELE_NUM       128
  79
  80 /* Wait count and inteval */
  81 #define I40E_CHK_Q_ENA_COUNT       1000
  82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  83
  84 /* Maximun number of VSI */
  85 #define I40E_MAX_NUM_VSIS          (384UL)
  86
  87 /* Bit shift and mask */
  88 #define I40E_16_BIT_SHIFT 16
  89 #define I40E_16_BIT_MASK  0xFFFF
  90 #define I40E_32_BIT_SHIFT 32
  91 #define I40E_32_BIT_MASK  0xFFFFFFFF
  92 #define I40E_48_BIT_SHIFT 48
  93 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  94
  95 /* Default queue interrupt throttling time in microseconds*/
  96 #define I40E_ITR_INDEX_DEFAULT          0
  97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  98 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  99
 100 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 101
 102 static int eth_i40e_dev_init(\
 103                         __attribute__((unused)) struct eth_driver *eth_drv,
 104                         struct rte_eth_dev *eth_dev);
 105 static int i40e_dev_configure(struct rte_eth_dev *dev);
 106 static int i40e_dev_start(struct rte_eth_dev *dev);
 107 static void i40e_dev_stop(struct rte_eth_dev *dev);
 108 static void i40e_dev_close(struct rte_eth_dev *dev);
 109 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 114 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 115 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 116                                struct rte_eth_stats *stats);
 117 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 118 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 119                                             uint16_t queue_id,
 120                                             uint8_t stat_idx,
 121                                             uint8_t is_rx);
 122 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 123                               struct rte_eth_dev_info *dev_info);
 124 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 125                                 uint16_t vlan_id,
 126                                 int on);
 127 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 128 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 130                                       uint16_t queue,
 131                                       int on);
 132 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 133 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 134 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 135 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 136                               struct rte_eth_fc_conf *fc_conf);
 137 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 138                                        struct rte_eth_pfc_conf *pfc_conf);
 139 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 140                           struct ether_addr *mac_addr,
 141                           uint32_t index,
 142                           uint32_t pool);
 143 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 144 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 145                                     struct rte_eth_rss_reta *reta_conf);
 146 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                                    struct rte_eth_rss_reta *reta_conf);
 148
 149 static int i40e_get_cap(struct i40e_hw *hw);
 150 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 151 static int i40e_pf_setup(struct i40e_pf *pf);
 152 static int i40e_vsi_init(struct i40e_vsi *vsi);
 153 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 154                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 155 static void i40e_stat_update_48(struct i40e_hw *hw,
 156                                uint32_t hireg,
 157                                uint32_t loreg,
 158                                bool offset_loaded,
 159                                uint64_t *offset,
 160                                uint64_t *stat);
 161 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 162 static void i40e_dev_interrupt_handler(
 163                 __rte_unused struct rte_intr_handle *handle, void *param);
 164 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 165                                 uint32_t base, uint32_t num);
 166 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 167 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 168                         uint32_t base);
 169 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 170                         uint16_t num);
 171 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 172 static int i40e_veb_release(struct i40e_veb *veb);
 173 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 174                                                 struct i40e_vsi *vsi);
 175 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 176 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 177 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 178                                              struct i40e_macvlan_filter *mv_f,
 179                                              int num,
 180                                              struct ether_addr *addr);
 181 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 182                                              struct i40e_macvlan_filter *mv_f,
 183                                              int num,
 184                                              uint16_t vlan);
 185 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 186 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 187                                     struct rte_eth_rss_conf *rss_conf);
 188 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 189                                       struct rte_eth_rss_conf *rss_conf);
 190 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 191                                 struct rte_eth_udp_tunnel *udp_tunnel);
 192 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 193                                 struct rte_eth_udp_tunnel *udp_tunnel);
 194 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 195                                 enum rte_filter_type filter_type,
 196                                 enum rte_filter_op filter_op,
 197                                 void *arg);
 198
 199 /* Default hash key buffer for RSS */
 200 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 201
 202 static struct rte_pci_id pci_id_i40e_map[] = {
 203 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 204 #include "rte_pci_dev_ids.h"
 205 { .vendor_id = 0, /* sentinel */ },
 206 };
 207
 208 static struct eth_dev_ops i40e_eth_dev_ops = {
 209         .dev_configure                = i40e_dev_configure,
 210         .dev_start                    = i40e_dev_start,
 211         .dev_stop                     = i40e_dev_stop,
 212         .dev_close                    = i40e_dev_close,
 213         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 214         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 215         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 216         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 217         .dev_set_link_up              = i40e_dev_set_link_up,
 218         .dev_set_link_down            = i40e_dev_set_link_down,
 219         .link_update                  = i40e_dev_link_update,
 220         .stats_get                    = i40e_dev_stats_get,
 221         .stats_reset                  = i40e_dev_stats_reset,
 222         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 223         .dev_infos_get                = i40e_dev_info_get,
 224         .vlan_filter_set              = i40e_vlan_filter_set,
 225         .vlan_tpid_set                = i40e_vlan_tpid_set,
 226         .vlan_offload_set             = i40e_vlan_offload_set,
 227         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 228         .vlan_pvid_set                = i40e_vlan_pvid_set,
 229         .rx_queue_start               = i40e_dev_rx_queue_start,
 230         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 231         .tx_queue_start               = i40e_dev_tx_queue_start,
 232         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 233         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 234         .rx_queue_release             = i40e_dev_rx_queue_release,
 235         .rx_queue_count               = i40e_dev_rx_queue_count,
 236         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 237         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 238         .tx_queue_release             = i40e_dev_tx_queue_release,
 239         .dev_led_on                   = i40e_dev_led_on,
 240         .dev_led_off                  = i40e_dev_led_off,
 241         .flow_ctrl_set                = i40e_flow_ctrl_set,
 242         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 243         .mac_addr_add                 = i40e_macaddr_add,
 244         .mac_addr_remove              = i40e_macaddr_remove,
 245         .reta_update                  = i40e_dev_rss_reta_update,
 246         .reta_query                   = i40e_dev_rss_reta_query,
 247         .rss_hash_update              = i40e_dev_rss_hash_update,
 248         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 249         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 250         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 251         .filter_ctrl                  = i40e_dev_filter_ctrl,
 252 };
 253
 254 static struct eth_driver rte_i40e_pmd = {
 255         {
 256                 .name = "rte_i40e_pmd",
 257                 .id_table = pci_id_i40e_map,
 258                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 259         },
 260         .eth_dev_init = eth_i40e_dev_init,
 261         .dev_private_size = sizeof(struct i40e_adapter),
 262 };
 263
 264 static inline int
 265 i40e_prev_power_of_2(int n)
 266 {
 267        int p = n;
 268
 269        --p;
 270        p |= p >> 1;
 271        p |= p >> 2;
 272        p |= p >> 4;
 273        p |= p >> 8;
 274        p |= p >> 16;
 275        if (p == (n - 1))
 276                return n;
 277        p >>= 1;
 278
 279        return ++p;
 280 }
 281
 282 static inline int
 283 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 284                                      struct rte_eth_link *link)
 285 {
 286         struct rte_eth_link *dst = link;
 287         struct rte_eth_link *src = &(dev->data->dev_link);
 288
 289         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 290                                         *(uint64_t *)src) == 0)
 291                 return -1;
 292
 293         return 0;
 294 }
 295
 296 static inline int
 297 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 298                                       struct rte_eth_link *link)
 299 {
 300         struct rte_eth_link *dst = &(dev->data->dev_link);
 301         struct rte_eth_link *src = link;
 302
 303         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 304                                         *(uint64_t *)src) == 0)
 305                 return -1;
 306
 307         return 0;
 308 }
 309
 310 /*
 311  * Driver initialization routine.
 312  * Invoked once at EAL init time.
 313  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 314  */
 315 static int
 316 rte_i40e_pmd_init(const char *name __rte_unused,
 317                   const char *params __rte_unused)
 318 {
 319         PMD_INIT_FUNC_TRACE();
 320         rte_eth_driver_register(&rte_i40e_pmd);
 321
 322         return 0;
 323 }
 324
 325 static struct rte_driver rte_i40e_driver = {
 326         .type = PMD_PDEV,
 327         .init = rte_i40e_pmd_init,
 328 };
 329
 330 PMD_REGISTER_DRIVER(rte_i40e_driver);
 331
 332 static int
 333 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 334                   struct rte_eth_dev *dev)
 335 {
 336         struct rte_pci_device *pci_dev;
 337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339         struct i40e_vsi *vsi;
 340         int ret;
 341         uint32_t len;
 342         uint8_t aq_fail = 0;
 343
 344         PMD_INIT_FUNC_TRACE();
 345
 346         dev->dev_ops = &i40e_eth_dev_ops;
 347         dev->rx_pkt_burst = i40e_recv_pkts;
 348         dev->tx_pkt_burst = i40e_xmit_pkts;
 349
 350         /* for secondary processes, we don't initialise any further as primary
 351          * has already done this work. Only check we don't need a different
 352          * RX function */
 353         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 354                 if (dev->data->scattered_rx)
 355                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 356                 return 0;
 357         }
 358         pci_dev = dev->pci_dev;
 359         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 360         pf->adapter->eth_dev = dev;
 361         pf->dev_data = dev->data;
 362
 363         hw->back = I40E_PF_TO_ADAPTER(pf);
 364         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 365         if (!hw->hw_addr) {
 366                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 367                              "as address is NULL");
 368                 return -ENODEV;
 369         }
 370
 371         hw->vendor_id = pci_dev->id.vendor_id;
 372         hw->device_id = pci_dev->id.device_id;
 373         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 374         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 375         hw->bus.device = pci_dev->addr.devid;
 376         hw->bus.func = pci_dev->addr.function;
 377
 378         /* Make sure all is clean before doing PF reset */
 379         i40e_clear_hw(hw);
 380
 381         /* Reset here to make sure all is clean for each PF */
 382         ret = i40e_pf_reset(hw);
 383         if (ret) {
 384                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 385                 return ret;
 386         }
 387
 388         /* Initialize the shared code (base driver) */
 389         ret = i40e_init_shared_code(hw);
 390         if (ret) {
 391                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 392                 return ret;
 393         }
 394
 395         /* Initialize the parameters for adminq */
 396         i40e_init_adminq_parameter(hw);
 397         ret = i40e_init_adminq(hw);
 398         if (ret != I40E_SUCCESS) {
 399                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 400                 return -EIO;
 401         }
 402         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 403                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 404                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 405                      ((hw->nvm.version >> 12) & 0xf),
 406                      ((hw->nvm.version >> 4) & 0xff),
 407                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 408
 409         /* Disable LLDP */
 410         ret = i40e_aq_stop_lldp(hw, true, NULL);
 411         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 412                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 413
 414         /* Clear PXE mode */
 415         i40e_clear_pxe_mode(hw);
 416
 417         /* Get hw capabilities */
 418         ret = i40e_get_cap(hw);
 419         if (ret != I40E_SUCCESS) {
 420                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 421                 goto err_get_capabilities;
 422         }
 423
 424         /* Initialize parameters for PF */
 425         ret = i40e_pf_parameter_init(dev);
 426         if (ret != 0) {
 427                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 428                 goto err_parameter_init;
 429         }
 430
 431         /* Initialize the queue management */
 432         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 433         if (ret < 0) {
 434                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 435                 goto err_qp_pool_init;
 436         }
 437         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 438                                 hw->func_caps.num_msix_vectors - 1);
 439         if (ret < 0) {
 440                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 441                 goto err_msix_pool_init;
 442         }
 443
 444         /* Initialize lan hmc */
 445         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 446                                 hw->func_caps.num_rx_qp, 0, 0);
 447         if (ret != I40E_SUCCESS) {
 448                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 449                 goto err_init_lan_hmc;
 450         }
 451
 452         /* Configure lan hmc */
 453         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 454         if (ret != I40E_SUCCESS) {
 455                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 456                 goto err_configure_lan_hmc;
 457         }
 458
 459         /* Get and check the mac address */
 460         i40e_get_mac_addr(hw, hw->mac.addr);
 461         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 462                 PMD_INIT_LOG(ERR, "mac address is not valid");
 463                 ret = -EIO;
 464                 goto err_get_mac_addr;
 465         }
 466         /* Copy the permanent MAC address */
 467         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 468                         (struct ether_addr *) hw->mac.perm_addr);
 469
 470         /* Disable flow control */
 471         hw->fc.requested_mode = I40E_FC_NONE;
 472         i40e_set_fc(hw, &aq_fail, TRUE);
 473
 474         /* PF setup, which includes VSI setup */
 475         ret = i40e_pf_setup(pf);
 476         if (ret) {
 477                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 478                 goto err_setup_pf_switch;
 479         }
 480
 481         vsi = pf->main_vsi;
 482
 483         /* Disable double vlan by default */
 484         i40e_vsi_config_double_vlan(vsi, FALSE);
 485
 486         if (!vsi->max_macaddrs)
 487                 len = ETHER_ADDR_LEN;
 488         else
 489                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 490
 491         /* Should be after VSI initialized */
 492         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 493         if (!dev->data->mac_addrs) {
 494                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 495                                         "for storing mac address");
 496                 goto err_get_mac_addr;
 497         }
 498         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 499                                         &dev->data->mac_addrs[0]);
 500
 501         /* initialize pf host driver to setup SRIOV resource if applicable */
 502         i40e_pf_host_init(dev);
 503
 504         /* register callback func to eal lib */
 505         rte_intr_callback_register(&(pci_dev->intr_handle),
 506                 i40e_dev_interrupt_handler, (void *)dev);
 507
 508         /* configure and enable device interrupt */
 509         i40e_pf_config_irq0(hw);
 510         i40e_pf_enable_irq0(hw);
 511
 512         /* enable uio intr after callback register */
 513         rte_intr_enable(&(pci_dev->intr_handle));
 514
 515         return 0;
 516
 517 err_setup_pf_switch:
 518         rte_free(pf->main_vsi);
 519 err_get_mac_addr:
 520 err_configure_lan_hmc:
 521         (void)i40e_shutdown_lan_hmc(hw);
 522 err_init_lan_hmc:
 523         i40e_res_pool_destroy(&pf->msix_pool);
 524 err_msix_pool_init:
 525         i40e_res_pool_destroy(&pf->qp_pool);
 526 err_qp_pool_init:
 527 err_parameter_init:
 528 err_get_capabilities:
 529         (void)i40e_shutdown_adminq(hw);
 530
 531         return ret;
 532 }
 533
 534 static int
 535 i40e_dev_configure(struct rte_eth_dev *dev)
 536 {
 537         return i40e_dev_init_vlan(dev);
 538 }
 539
 540 void
 541 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 542 {
 543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 544         uint16_t msix_vect = vsi->msix_intr;
 545         uint16_t i;
 546
 547         for (i = 0; i < vsi->nb_qps; i++) {
 548                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 549                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 550                 rte_wmb();
 551         }
 552
 553         if (vsi->type != I40E_VSI_SRIOV) {
 554                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 555                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 556                                 msix_vect - 1), 0);
 557         } else {
 558                 uint32_t reg;
 559                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 560                         vsi->user_param + (msix_vect - 1);
 561
 562                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 563         }
 564         I40E_WRITE_FLUSH(hw);
 565 }
 566
 567 static inline uint16_t
 568 i40e_calc_itr_interval(int16_t interval)
 569 {
 570         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 571                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 572
 573         /* Convert to hardware count, as writing each 1 represents 2 us */
 574         return (interval/2);
 575 }
 576
 577 void
 578 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 579 {
 580         uint32_t val;
 581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 582         uint16_t msix_vect = vsi->msix_intr;
 583         int i;
 584
 585         for (i = 0; i < vsi->nb_qps; i++)
 586                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 587
 588         /* Bind all RX queues to allocated MSIX interrupt */
 589         for (i = 0; i < vsi->nb_qps; i++) {
 590                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 591                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 592                         ((vsi->base_queue + i + 1) <<
 593                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 594                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 595                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 596
 597                 if (i == vsi->nb_qps - 1)
 598                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 599                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 600         }
 601
 602         /* Write first RX queue to Link list register as the head element */
 603         if (vsi->type != I40E_VSI_SRIOV) {
 604                 uint16_t interval =
 605                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 606
 607                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 608                                                 (vsi->base_queue <<
 609                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 610                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 611
 612                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 613                                                 msix_vect - 1), interval);
 614
 615                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 616                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 617                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 618         } else {
 619                 uint32_t reg;
 620
 621                 /* num_msix_vectors_vf needs to minus irq0 */
 622                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 623                         vsi->user_param + (msix_vect - 1);
 624
 625                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 626                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 627                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 628         }
 629
 630         I40E_WRITE_FLUSH(hw);
 631 }
 632
 633 static void
 634 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 635 {
 636         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 637         uint16_t interval = i40e_calc_itr_interval(\
 638                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 639
 640         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 641                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 642                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 643                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 644                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 645 }
 646
 647 static void
 648 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 649 {
 650         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 651
 652         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 653 }
 654
 655 static inline uint8_t
 656 i40e_parse_link_speed(uint16_t eth_link_speed)
 657 {
 658         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 659
 660         switch (eth_link_speed) {
 661         case ETH_LINK_SPEED_40G:
 662                 link_speed = I40E_LINK_SPEED_40GB;
 663                 break;
 664         case ETH_LINK_SPEED_20G:
 665                 link_speed = I40E_LINK_SPEED_20GB;
 666                 break;
 667         case ETH_LINK_SPEED_10G:
 668                 link_speed = I40E_LINK_SPEED_10GB;
 669                 break;
 670         case ETH_LINK_SPEED_1000:
 671                 link_speed = I40E_LINK_SPEED_1GB;
 672                 break;
 673         case ETH_LINK_SPEED_100:
 674                 link_speed = I40E_LINK_SPEED_100MB;
 675                 break;
 676         }
 677
 678         return link_speed;
 679 }
 680
 681 static int
 682 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 683 {
 684         enum i40e_status_code status;
 685         struct i40e_aq_get_phy_abilities_resp phy_ab;
 686         struct i40e_aq_set_phy_config phy_conf;
 687         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 688                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 689                         I40E_AQ_PHY_FLAG_LOW_POWER;
 690         const uint8_t advt = I40E_LINK_SPEED_40GB |
 691                         I40E_LINK_SPEED_10GB |
 692                         I40E_LINK_SPEED_1GB |
 693                         I40E_LINK_SPEED_100MB;
 694         int ret = -ENOTSUP;
 695
 696         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 697                                               NULL);
 698         if (status)
 699                 return ret;
 700
 701         memset(&phy_conf, 0, sizeof(phy_conf));
 702
 703         /* bits 0-2 use the values from get_phy_abilities_resp */
 704         abilities &= ~mask;
 705         abilities |= phy_ab.abilities & mask;
 706
 707         /* update ablities and speed */
 708         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 709                 phy_conf.link_speed = advt;
 710         else
 711                 phy_conf.link_speed = force_speed;
 712
 713         phy_conf.abilities = abilities;
 714
 715         /* use get_phy_abilities_resp value for the rest */
 716         phy_conf.phy_type = phy_ab.phy_type;
 717         phy_conf.eee_capability = phy_ab.eee_capability;
 718         phy_conf.eeer = phy_ab.eeer_val;
 719         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 720
 721         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 722                     phy_ab.abilities, phy_ab.link_speed);
 723         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 724                     phy_conf.abilities, phy_conf.link_speed);
 725
 726         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 727         if (status)
 728                 return ret;
 729
 730         return I40E_SUCCESS;
 731 }
 732
 733 static int
 734 i40e_apply_link_speed(struct rte_eth_dev *dev)
 735 {
 736         uint8_t speed;
 737         uint8_t abilities = 0;
 738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 739         struct rte_eth_conf *conf = &dev->data->dev_conf;
 740
 741         speed = i40e_parse_link_speed(conf->link_speed);
 742         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 743         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 744                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 745         else
 746                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 747
 748         return i40e_phy_conf_link(hw, abilities, speed);
 749 }
 750
 751 static int
 752 i40e_dev_start(struct rte_eth_dev *dev)
 753 {
 754         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 755         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 756         struct i40e_vsi *vsi = pf->main_vsi;
 757         int ret;
 758
 759         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 760                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 761                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 762                              dev->data->dev_conf.link_duplex,
 763                              dev->data->port_id);
 764                 return -EINVAL;
 765         }
 766
 767         /* Initialize VSI */
 768         ret = i40e_vsi_init(vsi);
 769         if (ret != I40E_SUCCESS) {
 770                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 771                 goto err_up;
 772         }
 773
 774         /* Map queues with MSIX interrupt */
 775         i40e_vsi_queues_bind_intr(vsi);
 776         i40e_vsi_enable_queues_intr(vsi);
 777
 778         /* Enable all queues which have been configured */
 779         ret = i40e_vsi_switch_queues(vsi, TRUE);
 780         if (ret != I40E_SUCCESS) {
 781                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 782                 goto err_up;
 783         }
 784
 785         /* Enable receiving broadcast packets */
 786         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 787                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 788                 if (ret != I40E_SUCCESS)
 789                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 790         }
 791
 792         /* Apply link configure */
 793         ret = i40e_apply_link_speed(dev);
 794         if (I40E_SUCCESS != ret) {
 795                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 796                 goto err_up;
 797         }
 798
 799         return I40E_SUCCESS;
 800
 801 err_up:
 802         i40e_vsi_switch_queues(vsi, FALSE);
 803
 804         return ret;
 805 }
 806
 807 static void
 808 i40e_dev_stop(struct rte_eth_dev *dev)
 809 {
 810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 811         struct i40e_vsi *vsi = pf->main_vsi;
 812
 813         /* Disable all queues */
 814         i40e_vsi_switch_queues(vsi, FALSE);
 815
 816         /* Set link down */
 817         i40e_dev_set_link_down(dev);
 818
 819         /* un-map queues with interrupt registers */
 820         i40e_vsi_disable_queues_intr(vsi);
 821         i40e_vsi_queues_unbind_intr(vsi);
 822 }
 823
 824 static void
 825 i40e_dev_close(struct rte_eth_dev *dev)
 826 {
 827         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 829         uint32_t reg;
 830
 831         PMD_INIT_FUNC_TRACE();
 832
 833         i40e_dev_stop(dev);
 834
 835         /* Disable interrupt */
 836         i40e_pf_disable_irq0(hw);
 837         rte_intr_disable(&(dev->pci_dev->intr_handle));
 838
 839         /* shutdown and destroy the HMC */
 840         i40e_shutdown_lan_hmc(hw);
 841
 842         /* release all the existing VSIs and VEBs */
 843         i40e_vsi_release(pf->main_vsi);
 844
 845         /* shutdown the adminq */
 846         i40e_aq_queue_shutdown(hw, true);
 847         i40e_shutdown_adminq(hw);
 848
 849         i40e_res_pool_destroy(&pf->qp_pool);
 850         i40e_res_pool_destroy(&pf->msix_pool);
 851
 852         /* force a PF reset to clean anything leftover */
 853         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 854         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 855                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 856         I40E_WRITE_FLUSH(hw);
 857 }
 858
 859 static void
 860 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 861 {
 862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 864         struct i40e_vsi *vsi = pf->main_vsi;
 865         int status;
 866
 867         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 868                                                         true, NULL);
 869         if (status != I40E_SUCCESS)
 870                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 871
 872         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 873                                                         TRUE, NULL);
 874         if (status != I40E_SUCCESS)
 875                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 876
 877 }
 878
 879 static void
 880 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 881 {
 882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884         struct i40e_vsi *vsi = pf->main_vsi;
 885         int status;
 886
 887         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 888                                                         false, NULL);
 889         if (status != I40E_SUCCESS)
 890                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 891
 892         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 893                                                         false, NULL);
 894         if (status != I40E_SUCCESS)
 895                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 896 }
 897
 898 static void
 899 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 900 {
 901         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 903         struct i40e_vsi *vsi = pf->main_vsi;
 904         int ret;
 905
 906         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 907         if (ret != I40E_SUCCESS)
 908                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 909 }
 910
 911 static void
 912 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 913 {
 914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916         struct i40e_vsi *vsi = pf->main_vsi;
 917         int ret;
 918
 919         if (dev->data->promiscuous == 1)
 920                 return; /* must remain in all_multicast mode */
 921
 922         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 923                                 vsi->seid, FALSE, NULL);
 924         if (ret != I40E_SUCCESS)
 925                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 926 }
 927
 928 /*
 929  * Set device link up.
 930  */
 931 static int
 932 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 933 {
 934         /* re-apply link speed setting */
 935         return i40e_apply_link_speed(dev);
 936 }
 937
 938 /*
 939  * Set device link down.
 940  */
 941 static int
 942 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 943 {
 944         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 945         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 946         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947
 948         return i40e_phy_conf_link(hw, abilities, speed);
 949 }
 950
 951 int
 952 i40e_dev_link_update(struct rte_eth_dev *dev,
 953                      __rte_unused int wait_to_complete)
 954 {
 955         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         struct i40e_link_status link_status;
 957         struct rte_eth_link link, old;
 958         int status;
 959
 960         memset(&link, 0, sizeof(link));
 961         memset(&old, 0, sizeof(old));
 962         memset(&link_status, 0, sizeof(link_status));
 963         rte_i40e_dev_atomic_read_link_status(dev, &old);
 964
 965         /* Get link status information from hardware */
 966         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 967         if (status != I40E_SUCCESS) {
 968                 link.link_speed = ETH_LINK_SPEED_100;
 969                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 970                 PMD_DRV_LOG(ERR, "Failed to get link info");
 971                 goto out;
 972         }
 973
 974         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 975
 976         if (!link.link_status)
 977                 goto out;
 978
 979         /* i40e uses full duplex only */
 980         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 981
 982         /* Parse the link status */
 983         switch (link_status.link_speed) {
 984         case I40E_LINK_SPEED_100MB:
 985                 link.link_speed = ETH_LINK_SPEED_100;
 986                 break;
 987         case I40E_LINK_SPEED_1GB:
 988                 link.link_speed = ETH_LINK_SPEED_1000;
 989                 break;
 990         case I40E_LINK_SPEED_10GB:
 991                 link.link_speed = ETH_LINK_SPEED_10G;
 992                 break;
 993         case I40E_LINK_SPEED_20GB:
 994                 link.link_speed = ETH_LINK_SPEED_20G;
 995                 break;
 996         case I40E_LINK_SPEED_40GB:
 997                 link.link_speed = ETH_LINK_SPEED_40G;
 998                 break;
 999         default:
1000                 link.link_speed = ETH_LINK_SPEED_100;
1001                 break;
1002         }
1003
1004 out:
1005         rte_i40e_dev_atomic_write_link_status(dev, &link);
1006         if (link.link_status == old.link_status)
1007                 return -1;
1008
1009         return 0;
1010 }
1011
1012 /* Get all the statistics of a VSI */
1013 void
1014 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1015 {
1016         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1017         struct i40e_eth_stats *nes = &vsi->eth_stats;
1018         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1019         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1020
1021         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1022                             vsi->offset_loaded, &oes->rx_bytes,
1023                             &nes->rx_bytes);
1024         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1025                             vsi->offset_loaded, &oes->rx_unicast,
1026                             &nes->rx_unicast);
1027         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1028                             vsi->offset_loaded, &oes->rx_multicast,
1029                             &nes->rx_multicast);
1030         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1031                             vsi->offset_loaded, &oes->rx_broadcast,
1032                             &nes->rx_broadcast);
1033         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1034                             &oes->rx_discards, &nes->rx_discards);
1035         /* GLV_REPC not supported */
1036         /* GLV_RMPC not supported */
1037         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1038                             &oes->rx_unknown_protocol,
1039                             &nes->rx_unknown_protocol);
1040         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1041                             vsi->offset_loaded, &oes->tx_bytes,
1042                             &nes->tx_bytes);
1043         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1044                             vsi->offset_loaded, &oes->tx_unicast,
1045                             &nes->tx_unicast);
1046         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1047                             vsi->offset_loaded, &oes->tx_multicast,
1048                             &nes->tx_multicast);
1049         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1050                             vsi->offset_loaded,  &oes->tx_broadcast,
1051                             &nes->tx_broadcast);
1052         /* GLV_TDPC not supported */
1053         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1054                             &oes->tx_errors, &nes->tx_errors);
1055         vsi->offset_loaded = true;
1056
1057         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1058                     vsi->vsi_id);
1059         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1060         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1061         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1062         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1063         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1064         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1065                     nes->rx_unknown_protocol);
1066         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1067         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1068         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1069         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1070         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1071         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1072         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1073                     vsi->vsi_id);
1074 }
1075
1076 /* Get all statistics of a port */
1077 static void
1078 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1079 {
1080         uint32_t i;
1081         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1082         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1083         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1084         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1085
1086         /* Get statistics of struct i40e_eth_stats */
1087         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1088                             I40E_GLPRT_GORCL(hw->port),
1089                             pf->offset_loaded, &os->eth.rx_bytes,
1090                             &ns->eth.rx_bytes);
1091         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1092                             I40E_GLPRT_UPRCL(hw->port),
1093                             pf->offset_loaded, &os->eth.rx_unicast,
1094                             &ns->eth.rx_unicast);
1095         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1096                             I40E_GLPRT_MPRCL(hw->port),
1097                             pf->offset_loaded, &os->eth.rx_multicast,
1098                             &ns->eth.rx_multicast);
1099         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1100                             I40E_GLPRT_BPRCL(hw->port),
1101                             pf->offset_loaded, &os->eth.rx_broadcast,
1102                             &ns->eth.rx_broadcast);
1103         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1104                             pf->offset_loaded, &os->eth.rx_discards,
1105                             &ns->eth.rx_discards);
1106         /* GLPRT_REPC not supported */
1107         /* GLPRT_RMPC not supported */
1108         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1109                             pf->offset_loaded,
1110                             &os->eth.rx_unknown_protocol,
1111                             &ns->eth.rx_unknown_protocol);
1112         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1113                             I40E_GLPRT_GOTCL(hw->port),
1114                             pf->offset_loaded, &os->eth.tx_bytes,
1115                             &ns->eth.tx_bytes);
1116         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1117                             I40E_GLPRT_UPTCL(hw->port),
1118                             pf->offset_loaded, &os->eth.tx_unicast,
1119                             &ns->eth.tx_unicast);
1120         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1121                             I40E_GLPRT_MPTCL(hw->port),
1122                             pf->offset_loaded, &os->eth.tx_multicast,
1123                             &ns->eth.tx_multicast);
1124         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1125                             I40E_GLPRT_BPTCL(hw->port),
1126                             pf->offset_loaded, &os->eth.tx_broadcast,
1127                             &ns->eth.tx_broadcast);
1128         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1129                             pf->offset_loaded, &os->eth.tx_discards,
1130                             &ns->eth.tx_discards);
1131         /* GLPRT_TEPC not supported */
1132
1133         /* additional port specific stats */
1134         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1135                             pf->offset_loaded, &os->tx_dropped_link_down,
1136                             &ns->tx_dropped_link_down);
1137         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1138                             pf->offset_loaded, &os->crc_errors,
1139                             &ns->crc_errors);
1140         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1141                             pf->offset_loaded, &os->illegal_bytes,
1142                             &ns->illegal_bytes);
1143         /* GLPRT_ERRBC not supported */
1144         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1145                             pf->offset_loaded, &os->mac_local_faults,
1146                             &ns->mac_local_faults);
1147         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1148                             pf->offset_loaded, &os->mac_remote_faults,
1149                             &ns->mac_remote_faults);
1150         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1151                             pf->offset_loaded, &os->rx_length_errors,
1152                             &ns->rx_length_errors);
1153         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1154                             pf->offset_loaded, &os->link_xon_rx,
1155                             &ns->link_xon_rx);
1156         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1157                             pf->offset_loaded, &os->link_xoff_rx,
1158                             &ns->link_xoff_rx);
1159         for (i = 0; i < 8; i++) {
1160                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1161                                     pf->offset_loaded,
1162                                     &os->priority_xon_rx[i],
1163                                     &ns->priority_xon_rx[i]);
1164                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1165                                     pf->offset_loaded,
1166                                     &os->priority_xoff_rx[i],
1167                                     &ns->priority_xoff_rx[i]);
1168         }
1169         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1170                             pf->offset_loaded, &os->link_xon_tx,
1171                             &ns->link_xon_tx);
1172         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1173                             pf->offset_loaded, &os->link_xoff_tx,
1174                             &ns->link_xoff_tx);
1175         for (i = 0; i < 8; i++) {
1176                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1177                                     pf->offset_loaded,
1178                                     &os->priority_xon_tx[i],
1179                                     &ns->priority_xon_tx[i]);
1180                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1181                                     pf->offset_loaded,
1182                                     &os->priority_xoff_tx[i],
1183                                     &ns->priority_xoff_tx[i]);
1184                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1185                                     pf->offset_loaded,
1186                                     &os->priority_xon_2_xoff[i],
1187                                     &ns->priority_xon_2_xoff[i]);
1188         }
1189         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1190                             I40E_GLPRT_PRC64L(hw->port),
1191                             pf->offset_loaded, &os->rx_size_64,
1192                             &ns->rx_size_64);
1193         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1194                             I40E_GLPRT_PRC127L(hw->port),
1195                             pf->offset_loaded, &os->rx_size_127,
1196                             &ns->rx_size_127);
1197         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1198                             I40E_GLPRT_PRC255L(hw->port),
1199                             pf->offset_loaded, &os->rx_size_255,
1200                             &ns->rx_size_255);
1201         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1202                             I40E_GLPRT_PRC511L(hw->port),
1203                             pf->offset_loaded, &os->rx_size_511,
1204                             &ns->rx_size_511);
1205         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1206                             I40E_GLPRT_PRC1023L(hw->port),
1207                             pf->offset_loaded, &os->rx_size_1023,
1208                             &ns->rx_size_1023);
1209         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1210                             I40E_GLPRT_PRC1522L(hw->port),
1211                             pf->offset_loaded, &os->rx_size_1522,
1212                             &ns->rx_size_1522);
1213         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1214                             I40E_GLPRT_PRC9522L(hw->port),
1215                             pf->offset_loaded, &os->rx_size_big,
1216                             &ns->rx_size_big);
1217         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1218                             pf->offset_loaded, &os->rx_undersize,
1219                             &ns->rx_undersize);
1220         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1221                             pf->offset_loaded, &os->rx_fragments,
1222                             &ns->rx_fragments);
1223         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1224                             pf->offset_loaded, &os->rx_oversize,
1225                             &ns->rx_oversize);
1226         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1227                             pf->offset_loaded, &os->rx_jabber,
1228                             &ns->rx_jabber);
1229         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1230                             I40E_GLPRT_PTC64L(hw->port),
1231                             pf->offset_loaded, &os->tx_size_64,
1232                             &ns->tx_size_64);
1233         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1234                             I40E_GLPRT_PTC127L(hw->port),
1235                             pf->offset_loaded, &os->tx_size_127,
1236                             &ns->tx_size_127);
1237         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1238                             I40E_GLPRT_PTC255L(hw->port),
1239                             pf->offset_loaded, &os->tx_size_255,
1240                             &ns->tx_size_255);
1241         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1242                             I40E_GLPRT_PTC511L(hw->port),
1243                             pf->offset_loaded, &os->tx_size_511,
1244                             &ns->tx_size_511);
1245         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1246                             I40E_GLPRT_PTC1023L(hw->port),
1247                             pf->offset_loaded, &os->tx_size_1023,
1248                             &ns->tx_size_1023);
1249         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1250                             I40E_GLPRT_PTC1522L(hw->port),
1251                             pf->offset_loaded, &os->tx_size_1522,
1252                             &ns->tx_size_1522);
1253         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1254                             I40E_GLPRT_PTC9522L(hw->port),
1255                             pf->offset_loaded, &os->tx_size_big,
1256                             &ns->tx_size_big);
1257         /* GLPRT_MSPDC not supported */
1258         /* GLPRT_XEC not supported */
1259
1260         pf->offset_loaded = true;
1261
1262         if (pf->main_vsi)
1263                 i40e_update_vsi_stats(pf->main_vsi);
1264
1265         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1266                                                 ns->eth.rx_broadcast;
1267         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1268                                                 ns->eth.tx_broadcast;
1269         stats->ibytes   = ns->eth.rx_bytes;
1270         stats->obytes   = ns->eth.tx_bytes;
1271         stats->oerrors  = ns->eth.tx_errors;
1272         stats->imcasts  = ns->eth.rx_multicast;
1273
1274         /* Rx Errors */
1275         stats->ibadcrc  = ns->crc_errors;
1276         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1277                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1278         stats->imissed  = ns->eth.rx_discards;
1279         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1280
1281         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1282         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1283         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1284         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1285         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1286         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1287         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1288                     ns->eth.rx_unknown_protocol);
1289         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1290         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1291         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1292         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1293         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1294         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1295
1296         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1297                     ns->tx_dropped_link_down);
1298         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1299         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1300                     ns->illegal_bytes);
1301         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1302         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1303                     ns->mac_local_faults);
1304         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1305                     ns->mac_remote_faults);
1306         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1307                     ns->rx_length_errors);
1308         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1309         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1310         for (i = 0; i < 8; i++) {
1311                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1312                                 i, ns->priority_xon_rx[i]);
1313                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1314                                 i, ns->priority_xoff_rx[i]);
1315         }
1316         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1317         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1318         for (i = 0; i < 8; i++) {
1319                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1320                                 i, ns->priority_xon_tx[i]);
1321                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1322                                 i, ns->priority_xoff_tx[i]);
1323                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1324                                 i, ns->priority_xon_2_xoff[i]);
1325         }
1326         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1327         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1328         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1329         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1330         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1331         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1332         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1333         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1334         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1335         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1336         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1337         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1338         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1339         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1340         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1341         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1342         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1343         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1344         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1345                         ns->mac_short_packet_dropped);
1346         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1347                     ns->checksum_error);
1348         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1349 }
1350
1351 /* Reset the statistics */
1352 static void
1353 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1354 {
1355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1356
1357         /* It results in reloading the start point of each counter */
1358         pf->offset_loaded = false;
1359 }
1360
1361 static int
1362 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1363                                  __rte_unused uint16_t queue_id,
1364                                  __rte_unused uint8_t stat_idx,
1365                                  __rte_unused uint8_t is_rx)
1366 {
1367         PMD_INIT_FUNC_TRACE();
1368
1369         return -ENOSYS;
1370 }
1371
1372 static void
1373 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1374 {
1375         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1376         struct i40e_vsi *vsi = pf->main_vsi;
1377
1378         dev_info->max_rx_queues = vsi->nb_qps;
1379         dev_info->max_tx_queues = vsi->nb_qps;
1380         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1381         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1382         dev_info->max_mac_addrs = vsi->max_macaddrs;
1383         dev_info->max_vfs = dev->pci_dev->max_vfs;
1384         dev_info->rx_offload_capa =
1385                 DEV_RX_OFFLOAD_VLAN_STRIP |
1386                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1387                 DEV_RX_OFFLOAD_UDP_CKSUM |
1388                 DEV_RX_OFFLOAD_TCP_CKSUM;
1389         dev_info->tx_offload_capa =
1390                 DEV_TX_OFFLOAD_VLAN_INSERT |
1391                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1392                 DEV_TX_OFFLOAD_UDP_CKSUM |
1393                 DEV_TX_OFFLOAD_TCP_CKSUM |
1394                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1395
1396         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1397                 .rx_thresh = {
1398                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1399                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1400                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1401                 },
1402                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1403                 .rx_drop_en = 0,
1404         };
1405
1406         dev_info->default_txconf = (struct rte_eth_txconf) {
1407                 .tx_thresh = {
1408                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1409                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1410                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1411                 },
1412                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1413                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1414                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1415         };
1416
1417 }
1418
1419 static int
1420 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1421 {
1422         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1423         struct i40e_vsi *vsi = pf->main_vsi;
1424         PMD_INIT_FUNC_TRACE();
1425
1426         if (on)
1427                 return i40e_vsi_add_vlan(vsi, vlan_id);
1428         else
1429                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1430 }
1431
1432 static void
1433 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1434                    __rte_unused uint16_t tpid)
1435 {
1436         PMD_INIT_FUNC_TRACE();
1437 }
1438
1439 static void
1440 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1441 {
1442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1443         struct i40e_vsi *vsi = pf->main_vsi;
1444
1445         if (mask & ETH_VLAN_STRIP_MASK) {
1446                 /* Enable or disable VLAN stripping */
1447                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1448                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1449                 else
1450                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1451         }
1452
1453         if (mask & ETH_VLAN_EXTEND_MASK) {
1454                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1455                         i40e_vsi_config_double_vlan(vsi, TRUE);
1456                 else
1457                         i40e_vsi_config_double_vlan(vsi, FALSE);
1458         }
1459 }
1460
1461 static void
1462 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1463                           __rte_unused uint16_t queue,
1464                           __rte_unused int on)
1465 {
1466         PMD_INIT_FUNC_TRACE();
1467 }
1468
1469 static int
1470 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1471 {
1472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473         struct i40e_vsi *vsi = pf->main_vsi;
1474         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1475         struct i40e_vsi_vlan_pvid_info info;
1476
1477         memset(&info, 0, sizeof(info));
1478         info.on = on;
1479         if (info.on)
1480                 info.config.pvid = pvid;
1481         else {
1482                 info.config.reject.tagged =
1483                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1484                 info.config.reject.untagged =
1485                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1486         }
1487
1488         return i40e_vsi_vlan_pvid_set(vsi, &info);
1489 }
1490
1491 static int
1492 i40e_dev_led_on(struct rte_eth_dev *dev)
1493 {
1494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1495         uint32_t mode = i40e_led_get(hw);
1496
1497         if (mode == 0)
1498                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1499
1500         return 0;
1501 }
1502
1503 static int
1504 i40e_dev_led_off(struct rte_eth_dev *dev)
1505 {
1506         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507         uint32_t mode = i40e_led_get(hw);
1508
1509         if (mode != 0)
1510                 i40e_led_set(hw, 0, false);
1511
1512         return 0;
1513 }
1514
1515 static int
1516 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1517                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1518 {
1519         PMD_INIT_FUNC_TRACE();
1520
1521         return -ENOSYS;
1522 }
1523
1524 static int
1525 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1526                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1527 {
1528         PMD_INIT_FUNC_TRACE();
1529
1530         return -ENOSYS;
1531 }
1532
1533 /* Add a MAC address, and update filters */
1534 static void
1535 i40e_macaddr_add(struct rte_eth_dev *dev,
1536                  struct ether_addr *mac_addr,
1537                  __attribute__((unused)) uint32_t index,
1538                  __attribute__((unused)) uint32_t pool)
1539 {
1540         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542         struct i40e_vsi *vsi = pf->main_vsi;
1543         struct ether_addr old_mac;
1544         int ret;
1545
1546         if (!is_valid_assigned_ether_addr(mac_addr)) {
1547                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1548                 return;
1549         }
1550
1551         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1552                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1553                 return;
1554         }
1555
1556         /* Write mac address */
1557         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1558                                         mac_addr->addr_bytes, NULL);
1559         if (ret != I40E_SUCCESS) {
1560                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1561                 return;
1562         }
1563
1564         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1565         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1566                         ETHER_ADDR_LEN);
1567
1568         ret = i40e_vsi_add_mac(vsi, mac_addr);
1569         if (ret != I40E_SUCCESS) {
1570                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1571                 return;
1572         }
1573
1574         ether_addr_copy(mac_addr, &pf->dev_addr);
1575         i40e_vsi_delete_mac(vsi, &old_mac);
1576 }
1577
1578 /* Remove a MAC address, and update filters */
1579 static void
1580 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1581 {
1582         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1583         struct i40e_vsi *vsi = pf->main_vsi;
1584         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1585         struct ether_addr *macaddr;
1586         int ret;
1587         struct i40e_hw *hw =
1588                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589
1590         if (index >= vsi->max_macaddrs)
1591                 return;
1592
1593         macaddr = &(data->mac_addrs[index]);
1594         if (!is_valid_assigned_ether_addr(macaddr))
1595                 return;
1596
1597         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1598                                         hw->mac.perm_addr, NULL);
1599         if (ret != I40E_SUCCESS) {
1600                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1601                 return;
1602         }
1603
1604         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1605
1606         ret = i40e_vsi_delete_mac(vsi, macaddr);
1607         if (ret != I40E_SUCCESS)
1608                 return;
1609
1610         /* Clear device address as it has been removed */
1611         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1612                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1613 }
1614
1615 static int
1616 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1617                          struct rte_eth_rss_reta *reta_conf)
1618 {
1619         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         uint32_t lut, l;
1621         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1622
1623         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1624                 if (i < max)
1625                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1626                 else
1627                         mask = (uint8_t)((reta_conf->mask_hi >>
1628                                                 (i - max)) & 0xF);
1629
1630                 if (!mask)
1631                         continue;
1632
1633                 if (mask == 0xF)
1634                         l = 0;
1635                 else
1636                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1637
1638                 for (j = 0, lut = 0; j < 4; j++) {
1639                         if (mask & (0x1 << j))
1640                                 lut |= reta_conf->reta[i + j] << (8 * j);
1641                         else
1642                                 lut |= l & (0xFF << (8 * j));
1643                 }
1644                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1645         }
1646
1647         return 0;
1648 }
1649
1650 static int
1651 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1652                         struct rte_eth_rss_reta *reta_conf)
1653 {
1654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         uint32_t lut;
1656         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1657
1658         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1659                 if (i < max)
1660                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1661                 else
1662                         mask = (uint8_t)((reta_conf->mask_hi >>
1663                                                 (i - max)) & 0xF);
1664
1665                 if (!mask)
1666                         continue;
1667
1668                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1669                 for (j = 0; j < 4; j++) {
1670                         if (mask & (0x1 << j))
1671                                 reta_conf->reta[i + j] =
1672                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 /**
1680  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1681  * @hw:   pointer to the HW structure
1682  * @mem:  pointer to mem struct to fill out
1683  * @size: size of memory requested
1684  * @alignment: what to align the allocation to
1685  **/
1686 enum i40e_status_code
1687 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1688                         struct i40e_dma_mem *mem,
1689                         u64 size,
1690                         u32 alignment)
1691 {
1692         static uint64_t id = 0;
1693         const struct rte_memzone *mz = NULL;
1694         char z_name[RTE_MEMZONE_NAMESIZE];
1695
1696         if (!mem)
1697                 return I40E_ERR_PARAM;
1698
1699         id++;
1700         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1701 #ifdef RTE_LIBRTE_XEN_DOM0
1702         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1703                                                         RTE_PGSIZE_2M);
1704 #else
1705         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1706 #endif
1707         if (!mz)
1708                 return I40E_ERR_NO_MEMORY;
1709
1710         mem->id = id;
1711         mem->size = size;
1712         mem->va = mz->addr;
1713 #ifdef RTE_LIBRTE_XEN_DOM0
1714         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1715 #else
1716         mem->pa = mz->phys_addr;
1717 #endif
1718
1719         return I40E_SUCCESS;
1720 }
1721
1722 /**
1723  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1724  * @hw:   pointer to the HW structure
1725  * @mem:  ptr to mem struct to free
1726  **/
1727 enum i40e_status_code
1728 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1729                     struct i40e_dma_mem *mem)
1730 {
1731         if (!mem || !mem->va)
1732                 return I40E_ERR_PARAM;
1733
1734         mem->va = NULL;
1735         mem->pa = (u64)0;
1736
1737         return I40E_SUCCESS;
1738 }
1739
1740 /**
1741  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1742  * @hw:   pointer to the HW structure
1743  * @mem:  pointer to mem struct to fill out
1744  * @size: size of memory requested
1745  **/
1746 enum i40e_status_code
1747 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1748                          struct i40e_virt_mem *mem,
1749                          u32 size)
1750 {
1751         if (!mem)
1752                 return I40E_ERR_PARAM;
1753
1754         mem->size = size;
1755         mem->va = rte_zmalloc("i40e", size, 0);
1756
1757         if (mem->va)
1758                 return I40E_SUCCESS;
1759         else
1760                 return I40E_ERR_NO_MEMORY;
1761 }
1762
1763 /**
1764  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1765  * @hw:   pointer to the HW structure
1766  * @mem:  pointer to mem struct to free
1767  **/
1768 enum i40e_status_code
1769 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1770                      struct i40e_virt_mem *mem)
1771 {
1772         if (!mem)
1773                 return I40E_ERR_PARAM;
1774
1775         rte_free(mem->va);
1776         mem->va = NULL;
1777
1778         return I40E_SUCCESS;
1779 }
1780
1781 void
1782 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1783 {
1784         rte_spinlock_init(&sp->spinlock);
1785 }
1786
1787 void
1788 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1789 {
1790         rte_spinlock_lock(&sp->spinlock);
1791 }
1792
1793 void
1794 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1795 {
1796         rte_spinlock_unlock(&sp->spinlock);
1797 }
1798
1799 void
1800 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1801 {
1802         return;
1803 }
1804
1805 /**
1806  * Get the hardware capabilities, which will be parsed
1807  * and saved into struct i40e_hw.
1808  */
1809 static int
1810 i40e_get_cap(struct i40e_hw *hw)
1811 {
1812         struct i40e_aqc_list_capabilities_element_resp *buf;
1813         uint16_t len, size = 0;
1814         int ret;
1815
1816         /* Calculate a huge enough buff for saving response data temporarily */
1817         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1818                                                 I40E_MAX_CAP_ELE_NUM;
1819         buf = rte_zmalloc("i40e", len, 0);
1820         if (!buf) {
1821                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1822                 return I40E_ERR_NO_MEMORY;
1823         }
1824
1825         /* Get, parse the capabilities and save it to hw */
1826         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1827                         i40e_aqc_opc_list_func_capabilities, NULL);
1828         if (ret != I40E_SUCCESS)
1829                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1830
1831         /* Free the temporary buffer after being used */
1832         rte_free(buf);
1833
1834         return ret;
1835 }
1836
1837 static int
1838 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1839 {
1840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1841         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1842         uint16_t sum_queues = 0, sum_vsis;
1843
1844         /* First check if FW support SRIOV */
1845         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1846                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1847                 return -EINVAL;
1848         }
1849
1850         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1851         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1852         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1853         /* Allocate queues for pf */
1854         if (hw->func_caps.rss) {
1855                 pf->flags |= I40E_FLAG_RSS;
1856                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1857                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1858                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1859         } else
1860                 pf->lan_nb_qps = 1;
1861         sum_queues = pf->lan_nb_qps;
1862         /* Default VSI is not counted in */
1863         sum_vsis = 0;
1864         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1865
1866         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1867                 pf->flags |= I40E_FLAG_SRIOV;
1868                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1869                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1870                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1871                                      "max supported %u.",
1872                                      dev->pci_dev->max_vfs,
1873                                      hw->func_caps.num_vfs);
1874                         return -EINVAL;
1875                 }
1876                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1877                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1878                                      "max support %u queues.",
1879                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1880                         return -EINVAL;
1881                 }
1882                 pf->vf_num = dev->pci_dev->max_vfs;
1883                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1884                 sum_vsis   += pf->vf_num;
1885                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1886                              pf->vf_num, pf->vf_nb_qps);
1887         } else
1888                 pf->vf_num = 0;
1889
1890         if (hw->func_caps.vmdq) {
1891                 pf->flags |= I40E_FLAG_VMDQ;
1892                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1893                 sum_queues += pf->vmdq_nb_qps;
1894                 sum_vsis += 1;
1895                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1896         }
1897
1898         if (hw->func_caps.fd) {
1899                 pf->flags |= I40E_FLAG_FDIR;
1900                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1901                 /**
1902                  * Each flow director consumes one VSI and one queue,
1903                  * but can't calculate out predictably here.
1904                  */
1905         }
1906
1907         if (sum_vsis > pf->max_num_vsi ||
1908                 sum_queues > hw->func_caps.num_rx_qp) {
1909                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1910                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1911                              pf->max_num_vsi, sum_vsis);
1912                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1913                              hw->func_caps.num_rx_qp, sum_queues);
1914                 return -EINVAL;
1915         }
1916
1917         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1918          * cause */
1919         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1920                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1921                              sum_vsis, hw->func_caps.num_msix_vectors);
1922                 return -EINVAL;
1923         }
1924         return I40E_SUCCESS;
1925 }
1926
1927 static int
1928 i40e_pf_get_switch_config(struct i40e_pf *pf)
1929 {
1930         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1931         struct i40e_aqc_get_switch_config_resp *switch_config;
1932         struct i40e_aqc_switch_config_element_resp *element;
1933         uint16_t start_seid = 0, num_reported;
1934         int ret;
1935
1936         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1937                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1938         if (!switch_config) {
1939                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1940                 return -ENOMEM;
1941         }
1942
1943         /* Get the switch configurations */
1944         ret = i40e_aq_get_switch_config(hw, switch_config,
1945                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1946         if (ret != I40E_SUCCESS) {
1947                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1948                 goto fail;
1949         }
1950         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1951         if (num_reported != 1) { /* The number should be 1 */
1952                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1953                 goto fail;
1954         }
1955
1956         /* Parse the switch configuration elements */
1957         element = &(switch_config->element[0]);
1958         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1959                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1960                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1961         } else
1962                 PMD_DRV_LOG(INFO, "Unknown element type");
1963
1964 fail:
1965         rte_free(switch_config);
1966
1967         return ret;
1968 }
1969
1970 static int
1971 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1972                         uint32_t num)
1973 {
1974         struct pool_entry *entry;
1975
1976         if (pool == NULL || num == 0)
1977                 return -EINVAL;
1978
1979         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1980         if (entry == NULL) {
1981                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1982                 return -ENOMEM;
1983         }
1984
1985         /* queue heap initialize */
1986         pool->num_free = num;
1987         pool->num_alloc = 0;
1988         pool->base = base;
1989         LIST_INIT(&pool->alloc_list);
1990         LIST_INIT(&pool->free_list);
1991
1992         /* Initialize element  */
1993         entry->base = 0;
1994         entry->len = num;
1995
1996         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1997         return 0;
1998 }
1999
2000 static void
2001 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2002 {
2003         struct pool_entry *entry;
2004
2005         if (pool == NULL)
2006                 return;
2007
2008         LIST_FOREACH(entry, &pool->alloc_list, next) {
2009                 LIST_REMOVE(entry, next);
2010                 rte_free(entry);
2011         }
2012
2013         LIST_FOREACH(entry, &pool->free_list, next) {
2014                 LIST_REMOVE(entry, next);
2015                 rte_free(entry);
2016         }
2017
2018         pool->num_free = 0;
2019         pool->num_alloc = 0;
2020         pool->base = 0;
2021         LIST_INIT(&pool->alloc_list);
2022         LIST_INIT(&pool->free_list);
2023 }
2024
2025 static int
2026 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2027                        uint32_t base)
2028 {
2029         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2030         uint32_t pool_offset;
2031         int insert;
2032
2033         if (pool == NULL) {
2034                 PMD_DRV_LOG(ERR, "Invalid parameter");
2035                 return -EINVAL;
2036         }
2037
2038         pool_offset = base - pool->base;
2039         /* Lookup in alloc list */
2040         LIST_FOREACH(entry, &pool->alloc_list, next) {
2041                 if (entry->base == pool_offset) {
2042                         valid_entry = entry;
2043                         LIST_REMOVE(entry, next);
2044                         break;
2045                 }
2046         }
2047
2048         /* Not find, return */
2049         if (valid_entry == NULL) {
2050                 PMD_DRV_LOG(ERR, "Failed to find entry");
2051                 return -EINVAL;
2052         }
2053
2054         /**
2055          * Found it, move it to free list  and try to merge.
2056          * In order to make merge easier, always sort it by qbase.
2057          * Find adjacent prev and last entries.
2058          */
2059         prev = next = NULL;
2060         LIST_FOREACH(entry, &pool->free_list, next) {
2061                 if (entry->base > valid_entry->base) {
2062                         next = entry;
2063                         break;
2064                 }
2065                 prev = entry;
2066         }
2067
2068         insert = 0;
2069         /* Try to merge with next one*/
2070         if (next != NULL) {
2071                 /* Merge with next one */
2072                 if (valid_entry->base + valid_entry->len == next->base) {
2073                         next->base = valid_entry->base;
2074                         next->len += valid_entry->len;
2075                         rte_free(valid_entry);
2076                         valid_entry = next;
2077                         insert = 1;
2078                 }
2079         }
2080
2081         if (prev != NULL) {
2082                 /* Merge with previous one */
2083                 if (prev->base + prev->len == valid_entry->base) {
2084                         prev->len += valid_entry->len;
2085                         /* If it merge with next one, remove next node */
2086                         if (insert == 1) {
2087                                 LIST_REMOVE(valid_entry, next);
2088                                 rte_free(valid_entry);
2089                         } else {
2090                                 rte_free(valid_entry);
2091                                 insert = 1;
2092                         }
2093                 }
2094         }
2095
2096         /* Not find any entry to merge, insert */
2097         if (insert == 0) {
2098                 if (prev != NULL)
2099                         LIST_INSERT_AFTER(prev, valid_entry, next);
2100                 else if (next != NULL)
2101                         LIST_INSERT_BEFORE(next, valid_entry, next);
2102                 else /* It's empty list, insert to head */
2103                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2104         }
2105
2106         pool->num_free += valid_entry->len;
2107         pool->num_alloc -= valid_entry->len;
2108
2109         return 0;
2110 }
2111
2112 static int
2113 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2114                        uint16_t num)
2115 {
2116         struct pool_entry *entry, *valid_entry;
2117
2118         if (pool == NULL || num == 0) {
2119                 PMD_DRV_LOG(ERR, "Invalid parameter");
2120                 return -EINVAL;
2121         }
2122
2123         if (pool->num_free < num) {
2124                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2125                             num, pool->num_free);
2126                 return -ENOMEM;
2127         }
2128
2129         valid_entry = NULL;
2130         /* Lookup  in free list and find most fit one */
2131         LIST_FOREACH(entry, &pool->free_list, next) {
2132                 if (entry->len >= num) {
2133                         /* Find best one */
2134                         if (entry->len == num) {
2135                                 valid_entry = entry;
2136                                 break;
2137                         }
2138                         if (valid_entry == NULL || valid_entry->len > entry->len)
2139                                 valid_entry = entry;
2140                 }
2141         }
2142
2143         /* Not find one to satisfy the request, return */
2144         if (valid_entry == NULL) {
2145                 PMD_DRV_LOG(ERR, "No valid entry found");
2146                 return -ENOMEM;
2147         }
2148         /**
2149          * The entry have equal queue number as requested,
2150          * remove it from alloc_list.
2151          */
2152         if (valid_entry->len == num) {
2153                 LIST_REMOVE(valid_entry, next);
2154         } else {
2155                 /**
2156                  * The entry have more numbers than requested,
2157                  * create a new entry for alloc_list and minus its
2158                  * queue base and number in free_list.
2159                  */
2160                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2161                 if (entry == NULL) {
2162                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2163                                     "resource pool");
2164                         return -ENOMEM;
2165                 }
2166                 entry->base = valid_entry->base;
2167                 entry->len = num;
2168                 valid_entry->base += num;
2169                 valid_entry->len -= num;
2170                 valid_entry = entry;
2171         }
2172
2173         /* Insert it into alloc list, not sorted */
2174         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2175
2176         pool->num_free -= valid_entry->len;
2177         pool->num_alloc += valid_entry->len;
2178
2179         return (valid_entry->base + pool->base);
2180 }
2181
2182 /**
2183  * bitmap_is_subset - Check whether src2 is subset of src1
2184  **/
2185 static inline int
2186 bitmap_is_subset(uint8_t src1, uint8_t src2)
2187 {
2188         return !((src1 ^ src2) & src2);
2189 }
2190
2191 static int
2192 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2193 {
2194         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2195
2196         /* If DCB is not supported, only default TC is supported */
2197         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2198                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2199                 return -EINVAL;
2200         }
2201
2202         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2203                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2204                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2205                             enabled_tcmap);
2206                 return -EINVAL;
2207         }
2208         return I40E_SUCCESS;
2209 }
2210
2211 int
2212 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2213                                 struct i40e_vsi_vlan_pvid_info *info)
2214 {
2215         struct i40e_hw *hw;
2216         struct i40e_vsi_context ctxt;
2217         uint8_t vlan_flags = 0;
2218         int ret;
2219
2220         if (vsi == NULL || info == NULL) {
2221                 PMD_DRV_LOG(ERR, "invalid parameters");
2222                 return I40E_ERR_PARAM;
2223         }
2224
2225         if (info->on) {
2226                 vsi->info.pvid = info->config.pvid;
2227                 /**
2228                  * If insert pvid is enabled, only tagged pkts are
2229                  * allowed to be sent out.
2230                  */
2231                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2232                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2233         } else {
2234                 vsi->info.pvid = 0;
2235                 if (info->config.reject.tagged == 0)
2236                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2237
2238                 if (info->config.reject.untagged == 0)
2239                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2240         }
2241         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2242                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2243         vsi->info.port_vlan_flags |= vlan_flags;
2244         vsi->info.valid_sections =
2245                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2246         memset(&ctxt, 0, sizeof(ctxt));
2247         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2248         ctxt.seid = vsi->seid;
2249
2250         hw = I40E_VSI_TO_HW(vsi);
2251         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2252         if (ret != I40E_SUCCESS)
2253                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2254
2255         return ret;
2256 }
2257
2258 static int
2259 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2260 {
2261         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2262         int i, ret;
2263         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2264
2265         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2266         if (ret != I40E_SUCCESS)
2267                 return ret;
2268
2269         if (!vsi->seid) {
2270                 PMD_DRV_LOG(ERR, "seid not valid");
2271                 return -EINVAL;
2272         }
2273
2274         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2275         tc_bw_data.tc_valid_bits = enabled_tcmap;
2276         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2277                 tc_bw_data.tc_bw_credits[i] =
2278                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2279
2280         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2281         if (ret != I40E_SUCCESS) {
2282                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2283                 return ret;
2284         }
2285
2286         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2287                                         sizeof(vsi->info.qs_handle));
2288         return I40E_SUCCESS;
2289 }
2290
2291 static int
2292 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2293                                  struct i40e_aqc_vsi_properties_data *info,
2294                                  uint8_t enabled_tcmap)
2295 {
2296         int ret, total_tc = 0, i;
2297         uint16_t qpnum_per_tc, bsf, qp_idx;
2298
2299         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2300         if (ret != I40E_SUCCESS)
2301                 return ret;
2302
2303         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2304                 if (enabled_tcmap & (1 << i))
2305                         total_tc++;
2306         vsi->enabled_tc = enabled_tcmap;
2307
2308         /* Number of queues per enabled TC */
2309         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2310         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2311         bsf = rte_bsf32(qpnum_per_tc);
2312
2313         /* Adjust the queue number to actual queues that can be applied */
2314         vsi->nb_qps = qpnum_per_tc * total_tc;
2315
2316         /**
2317          * Configure TC and queue mapping parameters, for enabled TC,
2318          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2319          * default queue will serve it.
2320          */
2321         qp_idx = 0;
2322         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2323                 if (vsi->enabled_tc & (1 << i)) {
2324                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2325                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2326                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2327                         qp_idx += qpnum_per_tc;
2328                 } else
2329                         info->tc_mapping[i] = 0;
2330         }
2331
2332         /* Associate queue number with VSI */
2333         if (vsi->type == I40E_VSI_SRIOV) {
2334                 info->mapping_flags |=
2335                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2336                 for (i = 0; i < vsi->nb_qps; i++)
2337                         info->queue_mapping[i] =
2338                                 rte_cpu_to_le_16(vsi->base_queue + i);
2339         } else {
2340                 info->mapping_flags |=
2341                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2342                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2343         }
2344         info->valid_sections =
2345                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2346
2347         return I40E_SUCCESS;
2348 }
2349
2350 static int
2351 i40e_veb_release(struct i40e_veb *veb)
2352 {
2353         struct i40e_vsi *vsi;
2354         struct i40e_hw *hw;
2355
2356         if (veb == NULL || veb->associate_vsi == NULL)
2357                 return -EINVAL;
2358
2359         if (!TAILQ_EMPTY(&veb->head)) {
2360                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2361                 return -EACCES;
2362         }
2363
2364         vsi = veb->associate_vsi;
2365         hw = I40E_VSI_TO_HW(vsi);
2366
2367         vsi->uplink_seid = veb->uplink_seid;
2368         i40e_aq_delete_element(hw, veb->seid, NULL);
2369         rte_free(veb);
2370         vsi->veb = NULL;
2371         return I40E_SUCCESS;
2372 }
2373
2374 /* Setup a veb */
2375 static struct i40e_veb *
2376 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2377 {
2378         struct i40e_veb *veb;
2379         int ret;
2380         struct i40e_hw *hw;
2381
2382         if (NULL == pf || vsi == NULL) {
2383                 PMD_DRV_LOG(ERR, "veb setup failed, "
2384                             "associated VSI shouldn't null");
2385                 return NULL;
2386         }
2387         hw = I40E_PF_TO_HW(pf);
2388
2389         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2390         if (!veb) {
2391                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2392                 goto fail;
2393         }
2394
2395         veb->associate_vsi = vsi;
2396         TAILQ_INIT(&veb->head);
2397         veb->uplink_seid = vsi->uplink_seid;
2398
2399         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2400                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2401
2402         if (ret != I40E_SUCCESS) {
2403                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2404                             hw->aq.asq_last_status);
2405                 goto fail;
2406         }
2407
2408         /* get statistics index */
2409         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2410                                 &veb->stats_idx, NULL, NULL, NULL);
2411         if (ret != I40E_SUCCESS) {
2412                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2413                             hw->aq.asq_last_status);
2414                 goto fail;
2415         }
2416
2417         /* Get VEB bandwidth, to be implemented */
2418         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2419         vsi->uplink_seid = veb->seid;
2420
2421         return veb;
2422 fail:
2423         rte_free(veb);
2424         return NULL;
2425 }
2426
2427 int
2428 i40e_vsi_release(struct i40e_vsi *vsi)
2429 {
2430         struct i40e_pf *pf;
2431         struct i40e_hw *hw;
2432         struct i40e_vsi_list *vsi_list;
2433         int ret;
2434         struct i40e_mac_filter *f;
2435
2436         if (!vsi)
2437                 return I40E_SUCCESS;
2438
2439         pf = I40E_VSI_TO_PF(vsi);
2440         hw = I40E_VSI_TO_HW(vsi);
2441
2442         /* VSI has child to attach, release child first */
2443         if (vsi->veb) {
2444                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2445                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2446                                 return -1;
2447                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2448                 }
2449                 i40e_veb_release(vsi->veb);
2450         }
2451
2452         /* Remove all macvlan filters of the VSI */
2453         i40e_vsi_remove_all_macvlan_filter(vsi);
2454         TAILQ_FOREACH(f, &vsi->mac_list, next)
2455                 rte_free(f);
2456
2457         if (vsi->type != I40E_VSI_MAIN) {
2458                 /* Remove vsi from parent's sibling list */
2459                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2460                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2461                         return I40E_ERR_PARAM;
2462                 }
2463                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2464                                 &vsi->sib_vsi_list, list);
2465
2466                 /* Remove all switch element of the VSI */
2467                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2468                 if (ret != I40E_SUCCESS)
2469                         PMD_DRV_LOG(ERR, "Failed to delete element");
2470         }
2471         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2472
2473         if (vsi->type != I40E_VSI_SRIOV)
2474                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2475         rte_free(vsi);
2476
2477         return I40E_SUCCESS;
2478 }
2479
2480 static int
2481 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2482 {
2483         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2484         struct i40e_aqc_remove_macvlan_element_data def_filter;
2485         int ret;
2486
2487         if (vsi->type != I40E_VSI_MAIN)
2488                 return I40E_ERR_CONFIG;
2489         memset(&def_filter, 0, sizeof(def_filter));
2490         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2491                                         ETH_ADDR_LEN);
2492         def_filter.vlan_tag = 0;
2493         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2494                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2495         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2496         if (ret != I40E_SUCCESS) {
2497                 struct i40e_mac_filter *f;
2498
2499                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2500                             "macvlan filter");
2501                 /* It needs to add the permanent mac into mac list */
2502                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2503                 if (f == NULL) {
2504                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2505                         return I40E_ERR_NO_MEMORY;
2506                 }
2507                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2508                                 ETH_ADDR_LEN);
2509                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2510                 vsi->mac_num++;
2511
2512                 return ret;
2513         }
2514
2515         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2516 }
2517
2518 static int
2519 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2520 {
2521         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2522         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2523         struct i40e_hw *hw = &vsi->adapter->hw;
2524         i40e_status ret;
2525         int i;
2526
2527         memset(&bw_config, 0, sizeof(bw_config));
2528         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2529         if (ret != I40E_SUCCESS) {
2530                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2531                             hw->aq.asq_last_status);
2532                 return ret;
2533         }
2534
2535         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2536         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2537                                         &ets_sla_config, NULL);
2538         if (ret != I40E_SUCCESS) {
2539                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2540                             "configuration %u", hw->aq.asq_last_status);
2541                 return ret;
2542         }
2543
2544         /* Not store the info yet, just print out */
2545         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2546         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2547         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2548                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2549                             ets_sla_config.share_credits[i]);
2550                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2551                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2552                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2553                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2554                             (i * 4));
2555         }
2556
2557         return 0;
2558 }
2559
2560 /* Setup a VSI */
2561 struct i40e_vsi *
2562 i40e_vsi_setup(struct i40e_pf *pf,
2563                enum i40e_vsi_type type,
2564                struct i40e_vsi *uplink_vsi,
2565                uint16_t user_param)
2566 {
2567         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2568         struct i40e_vsi *vsi;
2569         int ret;
2570         struct i40e_vsi_context ctxt;
2571         struct ether_addr broadcast =
2572                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2573
2574         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2575                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2576                             "VSI link shouldn't be NULL");
2577                 return NULL;
2578         }
2579
2580         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2581                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2582                             "uplink VSI should be NULL");
2583                 return NULL;
2584         }
2585
2586         /* If uplink vsi didn't setup VEB, create one first */
2587         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2588                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2589
2590                 if (NULL == uplink_vsi->veb) {
2591                         PMD_DRV_LOG(ERR, "VEB setup failed");
2592                         return NULL;
2593                 }
2594         }
2595
2596         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2597         if (!vsi) {
2598                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2599                 return NULL;
2600         }
2601         TAILQ_INIT(&vsi->mac_list);
2602         vsi->type = type;
2603         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2604         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2605         vsi->parent_vsi = uplink_vsi;
2606         vsi->user_param = user_param;
2607         /* Allocate queues */
2608         switch (vsi->type) {
2609         case I40E_VSI_MAIN  :
2610                 vsi->nb_qps = pf->lan_nb_qps;
2611                 break;
2612         case I40E_VSI_SRIOV :
2613                 vsi->nb_qps = pf->vf_nb_qps;
2614                 break;
2615         default:
2616                 goto fail_mem;
2617         }
2618         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2619         if (ret < 0) {
2620                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2621                                 vsi->seid, ret);
2622                 goto fail_mem;
2623         }
2624         vsi->base_queue = ret;
2625
2626         /* VF has MSIX interrupt in VF range, don't allocate here */
2627         if (type != I40E_VSI_SRIOV) {
2628                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2629                 if (ret < 0) {
2630                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2631                         goto fail_queue_alloc;
2632                 }
2633                 vsi->msix_intr = ret;
2634         } else
2635                 vsi->msix_intr = 0;
2636         /* Add VSI */
2637         if (type == I40E_VSI_MAIN) {
2638                 /* For main VSI, no need to add since it's default one */
2639                 vsi->uplink_seid = pf->mac_seid;
2640                 vsi->seid = pf->main_vsi_seid;
2641                 /* Bind queues with specific MSIX interrupt */
2642                 /**
2643                  * Needs 2 interrupt at least, one for misc cause which will
2644                  * enabled from OS side, Another for queues binding the
2645                  * interrupt from device side only.
2646                  */
2647
2648                 /* Get default VSI parameters from hardware */
2649                 memset(&ctxt, 0, sizeof(ctxt));
2650                 ctxt.seid = vsi->seid;
2651                 ctxt.pf_num = hw->pf_id;
2652                 ctxt.uplink_seid = vsi->uplink_seid;
2653                 ctxt.vf_num = 0;
2654                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2655                 if (ret != I40E_SUCCESS) {
2656                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2657                         goto fail_msix_alloc;
2658                 }
2659                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2660                         sizeof(struct i40e_aqc_vsi_properties_data));
2661                 vsi->vsi_id = ctxt.vsi_number;
2662                 vsi->info.valid_sections = 0;
2663
2664                 /* Configure tc, enabled TC0 only */
2665                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2666                         I40E_SUCCESS) {
2667                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2668                         goto fail_msix_alloc;
2669                 }
2670
2671                 /* TC, queue mapping */
2672                 memset(&ctxt, 0, sizeof(ctxt));
2673                 vsi->info.valid_sections |=
2674                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2675                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2676                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2677                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2678                         sizeof(struct i40e_aqc_vsi_properties_data));
2679                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2680                                                 I40E_DEFAULT_TCMAP);
2681                 if (ret != I40E_SUCCESS) {
2682                         PMD_DRV_LOG(ERR, "Failed to configure "
2683                                     "TC queue mapping");
2684                         goto fail_msix_alloc;
2685                 }
2686                 ctxt.seid = vsi->seid;
2687                 ctxt.pf_num = hw->pf_id;
2688                 ctxt.uplink_seid = vsi->uplink_seid;
2689                 ctxt.vf_num = 0;
2690
2691                 /* Update VSI parameters */
2692                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2693                 if (ret != I40E_SUCCESS) {
2694                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2695                         goto fail_msix_alloc;
2696                 }
2697
2698                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2699                                                 sizeof(vsi->info.tc_mapping));
2700                 (void)rte_memcpy(&vsi->info.queue_mapping,
2701                                 &ctxt.info.queue_mapping,
2702                         sizeof(vsi->info.queue_mapping));
2703                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2704                 vsi->info.valid_sections = 0;
2705
2706                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2707                                 ETH_ADDR_LEN);
2708
2709                 /**
2710                  * Updating default filter settings are necessary to prevent
2711                  * reception of tagged packets.
2712                  * Some old firmware configurations load a default macvlan
2713                  * filter which accepts both tagged and untagged packets.
2714                  * The updating is to use a normal filter instead if needed.
2715                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2716                  * The firmware with correct configurations load the default
2717                  * macvlan filter which is expected and cannot be removed.
2718                  */
2719                 i40e_update_default_filter_setting(vsi);
2720         } else if (type == I40E_VSI_SRIOV) {
2721                 memset(&ctxt, 0, sizeof(ctxt));
2722                 /**
2723                  * For other VSI, the uplink_seid equals to uplink VSI's
2724                  * uplink_seid since they share same VEB
2725                  */
2726                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2727                 ctxt.pf_num = hw->pf_id;
2728                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2729                 ctxt.uplink_seid = vsi->uplink_seid;
2730                 ctxt.connection_type = 0x1;
2731                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2732
2733                 /* Configure switch ID */
2734                 ctxt.info.valid_sections |=
2735                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2736                 ctxt.info.switch_id =
2737                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2738                 /* Configure port/vlan */
2739                 ctxt.info.valid_sections |=
2740                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2741                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2742                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2743                                                 I40E_DEFAULT_TCMAP);
2744                 if (ret != I40E_SUCCESS) {
2745                         PMD_DRV_LOG(ERR, "Failed to configure "
2746                                     "TC queue mapping");
2747                         goto fail_msix_alloc;
2748                 }
2749                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2750                 ctxt.info.valid_sections |=
2751                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2752                 /**
2753                  * Since VSI is not created yet, only configure parameter,
2754                  * will add vsi below.
2755                  */
2756         }
2757         else {
2758                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2759                 goto fail_msix_alloc;
2760         }
2761
2762         if (vsi->type != I40E_VSI_MAIN) {
2763                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2764                 if (ret) {
2765                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2766                                     hw->aq.asq_last_status);
2767                         goto fail_msix_alloc;
2768                 }
2769                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2770                 vsi->info.valid_sections = 0;
2771                 vsi->seid = ctxt.seid;
2772                 vsi->vsi_id = ctxt.vsi_number;
2773                 vsi->sib_vsi_list.vsi = vsi;
2774                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2775                                 &vsi->sib_vsi_list, list);
2776         }
2777
2778         /* MAC/VLAN configuration */
2779         ret = i40e_vsi_add_mac(vsi, &broadcast);
2780         if (ret != I40E_SUCCESS) {
2781                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2782                 goto fail_msix_alloc;
2783         }
2784
2785         /* Get VSI BW information */
2786         i40e_vsi_dump_bw_config(vsi);
2787         return vsi;
2788 fail_msix_alloc:
2789         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2790 fail_queue_alloc:
2791         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2792 fail_mem:
2793         rte_free(vsi);
2794         return NULL;
2795 }
2796
2797 /* Configure vlan stripping on or off */
2798 int
2799 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2800 {
2801         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2802         struct i40e_vsi_context ctxt;
2803         uint8_t vlan_flags;
2804         int ret = I40E_SUCCESS;
2805
2806         /* Check if it has been already on or off */
2807         if (vsi->info.valid_sections &
2808                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2809                 if (on) {
2810                         if ((vsi->info.port_vlan_flags &
2811                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2812                                 return 0; /* already on */
2813                 } else {
2814                         if ((vsi->info.port_vlan_flags &
2815                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2816                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2817                                 return 0; /* already off */
2818                 }
2819         }
2820
2821         if (on)
2822                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2823         else
2824                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2825         vsi->info.valid_sections =
2826                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2827         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2828         vsi->info.port_vlan_flags |= vlan_flags;
2829         ctxt.seid = vsi->seid;
2830         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2831         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2832         if (ret)
2833                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2834                             on ? "enable" : "disable");
2835
2836         return ret;
2837 }
2838
2839 static int
2840 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2841 {
2842         struct rte_eth_dev_data *data = dev->data;
2843         int ret;
2844
2845         /* Apply vlan offload setting */
2846         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2847
2848         /* Apply double-vlan setting, not implemented yet */
2849
2850         /* Apply pvid setting */
2851         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2852                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2853         if (ret)
2854                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2855
2856         return ret;
2857 }
2858
2859 static int
2860 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2861 {
2862         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2863
2864         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2865 }
2866
2867 static int
2868 i40e_update_flow_control(struct i40e_hw *hw)
2869 {
2870 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2871         struct i40e_link_status link_status;
2872         uint32_t rxfc = 0, txfc = 0, reg;
2873         uint8_t an_info;
2874         int ret;
2875
2876         memset(&link_status, 0, sizeof(link_status));
2877         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2878         if (ret != I40E_SUCCESS) {
2879                 PMD_DRV_LOG(ERR, "Failed to get link status information");
2880                 goto write_reg; /* Disable flow control */
2881         }
2882
2883         an_info = hw->phy.link_info.an_info;
2884         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2885                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2886                 ret = I40E_ERR_NOT_READY;
2887                 goto write_reg; /* Disable flow control */
2888         }
2889         /**
2890          * If link auto negotiation is enabled, flow control needs to
2891          * be configured according to it
2892          */
2893         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2894         case I40E_LINK_PAUSE_RXTX:
2895                 rxfc = 1;
2896                 txfc = 1;
2897                 hw->fc.current_mode = I40E_FC_FULL;
2898                 break;
2899         case I40E_AQ_LINK_PAUSE_RX:
2900                 rxfc = 1;
2901                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2902                 break;
2903         case I40E_AQ_LINK_PAUSE_TX:
2904                 txfc = 1;
2905                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2906                 break;
2907         default:
2908                 hw->fc.current_mode = I40E_FC_NONE;
2909                 break;
2910         }
2911
2912 write_reg:
2913         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2914                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2915         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2916         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2917         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2918         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2919
2920         return ret;
2921 }
2922
2923 /* PF setup */
2924 static int
2925 i40e_pf_setup(struct i40e_pf *pf)
2926 {
2927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2928         struct i40e_filter_control_settings settings;
2929         struct rte_eth_dev_data *dev_data = pf->dev_data;
2930         struct i40e_vsi *vsi;
2931         int ret;
2932
2933         /* Clear all stats counters */
2934         pf->offset_loaded = FALSE;
2935         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2936         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2937
2938         ret = i40e_pf_get_switch_config(pf);
2939         if (ret != I40E_SUCCESS) {
2940                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2941                 return ret;
2942         }
2943
2944         /* VSI setup */
2945         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2946         if (!vsi) {
2947                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2948                 return I40E_ERR_NOT_READY;
2949         }
2950         pf->main_vsi = vsi;
2951         dev_data->nb_rx_queues = vsi->nb_qps;
2952         dev_data->nb_tx_queues = vsi->nb_qps;
2953
2954         /* Configure filter control */
2955         memset(&settings, 0, sizeof(settings));
2956         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2957         /* Enable ethtype and macvlan filters */
2958         settings.enable_ethtype = TRUE;
2959         settings.enable_macvlan = TRUE;
2960         ret = i40e_set_filter_control(hw, &settings);
2961         if (ret)
2962                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2963                                                                 ret);
2964
2965         /* Update flow control according to the auto negotiation */
2966         i40e_update_flow_control(hw);
2967
2968         return I40E_SUCCESS;
2969 }
2970
2971 int
2972 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2973 {
2974         uint32_t reg;
2975         uint16_t j;
2976
2977         /**
2978          * Set or clear TX Queue Disable flags,
2979          * which is required by hardware.
2980          */
2981         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2982         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2983
2984         /* Wait until the request is finished */
2985         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2986                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2987                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2988                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2989                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2990                                                         & 0x1))) {
2991                         break;
2992                 }
2993         }
2994         if (on) {
2995                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2996                         return I40E_SUCCESS; /* already on, skip next steps */
2997
2998                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2999                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3000         } else {
3001                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3002                         return I40E_SUCCESS; /* already off, skip next steps */
3003                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3004         }
3005         /* Write the register */
3006         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3007         /* Check the result */
3008         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3009                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3010                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3011                 if (on) {
3012                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3013                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3014                                 break;
3015                 } else {
3016                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3017                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3018                                 break;
3019                 }
3020         }
3021         /* Check if it is timeout */
3022         if (j >= I40E_CHK_Q_ENA_COUNT) {
3023                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3024                             (on ? "enable" : "disable"), q_idx);
3025                 return I40E_ERR_TIMEOUT;
3026         }
3027
3028         return I40E_SUCCESS;
3029 }
3030
3031 /* Swith on or off the tx queues */
3032 static int
3033 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3034 {
3035         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3036         struct i40e_tx_queue *txq;
3037         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3038         uint16_t i;
3039         int ret;
3040
3041         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3042                 txq = dev_data->tx_queues[i];
3043                 /* Don't operate the queue if not configured or
3044                  * if starting only per queue */
3045                 if (!txq->q_set || (on && txq->tx_deferred_start))
3046                         continue;
3047                 if (on)
3048                         ret = i40e_dev_tx_queue_start(dev, i);
3049                 else
3050                         ret = i40e_dev_tx_queue_stop(dev, i);
3051                 if ( ret != I40E_SUCCESS)
3052                         return ret;
3053         }
3054
3055         return I40E_SUCCESS;
3056 }
3057
3058 int
3059 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3060 {
3061         uint32_t reg;
3062         uint16_t j;
3063
3064         /* Wait until the request is finished */
3065         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3066                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3067                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3068                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3069                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3070                         break;
3071         }
3072
3073         if (on) {
3074                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3075                         return I40E_SUCCESS; /* Already on, skip next steps */
3076                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3077         } else {
3078                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3079                         return I40E_SUCCESS; /* Already off, skip next steps */
3080                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3081         }
3082
3083         /* Write the register */
3084         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3085         /* Check the result */
3086         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3087                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3088                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3089                 if (on) {
3090                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3091                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3092                                 break;
3093                 } else {
3094                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3095                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3096                                 break;
3097                 }
3098         }
3099
3100         /* Check if it is timeout */
3101         if (j >= I40E_CHK_Q_ENA_COUNT) {
3102                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3103                             (on ? "enable" : "disable"), q_idx);
3104                 return I40E_ERR_TIMEOUT;
3105         }
3106
3107         return I40E_SUCCESS;
3108 }
3109 /* Switch on or off the rx queues */
3110 static int
3111 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3112 {
3113         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3114         struct i40e_rx_queue *rxq;
3115         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3116         uint16_t i;
3117         int ret;
3118
3119         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3120                 rxq = dev_data->rx_queues[i];
3121                 /* Don't operate the queue if not configured or
3122                  * if starting only per queue */
3123                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3124                         continue;
3125                 if (on)
3126                         ret = i40e_dev_rx_queue_start(dev, i);
3127                 else
3128                         ret = i40e_dev_rx_queue_stop(dev, i);
3129                 if (ret != I40E_SUCCESS)
3130                         return ret;
3131         }
3132
3133         return I40E_SUCCESS;
3134 }
3135
3136 /* Switch on or off all the rx/tx queues */
3137 int
3138 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3139 {
3140         int ret;
3141
3142         if (on) {
3143                 /* enable rx queues before enabling tx queues */
3144                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3145                 if (ret) {
3146                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3147                         return ret;
3148                 }
3149                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3150         } else {
3151                 /* Stop tx queues before stopping rx queues */
3152                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3153                 if (ret) {
3154                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3155                         return ret;
3156                 }
3157                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3158         }
3159
3160         return ret;
3161 }
3162
3163 /* Initialize VSI for TX */
3164 static int
3165 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3166 {
3167         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3168         struct rte_eth_dev_data *data = pf->dev_data;
3169         uint16_t i;
3170         uint32_t ret = I40E_SUCCESS;
3171
3172         for (i = 0; i < data->nb_tx_queues; i++) {
3173                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3174                 if (ret != I40E_SUCCESS)
3175                         break;
3176         }
3177
3178         return ret;
3179 }
3180
3181 /* Initialize VSI for RX */
3182 static int
3183 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3184 {
3185         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3186         struct rte_eth_dev_data *data = pf->dev_data;
3187         int ret = I40E_SUCCESS;
3188         uint16_t i;
3189
3190         i40e_pf_config_mq_rx(pf);
3191         for (i = 0; i < data->nb_rx_queues; i++) {
3192                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3193                 if (ret != I40E_SUCCESS) {
3194                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3195                                     "initialization");
3196                         break;
3197                 }
3198         }
3199
3200         return ret;
3201 }
3202
3203 /* Initialize VSI */
3204 static int
3205 i40e_vsi_init(struct i40e_vsi *vsi)
3206 {
3207         int err;
3208
3209         err = i40e_vsi_tx_init(vsi);
3210         if (err) {
3211                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3212                 return err;
3213         }
3214         err = i40e_vsi_rx_init(vsi);
3215         if (err) {
3216                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3217                 return err;
3218         }
3219
3220         return err;
3221 }
3222
3223 static void
3224 i40e_stat_update_32(struct i40e_hw *hw,
3225                    uint32_t reg,
3226                    bool offset_loaded,
3227                    uint64_t *offset,
3228                    uint64_t *stat)
3229 {
3230         uint64_t new_data;
3231
3232         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3233         if (!offset_loaded)
3234                 *offset = new_data;
3235
3236         if (new_data >= *offset)
3237                 *stat = (uint64_t)(new_data - *offset);
3238         else
3239                 *stat = (uint64_t)((new_data +
3240                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3241 }
3242
3243 static void
3244 i40e_stat_update_48(struct i40e_hw *hw,
3245                    uint32_t hireg,
3246                    uint32_t loreg,
3247                    bool offset_loaded,
3248                    uint64_t *offset,
3249                    uint64_t *stat)
3250 {
3251         uint64_t new_data;
3252
3253         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3254         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3255                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3256
3257         if (!offset_loaded)
3258                 *offset = new_data;
3259
3260         if (new_data >= *offset)
3261                 *stat = new_data - *offset;
3262         else
3263                 *stat = (uint64_t)((new_data +
3264                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3265
3266         *stat &= I40E_48_BIT_MASK;
3267 }
3268
3269 /* Disable IRQ0 */
3270 void
3271 i40e_pf_disable_irq0(struct i40e_hw *hw)
3272 {
3273         /* Disable all interrupt types */
3274         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3275         I40E_WRITE_FLUSH(hw);
3276 }
3277
3278 /* Enable IRQ0 */
3279 void
3280 i40e_pf_enable_irq0(struct i40e_hw *hw)
3281 {
3282         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3283                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3284                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3285                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3286         I40E_WRITE_FLUSH(hw);
3287 }
3288
3289 static void
3290 i40e_pf_config_irq0(struct i40e_hw *hw)
3291 {
3292         uint32_t enable;
3293
3294         /* read pending request and disable first */
3295         i40e_pf_disable_irq0(hw);
3296         /**
3297          * Enable all interrupt error options to detect possible errors,
3298          * other informative int are ignored
3299          */
3300         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3301                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3302                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3303                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3304                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3305                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3306                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3307                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3308
3309         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3310         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3311                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3312
3313         /* Link no queues with irq0 */
3314         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3315                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3316 }
3317
3318 static void
3319 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3320 {
3321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323         int i;
3324         uint16_t abs_vf_id;
3325         uint32_t index, offset, val;
3326
3327         if (!pf->vfs)
3328                 return;
3329         /**
3330          * Try to find which VF trigger a reset, use absolute VF id to access
3331          * since the reg is global register.
3332          */
3333         for (i = 0; i < pf->vf_num; i++) {
3334                 abs_vf_id = hw->func_caps.vf_base_id + i;
3335                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3336                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3337                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3338                 /* VFR event occured */
3339                 if (val & (0x1 << offset)) {
3340                         int ret;
3341
3342                         /* Clear the event first */
3343                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3344                                                         (0x1 << offset));
3345                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3346                         /**
3347                          * Only notify a VF reset event occured,
3348                          * don't trigger another SW reset
3349                          */
3350                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3351                         if (ret != I40E_SUCCESS)
3352                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3353                 }
3354         }
3355 }
3356
3357 static void
3358 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3359 {
3360         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         struct i40e_arq_event_info info;
3362         uint16_t pending, opcode;
3363         int ret;
3364
3365         info.buf_len = I40E_AQ_BUF_SZ;
3366         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3367         if (!info.msg_buf) {
3368                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3369                 return;
3370         }
3371
3372         pending = 1;
3373         while (pending) {
3374                 ret = i40e_clean_arq_element(hw, &info, &pending);
3375
3376                 if (ret != I40E_SUCCESS) {
3377                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3378                                     "aq_err: %u", hw->aq.asq_last_status);
3379                         break;
3380                 }
3381                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3382
3383                 switch (opcode) {
3384                 case i40e_aqc_opc_send_msg_to_pf:
3385                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3386                         i40e_pf_host_handle_vf_msg(dev,
3387                                         rte_le_to_cpu_16(info.desc.retval),
3388                                         rte_le_to_cpu_32(info.desc.cookie_high),
3389                                         rte_le_to_cpu_32(info.desc.cookie_low),
3390                                         info.msg_buf,
3391                                         info.msg_len);
3392                         break;
3393                 default:
3394                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3395                                     opcode);
3396                         break;
3397                 }
3398         }
3399         rte_free(info.msg_buf);
3400 }
3401
3402 /**
3403  * Interrupt handler triggered by NIC  for handling
3404  * specific interrupt.
3405  *
3406  * @param handle
3407  *  Pointer to interrupt handle.
3408  * @param param
3409  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3410  *
3411  * @return
3412  *  void
3413  */
3414 static void
3415 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3416                            void *param)
3417 {
3418         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420         uint32_t cause, enable;
3421
3422         i40e_pf_disable_irq0(hw);
3423
3424         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3425         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3426
3427         /* Shared IRQ case, return */
3428         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3429                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3430                             "no INT event to process", hw->pf_id);
3431                 goto done;
3432         }
3433
3434         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3435                 PMD_DRV_LOG(INFO, "INT:Link status changed");
3436                 i40e_dev_link_update(dev, 0);
3437         }
3438
3439         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3440                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3441
3442         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3443                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3444
3445         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3446                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3447
3448         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3449                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3450
3451         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3452                 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3453
3454         /* Add processing func to deal with VF reset vent */
3455         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3456                 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3457                 i40e_dev_handle_vfr_event(dev);
3458         }
3459         /* Find admin queue event */
3460         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3461                 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3462                 i40e_dev_handle_aq_msg(dev);
3463         }
3464
3465 done:
3466         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3467         /* Re-enable interrupt from device side */
3468         i40e_pf_enable_irq0(hw);
3469         /* Re-enable interrupt from host side */
3470         rte_intr_enable(&(dev->pci_dev->intr_handle));
3471 }
3472
3473 static int
3474 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3475                          struct i40e_macvlan_filter *filter,
3476                          int total)
3477 {
3478         int ele_num, ele_buff_size;
3479         int num, actual_num, i;
3480         int ret = I40E_SUCCESS;
3481         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3482         struct i40e_aqc_add_macvlan_element_data *req_list;
3483
3484         if (filter == NULL  || total == 0)
3485                 return I40E_ERR_PARAM;
3486         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3487         ele_buff_size = hw->aq.asq_buf_size;
3488
3489         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3490         if (req_list == NULL) {
3491                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3492                 return I40E_ERR_NO_MEMORY;
3493         }
3494
3495         num = 0;
3496         do {
3497                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3498                 memset(req_list, 0, ele_buff_size);
3499
3500                 for (i = 0; i < actual_num; i++) {
3501                         (void)rte_memcpy(req_list[i].mac_addr,
3502                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3503                         req_list[i].vlan_tag =
3504                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3505                         req_list[i].flags = rte_cpu_to_le_16(\
3506                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3507                         req_list[i].queue_number = 0;
3508                 }
3509
3510                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3511                                                 actual_num, NULL);
3512                 if (ret != I40E_SUCCESS) {
3513                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3514                         goto DONE;
3515                 }
3516                 num += actual_num;
3517         } while (num < total);
3518
3519 DONE:
3520         rte_free(req_list);
3521         return ret;
3522 }
3523
3524 static int
3525 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3526                             struct i40e_macvlan_filter *filter,
3527                             int total)
3528 {
3529         int ele_num, ele_buff_size;
3530         int num, actual_num, i;
3531         int ret = I40E_SUCCESS;
3532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3533         struct i40e_aqc_remove_macvlan_element_data *req_list;
3534
3535         if (filter == NULL  || total == 0)
3536                 return I40E_ERR_PARAM;
3537
3538         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3539         ele_buff_size = hw->aq.asq_buf_size;
3540
3541         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3542         if (req_list == NULL) {
3543                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3544                 return I40E_ERR_NO_MEMORY;
3545         }
3546
3547         num = 0;
3548         do {
3549                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3550                 memset(req_list, 0, ele_buff_size);
3551
3552                 for (i = 0; i < actual_num; i++) {
3553                         (void)rte_memcpy(req_list[i].mac_addr,
3554                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3555                         req_list[i].vlan_tag =
3556                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3557                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3558                 }
3559
3560                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3561                                                 actual_num, NULL);
3562                 if (ret != I40E_SUCCESS) {
3563                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3564                         goto DONE;
3565                 }
3566                 num += actual_num;
3567         } while (num < total);
3568
3569 DONE:
3570         rte_free(req_list);
3571         return ret;
3572 }
3573
3574 /* Find out specific MAC filter */
3575 static struct i40e_mac_filter *
3576 i40e_find_mac_filter(struct i40e_vsi *vsi,
3577                          struct ether_addr *macaddr)
3578 {
3579         struct i40e_mac_filter *f;
3580
3581         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3582                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3583                         return f;
3584         }
3585
3586         return NULL;
3587 }
3588
3589 static bool
3590 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3591                          uint16_t vlan_id)
3592 {
3593         uint32_t vid_idx, vid_bit;
3594
3595         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3596         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3597
3598         if (vsi->vfta[vid_idx] & vid_bit)
3599                 return 1;
3600         else
3601                 return 0;
3602 }
3603
3604 static void
3605 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3606                          uint16_t vlan_id, bool on)
3607 {
3608         uint32_t vid_idx, vid_bit;
3609
3610 #define UINT32_BIT_MASK      0x1F
3611 #define VALID_VLAN_BIT_MASK  0xFFF
3612         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3613          *  element first, then find the bits it belongs to
3614          */
3615         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3616                   sizeof(uint32_t));
3617         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3618
3619         if (on)
3620                 vsi->vfta[vid_idx] |= vid_bit;
3621         else
3622                 vsi->vfta[vid_idx] &= ~vid_bit;
3623 }
3624
3625 /**
3626  * Find all vlan options for specific mac addr,
3627  * return with actual vlan found.
3628  */
3629 static inline int
3630 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3631                            struct i40e_macvlan_filter *mv_f,
3632                            int num, struct ether_addr *addr)
3633 {
3634         int i;
3635         uint32_t j, k;
3636
3637         /**
3638          * Not to use i40e_find_vlan_filter to decrease the loop time,
3639          * although the code looks complex.
3640           */
3641         if (num < vsi->vlan_num)
3642                 return I40E_ERR_PARAM;
3643
3644         i = 0;
3645         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3646                 if (vsi->vfta[j]) {
3647                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3648                                 if (vsi->vfta[j] & (1 << k)) {
3649                                         if (i > num - 1) {
3650                                                 PMD_DRV_LOG(ERR, "vlan number "
3651                                                             "not match");
3652                                                 return I40E_ERR_PARAM;
3653                                         }
3654                                         (void)rte_memcpy(&mv_f[i].macaddr,
3655                                                         addr, ETH_ADDR_LEN);
3656                                         mv_f[i].vlan_id =
3657                                                 j * I40E_UINT32_BIT_SIZE + k;
3658                                         i++;
3659                                 }
3660                         }
3661                 }
3662         }
3663         return I40E_SUCCESS;
3664 }
3665
3666 static inline int
3667 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3668                            struct i40e_macvlan_filter *mv_f,
3669                            int num,
3670                            uint16_t vlan)
3671 {
3672         int i = 0;
3673         struct i40e_mac_filter *f;
3674
3675         if (num < vsi->mac_num)
3676                 return I40E_ERR_PARAM;
3677
3678         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3679                 if (i > num - 1) {
3680                         PMD_DRV_LOG(ERR, "buffer number not match");
3681                         return I40E_ERR_PARAM;
3682                 }
3683                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3684                 mv_f[i].vlan_id = vlan;
3685                 i++;
3686         }
3687
3688         return I40E_SUCCESS;
3689 }
3690
3691 static int
3692 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3693 {
3694         int i, num;
3695         struct i40e_mac_filter *f;
3696         struct i40e_macvlan_filter *mv_f;
3697         int ret = I40E_SUCCESS;
3698
3699         if (vsi == NULL || vsi->mac_num == 0)
3700                 return I40E_ERR_PARAM;
3701
3702         /* Case that no vlan is set */
3703         if (vsi->vlan_num == 0)
3704                 num = vsi->mac_num;
3705         else
3706                 num = vsi->mac_num * vsi->vlan_num;
3707
3708         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3709         if (mv_f == NULL) {
3710                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3711                 return I40E_ERR_NO_MEMORY;
3712         }
3713
3714         i = 0;
3715         if (vsi->vlan_num == 0) {
3716                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3717                         (void)rte_memcpy(&mv_f[i].macaddr,
3718                                 &f->macaddr, ETH_ADDR_LEN);
3719                         mv_f[i].vlan_id = 0;
3720                         i++;
3721                 }
3722         } else {
3723                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3724                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3725                                         vsi->vlan_num, &f->macaddr);
3726                         if (ret != I40E_SUCCESS)
3727                                 goto DONE;
3728                         i += vsi->vlan_num;
3729                 }
3730         }
3731
3732         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3733 DONE:
3734         rte_free(mv_f);
3735
3736         return ret;
3737 }
3738
3739 int
3740 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3741 {
3742         struct i40e_macvlan_filter *mv_f;
3743         int mac_num;
3744         int ret = I40E_SUCCESS;
3745
3746         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3747                 return I40E_ERR_PARAM;
3748
3749         /* If it's already set, just return */
3750         if (i40e_find_vlan_filter(vsi,vlan))
3751                 return I40E_SUCCESS;
3752
3753         mac_num = vsi->mac_num;
3754
3755         if (mac_num == 0) {
3756                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3757                 return I40E_ERR_PARAM;
3758         }
3759
3760         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3761
3762         if (mv_f == NULL) {
3763                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3764                 return I40E_ERR_NO_MEMORY;
3765         }
3766
3767         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3768
3769         if (ret != I40E_SUCCESS)
3770                 goto DONE;
3771
3772         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3773
3774         if (ret != I40E_SUCCESS)
3775                 goto DONE;
3776
3777         i40e_set_vlan_filter(vsi, vlan, 1);
3778
3779         vsi->vlan_num++;
3780         ret = I40E_SUCCESS;
3781 DONE:
3782         rte_free(mv_f);
3783         return ret;
3784 }
3785
3786 int
3787 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3788 {
3789         struct i40e_macvlan_filter *mv_f;
3790         int mac_num;
3791         int ret = I40E_SUCCESS;
3792
3793         /**
3794          * Vlan 0 is the generic filter for untagged packets
3795          * and can't be removed.
3796          */
3797         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3798                 return I40E_ERR_PARAM;
3799
3800         /* If can't find it, just return */
3801         if (!i40e_find_vlan_filter(vsi, vlan))
3802                 return I40E_ERR_PARAM;
3803
3804         mac_num = vsi->mac_num;
3805
3806         if (mac_num == 0) {
3807                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3808                 return I40E_ERR_PARAM;
3809         }
3810
3811         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3812
3813         if (mv_f == NULL) {
3814                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3815                 return I40E_ERR_NO_MEMORY;
3816         }
3817
3818         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3819
3820         if (ret != I40E_SUCCESS)
3821                 goto DONE;
3822
3823         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3824
3825         if (ret != I40E_SUCCESS)
3826                 goto DONE;
3827
3828         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3829         if (vsi->vlan_num == 1) {
3830                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3831                 if (ret != I40E_SUCCESS)
3832                         goto DONE;
3833
3834                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3835                 if (ret != I40E_SUCCESS)
3836                         goto DONE;
3837         }
3838
3839         i40e_set_vlan_filter(vsi, vlan, 0);
3840
3841         vsi->vlan_num--;
3842         ret = I40E_SUCCESS;
3843 DONE:
3844         rte_free(mv_f);
3845         return ret;
3846 }
3847
3848 int
3849 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3850 {
3851         struct i40e_mac_filter *f;
3852         struct i40e_macvlan_filter *mv_f;
3853         int vlan_num;
3854         int ret = I40E_SUCCESS;
3855
3856         /* If it's add and we've config it, return */
3857         f = i40e_find_mac_filter(vsi, addr);
3858         if (f != NULL)
3859                 return I40E_SUCCESS;
3860
3861         /**
3862          * If vlan_num is 0, that's the first time to add mac,
3863          * set mask for vlan_id 0.
3864          */
3865         if (vsi->vlan_num == 0) {
3866                 i40e_set_vlan_filter(vsi, 0, 1);
3867                 vsi->vlan_num = 1;
3868         }
3869
3870         vlan_num = vsi->vlan_num;
3871
3872         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3873         if (mv_f == NULL) {
3874                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3875                 return I40E_ERR_NO_MEMORY;
3876         }
3877
3878         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3879         if (ret != I40E_SUCCESS)
3880                 goto DONE;
3881
3882         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3883         if (ret != I40E_SUCCESS)
3884                 goto DONE;
3885
3886         /* Add the mac addr into mac list */
3887         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3888         if (f == NULL) {
3889                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3890                 ret = I40E_ERR_NO_MEMORY;
3891                 goto DONE;
3892         }
3893         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3894         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3895         vsi->mac_num++;
3896
3897         ret = I40E_SUCCESS;
3898 DONE:
3899         rte_free(mv_f);
3900
3901         return ret;
3902 }
3903
3904 int
3905 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3906 {
3907         struct i40e_mac_filter *f;
3908         struct i40e_macvlan_filter *mv_f;
3909         int vlan_num;
3910         int ret = I40E_SUCCESS;
3911
3912         /* Can't find it, return an error */
3913         f = i40e_find_mac_filter(vsi, addr);
3914         if (f == NULL)
3915                 return I40E_ERR_PARAM;
3916
3917         vlan_num = vsi->vlan_num;
3918         if (vlan_num == 0) {
3919                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3920                 return I40E_ERR_PARAM;
3921         }
3922         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3923         if (mv_f == NULL) {
3924                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3925                 return I40E_ERR_NO_MEMORY;
3926         }
3927
3928         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3929         if (ret != I40E_SUCCESS)
3930                 goto DONE;
3931
3932         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3933         if (ret != I40E_SUCCESS)
3934                 goto DONE;
3935
3936         /* Remove the mac addr into mac list */
3937         TAILQ_REMOVE(&vsi->mac_list, f, next);
3938         rte_free(f);
3939         vsi->mac_num--;
3940
3941         ret = I40E_SUCCESS;
3942 DONE:
3943         rte_free(mv_f);
3944         return ret;
3945 }
3946
3947 /* Configure hash enable flags for RSS */
3948 uint64_t
3949 i40e_config_hena(uint64_t flags)
3950 {
3951         uint64_t hena = 0;
3952
3953         if (!flags)
3954                 return hena;
3955
3956         if (flags & ETH_RSS_NONF_IPV4_UDP)
3957                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3958         if (flags & ETH_RSS_NONF_IPV4_TCP)
3959                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3960         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3961                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3962         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3963                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3964         if (flags & ETH_RSS_FRAG_IPV4)
3965                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3966         if (flags & ETH_RSS_NONF_IPV6_UDP)
3967                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3968         if (flags & ETH_RSS_NONF_IPV6_TCP)
3969                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3970         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3971                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3972         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3973                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3974         if (flags & ETH_RSS_FRAG_IPV6)
3975                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3976         if (flags & ETH_RSS_L2_PAYLOAD)
3977                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3978
3979         return hena;
3980 }
3981
3982 /* Parse the hash enable flags */
3983 uint64_t
3984 i40e_parse_hena(uint64_t flags)
3985 {
3986         uint64_t rss_hf = 0;
3987
3988         if (!flags)
3989                 return rss_hf;
3990
3991         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3992                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3993         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3994                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3995         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3996                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3997         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3998                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3999         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4000                 rss_hf |= ETH_RSS_FRAG_IPV4;
4001         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4002                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4003         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4004                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4005         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4006                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4007         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4008                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4009         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4010                 rss_hf |= ETH_RSS_FRAG_IPV6;
4011         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4012                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4013
4014         return rss_hf;
4015 }
4016
4017 /* Disable RSS */
4018 static void
4019 i40e_pf_disable_rss(struct i40e_pf *pf)
4020 {
4021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4022         uint64_t hena;
4023
4024         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4025         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4026         hena &= ~I40E_RSS_HENA_ALL;
4027         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4028         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4029         I40E_WRITE_FLUSH(hw);
4030 }
4031
4032 static int
4033 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4034 {
4035         uint32_t *hash_key;
4036         uint8_t hash_key_len;
4037         uint64_t rss_hf;
4038         uint16_t i;
4039         uint64_t hena;
4040
4041         hash_key = (uint32_t *)(rss_conf->rss_key);
4042         hash_key_len = rss_conf->rss_key_len;
4043         if (hash_key != NULL && hash_key_len >=
4044                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4045                 /* Fill in RSS hash key */
4046                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4047                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4048         }
4049
4050         rss_hf = rss_conf->rss_hf;
4051         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4052         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4053         hena &= ~I40E_RSS_HENA_ALL;
4054         hena |= i40e_config_hena(rss_hf);
4055         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4056         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4057         I40E_WRITE_FLUSH(hw);
4058
4059         return 0;
4060 }
4061
4062 static int
4063 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4064                          struct rte_eth_rss_conf *rss_conf)
4065 {
4066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4068         uint64_t hena;
4069
4070         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4071         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4072         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4073                 if (rss_hf != 0) /* Enable RSS */
4074                         return -EINVAL;
4075                 return 0; /* Nothing to do */
4076         }
4077         /* RSS enabled */
4078         if (rss_hf == 0) /* Disable RSS */
4079                 return -EINVAL;
4080
4081         return i40e_hw_rss_hash_set(hw, rss_conf);
4082 }
4083
4084 static int
4085 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4086                            struct rte_eth_rss_conf *rss_conf)
4087 {
4088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4090         uint64_t hena;
4091         uint16_t i;
4092
4093         if (hash_key != NULL) {
4094                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4095                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4096                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4097         }
4098         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4099         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4100         rss_conf->rss_hf = i40e_parse_hena(hena);
4101
4102         return 0;
4103 }
4104
4105 static int
4106 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4107 {
4108         switch (filter_type) {
4109         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4110                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4111                 break;
4112         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4113                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4114                 break;
4115         case RTE_TUNNEL_FILTER_IMAC_TENID:
4116                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4117                 break;
4118         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4119                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4120                 break;
4121         case ETH_TUNNEL_FILTER_IMAC:
4122                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4123                 break;
4124         default:
4125                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4126                 return -EINVAL;
4127         }
4128
4129         return 0;
4130 }
4131
4132 static int
4133 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4134                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4135                         uint8_t add)
4136 {
4137         uint16_t ip_type;
4138         uint8_t tun_type = 0;
4139         int val, ret = 0;
4140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4141         struct i40e_vsi *vsi = pf->main_vsi;
4142         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4143         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4144
4145         cld_filter = rte_zmalloc("tunnel_filter",
4146                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4147                 0);
4148
4149         if (NULL == cld_filter) {
4150                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4151                 return -EINVAL;
4152         }
4153         pfilter = cld_filter;
4154
4155         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4156                         sizeof(struct ether_addr));
4157         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4158                         sizeof(struct ether_addr));
4159
4160         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4161         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4162                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4163                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4164                                 &tunnel_filter->ip_addr,
4165                                 sizeof(pfilter->ipaddr.v4.data));
4166         } else {
4167                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4168                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4169                                 &tunnel_filter->ip_addr,
4170                                 sizeof(pfilter->ipaddr.v6.data));
4171         }
4172
4173         /* check tunneled type */
4174         switch (tunnel_filter->tunnel_type) {
4175         case RTE_TUNNEL_TYPE_VXLAN:
4176                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4177                 break;
4178         default:
4179                 /* Other tunnel types is not supported. */
4180                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4181                 rte_free(cld_filter);
4182                 return -EINVAL;
4183         }
4184
4185         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4186                                                 &pfilter->flags);
4187         if (val < 0) {
4188                 rte_free(cld_filter);
4189                 return -EINVAL;
4190         }
4191
4192         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4193                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4194         pfilter->tenant_id = tunnel_filter->tenant_id;
4195         pfilter->queue_number = tunnel_filter->queue_id;
4196
4197         if (add)
4198                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4199         else
4200                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4201                                                 cld_filter, 1);
4202
4203         rte_free(cld_filter);
4204         return ret;
4205 }
4206
4207 static int
4208 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4209 {
4210         uint8_t i;
4211
4212         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4213                 if (pf->vxlan_ports[i] == port)
4214                         return i;
4215         }
4216
4217         return -1;
4218 }
4219
4220 static int
4221 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4222 {
4223         int  idx, ret;
4224         uint8_t filter_idx;
4225         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4226
4227         idx = i40e_get_vxlan_port_idx(pf, port);
4228
4229         /* Check if port already exists */
4230         if (idx >= 0) {
4231                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4232                 return -EINVAL;
4233         }
4234
4235         /* Now check if there is space to add the new port */
4236         idx = i40e_get_vxlan_port_idx(pf, 0);
4237         if (idx < 0) {
4238                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4239                         "not adding port %d", port);
4240                 return -ENOSPC;
4241         }
4242
4243         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4244                                         &filter_idx, NULL);
4245         if (ret < 0) {
4246                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4247                 return -1;
4248         }
4249
4250         PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4251                          port,  filter_index);
4252
4253         /* New port: add it and mark its index in the bitmap */
4254         pf->vxlan_ports[idx] = port;
4255         pf->vxlan_bitmap |= (1 << idx);
4256
4257         if (!(pf->flags & I40E_FLAG_VXLAN))
4258                 pf->flags |= I40E_FLAG_VXLAN;
4259
4260         return 0;
4261 }
4262
4263 static int
4264 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4265 {
4266         int idx;
4267         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4268
4269         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4270                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4271                 return -EINVAL;
4272         }
4273
4274         idx = i40e_get_vxlan_port_idx(pf, port);
4275
4276         if (idx < 0) {
4277                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4278                 return -EINVAL;
4279         }
4280
4281         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4282                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4283                 return -1;
4284         }
4285
4286         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4287                         port, idx);
4288
4289         pf->vxlan_ports[idx] = 0;
4290         pf->vxlan_bitmap &= ~(1 << idx);
4291
4292         if (!pf->vxlan_bitmap)
4293                 pf->flags &= ~I40E_FLAG_VXLAN;
4294
4295         return 0;
4296 }
4297
4298 /* Add UDP tunneling port */
4299 static int
4300 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4301                         struct rte_eth_udp_tunnel *udp_tunnel)
4302 {
4303         int ret = 0;
4304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4305
4306         if (udp_tunnel == NULL)
4307                 return -EINVAL;
4308
4309         switch (udp_tunnel->prot_type) {
4310         case RTE_TUNNEL_TYPE_VXLAN:
4311                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4312                 break;
4313
4314         case RTE_TUNNEL_TYPE_GENEVE:
4315         case RTE_TUNNEL_TYPE_TEREDO:
4316                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4317                 ret = -1;
4318                 break;
4319
4320         default:
4321                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4322                 ret = -1;
4323                 break;
4324         }
4325
4326         return ret;
4327 }
4328
4329 /* Remove UDP tunneling port */
4330 static int
4331 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4332                         struct rte_eth_udp_tunnel *udp_tunnel)
4333 {
4334         int ret = 0;
4335         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4336
4337         if (udp_tunnel == NULL)
4338                 return -EINVAL;
4339
4340         switch (udp_tunnel->prot_type) {
4341         case RTE_TUNNEL_TYPE_VXLAN:
4342                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4343                 break;
4344         case RTE_TUNNEL_TYPE_GENEVE:
4345         case RTE_TUNNEL_TYPE_TEREDO:
4346                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4347                 ret = -1;
4348                 break;
4349         default:
4350                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4351                 ret = -1;
4352                 break;
4353         }
4354
4355         return ret;
4356 }
4357
4358 /* Configure RSS */
4359 static int
4360 i40e_pf_config_rss(struct i40e_pf *pf)
4361 {
4362         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4363         struct rte_eth_rss_conf rss_conf;
4364         uint32_t i, lut = 0;
4365         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4366
4367         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4368                 if (j == num)
4369                         j = 0;
4370                 lut = (lut << 8) | (j & ((0x1 <<
4371                         hw->func_caps.rss_table_entry_width) - 1));
4372                 if ((i & 3) == 3)
4373                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4374         }
4375
4376         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4377         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4378                 i40e_pf_disable_rss(pf);
4379                 return 0;
4380         }
4381         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4382                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4383                 /* Calculate the default hash key */
4384                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4385                         rss_key_default[i] = (uint32_t)rte_rand();
4386                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4387                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4388                                                         sizeof(uint32_t);
4389         }
4390
4391         return i40e_hw_rss_hash_set(hw, &rss_conf);
4392 }
4393
4394 static int
4395 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4396                         struct rte_eth_tunnel_filter_conf *filter)
4397 {
4398         if (pf == NULL || filter == NULL) {
4399                 PMD_DRV_LOG(ERR, "Invalid parameter");
4400                 return -EINVAL;
4401         }
4402
4403         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4404                 PMD_DRV_LOG(ERR, "Invalid queue ID");
4405                 return -EINVAL;
4406         }
4407
4408         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4409                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4410                 return -EINVAL;
4411         }
4412
4413         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4414                 (is_zero_ether_addr(filter->outer_mac))) {
4415                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4416                 return -EINVAL;
4417         }
4418
4419         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4420                 (is_zero_ether_addr(filter->inner_mac))) {
4421                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4422                 return -EINVAL;
4423         }
4424
4425         return 0;
4426 }
4427
4428 static int
4429 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4430                         void *arg)
4431 {
4432         struct rte_eth_tunnel_filter_conf *filter;
4433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4434         int ret = I40E_SUCCESS;
4435
4436         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4437
4438         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4439                 return I40E_ERR_PARAM;
4440
4441         switch (filter_op) {
4442         case RTE_ETH_FILTER_NOP:
4443                 if (!(pf->flags & I40E_FLAG_VXLAN))
4444                         ret = I40E_NOT_SUPPORTED;
4445         case RTE_ETH_FILTER_ADD:
4446                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4447                 break;
4448         case RTE_ETH_FILTER_DELETE:
4449                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4450                 break;
4451         default:
4452                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4453                 ret = I40E_ERR_PARAM;
4454                 break;
4455         }
4456
4457         return ret;
4458 }
4459
4460 static int
4461 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4462 {
4463         if (!pf->dev_data->sriov.active) {
4464                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4465                 case ETH_MQ_RX_RSS:
4466                         i40e_pf_config_rss(pf);
4467                         break;
4468                 default:
4469                         i40e_pf_disable_rss(pf);
4470                         break;
4471                 }
4472         }
4473
4474         return 0;
4475 }
4476
4477 static int
4478 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4479                      enum rte_filter_type filter_type,
4480                      enum rte_filter_op filter_op,
4481                      void *arg)
4482 {
4483         int ret = 0;
4484
4485         if (dev == NULL)
4486                 return -EINVAL;
4487
4488         switch (filter_type) {
4489         case RTE_ETH_FILTER_TUNNEL:
4490                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
4491                 break;
4492         default:
4493                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4494                                                         filter_type);
4495                 ret = -EINVAL;
4496                 break;
4497         }
4498
4499         return ret;
4500 }