4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
52 #include "i40e_logs.h"
53 #include "i40e/i40e_register_x710_int.h"
54 #include "i40e/i40e_prototype.h"
55 #include "i40e/i40e_adminq_cmd.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
61 #define I40E_DEFAULT_RX_FREE_THRESH 32
62 #define I40E_DEFAULT_RX_PTHRESH 8
63 #define I40E_DEFAULT_RX_HTHRESH 8
64 #define I40E_DEFAULT_RX_WTHRESH 0
66 #define I40E_DEFAULT_TX_FREE_THRESH 32
67 #define I40E_DEFAULT_TX_PTHRESH 32
68 #define I40E_DEFAULT_TX_HTHRESH 0
69 #define I40E_DEFAULT_TX_WTHRESH 0
70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
72 /* Maximun number of MAC addresses */
73 #define I40E_NUM_MACADDR_MAX 64
74 #define I40E_CLEAR_PXE_WAIT_MS 200
76 /* Maximun number of capability elements */
77 #define I40E_MAX_CAP_ELE_NUM 128
79 /* Wait count and inteval */
80 #define I40E_CHK_Q_ENA_COUNT 1000
81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
83 /* Maximun number of VSI */
84 #define I40E_MAX_NUM_VSIS (384UL)
86 /* Bit shift and mask */
87 #define I40E_16_BIT_SHIFT 16
88 #define I40E_16_BIT_MASK 0xFFFF
89 #define I40E_32_BIT_SHIFT 32
90 #define I40E_32_BIT_MASK 0xFFFFFFFF
91 #define I40E_48_BIT_SHIFT 48
92 #define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL
94 /* Default queue interrupt throttling time in microseconds*/
95 #define I40E_ITR_INDEX_DEFAULT 0
96 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
97 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
99 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
101 #define I40E_RSS_OFFLOAD_ALL ( \
102 ETH_RSS_NONF_IPV4_UDP | \
103 ETH_RSS_NONF_IPV4_TCP | \
104 ETH_RSS_NONF_IPV4_SCTP | \
105 ETH_RSS_NONF_IPV4_OTHER | \
106 ETH_RSS_FRAG_IPV4 | \
107 ETH_RSS_NONF_IPV6_UDP | \
108 ETH_RSS_NONF_IPV6_TCP | \
109 ETH_RSS_NONF_IPV6_SCTP | \
110 ETH_RSS_NONF_IPV6_OTHER | \
111 ETH_RSS_FRAG_IPV6 | \
114 /* All bits of RSS hash enable */
115 #define I40E_RSS_HENA_ALL ( \
116 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
117 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
118 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
119 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
120 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
121 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
122 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
123 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
124 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
125 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
126 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
127 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
128 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
129 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
131 static int eth_i40e_dev_init(\
132 __attribute__((unused)) struct eth_driver *eth_drv,
133 struct rte_eth_dev *eth_dev);
134 static int i40e_dev_configure(struct rte_eth_dev *dev);
135 static int i40e_dev_start(struct rte_eth_dev *dev);
136 static void i40e_dev_stop(struct rte_eth_dev *dev);
137 static void i40e_dev_close(struct rte_eth_dev *dev);
138 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
139 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
140 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
141 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
142 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
143 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
144 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
145 struct rte_eth_stats *stats);
146 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
147 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
151 static void i40e_dev_info_get(struct rte_eth_dev *dev,
152 struct rte_eth_dev_info *dev_info);
153 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
156 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
157 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
158 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
161 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
162 static int i40e_dev_led_on(struct rte_eth_dev *dev);
163 static int i40e_dev_led_off(struct rte_eth_dev *dev);
164 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
167 struct rte_eth_pfc_conf *pfc_conf);
168 static void i40e_macaddr_add(struct rte_eth_dev *dev,
169 struct ether_addr *mac_addr,
172 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
173 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
174 struct rte_eth_rss_reta *reta_conf);
175 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
176 struct rte_eth_rss_reta *reta_conf);
178 static int i40e_get_cap(struct i40e_hw *hw);
179 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
180 static int i40e_pf_setup(struct i40e_pf *pf);
181 static int i40e_vsi_init(struct i40e_vsi *vsi);
182 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
183 bool offset_loaded, uint64_t *offset, uint64_t *stat);
184 static void i40e_stat_update_48(struct i40e_hw *hw,
190 static void i40e_pf_config_irq0(struct i40e_hw *hw);
191 static void i40e_dev_interrupt_handler(
192 __rte_unused struct rte_intr_handle *handle, void *param);
193 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
194 uint32_t base, uint32_t num);
195 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
196 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
198 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
200 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
201 static int i40e_veb_release(struct i40e_veb *veb);
202 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
203 struct i40e_vsi *vsi);
204 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
205 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
206 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
207 struct i40e_macvlan_filter *mv_f,
209 struct ether_addr *addr);
210 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
211 struct i40e_macvlan_filter *mv_f,
214 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
215 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
216 struct rte_eth_rss_conf *rss_conf);
217 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
218 struct rte_eth_rss_conf *rss_conf);
220 /* Default hash key buffer for RSS */
221 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
223 static struct rte_pci_id pci_id_i40e_map[] = {
224 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
225 #include "rte_pci_dev_ids.h"
226 { .vendor_id = 0, /* sentinel */ },
229 static struct eth_dev_ops i40e_eth_dev_ops = {
230 .dev_configure = i40e_dev_configure,
231 .dev_start = i40e_dev_start,
232 .dev_stop = i40e_dev_stop,
233 .dev_close = i40e_dev_close,
234 .promiscuous_enable = i40e_dev_promiscuous_enable,
235 .promiscuous_disable = i40e_dev_promiscuous_disable,
236 .allmulticast_enable = i40e_dev_allmulticast_enable,
237 .allmulticast_disable = i40e_dev_allmulticast_disable,
238 .dev_set_link_up = i40e_dev_set_link_up,
239 .dev_set_link_down = i40e_dev_set_link_down,
240 .link_update = i40e_dev_link_update,
241 .stats_get = i40e_dev_stats_get,
242 .stats_reset = i40e_dev_stats_reset,
243 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
244 .dev_infos_get = i40e_dev_info_get,
245 .vlan_filter_set = i40e_vlan_filter_set,
246 .vlan_tpid_set = i40e_vlan_tpid_set,
247 .vlan_offload_set = i40e_vlan_offload_set,
248 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
249 .vlan_pvid_set = i40e_vlan_pvid_set,
250 .rx_queue_start = i40e_dev_rx_queue_start,
251 .rx_queue_stop = i40e_dev_rx_queue_stop,
252 .tx_queue_start = i40e_dev_tx_queue_start,
253 .tx_queue_stop = i40e_dev_tx_queue_stop,
254 .rx_queue_setup = i40e_dev_rx_queue_setup,
255 .rx_queue_release = i40e_dev_rx_queue_release,
256 .rx_queue_count = i40e_dev_rx_queue_count,
257 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
258 .tx_queue_setup = i40e_dev_tx_queue_setup,
259 .tx_queue_release = i40e_dev_tx_queue_release,
260 .dev_led_on = i40e_dev_led_on,
261 .dev_led_off = i40e_dev_led_off,
262 .flow_ctrl_set = i40e_flow_ctrl_set,
263 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
264 .mac_addr_add = i40e_macaddr_add,
265 .mac_addr_remove = i40e_macaddr_remove,
266 .reta_update = i40e_dev_rss_reta_update,
267 .reta_query = i40e_dev_rss_reta_query,
268 .rss_hash_update = i40e_dev_rss_hash_update,
269 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
272 static struct eth_driver rte_i40e_pmd = {
274 .name = "rte_i40e_pmd",
275 .id_table = pci_id_i40e_map,
276 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
278 .eth_dev_init = eth_i40e_dev_init,
279 .dev_private_size = sizeof(struct i40e_adapter),
283 i40e_prev_power_of_2(int n)
301 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
302 struct rte_eth_link *link)
304 struct rte_eth_link *dst = link;
305 struct rte_eth_link *src = &(dev->data->dev_link);
307 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
308 *(uint64_t *)src) == 0)
315 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
316 struct rte_eth_link *link)
318 struct rte_eth_link *dst = &(dev->data->dev_link);
319 struct rte_eth_link *src = link;
321 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
322 *(uint64_t *)src) == 0)
329 * Driver initialization routine.
330 * Invoked once at EAL init time.
331 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
334 rte_i40e_pmd_init(const char *name __rte_unused,
335 const char *params __rte_unused)
337 PMD_INIT_FUNC_TRACE();
338 rte_eth_driver_register(&rte_i40e_pmd);
343 static struct rte_driver rte_i40e_driver = {
345 .init = rte_i40e_pmd_init,
348 PMD_REGISTER_DRIVER(rte_i40e_driver);
351 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
352 struct rte_eth_dev *dev)
354 struct rte_pci_device *pci_dev;
355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
357 struct i40e_vsi *vsi;
362 PMD_INIT_FUNC_TRACE();
364 dev->dev_ops = &i40e_eth_dev_ops;
365 dev->rx_pkt_burst = i40e_recv_pkts;
366 dev->tx_pkt_burst = i40e_xmit_pkts;
368 /* for secondary processes, we don't initialise any further as primary
369 * has already done this work. Only check we don't need a different
371 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
372 if (dev->data->scattered_rx)
373 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
376 pci_dev = dev->pci_dev;
377 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
378 pf->adapter->eth_dev = dev;
379 pf->dev_data = dev->data;
381 hw->back = I40E_PF_TO_ADAPTER(pf);
382 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
384 PMD_INIT_LOG(ERR, "Hardware is not available, "
385 "as address is NULL");
389 hw->vendor_id = pci_dev->id.vendor_id;
390 hw->device_id = pci_dev->id.device_id;
391 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
392 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
393 hw->bus.device = pci_dev->addr.devid;
394 hw->bus.func = pci_dev->addr.function;
396 /* Make sure all is clean before doing PF reset */
399 /* Reset here to make sure all is clean for each PF */
400 ret = i40e_pf_reset(hw);
402 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
406 /* Initialize the shared code (base driver) */
407 ret = i40e_init_shared_code(hw);
409 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
413 /* Initialize the parameters for adminq */
414 i40e_init_adminq_parameter(hw);
415 ret = i40e_init_adminq(hw);
416 if (ret != I40E_SUCCESS) {
417 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
420 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
421 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
422 hw->aq.api_maj_ver, hw->aq.api_min_ver,
423 ((hw->nvm.version >> 12) & 0xf),
424 ((hw->nvm.version >> 4) & 0xff),
425 (hw->nvm.version & 0xf), hw->nvm.eetrack);
428 ret = i40e_aq_stop_lldp(hw, true, NULL);
429 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
430 PMD_INIT_LOG(INFO, "Failed to stop lldp");
433 i40e_clear_pxe_mode(hw);
435 /* Get hw capabilities */
436 ret = i40e_get_cap(hw);
437 if (ret != I40E_SUCCESS) {
438 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
439 goto err_get_capabilities;
442 /* Initialize parameters for PF */
443 ret = i40e_pf_parameter_init(dev);
445 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
446 goto err_parameter_init;
449 /* Initialize the queue management */
450 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
452 PMD_INIT_LOG(ERR, "Failed to init queue pool");
453 goto err_qp_pool_init;
455 ret = i40e_res_pool_init(&pf->msix_pool, 1,
456 hw->func_caps.num_msix_vectors - 1);
458 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
459 goto err_msix_pool_init;
462 /* Initialize lan hmc */
463 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
464 hw->func_caps.num_rx_qp, 0, 0);
465 if (ret != I40E_SUCCESS) {
466 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
467 goto err_init_lan_hmc;
470 /* Configure lan hmc */
471 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
472 if (ret != I40E_SUCCESS) {
473 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
474 goto err_configure_lan_hmc;
477 /* Get and check the mac address */
478 i40e_get_mac_addr(hw, hw->mac.addr);
479 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
480 PMD_INIT_LOG(ERR, "mac address is not valid");
482 goto err_get_mac_addr;
484 /* Copy the permanent MAC address */
485 ether_addr_copy((struct ether_addr *) hw->mac.addr,
486 (struct ether_addr *) hw->mac.perm_addr);
488 /* Disable flow control */
489 hw->fc.requested_mode = I40E_FC_NONE;
490 i40e_set_fc(hw, &aq_fail, TRUE);
492 /* PF setup, which includes VSI setup */
493 ret = i40e_pf_setup(pf);
495 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
496 goto err_setup_pf_switch;
501 /* Disable double vlan by default */
502 i40e_vsi_config_double_vlan(vsi, FALSE);
504 if (!vsi->max_macaddrs)
505 len = ETHER_ADDR_LEN;
507 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
509 /* Should be after VSI initialized */
510 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
511 if (!dev->data->mac_addrs) {
512 PMD_INIT_LOG(ERR, "Failed to allocated memory "
513 "for storing mac address");
514 goto err_get_mac_addr;
516 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
517 &dev->data->mac_addrs[0]);
519 /* initialize pf host driver to setup SRIOV resource if applicable */
520 i40e_pf_host_init(dev);
522 /* register callback func to eal lib */
523 rte_intr_callback_register(&(pci_dev->intr_handle),
524 i40e_dev_interrupt_handler, (void *)dev);
526 /* configure and enable device interrupt */
527 i40e_pf_config_irq0(hw);
528 i40e_pf_enable_irq0(hw);
530 /* enable uio intr after callback register */
531 rte_intr_enable(&(pci_dev->intr_handle));
536 rte_free(pf->main_vsi);
538 err_configure_lan_hmc:
539 (void)i40e_shutdown_lan_hmc(hw);
541 i40e_res_pool_destroy(&pf->msix_pool);
543 i40e_res_pool_destroy(&pf->qp_pool);
546 err_get_capabilities:
547 (void)i40e_shutdown_adminq(hw);
553 i40e_dev_configure(struct rte_eth_dev *dev)
555 return i40e_dev_init_vlan(dev);
559 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
561 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
562 uint16_t msix_vect = vsi->msix_intr;
565 for (i = 0; i < vsi->nb_qps; i++) {
566 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
567 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
571 if (vsi->type != I40E_VSI_SRIOV) {
572 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
573 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
577 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
578 vsi->user_param + (msix_vect - 1);
580 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
582 I40E_WRITE_FLUSH(hw);
585 static inline uint16_t
586 i40e_calc_itr_interval(int16_t interval)
588 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
589 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
591 /* Convert to hardware count, as writing each 1 represents 2 us */
596 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
599 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
600 uint16_t msix_vect = vsi->msix_intr;
601 uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
604 for (i = 0; i < vsi->nb_qps; i++)
605 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
607 /* Bind all RX queues to allocated MSIX interrupt */
608 for (i = 0; i < vsi->nb_qps; i++) {
609 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
610 (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
611 ((vsi->base_queue + i + 1) <<
612 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
613 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
614 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
616 if (i == vsi->nb_qps - 1)
617 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
618 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
621 /* Write first RX queue to Link list register as the head element */
622 if (vsi->type != I40E_VSI_SRIOV) {
623 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
624 (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
625 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
627 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
628 msix_vect - 1), interval);
630 /* Disable auto-mask on enabling of all none-zero interrupt */
631 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
632 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
636 /* num_msix_vectors_vf needs to minus irq0 */
637 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
638 vsi->user_param + (msix_vect - 1);
640 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
641 (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
642 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
645 I40E_WRITE_FLUSH(hw);
649 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
651 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
652 uint16_t interval = i40e_calc_itr_interval(\
653 RTE_LIBRTE_I40E_ITR_INTERVAL);
655 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
656 I40E_PFINT_DYN_CTLN_INTENA_MASK |
657 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
658 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
659 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
663 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
665 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
667 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
670 static inline uint8_t
671 i40e_parse_link_speed(uint16_t eth_link_speed)
673 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
675 switch (eth_link_speed) {
676 case ETH_LINK_SPEED_40G:
677 link_speed = I40E_LINK_SPEED_40GB;
679 case ETH_LINK_SPEED_20G:
680 link_speed = I40E_LINK_SPEED_20GB;
682 case ETH_LINK_SPEED_10G:
683 link_speed = I40E_LINK_SPEED_10GB;
685 case ETH_LINK_SPEED_1000:
686 link_speed = I40E_LINK_SPEED_1GB;
688 case ETH_LINK_SPEED_100:
689 link_speed = I40E_LINK_SPEED_100MB;
697 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
699 enum i40e_status_code status;
700 struct i40e_aq_get_phy_abilities_resp phy_ab;
701 struct i40e_aq_set_phy_config phy_conf;
702 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
703 I40E_AQ_PHY_FLAG_PAUSE_RX |
704 I40E_AQ_PHY_FLAG_LOW_POWER;
705 const uint8_t advt = I40E_LINK_SPEED_40GB |
706 I40E_LINK_SPEED_10GB |
707 I40E_LINK_SPEED_1GB |
708 I40E_LINK_SPEED_100MB;
711 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
716 memset(&phy_conf, 0, sizeof(phy_conf));
718 /* bits 0-2 use the values from get_phy_abilities_resp */
720 abilities |= phy_ab.abilities & mask;
722 /* update ablities and speed */
723 if (abilities & I40E_AQ_PHY_AN_ENABLED)
724 phy_conf.link_speed = advt;
726 phy_conf.link_speed = force_speed;
728 phy_conf.abilities = abilities;
730 /* use get_phy_abilities_resp value for the rest */
731 phy_conf.phy_type = phy_ab.phy_type;
732 phy_conf.eee_capability = phy_ab.eee_capability;
733 phy_conf.eeer = phy_ab.eeer_val;
734 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
736 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
737 phy_ab.abilities, phy_ab.link_speed);
738 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
739 phy_conf.abilities, phy_conf.link_speed);
741 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
749 i40e_apply_link_speed(struct rte_eth_dev *dev)
752 uint8_t abilities = 0;
753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
754 struct rte_eth_conf *conf = &dev->data->dev_conf;
756 speed = i40e_parse_link_speed(conf->link_speed);
757 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
758 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
759 abilities |= I40E_AQ_PHY_AN_ENABLED;
761 abilities |= I40E_AQ_PHY_LINK_ENABLED;
763 return i40e_phy_conf_link(hw, abilities, speed);
767 i40e_dev_start(struct rte_eth_dev *dev)
769 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
771 struct i40e_vsi *vsi = pf->main_vsi;
774 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
775 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
776 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
777 dev->data->dev_conf.link_duplex,
783 ret = i40e_vsi_init(vsi);
784 if (ret != I40E_SUCCESS) {
785 PMD_DRV_LOG(ERR, "Failed to init VSI");
789 /* Map queues with MSIX interrupt */
790 i40e_vsi_queues_bind_intr(vsi);
791 i40e_vsi_enable_queues_intr(vsi);
793 /* Enable all queues which have been configured */
794 ret = i40e_vsi_switch_queues(vsi, TRUE);
795 if (ret != I40E_SUCCESS) {
796 PMD_DRV_LOG(ERR, "Failed to enable VSI");
800 /* Enable receiving broadcast packets */
801 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
802 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
803 if (ret != I40E_SUCCESS)
804 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
807 /* Apply link configure */
808 ret = i40e_apply_link_speed(dev);
809 if (I40E_SUCCESS != ret) {
810 PMD_DRV_LOG(ERR, "Fail to apply link setting");
817 i40e_vsi_switch_queues(vsi, FALSE);
823 i40e_dev_stop(struct rte_eth_dev *dev)
825 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
826 struct i40e_vsi *vsi = pf->main_vsi;
828 /* Disable all queues */
829 i40e_vsi_switch_queues(vsi, FALSE);
832 i40e_dev_set_link_down(dev);
834 /* un-map queues with interrupt registers */
835 i40e_vsi_disable_queues_intr(vsi);
836 i40e_vsi_queues_unbind_intr(vsi);
840 i40e_dev_close(struct rte_eth_dev *dev)
842 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
846 PMD_INIT_FUNC_TRACE();
850 /* Disable interrupt */
851 i40e_pf_disable_irq0(hw);
852 rte_intr_disable(&(dev->pci_dev->intr_handle));
854 /* shutdown and destroy the HMC */
855 i40e_shutdown_lan_hmc(hw);
857 /* release all the existing VSIs and VEBs */
858 i40e_vsi_release(pf->main_vsi);
860 /* shutdown the adminq */
861 i40e_aq_queue_shutdown(hw, true);
862 i40e_shutdown_adminq(hw);
864 i40e_res_pool_destroy(&pf->qp_pool);
865 i40e_res_pool_destroy(&pf->msix_pool);
867 /* force a PF reset to clean anything leftover */
868 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
869 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
870 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
871 I40E_WRITE_FLUSH(hw);
875 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
877 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
878 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
879 struct i40e_vsi *vsi = pf->main_vsi;
882 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
884 if (status != I40E_SUCCESS)
885 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
887 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
889 if (status != I40E_SUCCESS)
890 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
895 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
897 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
898 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
899 struct i40e_vsi *vsi = pf->main_vsi;
902 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
904 if (status != I40E_SUCCESS)
905 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
907 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
909 if (status != I40E_SUCCESS)
910 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
914 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
918 struct i40e_vsi *vsi = pf->main_vsi;
921 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
922 if (ret != I40E_SUCCESS)
923 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
927 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
931 struct i40e_vsi *vsi = pf->main_vsi;
934 if (dev->data->promiscuous == 1)
935 return; /* must remain in all_multicast mode */
937 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
938 vsi->seid, FALSE, NULL);
939 if (ret != I40E_SUCCESS)
940 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
944 * Set device link up.
947 i40e_dev_set_link_up(struct rte_eth_dev *dev)
949 /* re-apply link speed setting */
950 return i40e_apply_link_speed(dev);
954 * Set device link down.
957 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
959 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
960 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
963 return i40e_phy_conf_link(hw, abilities, speed);
967 i40e_dev_link_update(struct rte_eth_dev *dev,
968 __rte_unused int wait_to_complete)
970 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
971 struct i40e_link_status link_status;
972 struct rte_eth_link link, old;
975 memset(&link, 0, sizeof(link));
976 memset(&old, 0, sizeof(old));
977 memset(&link_status, 0, sizeof(link_status));
978 rte_i40e_dev_atomic_read_link_status(dev, &old);
980 /* Get link status information from hardware */
981 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
982 if (status != I40E_SUCCESS) {
983 link.link_speed = ETH_LINK_SPEED_100;
984 link.link_duplex = ETH_LINK_FULL_DUPLEX;
985 PMD_DRV_LOG(ERR, "Failed to get link info");
989 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
991 if (!link.link_status)
994 /* i40e uses full duplex only */
995 link.link_duplex = ETH_LINK_FULL_DUPLEX;
997 /* Parse the link status */
998 switch (link_status.link_speed) {
999 case I40E_LINK_SPEED_100MB:
1000 link.link_speed = ETH_LINK_SPEED_100;
1002 case I40E_LINK_SPEED_1GB:
1003 link.link_speed = ETH_LINK_SPEED_1000;
1005 case I40E_LINK_SPEED_10GB:
1006 link.link_speed = ETH_LINK_SPEED_10G;
1008 case I40E_LINK_SPEED_20GB:
1009 link.link_speed = ETH_LINK_SPEED_20G;
1011 case I40E_LINK_SPEED_40GB:
1012 link.link_speed = ETH_LINK_SPEED_40G;
1015 link.link_speed = ETH_LINK_SPEED_100;
1020 rte_i40e_dev_atomic_write_link_status(dev, &link);
1021 if (link.link_status == old.link_status)
1027 /* Get all the statistics of a VSI */
1029 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1031 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1032 struct i40e_eth_stats *nes = &vsi->eth_stats;
1033 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1034 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1036 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1037 vsi->offset_loaded, &oes->rx_bytes,
1039 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1040 vsi->offset_loaded, &oes->rx_unicast,
1042 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1043 vsi->offset_loaded, &oes->rx_multicast,
1044 &nes->rx_multicast);
1045 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1046 vsi->offset_loaded, &oes->rx_broadcast,
1047 &nes->rx_broadcast);
1048 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1049 &oes->rx_discards, &nes->rx_discards);
1050 /* GLV_REPC not supported */
1051 /* GLV_RMPC not supported */
1052 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1053 &oes->rx_unknown_protocol,
1054 &nes->rx_unknown_protocol);
1055 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1056 vsi->offset_loaded, &oes->tx_bytes,
1058 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1059 vsi->offset_loaded, &oes->tx_unicast,
1061 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1062 vsi->offset_loaded, &oes->tx_multicast,
1063 &nes->tx_multicast);
1064 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1065 vsi->offset_loaded, &oes->tx_broadcast,
1066 &nes->tx_broadcast);
1067 /* GLV_TDPC not supported */
1068 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1069 &oes->tx_errors, &nes->tx_errors);
1070 vsi->offset_loaded = true;
1072 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1074 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1075 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1076 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1077 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1078 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1079 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1080 nes->rx_unknown_protocol);
1081 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1082 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1083 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1084 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1085 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1086 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1087 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1091 /* Get all statistics of a port */
1093 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1096 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1099 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1101 /* Get statistics of struct i40e_eth_stats */
1102 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1103 I40E_GLPRT_GORCL(hw->port),
1104 pf->offset_loaded, &os->eth.rx_bytes,
1106 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1107 I40E_GLPRT_UPRCL(hw->port),
1108 pf->offset_loaded, &os->eth.rx_unicast,
1109 &ns->eth.rx_unicast);
1110 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1111 I40E_GLPRT_MPRCL(hw->port),
1112 pf->offset_loaded, &os->eth.rx_multicast,
1113 &ns->eth.rx_multicast);
1114 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1115 I40E_GLPRT_BPRCL(hw->port),
1116 pf->offset_loaded, &os->eth.rx_broadcast,
1117 &ns->eth.rx_broadcast);
1118 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1119 pf->offset_loaded, &os->eth.rx_discards,
1120 &ns->eth.rx_discards);
1121 /* GLPRT_REPC not supported */
1122 /* GLPRT_RMPC not supported */
1123 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1125 &os->eth.rx_unknown_protocol,
1126 &ns->eth.rx_unknown_protocol);
1127 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1128 I40E_GLPRT_GOTCL(hw->port),
1129 pf->offset_loaded, &os->eth.tx_bytes,
1131 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1132 I40E_GLPRT_UPTCL(hw->port),
1133 pf->offset_loaded, &os->eth.tx_unicast,
1134 &ns->eth.tx_unicast);
1135 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1136 I40E_GLPRT_MPTCL(hw->port),
1137 pf->offset_loaded, &os->eth.tx_multicast,
1138 &ns->eth.tx_multicast);
1139 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1140 I40E_GLPRT_BPTCL(hw->port),
1141 pf->offset_loaded, &os->eth.tx_broadcast,
1142 &ns->eth.tx_broadcast);
1143 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1144 pf->offset_loaded, &os->eth.tx_discards,
1145 &ns->eth.tx_discards);
1146 /* GLPRT_TEPC not supported */
1148 /* additional port specific stats */
1149 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1150 pf->offset_loaded, &os->tx_dropped_link_down,
1151 &ns->tx_dropped_link_down);
1152 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1153 pf->offset_loaded, &os->crc_errors,
1155 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1156 pf->offset_loaded, &os->illegal_bytes,
1157 &ns->illegal_bytes);
1158 /* GLPRT_ERRBC not supported */
1159 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1160 pf->offset_loaded, &os->mac_local_faults,
1161 &ns->mac_local_faults);
1162 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1163 pf->offset_loaded, &os->mac_remote_faults,
1164 &ns->mac_remote_faults);
1165 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1166 pf->offset_loaded, &os->rx_length_errors,
1167 &ns->rx_length_errors);
1168 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1169 pf->offset_loaded, &os->link_xon_rx,
1171 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1172 pf->offset_loaded, &os->link_xoff_rx,
1174 for (i = 0; i < 8; i++) {
1175 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1177 &os->priority_xon_rx[i],
1178 &ns->priority_xon_rx[i]);
1179 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1181 &os->priority_xoff_rx[i],
1182 &ns->priority_xoff_rx[i]);
1184 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1185 pf->offset_loaded, &os->link_xon_tx,
1187 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1188 pf->offset_loaded, &os->link_xoff_tx,
1190 for (i = 0; i < 8; i++) {
1191 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1193 &os->priority_xon_tx[i],
1194 &ns->priority_xon_tx[i]);
1195 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1197 &os->priority_xoff_tx[i],
1198 &ns->priority_xoff_tx[i]);
1199 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1201 &os->priority_xon_2_xoff[i],
1202 &ns->priority_xon_2_xoff[i]);
1204 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1205 I40E_GLPRT_PRC64L(hw->port),
1206 pf->offset_loaded, &os->rx_size_64,
1208 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1209 I40E_GLPRT_PRC127L(hw->port),
1210 pf->offset_loaded, &os->rx_size_127,
1212 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1213 I40E_GLPRT_PRC255L(hw->port),
1214 pf->offset_loaded, &os->rx_size_255,
1216 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1217 I40E_GLPRT_PRC511L(hw->port),
1218 pf->offset_loaded, &os->rx_size_511,
1220 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1221 I40E_GLPRT_PRC1023L(hw->port),
1222 pf->offset_loaded, &os->rx_size_1023,
1224 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1225 I40E_GLPRT_PRC1522L(hw->port),
1226 pf->offset_loaded, &os->rx_size_1522,
1228 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1229 I40E_GLPRT_PRC9522L(hw->port),
1230 pf->offset_loaded, &os->rx_size_big,
1232 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1233 pf->offset_loaded, &os->rx_undersize,
1235 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1236 pf->offset_loaded, &os->rx_fragments,
1238 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1239 pf->offset_loaded, &os->rx_oversize,
1241 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1242 pf->offset_loaded, &os->rx_jabber,
1244 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1245 I40E_GLPRT_PTC64L(hw->port),
1246 pf->offset_loaded, &os->tx_size_64,
1248 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1249 I40E_GLPRT_PTC127L(hw->port),
1250 pf->offset_loaded, &os->tx_size_127,
1252 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1253 I40E_GLPRT_PTC255L(hw->port),
1254 pf->offset_loaded, &os->tx_size_255,
1256 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1257 I40E_GLPRT_PTC511L(hw->port),
1258 pf->offset_loaded, &os->tx_size_511,
1260 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1261 I40E_GLPRT_PTC1023L(hw->port),
1262 pf->offset_loaded, &os->tx_size_1023,
1264 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1265 I40E_GLPRT_PTC1522L(hw->port),
1266 pf->offset_loaded, &os->tx_size_1522,
1268 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1269 I40E_GLPRT_PTC9522L(hw->port),
1270 pf->offset_loaded, &os->tx_size_big,
1272 /* GLPRT_MSPDC not supported */
1273 /* GLPRT_XEC not supported */
1275 pf->offset_loaded = true;
1277 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1278 ns->eth.rx_broadcast;
1279 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1280 ns->eth.tx_broadcast;
1281 stats->ibytes = ns->eth.rx_bytes;
1282 stats->obytes = ns->eth.tx_bytes;
1283 stats->oerrors = ns->eth.tx_errors;
1284 stats->imcasts = ns->eth.rx_multicast;
1287 i40e_update_vsi_stats(pf->main_vsi);
1289 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1290 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1291 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1292 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1293 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1294 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1295 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1296 ns->eth.rx_unknown_protocol);
1297 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1298 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1299 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1300 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1301 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1302 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1304 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1305 ns->tx_dropped_link_down);
1306 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1307 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1309 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1310 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1311 ns->mac_local_faults);
1312 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1313 ns->mac_remote_faults);
1314 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1315 ns->rx_length_errors);
1316 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1317 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1318 for (i = 0; i < 8; i++) {
1319 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1320 i, ns->priority_xon_rx[i]);
1321 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1322 i, ns->priority_xoff_rx[i]);
1324 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1325 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1326 for (i = 0; i < 8; i++) {
1327 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1328 i, ns->priority_xon_tx[i]);
1329 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1330 i, ns->priority_xoff_tx[i]);
1331 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1332 i, ns->priority_xon_2_xoff[i]);
1334 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1335 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1336 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1337 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1338 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1339 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1340 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1341 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1342 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1343 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1344 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1345 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1346 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1347 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1348 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1349 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1350 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1351 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1352 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1353 ns->mac_short_packet_dropped);
1354 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1355 ns->checksum_error);
1356 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1359 /* Reset the statistics */
1361 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1363 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1365 /* It results in reloading the start point of each counter */
1366 pf->offset_loaded = false;
1370 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1371 __rte_unused uint16_t queue_id,
1372 __rte_unused uint8_t stat_idx,
1373 __rte_unused uint8_t is_rx)
1375 PMD_INIT_FUNC_TRACE();
1381 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1383 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1384 struct i40e_vsi *vsi = pf->main_vsi;
1386 dev_info->max_rx_queues = vsi->nb_qps;
1387 dev_info->max_tx_queues = vsi->nb_qps;
1388 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1389 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1390 dev_info->max_mac_addrs = vsi->max_macaddrs;
1391 dev_info->max_vfs = dev->pci_dev->max_vfs;
1392 dev_info->rx_offload_capa =
1393 DEV_RX_OFFLOAD_VLAN_STRIP |
1394 DEV_RX_OFFLOAD_IPV4_CKSUM |
1395 DEV_RX_OFFLOAD_UDP_CKSUM |
1396 DEV_RX_OFFLOAD_TCP_CKSUM;
1397 dev_info->tx_offload_capa =
1398 DEV_TX_OFFLOAD_VLAN_INSERT |
1399 DEV_TX_OFFLOAD_IPV4_CKSUM |
1400 DEV_TX_OFFLOAD_UDP_CKSUM |
1401 DEV_TX_OFFLOAD_TCP_CKSUM |
1402 DEV_TX_OFFLOAD_SCTP_CKSUM;
1404 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1406 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1407 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1408 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1410 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1414 dev_info->default_txconf = (struct rte_eth_txconf) {
1416 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1417 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1418 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1420 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1421 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1422 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1428 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431 struct i40e_vsi *vsi = pf->main_vsi;
1432 PMD_INIT_FUNC_TRACE();
1435 return i40e_vsi_add_vlan(vsi, vlan_id);
1437 return i40e_vsi_delete_vlan(vsi, vlan_id);
1441 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1442 __rte_unused uint16_t tpid)
1444 PMD_INIT_FUNC_TRACE();
1448 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1450 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1451 struct i40e_vsi *vsi = pf->main_vsi;
1453 if (mask & ETH_VLAN_STRIP_MASK) {
1454 /* Enable or disable VLAN stripping */
1455 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1456 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1458 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1461 if (mask & ETH_VLAN_EXTEND_MASK) {
1462 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1463 i40e_vsi_config_double_vlan(vsi, TRUE);
1465 i40e_vsi_config_double_vlan(vsi, FALSE);
1470 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1471 __rte_unused uint16_t queue,
1472 __rte_unused int on)
1474 PMD_INIT_FUNC_TRACE();
1478 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1481 struct i40e_vsi *vsi = pf->main_vsi;
1482 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1483 struct i40e_vsi_vlan_pvid_info info;
1485 memset(&info, 0, sizeof(info));
1488 info.config.pvid = pvid;
1490 info.config.reject.tagged =
1491 data->dev_conf.txmode.hw_vlan_reject_tagged;
1492 info.config.reject.untagged =
1493 data->dev_conf.txmode.hw_vlan_reject_untagged;
1496 return i40e_vsi_vlan_pvid_set(vsi, &info);
1500 i40e_dev_led_on(struct rte_eth_dev *dev)
1502 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 uint32_t mode = i40e_led_get(hw);
1506 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1512 i40e_dev_led_off(struct rte_eth_dev *dev)
1514 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 uint32_t mode = i40e_led_get(hw);
1518 i40e_led_set(hw, 0, false);
1524 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1525 __rte_unused struct rte_eth_fc_conf *fc_conf)
1527 PMD_INIT_FUNC_TRACE();
1533 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1534 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1536 PMD_INIT_FUNC_TRACE();
1541 /* Add a MAC address, and update filters */
1543 i40e_macaddr_add(struct rte_eth_dev *dev,
1544 struct ether_addr *mac_addr,
1545 __attribute__((unused)) uint32_t index,
1546 __attribute__((unused)) uint32_t pool)
1548 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1549 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550 struct i40e_vsi *vsi = pf->main_vsi;
1551 struct ether_addr old_mac;
1554 if (!is_valid_assigned_ether_addr(mac_addr)) {
1555 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1559 if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1560 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1564 /* Write mac address */
1565 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1566 mac_addr->addr_bytes, NULL);
1567 if (ret != I40E_SUCCESS) {
1568 PMD_DRV_LOG(ERR, "Failed to write mac address");
1572 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1573 (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1576 ret = i40e_vsi_add_mac(vsi, mac_addr);
1577 if (ret != I40E_SUCCESS) {
1578 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1582 ether_addr_copy(mac_addr, &pf->dev_addr);
1583 i40e_vsi_delete_mac(vsi, &old_mac);
1586 /* Remove a MAC address, and update filters */
1588 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1591 struct i40e_vsi *vsi = pf->main_vsi;
1592 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1593 struct ether_addr *macaddr;
1595 struct i40e_hw *hw =
1596 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598 if (index >= vsi->max_macaddrs)
1601 macaddr = &(data->mac_addrs[index]);
1602 if (!is_valid_assigned_ether_addr(macaddr))
1605 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1606 hw->mac.perm_addr, NULL);
1607 if (ret != I40E_SUCCESS) {
1608 PMD_DRV_LOG(ERR, "Failed to write mac address");
1612 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1614 ret = i40e_vsi_delete_mac(vsi, macaddr);
1615 if (ret != I40E_SUCCESS)
1618 /* Clear device address as it has been removed */
1619 if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1620 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1624 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1625 struct rte_eth_rss_reta *reta_conf)
1627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1631 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1633 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1635 mask = (uint8_t)((reta_conf->mask_hi >>
1644 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1646 for (j = 0, lut = 0; j < 4; j++) {
1647 if (mask & (0x1 << j))
1648 lut |= reta_conf->reta[i + j] << (8 * j);
1650 lut |= l & (0xFF << (8 * j));
1652 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1659 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1660 struct rte_eth_rss_reta *reta_conf)
1662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1666 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1668 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1670 mask = (uint8_t)((reta_conf->mask_hi >>
1676 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1677 for (j = 0; j < 4; j++) {
1678 if (mask & (0x1 << j))
1679 reta_conf->reta[i + j] =
1680 (uint8_t)((lut >> (8 * j)) & 0xFF);
1688 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1689 * @hw: pointer to the HW structure
1690 * @mem: pointer to mem struct to fill out
1691 * @size: size of memory requested
1692 * @alignment: what to align the allocation to
1694 enum i40e_status_code
1695 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1696 struct i40e_dma_mem *mem,
1700 static uint64_t id = 0;
1701 const struct rte_memzone *mz = NULL;
1702 char z_name[RTE_MEMZONE_NAMESIZE];
1705 return I40E_ERR_PARAM;
1708 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1709 #ifdef RTE_LIBRTE_XEN_DOM0
1710 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1713 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1716 return I40E_ERR_NO_MEMORY;
1721 #ifdef RTE_LIBRTE_XEN_DOM0
1722 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1724 mem->pa = mz->phys_addr;
1727 return I40E_SUCCESS;
1731 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1732 * @hw: pointer to the HW structure
1733 * @mem: ptr to mem struct to free
1735 enum i40e_status_code
1736 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1737 struct i40e_dma_mem *mem)
1739 if (!mem || !mem->va)
1740 return I40E_ERR_PARAM;
1745 return I40E_SUCCESS;
1749 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1750 * @hw: pointer to the HW structure
1751 * @mem: pointer to mem struct to fill out
1752 * @size: size of memory requested
1754 enum i40e_status_code
1755 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1756 struct i40e_virt_mem *mem,
1760 return I40E_ERR_PARAM;
1763 mem->va = rte_zmalloc("i40e", size, 0);
1766 return I40E_SUCCESS;
1768 return I40E_ERR_NO_MEMORY;
1772 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1773 * @hw: pointer to the HW structure
1774 * @mem: pointer to mem struct to free
1776 enum i40e_status_code
1777 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1778 struct i40e_virt_mem *mem)
1781 return I40E_ERR_PARAM;
1786 return I40E_SUCCESS;
1790 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1792 rte_spinlock_init(&sp->spinlock);
1796 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1798 rte_spinlock_lock(&sp->spinlock);
1802 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1804 rte_spinlock_unlock(&sp->spinlock);
1808 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1814 * Get the hardware capabilities, which will be parsed
1815 * and saved into struct i40e_hw.
1818 i40e_get_cap(struct i40e_hw *hw)
1820 struct i40e_aqc_list_capabilities_element_resp *buf;
1821 uint16_t len, size = 0;
1824 /* Calculate a huge enough buff for saving response data temporarily */
1825 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1826 I40E_MAX_CAP_ELE_NUM;
1827 buf = rte_zmalloc("i40e", len, 0);
1829 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1830 return I40E_ERR_NO_MEMORY;
1833 /* Get, parse the capabilities and save it to hw */
1834 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1835 i40e_aqc_opc_list_func_capabilities, NULL);
1836 if (ret != I40E_SUCCESS)
1837 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1839 /* Free the temporary buffer after being used */
1846 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1848 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1849 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1850 uint16_t sum_queues = 0, sum_vsis;
1852 /* First check if FW support SRIOV */
1853 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1854 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1858 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1859 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1860 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1861 /* Allocate queues for pf */
1862 if (hw->func_caps.rss) {
1863 pf->flags |= I40E_FLAG_RSS;
1864 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1865 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1866 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1869 sum_queues = pf->lan_nb_qps;
1870 /* Default VSI is not counted in */
1872 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1874 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1875 pf->flags |= I40E_FLAG_SRIOV;
1876 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1877 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1878 PMD_INIT_LOG(ERR, "Config VF number %u, "
1879 "max supported %u.",
1880 dev->pci_dev->max_vfs,
1881 hw->func_caps.num_vfs);
1884 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1885 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1886 "max support %u queues.",
1887 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1890 pf->vf_num = dev->pci_dev->max_vfs;
1891 sum_queues += pf->vf_nb_qps * pf->vf_num;
1892 sum_vsis += pf->vf_num;
1893 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1894 pf->vf_num, pf->vf_nb_qps);
1898 if (hw->func_caps.vmdq) {
1899 pf->flags |= I40E_FLAG_VMDQ;
1900 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1901 sum_queues += pf->vmdq_nb_qps;
1903 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1906 if (hw->func_caps.fd) {
1907 pf->flags |= I40E_FLAG_FDIR;
1908 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1910 * Each flow director consumes one VSI and one queue,
1911 * but can't calculate out predictably here.
1915 if (sum_vsis > pf->max_num_vsi ||
1916 sum_queues > hw->func_caps.num_rx_qp) {
1917 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1918 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1919 pf->max_num_vsi, sum_vsis);
1920 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1921 hw->func_caps.num_rx_qp, sum_queues);
1925 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1927 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1928 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1929 sum_vsis, hw->func_caps.num_msix_vectors);
1932 return I40E_SUCCESS;
1936 i40e_pf_get_switch_config(struct i40e_pf *pf)
1938 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1939 struct i40e_aqc_get_switch_config_resp *switch_config;
1940 struct i40e_aqc_switch_config_element_resp *element;
1941 uint16_t start_seid = 0, num_reported;
1944 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1945 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1946 if (!switch_config) {
1947 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1951 /* Get the switch configurations */
1952 ret = i40e_aq_get_switch_config(hw, switch_config,
1953 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1954 if (ret != I40E_SUCCESS) {
1955 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1958 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1959 if (num_reported != 1) { /* The number should be 1 */
1960 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1964 /* Parse the switch configuration elements */
1965 element = &(switch_config->element[0]);
1966 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1967 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1968 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1970 PMD_DRV_LOG(INFO, "Unknown element type");
1973 rte_free(switch_config);
1979 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1982 struct pool_entry *entry;
1984 if (pool == NULL || num == 0)
1987 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1988 if (entry == NULL) {
1989 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1993 /* queue heap initialize */
1994 pool->num_free = num;
1995 pool->num_alloc = 0;
1997 LIST_INIT(&pool->alloc_list);
1998 LIST_INIT(&pool->free_list);
2000 /* Initialize element */
2004 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2009 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2011 struct pool_entry *entry;
2016 LIST_FOREACH(entry, &pool->alloc_list, next) {
2017 LIST_REMOVE(entry, next);
2021 LIST_FOREACH(entry, &pool->free_list, next) {
2022 LIST_REMOVE(entry, next);
2027 pool->num_alloc = 0;
2029 LIST_INIT(&pool->alloc_list);
2030 LIST_INIT(&pool->free_list);
2034 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2037 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2038 uint32_t pool_offset;
2042 PMD_DRV_LOG(ERR, "Invalid parameter");
2046 pool_offset = base - pool->base;
2047 /* Lookup in alloc list */
2048 LIST_FOREACH(entry, &pool->alloc_list, next) {
2049 if (entry->base == pool_offset) {
2050 valid_entry = entry;
2051 LIST_REMOVE(entry, next);
2056 /* Not find, return */
2057 if (valid_entry == NULL) {
2058 PMD_DRV_LOG(ERR, "Failed to find entry");
2063 * Found it, move it to free list and try to merge.
2064 * In order to make merge easier, always sort it by qbase.
2065 * Find adjacent prev and last entries.
2068 LIST_FOREACH(entry, &pool->free_list, next) {
2069 if (entry->base > valid_entry->base) {
2077 /* Try to merge with next one*/
2079 /* Merge with next one */
2080 if (valid_entry->base + valid_entry->len == next->base) {
2081 next->base = valid_entry->base;
2082 next->len += valid_entry->len;
2083 rte_free(valid_entry);
2090 /* Merge with previous one */
2091 if (prev->base + prev->len == valid_entry->base) {
2092 prev->len += valid_entry->len;
2093 /* If it merge with next one, remove next node */
2095 LIST_REMOVE(valid_entry, next);
2096 rte_free(valid_entry);
2098 rte_free(valid_entry);
2104 /* Not find any entry to merge, insert */
2107 LIST_INSERT_AFTER(prev, valid_entry, next);
2108 else if (next != NULL)
2109 LIST_INSERT_BEFORE(next, valid_entry, next);
2110 else /* It's empty list, insert to head */
2111 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2114 pool->num_free += valid_entry->len;
2115 pool->num_alloc -= valid_entry->len;
2121 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2124 struct pool_entry *entry, *valid_entry;
2126 if (pool == NULL || num == 0) {
2127 PMD_DRV_LOG(ERR, "Invalid parameter");
2131 if (pool->num_free < num) {
2132 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2133 num, pool->num_free);
2138 /* Lookup in free list and find most fit one */
2139 LIST_FOREACH(entry, &pool->free_list, next) {
2140 if (entry->len >= num) {
2142 if (entry->len == num) {
2143 valid_entry = entry;
2146 if (valid_entry == NULL || valid_entry->len > entry->len)
2147 valid_entry = entry;
2151 /* Not find one to satisfy the request, return */
2152 if (valid_entry == NULL) {
2153 PMD_DRV_LOG(ERR, "No valid entry found");
2157 * The entry have equal queue number as requested,
2158 * remove it from alloc_list.
2160 if (valid_entry->len == num) {
2161 LIST_REMOVE(valid_entry, next);
2164 * The entry have more numbers than requested,
2165 * create a new entry for alloc_list and minus its
2166 * queue base and number in free_list.
2168 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2169 if (entry == NULL) {
2170 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2174 entry->base = valid_entry->base;
2176 valid_entry->base += num;
2177 valid_entry->len -= num;
2178 valid_entry = entry;
2181 /* Insert it into alloc list, not sorted */
2182 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2184 pool->num_free -= valid_entry->len;
2185 pool->num_alloc += valid_entry->len;
2187 return (valid_entry->base + pool->base);
2191 * bitmap_is_subset - Check whether src2 is subset of src1
2194 bitmap_is_subset(uint8_t src1, uint8_t src2)
2196 return !((src1 ^ src2) & src2);
2200 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2202 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2204 /* If DCB is not supported, only default TC is supported */
2205 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2206 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2210 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2211 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2212 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2216 return I40E_SUCCESS;
2220 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2221 struct i40e_vsi_vlan_pvid_info *info)
2224 struct i40e_vsi_context ctxt;
2225 uint8_t vlan_flags = 0;
2228 if (vsi == NULL || info == NULL) {
2229 PMD_DRV_LOG(ERR, "invalid parameters");
2230 return I40E_ERR_PARAM;
2234 vsi->info.pvid = info->config.pvid;
2236 * If insert pvid is enabled, only tagged pkts are
2237 * allowed to be sent out.
2239 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2240 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2243 if (info->config.reject.tagged == 0)
2244 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2246 if (info->config.reject.untagged == 0)
2247 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2249 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2250 I40E_AQ_VSI_PVLAN_MODE_MASK);
2251 vsi->info.port_vlan_flags |= vlan_flags;
2252 vsi->info.valid_sections =
2253 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2254 memset(&ctxt, 0, sizeof(ctxt));
2255 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2256 ctxt.seid = vsi->seid;
2258 hw = I40E_VSI_TO_HW(vsi);
2259 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2260 if (ret != I40E_SUCCESS)
2261 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2267 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2269 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2271 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2273 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2274 if (ret != I40E_SUCCESS)
2278 PMD_DRV_LOG(ERR, "seid not valid");
2282 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2283 tc_bw_data.tc_valid_bits = enabled_tcmap;
2284 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2285 tc_bw_data.tc_bw_credits[i] =
2286 (enabled_tcmap & (1 << i)) ? 1 : 0;
2288 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2289 if (ret != I40E_SUCCESS) {
2290 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2294 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2295 sizeof(vsi->info.qs_handle));
2296 return I40E_SUCCESS;
2300 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2301 struct i40e_aqc_vsi_properties_data *info,
2302 uint8_t enabled_tcmap)
2304 int ret, total_tc = 0, i;
2305 uint16_t qpnum_per_tc, bsf, qp_idx;
2307 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2308 if (ret != I40E_SUCCESS)
2311 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2312 if (enabled_tcmap & (1 << i))
2314 vsi->enabled_tc = enabled_tcmap;
2316 /* Number of queues per enabled TC */
2317 qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2318 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2319 bsf = rte_bsf32(qpnum_per_tc);
2321 /* Adjust the queue number to actual queues that can be applied */
2322 vsi->nb_qps = qpnum_per_tc * total_tc;
2325 * Configure TC and queue mapping parameters, for enabled TC,
2326 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2327 * default queue will serve it.
2330 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2331 if (vsi->enabled_tc & (1 << i)) {
2332 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2333 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2334 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2335 qp_idx += qpnum_per_tc;
2337 info->tc_mapping[i] = 0;
2340 /* Associate queue number with VSI */
2341 if (vsi->type == I40E_VSI_SRIOV) {
2342 info->mapping_flags |=
2343 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2344 for (i = 0; i < vsi->nb_qps; i++)
2345 info->queue_mapping[i] =
2346 rte_cpu_to_le_16(vsi->base_queue + i);
2348 info->mapping_flags |=
2349 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2350 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2352 info->valid_sections =
2353 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2355 return I40E_SUCCESS;
2359 i40e_veb_release(struct i40e_veb *veb)
2361 struct i40e_vsi *vsi;
2364 if (veb == NULL || veb->associate_vsi == NULL)
2367 if (!TAILQ_EMPTY(&veb->head)) {
2368 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2372 vsi = veb->associate_vsi;
2373 hw = I40E_VSI_TO_HW(vsi);
2375 vsi->uplink_seid = veb->uplink_seid;
2376 i40e_aq_delete_element(hw, veb->seid, NULL);
2379 return I40E_SUCCESS;
2383 static struct i40e_veb *
2384 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2386 struct i40e_veb *veb;
2390 if (NULL == pf || vsi == NULL) {
2391 PMD_DRV_LOG(ERR, "veb setup failed, "
2392 "associated VSI shouldn't null");
2395 hw = I40E_PF_TO_HW(pf);
2397 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2399 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2403 veb->associate_vsi = vsi;
2404 TAILQ_INIT(&veb->head);
2405 veb->uplink_seid = vsi->uplink_seid;
2407 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2408 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2410 if (ret != I40E_SUCCESS) {
2411 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2412 hw->aq.asq_last_status);
2416 /* get statistics index */
2417 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2418 &veb->stats_idx, NULL, NULL, NULL);
2419 if (ret != I40E_SUCCESS) {
2420 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2421 hw->aq.asq_last_status);
2425 /* Get VEB bandwidth, to be implemented */
2426 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2427 vsi->uplink_seid = veb->seid;
2436 i40e_vsi_release(struct i40e_vsi *vsi)
2440 struct i40e_vsi_list *vsi_list;
2442 struct i40e_mac_filter *f;
2445 return I40E_SUCCESS;
2447 pf = I40E_VSI_TO_PF(vsi);
2448 hw = I40E_VSI_TO_HW(vsi);
2450 /* VSI has child to attach, release child first */
2452 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2453 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2455 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2457 i40e_veb_release(vsi->veb);
2460 /* Remove all macvlan filters of the VSI */
2461 i40e_vsi_remove_all_macvlan_filter(vsi);
2462 TAILQ_FOREACH(f, &vsi->mac_list, next)
2465 if (vsi->type != I40E_VSI_MAIN) {
2466 /* Remove vsi from parent's sibling list */
2467 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2468 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2469 return I40E_ERR_PARAM;
2471 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2472 &vsi->sib_vsi_list, list);
2474 /* Remove all switch element of the VSI */
2475 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2476 if (ret != I40E_SUCCESS)
2477 PMD_DRV_LOG(ERR, "Failed to delete element");
2479 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2481 if (vsi->type != I40E_VSI_SRIOV)
2482 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2485 return I40E_SUCCESS;
2489 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2491 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2492 struct i40e_aqc_remove_macvlan_element_data def_filter;
2495 if (vsi->type != I40E_VSI_MAIN)
2496 return I40E_ERR_CONFIG;
2497 memset(&def_filter, 0, sizeof(def_filter));
2498 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2500 def_filter.vlan_tag = 0;
2501 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2502 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2503 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2504 if (ret != I40E_SUCCESS) {
2505 struct i40e_mac_filter *f;
2507 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2509 /* It needs to add the permanent mac into mac list */
2510 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2512 PMD_DRV_LOG(ERR, "failed to allocate memory");
2513 return I40E_ERR_NO_MEMORY;
2515 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2517 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2523 return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2527 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2529 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2530 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2531 struct i40e_hw *hw = &vsi->adapter->hw;
2535 memset(&bw_config, 0, sizeof(bw_config));
2536 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2537 if (ret != I40E_SUCCESS) {
2538 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2539 hw->aq.asq_last_status);
2543 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2544 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2545 &ets_sla_config, NULL);
2546 if (ret != I40E_SUCCESS) {
2547 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2548 "configuration %u", hw->aq.asq_last_status);
2552 /* Not store the info yet, just print out */
2553 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2554 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2555 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2556 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2557 ets_sla_config.share_credits[i]);
2558 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2559 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2560 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2561 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2570 i40e_vsi_setup(struct i40e_pf *pf,
2571 enum i40e_vsi_type type,
2572 struct i40e_vsi *uplink_vsi,
2573 uint16_t user_param)
2575 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2576 struct i40e_vsi *vsi;
2578 struct i40e_vsi_context ctxt;
2579 struct ether_addr broadcast =
2580 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2582 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2583 PMD_DRV_LOG(ERR, "VSI setup failed, "
2584 "VSI link shouldn't be NULL");
2588 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2589 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2590 "uplink VSI should be NULL");
2594 /* If uplink vsi didn't setup VEB, create one first */
2595 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2596 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2598 if (NULL == uplink_vsi->veb) {
2599 PMD_DRV_LOG(ERR, "VEB setup failed");
2604 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2606 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2609 TAILQ_INIT(&vsi->mac_list);
2611 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2612 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2613 vsi->parent_vsi = uplink_vsi;
2614 vsi->user_param = user_param;
2615 /* Allocate queues */
2616 switch (vsi->type) {
2617 case I40E_VSI_MAIN :
2618 vsi->nb_qps = pf->lan_nb_qps;
2620 case I40E_VSI_SRIOV :
2621 vsi->nb_qps = pf->vf_nb_qps;
2626 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2628 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2632 vsi->base_queue = ret;
2634 /* VF has MSIX interrupt in VF range, don't allocate here */
2635 if (type != I40E_VSI_SRIOV) {
2636 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2638 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2639 goto fail_queue_alloc;
2641 vsi->msix_intr = ret;
2645 if (type == I40E_VSI_MAIN) {
2646 /* For main VSI, no need to add since it's default one */
2647 vsi->uplink_seid = pf->mac_seid;
2648 vsi->seid = pf->main_vsi_seid;
2649 /* Bind queues with specific MSIX interrupt */
2651 * Needs 2 interrupt at least, one for misc cause which will
2652 * enabled from OS side, Another for queues binding the
2653 * interrupt from device side only.
2656 /* Get default VSI parameters from hardware */
2657 memset(&ctxt, 0, sizeof(ctxt));
2658 ctxt.seid = vsi->seid;
2659 ctxt.pf_num = hw->pf_id;
2660 ctxt.uplink_seid = vsi->uplink_seid;
2662 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2663 if (ret != I40E_SUCCESS) {
2664 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2665 goto fail_msix_alloc;
2667 (void)rte_memcpy(&vsi->info, &ctxt.info,
2668 sizeof(struct i40e_aqc_vsi_properties_data));
2669 vsi->vsi_id = ctxt.vsi_number;
2670 vsi->info.valid_sections = 0;
2672 /* Configure tc, enabled TC0 only */
2673 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2675 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2676 goto fail_msix_alloc;
2679 /* TC, queue mapping */
2680 memset(&ctxt, 0, sizeof(ctxt));
2681 vsi->info.valid_sections |=
2682 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2683 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2684 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2685 (void)rte_memcpy(&ctxt.info, &vsi->info,
2686 sizeof(struct i40e_aqc_vsi_properties_data));
2687 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2688 I40E_DEFAULT_TCMAP);
2689 if (ret != I40E_SUCCESS) {
2690 PMD_DRV_LOG(ERR, "Failed to configure "
2691 "TC queue mapping");
2692 goto fail_msix_alloc;
2694 ctxt.seid = vsi->seid;
2695 ctxt.pf_num = hw->pf_id;
2696 ctxt.uplink_seid = vsi->uplink_seid;
2699 /* Update VSI parameters */
2700 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2701 if (ret != I40E_SUCCESS) {
2702 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2703 goto fail_msix_alloc;
2706 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2707 sizeof(vsi->info.tc_mapping));
2708 (void)rte_memcpy(&vsi->info.queue_mapping,
2709 &ctxt.info.queue_mapping,
2710 sizeof(vsi->info.queue_mapping));
2711 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2712 vsi->info.valid_sections = 0;
2714 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2718 * Updating default filter settings are necessary to prevent
2719 * reception of tagged packets.
2720 * Some old firmware configurations load a default macvlan
2721 * filter which accepts both tagged and untagged packets.
2722 * The updating is to use a normal filter instead if needed.
2723 * For NVM 4.2.2 or after, the updating is not needed anymore.
2724 * The firmware with correct configurations load the default
2725 * macvlan filter which is expected and cannot be removed.
2727 i40e_update_default_filter_setting(vsi);
2728 } else if (type == I40E_VSI_SRIOV) {
2729 memset(&ctxt, 0, sizeof(ctxt));
2731 * For other VSI, the uplink_seid equals to uplink VSI's
2732 * uplink_seid since they share same VEB
2734 vsi->uplink_seid = uplink_vsi->uplink_seid;
2735 ctxt.pf_num = hw->pf_id;
2736 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2737 ctxt.uplink_seid = vsi->uplink_seid;
2738 ctxt.connection_type = 0x1;
2739 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2741 /* Configure switch ID */
2742 ctxt.info.valid_sections |=
2743 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2744 ctxt.info.switch_id =
2745 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2746 /* Configure port/vlan */
2747 ctxt.info.valid_sections |=
2748 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2749 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2750 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2751 I40E_DEFAULT_TCMAP);
2752 if (ret != I40E_SUCCESS) {
2753 PMD_DRV_LOG(ERR, "Failed to configure "
2754 "TC queue mapping");
2755 goto fail_msix_alloc;
2757 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2758 ctxt.info.valid_sections |=
2759 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2761 * Since VSI is not created yet, only configure parameter,
2762 * will add vsi below.
2766 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2767 goto fail_msix_alloc;
2770 if (vsi->type != I40E_VSI_MAIN) {
2771 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2773 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2774 hw->aq.asq_last_status);
2775 goto fail_msix_alloc;
2777 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2778 vsi->info.valid_sections = 0;
2779 vsi->seid = ctxt.seid;
2780 vsi->vsi_id = ctxt.vsi_number;
2781 vsi->sib_vsi_list.vsi = vsi;
2782 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2783 &vsi->sib_vsi_list, list);
2786 /* MAC/VLAN configuration */
2787 ret = i40e_vsi_add_mac(vsi, &broadcast);
2788 if (ret != I40E_SUCCESS) {
2789 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2790 goto fail_msix_alloc;
2793 /* Get VSI BW information */
2794 i40e_vsi_dump_bw_config(vsi);
2797 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2799 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2805 /* Configure vlan stripping on or off */
2807 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2809 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2810 struct i40e_vsi_context ctxt;
2812 int ret = I40E_SUCCESS;
2814 /* Check if it has been already on or off */
2815 if (vsi->info.valid_sections &
2816 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2818 if ((vsi->info.port_vlan_flags &
2819 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2820 return 0; /* already on */
2822 if ((vsi->info.port_vlan_flags &
2823 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2824 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2825 return 0; /* already off */
2830 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2832 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2833 vsi->info.valid_sections =
2834 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2835 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2836 vsi->info.port_vlan_flags |= vlan_flags;
2837 ctxt.seid = vsi->seid;
2838 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2839 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2841 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2842 on ? "enable" : "disable");
2848 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2850 struct rte_eth_dev_data *data = dev->data;
2853 /* Apply vlan offload setting */
2854 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2856 /* Apply double-vlan setting, not implemented yet */
2858 /* Apply pvid setting */
2859 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2860 data->dev_conf.txmode.hw_vlan_insert_pvid);
2862 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2868 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2870 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2872 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2876 i40e_update_flow_control(struct i40e_hw *hw)
2878 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2879 struct i40e_link_status link_status;
2880 uint32_t rxfc = 0, txfc = 0, reg;
2884 memset(&link_status, 0, sizeof(link_status));
2885 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2886 if (ret != I40E_SUCCESS) {
2887 PMD_DRV_LOG(ERR, "Failed to get link status information");
2888 goto write_reg; /* Disable flow control */
2891 an_info = hw->phy.link_info.an_info;
2892 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2893 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2894 ret = I40E_ERR_NOT_READY;
2895 goto write_reg; /* Disable flow control */
2898 * If link auto negotiation is enabled, flow control needs to
2899 * be configured according to it
2901 switch (an_info & I40E_LINK_PAUSE_RXTX) {
2902 case I40E_LINK_PAUSE_RXTX:
2905 hw->fc.current_mode = I40E_FC_FULL;
2907 case I40E_AQ_LINK_PAUSE_RX:
2909 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2911 case I40E_AQ_LINK_PAUSE_TX:
2913 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2916 hw->fc.current_mode = I40E_FC_NONE;
2921 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2922 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2923 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2924 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2925 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2926 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2933 i40e_pf_setup(struct i40e_pf *pf)
2935 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2936 struct i40e_filter_control_settings settings;
2937 struct rte_eth_dev_data *dev_data = pf->dev_data;
2938 struct i40e_vsi *vsi;
2941 /* Clear all stats counters */
2942 pf->offset_loaded = FALSE;
2943 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2944 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2946 ret = i40e_pf_get_switch_config(pf);
2947 if (ret != I40E_SUCCESS) {
2948 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2953 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2955 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2956 return I40E_ERR_NOT_READY;
2959 dev_data->nb_rx_queues = vsi->nb_qps;
2960 dev_data->nb_tx_queues = vsi->nb_qps;
2962 /* Configure filter control */
2963 memset(&settings, 0, sizeof(settings));
2964 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2965 /* Enable ethtype and macvlan filters */
2966 settings.enable_ethtype = TRUE;
2967 settings.enable_macvlan = TRUE;
2968 ret = i40e_set_filter_control(hw, &settings);
2970 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2973 /* Update flow control according to the auto negotiation */
2974 i40e_update_flow_control(hw);
2976 return I40E_SUCCESS;
2980 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2986 * Set or clear TX Queue Disable flags,
2987 * which is required by hardware.
2989 i40e_pre_tx_queue_cfg(hw, q_idx, on);
2990 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2992 /* Wait until the request is finished */
2993 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2994 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2995 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2996 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2997 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3003 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3004 return I40E_SUCCESS; /* already on, skip next steps */
3006 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3007 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3009 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3010 return I40E_SUCCESS; /* already off, skip next steps */
3011 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3013 /* Write the register */
3014 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3015 /* Check the result */
3016 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3017 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3018 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3020 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3021 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3024 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3025 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3029 /* Check if it is timeout */
3030 if (j >= I40E_CHK_Q_ENA_COUNT) {
3031 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3032 (on ? "enable" : "disable"), q_idx);
3033 return I40E_ERR_TIMEOUT;
3036 return I40E_SUCCESS;
3039 /* Swith on or off the tx queues */
3041 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3043 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3044 struct i40e_tx_queue *txq;
3045 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3049 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3050 txq = dev_data->tx_queues[i];
3051 /* Don't operate the queue if not configured or
3052 * if starting only per queue */
3053 if (!txq->q_set || (on && txq->tx_deferred_start))
3056 ret = i40e_dev_tx_queue_start(dev, i);
3058 ret = i40e_dev_tx_queue_stop(dev, i);
3059 if ( ret != I40E_SUCCESS)
3063 return I40E_SUCCESS;
3067 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3072 /* Wait until the request is finished */
3073 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3074 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3075 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3076 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3077 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3082 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3083 return I40E_SUCCESS; /* Already on, skip next steps */
3084 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3086 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3087 return I40E_SUCCESS; /* Already off, skip next steps */
3088 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3091 /* Write the register */
3092 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3093 /* Check the result */
3094 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3095 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3096 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3098 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3099 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3102 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3103 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3108 /* Check if it is timeout */
3109 if (j >= I40E_CHK_Q_ENA_COUNT) {
3110 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3111 (on ? "enable" : "disable"), q_idx);
3112 return I40E_ERR_TIMEOUT;
3115 return I40E_SUCCESS;
3117 /* Switch on or off the rx queues */
3119 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3121 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3122 struct i40e_rx_queue *rxq;
3123 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3127 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3128 rxq = dev_data->rx_queues[i];
3129 /* Don't operate the queue if not configured or
3130 * if starting only per queue */
3131 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3134 ret = i40e_dev_rx_queue_start(dev, i);
3136 ret = i40e_dev_rx_queue_stop(dev, i);
3137 if (ret != I40E_SUCCESS)
3141 return I40E_SUCCESS;
3144 /* Switch on or off all the rx/tx queues */
3146 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3151 /* enable rx queues before enabling tx queues */
3152 ret = i40e_vsi_switch_rx_queues(vsi, on);
3154 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3157 ret = i40e_vsi_switch_tx_queues(vsi, on);
3159 /* Stop tx queues before stopping rx queues */
3160 ret = i40e_vsi_switch_tx_queues(vsi, on);
3162 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3165 ret = i40e_vsi_switch_rx_queues(vsi, on);
3171 /* Initialize VSI for TX */
3173 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3175 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3176 struct rte_eth_dev_data *data = pf->dev_data;
3178 uint32_t ret = I40E_SUCCESS;
3180 for (i = 0; i < data->nb_tx_queues; i++) {
3181 ret = i40e_tx_queue_init(data->tx_queues[i]);
3182 if (ret != I40E_SUCCESS)
3189 /* Initialize VSI for RX */
3191 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3193 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3194 struct rte_eth_dev_data *data = pf->dev_data;
3195 int ret = I40E_SUCCESS;
3198 i40e_pf_config_mq_rx(pf);
3199 for (i = 0; i < data->nb_rx_queues; i++) {
3200 ret = i40e_rx_queue_init(data->rx_queues[i]);
3201 if (ret != I40E_SUCCESS) {
3202 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3211 /* Initialize VSI */
3213 i40e_vsi_init(struct i40e_vsi *vsi)
3217 err = i40e_vsi_tx_init(vsi);
3219 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3222 err = i40e_vsi_rx_init(vsi);
3224 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3232 i40e_stat_update_32(struct i40e_hw *hw,
3240 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3244 if (new_data >= *offset)
3245 *stat = (uint64_t)(new_data - *offset);
3247 *stat = (uint64_t)((new_data +
3248 ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3252 i40e_stat_update_48(struct i40e_hw *hw,
3261 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3262 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3263 I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3268 if (new_data >= *offset)
3269 *stat = new_data - *offset;
3271 *stat = (uint64_t)((new_data +
3272 ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3274 *stat &= I40E_48_BIT_MASK;
3279 i40e_pf_disable_irq0(struct i40e_hw *hw)
3281 /* Disable all interrupt types */
3282 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3283 I40E_WRITE_FLUSH(hw);
3288 i40e_pf_enable_irq0(struct i40e_hw *hw)
3290 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3291 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3292 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3293 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3294 I40E_WRITE_FLUSH(hw);
3298 i40e_pf_config_irq0(struct i40e_hw *hw)
3302 /* read pending request and disable first */
3303 i40e_pf_disable_irq0(hw);
3305 * Enable all interrupt error options to detect possible errors,
3306 * other informative int are ignored
3308 enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3309 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3310 I40E_PFINT_ICR0_ENA_GRST_MASK |
3311 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3312 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3313 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3314 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3315 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3317 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3318 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3319 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3321 /* Link no queues with irq0 */
3322 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3323 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3327 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3333 uint32_t index, offset, val;
3338 * Try to find which VF trigger a reset, use absolute VF id to access
3339 * since the reg is global register.
3341 for (i = 0; i < pf->vf_num; i++) {
3342 abs_vf_id = hw->func_caps.vf_base_id + i;
3343 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3344 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3345 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3346 /* VFR event occured */
3347 if (val & (0x1 << offset)) {
3350 /* Clear the event first */
3351 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3353 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3355 * Only notify a VF reset event occured,
3356 * don't trigger another SW reset
3358 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3359 if (ret != I40E_SUCCESS)
3360 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3366 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3368 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369 struct i40e_arq_event_info info;
3370 uint16_t pending, opcode;
3373 info.buf_len = I40E_AQ_BUF_SZ;
3374 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3375 if (!info.msg_buf) {
3376 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3382 ret = i40e_clean_arq_element(hw, &info, &pending);
3384 if (ret != I40E_SUCCESS) {
3385 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3386 "aq_err: %u", hw->aq.asq_last_status);
3389 opcode = rte_le_to_cpu_16(info.desc.opcode);
3392 case i40e_aqc_opc_send_msg_to_pf:
3393 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3394 i40e_pf_host_handle_vf_msg(dev,
3395 rte_le_to_cpu_16(info.desc.retval),
3396 rte_le_to_cpu_32(info.desc.cookie_high),
3397 rte_le_to_cpu_32(info.desc.cookie_low),
3402 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3407 rte_free(info.msg_buf);
3411 * Interrupt handler triggered by NIC for handling
3412 * specific interrupt.
3415 * Pointer to interrupt handle.
3417 * The address of parameter (struct rte_eth_dev *) regsitered before.
3423 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3426 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428 uint32_t cause, enable;
3430 i40e_pf_disable_irq0(hw);
3432 cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3433 enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3435 /* Shared IRQ case, return */
3436 if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3437 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3438 "no INT event to process", hw->pf_id);
3442 if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3443 PMD_DRV_LOG(INFO, "INT:Link status changed");
3444 i40e_dev_link_update(dev, 0);
3447 if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3448 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3450 if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3451 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3453 if (cause & I40E_PFINT_ICR0_GRST_MASK)
3454 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3456 if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3457 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3459 if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3460 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3462 /* Add processing func to deal with VF reset vent */
3463 if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3464 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3465 i40e_dev_handle_vfr_event(dev);
3467 /* Find admin queue event */
3468 if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3469 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3470 i40e_dev_handle_aq_msg(dev);
3474 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3475 /* Re-enable interrupt from device side */
3476 i40e_pf_enable_irq0(hw);
3477 /* Re-enable interrupt from host side */
3478 rte_intr_enable(&(dev->pci_dev->intr_handle));
3482 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3483 struct i40e_macvlan_filter *filter,
3486 int ele_num, ele_buff_size;
3487 int num, actual_num, i;
3488 int ret = I40E_SUCCESS;
3489 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3490 struct i40e_aqc_add_macvlan_element_data *req_list;
3492 if (filter == NULL || total == 0)
3493 return I40E_ERR_PARAM;
3494 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3495 ele_buff_size = hw->aq.asq_buf_size;
3497 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3498 if (req_list == NULL) {
3499 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3500 return I40E_ERR_NO_MEMORY;
3505 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3506 memset(req_list, 0, ele_buff_size);
3508 for (i = 0; i < actual_num; i++) {
3509 (void)rte_memcpy(req_list[i].mac_addr,
3510 &filter[num + i].macaddr, ETH_ADDR_LEN);
3511 req_list[i].vlan_tag =
3512 rte_cpu_to_le_16(filter[num + i].vlan_id);
3513 req_list[i].flags = rte_cpu_to_le_16(\
3514 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3515 req_list[i].queue_number = 0;
3518 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3520 if (ret != I40E_SUCCESS) {
3521 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3525 } while (num < total);
3533 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3534 struct i40e_macvlan_filter *filter,
3537 int ele_num, ele_buff_size;
3538 int num, actual_num, i;
3539 int ret = I40E_SUCCESS;
3540 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3541 struct i40e_aqc_remove_macvlan_element_data *req_list;
3543 if (filter == NULL || total == 0)
3544 return I40E_ERR_PARAM;
3546 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3547 ele_buff_size = hw->aq.asq_buf_size;
3549 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3550 if (req_list == NULL) {
3551 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3552 return I40E_ERR_NO_MEMORY;
3557 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3558 memset(req_list, 0, ele_buff_size);
3560 for (i = 0; i < actual_num; i++) {
3561 (void)rte_memcpy(req_list[i].mac_addr,
3562 &filter[num + i].macaddr, ETH_ADDR_LEN);
3563 req_list[i].vlan_tag =
3564 rte_cpu_to_le_16(filter[num + i].vlan_id);
3565 req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3568 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3570 if (ret != I40E_SUCCESS) {
3571 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3575 } while (num < total);
3582 /* Find out specific MAC filter */
3583 static struct i40e_mac_filter *
3584 i40e_find_mac_filter(struct i40e_vsi *vsi,
3585 struct ether_addr *macaddr)
3587 struct i40e_mac_filter *f;
3589 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3590 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3598 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3601 uint32_t vid_idx, vid_bit;
3603 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3604 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3606 if (vsi->vfta[vid_idx] & vid_bit)
3613 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3614 uint16_t vlan_id, bool on)
3616 uint32_t vid_idx, vid_bit;
3618 #define UINT32_BIT_MASK 0x1F
3619 #define VALID_VLAN_BIT_MASK 0xFFF
3620 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3621 * element first, then find the bits it belongs to
3623 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3625 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3628 vsi->vfta[vid_idx] |= vid_bit;
3630 vsi->vfta[vid_idx] &= ~vid_bit;
3634 * Find all vlan options for specific mac addr,
3635 * return with actual vlan found.
3638 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3639 struct i40e_macvlan_filter *mv_f,
3640 int num, struct ether_addr *addr)
3646 * Not to use i40e_find_vlan_filter to decrease the loop time,
3647 * although the code looks complex.
3649 if (num < vsi->vlan_num)
3650 return I40E_ERR_PARAM;
3653 for (j = 0; j < I40E_VFTA_SIZE; j++) {
3655 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3656 if (vsi->vfta[j] & (1 << k)) {
3658 PMD_DRV_LOG(ERR, "vlan number "
3660 return I40E_ERR_PARAM;
3662 (void)rte_memcpy(&mv_f[i].macaddr,
3663 addr, ETH_ADDR_LEN);
3665 j * I40E_UINT32_BIT_SIZE + k;
3671 return I40E_SUCCESS;
3675 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3676 struct i40e_macvlan_filter *mv_f,
3681 struct i40e_mac_filter *f;
3683 if (num < vsi->mac_num)
3684 return I40E_ERR_PARAM;
3686 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3688 PMD_DRV_LOG(ERR, "buffer number not match");
3689 return I40E_ERR_PARAM;
3691 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3692 mv_f[i].vlan_id = vlan;
3696 return I40E_SUCCESS;
3700 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3703 struct i40e_mac_filter *f;
3704 struct i40e_macvlan_filter *mv_f;
3705 int ret = I40E_SUCCESS;
3707 if (vsi == NULL || vsi->mac_num == 0)
3708 return I40E_ERR_PARAM;
3710 /* Case that no vlan is set */
3711 if (vsi->vlan_num == 0)
3714 num = vsi->mac_num * vsi->vlan_num;
3716 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3718 PMD_DRV_LOG(ERR, "failed to allocate memory");
3719 return I40E_ERR_NO_MEMORY;
3723 if (vsi->vlan_num == 0) {
3724 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3725 (void)rte_memcpy(&mv_f[i].macaddr,
3726 &f->macaddr, ETH_ADDR_LEN);
3727 mv_f[i].vlan_id = 0;
3731 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3732 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3733 vsi->vlan_num, &f->macaddr);
3734 if (ret != I40E_SUCCESS)
3740 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3748 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3750 struct i40e_macvlan_filter *mv_f;
3752 int ret = I40E_SUCCESS;
3754 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3755 return I40E_ERR_PARAM;
3757 /* If it's already set, just return */
3758 if (i40e_find_vlan_filter(vsi,vlan))
3759 return I40E_SUCCESS;
3761 mac_num = vsi->mac_num;
3764 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3765 return I40E_ERR_PARAM;
3768 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3771 PMD_DRV_LOG(ERR, "failed to allocate memory");
3772 return I40E_ERR_NO_MEMORY;
3775 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3777 if (ret != I40E_SUCCESS)
3780 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3782 if (ret != I40E_SUCCESS)
3785 i40e_set_vlan_filter(vsi, vlan, 1);
3795 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3797 struct i40e_macvlan_filter *mv_f;
3799 int ret = I40E_SUCCESS;
3802 * Vlan 0 is the generic filter for untagged packets
3803 * and can't be removed.
3805 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3806 return I40E_ERR_PARAM;
3808 /* If can't find it, just return */
3809 if (!i40e_find_vlan_filter(vsi, vlan))
3810 return I40E_ERR_PARAM;
3812 mac_num = vsi->mac_num;
3815 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3816 return I40E_ERR_PARAM;
3819 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3822 PMD_DRV_LOG(ERR, "failed to allocate memory");
3823 return I40E_ERR_NO_MEMORY;
3826 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3828 if (ret != I40E_SUCCESS)
3831 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3833 if (ret != I40E_SUCCESS)
3836 /* This is last vlan to remove, replace all mac filter with vlan 0 */
3837 if (vsi->vlan_num == 1) {
3838 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3839 if (ret != I40E_SUCCESS)
3842 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3843 if (ret != I40E_SUCCESS)
3847 i40e_set_vlan_filter(vsi, vlan, 0);
3857 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3859 struct i40e_mac_filter *f;
3860 struct i40e_macvlan_filter *mv_f;
3862 int ret = I40E_SUCCESS;
3864 /* If it's add and we've config it, return */
3865 f = i40e_find_mac_filter(vsi, addr);
3867 return I40E_SUCCESS;
3870 * If vlan_num is 0, that's the first time to add mac,
3871 * set mask for vlan_id 0.
3873 if (vsi->vlan_num == 0) {
3874 i40e_set_vlan_filter(vsi, 0, 1);
3878 vlan_num = vsi->vlan_num;
3880 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3882 PMD_DRV_LOG(ERR, "failed to allocate memory");
3883 return I40E_ERR_NO_MEMORY;
3886 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3887 if (ret != I40E_SUCCESS)
3890 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3891 if (ret != I40E_SUCCESS)
3894 /* Add the mac addr into mac list */
3895 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3897 PMD_DRV_LOG(ERR, "failed to allocate memory");
3898 ret = I40E_ERR_NO_MEMORY;
3901 (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3902 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3913 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3915 struct i40e_mac_filter *f;
3916 struct i40e_macvlan_filter *mv_f;
3918 int ret = I40E_SUCCESS;
3920 /* Can't find it, return an error */
3921 f = i40e_find_mac_filter(vsi, addr);
3923 return I40E_ERR_PARAM;
3925 vlan_num = vsi->vlan_num;
3926 if (vlan_num == 0) {
3927 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3928 return I40E_ERR_PARAM;
3930 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3932 PMD_DRV_LOG(ERR, "failed to allocate memory");
3933 return I40E_ERR_NO_MEMORY;
3936 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3937 if (ret != I40E_SUCCESS)
3940 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3941 if (ret != I40E_SUCCESS)
3944 /* Remove the mac addr into mac list */
3945 TAILQ_REMOVE(&vsi->mac_list, f, next);
3955 /* Configure hash enable flags for RSS */
3957 i40e_config_hena(uint64_t flags)
3964 if (flags & ETH_RSS_NONF_IPV4_UDP)
3965 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3966 if (flags & ETH_RSS_NONF_IPV4_TCP)
3967 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3968 if (flags & ETH_RSS_NONF_IPV4_SCTP)
3969 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3970 if (flags & ETH_RSS_NONF_IPV4_OTHER)
3971 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3972 if (flags & ETH_RSS_FRAG_IPV4)
3973 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3974 if (flags & ETH_RSS_NONF_IPV6_UDP)
3975 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3976 if (flags & ETH_RSS_NONF_IPV6_TCP)
3977 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3978 if (flags & ETH_RSS_NONF_IPV6_SCTP)
3979 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3980 if (flags & ETH_RSS_NONF_IPV6_OTHER)
3981 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3982 if (flags & ETH_RSS_FRAG_IPV6)
3983 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3984 if (flags & ETH_RSS_L2_PAYLOAD)
3985 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3990 /* Parse the hash enable flags */
3992 i40e_parse_hena(uint64_t flags)
3994 uint64_t rss_hf = 0;
3999 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4000 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4001 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4002 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4003 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4004 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4005 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4006 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4007 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4008 rss_hf |= ETH_RSS_FRAG_IPV4;
4009 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4010 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4011 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4012 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4013 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4014 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4015 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4016 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4017 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4018 rss_hf |= ETH_RSS_FRAG_IPV6;
4019 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4020 rss_hf |= ETH_RSS_L2_PAYLOAD;
4027 i40e_pf_disable_rss(struct i40e_pf *pf)
4029 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4032 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4033 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4034 hena &= ~I40E_RSS_HENA_ALL;
4035 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4036 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4037 I40E_WRITE_FLUSH(hw);
4041 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4044 uint8_t hash_key_len;
4049 hash_key = (uint32_t *)(rss_conf->rss_key);
4050 hash_key_len = rss_conf->rss_key_len;
4051 if (hash_key != NULL && hash_key_len >=
4052 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4053 /* Fill in RSS hash key */
4054 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4055 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4058 rss_hf = rss_conf->rss_hf;
4059 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4060 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4061 hena &= ~I40E_RSS_HENA_ALL;
4062 hena |= i40e_config_hena(rss_hf);
4063 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4064 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4065 I40E_WRITE_FLUSH(hw);
4071 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4072 struct rte_eth_rss_conf *rss_conf)
4074 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4078 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4079 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4080 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4081 if (rss_hf != 0) /* Enable RSS */
4083 return 0; /* Nothing to do */
4086 if (rss_hf == 0) /* Disable RSS */
4089 return i40e_hw_rss_hash_set(hw, rss_conf);
4093 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4094 struct rte_eth_rss_conf *rss_conf)
4096 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4101 if (hash_key != NULL) {
4102 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4103 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4104 rss_conf->rss_key_len = i * sizeof(uint32_t);
4106 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4107 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4108 rss_conf->rss_hf = i40e_parse_hena(hena);
4115 i40e_pf_config_rss(struct i40e_pf *pf)
4117 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4118 struct rte_eth_rss_conf rss_conf;
4119 uint32_t i, lut = 0;
4120 uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4122 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4125 lut = (lut << 8) | (j & ((0x1 <<
4126 hw->func_caps.rss_table_entry_width) - 1));
4128 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4131 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4132 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4133 i40e_pf_disable_rss(pf);
4136 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4137 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4138 /* Calculate the default hash key */
4139 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4140 rss_key_default[i] = (uint32_t)rte_rand();
4141 rss_conf.rss_key = (uint8_t *)rss_key_default;
4142 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4146 return i40e_hw_rss_hash_set(hw, &rss_conf);
4150 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4152 if (!pf->dev_data->sriov.active) {
4153 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4155 i40e_pf_config_rss(pf);
4158 i40e_pf_disable_rss(pf);