lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 #define I40E_DEFAULT_RX_FREE_THRESH  32
  62 #define I40E_DEFAULT_RX_PTHRESH      8
  63 #define I40E_DEFAULT_RX_HTHRESH      8
  64 #define I40E_DEFAULT_RX_WTHRESH      0
  65
  66 #define I40E_DEFAULT_TX_FREE_THRESH  32
  67 #define I40E_DEFAULT_TX_PTHRESH      32
  68 #define I40E_DEFAULT_TX_HTHRESH      0
  69 #define I40E_DEFAULT_TX_WTHRESH      0
  70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  71
  72 /* Maximun number of MAC addresses */
  73 #define I40E_NUM_MACADDR_MAX       64
  74 #define I40E_CLEAR_PXE_WAIT_MS     200
  75
  76 /* Maximun number of capability elements */
  77 #define I40E_MAX_CAP_ELE_NUM       128
  78
  79 /* Wait count and inteval */
  80 #define I40E_CHK_Q_ENA_COUNT       1000
  81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  82
  83 /* Maximun number of VSI */
  84 #define I40E_MAX_NUM_VSIS          (384UL)
  85
  86 /* Bit shift and mask */
  87 #define I40E_16_BIT_SHIFT 16
  88 #define I40E_16_BIT_MASK  0xFFFF
  89 #define I40E_32_BIT_SHIFT 32
  90 #define I40E_32_BIT_MASK  0xFFFFFFFF
  91 #define I40E_48_BIT_SHIFT 48
  92 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  93
  94 /* Default queue interrupt throttling time in microseconds*/
  95 #define I40E_ITR_INDEX_DEFAULT          0
  96 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  97 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  98
  99 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 100
 101 #define I40E_RSS_OFFLOAD_ALL ( \
 102         ETH_RSS_NONF_IPV4_UDP | \
 103         ETH_RSS_NONF_IPV4_TCP | \
 104         ETH_RSS_NONF_IPV4_SCTP | \
 105         ETH_RSS_NONF_IPV4_OTHER | \
 106         ETH_RSS_FRAG_IPV4 | \
 107         ETH_RSS_NONF_IPV6_UDP | \
 108         ETH_RSS_NONF_IPV6_TCP | \
 109         ETH_RSS_NONF_IPV6_SCTP | \
 110         ETH_RSS_NONF_IPV6_OTHER | \
 111         ETH_RSS_FRAG_IPV6 | \
 112         ETH_RSS_L2_PAYLOAD)
 113
 114 /* All bits of RSS hash enable */
 115 #define I40E_RSS_HENA_ALL ( \
 116         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 117         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 118         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 119         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 120         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 121         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 122         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 123         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 124         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 125         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 126         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 127         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 128         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 129         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 130
 131 static int eth_i40e_dev_init(\
 132                         __attribute__((unused)) struct eth_driver *eth_drv,
 133                         struct rte_eth_dev *eth_dev);
 134 static int i40e_dev_configure(struct rte_eth_dev *dev);
 135 static int i40e_dev_start(struct rte_eth_dev *dev);
 136 static void i40e_dev_stop(struct rte_eth_dev *dev);
 137 static void i40e_dev_close(struct rte_eth_dev *dev);
 138 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 139 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 140 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 141 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 142 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 145                                struct rte_eth_stats *stats);
 146 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 147 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 148                                             uint16_t queue_id,
 149                                             uint8_t stat_idx,
 150                                             uint8_t is_rx);
 151 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 152                               struct rte_eth_dev_info *dev_info);
 153 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 154                                 uint16_t vlan_id,
 155                                 int on);
 156 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 157 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 158 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 159                                       uint16_t queue,
 160                                       int on);
 161 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 162 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 163 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 164 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 165                               struct rte_eth_fc_conf *fc_conf);
 166 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                                        struct rte_eth_pfc_conf *pfc_conf);
 168 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 169                           struct ether_addr *mac_addr,
 170                           uint32_t index,
 171                           uint32_t pool);
 172 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 173 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 174                                     struct rte_eth_rss_reta *reta_conf);
 175 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 176                                    struct rte_eth_rss_reta *reta_conf);
 177
 178 static int i40e_get_cap(struct i40e_hw *hw);
 179 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 180 static int i40e_pf_setup(struct i40e_pf *pf);
 181 static int i40e_vsi_init(struct i40e_vsi *vsi);
 182 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 183                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 184 static void i40e_stat_update_48(struct i40e_hw *hw,
 185                                uint32_t hireg,
 186                                uint32_t loreg,
 187                                bool offset_loaded,
 188                                uint64_t *offset,
 189                                uint64_t *stat);
 190 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 191 static void i40e_dev_interrupt_handler(
 192                 __rte_unused struct rte_intr_handle *handle, void *param);
 193 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 194                                 uint32_t base, uint32_t num);
 195 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 196 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 197                         uint32_t base);
 198 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 199                         uint16_t num);
 200 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 201 static int i40e_veb_release(struct i40e_veb *veb);
 202 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 203                                                 struct i40e_vsi *vsi);
 204 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 205 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 206 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 207                                              struct i40e_macvlan_filter *mv_f,
 208                                              int num,
 209                                              struct ether_addr *addr);
 210 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 211                                              struct i40e_macvlan_filter *mv_f,
 212                                              int num,
 213                                              uint16_t vlan);
 214 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 215 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 216                                     struct rte_eth_rss_conf *rss_conf);
 217 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 218                                       struct rte_eth_rss_conf *rss_conf);
 219
 220 /* Default hash key buffer for RSS */
 221 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 222
 223 static struct rte_pci_id pci_id_i40e_map[] = {
 224 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 225 #include "rte_pci_dev_ids.h"
 226 { .vendor_id = 0, /* sentinel */ },
 227 };
 228
 229 static struct eth_dev_ops i40e_eth_dev_ops = {
 230         .dev_configure                = i40e_dev_configure,
 231         .dev_start                    = i40e_dev_start,
 232         .dev_stop                     = i40e_dev_stop,
 233         .dev_close                    = i40e_dev_close,
 234         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 235         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 236         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 237         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 238         .dev_set_link_up              = i40e_dev_set_link_up,
 239         .dev_set_link_down            = i40e_dev_set_link_down,
 240         .link_update                  = i40e_dev_link_update,
 241         .stats_get                    = i40e_dev_stats_get,
 242         .stats_reset                  = i40e_dev_stats_reset,
 243         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 244         .dev_infos_get                = i40e_dev_info_get,
 245         .vlan_filter_set              = i40e_vlan_filter_set,
 246         .vlan_tpid_set                = i40e_vlan_tpid_set,
 247         .vlan_offload_set             = i40e_vlan_offload_set,
 248         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 249         .vlan_pvid_set                = i40e_vlan_pvid_set,
 250         .rx_queue_start               = i40e_dev_rx_queue_start,
 251         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 252         .tx_queue_start               = i40e_dev_tx_queue_start,
 253         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 254         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 255         .rx_queue_release             = i40e_dev_rx_queue_release,
 256         .rx_queue_count               = i40e_dev_rx_queue_count,
 257         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 258         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 259         .tx_queue_release             = i40e_dev_tx_queue_release,
 260         .dev_led_on                   = i40e_dev_led_on,
 261         .dev_led_off                  = i40e_dev_led_off,
 262         .flow_ctrl_set                = i40e_flow_ctrl_set,
 263         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 264         .mac_addr_add                 = i40e_macaddr_add,
 265         .mac_addr_remove              = i40e_macaddr_remove,
 266         .reta_update                  = i40e_dev_rss_reta_update,
 267         .reta_query                   = i40e_dev_rss_reta_query,
 268         .rss_hash_update              = i40e_dev_rss_hash_update,
 269         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 270 };
 271
 272 static struct eth_driver rte_i40e_pmd = {
 273         {
 274                 .name = "rte_i40e_pmd",
 275                 .id_table = pci_id_i40e_map,
 276                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 277         },
 278         .eth_dev_init = eth_i40e_dev_init,
 279         .dev_private_size = sizeof(struct i40e_adapter),
 280 };
 281
 282 static inline int
 283 i40e_prev_power_of_2(int n)
 284 {
 285        int p = n;
 286
 287        --p;
 288        p |= p >> 1;
 289        p |= p >> 2;
 290        p |= p >> 4;
 291        p |= p >> 8;
 292        p |= p >> 16;
 293        if (p == (n - 1))
 294                return n;
 295        p >>= 1;
 296
 297        return ++p;
 298 }
 299
 300 static inline int
 301 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 302                                      struct rte_eth_link *link)
 303 {
 304         struct rte_eth_link *dst = link;
 305         struct rte_eth_link *src = &(dev->data->dev_link);
 306
 307         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 308                                         *(uint64_t *)src) == 0)
 309                 return -1;
 310
 311         return 0;
 312 }
 313
 314 static inline int
 315 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 316                                       struct rte_eth_link *link)
 317 {
 318         struct rte_eth_link *dst = &(dev->data->dev_link);
 319         struct rte_eth_link *src = link;
 320
 321         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 322                                         *(uint64_t *)src) == 0)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 /*
 329  * Driver initialization routine.
 330  * Invoked once at EAL init time.
 331  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 332  */
 333 static int
 334 rte_i40e_pmd_init(const char *name __rte_unused,
 335                   const char *params __rte_unused)
 336 {
 337         PMD_INIT_FUNC_TRACE();
 338         rte_eth_driver_register(&rte_i40e_pmd);
 339
 340         return 0;
 341 }
 342
 343 static struct rte_driver rte_i40e_driver = {
 344         .type = PMD_PDEV,
 345         .init = rte_i40e_pmd_init,
 346 };
 347
 348 PMD_REGISTER_DRIVER(rte_i40e_driver);
 349
 350 static int
 351 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 352                   struct rte_eth_dev *dev)
 353 {
 354         struct rte_pci_device *pci_dev;
 355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 357         struct i40e_vsi *vsi;
 358         int ret;
 359         uint32_t len;
 360         uint8_t aq_fail = 0;
 361
 362         PMD_INIT_FUNC_TRACE();
 363
 364         dev->dev_ops = &i40e_eth_dev_ops;
 365         dev->rx_pkt_burst = i40e_recv_pkts;
 366         dev->tx_pkt_burst = i40e_xmit_pkts;
 367
 368         /* for secondary processes, we don't initialise any further as primary
 369          * has already done this work. Only check we don't need a different
 370          * RX function */
 371         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 372                 if (dev->data->scattered_rx)
 373                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 374                 return 0;
 375         }
 376         pci_dev = dev->pci_dev;
 377         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 378         pf->adapter->eth_dev = dev;
 379         pf->dev_data = dev->data;
 380
 381         hw->back = I40E_PF_TO_ADAPTER(pf);
 382         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 383         if (!hw->hw_addr) {
 384                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 385                              "as address is NULL");
 386                 return -ENODEV;
 387         }
 388
 389         hw->vendor_id = pci_dev->id.vendor_id;
 390         hw->device_id = pci_dev->id.device_id;
 391         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 392         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 393         hw->bus.device = pci_dev->addr.devid;
 394         hw->bus.func = pci_dev->addr.function;
 395
 396         /* Make sure all is clean before doing PF reset */
 397         i40e_clear_hw(hw);
 398
 399         /* Reset here to make sure all is clean for each PF */
 400         ret = i40e_pf_reset(hw);
 401         if (ret) {
 402                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 403                 return ret;
 404         }
 405
 406         /* Initialize the shared code (base driver) */
 407         ret = i40e_init_shared_code(hw);
 408         if (ret) {
 409                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 410                 return ret;
 411         }
 412
 413         /* Initialize the parameters for adminq */
 414         i40e_init_adminq_parameter(hw);
 415         ret = i40e_init_adminq(hw);
 416         if (ret != I40E_SUCCESS) {
 417                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 418                 return -EIO;
 419         }
 420         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 421                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 422                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 423                      ((hw->nvm.version >> 12) & 0xf),
 424                      ((hw->nvm.version >> 4) & 0xff),
 425                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 426
 427         /* Disable LLDP */
 428         ret = i40e_aq_stop_lldp(hw, true, NULL);
 429         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 430                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 431
 432         /* Clear PXE mode */
 433         i40e_clear_pxe_mode(hw);
 434
 435         /* Get hw capabilities */
 436         ret = i40e_get_cap(hw);
 437         if (ret != I40E_SUCCESS) {
 438                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 439                 goto err_get_capabilities;
 440         }
 441
 442         /* Initialize parameters for PF */
 443         ret = i40e_pf_parameter_init(dev);
 444         if (ret != 0) {
 445                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 446                 goto err_parameter_init;
 447         }
 448
 449         /* Initialize the queue management */
 450         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 451         if (ret < 0) {
 452                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 453                 goto err_qp_pool_init;
 454         }
 455         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 456                                 hw->func_caps.num_msix_vectors - 1);
 457         if (ret < 0) {
 458                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 459                 goto err_msix_pool_init;
 460         }
 461
 462         /* Initialize lan hmc */
 463         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 464                                 hw->func_caps.num_rx_qp, 0, 0);
 465         if (ret != I40E_SUCCESS) {
 466                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 467                 goto err_init_lan_hmc;
 468         }
 469
 470         /* Configure lan hmc */
 471         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 472         if (ret != I40E_SUCCESS) {
 473                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 474                 goto err_configure_lan_hmc;
 475         }
 476
 477         /* Get and check the mac address */
 478         i40e_get_mac_addr(hw, hw->mac.addr);
 479         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 480                 PMD_INIT_LOG(ERR, "mac address is not valid");
 481                 ret = -EIO;
 482                 goto err_get_mac_addr;
 483         }
 484         /* Copy the permanent MAC address */
 485         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 486                         (struct ether_addr *) hw->mac.perm_addr);
 487
 488         /* Disable flow control */
 489         hw->fc.requested_mode = I40E_FC_NONE;
 490         i40e_set_fc(hw, &aq_fail, TRUE);
 491
 492         /* PF setup, which includes VSI setup */
 493         ret = i40e_pf_setup(pf);
 494         if (ret) {
 495                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 496                 goto err_setup_pf_switch;
 497         }
 498
 499         vsi = pf->main_vsi;
 500
 501         /* Disable double vlan by default */
 502         i40e_vsi_config_double_vlan(vsi, FALSE);
 503
 504         if (!vsi->max_macaddrs)
 505                 len = ETHER_ADDR_LEN;
 506         else
 507                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 508
 509         /* Should be after VSI initialized */
 510         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 511         if (!dev->data->mac_addrs) {
 512                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 513                                         "for storing mac address");
 514                 goto err_get_mac_addr;
 515         }
 516         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 517                                         &dev->data->mac_addrs[0]);
 518
 519         /* initialize pf host driver to setup SRIOV resource if applicable */
 520         i40e_pf_host_init(dev);
 521
 522         /* register callback func to eal lib */
 523         rte_intr_callback_register(&(pci_dev->intr_handle),
 524                 i40e_dev_interrupt_handler, (void *)dev);
 525
 526         /* configure and enable device interrupt */
 527         i40e_pf_config_irq0(hw);
 528         i40e_pf_enable_irq0(hw);
 529
 530         /* enable uio intr after callback register */
 531         rte_intr_enable(&(pci_dev->intr_handle));
 532
 533         return 0;
 534
 535 err_setup_pf_switch:
 536         rte_free(pf->main_vsi);
 537 err_get_mac_addr:
 538 err_configure_lan_hmc:
 539         (void)i40e_shutdown_lan_hmc(hw);
 540 err_init_lan_hmc:
 541         i40e_res_pool_destroy(&pf->msix_pool);
 542 err_msix_pool_init:
 543         i40e_res_pool_destroy(&pf->qp_pool);
 544 err_qp_pool_init:
 545 err_parameter_init:
 546 err_get_capabilities:
 547         (void)i40e_shutdown_adminq(hw);
 548
 549         return ret;
 550 }
 551
 552 static int
 553 i40e_dev_configure(struct rte_eth_dev *dev)
 554 {
 555         return i40e_dev_init_vlan(dev);
 556 }
 557
 558 void
 559 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 560 {
 561         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 562         uint16_t msix_vect = vsi->msix_intr;
 563         uint16_t i;
 564
 565         for (i = 0; i < vsi->nb_qps; i++) {
 566                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 567                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 568                 rte_wmb();
 569         }
 570
 571         if (vsi->type != I40E_VSI_SRIOV) {
 572                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 573                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 574                                 msix_vect - 1), 0);
 575         } else {
 576                 uint32_t reg;
 577                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 578                         vsi->user_param + (msix_vect - 1);
 579
 580                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 581         }
 582         I40E_WRITE_FLUSH(hw);
 583 }
 584
 585 static inline uint16_t
 586 i40e_calc_itr_interval(int16_t interval)
 587 {
 588         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 589                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 590
 591         /* Convert to hardware count, as writing each 1 represents 2 us */
 592         return (interval/2);
 593 }
 594
 595 void
 596 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 597 {
 598         uint32_t val;
 599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 600         uint16_t msix_vect = vsi->msix_intr;
 601         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 602         int i;
 603
 604         for (i = 0; i < vsi->nb_qps; i++)
 605                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 606
 607         /* Bind all RX queues to allocated MSIX interrupt */
 608         for (i = 0; i < vsi->nb_qps; i++) {
 609                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 610                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 611                         ((vsi->base_queue + i + 1) <<
 612                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 613                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 614                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 615
 616                 if (i == vsi->nb_qps - 1)
 617                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 618                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 619         }
 620
 621         /* Write first RX queue to Link list register as the head element */
 622         if (vsi->type != I40E_VSI_SRIOV) {
 623                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 624                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 625                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 626
 627                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 628                                 msix_vect - 1), interval);
 629
 630                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 631                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 632                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 633         }
 634         else {
 635                 uint32_t reg;
 636                 /* num_msix_vectors_vf needs to minus irq0 */
 637                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 638                         vsi->user_param + (msix_vect - 1);
 639
 640                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 641                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 642                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 643         }
 644
 645         I40E_WRITE_FLUSH(hw);
 646 }
 647
 648 static void
 649 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 650 {
 651         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 652         uint16_t interval = i40e_calc_itr_interval(\
 653                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 654
 655         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 656                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 657                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 658                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 659                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 660 }
 661
 662 static void
 663 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 664 {
 665         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 666
 667         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 668 }
 669
 670 static inline uint8_t
 671 i40e_parse_link_speed(uint16_t eth_link_speed)
 672 {
 673         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 674
 675         switch (eth_link_speed) {
 676         case ETH_LINK_SPEED_40G:
 677                 link_speed = I40E_LINK_SPEED_40GB;
 678                 break;
 679         case ETH_LINK_SPEED_20G:
 680                 link_speed = I40E_LINK_SPEED_20GB;
 681                 break;
 682         case ETH_LINK_SPEED_10G:
 683                 link_speed = I40E_LINK_SPEED_10GB;
 684                 break;
 685         case ETH_LINK_SPEED_1000:
 686                 link_speed = I40E_LINK_SPEED_1GB;
 687                 break;
 688         case ETH_LINK_SPEED_100:
 689                 link_speed = I40E_LINK_SPEED_100MB;
 690                 break;
 691         }
 692
 693         return link_speed;
 694 }
 695
 696 static int
 697 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 698 {
 699         enum i40e_status_code status;
 700         struct i40e_aq_get_phy_abilities_resp phy_ab;
 701         struct i40e_aq_set_phy_config phy_conf;
 702         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 703                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 704                         I40E_AQ_PHY_FLAG_LOW_POWER;
 705         const uint8_t advt = I40E_LINK_SPEED_40GB |
 706                         I40E_LINK_SPEED_10GB |
 707                         I40E_LINK_SPEED_1GB |
 708                         I40E_LINK_SPEED_100MB;
 709         int ret = -ENOTSUP;
 710
 711         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 712                                               NULL);
 713         if (status)
 714                 return ret;
 715
 716         memset(&phy_conf, 0, sizeof(phy_conf));
 717
 718         /* bits 0-2 use the values from get_phy_abilities_resp */
 719         abilities &= ~mask;
 720         abilities |= phy_ab.abilities & mask;
 721
 722         /* update ablities and speed */
 723         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 724                 phy_conf.link_speed = advt;
 725         else
 726                 phy_conf.link_speed = force_speed;
 727
 728         phy_conf.abilities = abilities;
 729
 730         /* use get_phy_abilities_resp value for the rest */
 731         phy_conf.phy_type = phy_ab.phy_type;
 732         phy_conf.eee_capability = phy_ab.eee_capability;
 733         phy_conf.eeer = phy_ab.eeer_val;
 734         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 735
 736         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 737                     phy_ab.abilities, phy_ab.link_speed);
 738         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 739                     phy_conf.abilities, phy_conf.link_speed);
 740
 741         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 742         if (status)
 743                 return ret;
 744
 745         return I40E_SUCCESS;
 746 }
 747
 748 static int
 749 i40e_apply_link_speed(struct rte_eth_dev *dev)
 750 {
 751         uint8_t speed;
 752         uint8_t abilities = 0;
 753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755
 756         speed = i40e_parse_link_speed(conf->link_speed);
 757         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 758         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 759                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 760         else
 761                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 762
 763         return i40e_phy_conf_link(hw, abilities, speed);
 764 }
 765
 766 static int
 767 i40e_dev_start(struct rte_eth_dev *dev)
 768 {
 769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 771         struct i40e_vsi *vsi = pf->main_vsi;
 772         int ret;
 773
 774         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 775                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 776                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 777                              dev->data->dev_conf.link_duplex,
 778                              dev->data->port_id);
 779                 return -EINVAL;
 780         }
 781
 782         /* Initialize VSI */
 783         ret = i40e_vsi_init(vsi);
 784         if (ret != I40E_SUCCESS) {
 785                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 786                 goto err_up;
 787         }
 788
 789         /* Map queues with MSIX interrupt */
 790         i40e_vsi_queues_bind_intr(vsi);
 791         i40e_vsi_enable_queues_intr(vsi);
 792
 793         /* Enable all queues which have been configured */
 794         ret = i40e_vsi_switch_queues(vsi, TRUE);
 795         if (ret != I40E_SUCCESS) {
 796                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 797                 goto err_up;
 798         }
 799
 800         /* Enable receiving broadcast packets */
 801         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 802                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 803                 if (ret != I40E_SUCCESS)
 804                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 805         }
 806
 807         /* Apply link configure */
 808         ret = i40e_apply_link_speed(dev);
 809         if (I40E_SUCCESS != ret) {
 810                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 811                 goto err_up;
 812         }
 813
 814         return I40E_SUCCESS;
 815
 816 err_up:
 817         i40e_vsi_switch_queues(vsi, FALSE);
 818
 819         return ret;
 820 }
 821
 822 static void
 823 i40e_dev_stop(struct rte_eth_dev *dev)
 824 {
 825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 826         struct i40e_vsi *vsi = pf->main_vsi;
 827
 828         /* Disable all queues */
 829         i40e_vsi_switch_queues(vsi, FALSE);
 830
 831         /* Set link down */
 832         i40e_dev_set_link_down(dev);
 833
 834         /* un-map queues with interrupt registers */
 835         i40e_vsi_disable_queues_intr(vsi);
 836         i40e_vsi_queues_unbind_intr(vsi);
 837 }
 838
 839 static void
 840 i40e_dev_close(struct rte_eth_dev *dev)
 841 {
 842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844         uint32_t reg;
 845
 846         PMD_INIT_FUNC_TRACE();
 847
 848         i40e_dev_stop(dev);
 849
 850         /* Disable interrupt */
 851         i40e_pf_disable_irq0(hw);
 852         rte_intr_disable(&(dev->pci_dev->intr_handle));
 853
 854         /* shutdown and destroy the HMC */
 855         i40e_shutdown_lan_hmc(hw);
 856
 857         /* release all the existing VSIs and VEBs */
 858         i40e_vsi_release(pf->main_vsi);
 859
 860         /* shutdown the adminq */
 861         i40e_aq_queue_shutdown(hw, true);
 862         i40e_shutdown_adminq(hw);
 863
 864         i40e_res_pool_destroy(&pf->qp_pool);
 865         i40e_res_pool_destroy(&pf->msix_pool);
 866
 867         /* force a PF reset to clean anything leftover */
 868         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 869         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 870                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 871         I40E_WRITE_FLUSH(hw);
 872 }
 873
 874 static void
 875 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 876 {
 877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 879         struct i40e_vsi *vsi = pf->main_vsi;
 880         int status;
 881
 882         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 883                                                         true, NULL);
 884         if (status != I40E_SUCCESS)
 885                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 886
 887         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 888                                                         TRUE, NULL);
 889         if (status != I40E_SUCCESS)
 890                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 891
 892 }
 893
 894 static void
 895 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 896 {
 897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 899         struct i40e_vsi *vsi = pf->main_vsi;
 900         int status;
 901
 902         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 903                                                         false, NULL);
 904         if (status != I40E_SUCCESS)
 905                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 906
 907         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 908                                                         false, NULL);
 909         if (status != I40E_SUCCESS)
 910                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 911 }
 912
 913 static void
 914 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 915 {
 916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918         struct i40e_vsi *vsi = pf->main_vsi;
 919         int ret;
 920
 921         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 922         if (ret != I40E_SUCCESS)
 923                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 924 }
 925
 926 static void
 927 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 928 {
 929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 931         struct i40e_vsi *vsi = pf->main_vsi;
 932         int ret;
 933
 934         if (dev->data->promiscuous == 1)
 935                 return; /* must remain in all_multicast mode */
 936
 937         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 938                                 vsi->seid, FALSE, NULL);
 939         if (ret != I40E_SUCCESS)
 940                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 941 }
 942
 943 /*
 944  * Set device link up.
 945  */
 946 static int
 947 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 948 {
 949         /* re-apply link speed setting */
 950         return i40e_apply_link_speed(dev);
 951 }
 952
 953 /*
 954  * Set device link down.
 955  */
 956 static int
 957 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 958 {
 959         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 960         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962
 963         return i40e_phy_conf_link(hw, abilities, speed);
 964 }
 965
 966 int
 967 i40e_dev_link_update(struct rte_eth_dev *dev,
 968                      __rte_unused int wait_to_complete)
 969 {
 970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         struct i40e_link_status link_status;
 972         struct rte_eth_link link, old;
 973         int status;
 974
 975         memset(&link, 0, sizeof(link));
 976         memset(&old, 0, sizeof(old));
 977         memset(&link_status, 0, sizeof(link_status));
 978         rte_i40e_dev_atomic_read_link_status(dev, &old);
 979
 980         /* Get link status information from hardware */
 981         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 982         if (status != I40E_SUCCESS) {
 983                 link.link_speed = ETH_LINK_SPEED_100;
 984                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 985                 PMD_DRV_LOG(ERR, "Failed to get link info");
 986                 goto out;
 987         }
 988
 989         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 990
 991         if (!link.link_status)
 992                 goto out;
 993
 994         /* i40e uses full duplex only */
 995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 996
 997         /* Parse the link status */
 998         switch (link_status.link_speed) {
 999         case I40E_LINK_SPEED_100MB:
1000                 link.link_speed = ETH_LINK_SPEED_100;
1001                 break;
1002         case I40E_LINK_SPEED_1GB:
1003                 link.link_speed = ETH_LINK_SPEED_1000;
1004                 break;
1005         case I40E_LINK_SPEED_10GB:
1006                 link.link_speed = ETH_LINK_SPEED_10G;
1007                 break;
1008         case I40E_LINK_SPEED_20GB:
1009                 link.link_speed = ETH_LINK_SPEED_20G;
1010                 break;
1011         case I40E_LINK_SPEED_40GB:
1012                 link.link_speed = ETH_LINK_SPEED_40G;
1013                 break;
1014         default:
1015                 link.link_speed = ETH_LINK_SPEED_100;
1016                 break;
1017         }
1018
1019 out:
1020         rte_i40e_dev_atomic_write_link_status(dev, &link);
1021         if (link.link_status == old.link_status)
1022                 return -1;
1023
1024         return 0;
1025 }
1026
1027 /* Get all the statistics of a VSI */
1028 void
1029 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1030 {
1031         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1032         struct i40e_eth_stats *nes = &vsi->eth_stats;
1033         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1034         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1035
1036         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1037                             vsi->offset_loaded, &oes->rx_bytes,
1038                             &nes->rx_bytes);
1039         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1040                             vsi->offset_loaded, &oes->rx_unicast,
1041                             &nes->rx_unicast);
1042         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1043                             vsi->offset_loaded, &oes->rx_multicast,
1044                             &nes->rx_multicast);
1045         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1046                             vsi->offset_loaded, &oes->rx_broadcast,
1047                             &nes->rx_broadcast);
1048         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1049                             &oes->rx_discards, &nes->rx_discards);
1050         /* GLV_REPC not supported */
1051         /* GLV_RMPC not supported */
1052         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1053                             &oes->rx_unknown_protocol,
1054                             &nes->rx_unknown_protocol);
1055         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1056                             vsi->offset_loaded, &oes->tx_bytes,
1057                             &nes->tx_bytes);
1058         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1059                             vsi->offset_loaded, &oes->tx_unicast,
1060                             &nes->tx_unicast);
1061         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1062                             vsi->offset_loaded, &oes->tx_multicast,
1063                             &nes->tx_multicast);
1064         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1065                             vsi->offset_loaded,  &oes->tx_broadcast,
1066                             &nes->tx_broadcast);
1067         /* GLV_TDPC not supported */
1068         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1069                             &oes->tx_errors, &nes->tx_errors);
1070         vsi->offset_loaded = true;
1071
1072         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1073                     vsi->vsi_id);
1074         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1075         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1076         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1077         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1078         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1079         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1080                     nes->rx_unknown_protocol);
1081         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1082         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1083         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1084         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1085         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1086         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1087         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1088                     vsi->vsi_id);
1089 }
1090
1091 /* Get all statistics of a port */
1092 static void
1093 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1094 {
1095         uint32_t i;
1096         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1097         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1099         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1100
1101         /* Get statistics of struct i40e_eth_stats */
1102         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1103                             I40E_GLPRT_GORCL(hw->port),
1104                             pf->offset_loaded, &os->eth.rx_bytes,
1105                             &ns->eth.rx_bytes);
1106         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1107                             I40E_GLPRT_UPRCL(hw->port),
1108                             pf->offset_loaded, &os->eth.rx_unicast,
1109                             &ns->eth.rx_unicast);
1110         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1111                             I40E_GLPRT_MPRCL(hw->port),
1112                             pf->offset_loaded, &os->eth.rx_multicast,
1113                             &ns->eth.rx_multicast);
1114         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1115                             I40E_GLPRT_BPRCL(hw->port),
1116                             pf->offset_loaded, &os->eth.rx_broadcast,
1117                             &ns->eth.rx_broadcast);
1118         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1119                             pf->offset_loaded, &os->eth.rx_discards,
1120                             &ns->eth.rx_discards);
1121         /* GLPRT_REPC not supported */
1122         /* GLPRT_RMPC not supported */
1123         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1124                             pf->offset_loaded,
1125                             &os->eth.rx_unknown_protocol,
1126                             &ns->eth.rx_unknown_protocol);
1127         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1128                             I40E_GLPRT_GOTCL(hw->port),
1129                             pf->offset_loaded, &os->eth.tx_bytes,
1130                             &ns->eth.tx_bytes);
1131         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1132                             I40E_GLPRT_UPTCL(hw->port),
1133                             pf->offset_loaded, &os->eth.tx_unicast,
1134                             &ns->eth.tx_unicast);
1135         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1136                             I40E_GLPRT_MPTCL(hw->port),
1137                             pf->offset_loaded, &os->eth.tx_multicast,
1138                             &ns->eth.tx_multicast);
1139         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1140                             I40E_GLPRT_BPTCL(hw->port),
1141                             pf->offset_loaded, &os->eth.tx_broadcast,
1142                             &ns->eth.tx_broadcast);
1143         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1144                             pf->offset_loaded, &os->eth.tx_discards,
1145                             &ns->eth.tx_discards);
1146         /* GLPRT_TEPC not supported */
1147
1148         /* additional port specific stats */
1149         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1150                             pf->offset_loaded, &os->tx_dropped_link_down,
1151                             &ns->tx_dropped_link_down);
1152         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1153                             pf->offset_loaded, &os->crc_errors,
1154                             &ns->crc_errors);
1155         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1156                             pf->offset_loaded, &os->illegal_bytes,
1157                             &ns->illegal_bytes);
1158         /* GLPRT_ERRBC not supported */
1159         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1160                             pf->offset_loaded, &os->mac_local_faults,
1161                             &ns->mac_local_faults);
1162         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1163                             pf->offset_loaded, &os->mac_remote_faults,
1164                             &ns->mac_remote_faults);
1165         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1166                             pf->offset_loaded, &os->rx_length_errors,
1167                             &ns->rx_length_errors);
1168         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1169                             pf->offset_loaded, &os->link_xon_rx,
1170                             &ns->link_xon_rx);
1171         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1172                             pf->offset_loaded, &os->link_xoff_rx,
1173                             &ns->link_xoff_rx);
1174         for (i = 0; i < 8; i++) {
1175                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1176                                     pf->offset_loaded,
1177                                     &os->priority_xon_rx[i],
1178                                     &ns->priority_xon_rx[i]);
1179                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1180                                     pf->offset_loaded,
1181                                     &os->priority_xoff_rx[i],
1182                                     &ns->priority_xoff_rx[i]);
1183         }
1184         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1185                             pf->offset_loaded, &os->link_xon_tx,
1186                             &ns->link_xon_tx);
1187         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1188                             pf->offset_loaded, &os->link_xoff_tx,
1189                             &ns->link_xoff_tx);
1190         for (i = 0; i < 8; i++) {
1191                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1192                                     pf->offset_loaded,
1193                                     &os->priority_xon_tx[i],
1194                                     &ns->priority_xon_tx[i]);
1195                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1196                                     pf->offset_loaded,
1197                                     &os->priority_xoff_tx[i],
1198                                     &ns->priority_xoff_tx[i]);
1199                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1200                                     pf->offset_loaded,
1201                                     &os->priority_xon_2_xoff[i],
1202                                     &ns->priority_xon_2_xoff[i]);
1203         }
1204         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1205                             I40E_GLPRT_PRC64L(hw->port),
1206                             pf->offset_loaded, &os->rx_size_64,
1207                             &ns->rx_size_64);
1208         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1209                             I40E_GLPRT_PRC127L(hw->port),
1210                             pf->offset_loaded, &os->rx_size_127,
1211                             &ns->rx_size_127);
1212         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1213                             I40E_GLPRT_PRC255L(hw->port),
1214                             pf->offset_loaded, &os->rx_size_255,
1215                             &ns->rx_size_255);
1216         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1217                             I40E_GLPRT_PRC511L(hw->port),
1218                             pf->offset_loaded, &os->rx_size_511,
1219                             &ns->rx_size_511);
1220         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1221                             I40E_GLPRT_PRC1023L(hw->port),
1222                             pf->offset_loaded, &os->rx_size_1023,
1223                             &ns->rx_size_1023);
1224         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1225                             I40E_GLPRT_PRC1522L(hw->port),
1226                             pf->offset_loaded, &os->rx_size_1522,
1227                             &ns->rx_size_1522);
1228         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1229                             I40E_GLPRT_PRC9522L(hw->port),
1230                             pf->offset_loaded, &os->rx_size_big,
1231                             &ns->rx_size_big);
1232         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1233                             pf->offset_loaded, &os->rx_undersize,
1234                             &ns->rx_undersize);
1235         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1236                             pf->offset_loaded, &os->rx_fragments,
1237                             &ns->rx_fragments);
1238         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1239                             pf->offset_loaded, &os->rx_oversize,
1240                             &ns->rx_oversize);
1241         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1242                             pf->offset_loaded, &os->rx_jabber,
1243                             &ns->rx_jabber);
1244         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1245                             I40E_GLPRT_PTC64L(hw->port),
1246                             pf->offset_loaded, &os->tx_size_64,
1247                             &ns->tx_size_64);
1248         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1249                             I40E_GLPRT_PTC127L(hw->port),
1250                             pf->offset_loaded, &os->tx_size_127,
1251                             &ns->tx_size_127);
1252         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1253                             I40E_GLPRT_PTC255L(hw->port),
1254                             pf->offset_loaded, &os->tx_size_255,
1255                             &ns->tx_size_255);
1256         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1257                             I40E_GLPRT_PTC511L(hw->port),
1258                             pf->offset_loaded, &os->tx_size_511,
1259                             &ns->tx_size_511);
1260         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1261                             I40E_GLPRT_PTC1023L(hw->port),
1262                             pf->offset_loaded, &os->tx_size_1023,
1263                             &ns->tx_size_1023);
1264         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1265                             I40E_GLPRT_PTC1522L(hw->port),
1266                             pf->offset_loaded, &os->tx_size_1522,
1267                             &ns->tx_size_1522);
1268         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1269                             I40E_GLPRT_PTC9522L(hw->port),
1270                             pf->offset_loaded, &os->tx_size_big,
1271                             &ns->tx_size_big);
1272         /* GLPRT_MSPDC not supported */
1273         /* GLPRT_XEC not supported */
1274
1275         pf->offset_loaded = true;
1276
1277         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1278                                                 ns->eth.rx_broadcast;
1279         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1280                                                 ns->eth.tx_broadcast;
1281         stats->ibytes   = ns->eth.rx_bytes;
1282         stats->obytes   = ns->eth.tx_bytes;
1283         stats->oerrors  = ns->eth.tx_errors;
1284         stats->imcasts  = ns->eth.rx_multicast;
1285
1286         if (pf->main_vsi)
1287                 i40e_update_vsi_stats(pf->main_vsi);
1288
1289         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1290         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1291         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1292         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1293         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1294         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1295         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1296                     ns->eth.rx_unknown_protocol);
1297         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1298         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1299         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1300         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1301         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1302         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1303
1304         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1305                     ns->tx_dropped_link_down);
1306         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1307         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1308                     ns->illegal_bytes);
1309         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1310         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1311                     ns->mac_local_faults);
1312         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1313                     ns->mac_remote_faults);
1314         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1315                     ns->rx_length_errors);
1316         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1317         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1318         for (i = 0; i < 8; i++) {
1319                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1320                                 i, ns->priority_xon_rx[i]);
1321                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1322                                 i, ns->priority_xoff_rx[i]);
1323         }
1324         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1325         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1326         for (i = 0; i < 8; i++) {
1327                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1328                                 i, ns->priority_xon_tx[i]);
1329                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1330                                 i, ns->priority_xoff_tx[i]);
1331                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1332                                 i, ns->priority_xon_2_xoff[i]);
1333         }
1334         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1335         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1336         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1337         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1338         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1339         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1340         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1341         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1342         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1343         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1344         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1345         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1346         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1347         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1348         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1349         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1350         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1351         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1352         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1353                         ns->mac_short_packet_dropped);
1354         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1355                     ns->checksum_error);
1356         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1357 }
1358
1359 /* Reset the statistics */
1360 static void
1361 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1362 {
1363         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1364
1365         /* It results in reloading the start point of each counter */
1366         pf->offset_loaded = false;
1367 }
1368
1369 static int
1370 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1371                                  __rte_unused uint16_t queue_id,
1372                                  __rte_unused uint8_t stat_idx,
1373                                  __rte_unused uint8_t is_rx)
1374 {
1375         PMD_INIT_FUNC_TRACE();
1376
1377         return -ENOSYS;
1378 }
1379
1380 static void
1381 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1382 {
1383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1384         struct i40e_vsi *vsi = pf->main_vsi;
1385
1386         dev_info->max_rx_queues = vsi->nb_qps;
1387         dev_info->max_tx_queues = vsi->nb_qps;
1388         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1389         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1390         dev_info->max_mac_addrs = vsi->max_macaddrs;
1391         dev_info->max_vfs = dev->pci_dev->max_vfs;
1392         dev_info->rx_offload_capa =
1393                 DEV_RX_OFFLOAD_VLAN_STRIP |
1394                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1395                 DEV_RX_OFFLOAD_UDP_CKSUM |
1396                 DEV_RX_OFFLOAD_TCP_CKSUM;
1397         dev_info->tx_offload_capa =
1398                 DEV_TX_OFFLOAD_VLAN_INSERT |
1399                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1400                 DEV_TX_OFFLOAD_UDP_CKSUM |
1401                 DEV_TX_OFFLOAD_TCP_CKSUM |
1402                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1403
1404         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1405                 .rx_thresh = {
1406                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1407                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1408                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1409                 },
1410                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1411                 .rx_drop_en = 0,
1412         };
1413
1414         dev_info->default_txconf = (struct rte_eth_txconf) {
1415                 .tx_thresh = {
1416                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1417                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1418                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1419                 },
1420                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1421                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1422                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1423         };
1424
1425 }
1426
1427 static int
1428 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1429 {
1430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431         struct i40e_vsi *vsi = pf->main_vsi;
1432         PMD_INIT_FUNC_TRACE();
1433
1434         if (on)
1435                 return i40e_vsi_add_vlan(vsi, vlan_id);
1436         else
1437                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1438 }
1439
1440 static void
1441 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1442                    __rte_unused uint16_t tpid)
1443 {
1444         PMD_INIT_FUNC_TRACE();
1445 }
1446
1447 static void
1448 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1449 {
1450         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1451         struct i40e_vsi *vsi = pf->main_vsi;
1452
1453         if (mask & ETH_VLAN_STRIP_MASK) {
1454                 /* Enable or disable VLAN stripping */
1455                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1456                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1457                 else
1458                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1459         }
1460
1461         if (mask & ETH_VLAN_EXTEND_MASK) {
1462                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1463                         i40e_vsi_config_double_vlan(vsi, TRUE);
1464                 else
1465                         i40e_vsi_config_double_vlan(vsi, FALSE);
1466         }
1467 }
1468
1469 static void
1470 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1471                           __rte_unused uint16_t queue,
1472                           __rte_unused int on)
1473 {
1474         PMD_INIT_FUNC_TRACE();
1475 }
1476
1477 static int
1478 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1479 {
1480         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1481         struct i40e_vsi *vsi = pf->main_vsi;
1482         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1483         struct i40e_vsi_vlan_pvid_info info;
1484
1485         memset(&info, 0, sizeof(info));
1486         info.on = on;
1487         if (info.on)
1488                 info.config.pvid = pvid;
1489         else {
1490                 info.config.reject.tagged =
1491                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1492                 info.config.reject.untagged =
1493                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1494         }
1495
1496         return i40e_vsi_vlan_pvid_set(vsi, &info);
1497 }
1498
1499 static int
1500 i40e_dev_led_on(struct rte_eth_dev *dev)
1501 {
1502         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         uint32_t mode = i40e_led_get(hw);
1504
1505         if (mode == 0)
1506                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1507
1508         return 0;
1509 }
1510
1511 static int
1512 i40e_dev_led_off(struct rte_eth_dev *dev)
1513 {
1514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515         uint32_t mode = i40e_led_get(hw);
1516
1517         if (mode != 0)
1518                 i40e_led_set(hw, 0, false);
1519
1520         return 0;
1521 }
1522
1523 static int
1524 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1525                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1526 {
1527         PMD_INIT_FUNC_TRACE();
1528
1529         return -ENOSYS;
1530 }
1531
1532 static int
1533 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1534                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1535 {
1536         PMD_INIT_FUNC_TRACE();
1537
1538         return -ENOSYS;
1539 }
1540
1541 /* Add a MAC address, and update filters */
1542 static void
1543 i40e_macaddr_add(struct rte_eth_dev *dev,
1544                  struct ether_addr *mac_addr,
1545                  __attribute__((unused)) uint32_t index,
1546                  __attribute__((unused)) uint32_t pool)
1547 {
1548         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct i40e_vsi *vsi = pf->main_vsi;
1551         struct ether_addr old_mac;
1552         int ret;
1553
1554         if (!is_valid_assigned_ether_addr(mac_addr)) {
1555                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1556                 return;
1557         }
1558
1559         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1560                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1561                 return;
1562         }
1563
1564         /* Write mac address */
1565         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1566                                         mac_addr->addr_bytes, NULL);
1567         if (ret != I40E_SUCCESS) {
1568                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1569                 return;
1570         }
1571
1572         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1573         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1574                         ETHER_ADDR_LEN);
1575
1576         ret = i40e_vsi_add_mac(vsi, mac_addr);
1577         if (ret != I40E_SUCCESS) {
1578                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1579                 return;
1580         }
1581
1582         ether_addr_copy(mac_addr, &pf->dev_addr);
1583         i40e_vsi_delete_mac(vsi, &old_mac);
1584 }
1585
1586 /* Remove a MAC address, and update filters */
1587 static void
1588 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1589 {
1590         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1591         struct i40e_vsi *vsi = pf->main_vsi;
1592         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1593         struct ether_addr *macaddr;
1594         int ret;
1595         struct i40e_hw *hw =
1596                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597
1598         if (index >= vsi->max_macaddrs)
1599                 return;
1600
1601         macaddr = &(data->mac_addrs[index]);
1602         if (!is_valid_assigned_ether_addr(macaddr))
1603                 return;
1604
1605         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1606                                         hw->mac.perm_addr, NULL);
1607         if (ret != I40E_SUCCESS) {
1608                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1609                 return;
1610         }
1611
1612         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1613
1614         ret = i40e_vsi_delete_mac(vsi, macaddr);
1615         if (ret != I40E_SUCCESS)
1616                 return;
1617
1618         /* Clear device address as it has been removed */
1619         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1620                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1621 }
1622
1623 static int
1624 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1625                          struct rte_eth_rss_reta *reta_conf)
1626 {
1627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         uint32_t lut, l;
1629         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1630
1631         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1632                 if (i < max)
1633                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1634                 else
1635                         mask = (uint8_t)((reta_conf->mask_hi >>
1636                                                 (i - max)) & 0xF);
1637
1638                 if (!mask)
1639                         continue;
1640
1641                 if (mask == 0xF)
1642                         l = 0;
1643                 else
1644                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1645
1646                 for (j = 0, lut = 0; j < 4; j++) {
1647                         if (mask & (0x1 << j))
1648                                 lut |= reta_conf->reta[i + j] << (8 * j);
1649                         else
1650                                 lut |= l & (0xFF << (8 * j));
1651                 }
1652                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int
1659 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1660                         struct rte_eth_rss_reta *reta_conf)
1661 {
1662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         uint32_t lut;
1664         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1665
1666         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1667                 if (i < max)
1668                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1669                 else
1670                         mask = (uint8_t)((reta_conf->mask_hi >>
1671                                                 (i - max)) & 0xF);
1672
1673                 if (!mask)
1674                         continue;
1675
1676                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1677                 for (j = 0; j < 4; j++) {
1678                         if (mask & (0x1 << j))
1679                                 reta_conf->reta[i + j] =
1680                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1681                 }
1682         }
1683
1684         return 0;
1685 }
1686
1687 /**
1688  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1689  * @hw:   pointer to the HW structure
1690  * @mem:  pointer to mem struct to fill out
1691  * @size: size of memory requested
1692  * @alignment: what to align the allocation to
1693  **/
1694 enum i40e_status_code
1695 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1696                         struct i40e_dma_mem *mem,
1697                         u64 size,
1698                         u32 alignment)
1699 {
1700         static uint64_t id = 0;
1701         const struct rte_memzone *mz = NULL;
1702         char z_name[RTE_MEMZONE_NAMESIZE];
1703
1704         if (!mem)
1705                 return I40E_ERR_PARAM;
1706
1707         id++;
1708         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1709 #ifdef RTE_LIBRTE_XEN_DOM0
1710         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1711                                                         RTE_PGSIZE_2M);
1712 #else
1713         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1714 #endif
1715         if (!mz)
1716                 return I40E_ERR_NO_MEMORY;
1717
1718         mem->id = id;
1719         mem->size = size;
1720         mem->va = mz->addr;
1721 #ifdef RTE_LIBRTE_XEN_DOM0
1722         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1723 #else
1724         mem->pa = mz->phys_addr;
1725 #endif
1726
1727         return I40E_SUCCESS;
1728 }
1729
1730 /**
1731  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1732  * @hw:   pointer to the HW structure
1733  * @mem:  ptr to mem struct to free
1734  **/
1735 enum i40e_status_code
1736 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1737                     struct i40e_dma_mem *mem)
1738 {
1739         if (!mem || !mem->va)
1740                 return I40E_ERR_PARAM;
1741
1742         mem->va = NULL;
1743         mem->pa = (u64)0;
1744
1745         return I40E_SUCCESS;
1746 }
1747
1748 /**
1749  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1750  * @hw:   pointer to the HW structure
1751  * @mem:  pointer to mem struct to fill out
1752  * @size: size of memory requested
1753  **/
1754 enum i40e_status_code
1755 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1756                          struct i40e_virt_mem *mem,
1757                          u32 size)
1758 {
1759         if (!mem)
1760                 return I40E_ERR_PARAM;
1761
1762         mem->size = size;
1763         mem->va = rte_zmalloc("i40e", size, 0);
1764
1765         if (mem->va)
1766                 return I40E_SUCCESS;
1767         else
1768                 return I40E_ERR_NO_MEMORY;
1769 }
1770
1771 /**
1772  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1773  * @hw:   pointer to the HW structure
1774  * @mem:  pointer to mem struct to free
1775  **/
1776 enum i40e_status_code
1777 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1778                      struct i40e_virt_mem *mem)
1779 {
1780         if (!mem)
1781                 return I40E_ERR_PARAM;
1782
1783         rte_free(mem->va);
1784         mem->va = NULL;
1785
1786         return I40E_SUCCESS;
1787 }
1788
1789 void
1790 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1791 {
1792         rte_spinlock_init(&sp->spinlock);
1793 }
1794
1795 void
1796 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1797 {
1798         rte_spinlock_lock(&sp->spinlock);
1799 }
1800
1801 void
1802 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1803 {
1804         rte_spinlock_unlock(&sp->spinlock);
1805 }
1806
1807 void
1808 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1809 {
1810         return;
1811 }
1812
1813 /**
1814  * Get the hardware capabilities, which will be parsed
1815  * and saved into struct i40e_hw.
1816  */
1817 static int
1818 i40e_get_cap(struct i40e_hw *hw)
1819 {
1820         struct i40e_aqc_list_capabilities_element_resp *buf;
1821         uint16_t len, size = 0;
1822         int ret;
1823
1824         /* Calculate a huge enough buff for saving response data temporarily */
1825         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1826                                                 I40E_MAX_CAP_ELE_NUM;
1827         buf = rte_zmalloc("i40e", len, 0);
1828         if (!buf) {
1829                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1830                 return I40E_ERR_NO_MEMORY;
1831         }
1832
1833         /* Get, parse the capabilities and save it to hw */
1834         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1835                         i40e_aqc_opc_list_func_capabilities, NULL);
1836         if (ret != I40E_SUCCESS)
1837                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1838
1839         /* Free the temporary buffer after being used */
1840         rte_free(buf);
1841
1842         return ret;
1843 }
1844
1845 static int
1846 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1847 {
1848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1849         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1850         uint16_t sum_queues = 0, sum_vsis;
1851
1852         /* First check if FW support SRIOV */
1853         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1854                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1855                 return -EINVAL;
1856         }
1857
1858         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1859         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1860         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1861         /* Allocate queues for pf */
1862         if (hw->func_caps.rss) {
1863                 pf->flags |= I40E_FLAG_RSS;
1864                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1865                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1866                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1867         } else
1868                 pf->lan_nb_qps = 1;
1869         sum_queues = pf->lan_nb_qps;
1870         /* Default VSI is not counted in */
1871         sum_vsis = 0;
1872         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1873
1874         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1875                 pf->flags |= I40E_FLAG_SRIOV;
1876                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1877                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1878                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1879                                      "max supported %u.",
1880                                      dev->pci_dev->max_vfs,
1881                                      hw->func_caps.num_vfs);
1882                         return -EINVAL;
1883                 }
1884                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1885                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1886                                      "max support %u queues.",
1887                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1888                         return -EINVAL;
1889                 }
1890                 pf->vf_num = dev->pci_dev->max_vfs;
1891                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1892                 sum_vsis   += pf->vf_num;
1893                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1894                              pf->vf_num, pf->vf_nb_qps);
1895         } else
1896                 pf->vf_num = 0;
1897
1898         if (hw->func_caps.vmdq) {
1899                 pf->flags |= I40E_FLAG_VMDQ;
1900                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1901                 sum_queues += pf->vmdq_nb_qps;
1902                 sum_vsis += 1;
1903                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1904         }
1905
1906         if (hw->func_caps.fd) {
1907                 pf->flags |= I40E_FLAG_FDIR;
1908                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1909                 /**
1910                  * Each flow director consumes one VSI and one queue,
1911                  * but can't calculate out predictably here.
1912                  */
1913         }
1914
1915         if (sum_vsis > pf->max_num_vsi ||
1916                 sum_queues > hw->func_caps.num_rx_qp) {
1917                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1918                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1919                              pf->max_num_vsi, sum_vsis);
1920                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1921                              hw->func_caps.num_rx_qp, sum_queues);
1922                 return -EINVAL;
1923         }
1924
1925         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1926          * cause */
1927         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1928                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1929                              sum_vsis, hw->func_caps.num_msix_vectors);
1930                 return -EINVAL;
1931         }
1932         return I40E_SUCCESS;
1933 }
1934
1935 static int
1936 i40e_pf_get_switch_config(struct i40e_pf *pf)
1937 {
1938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1939         struct i40e_aqc_get_switch_config_resp *switch_config;
1940         struct i40e_aqc_switch_config_element_resp *element;
1941         uint16_t start_seid = 0, num_reported;
1942         int ret;
1943
1944         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1945                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1946         if (!switch_config) {
1947                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1948                 return -ENOMEM;
1949         }
1950
1951         /* Get the switch configurations */
1952         ret = i40e_aq_get_switch_config(hw, switch_config,
1953                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1954         if (ret != I40E_SUCCESS) {
1955                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1956                 goto fail;
1957         }
1958         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1959         if (num_reported != 1) { /* The number should be 1 */
1960                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1961                 goto fail;
1962         }
1963
1964         /* Parse the switch configuration elements */
1965         element = &(switch_config->element[0]);
1966         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1967                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1968                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1969         } else
1970                 PMD_DRV_LOG(INFO, "Unknown element type");
1971
1972 fail:
1973         rte_free(switch_config);
1974
1975         return ret;
1976 }
1977
1978 static int
1979 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1980                         uint32_t num)
1981 {
1982         struct pool_entry *entry;
1983
1984         if (pool == NULL || num == 0)
1985                 return -EINVAL;
1986
1987         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1988         if (entry == NULL) {
1989                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1990                 return -ENOMEM;
1991         }
1992
1993         /* queue heap initialize */
1994         pool->num_free = num;
1995         pool->num_alloc = 0;
1996         pool->base = base;
1997         LIST_INIT(&pool->alloc_list);
1998         LIST_INIT(&pool->free_list);
1999
2000         /* Initialize element  */
2001         entry->base = 0;
2002         entry->len = num;
2003
2004         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2005         return 0;
2006 }
2007
2008 static void
2009 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2010 {
2011         struct pool_entry *entry;
2012
2013         if (pool == NULL)
2014                 return;
2015
2016         LIST_FOREACH(entry, &pool->alloc_list, next) {
2017                 LIST_REMOVE(entry, next);
2018                 rte_free(entry);
2019         }
2020
2021         LIST_FOREACH(entry, &pool->free_list, next) {
2022                 LIST_REMOVE(entry, next);
2023                 rte_free(entry);
2024         }
2025
2026         pool->num_free = 0;
2027         pool->num_alloc = 0;
2028         pool->base = 0;
2029         LIST_INIT(&pool->alloc_list);
2030         LIST_INIT(&pool->free_list);
2031 }
2032
2033 static int
2034 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2035                        uint32_t base)
2036 {
2037         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2038         uint32_t pool_offset;
2039         int insert;
2040
2041         if (pool == NULL) {
2042                 PMD_DRV_LOG(ERR, "Invalid parameter");
2043                 return -EINVAL;
2044         }
2045
2046         pool_offset = base - pool->base;
2047         /* Lookup in alloc list */
2048         LIST_FOREACH(entry, &pool->alloc_list, next) {
2049                 if (entry->base == pool_offset) {
2050                         valid_entry = entry;
2051                         LIST_REMOVE(entry, next);
2052                         break;
2053                 }
2054         }
2055
2056         /* Not find, return */
2057         if (valid_entry == NULL) {
2058                 PMD_DRV_LOG(ERR, "Failed to find entry");
2059                 return -EINVAL;
2060         }
2061
2062         /**
2063          * Found it, move it to free list  and try to merge.
2064          * In order to make merge easier, always sort it by qbase.
2065          * Find adjacent prev and last entries.
2066          */
2067         prev = next = NULL;
2068         LIST_FOREACH(entry, &pool->free_list, next) {
2069                 if (entry->base > valid_entry->base) {
2070                         next = entry;
2071                         break;
2072                 }
2073                 prev = entry;
2074         }
2075
2076         insert = 0;
2077         /* Try to merge with next one*/
2078         if (next != NULL) {
2079                 /* Merge with next one */
2080                 if (valid_entry->base + valid_entry->len == next->base) {
2081                         next->base = valid_entry->base;
2082                         next->len += valid_entry->len;
2083                         rte_free(valid_entry);
2084                         valid_entry = next;
2085                         insert = 1;
2086                 }
2087         }
2088
2089         if (prev != NULL) {
2090                 /* Merge with previous one */
2091                 if (prev->base + prev->len == valid_entry->base) {
2092                         prev->len += valid_entry->len;
2093                         /* If it merge with next one, remove next node */
2094                         if (insert == 1) {
2095                                 LIST_REMOVE(valid_entry, next);
2096                                 rte_free(valid_entry);
2097                         } else {
2098                                 rte_free(valid_entry);
2099                                 insert = 1;
2100                         }
2101                 }
2102         }
2103
2104         /* Not find any entry to merge, insert */
2105         if (insert == 0) {
2106                 if (prev != NULL)
2107                         LIST_INSERT_AFTER(prev, valid_entry, next);
2108                 else if (next != NULL)
2109                         LIST_INSERT_BEFORE(next, valid_entry, next);
2110                 else /* It's empty list, insert to head */
2111                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2112         }
2113
2114         pool->num_free += valid_entry->len;
2115         pool->num_alloc -= valid_entry->len;
2116
2117         return 0;
2118 }
2119
2120 static int
2121 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2122                        uint16_t num)
2123 {
2124         struct pool_entry *entry, *valid_entry;
2125
2126         if (pool == NULL || num == 0) {
2127                 PMD_DRV_LOG(ERR, "Invalid parameter");
2128                 return -EINVAL;
2129         }
2130
2131         if (pool->num_free < num) {
2132                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2133                             num, pool->num_free);
2134                 return -ENOMEM;
2135         }
2136
2137         valid_entry = NULL;
2138         /* Lookup  in free list and find most fit one */
2139         LIST_FOREACH(entry, &pool->free_list, next) {
2140                 if (entry->len >= num) {
2141                         /* Find best one */
2142                         if (entry->len == num) {
2143                                 valid_entry = entry;
2144                                 break;
2145                         }
2146                         if (valid_entry == NULL || valid_entry->len > entry->len)
2147                                 valid_entry = entry;
2148                 }
2149         }
2150
2151         /* Not find one to satisfy the request, return */
2152         if (valid_entry == NULL) {
2153                 PMD_DRV_LOG(ERR, "No valid entry found");
2154                 return -ENOMEM;
2155         }
2156         /**
2157          * The entry have equal queue number as requested,
2158          * remove it from alloc_list.
2159          */
2160         if (valid_entry->len == num) {
2161                 LIST_REMOVE(valid_entry, next);
2162         } else {
2163                 /**
2164                  * The entry have more numbers than requested,
2165                  * create a new entry for alloc_list and minus its
2166                  * queue base and number in free_list.
2167                  */
2168                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2169                 if (entry == NULL) {
2170                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2171                                     "resource pool");
2172                         return -ENOMEM;
2173                 }
2174                 entry->base = valid_entry->base;
2175                 entry->len = num;
2176                 valid_entry->base += num;
2177                 valid_entry->len -= num;
2178                 valid_entry = entry;
2179         }
2180
2181         /* Insert it into alloc list, not sorted */
2182         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2183
2184         pool->num_free -= valid_entry->len;
2185         pool->num_alloc += valid_entry->len;
2186
2187         return (valid_entry->base + pool->base);
2188 }
2189
2190 /**
2191  * bitmap_is_subset - Check whether src2 is subset of src1
2192  **/
2193 static inline int
2194 bitmap_is_subset(uint8_t src1, uint8_t src2)
2195 {
2196         return !((src1 ^ src2) & src2);
2197 }
2198
2199 static int
2200 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2201 {
2202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203
2204         /* If DCB is not supported, only default TC is supported */
2205         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2206                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2207                 return -EINVAL;
2208         }
2209
2210         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2211                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2212                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2213                             enabled_tcmap);
2214                 return -EINVAL;
2215         }
2216         return I40E_SUCCESS;
2217 }
2218
2219 int
2220 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2221                                 struct i40e_vsi_vlan_pvid_info *info)
2222 {
2223         struct i40e_hw *hw;
2224         struct i40e_vsi_context ctxt;
2225         uint8_t vlan_flags = 0;
2226         int ret;
2227
2228         if (vsi == NULL || info == NULL) {
2229                 PMD_DRV_LOG(ERR, "invalid parameters");
2230                 return I40E_ERR_PARAM;
2231         }
2232
2233         if (info->on) {
2234                 vsi->info.pvid = info->config.pvid;
2235                 /**
2236                  * If insert pvid is enabled, only tagged pkts are
2237                  * allowed to be sent out.
2238                  */
2239                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2240                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2241         } else {
2242                 vsi->info.pvid = 0;
2243                 if (info->config.reject.tagged == 0)
2244                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2245
2246                 if (info->config.reject.untagged == 0)
2247                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2248         }
2249         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2250                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2251         vsi->info.port_vlan_flags |= vlan_flags;
2252         vsi->info.valid_sections =
2253                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2254         memset(&ctxt, 0, sizeof(ctxt));
2255         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2256         ctxt.seid = vsi->seid;
2257
2258         hw = I40E_VSI_TO_HW(vsi);
2259         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2260         if (ret != I40E_SUCCESS)
2261                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2262
2263         return ret;
2264 }
2265
2266 static int
2267 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2268 {
2269         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2270         int i, ret;
2271         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2272
2273         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2274         if (ret != I40E_SUCCESS)
2275                 return ret;
2276
2277         if (!vsi->seid) {
2278                 PMD_DRV_LOG(ERR, "seid not valid");
2279                 return -EINVAL;
2280         }
2281
2282         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2283         tc_bw_data.tc_valid_bits = enabled_tcmap;
2284         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2285                 tc_bw_data.tc_bw_credits[i] =
2286                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2287
2288         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2289         if (ret != I40E_SUCCESS) {
2290                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2291                 return ret;
2292         }
2293
2294         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2295                                         sizeof(vsi->info.qs_handle));
2296         return I40E_SUCCESS;
2297 }
2298
2299 static int
2300 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2301                                  struct i40e_aqc_vsi_properties_data *info,
2302                                  uint8_t enabled_tcmap)
2303 {
2304         int ret, total_tc = 0, i;
2305         uint16_t qpnum_per_tc, bsf, qp_idx;
2306
2307         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2308         if (ret != I40E_SUCCESS)
2309                 return ret;
2310
2311         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2312                 if (enabled_tcmap & (1 << i))
2313                         total_tc++;
2314         vsi->enabled_tc = enabled_tcmap;
2315
2316         /* Number of queues per enabled TC */
2317         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2318         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2319         bsf = rte_bsf32(qpnum_per_tc);
2320
2321         /* Adjust the queue number to actual queues that can be applied */
2322         vsi->nb_qps = qpnum_per_tc * total_tc;
2323
2324         /**
2325          * Configure TC and queue mapping parameters, for enabled TC,
2326          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2327          * default queue will serve it.
2328          */
2329         qp_idx = 0;
2330         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2331                 if (vsi->enabled_tc & (1 << i)) {
2332                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2333                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2334                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2335                         qp_idx += qpnum_per_tc;
2336                 } else
2337                         info->tc_mapping[i] = 0;
2338         }
2339
2340         /* Associate queue number with VSI */
2341         if (vsi->type == I40E_VSI_SRIOV) {
2342                 info->mapping_flags |=
2343                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2344                 for (i = 0; i < vsi->nb_qps; i++)
2345                         info->queue_mapping[i] =
2346                                 rte_cpu_to_le_16(vsi->base_queue + i);
2347         } else {
2348                 info->mapping_flags |=
2349                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2350                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2351         }
2352         info->valid_sections =
2353                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2354
2355         return I40E_SUCCESS;
2356 }
2357
2358 static int
2359 i40e_veb_release(struct i40e_veb *veb)
2360 {
2361         struct i40e_vsi *vsi;
2362         struct i40e_hw *hw;
2363
2364         if (veb == NULL || veb->associate_vsi == NULL)
2365                 return -EINVAL;
2366
2367         if (!TAILQ_EMPTY(&veb->head)) {
2368                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2369                 return -EACCES;
2370         }
2371
2372         vsi = veb->associate_vsi;
2373         hw = I40E_VSI_TO_HW(vsi);
2374
2375         vsi->uplink_seid = veb->uplink_seid;
2376         i40e_aq_delete_element(hw, veb->seid, NULL);
2377         rte_free(veb);
2378         vsi->veb = NULL;
2379         return I40E_SUCCESS;
2380 }
2381
2382 /* Setup a veb */
2383 static struct i40e_veb *
2384 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2385 {
2386         struct i40e_veb *veb;
2387         int ret;
2388         struct i40e_hw *hw;
2389
2390         if (NULL == pf || vsi == NULL) {
2391                 PMD_DRV_LOG(ERR, "veb setup failed, "
2392                             "associated VSI shouldn't null");
2393                 return NULL;
2394         }
2395         hw = I40E_PF_TO_HW(pf);
2396
2397         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2398         if (!veb) {
2399                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2400                 goto fail;
2401         }
2402
2403         veb->associate_vsi = vsi;
2404         TAILQ_INIT(&veb->head);
2405         veb->uplink_seid = vsi->uplink_seid;
2406
2407         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2408                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2409
2410         if (ret != I40E_SUCCESS) {
2411                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2412                             hw->aq.asq_last_status);
2413                 goto fail;
2414         }
2415
2416         /* get statistics index */
2417         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2418                                 &veb->stats_idx, NULL, NULL, NULL);
2419         if (ret != I40E_SUCCESS) {
2420                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2421                             hw->aq.asq_last_status);
2422                 goto fail;
2423         }
2424
2425         /* Get VEB bandwidth, to be implemented */
2426         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2427         vsi->uplink_seid = veb->seid;
2428
2429         return veb;
2430 fail:
2431         rte_free(veb);
2432         return NULL;
2433 }
2434
2435 int
2436 i40e_vsi_release(struct i40e_vsi *vsi)
2437 {
2438         struct i40e_pf *pf;
2439         struct i40e_hw *hw;
2440         struct i40e_vsi_list *vsi_list;
2441         int ret;
2442         struct i40e_mac_filter *f;
2443
2444         if (!vsi)
2445                 return I40E_SUCCESS;
2446
2447         pf = I40E_VSI_TO_PF(vsi);
2448         hw = I40E_VSI_TO_HW(vsi);
2449
2450         /* VSI has child to attach, release child first */
2451         if (vsi->veb) {
2452                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2453                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2454                                 return -1;
2455                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2456                 }
2457                 i40e_veb_release(vsi->veb);
2458         }
2459
2460         /* Remove all macvlan filters of the VSI */
2461         i40e_vsi_remove_all_macvlan_filter(vsi);
2462         TAILQ_FOREACH(f, &vsi->mac_list, next)
2463                 rte_free(f);
2464
2465         if (vsi->type != I40E_VSI_MAIN) {
2466                 /* Remove vsi from parent's sibling list */
2467                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2468                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2469                         return I40E_ERR_PARAM;
2470                 }
2471                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2472                                 &vsi->sib_vsi_list, list);
2473
2474                 /* Remove all switch element of the VSI */
2475                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2476                 if (ret != I40E_SUCCESS)
2477                         PMD_DRV_LOG(ERR, "Failed to delete element");
2478         }
2479         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2480
2481         if (vsi->type != I40E_VSI_SRIOV)
2482                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2483         rte_free(vsi);
2484
2485         return I40E_SUCCESS;
2486 }
2487
2488 static int
2489 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2490 {
2491         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2492         struct i40e_aqc_remove_macvlan_element_data def_filter;
2493         int ret;
2494
2495         if (vsi->type != I40E_VSI_MAIN)
2496                 return I40E_ERR_CONFIG;
2497         memset(&def_filter, 0, sizeof(def_filter));
2498         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2499                                         ETH_ADDR_LEN);
2500         def_filter.vlan_tag = 0;
2501         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2502                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2503         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2504         if (ret != I40E_SUCCESS) {
2505                 struct i40e_mac_filter *f;
2506
2507                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2508                             "macvlan filter");
2509                 /* It needs to add the permanent mac into mac list */
2510                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2511                 if (f == NULL) {
2512                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2513                         return I40E_ERR_NO_MEMORY;
2514                 }
2515                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2516                                 ETH_ADDR_LEN);
2517                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2518                 vsi->mac_num++;
2519
2520                 return ret;
2521         }
2522
2523         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2524 }
2525
2526 static int
2527 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2528 {
2529         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2530         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2531         struct i40e_hw *hw = &vsi->adapter->hw;
2532         i40e_status ret;
2533         int i;
2534
2535         memset(&bw_config, 0, sizeof(bw_config));
2536         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2537         if (ret != I40E_SUCCESS) {
2538                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2539                             hw->aq.asq_last_status);
2540                 return ret;
2541         }
2542
2543         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2544         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2545                                         &ets_sla_config, NULL);
2546         if (ret != I40E_SUCCESS) {
2547                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2548                             "configuration %u", hw->aq.asq_last_status);
2549                 return ret;
2550         }
2551
2552         /* Not store the info yet, just print out */
2553         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2554         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2555         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2556                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2557                             ets_sla_config.share_credits[i]);
2558                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2559                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2560                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2561                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2562                             (i * 4));
2563         }
2564
2565         return 0;
2566 }
2567
2568 /* Setup a VSI */
2569 struct i40e_vsi *
2570 i40e_vsi_setup(struct i40e_pf *pf,
2571                enum i40e_vsi_type type,
2572                struct i40e_vsi *uplink_vsi,
2573                uint16_t user_param)
2574 {
2575         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2576         struct i40e_vsi *vsi;
2577         int ret;
2578         struct i40e_vsi_context ctxt;
2579         struct ether_addr broadcast =
2580                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2581
2582         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2583                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2584                             "VSI link shouldn't be NULL");
2585                 return NULL;
2586         }
2587
2588         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2589                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2590                             "uplink VSI should be NULL");
2591                 return NULL;
2592         }
2593
2594         /* If uplink vsi didn't setup VEB, create one first */
2595         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2596                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2597
2598                 if (NULL == uplink_vsi->veb) {
2599                         PMD_DRV_LOG(ERR, "VEB setup failed");
2600                         return NULL;
2601                 }
2602         }
2603
2604         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2605         if (!vsi) {
2606                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2607                 return NULL;
2608         }
2609         TAILQ_INIT(&vsi->mac_list);
2610         vsi->type = type;
2611         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2612         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2613         vsi->parent_vsi = uplink_vsi;
2614         vsi->user_param = user_param;
2615         /* Allocate queues */
2616         switch (vsi->type) {
2617         case I40E_VSI_MAIN  :
2618                 vsi->nb_qps = pf->lan_nb_qps;
2619                 break;
2620         case I40E_VSI_SRIOV :
2621                 vsi->nb_qps = pf->vf_nb_qps;
2622                 break;
2623         default:
2624                 goto fail_mem;
2625         }
2626         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2627         if (ret < 0) {
2628                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2629                                 vsi->seid, ret);
2630                 goto fail_mem;
2631         }
2632         vsi->base_queue = ret;
2633
2634         /* VF has MSIX interrupt in VF range, don't allocate here */
2635         if (type != I40E_VSI_SRIOV) {
2636                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2637                 if (ret < 0) {
2638                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2639                         goto fail_queue_alloc;
2640                 }
2641                 vsi->msix_intr = ret;
2642         } else
2643                 vsi->msix_intr = 0;
2644         /* Add VSI */
2645         if (type == I40E_VSI_MAIN) {
2646                 /* For main VSI, no need to add since it's default one */
2647                 vsi->uplink_seid = pf->mac_seid;
2648                 vsi->seid = pf->main_vsi_seid;
2649                 /* Bind queues with specific MSIX interrupt */
2650                 /**
2651                  * Needs 2 interrupt at least, one for misc cause which will
2652                  * enabled from OS side, Another for queues binding the
2653                  * interrupt from device side only.
2654                  */
2655
2656                 /* Get default VSI parameters from hardware */
2657                 memset(&ctxt, 0, sizeof(ctxt));
2658                 ctxt.seid = vsi->seid;
2659                 ctxt.pf_num = hw->pf_id;
2660                 ctxt.uplink_seid = vsi->uplink_seid;
2661                 ctxt.vf_num = 0;
2662                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2663                 if (ret != I40E_SUCCESS) {
2664                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2665                         goto fail_msix_alloc;
2666                 }
2667                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2668                         sizeof(struct i40e_aqc_vsi_properties_data));
2669                 vsi->vsi_id = ctxt.vsi_number;
2670                 vsi->info.valid_sections = 0;
2671
2672                 /* Configure tc, enabled TC0 only */
2673                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2674                         I40E_SUCCESS) {
2675                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2676                         goto fail_msix_alloc;
2677                 }
2678
2679                 /* TC, queue mapping */
2680                 memset(&ctxt, 0, sizeof(ctxt));
2681                 vsi->info.valid_sections |=
2682                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2683                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2684                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2685                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2686                         sizeof(struct i40e_aqc_vsi_properties_data));
2687                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2688                                                 I40E_DEFAULT_TCMAP);
2689                 if (ret != I40E_SUCCESS) {
2690                         PMD_DRV_LOG(ERR, "Failed to configure "
2691                                     "TC queue mapping");
2692                         goto fail_msix_alloc;
2693                 }
2694                 ctxt.seid = vsi->seid;
2695                 ctxt.pf_num = hw->pf_id;
2696                 ctxt.uplink_seid = vsi->uplink_seid;
2697                 ctxt.vf_num = 0;
2698
2699                 /* Update VSI parameters */
2700                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2701                 if (ret != I40E_SUCCESS) {
2702                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2703                         goto fail_msix_alloc;
2704                 }
2705
2706                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2707                                                 sizeof(vsi->info.tc_mapping));
2708                 (void)rte_memcpy(&vsi->info.queue_mapping,
2709                                 &ctxt.info.queue_mapping,
2710                         sizeof(vsi->info.queue_mapping));
2711                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2712                 vsi->info.valid_sections = 0;
2713
2714                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2715                                 ETH_ADDR_LEN);
2716
2717                 /**
2718                  * Updating default filter settings are necessary to prevent
2719                  * reception of tagged packets.
2720                  * Some old firmware configurations load a default macvlan
2721                  * filter which accepts both tagged and untagged packets.
2722                  * The updating is to use a normal filter instead if needed.
2723                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2724                  * The firmware with correct configurations load the default
2725                  * macvlan filter which is expected and cannot be removed.
2726                  */
2727                 i40e_update_default_filter_setting(vsi);
2728         } else if (type == I40E_VSI_SRIOV) {
2729                 memset(&ctxt, 0, sizeof(ctxt));
2730                 /**
2731                  * For other VSI, the uplink_seid equals to uplink VSI's
2732                  * uplink_seid since they share same VEB
2733                  */
2734                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2735                 ctxt.pf_num = hw->pf_id;
2736                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2737                 ctxt.uplink_seid = vsi->uplink_seid;
2738                 ctxt.connection_type = 0x1;
2739                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2740
2741                 /* Configure switch ID */
2742                 ctxt.info.valid_sections |=
2743                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2744                 ctxt.info.switch_id =
2745                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2746                 /* Configure port/vlan */
2747                 ctxt.info.valid_sections |=
2748                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2749                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2750                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2751                                                 I40E_DEFAULT_TCMAP);
2752                 if (ret != I40E_SUCCESS) {
2753                         PMD_DRV_LOG(ERR, "Failed to configure "
2754                                     "TC queue mapping");
2755                         goto fail_msix_alloc;
2756                 }
2757                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2758                 ctxt.info.valid_sections |=
2759                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2760                 /**
2761                  * Since VSI is not created yet, only configure parameter,
2762                  * will add vsi below.
2763                  */
2764         }
2765         else {
2766                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2767                 goto fail_msix_alloc;
2768         }
2769
2770         if (vsi->type != I40E_VSI_MAIN) {
2771                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2772                 if (ret) {
2773                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2774                                     hw->aq.asq_last_status);
2775                         goto fail_msix_alloc;
2776                 }
2777                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2778                 vsi->info.valid_sections = 0;
2779                 vsi->seid = ctxt.seid;
2780                 vsi->vsi_id = ctxt.vsi_number;
2781                 vsi->sib_vsi_list.vsi = vsi;
2782                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2783                                 &vsi->sib_vsi_list, list);
2784         }
2785
2786         /* MAC/VLAN configuration */
2787         ret = i40e_vsi_add_mac(vsi, &broadcast);
2788         if (ret != I40E_SUCCESS) {
2789                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2790                 goto fail_msix_alloc;
2791         }
2792
2793         /* Get VSI BW information */
2794         i40e_vsi_dump_bw_config(vsi);
2795         return vsi;
2796 fail_msix_alloc:
2797         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2798 fail_queue_alloc:
2799         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2800 fail_mem:
2801         rte_free(vsi);
2802         return NULL;
2803 }
2804
2805 /* Configure vlan stripping on or off */
2806 int
2807 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2808 {
2809         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2810         struct i40e_vsi_context ctxt;
2811         uint8_t vlan_flags;
2812         int ret = I40E_SUCCESS;
2813
2814         /* Check if it has been already on or off */
2815         if (vsi->info.valid_sections &
2816                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2817                 if (on) {
2818                         if ((vsi->info.port_vlan_flags &
2819                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2820                                 return 0; /* already on */
2821                 } else {
2822                         if ((vsi->info.port_vlan_flags &
2823                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2824                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2825                                 return 0; /* already off */
2826                 }
2827         }
2828
2829         if (on)
2830                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2831         else
2832                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2833         vsi->info.valid_sections =
2834                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2835         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2836         vsi->info.port_vlan_flags |= vlan_flags;
2837         ctxt.seid = vsi->seid;
2838         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2839         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2840         if (ret)
2841                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2842                             on ? "enable" : "disable");
2843
2844         return ret;
2845 }
2846
2847 static int
2848 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2849 {
2850         struct rte_eth_dev_data *data = dev->data;
2851         int ret;
2852
2853         /* Apply vlan offload setting */
2854         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2855
2856         /* Apply double-vlan setting, not implemented yet */
2857
2858         /* Apply pvid setting */
2859         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2860                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2861         if (ret)
2862                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2863
2864         return ret;
2865 }
2866
2867 static int
2868 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2869 {
2870         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2871
2872         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2873 }
2874
2875 static int
2876 i40e_update_flow_control(struct i40e_hw *hw)
2877 {
2878 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2879         struct i40e_link_status link_status;
2880         uint32_t rxfc = 0, txfc = 0, reg;
2881         uint8_t an_info;
2882         int ret;
2883
2884         memset(&link_status, 0, sizeof(link_status));
2885         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2886         if (ret != I40E_SUCCESS) {
2887                 PMD_DRV_LOG(ERR, "Failed to get link status information");
2888                 goto write_reg; /* Disable flow control */
2889         }
2890
2891         an_info = hw->phy.link_info.an_info;
2892         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2893                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2894                 ret = I40E_ERR_NOT_READY;
2895                 goto write_reg; /* Disable flow control */
2896         }
2897         /**
2898          * If link auto negotiation is enabled, flow control needs to
2899          * be configured according to it
2900          */
2901         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2902         case I40E_LINK_PAUSE_RXTX:
2903                 rxfc = 1;
2904                 txfc = 1;
2905                 hw->fc.current_mode = I40E_FC_FULL;
2906                 break;
2907         case I40E_AQ_LINK_PAUSE_RX:
2908                 rxfc = 1;
2909                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2910                 break;
2911         case I40E_AQ_LINK_PAUSE_TX:
2912                 txfc = 1;
2913                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2914                 break;
2915         default:
2916                 hw->fc.current_mode = I40E_FC_NONE;
2917                 break;
2918         }
2919
2920 write_reg:
2921         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2922                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2923         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2924         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2925         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2926         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2927
2928         return ret;
2929 }
2930
2931 /* PF setup */
2932 static int
2933 i40e_pf_setup(struct i40e_pf *pf)
2934 {
2935         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2936         struct i40e_filter_control_settings settings;
2937         struct rte_eth_dev_data *dev_data = pf->dev_data;
2938         struct i40e_vsi *vsi;
2939         int ret;
2940
2941         /* Clear all stats counters */
2942         pf->offset_loaded = FALSE;
2943         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2944         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2945
2946         ret = i40e_pf_get_switch_config(pf);
2947         if (ret != I40E_SUCCESS) {
2948                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2949                 return ret;
2950         }
2951
2952         /* VSI setup */
2953         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2954         if (!vsi) {
2955                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2956                 return I40E_ERR_NOT_READY;
2957         }
2958         pf->main_vsi = vsi;
2959         dev_data->nb_rx_queues = vsi->nb_qps;
2960         dev_data->nb_tx_queues = vsi->nb_qps;
2961
2962         /* Configure filter control */
2963         memset(&settings, 0, sizeof(settings));
2964         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2965         /* Enable ethtype and macvlan filters */
2966         settings.enable_ethtype = TRUE;
2967         settings.enable_macvlan = TRUE;
2968         ret = i40e_set_filter_control(hw, &settings);
2969         if (ret)
2970                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2971                                                                 ret);
2972
2973         /* Update flow control according to the auto negotiation */
2974         i40e_update_flow_control(hw);
2975
2976         return I40E_SUCCESS;
2977 }
2978
2979 int
2980 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2981 {
2982         uint32_t reg;
2983         uint16_t j;
2984
2985         /**
2986          * Set or clear TX Queue Disable flags,
2987          * which is required by hardware.
2988          */
2989         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2990         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2991
2992         /* Wait until the request is finished */
2993         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2994                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2995                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2996                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2997                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2998                                                         & 0x1))) {
2999                         break;
3000                 }
3001         }
3002         if (on) {
3003                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3004                         return I40E_SUCCESS; /* already on, skip next steps */
3005
3006                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3007                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3008         } else {
3009                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3010                         return I40E_SUCCESS; /* already off, skip next steps */
3011                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3012         }
3013         /* Write the register */
3014         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3015         /* Check the result */
3016         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3017                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3018                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3019                 if (on) {
3020                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3021                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3022                                 break;
3023                 } else {
3024                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3025                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3026                                 break;
3027                 }
3028         }
3029         /* Check if it is timeout */
3030         if (j >= I40E_CHK_Q_ENA_COUNT) {
3031                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3032                             (on ? "enable" : "disable"), q_idx);
3033                 return I40E_ERR_TIMEOUT;
3034         }
3035
3036         return I40E_SUCCESS;
3037 }
3038
3039 /* Swith on or off the tx queues */
3040 static int
3041 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3042 {
3043         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3044         struct i40e_tx_queue *txq;
3045         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3046         uint16_t i;
3047         int ret;
3048
3049         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3050                 txq = dev_data->tx_queues[i];
3051                 /* Don't operate the queue if not configured or
3052                  * if starting only per queue */
3053                 if (!txq->q_set || (on && txq->tx_deferred_start))
3054                         continue;
3055                 if (on)
3056                         ret = i40e_dev_tx_queue_start(dev, i);
3057                 else
3058                         ret = i40e_dev_tx_queue_stop(dev, i);
3059                 if ( ret != I40E_SUCCESS)
3060                         return ret;
3061         }
3062
3063         return I40E_SUCCESS;
3064 }
3065
3066 int
3067 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3068 {
3069         uint32_t reg;
3070         uint16_t j;
3071
3072         /* Wait until the request is finished */
3073         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3074                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3075                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3076                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3077                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3078                         break;
3079         }
3080
3081         if (on) {
3082                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3083                         return I40E_SUCCESS; /* Already on, skip next steps */
3084                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3085         } else {
3086                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3087                         return I40E_SUCCESS; /* Already off, skip next steps */
3088                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3089         }
3090
3091         /* Write the register */
3092         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3093         /* Check the result */
3094         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3095                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3096                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3097                 if (on) {
3098                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3099                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3100                                 break;
3101                 } else {
3102                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3103                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3104                                 break;
3105                 }
3106         }
3107
3108         /* Check if it is timeout */
3109         if (j >= I40E_CHK_Q_ENA_COUNT) {
3110                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3111                             (on ? "enable" : "disable"), q_idx);
3112                 return I40E_ERR_TIMEOUT;
3113         }
3114
3115         return I40E_SUCCESS;
3116 }
3117 /* Switch on or off the rx queues */
3118 static int
3119 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3120 {
3121         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3122         struct i40e_rx_queue *rxq;
3123         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3124         uint16_t i;
3125         int ret;
3126
3127         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3128                 rxq = dev_data->rx_queues[i];
3129                 /* Don't operate the queue if not configured or
3130                  * if starting only per queue */
3131                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3132                         continue;
3133                 if (on)
3134                         ret = i40e_dev_rx_queue_start(dev, i);
3135                 else
3136                         ret = i40e_dev_rx_queue_stop(dev, i);
3137                 if (ret != I40E_SUCCESS)
3138                         return ret;
3139         }
3140
3141         return I40E_SUCCESS;
3142 }
3143
3144 /* Switch on or off all the rx/tx queues */
3145 int
3146 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3147 {
3148         int ret;
3149
3150         if (on) {
3151                 /* enable rx queues before enabling tx queues */
3152                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3153                 if (ret) {
3154                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3155                         return ret;
3156                 }
3157                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3158         } else {
3159                 /* Stop tx queues before stopping rx queues */
3160                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3161                 if (ret) {
3162                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3163                         return ret;
3164                 }
3165                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3166         }
3167
3168         return ret;
3169 }
3170
3171 /* Initialize VSI for TX */
3172 static int
3173 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3174 {
3175         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3176         struct rte_eth_dev_data *data = pf->dev_data;
3177         uint16_t i;
3178         uint32_t ret = I40E_SUCCESS;
3179
3180         for (i = 0; i < data->nb_tx_queues; i++) {
3181                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3182                 if (ret != I40E_SUCCESS)
3183                         break;
3184         }
3185
3186         return ret;
3187 }
3188
3189 /* Initialize VSI for RX */
3190 static int
3191 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3192 {
3193         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3194         struct rte_eth_dev_data *data = pf->dev_data;
3195         int ret = I40E_SUCCESS;
3196         uint16_t i;
3197
3198         i40e_pf_config_mq_rx(pf);
3199         for (i = 0; i < data->nb_rx_queues; i++) {
3200                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3201                 if (ret != I40E_SUCCESS) {
3202                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3203                                     "initialization");
3204                         break;
3205                 }
3206         }
3207
3208         return ret;
3209 }
3210
3211 /* Initialize VSI */
3212 static int
3213 i40e_vsi_init(struct i40e_vsi *vsi)
3214 {
3215         int err;
3216
3217         err = i40e_vsi_tx_init(vsi);
3218         if (err) {
3219                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3220                 return err;
3221         }
3222         err = i40e_vsi_rx_init(vsi);
3223         if (err) {
3224                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3225                 return err;
3226         }
3227
3228         return err;
3229 }
3230
3231 static void
3232 i40e_stat_update_32(struct i40e_hw *hw,
3233                    uint32_t reg,
3234                    bool offset_loaded,
3235                    uint64_t *offset,
3236                    uint64_t *stat)
3237 {
3238         uint64_t new_data;
3239
3240         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3241         if (!offset_loaded)
3242                 *offset = new_data;
3243
3244         if (new_data >= *offset)
3245                 *stat = (uint64_t)(new_data - *offset);
3246         else
3247                 *stat = (uint64_t)((new_data +
3248                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3249 }
3250
3251 static void
3252 i40e_stat_update_48(struct i40e_hw *hw,
3253                    uint32_t hireg,
3254                    uint32_t loreg,
3255                    bool offset_loaded,
3256                    uint64_t *offset,
3257                    uint64_t *stat)
3258 {
3259         uint64_t new_data;
3260
3261         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3262         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3263                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3264
3265         if (!offset_loaded)
3266                 *offset = new_data;
3267
3268         if (new_data >= *offset)
3269                 *stat = new_data - *offset;
3270         else
3271                 *stat = (uint64_t)((new_data +
3272                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3273
3274         *stat &= I40E_48_BIT_MASK;
3275 }
3276
3277 /* Disable IRQ0 */
3278 void
3279 i40e_pf_disable_irq0(struct i40e_hw *hw)
3280 {
3281         /* Disable all interrupt types */
3282         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3283         I40E_WRITE_FLUSH(hw);
3284 }
3285
3286 /* Enable IRQ0 */
3287 void
3288 i40e_pf_enable_irq0(struct i40e_hw *hw)
3289 {
3290         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3291                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3292                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3293                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3294         I40E_WRITE_FLUSH(hw);
3295 }
3296
3297 static void
3298 i40e_pf_config_irq0(struct i40e_hw *hw)
3299 {
3300         uint32_t enable;
3301
3302         /* read pending request and disable first */
3303         i40e_pf_disable_irq0(hw);
3304         /**
3305          * Enable all interrupt error options to detect possible errors,
3306          * other informative int are ignored
3307          */
3308         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3309                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3310                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3311                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3312                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3313                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3314                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3315                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3316
3317         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3318         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3319                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3320
3321         /* Link no queues with irq0 */
3322         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3323                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3324 }
3325
3326 static void
3327 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3328 {
3329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3331         int i;
3332         uint16_t abs_vf_id;
3333         uint32_t index, offset, val;
3334
3335         if (!pf->vfs)
3336                 return;
3337         /**
3338          * Try to find which VF trigger a reset, use absolute VF id to access
3339          * since the reg is global register.
3340          */
3341         for (i = 0; i < pf->vf_num; i++) {
3342                 abs_vf_id = hw->func_caps.vf_base_id + i;
3343                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3344                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3345                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3346                 /* VFR event occured */
3347                 if (val & (0x1 << offset)) {
3348                         int ret;
3349
3350                         /* Clear the event first */
3351                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3352                                                         (0x1 << offset));
3353                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3354                         /**
3355                          * Only notify a VF reset event occured,
3356                          * don't trigger another SW reset
3357                          */
3358                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3359                         if (ret != I40E_SUCCESS)
3360                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3361                 }
3362         }
3363 }
3364
3365 static void
3366 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3367 {
3368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369         struct i40e_arq_event_info info;
3370         uint16_t pending, opcode;
3371         int ret;
3372
3373         info.buf_len = I40E_AQ_BUF_SZ;
3374         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3375         if (!info.msg_buf) {
3376                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3377                 return;
3378         }
3379
3380         pending = 1;
3381         while (pending) {
3382                 ret = i40e_clean_arq_element(hw, &info, &pending);
3383
3384                 if (ret != I40E_SUCCESS) {
3385                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3386                                     "aq_err: %u", hw->aq.asq_last_status);
3387                         break;
3388                 }
3389                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3390
3391                 switch (opcode) {
3392                 case i40e_aqc_opc_send_msg_to_pf:
3393                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3394                         i40e_pf_host_handle_vf_msg(dev,
3395                                         rte_le_to_cpu_16(info.desc.retval),
3396                                         rte_le_to_cpu_32(info.desc.cookie_high),
3397                                         rte_le_to_cpu_32(info.desc.cookie_low),
3398                                         info.msg_buf,
3399                                         info.msg_len);
3400                         break;
3401                 default:
3402                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3403                                     opcode);
3404                         break;
3405                 }
3406         }
3407         rte_free(info.msg_buf);
3408 }
3409
3410 /**
3411  * Interrupt handler triggered by NIC  for handling
3412  * specific interrupt.
3413  *
3414  * @param handle
3415  *  Pointer to interrupt handle.
3416  * @param param
3417  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3418  *
3419  * @return
3420  *  void
3421  */
3422 static void
3423 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3424                            void *param)
3425 {
3426         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428         uint32_t cause, enable;
3429
3430         i40e_pf_disable_irq0(hw);
3431
3432         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3433         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3434
3435         /* Shared IRQ case, return */
3436         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3437                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3438                             "no INT event to process", hw->pf_id);
3439                 goto done;
3440         }
3441
3442         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3443                 PMD_DRV_LOG(INFO, "INT:Link status changed");
3444                 i40e_dev_link_update(dev, 0);
3445         }
3446
3447         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3448                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3449
3450         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3451                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3452
3453         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3454                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3455
3456         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3457                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3458
3459         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3460                 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3461
3462         /* Add processing func to deal with VF reset vent */
3463         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3464                 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3465                 i40e_dev_handle_vfr_event(dev);
3466         }
3467         /* Find admin queue event */
3468         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3469                 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3470                 i40e_dev_handle_aq_msg(dev);
3471         }
3472
3473 done:
3474         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3475         /* Re-enable interrupt from device side */
3476         i40e_pf_enable_irq0(hw);
3477         /* Re-enable interrupt from host side */
3478         rte_intr_enable(&(dev->pci_dev->intr_handle));
3479 }
3480
3481 static int
3482 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3483                          struct i40e_macvlan_filter *filter,
3484                          int total)
3485 {
3486         int ele_num, ele_buff_size;
3487         int num, actual_num, i;
3488         int ret = I40E_SUCCESS;
3489         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3490         struct i40e_aqc_add_macvlan_element_data *req_list;
3491
3492         if (filter == NULL  || total == 0)
3493                 return I40E_ERR_PARAM;
3494         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3495         ele_buff_size = hw->aq.asq_buf_size;
3496
3497         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3498         if (req_list == NULL) {
3499                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3500                 return I40E_ERR_NO_MEMORY;
3501         }
3502
3503         num = 0;
3504         do {
3505                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3506                 memset(req_list, 0, ele_buff_size);
3507
3508                 for (i = 0; i < actual_num; i++) {
3509                         (void)rte_memcpy(req_list[i].mac_addr,
3510                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3511                         req_list[i].vlan_tag =
3512                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3513                         req_list[i].flags = rte_cpu_to_le_16(\
3514                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3515                         req_list[i].queue_number = 0;
3516                 }
3517
3518                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3519                                                 actual_num, NULL);
3520                 if (ret != I40E_SUCCESS) {
3521                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3522                         goto DONE;
3523                 }
3524                 num += actual_num;
3525         } while (num < total);
3526
3527 DONE:
3528         rte_free(req_list);
3529         return ret;
3530 }
3531
3532 static int
3533 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3534                             struct i40e_macvlan_filter *filter,
3535                             int total)
3536 {
3537         int ele_num, ele_buff_size;
3538         int num, actual_num, i;
3539         int ret = I40E_SUCCESS;
3540         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3541         struct i40e_aqc_remove_macvlan_element_data *req_list;
3542
3543         if (filter == NULL  || total == 0)
3544                 return I40E_ERR_PARAM;
3545
3546         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3547         ele_buff_size = hw->aq.asq_buf_size;
3548
3549         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3550         if (req_list == NULL) {
3551                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3552                 return I40E_ERR_NO_MEMORY;
3553         }
3554
3555         num = 0;
3556         do {
3557                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3558                 memset(req_list, 0, ele_buff_size);
3559
3560                 for (i = 0; i < actual_num; i++) {
3561                         (void)rte_memcpy(req_list[i].mac_addr,
3562                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3563                         req_list[i].vlan_tag =
3564                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3565                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3566                 }
3567
3568                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3569                                                 actual_num, NULL);
3570                 if (ret != I40E_SUCCESS) {
3571                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3572                         goto DONE;
3573                 }
3574                 num += actual_num;
3575         } while (num < total);
3576
3577 DONE:
3578         rte_free(req_list);
3579         return ret;
3580 }
3581
3582 /* Find out specific MAC filter */
3583 static struct i40e_mac_filter *
3584 i40e_find_mac_filter(struct i40e_vsi *vsi,
3585                          struct ether_addr *macaddr)
3586 {
3587         struct i40e_mac_filter *f;
3588
3589         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3590                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3591                         return f;
3592         }
3593
3594         return NULL;
3595 }
3596
3597 static bool
3598 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3599                          uint16_t vlan_id)
3600 {
3601         uint32_t vid_idx, vid_bit;
3602
3603         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3604         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3605
3606         if (vsi->vfta[vid_idx] & vid_bit)
3607                 return 1;
3608         else
3609                 return 0;
3610 }
3611
3612 static void
3613 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3614                          uint16_t vlan_id, bool on)
3615 {
3616         uint32_t vid_idx, vid_bit;
3617
3618 #define UINT32_BIT_MASK      0x1F
3619 #define VALID_VLAN_BIT_MASK  0xFFF
3620         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3621          *  element first, then find the bits it belongs to
3622          */
3623         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3624                   sizeof(uint32_t));
3625         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3626
3627         if (on)
3628                 vsi->vfta[vid_idx] |= vid_bit;
3629         else
3630                 vsi->vfta[vid_idx] &= ~vid_bit;
3631 }
3632
3633 /**
3634  * Find all vlan options for specific mac addr,
3635  * return with actual vlan found.
3636  */
3637 static inline int
3638 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3639                            struct i40e_macvlan_filter *mv_f,
3640                            int num, struct ether_addr *addr)
3641 {
3642         int i;
3643         uint32_t j, k;
3644
3645         /**
3646          * Not to use i40e_find_vlan_filter to decrease the loop time,
3647          * although the code looks complex.
3648           */
3649         if (num < vsi->vlan_num)
3650                 return I40E_ERR_PARAM;
3651
3652         i = 0;
3653         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3654                 if (vsi->vfta[j]) {
3655                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3656                                 if (vsi->vfta[j] & (1 << k)) {
3657                                         if (i > num - 1) {
3658                                                 PMD_DRV_LOG(ERR, "vlan number "
3659                                                             "not match");
3660                                                 return I40E_ERR_PARAM;
3661                                         }
3662                                         (void)rte_memcpy(&mv_f[i].macaddr,
3663                                                         addr, ETH_ADDR_LEN);
3664                                         mv_f[i].vlan_id =
3665                                                 j * I40E_UINT32_BIT_SIZE + k;
3666                                         i++;
3667                                 }
3668                         }
3669                 }
3670         }
3671         return I40E_SUCCESS;
3672 }
3673
3674 static inline int
3675 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3676                            struct i40e_macvlan_filter *mv_f,
3677                            int num,
3678                            uint16_t vlan)
3679 {
3680         int i = 0;
3681         struct i40e_mac_filter *f;
3682
3683         if (num < vsi->mac_num)
3684                 return I40E_ERR_PARAM;
3685
3686         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3687                 if (i > num - 1) {
3688                         PMD_DRV_LOG(ERR, "buffer number not match");
3689                         return I40E_ERR_PARAM;
3690                 }
3691                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3692                 mv_f[i].vlan_id = vlan;
3693                 i++;
3694         }
3695
3696         return I40E_SUCCESS;
3697 }
3698
3699 static int
3700 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3701 {
3702         int i, num;
3703         struct i40e_mac_filter *f;
3704         struct i40e_macvlan_filter *mv_f;
3705         int ret = I40E_SUCCESS;
3706
3707         if (vsi == NULL || vsi->mac_num == 0)
3708                 return I40E_ERR_PARAM;
3709
3710         /* Case that no vlan is set */
3711         if (vsi->vlan_num == 0)
3712                 num = vsi->mac_num;
3713         else
3714                 num = vsi->mac_num * vsi->vlan_num;
3715
3716         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3717         if (mv_f == NULL) {
3718                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3719                 return I40E_ERR_NO_MEMORY;
3720         }
3721
3722         i = 0;
3723         if (vsi->vlan_num == 0) {
3724                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3725                         (void)rte_memcpy(&mv_f[i].macaddr,
3726                                 &f->macaddr, ETH_ADDR_LEN);
3727                         mv_f[i].vlan_id = 0;
3728                         i++;
3729                 }
3730         } else {
3731                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3732                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3733                                         vsi->vlan_num, &f->macaddr);
3734                         if (ret != I40E_SUCCESS)
3735                                 goto DONE;
3736                         i += vsi->vlan_num;
3737                 }
3738         }
3739
3740         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3741 DONE:
3742         rte_free(mv_f);
3743
3744         return ret;
3745 }
3746
3747 int
3748 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3749 {
3750         struct i40e_macvlan_filter *mv_f;
3751         int mac_num;
3752         int ret = I40E_SUCCESS;
3753
3754         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3755                 return I40E_ERR_PARAM;
3756
3757         /* If it's already set, just return */
3758         if (i40e_find_vlan_filter(vsi,vlan))
3759                 return I40E_SUCCESS;
3760
3761         mac_num = vsi->mac_num;
3762
3763         if (mac_num == 0) {
3764                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3765                 return I40E_ERR_PARAM;
3766         }
3767
3768         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3769
3770         if (mv_f == NULL) {
3771                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3772                 return I40E_ERR_NO_MEMORY;
3773         }
3774
3775         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3776
3777         if (ret != I40E_SUCCESS)
3778                 goto DONE;
3779
3780         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3781
3782         if (ret != I40E_SUCCESS)
3783                 goto DONE;
3784
3785         i40e_set_vlan_filter(vsi, vlan, 1);
3786
3787         vsi->vlan_num++;
3788         ret = I40E_SUCCESS;
3789 DONE:
3790         rte_free(mv_f);
3791         return ret;
3792 }
3793
3794 int
3795 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3796 {
3797         struct i40e_macvlan_filter *mv_f;
3798         int mac_num;
3799         int ret = I40E_SUCCESS;
3800
3801         /**
3802          * Vlan 0 is the generic filter for untagged packets
3803          * and can't be removed.
3804          */
3805         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3806                 return I40E_ERR_PARAM;
3807
3808         /* If can't find it, just return */
3809         if (!i40e_find_vlan_filter(vsi, vlan))
3810                 return I40E_ERR_PARAM;
3811
3812         mac_num = vsi->mac_num;
3813
3814         if (mac_num == 0) {
3815                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3816                 return I40E_ERR_PARAM;
3817         }
3818
3819         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3820
3821         if (mv_f == NULL) {
3822                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3823                 return I40E_ERR_NO_MEMORY;
3824         }
3825
3826         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3827
3828         if (ret != I40E_SUCCESS)
3829                 goto DONE;
3830
3831         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3832
3833         if (ret != I40E_SUCCESS)
3834                 goto DONE;
3835
3836         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3837         if (vsi->vlan_num == 1) {
3838                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3839                 if (ret != I40E_SUCCESS)
3840                         goto DONE;
3841
3842                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3843                 if (ret != I40E_SUCCESS)
3844                         goto DONE;
3845         }
3846
3847         i40e_set_vlan_filter(vsi, vlan, 0);
3848
3849         vsi->vlan_num--;
3850         ret = I40E_SUCCESS;
3851 DONE:
3852         rte_free(mv_f);
3853         return ret;
3854 }
3855
3856 int
3857 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3858 {
3859         struct i40e_mac_filter *f;
3860         struct i40e_macvlan_filter *mv_f;
3861         int vlan_num;
3862         int ret = I40E_SUCCESS;
3863
3864         /* If it's add and we've config it, return */
3865         f = i40e_find_mac_filter(vsi, addr);
3866         if (f != NULL)
3867                 return I40E_SUCCESS;
3868
3869         /**
3870          * If vlan_num is 0, that's the first time to add mac,
3871          * set mask for vlan_id 0.
3872          */
3873         if (vsi->vlan_num == 0) {
3874                 i40e_set_vlan_filter(vsi, 0, 1);
3875                 vsi->vlan_num = 1;
3876         }
3877
3878         vlan_num = vsi->vlan_num;
3879
3880         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3881         if (mv_f == NULL) {
3882                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3883                 return I40E_ERR_NO_MEMORY;
3884         }
3885
3886         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3887         if (ret != I40E_SUCCESS)
3888                 goto DONE;
3889
3890         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3891         if (ret != I40E_SUCCESS)
3892                 goto DONE;
3893
3894         /* Add the mac addr into mac list */
3895         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3896         if (f == NULL) {
3897                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3898                 ret = I40E_ERR_NO_MEMORY;
3899                 goto DONE;
3900         }
3901         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3902         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3903         vsi->mac_num++;
3904
3905         ret = I40E_SUCCESS;
3906 DONE:
3907         rte_free(mv_f);
3908
3909         return ret;
3910 }
3911
3912 int
3913 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3914 {
3915         struct i40e_mac_filter *f;
3916         struct i40e_macvlan_filter *mv_f;
3917         int vlan_num;
3918         int ret = I40E_SUCCESS;
3919
3920         /* Can't find it, return an error */
3921         f = i40e_find_mac_filter(vsi, addr);
3922         if (f == NULL)
3923                 return I40E_ERR_PARAM;
3924
3925         vlan_num = vsi->vlan_num;
3926         if (vlan_num == 0) {
3927                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3928                 return I40E_ERR_PARAM;
3929         }
3930         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3931         if (mv_f == NULL) {
3932                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3933                 return I40E_ERR_NO_MEMORY;
3934         }
3935
3936         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3937         if (ret != I40E_SUCCESS)
3938                 goto DONE;
3939
3940         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3941         if (ret != I40E_SUCCESS)
3942                 goto DONE;
3943
3944         /* Remove the mac addr into mac list */
3945         TAILQ_REMOVE(&vsi->mac_list, f, next);
3946         rte_free(f);
3947         vsi->mac_num--;
3948
3949         ret = I40E_SUCCESS;
3950 DONE:
3951         rte_free(mv_f);
3952         return ret;
3953 }
3954
3955 /* Configure hash enable flags for RSS */
3956 static uint64_t
3957 i40e_config_hena(uint64_t flags)
3958 {
3959         uint64_t hena = 0;
3960
3961         if (!flags)
3962                 return hena;
3963
3964         if (flags & ETH_RSS_NONF_IPV4_UDP)
3965                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3966         if (flags & ETH_RSS_NONF_IPV4_TCP)
3967                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3968         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3969                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3970         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3971                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3972         if (flags & ETH_RSS_FRAG_IPV4)
3973                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3974         if (flags & ETH_RSS_NONF_IPV6_UDP)
3975                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3976         if (flags & ETH_RSS_NONF_IPV6_TCP)
3977                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3978         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3979                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3980         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3981                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3982         if (flags & ETH_RSS_FRAG_IPV6)
3983                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3984         if (flags & ETH_RSS_L2_PAYLOAD)
3985                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3986
3987         return hena;
3988 }
3989
3990 /* Parse the hash enable flags */
3991 static uint64_t
3992 i40e_parse_hena(uint64_t flags)
3993 {
3994         uint64_t rss_hf = 0;
3995
3996         if (!flags)
3997                 return rss_hf;
3998
3999         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4000                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4001         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4002                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4003         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4004                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4005         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4006                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4007         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4008                 rss_hf |= ETH_RSS_FRAG_IPV4;
4009         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4010                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4011         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4012                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4013         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4014                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4015         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4016                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4017         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4018                 rss_hf |= ETH_RSS_FRAG_IPV6;
4019         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4020                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4021
4022         return rss_hf;
4023 }
4024
4025 /* Disable RSS */
4026 static void
4027 i40e_pf_disable_rss(struct i40e_pf *pf)
4028 {
4029         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4030         uint64_t hena;
4031
4032         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4033         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4034         hena &= ~I40E_RSS_HENA_ALL;
4035         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4036         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4037         I40E_WRITE_FLUSH(hw);
4038 }
4039
4040 static int
4041 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4042 {
4043         uint32_t *hash_key;
4044         uint8_t hash_key_len;
4045         uint64_t rss_hf;
4046         uint16_t i;
4047         uint64_t hena;
4048
4049         hash_key = (uint32_t *)(rss_conf->rss_key);
4050         hash_key_len = rss_conf->rss_key_len;
4051         if (hash_key != NULL && hash_key_len >=
4052                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4053                 /* Fill in RSS hash key */
4054                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4055                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4056         }
4057
4058         rss_hf = rss_conf->rss_hf;
4059         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4060         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4061         hena &= ~I40E_RSS_HENA_ALL;
4062         hena |= i40e_config_hena(rss_hf);
4063         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4064         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4065         I40E_WRITE_FLUSH(hw);
4066
4067         return 0;
4068 }
4069
4070 static int
4071 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4072                          struct rte_eth_rss_conf *rss_conf)
4073 {
4074         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4076         uint64_t hena;
4077
4078         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4079         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4080         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4081                 if (rss_hf != 0) /* Enable RSS */
4082                         return -EINVAL;
4083                 return 0; /* Nothing to do */
4084         }
4085         /* RSS enabled */
4086         if (rss_hf == 0) /* Disable RSS */
4087                 return -EINVAL;
4088
4089         return i40e_hw_rss_hash_set(hw, rss_conf);
4090 }
4091
4092 static int
4093 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4094                            struct rte_eth_rss_conf *rss_conf)
4095 {
4096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4098         uint64_t hena;
4099         uint16_t i;
4100
4101         if (hash_key != NULL) {
4102                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4103                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4104                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4105         }
4106         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4107         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4108         rss_conf->rss_hf = i40e_parse_hena(hena);
4109
4110         return 0;
4111 }
4112
4113 /* Configure RSS */
4114 static int
4115 i40e_pf_config_rss(struct i40e_pf *pf)
4116 {
4117         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4118         struct rte_eth_rss_conf rss_conf;
4119         uint32_t i, lut = 0;
4120         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4121
4122         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4123                 if (j == num)
4124                         j = 0;
4125                 lut = (lut << 8) | (j & ((0x1 <<
4126                         hw->func_caps.rss_table_entry_width) - 1));
4127                 if ((i & 3) == 3)
4128                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4129         }
4130
4131         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4132         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4133                 i40e_pf_disable_rss(pf);
4134                 return 0;
4135         }
4136         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4137                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4138                 /* Calculate the default hash key */
4139                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4140                         rss_key_default[i] = (uint32_t)rte_rand();
4141                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4142                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4143                                                         sizeof(uint32_t);
4144         }
4145
4146         return i40e_hw_rss_hash_set(hw, &rss_conf);
4147 }
4148
4149 static int
4150 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4151 {
4152         if (!pf->dev_data->sriov.active) {
4153                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4154                 case ETH_MQ_RX_RSS:
4155                         i40e_pf_config_rss(pf);
4156                         break;
4157                 default:
4158                         i40e_pf_disable_rss(pf);
4159                         break;
4160                 }
4161         }
4162
4163         return 0;
4164 }