lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 static int eth_i40e_dev_init(\
  97                         __attribute__((unused)) struct eth_driver *eth_drv,
  98                         struct rte_eth_dev *eth_dev);
  99 static int i40e_dev_configure(struct rte_eth_dev *dev);
 100 static int i40e_dev_start(struct rte_eth_dev *dev);
 101 static void i40e_dev_stop(struct rte_eth_dev *dev);
 102 static void i40e_dev_close(struct rte_eth_dev *dev);
 103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 110                                struct rte_eth_stats *stats);
 111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 113                                             uint16_t queue_id,
 114                                             uint8_t stat_idx,
 115                                             uint8_t is_rx);
 116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_dev_info *dev_info);
 118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 119                                 uint16_t vlan_id,
 120                                 int on);
 121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 124                                       uint16_t queue,
 125                                       int on);
 126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 130                               struct rte_eth_fc_conf *fc_conf);
 131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 132                                        struct rte_eth_pfc_conf *pfc_conf);
 133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 134                           struct ether_addr *mac_addr,
 135                           uint32_t index,
 136                           uint32_t pool);
 137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 139                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 140                                     uint16_t reta_size);
 141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 142                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 143                                    uint16_t reta_size);
 144
 145 static int i40e_get_cap(struct i40e_hw *hw);
 146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 147 static int i40e_pf_setup(struct i40e_pf *pf);
 148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 151                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 152 static void i40e_stat_update_48(struct i40e_hw *hw,
 153                                uint32_t hireg,
 154                                uint32_t loreg,
 155                                bool offset_loaded,
 156                                uint64_t *offset,
 157                                uint64_t *stat);
 158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 159 static void i40e_dev_interrupt_handler(
 160                 __rte_unused struct rte_intr_handle *handle, void *param);
 161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 162                                 uint32_t base, uint32_t num);
 163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 165                         uint32_t base);
 166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 167                         uint16_t num);
 168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 169 static int i40e_veb_release(struct i40e_veb *veb);
 170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 171                                                 struct i40e_vsi *vsi);
 172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 175                                              struct i40e_macvlan_filter *mv_f,
 176                                              int num,
 177                                              struct ether_addr *addr);
 178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 179                                              struct i40e_macvlan_filter *mv_f,
 180                                              int num,
 181                                              uint16_t vlan);
 182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 184                                     struct rte_eth_rss_conf *rss_conf);
 185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 186                                       struct rte_eth_rss_conf *rss_conf);
 187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 188                                 struct rte_eth_udp_tunnel *udp_tunnel);
 189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 190                                 struct rte_eth_udp_tunnel *udp_tunnel);
 191 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 192                         struct rte_eth_ethertype_filter *filter,
 193                         bool add);
 194 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 195                                 enum rte_filter_op filter_op,
 196                                 void *arg);
 197 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 198                                 enum rte_filter_type filter_type,
 199                                 enum rte_filter_op filter_op,
 200                                 void *arg);
 201 static void i40e_configure_registers(struct i40e_hw *hw);
 202
 203 static struct rte_pci_id pci_id_i40e_map[] = {
 204 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 205 #include "rte_pci_dev_ids.h"
 206 { .vendor_id = 0, /* sentinel */ },
 207 };
 208
 209 static struct eth_dev_ops i40e_eth_dev_ops = {
 210         .dev_configure                = i40e_dev_configure,
 211         .dev_start                    = i40e_dev_start,
 212         .dev_stop                     = i40e_dev_stop,
 213         .dev_close                    = i40e_dev_close,
 214         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 215         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 216         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 217         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 218         .dev_set_link_up              = i40e_dev_set_link_up,
 219         .dev_set_link_down            = i40e_dev_set_link_down,
 220         .link_update                  = i40e_dev_link_update,
 221         .stats_get                    = i40e_dev_stats_get,
 222         .stats_reset                  = i40e_dev_stats_reset,
 223         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 224         .dev_infos_get                = i40e_dev_info_get,
 225         .vlan_filter_set              = i40e_vlan_filter_set,
 226         .vlan_tpid_set                = i40e_vlan_tpid_set,
 227         .vlan_offload_set             = i40e_vlan_offload_set,
 228         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 229         .vlan_pvid_set                = i40e_vlan_pvid_set,
 230         .rx_queue_start               = i40e_dev_rx_queue_start,
 231         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 232         .tx_queue_start               = i40e_dev_tx_queue_start,
 233         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 234         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 235         .rx_queue_release             = i40e_dev_rx_queue_release,
 236         .rx_queue_count               = i40e_dev_rx_queue_count,
 237         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 238         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 239         .tx_queue_release             = i40e_dev_tx_queue_release,
 240         .dev_led_on                   = i40e_dev_led_on,
 241         .dev_led_off                  = i40e_dev_led_off,
 242         .flow_ctrl_set                = i40e_flow_ctrl_set,
 243         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 244         .mac_addr_add                 = i40e_macaddr_add,
 245         .mac_addr_remove              = i40e_macaddr_remove,
 246         .reta_update                  = i40e_dev_rss_reta_update,
 247         .reta_query                   = i40e_dev_rss_reta_query,
 248         .rss_hash_update              = i40e_dev_rss_hash_update,
 249         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 250         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 251         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 252         .filter_ctrl                  = i40e_dev_filter_ctrl,
 253 };
 254
 255 static struct eth_driver rte_i40e_pmd = {
 256         {
 257                 .name = "rte_i40e_pmd",
 258                 .id_table = pci_id_i40e_map,
 259                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 260         },
 261         .eth_dev_init = eth_i40e_dev_init,
 262         .dev_private_size = sizeof(struct i40e_adapter),
 263 };
 264
 265 static inline int
 266 i40e_align_floor(int n)
 267 {
 268         if (n == 0)
 269                 return 0;
 270         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 271 }
 272
 273 static inline int
 274 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 275                                      struct rte_eth_link *link)
 276 {
 277         struct rte_eth_link *dst = link;
 278         struct rte_eth_link *src = &(dev->data->dev_link);
 279
 280         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 281                                         *(uint64_t *)src) == 0)
 282                 return -1;
 283
 284         return 0;
 285 }
 286
 287 static inline int
 288 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 289                                       struct rte_eth_link *link)
 290 {
 291         struct rte_eth_link *dst = &(dev->data->dev_link);
 292         struct rte_eth_link *src = link;
 293
 294         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 295                                         *(uint64_t *)src) == 0)
 296                 return -1;
 297
 298         return 0;
 299 }
 300
 301 /*
 302  * Driver initialization routine.
 303  * Invoked once at EAL init time.
 304  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 305  */
 306 static int
 307 rte_i40e_pmd_init(const char *name __rte_unused,
 308                   const char *params __rte_unused)
 309 {
 310         PMD_INIT_FUNC_TRACE();
 311         rte_eth_driver_register(&rte_i40e_pmd);
 312
 313         return 0;
 314 }
 315
 316 static struct rte_driver rte_i40e_driver = {
 317         .type = PMD_PDEV,
 318         .init = rte_i40e_pmd_init,
 319 };
 320
 321 PMD_REGISTER_DRIVER(rte_i40e_driver);
 322
 323 /*
 324  * Initialize registers for flexible payload, which should be set by NVM.
 325  * This should be removed from code once it is fixed in NVM.
 326  */
 327 #ifndef I40E_GLQF_ORT
 328 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 329 #endif
 330 #ifndef I40E_GLQF_PIT
 331 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 332 #endif
 333
 334 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 335 {
 336         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 337         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 338         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 339         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 340         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 341         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 342         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 343         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 344         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 345         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 346
 347         /* GLQF_PIT Registers */
 348         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 349         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 350 }
 351
 352 static int
 353 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 354                   struct rte_eth_dev *dev)
 355 {
 356         struct rte_pci_device *pci_dev;
 357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 358         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 359         struct i40e_vsi *vsi;
 360         int ret;
 361         uint32_t len;
 362         uint8_t aq_fail = 0;
 363
 364         PMD_INIT_FUNC_TRACE();
 365
 366         dev->dev_ops = &i40e_eth_dev_ops;
 367         dev->rx_pkt_burst = i40e_recv_pkts;
 368         dev->tx_pkt_burst = i40e_xmit_pkts;
 369
 370         /* for secondary processes, we don't initialise any further as primary
 371          * has already done this work. Only check we don't need a different
 372          * RX function */
 373         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 374                 if (dev->data->scattered_rx)
 375                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 376                 return 0;
 377         }
 378         pci_dev = dev->pci_dev;
 379         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 380         pf->adapter->eth_dev = dev;
 381         pf->dev_data = dev->data;
 382
 383         hw->back = I40E_PF_TO_ADAPTER(pf);
 384         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 385         if (!hw->hw_addr) {
 386                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 387                              "as address is NULL");
 388                 return -ENODEV;
 389         }
 390
 391         hw->vendor_id = pci_dev->id.vendor_id;
 392         hw->device_id = pci_dev->id.device_id;
 393         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 394         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 395         hw->bus.device = pci_dev->addr.devid;
 396         hw->bus.func = pci_dev->addr.function;
 397
 398         /* Make sure all is clean before doing PF reset */
 399         i40e_clear_hw(hw);
 400
 401         /* Reset here to make sure all is clean for each PF */
 402         ret = i40e_pf_reset(hw);
 403         if (ret) {
 404                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 405                 return ret;
 406         }
 407
 408         /* Initialize the shared code (base driver) */
 409         ret = i40e_init_shared_code(hw);
 410         if (ret) {
 411                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 412                 return ret;
 413         }
 414
 415         /*
 416          * To work around the NVM issue,initialize registers
 417          * for flexible payload by software.
 418          * It should be removed once issues are fixed in NVM.
 419          */
 420         i40e_flex_payload_reg_init(hw);
 421
 422         /* Initialize the parameters for adminq */
 423         i40e_init_adminq_parameter(hw);
 424         ret = i40e_init_adminq(hw);
 425         if (ret != I40E_SUCCESS) {
 426                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 427                 return -EIO;
 428         }
 429         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 430                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 431                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 432                      ((hw->nvm.version >> 12) & 0xf),
 433                      ((hw->nvm.version >> 4) & 0xff),
 434                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 435
 436         /* Disable LLDP */
 437         ret = i40e_aq_stop_lldp(hw, true, NULL);
 438         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 439                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 440
 441         /* Clear PXE mode */
 442         i40e_clear_pxe_mode(hw);
 443
 444         /*
 445          * On X710, performance number is far from the expectation on recent
 446          * firmware versions. The fix for this issue may not be integrated in
 447          * the following firmware version. So the workaround in software driver
 448          * is needed. It needs to modify the initial values of 3 internal only
 449          * registers. Note that the workaround can be removed when it is fixed
 450          * in firmware in the future.
 451          */
 452         i40e_configure_registers(hw);
 453
 454         /* Get hw capabilities */
 455         ret = i40e_get_cap(hw);
 456         if (ret != I40E_SUCCESS) {
 457                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 458                 goto err_get_capabilities;
 459         }
 460
 461         /* Initialize parameters for PF */
 462         ret = i40e_pf_parameter_init(dev);
 463         if (ret != 0) {
 464                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 465                 goto err_parameter_init;
 466         }
 467
 468         /* Initialize the queue management */
 469         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 470         if (ret < 0) {
 471                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 472                 goto err_qp_pool_init;
 473         }
 474         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 475                                 hw->func_caps.num_msix_vectors - 1);
 476         if (ret < 0) {
 477                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 478                 goto err_msix_pool_init;
 479         }
 480
 481         /* Initialize lan hmc */
 482         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 483                                 hw->func_caps.num_rx_qp, 0, 0);
 484         if (ret != I40E_SUCCESS) {
 485                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 486                 goto err_init_lan_hmc;
 487         }
 488
 489         /* Configure lan hmc */
 490         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 491         if (ret != I40E_SUCCESS) {
 492                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 493                 goto err_configure_lan_hmc;
 494         }
 495
 496         /* Get and check the mac address */
 497         i40e_get_mac_addr(hw, hw->mac.addr);
 498         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 499                 PMD_INIT_LOG(ERR, "mac address is not valid");
 500                 ret = -EIO;
 501                 goto err_get_mac_addr;
 502         }
 503         /* Copy the permanent MAC address */
 504         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 505                         (struct ether_addr *) hw->mac.perm_addr);
 506
 507         /* Disable flow control */
 508         hw->fc.requested_mode = I40E_FC_NONE;
 509         i40e_set_fc(hw, &aq_fail, TRUE);
 510
 511         /* PF setup, which includes VSI setup */
 512         ret = i40e_pf_setup(pf);
 513         if (ret) {
 514                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 515                 goto err_setup_pf_switch;
 516         }
 517
 518         vsi = pf->main_vsi;
 519
 520         /* Disable double vlan by default */
 521         i40e_vsi_config_double_vlan(vsi, FALSE);
 522
 523         if (!vsi->max_macaddrs)
 524                 len = ETHER_ADDR_LEN;
 525         else
 526                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 527
 528         /* Should be after VSI initialized */
 529         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 530         if (!dev->data->mac_addrs) {
 531                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 532                                         "for storing mac address");
 533                 goto err_mac_alloc;
 534         }
 535         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 536                                         &dev->data->mac_addrs[0]);
 537
 538         /* initialize pf host driver to setup SRIOV resource if applicable */
 539         i40e_pf_host_init(dev);
 540
 541         /* register callback func to eal lib */
 542         rte_intr_callback_register(&(pci_dev->intr_handle),
 543                 i40e_dev_interrupt_handler, (void *)dev);
 544
 545         /* configure and enable device interrupt */
 546         i40e_pf_config_irq0(hw);
 547         i40e_pf_enable_irq0(hw);
 548
 549         /* enable uio intr after callback register */
 550         rte_intr_enable(&(pci_dev->intr_handle));
 551
 552         return 0;
 553
 554 err_mac_alloc:
 555         i40e_vsi_release(pf->main_vsi);
 556 err_setup_pf_switch:
 557 err_get_mac_addr:
 558 err_configure_lan_hmc:
 559         (void)i40e_shutdown_lan_hmc(hw);
 560 err_init_lan_hmc:
 561         i40e_res_pool_destroy(&pf->msix_pool);
 562 err_msix_pool_init:
 563         i40e_res_pool_destroy(&pf->qp_pool);
 564 err_qp_pool_init:
 565 err_parameter_init:
 566 err_get_capabilities:
 567         (void)i40e_shutdown_adminq(hw);
 568
 569         return ret;
 570 }
 571
 572 static int
 573 i40e_dev_configure(struct rte_eth_dev *dev)
 574 {
 575         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 576         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 577         int ret;
 578
 579         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 580                 ret = i40e_fdir_setup(pf);
 581                 if (ret != I40E_SUCCESS) {
 582                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 583                         return -ENOTSUP;
 584                 }
 585                 ret = i40e_fdir_configure(dev);
 586                 if (ret < 0) {
 587                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 588                         goto err;
 589                 }
 590         } else
 591                 i40e_fdir_teardown(pf);
 592
 593         ret = i40e_dev_init_vlan(dev);
 594         if (ret < 0)
 595                 goto err;
 596
 597         /* VMDQ setup.
 598          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 599          *  RSS setting have different requirements.
 600          *  General PMD driver call sequence are NIC init, configure,
 601          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 602          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 603          *  applicable. So, VMDQ setting has to be done before
 604          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 605          *  For RSS setting, it will try to calculate actual configured RX queue
 606          *  number, which will be available after rx_queue_setup(). dev_start()
 607          *  function is good to place RSS setup.
 608          */
 609         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 610                 ret = i40e_vmdq_setup(dev);
 611                 if (ret)
 612                         goto err;
 613         }
 614         return 0;
 615 err:
 616         i40e_fdir_teardown(pf);
 617         return ret;
 618 }
 619
 620 void
 621 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 622 {
 623         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 624         uint16_t msix_vect = vsi->msix_intr;
 625         uint16_t i;
 626
 627         for (i = 0; i < vsi->nb_qps; i++) {
 628                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 629                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 630                 rte_wmb();
 631         }
 632
 633         if (vsi->type != I40E_VSI_SRIOV) {
 634                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 635                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 636                                 msix_vect - 1), 0);
 637         } else {
 638                 uint32_t reg;
 639                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 640                         vsi->user_param + (msix_vect - 1);
 641
 642                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 643         }
 644         I40E_WRITE_FLUSH(hw);
 645 }
 646
 647 static inline uint16_t
 648 i40e_calc_itr_interval(int16_t interval)
 649 {
 650         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 651                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 652
 653         /* Convert to hardware count, as writing each 1 represents 2 us */
 654         return (interval/2);
 655 }
 656
 657 void
 658 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 659 {
 660         uint32_t val;
 661         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 662         uint16_t msix_vect = vsi->msix_intr;
 663         int i;
 664
 665         for (i = 0; i < vsi->nb_qps; i++)
 666                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 667
 668         /* Bind all RX queues to allocated MSIX interrupt */
 669         for (i = 0; i < vsi->nb_qps; i++) {
 670                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 671                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 672                         ((vsi->base_queue + i + 1) <<
 673                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 674                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 675                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 676
 677                 if (i == vsi->nb_qps - 1)
 678                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 679                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 680         }
 681
 682         /* Write first RX queue to Link list register as the head element */
 683         if (vsi->type != I40E_VSI_SRIOV) {
 684                 uint16_t interval =
 685                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 686
 687                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 688                                                 (vsi->base_queue <<
 689                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 690                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 691
 692                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 693                                                 msix_vect - 1), interval);
 694
 695 #ifndef I40E_GLINT_CTL
 696 #define I40E_GLINT_CTL                     0x0003F800
 697 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 698 #endif
 699                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 700                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 701                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 702         } else {
 703                 uint32_t reg;
 704
 705                 /* num_msix_vectors_vf needs to minus irq0 */
 706                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 707                         vsi->user_param + (msix_vect - 1);
 708
 709                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 710                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 711                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 712         }
 713
 714         I40E_WRITE_FLUSH(hw);
 715 }
 716
 717 static void
 718 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 719 {
 720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 721         uint16_t interval = i40e_calc_itr_interval(\
 722                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 723
 724         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 725                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 726                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 727                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 728                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 729 }
 730
 731 static void
 732 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 733 {
 734         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 735
 736         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 737 }
 738
 739 static inline uint8_t
 740 i40e_parse_link_speed(uint16_t eth_link_speed)
 741 {
 742         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 743
 744         switch (eth_link_speed) {
 745         case ETH_LINK_SPEED_40G:
 746                 link_speed = I40E_LINK_SPEED_40GB;
 747                 break;
 748         case ETH_LINK_SPEED_20G:
 749                 link_speed = I40E_LINK_SPEED_20GB;
 750                 break;
 751         case ETH_LINK_SPEED_10G:
 752                 link_speed = I40E_LINK_SPEED_10GB;
 753                 break;
 754         case ETH_LINK_SPEED_1000:
 755                 link_speed = I40E_LINK_SPEED_1GB;
 756                 break;
 757         case ETH_LINK_SPEED_100:
 758                 link_speed = I40E_LINK_SPEED_100MB;
 759                 break;
 760         }
 761
 762         return link_speed;
 763 }
 764
 765 static int
 766 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 767 {
 768         enum i40e_status_code status;
 769         struct i40e_aq_get_phy_abilities_resp phy_ab;
 770         struct i40e_aq_set_phy_config phy_conf;
 771         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 772                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 773                         I40E_AQ_PHY_FLAG_LOW_POWER;
 774         const uint8_t advt = I40E_LINK_SPEED_40GB |
 775                         I40E_LINK_SPEED_10GB |
 776                         I40E_LINK_SPEED_1GB |
 777                         I40E_LINK_SPEED_100MB;
 778         int ret = -ENOTSUP;
 779
 780         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 781                                               NULL);
 782         if (status)
 783                 return ret;
 784
 785         memset(&phy_conf, 0, sizeof(phy_conf));
 786
 787         /* bits 0-2 use the values from get_phy_abilities_resp */
 788         abilities &= ~mask;
 789         abilities |= phy_ab.abilities & mask;
 790
 791         /* update ablities and speed */
 792         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 793                 phy_conf.link_speed = advt;
 794         else
 795                 phy_conf.link_speed = force_speed;
 796
 797         phy_conf.abilities = abilities;
 798
 799         /* use get_phy_abilities_resp value for the rest */
 800         phy_conf.phy_type = phy_ab.phy_type;
 801         phy_conf.eee_capability = phy_ab.eee_capability;
 802         phy_conf.eeer = phy_ab.eeer_val;
 803         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 804
 805         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 806                     phy_ab.abilities, phy_ab.link_speed);
 807         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 808                     phy_conf.abilities, phy_conf.link_speed);
 809
 810         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 811         if (status)
 812                 return ret;
 813
 814         return I40E_SUCCESS;
 815 }
 816
 817 static int
 818 i40e_apply_link_speed(struct rte_eth_dev *dev)
 819 {
 820         uint8_t speed;
 821         uint8_t abilities = 0;
 822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 823         struct rte_eth_conf *conf = &dev->data->dev_conf;
 824
 825         speed = i40e_parse_link_speed(conf->link_speed);
 826         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 827         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 828                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 829         else
 830                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 831
 832         return i40e_phy_conf_link(hw, abilities, speed);
 833 }
 834
 835 static int
 836 i40e_dev_start(struct rte_eth_dev *dev)
 837 {
 838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 840         struct i40e_vsi *main_vsi = pf->main_vsi;
 841         int ret, i;
 842
 843         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 844                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 845                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 846                              dev->data->dev_conf.link_duplex,
 847                              dev->data->port_id);
 848                 return -EINVAL;
 849         }
 850
 851         /* Initialize VSI */
 852         ret = i40e_dev_rxtx_init(pf);
 853         if (ret != I40E_SUCCESS) {
 854                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 855                 goto err_up;
 856         }
 857
 858         /* Map queues with MSIX interrupt */
 859         i40e_vsi_queues_bind_intr(main_vsi);
 860         i40e_vsi_enable_queues_intr(main_vsi);
 861
 862         /* Map VMDQ VSI queues with MSIX interrupt */
 863         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 864                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 865                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 866         }
 867
 868         /* enable FDIR MSIX interrupt */
 869         if (pf->fdir.fdir_vsi) {
 870                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 871                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 872         }
 873
 874         /* Enable all queues which have been configured */
 875         ret = i40e_dev_switch_queues(pf, TRUE);
 876         if (ret != I40E_SUCCESS) {
 877                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 878                 goto err_up;
 879         }
 880
 881         /* Enable receiving broadcast packets */
 882         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 883         if (ret != I40E_SUCCESS)
 884                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 885
 886         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 887                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 888                                                 true, NULL);
 889                 if (ret != I40E_SUCCESS)
 890                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 891         }
 892
 893         /* Apply link configure */
 894         ret = i40e_apply_link_speed(dev);
 895         if (I40E_SUCCESS != ret) {
 896                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 897                 goto err_up;
 898         }
 899
 900         return I40E_SUCCESS;
 901
 902 err_up:
 903         i40e_dev_switch_queues(pf, FALSE);
 904         i40e_dev_clear_queues(dev);
 905
 906         return ret;
 907 }
 908
 909 static void
 910 i40e_dev_stop(struct rte_eth_dev *dev)
 911 {
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_vsi *main_vsi = pf->main_vsi;
 914         int i;
 915
 916         /* Disable all queues */
 917         i40e_dev_switch_queues(pf, FALSE);
 918
 919         /* un-map queues with interrupt registers */
 920         i40e_vsi_disable_queues_intr(main_vsi);
 921         i40e_vsi_queues_unbind_intr(main_vsi);
 922
 923         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 924                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 925                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 926         }
 927
 928         if (pf->fdir.fdir_vsi) {
 929                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 930                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 931         }
 932         /* Clear all queues and release memory */
 933         i40e_dev_clear_queues(dev);
 934
 935         /* Set link down */
 936         i40e_dev_set_link_down(dev);
 937
 938 }
 939
 940 static void
 941 i40e_dev_close(struct rte_eth_dev *dev)
 942 {
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 945         uint32_t reg;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         i40e_dev_stop(dev);
 950
 951         /* Disable interrupt */
 952         i40e_pf_disable_irq0(hw);
 953         rte_intr_disable(&(dev->pci_dev->intr_handle));
 954
 955         /* shutdown and destroy the HMC */
 956         i40e_shutdown_lan_hmc(hw);
 957
 958         /* release all the existing VSIs and VEBs */
 959         i40e_fdir_teardown(pf);
 960         i40e_vsi_release(pf->main_vsi);
 961
 962         /* shutdown the adminq */
 963         i40e_aq_queue_shutdown(hw, true);
 964         i40e_shutdown_adminq(hw);
 965
 966         i40e_res_pool_destroy(&pf->qp_pool);
 967         i40e_res_pool_destroy(&pf->msix_pool);
 968
 969         /* force a PF reset to clean anything leftover */
 970         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 971         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 972                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 973         I40E_WRITE_FLUSH(hw);
 974 }
 975
 976 static void
 977 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 978 {
 979         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 980         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         struct i40e_vsi *vsi = pf->main_vsi;
 982         int status;
 983
 984         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 985                                                         true, NULL);
 986         if (status != I40E_SUCCESS)
 987                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 988
 989         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 990                                                         TRUE, NULL);
 991         if (status != I40E_SUCCESS)
 992                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 993
 994 }
 995
 996 static void
 997 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 998 {
 999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001         struct i40e_vsi *vsi = pf->main_vsi;
1002         int status;
1003
1004         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1005                                                         false, NULL);
1006         if (status != I40E_SUCCESS)
1007                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1008
1009         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1010                                                         false, NULL);
1011         if (status != I40E_SUCCESS)
1012                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1013 }
1014
1015 static void
1016 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1017 {
1018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         struct i40e_vsi *vsi = pf->main_vsi;
1021         int ret;
1022
1023         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1024         if (ret != I40E_SUCCESS)
1025                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1026 }
1027
1028 static void
1029 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1030 {
1031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1032         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033         struct i40e_vsi *vsi = pf->main_vsi;
1034         int ret;
1035
1036         if (dev->data->promiscuous == 1)
1037                 return; /* must remain in all_multicast mode */
1038
1039         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1040                                 vsi->seid, FALSE, NULL);
1041         if (ret != I40E_SUCCESS)
1042                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1043 }
1044
1045 /*
1046  * Set device link up.
1047  */
1048 static int
1049 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1050 {
1051         /* re-apply link speed setting */
1052         return i40e_apply_link_speed(dev);
1053 }
1054
1055 /*
1056  * Set device link down.
1057  */
1058 static int
1059 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1060 {
1061         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1062         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064
1065         return i40e_phy_conf_link(hw, abilities, speed);
1066 }
1067
1068 int
1069 i40e_dev_link_update(struct rte_eth_dev *dev,
1070                      __rte_unused int wait_to_complete)
1071 {
1072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1073         struct i40e_link_status link_status;
1074         struct rte_eth_link link, old;
1075         int status;
1076
1077         memset(&link, 0, sizeof(link));
1078         memset(&old, 0, sizeof(old));
1079         memset(&link_status, 0, sizeof(link_status));
1080         rte_i40e_dev_atomic_read_link_status(dev, &old);
1081
1082         /* Get link status information from hardware */
1083         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1084         if (status != I40E_SUCCESS) {
1085                 link.link_speed = ETH_LINK_SPEED_100;
1086                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1087                 PMD_DRV_LOG(ERR, "Failed to get link info");
1088                 goto out;
1089         }
1090
1091         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1092
1093         if (!link.link_status)
1094                 goto out;
1095
1096         /* i40e uses full duplex only */
1097         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1098
1099         /* Parse the link status */
1100         switch (link_status.link_speed) {
1101         case I40E_LINK_SPEED_100MB:
1102                 link.link_speed = ETH_LINK_SPEED_100;
1103                 break;
1104         case I40E_LINK_SPEED_1GB:
1105                 link.link_speed = ETH_LINK_SPEED_1000;
1106                 break;
1107         case I40E_LINK_SPEED_10GB:
1108                 link.link_speed = ETH_LINK_SPEED_10G;
1109                 break;
1110         case I40E_LINK_SPEED_20GB:
1111                 link.link_speed = ETH_LINK_SPEED_20G;
1112                 break;
1113         case I40E_LINK_SPEED_40GB:
1114                 link.link_speed = ETH_LINK_SPEED_40G;
1115                 break;
1116         default:
1117                 link.link_speed = ETH_LINK_SPEED_100;
1118                 break;
1119         }
1120
1121 out:
1122         rte_i40e_dev_atomic_write_link_status(dev, &link);
1123         if (link.link_status == old.link_status)
1124                 return -1;
1125
1126         return 0;
1127 }
1128
1129 /* Get all the statistics of a VSI */
1130 void
1131 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1132 {
1133         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1134         struct i40e_eth_stats *nes = &vsi->eth_stats;
1135         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1136         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1137
1138         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1139                             vsi->offset_loaded, &oes->rx_bytes,
1140                             &nes->rx_bytes);
1141         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1142                             vsi->offset_loaded, &oes->rx_unicast,
1143                             &nes->rx_unicast);
1144         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1145                             vsi->offset_loaded, &oes->rx_multicast,
1146                             &nes->rx_multicast);
1147         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1148                             vsi->offset_loaded, &oes->rx_broadcast,
1149                             &nes->rx_broadcast);
1150         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1151                             &oes->rx_discards, &nes->rx_discards);
1152         /* GLV_REPC not supported */
1153         /* GLV_RMPC not supported */
1154         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1155                             &oes->rx_unknown_protocol,
1156                             &nes->rx_unknown_protocol);
1157         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1158                             vsi->offset_loaded, &oes->tx_bytes,
1159                             &nes->tx_bytes);
1160         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1161                             vsi->offset_loaded, &oes->tx_unicast,
1162                             &nes->tx_unicast);
1163         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1164                             vsi->offset_loaded, &oes->tx_multicast,
1165                             &nes->tx_multicast);
1166         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1167                             vsi->offset_loaded,  &oes->tx_broadcast,
1168                             &nes->tx_broadcast);
1169         /* GLV_TDPC not supported */
1170         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1171                             &oes->tx_errors, &nes->tx_errors);
1172         vsi->offset_loaded = true;
1173
1174         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1175                     vsi->vsi_id);
1176         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1177         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1178         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1179         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1180         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1181         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1182                     nes->rx_unknown_protocol);
1183         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1184         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1185         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1186         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1187         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1188         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1189         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1190                     vsi->vsi_id);
1191 }
1192
1193 /* Get all statistics of a port */
1194 static void
1195 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1196 {
1197         uint32_t i;
1198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1201         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1202
1203         /* Get statistics of struct i40e_eth_stats */
1204         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1205                             I40E_GLPRT_GORCL(hw->port),
1206                             pf->offset_loaded, &os->eth.rx_bytes,
1207                             &ns->eth.rx_bytes);
1208         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1209                             I40E_GLPRT_UPRCL(hw->port),
1210                             pf->offset_loaded, &os->eth.rx_unicast,
1211                             &ns->eth.rx_unicast);
1212         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1213                             I40E_GLPRT_MPRCL(hw->port),
1214                             pf->offset_loaded, &os->eth.rx_multicast,
1215                             &ns->eth.rx_multicast);
1216         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1217                             I40E_GLPRT_BPRCL(hw->port),
1218                             pf->offset_loaded, &os->eth.rx_broadcast,
1219                             &ns->eth.rx_broadcast);
1220         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1221                             pf->offset_loaded, &os->eth.rx_discards,
1222                             &ns->eth.rx_discards);
1223         /* GLPRT_REPC not supported */
1224         /* GLPRT_RMPC not supported */
1225         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1226                             pf->offset_loaded,
1227                             &os->eth.rx_unknown_protocol,
1228                             &ns->eth.rx_unknown_protocol);
1229         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1230                             I40E_GLPRT_GOTCL(hw->port),
1231                             pf->offset_loaded, &os->eth.tx_bytes,
1232                             &ns->eth.tx_bytes);
1233         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1234                             I40E_GLPRT_UPTCL(hw->port),
1235                             pf->offset_loaded, &os->eth.tx_unicast,
1236                             &ns->eth.tx_unicast);
1237         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1238                             I40E_GLPRT_MPTCL(hw->port),
1239                             pf->offset_loaded, &os->eth.tx_multicast,
1240                             &ns->eth.tx_multicast);
1241         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1242                             I40E_GLPRT_BPTCL(hw->port),
1243                             pf->offset_loaded, &os->eth.tx_broadcast,
1244                             &ns->eth.tx_broadcast);
1245         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1246                             pf->offset_loaded, &os->eth.tx_discards,
1247                             &ns->eth.tx_discards);
1248         /* GLPRT_TEPC not supported */
1249
1250         /* additional port specific stats */
1251         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1252                             pf->offset_loaded, &os->tx_dropped_link_down,
1253                             &ns->tx_dropped_link_down);
1254         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1255                             pf->offset_loaded, &os->crc_errors,
1256                             &ns->crc_errors);
1257         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1258                             pf->offset_loaded, &os->illegal_bytes,
1259                             &ns->illegal_bytes);
1260         /* GLPRT_ERRBC not supported */
1261         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1262                             pf->offset_loaded, &os->mac_local_faults,
1263                             &ns->mac_local_faults);
1264         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1265                             pf->offset_loaded, &os->mac_remote_faults,
1266                             &ns->mac_remote_faults);
1267         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1268                             pf->offset_loaded, &os->rx_length_errors,
1269                             &ns->rx_length_errors);
1270         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1271                             pf->offset_loaded, &os->link_xon_rx,
1272                             &ns->link_xon_rx);
1273         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1274                             pf->offset_loaded, &os->link_xoff_rx,
1275                             &ns->link_xoff_rx);
1276         for (i = 0; i < 8; i++) {
1277                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1278                                     pf->offset_loaded,
1279                                     &os->priority_xon_rx[i],
1280                                     &ns->priority_xon_rx[i]);
1281                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1282                                     pf->offset_loaded,
1283                                     &os->priority_xoff_rx[i],
1284                                     &ns->priority_xoff_rx[i]);
1285         }
1286         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1287                             pf->offset_loaded, &os->link_xon_tx,
1288                             &ns->link_xon_tx);
1289         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1290                             pf->offset_loaded, &os->link_xoff_tx,
1291                             &ns->link_xoff_tx);
1292         for (i = 0; i < 8; i++) {
1293                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1294                                     pf->offset_loaded,
1295                                     &os->priority_xon_tx[i],
1296                                     &ns->priority_xon_tx[i]);
1297                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1298                                     pf->offset_loaded,
1299                                     &os->priority_xoff_tx[i],
1300                                     &ns->priority_xoff_tx[i]);
1301                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1302                                     pf->offset_loaded,
1303                                     &os->priority_xon_2_xoff[i],
1304                                     &ns->priority_xon_2_xoff[i]);
1305         }
1306         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1307                             I40E_GLPRT_PRC64L(hw->port),
1308                             pf->offset_loaded, &os->rx_size_64,
1309                             &ns->rx_size_64);
1310         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1311                             I40E_GLPRT_PRC127L(hw->port),
1312                             pf->offset_loaded, &os->rx_size_127,
1313                             &ns->rx_size_127);
1314         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1315                             I40E_GLPRT_PRC255L(hw->port),
1316                             pf->offset_loaded, &os->rx_size_255,
1317                             &ns->rx_size_255);
1318         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1319                             I40E_GLPRT_PRC511L(hw->port),
1320                             pf->offset_loaded, &os->rx_size_511,
1321                             &ns->rx_size_511);
1322         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1323                             I40E_GLPRT_PRC1023L(hw->port),
1324                             pf->offset_loaded, &os->rx_size_1023,
1325                             &ns->rx_size_1023);
1326         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1327                             I40E_GLPRT_PRC1522L(hw->port),
1328                             pf->offset_loaded, &os->rx_size_1522,
1329                             &ns->rx_size_1522);
1330         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1331                             I40E_GLPRT_PRC9522L(hw->port),
1332                             pf->offset_loaded, &os->rx_size_big,
1333                             &ns->rx_size_big);
1334         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1335                             pf->offset_loaded, &os->rx_undersize,
1336                             &ns->rx_undersize);
1337         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1338                             pf->offset_loaded, &os->rx_fragments,
1339                             &ns->rx_fragments);
1340         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1341                             pf->offset_loaded, &os->rx_oversize,
1342                             &ns->rx_oversize);
1343         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1344                             pf->offset_loaded, &os->rx_jabber,
1345                             &ns->rx_jabber);
1346         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1347                             I40E_GLPRT_PTC64L(hw->port),
1348                             pf->offset_loaded, &os->tx_size_64,
1349                             &ns->tx_size_64);
1350         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1351                             I40E_GLPRT_PTC127L(hw->port),
1352                             pf->offset_loaded, &os->tx_size_127,
1353                             &ns->tx_size_127);
1354         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1355                             I40E_GLPRT_PTC255L(hw->port),
1356                             pf->offset_loaded, &os->tx_size_255,
1357                             &ns->tx_size_255);
1358         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1359                             I40E_GLPRT_PTC511L(hw->port),
1360                             pf->offset_loaded, &os->tx_size_511,
1361                             &ns->tx_size_511);
1362         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1363                             I40E_GLPRT_PTC1023L(hw->port),
1364                             pf->offset_loaded, &os->tx_size_1023,
1365                             &ns->tx_size_1023);
1366         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1367                             I40E_GLPRT_PTC1522L(hw->port),
1368                             pf->offset_loaded, &os->tx_size_1522,
1369                             &ns->tx_size_1522);
1370         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1371                             I40E_GLPRT_PTC9522L(hw->port),
1372                             pf->offset_loaded, &os->tx_size_big,
1373                             &ns->tx_size_big);
1374         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1375                            pf->offset_loaded,
1376                            &os->fd_sb_match, &ns->fd_sb_match);
1377         /* GLPRT_MSPDC not supported */
1378         /* GLPRT_XEC not supported */
1379
1380         pf->offset_loaded = true;
1381
1382         if (pf->main_vsi)
1383                 i40e_update_vsi_stats(pf->main_vsi);
1384
1385         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1386                                                 ns->eth.rx_broadcast;
1387         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1388                                                 ns->eth.tx_broadcast;
1389         stats->ibytes   = ns->eth.rx_bytes;
1390         stats->obytes   = ns->eth.tx_bytes;
1391         stats->oerrors  = ns->eth.tx_errors;
1392         stats->imcasts  = ns->eth.rx_multicast;
1393         stats->fdirmatch = ns->fd_sb_match;
1394
1395         /* Rx Errors */
1396         stats->ibadcrc  = ns->crc_errors;
1397         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1398                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1399         stats->imissed  = ns->eth.rx_discards;
1400         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1401
1402         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1403         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1404         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1405         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1406         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1407         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1408         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1409                     ns->eth.rx_unknown_protocol);
1410         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1411         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1412         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1413         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1414         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1415         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1416
1417         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1418                     ns->tx_dropped_link_down);
1419         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1420         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1421                     ns->illegal_bytes);
1422         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1423         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1424                     ns->mac_local_faults);
1425         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1426                     ns->mac_remote_faults);
1427         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1428                     ns->rx_length_errors);
1429         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1430         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1431         for (i = 0; i < 8; i++) {
1432                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1433                                 i, ns->priority_xon_rx[i]);
1434                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1435                                 i, ns->priority_xoff_rx[i]);
1436         }
1437         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1438         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1439         for (i = 0; i < 8; i++) {
1440                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1441                                 i, ns->priority_xon_tx[i]);
1442                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1443                                 i, ns->priority_xoff_tx[i]);
1444                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1445                                 i, ns->priority_xon_2_xoff[i]);
1446         }
1447         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1448         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1449         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1450         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1451         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1452         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1453         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1454         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1455         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1456         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1457         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1458         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1459         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1460         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1461         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1462         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1463         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1464         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1465         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1466                         ns->mac_short_packet_dropped);
1467         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1468                     ns->checksum_error);
1469         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1470         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1471 }
1472
1473 /* Reset the statistics */
1474 static void
1475 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1476 {
1477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478
1479         /* It results in reloading the start point of each counter */
1480         pf->offset_loaded = false;
1481 }
1482
1483 static int
1484 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1485                                  __rte_unused uint16_t queue_id,
1486                                  __rte_unused uint8_t stat_idx,
1487                                  __rte_unused uint8_t is_rx)
1488 {
1489         PMD_INIT_FUNC_TRACE();
1490
1491         return -ENOSYS;
1492 }
1493
1494 static void
1495 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1496 {
1497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1498         struct i40e_vsi *vsi = pf->main_vsi;
1499
1500         dev_info->max_rx_queues = vsi->nb_qps;
1501         dev_info->max_tx_queues = vsi->nb_qps;
1502         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1503         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1504         dev_info->max_mac_addrs = vsi->max_macaddrs;
1505         dev_info->max_vfs = dev->pci_dev->max_vfs;
1506         dev_info->rx_offload_capa =
1507                 DEV_RX_OFFLOAD_VLAN_STRIP |
1508                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1509                 DEV_RX_OFFLOAD_UDP_CKSUM |
1510                 DEV_RX_OFFLOAD_TCP_CKSUM;
1511         dev_info->tx_offload_capa =
1512                 DEV_TX_OFFLOAD_VLAN_INSERT |
1513                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1514                 DEV_TX_OFFLOAD_UDP_CKSUM |
1515                 DEV_TX_OFFLOAD_TCP_CKSUM |
1516                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1517         dev_info->reta_size = pf->hash_lut_size;
1518
1519         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1520                 .rx_thresh = {
1521                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1522                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1523                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1524                 },
1525                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1526                 .rx_drop_en = 0,
1527         };
1528
1529         dev_info->default_txconf = (struct rte_eth_txconf) {
1530                 .tx_thresh = {
1531                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1532                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1533                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1534                 },
1535                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1536                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1537                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1538                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1539         };
1540
1541         if (pf->flags | I40E_FLAG_VMDQ) {
1542                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1543                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1544                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1545                                                 pf->max_nb_vmdq_vsi;
1546                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1547                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1548                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1549         }
1550 }
1551
1552 static int
1553 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1554 {
1555         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1556         struct i40e_vsi *vsi = pf->main_vsi;
1557         PMD_INIT_FUNC_TRACE();
1558
1559         if (on)
1560                 return i40e_vsi_add_vlan(vsi, vlan_id);
1561         else
1562                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1563 }
1564
1565 static void
1566 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1567                    __rte_unused uint16_t tpid)
1568 {
1569         PMD_INIT_FUNC_TRACE();
1570 }
1571
1572 static void
1573 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1574 {
1575         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1576         struct i40e_vsi *vsi = pf->main_vsi;
1577
1578         if (mask & ETH_VLAN_STRIP_MASK) {
1579                 /* Enable or disable VLAN stripping */
1580                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1581                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1582                 else
1583                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1584         }
1585
1586         if (mask & ETH_VLAN_EXTEND_MASK) {
1587                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1588                         i40e_vsi_config_double_vlan(vsi, TRUE);
1589                 else
1590                         i40e_vsi_config_double_vlan(vsi, FALSE);
1591         }
1592 }
1593
1594 static void
1595 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1596                           __rte_unused uint16_t queue,
1597                           __rte_unused int on)
1598 {
1599         PMD_INIT_FUNC_TRACE();
1600 }
1601
1602 static int
1603 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1604 {
1605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1606         struct i40e_vsi *vsi = pf->main_vsi;
1607         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1608         struct i40e_vsi_vlan_pvid_info info;
1609
1610         memset(&info, 0, sizeof(info));
1611         info.on = on;
1612         if (info.on)
1613                 info.config.pvid = pvid;
1614         else {
1615                 info.config.reject.tagged =
1616                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1617                 info.config.reject.untagged =
1618                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1619         }
1620
1621         return i40e_vsi_vlan_pvid_set(vsi, &info);
1622 }
1623
1624 static int
1625 i40e_dev_led_on(struct rte_eth_dev *dev)
1626 {
1627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         uint32_t mode = i40e_led_get(hw);
1629
1630         if (mode == 0)
1631                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1632
1633         return 0;
1634 }
1635
1636 static int
1637 i40e_dev_led_off(struct rte_eth_dev *dev)
1638 {
1639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         uint32_t mode = i40e_led_get(hw);
1641
1642         if (mode != 0)
1643                 i40e_led_set(hw, 0, false);
1644
1645         return 0;
1646 }
1647
1648 static int
1649 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1650                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1651 {
1652         PMD_INIT_FUNC_TRACE();
1653
1654         return -ENOSYS;
1655 }
1656
1657 static int
1658 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1659                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1660 {
1661         PMD_INIT_FUNC_TRACE();
1662
1663         return -ENOSYS;
1664 }
1665
1666 /* Add a MAC address, and update filters */
1667 static void
1668 i40e_macaddr_add(struct rte_eth_dev *dev,
1669                  struct ether_addr *mac_addr,
1670                  __rte_unused uint32_t index,
1671                  uint32_t pool)
1672 {
1673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1674         struct i40e_mac_filter_info mac_filter;
1675         struct i40e_vsi *vsi;
1676         int ret;
1677
1678         /* If VMDQ not enabled or configured, return */
1679         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1680                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1681                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1682                         pool);
1683                 return;
1684         }
1685
1686         if (pool > pf->nb_cfg_vmdq_vsi) {
1687                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1688                                 pool, pf->nb_cfg_vmdq_vsi);
1689                 return;
1690         }
1691
1692         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1693         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1694
1695         if (pool == 0)
1696                 vsi = pf->main_vsi;
1697         else
1698                 vsi = pf->vmdq[pool - 1].vsi;
1699
1700         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1701         if (ret != I40E_SUCCESS) {
1702                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1703                 return;
1704         }
1705 }
1706
1707 /* Remove a MAC address, and update filters */
1708 static void
1709 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1710 {
1711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712         struct i40e_vsi *vsi;
1713         struct rte_eth_dev_data *data = dev->data;
1714         struct ether_addr *macaddr;
1715         int ret;
1716         uint32_t i;
1717         uint64_t pool_sel;
1718
1719         macaddr = &(data->mac_addrs[index]);
1720
1721         pool_sel = dev->data->mac_pool_sel[index];
1722
1723         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1724                 if (pool_sel & (1ULL << i)) {
1725                         if (i == 0)
1726                                 vsi = pf->main_vsi;
1727                         else {
1728                                 /* No VMDQ pool enabled or configured */
1729                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1730                                         (i > pf->nb_cfg_vmdq_vsi)) {
1731                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1732                                                         "/configured");
1733                                         return;
1734                                 }
1735                                 vsi = pf->vmdq[i - 1].vsi;
1736                         }
1737                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1738
1739                         if (ret) {
1740                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1741                                 return;
1742                         }
1743                 }
1744         }
1745 }
1746
1747 /* Set perfect match or hash match of MAC and VLAN for a VF */
1748 static int
1749 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1750                  struct rte_eth_mac_filter *filter,
1751                  bool add)
1752 {
1753         struct i40e_hw *hw;
1754         struct i40e_mac_filter_info mac_filter;
1755         struct ether_addr old_mac;
1756         struct ether_addr *new_mac;
1757         struct i40e_pf_vf *vf = NULL;
1758         uint16_t vf_id;
1759         int ret;
1760
1761         if (pf == NULL) {
1762                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1763                 return -EINVAL;
1764         }
1765         hw = I40E_PF_TO_HW(pf);
1766
1767         if (filter == NULL) {
1768                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1769                 return -EINVAL;
1770         }
1771
1772         new_mac = &filter->mac_addr;
1773
1774         if (is_zero_ether_addr(new_mac)) {
1775                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1776                 return -EINVAL;
1777         }
1778
1779         vf_id = filter->dst_id;
1780
1781         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1782                 PMD_DRV_LOG(ERR, "Invalid argument.");
1783                 return -EINVAL;
1784         }
1785         vf = &pf->vfs[vf_id];
1786
1787         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1788                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1789                 return -EINVAL;
1790         }
1791
1792         if (add) {
1793                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1794                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1795                                 ETHER_ADDR_LEN);
1796                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1797                                  ETHER_ADDR_LEN);
1798
1799                 mac_filter.filter_type = filter->filter_type;
1800                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1801                 if (ret != I40E_SUCCESS) {
1802                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1803                         return -1;
1804                 }
1805                 ether_addr_copy(new_mac, &pf->dev_addr);
1806         } else {
1807                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1808                                 ETHER_ADDR_LEN);
1809                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1810                 if (ret != I40E_SUCCESS) {
1811                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1812                         return -1;
1813                 }
1814
1815                 /* Clear device address as it has been removed */
1816                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1817                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1818         }
1819
1820         return 0;
1821 }
1822
1823 /* MAC filter handle */
1824 static int
1825 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1826                 void *arg)
1827 {
1828         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1829         struct rte_eth_mac_filter *filter;
1830         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1831         int ret = I40E_NOT_SUPPORTED;
1832
1833         filter = (struct rte_eth_mac_filter *)(arg);
1834
1835         switch (filter_op) {
1836         case RTE_ETH_FILTER_NOP:
1837                 ret = I40E_SUCCESS;
1838                 break;
1839         case RTE_ETH_FILTER_ADD:
1840                 i40e_pf_disable_irq0(hw);
1841                 if (filter->is_vf)
1842                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1843                 i40e_pf_enable_irq0(hw);
1844                 break;
1845         case RTE_ETH_FILTER_DELETE:
1846                 i40e_pf_disable_irq0(hw);
1847                 if (filter->is_vf)
1848                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1849                 i40e_pf_enable_irq0(hw);
1850                 break;
1851         default:
1852                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1853                 ret = I40E_ERR_PARAM;
1854                 break;
1855         }
1856
1857         return ret;
1858 }
1859
1860 static int
1861 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1862                          struct rte_eth_rss_reta_entry64 *reta_conf,
1863                          uint16_t reta_size)
1864 {
1865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867         uint32_t lut, l;
1868         uint16_t i, j, lut_size = pf->hash_lut_size;
1869         uint16_t idx, shift;
1870         uint8_t mask;
1871
1872         if (reta_size != lut_size ||
1873                 reta_size > ETH_RSS_RETA_SIZE_512) {
1874                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1875                         "(%d) doesn't match the number hardware can supported "
1876                                         "(%d)\n", reta_size, lut_size);
1877                 return -EINVAL;
1878         }
1879
1880         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1881                 idx = i / RTE_RETA_GROUP_SIZE;
1882                 shift = i % RTE_RETA_GROUP_SIZE;
1883                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1884                                                 I40E_4_BIT_MASK);
1885                 if (!mask)
1886                         continue;
1887                 if (mask == I40E_4_BIT_MASK)
1888                         l = 0;
1889                 else
1890                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1891                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1892                         if (mask & (0x1 << j))
1893                                 lut |= reta_conf[idx].reta[shift + j] <<
1894                                                         (CHAR_BIT * j);
1895                         else
1896                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1897                 }
1898                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int
1905 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1906                         struct rte_eth_rss_reta_entry64 *reta_conf,
1907                         uint16_t reta_size)
1908 {
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         uint32_t lut;
1912         uint16_t i, j, lut_size = pf->hash_lut_size;
1913         uint16_t idx, shift;
1914         uint8_t mask;
1915
1916         if (reta_size != lut_size ||
1917                 reta_size > ETH_RSS_RETA_SIZE_512) {
1918                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1919                         "(%d) doesn't match the number hardware can supported "
1920                                         "(%d)\n", reta_size, lut_size);
1921                 return -EINVAL;
1922         }
1923
1924         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1925                 idx = i / RTE_RETA_GROUP_SIZE;
1926                 shift = i % RTE_RETA_GROUP_SIZE;
1927                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1928                                                 I40E_4_BIT_MASK);
1929                 if (!mask)
1930                         continue;
1931
1932                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1933                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1934                         if (mask & (0x1 << j))
1935                                 reta_conf[idx].reta[shift + j] = ((lut >>
1936                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1937                 }
1938         }
1939
1940         return 0;
1941 }
1942
1943 /**
1944  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1945  * @hw:   pointer to the HW structure
1946  * @mem:  pointer to mem struct to fill out
1947  * @size: size of memory requested
1948  * @alignment: what to align the allocation to
1949  **/
1950 enum i40e_status_code
1951 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1952                         struct i40e_dma_mem *mem,
1953                         u64 size,
1954                         u32 alignment)
1955 {
1956         static uint64_t id = 0;
1957         const struct rte_memzone *mz = NULL;
1958         char z_name[RTE_MEMZONE_NAMESIZE];
1959
1960         if (!mem)
1961                 return I40E_ERR_PARAM;
1962
1963         id++;
1964         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1965 #ifdef RTE_LIBRTE_XEN_DOM0
1966         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1967                                                         RTE_PGSIZE_2M);
1968 #else
1969         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1970 #endif
1971         if (!mz)
1972                 return I40E_ERR_NO_MEMORY;
1973
1974         mem->id = id;
1975         mem->size = size;
1976         mem->va = mz->addr;
1977 #ifdef RTE_LIBRTE_XEN_DOM0
1978         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1979 #else
1980         mem->pa = mz->phys_addr;
1981 #endif
1982
1983         return I40E_SUCCESS;
1984 }
1985
1986 /**
1987  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1988  * @hw:   pointer to the HW structure
1989  * @mem:  ptr to mem struct to free
1990  **/
1991 enum i40e_status_code
1992 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1993                     struct i40e_dma_mem *mem)
1994 {
1995         if (!mem || !mem->va)
1996                 return I40E_ERR_PARAM;
1997
1998         mem->va = NULL;
1999         mem->pa = (u64)0;
2000
2001         return I40E_SUCCESS;
2002 }
2003
2004 /**
2005  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2006  * @hw:   pointer to the HW structure
2007  * @mem:  pointer to mem struct to fill out
2008  * @size: size of memory requested
2009  **/
2010 enum i40e_status_code
2011 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2012                          struct i40e_virt_mem *mem,
2013                          u32 size)
2014 {
2015         if (!mem)
2016                 return I40E_ERR_PARAM;
2017
2018         mem->size = size;
2019         mem->va = rte_zmalloc("i40e", size, 0);
2020
2021         if (mem->va)
2022                 return I40E_SUCCESS;
2023         else
2024                 return I40E_ERR_NO_MEMORY;
2025 }
2026
2027 /**
2028  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2029  * @hw:   pointer to the HW structure
2030  * @mem:  pointer to mem struct to free
2031  **/
2032 enum i40e_status_code
2033 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2034                      struct i40e_virt_mem *mem)
2035 {
2036         if (!mem)
2037                 return I40E_ERR_PARAM;
2038
2039         rte_free(mem->va);
2040         mem->va = NULL;
2041
2042         return I40E_SUCCESS;
2043 }
2044
2045 void
2046 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2047 {
2048         rte_spinlock_init(&sp->spinlock);
2049 }
2050
2051 void
2052 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2053 {
2054         rte_spinlock_lock(&sp->spinlock);
2055 }
2056
2057 void
2058 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2059 {
2060         rte_spinlock_unlock(&sp->spinlock);
2061 }
2062
2063 void
2064 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2065 {
2066         return;
2067 }
2068
2069 /**
2070  * Get the hardware capabilities, which will be parsed
2071  * and saved into struct i40e_hw.
2072  */
2073 static int
2074 i40e_get_cap(struct i40e_hw *hw)
2075 {
2076         struct i40e_aqc_list_capabilities_element_resp *buf;
2077         uint16_t len, size = 0;
2078         int ret;
2079
2080         /* Calculate a huge enough buff for saving response data temporarily */
2081         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2082                                                 I40E_MAX_CAP_ELE_NUM;
2083         buf = rte_zmalloc("i40e", len, 0);
2084         if (!buf) {
2085                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2086                 return I40E_ERR_NO_MEMORY;
2087         }
2088
2089         /* Get, parse the capabilities and save it to hw */
2090         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2091                         i40e_aqc_opc_list_func_capabilities, NULL);
2092         if (ret != I40E_SUCCESS)
2093                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2094
2095         /* Free the temporary buffer after being used */
2096         rte_free(buf);
2097
2098         return ret;
2099 }
2100
2101 static int
2102 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2103 {
2104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2106         uint16_t sum_queues = 0, sum_vsis, left_queues;
2107
2108         /* First check if FW support SRIOV */
2109         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2110                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2111                 return -EINVAL;
2112         }
2113
2114         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2115         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2116         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2117         /* Allocate queues for pf */
2118         if (hw->func_caps.rss) {
2119                 pf->flags |= I40E_FLAG_RSS;
2120                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2121                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2122                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2123         } else
2124                 pf->lan_nb_qps = 1;
2125         sum_queues = pf->lan_nb_qps;
2126         /* Default VSI is not counted in */
2127         sum_vsis = 0;
2128         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2129
2130         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2131                 pf->flags |= I40E_FLAG_SRIOV;
2132                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2133                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2134                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2135                                      "max supported %u.",
2136                                      dev->pci_dev->max_vfs,
2137                                      hw->func_caps.num_vfs);
2138                         return -EINVAL;
2139                 }
2140                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2141                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2142                                      "max support %u queues.",
2143                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2144                         return -EINVAL;
2145                 }
2146                 pf->vf_num = dev->pci_dev->max_vfs;
2147                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2148                 sum_vsis   += pf->vf_num;
2149                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2150                              pf->vf_num, pf->vf_nb_qps);
2151         } else
2152                 pf->vf_num = 0;
2153
2154         if (hw->func_caps.vmdq) {
2155                 pf->flags |= I40E_FLAG_VMDQ;
2156                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2157                 pf->max_nb_vmdq_vsi = 1;
2158                 /*
2159                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2160                  * later.
2161                  */
2162                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2163                 sum_vsis += pf->max_nb_vmdq_vsi;
2164         } else {
2165                 pf->vmdq_nb_qps = 0;
2166                 pf->max_nb_vmdq_vsi = 0;
2167         }
2168         pf->nb_cfg_vmdq_vsi = 0;
2169
2170         if (hw->func_caps.fd) {
2171                 pf->flags |= I40E_FLAG_FDIR;
2172                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2173                 /**
2174                  * Each flow director consumes one VSI and one queue,
2175                  * but can't calculate out predictably here.
2176                  */
2177         }
2178
2179         if (sum_vsis > pf->max_num_vsi ||
2180                 sum_queues > hw->func_caps.num_rx_qp) {
2181                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2182                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2183                              pf->max_num_vsi, sum_vsis);
2184                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2185                              hw->func_caps.num_rx_qp, sum_queues);
2186                 return -EINVAL;
2187         }
2188
2189         /* Adjust VMDQ setting to support as many VMs as possible */
2190         if (pf->flags & I40E_FLAG_VMDQ) {
2191                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2192
2193                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2194                                         pf->max_num_vsi - sum_vsis);
2195
2196                 /* Limit the max VMDQ number that rte_ether that can support  */
2197                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2198                                         ETH_64_POOLS - 1);
2199
2200                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2201                                 pf->max_nb_vmdq_vsi);
2202                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2203         }
2204
2205         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2206          * cause */
2207         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2208                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2209                              sum_vsis, hw->func_caps.num_msix_vectors);
2210                 return -EINVAL;
2211         }
2212         return I40E_SUCCESS;
2213 }
2214
2215 static int
2216 i40e_pf_get_switch_config(struct i40e_pf *pf)
2217 {
2218         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2219         struct i40e_aqc_get_switch_config_resp *switch_config;
2220         struct i40e_aqc_switch_config_element_resp *element;
2221         uint16_t start_seid = 0, num_reported;
2222         int ret;
2223
2224         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2225                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2226         if (!switch_config) {
2227                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2228                 return -ENOMEM;
2229         }
2230
2231         /* Get the switch configurations */
2232         ret = i40e_aq_get_switch_config(hw, switch_config,
2233                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2234         if (ret != I40E_SUCCESS) {
2235                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2236                 goto fail;
2237         }
2238         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2239         if (num_reported != 1) { /* The number should be 1 */
2240                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2241                 goto fail;
2242         }
2243
2244         /* Parse the switch configuration elements */
2245         element = &(switch_config->element[0]);
2246         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2247                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2248                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2249         } else
2250                 PMD_DRV_LOG(INFO, "Unknown element type");
2251
2252 fail:
2253         rte_free(switch_config);
2254
2255         return ret;
2256 }
2257
2258 static int
2259 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2260                         uint32_t num)
2261 {
2262         struct pool_entry *entry;
2263
2264         if (pool == NULL || num == 0)
2265                 return -EINVAL;
2266
2267         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2268         if (entry == NULL) {
2269                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2270                 return -ENOMEM;
2271         }
2272
2273         /* queue heap initialize */
2274         pool->num_free = num;
2275         pool->num_alloc = 0;
2276         pool->base = base;
2277         LIST_INIT(&pool->alloc_list);
2278         LIST_INIT(&pool->free_list);
2279
2280         /* Initialize element  */
2281         entry->base = 0;
2282         entry->len = num;
2283
2284         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2285         return 0;
2286 }
2287
2288 static void
2289 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2290 {
2291         struct pool_entry *entry;
2292
2293         if (pool == NULL)
2294                 return;
2295
2296         LIST_FOREACH(entry, &pool->alloc_list, next) {
2297                 LIST_REMOVE(entry, next);
2298                 rte_free(entry);
2299         }
2300
2301         LIST_FOREACH(entry, &pool->free_list, next) {
2302                 LIST_REMOVE(entry, next);
2303                 rte_free(entry);
2304         }
2305
2306         pool->num_free = 0;
2307         pool->num_alloc = 0;
2308         pool->base = 0;
2309         LIST_INIT(&pool->alloc_list);
2310         LIST_INIT(&pool->free_list);
2311 }
2312
2313 static int
2314 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2315                        uint32_t base)
2316 {
2317         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2318         uint32_t pool_offset;
2319         int insert;
2320
2321         if (pool == NULL) {
2322                 PMD_DRV_LOG(ERR, "Invalid parameter");
2323                 return -EINVAL;
2324         }
2325
2326         pool_offset = base - pool->base;
2327         /* Lookup in alloc list */
2328         LIST_FOREACH(entry, &pool->alloc_list, next) {
2329                 if (entry->base == pool_offset) {
2330                         valid_entry = entry;
2331                         LIST_REMOVE(entry, next);
2332                         break;
2333                 }
2334         }
2335
2336         /* Not find, return */
2337         if (valid_entry == NULL) {
2338                 PMD_DRV_LOG(ERR, "Failed to find entry");
2339                 return -EINVAL;
2340         }
2341
2342         /**
2343          * Found it, move it to free list  and try to merge.
2344          * In order to make merge easier, always sort it by qbase.
2345          * Find adjacent prev and last entries.
2346          */
2347         prev = next = NULL;
2348         LIST_FOREACH(entry, &pool->free_list, next) {
2349                 if (entry->base > valid_entry->base) {
2350                         next = entry;
2351                         break;
2352                 }
2353                 prev = entry;
2354         }
2355
2356         insert = 0;
2357         /* Try to merge with next one*/
2358         if (next != NULL) {
2359                 /* Merge with next one */
2360                 if (valid_entry->base + valid_entry->len == next->base) {
2361                         next->base = valid_entry->base;
2362                         next->len += valid_entry->len;
2363                         rte_free(valid_entry);
2364                         valid_entry = next;
2365                         insert = 1;
2366                 }
2367         }
2368
2369         if (prev != NULL) {
2370                 /* Merge with previous one */
2371                 if (prev->base + prev->len == valid_entry->base) {
2372                         prev->len += valid_entry->len;
2373                         /* If it merge with next one, remove next node */
2374                         if (insert == 1) {
2375                                 LIST_REMOVE(valid_entry, next);
2376                                 rte_free(valid_entry);
2377                         } else {
2378                                 rte_free(valid_entry);
2379                                 insert = 1;
2380                         }
2381                 }
2382         }
2383
2384         /* Not find any entry to merge, insert */
2385         if (insert == 0) {
2386                 if (prev != NULL)
2387                         LIST_INSERT_AFTER(prev, valid_entry, next);
2388                 else if (next != NULL)
2389                         LIST_INSERT_BEFORE(next, valid_entry, next);
2390                 else /* It's empty list, insert to head */
2391                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2392         }
2393
2394         pool->num_free += valid_entry->len;
2395         pool->num_alloc -= valid_entry->len;
2396
2397         return 0;
2398 }
2399
2400 static int
2401 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2402                        uint16_t num)
2403 {
2404         struct pool_entry *entry, *valid_entry;
2405
2406         if (pool == NULL || num == 0) {
2407                 PMD_DRV_LOG(ERR, "Invalid parameter");
2408                 return -EINVAL;
2409         }
2410
2411         if (pool->num_free < num) {
2412                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2413                             num, pool->num_free);
2414                 return -ENOMEM;
2415         }
2416
2417         valid_entry = NULL;
2418         /* Lookup  in free list and find most fit one */
2419         LIST_FOREACH(entry, &pool->free_list, next) {
2420                 if (entry->len >= num) {
2421                         /* Find best one */
2422                         if (entry->len == num) {
2423                                 valid_entry = entry;
2424                                 break;
2425                         }
2426                         if (valid_entry == NULL || valid_entry->len > entry->len)
2427                                 valid_entry = entry;
2428                 }
2429         }
2430
2431         /* Not find one to satisfy the request, return */
2432         if (valid_entry == NULL) {
2433                 PMD_DRV_LOG(ERR, "No valid entry found");
2434                 return -ENOMEM;
2435         }
2436         /**
2437          * The entry have equal queue number as requested,
2438          * remove it from alloc_list.
2439          */
2440         if (valid_entry->len == num) {
2441                 LIST_REMOVE(valid_entry, next);
2442         } else {
2443                 /**
2444                  * The entry have more numbers than requested,
2445                  * create a new entry for alloc_list and minus its
2446                  * queue base and number in free_list.
2447                  */
2448                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2449                 if (entry == NULL) {
2450                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2451                                     "resource pool");
2452                         return -ENOMEM;
2453                 }
2454                 entry->base = valid_entry->base;
2455                 entry->len = num;
2456                 valid_entry->base += num;
2457                 valid_entry->len -= num;
2458                 valid_entry = entry;
2459         }
2460
2461         /* Insert it into alloc list, not sorted */
2462         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2463
2464         pool->num_free -= valid_entry->len;
2465         pool->num_alloc += valid_entry->len;
2466
2467         return (valid_entry->base + pool->base);
2468 }
2469
2470 /**
2471  * bitmap_is_subset - Check whether src2 is subset of src1
2472  **/
2473 static inline int
2474 bitmap_is_subset(uint8_t src1, uint8_t src2)
2475 {
2476         return !((src1 ^ src2) & src2);
2477 }
2478
2479 static int
2480 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2481 {
2482         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2483
2484         /* If DCB is not supported, only default TC is supported */
2485         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2486                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2487                 return -EINVAL;
2488         }
2489
2490         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2491                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2492                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2493                             enabled_tcmap);
2494                 return -EINVAL;
2495         }
2496         return I40E_SUCCESS;
2497 }
2498
2499 int
2500 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2501                                 struct i40e_vsi_vlan_pvid_info *info)
2502 {
2503         struct i40e_hw *hw;
2504         struct i40e_vsi_context ctxt;
2505         uint8_t vlan_flags = 0;
2506         int ret;
2507
2508         if (vsi == NULL || info == NULL) {
2509                 PMD_DRV_LOG(ERR, "invalid parameters");
2510                 return I40E_ERR_PARAM;
2511         }
2512
2513         if (info->on) {
2514                 vsi->info.pvid = info->config.pvid;
2515                 /**
2516                  * If insert pvid is enabled, only tagged pkts are
2517                  * allowed to be sent out.
2518                  */
2519                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2520                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2521         } else {
2522                 vsi->info.pvid = 0;
2523                 if (info->config.reject.tagged == 0)
2524                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2525
2526                 if (info->config.reject.untagged == 0)
2527                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2528         }
2529         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2530                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2531         vsi->info.port_vlan_flags |= vlan_flags;
2532         vsi->info.valid_sections =
2533                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2534         memset(&ctxt, 0, sizeof(ctxt));
2535         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2536         ctxt.seid = vsi->seid;
2537
2538         hw = I40E_VSI_TO_HW(vsi);
2539         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2540         if (ret != I40E_SUCCESS)
2541                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2542
2543         return ret;
2544 }
2545
2546 static int
2547 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2548 {
2549         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2550         int i, ret;
2551         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2552
2553         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2554         if (ret != I40E_SUCCESS)
2555                 return ret;
2556
2557         if (!vsi->seid) {
2558                 PMD_DRV_LOG(ERR, "seid not valid");
2559                 return -EINVAL;
2560         }
2561
2562         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2563         tc_bw_data.tc_valid_bits = enabled_tcmap;
2564         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2565                 tc_bw_data.tc_bw_credits[i] =
2566                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2567
2568         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2569         if (ret != I40E_SUCCESS) {
2570                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2571                 return ret;
2572         }
2573
2574         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2575                                         sizeof(vsi->info.qs_handle));
2576         return I40E_SUCCESS;
2577 }
2578
2579 static int
2580 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2581                                  struct i40e_aqc_vsi_properties_data *info,
2582                                  uint8_t enabled_tcmap)
2583 {
2584         int ret, total_tc = 0, i;
2585         uint16_t qpnum_per_tc, bsf, qp_idx;
2586
2587         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2588         if (ret != I40E_SUCCESS)
2589                 return ret;
2590
2591         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2592                 if (enabled_tcmap & (1 << i))
2593                         total_tc++;
2594         vsi->enabled_tc = enabled_tcmap;
2595
2596         /* Number of queues per enabled TC */
2597         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2598         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2599         bsf = rte_bsf32(qpnum_per_tc);
2600
2601         /* Adjust the queue number to actual queues that can be applied */
2602         vsi->nb_qps = qpnum_per_tc * total_tc;
2603
2604         /**
2605          * Configure TC and queue mapping parameters, for enabled TC,
2606          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2607          * default queue will serve it.
2608          */
2609         qp_idx = 0;
2610         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2611                 if (vsi->enabled_tc & (1 << i)) {
2612                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2613                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2614                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2615                         qp_idx += qpnum_per_tc;
2616                 } else
2617                         info->tc_mapping[i] = 0;
2618         }
2619
2620         /* Associate queue number with VSI */
2621         if (vsi->type == I40E_VSI_SRIOV) {
2622                 info->mapping_flags |=
2623                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2624                 for (i = 0; i < vsi->nb_qps; i++)
2625                         info->queue_mapping[i] =
2626                                 rte_cpu_to_le_16(vsi->base_queue + i);
2627         } else {
2628                 info->mapping_flags |=
2629                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2630                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2631         }
2632         info->valid_sections =
2633                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2634
2635         return I40E_SUCCESS;
2636 }
2637
2638 static int
2639 i40e_veb_release(struct i40e_veb *veb)
2640 {
2641         struct i40e_vsi *vsi;
2642         struct i40e_hw *hw;
2643
2644         if (veb == NULL || veb->associate_vsi == NULL)
2645                 return -EINVAL;
2646
2647         if (!TAILQ_EMPTY(&veb->head)) {
2648                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2649                 return -EACCES;
2650         }
2651
2652         vsi = veb->associate_vsi;
2653         hw = I40E_VSI_TO_HW(vsi);
2654
2655         vsi->uplink_seid = veb->uplink_seid;
2656         i40e_aq_delete_element(hw, veb->seid, NULL);
2657         rte_free(veb);
2658         vsi->veb = NULL;
2659         return I40E_SUCCESS;
2660 }
2661
2662 /* Setup a veb */
2663 static struct i40e_veb *
2664 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2665 {
2666         struct i40e_veb *veb;
2667         int ret;
2668         struct i40e_hw *hw;
2669
2670         if (NULL == pf || vsi == NULL) {
2671                 PMD_DRV_LOG(ERR, "veb setup failed, "
2672                             "associated VSI shouldn't null");
2673                 return NULL;
2674         }
2675         hw = I40E_PF_TO_HW(pf);
2676
2677         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2678         if (!veb) {
2679                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2680                 goto fail;
2681         }
2682
2683         veb->associate_vsi = vsi;
2684         TAILQ_INIT(&veb->head);
2685         veb->uplink_seid = vsi->uplink_seid;
2686
2687         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2688                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2689
2690         if (ret != I40E_SUCCESS) {
2691                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2692                             hw->aq.asq_last_status);
2693                 goto fail;
2694         }
2695
2696         /* get statistics index */
2697         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2698                                 &veb->stats_idx, NULL, NULL, NULL);
2699         if (ret != I40E_SUCCESS) {
2700                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2701                             hw->aq.asq_last_status);
2702                 goto fail;
2703         }
2704
2705         /* Get VEB bandwidth, to be implemented */
2706         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2707         vsi->uplink_seid = veb->seid;
2708
2709         return veb;
2710 fail:
2711         rte_free(veb);
2712         return NULL;
2713 }
2714
2715 int
2716 i40e_vsi_release(struct i40e_vsi *vsi)
2717 {
2718         struct i40e_pf *pf;
2719         struct i40e_hw *hw;
2720         struct i40e_vsi_list *vsi_list;
2721         int ret;
2722         struct i40e_mac_filter *f;
2723
2724         if (!vsi)
2725                 return I40E_SUCCESS;
2726
2727         pf = I40E_VSI_TO_PF(vsi);
2728         hw = I40E_VSI_TO_HW(vsi);
2729
2730         /* VSI has child to attach, release child first */
2731         if (vsi->veb) {
2732                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2733                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2734                                 return -1;
2735                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2736                 }
2737                 i40e_veb_release(vsi->veb);
2738         }
2739
2740         /* Remove all macvlan filters of the VSI */
2741         i40e_vsi_remove_all_macvlan_filter(vsi);
2742         TAILQ_FOREACH(f, &vsi->mac_list, next)
2743                 rte_free(f);
2744
2745         if (vsi->type != I40E_VSI_MAIN) {
2746                 /* Remove vsi from parent's sibling list */
2747                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2748                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2749                         return I40E_ERR_PARAM;
2750                 }
2751                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2752                                 &vsi->sib_vsi_list, list);
2753
2754                 /* Remove all switch element of the VSI */
2755                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2756                 if (ret != I40E_SUCCESS)
2757                         PMD_DRV_LOG(ERR, "Failed to delete element");
2758         }
2759         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2760
2761         if (vsi->type != I40E_VSI_SRIOV)
2762                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2763         rte_free(vsi);
2764
2765         return I40E_SUCCESS;
2766 }
2767
2768 static int
2769 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2770 {
2771         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2772         struct i40e_aqc_remove_macvlan_element_data def_filter;
2773         struct i40e_mac_filter_info filter;
2774         int ret;
2775
2776         if (vsi->type != I40E_VSI_MAIN)
2777                 return I40E_ERR_CONFIG;
2778         memset(&def_filter, 0, sizeof(def_filter));
2779         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2780                                         ETH_ADDR_LEN);
2781         def_filter.vlan_tag = 0;
2782         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2783                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2784         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2785         if (ret != I40E_SUCCESS) {
2786                 struct i40e_mac_filter *f;
2787                 struct ether_addr *mac;
2788
2789                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2790                             "macvlan filter");
2791                 /* It needs to add the permanent mac into mac list */
2792                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2793                 if (f == NULL) {
2794                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2795                         return I40E_ERR_NO_MEMORY;
2796                 }
2797                 mac = &f->mac_info.mac_addr;
2798                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2799                                 ETH_ADDR_LEN);
2800                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2801                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2802                 vsi->mac_num++;
2803
2804                 return ret;
2805         }
2806         (void)rte_memcpy(&filter.mac_addr,
2807                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2808         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2809         return i40e_vsi_add_mac(vsi, &filter);
2810 }
2811
2812 static int
2813 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2814 {
2815         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2816         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2817         struct i40e_hw *hw = &vsi->adapter->hw;
2818         i40e_status ret;
2819         int i;
2820
2821         memset(&bw_config, 0, sizeof(bw_config));
2822         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2823         if (ret != I40E_SUCCESS) {
2824                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2825                             hw->aq.asq_last_status);
2826                 return ret;
2827         }
2828
2829         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2830         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2831                                         &ets_sla_config, NULL);
2832         if (ret != I40E_SUCCESS) {
2833                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2834                             "configuration %u", hw->aq.asq_last_status);
2835                 return ret;
2836         }
2837
2838         /* Not store the info yet, just print out */
2839         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2840         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2841         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2842                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2843                             ets_sla_config.share_credits[i]);
2844                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2845                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2846                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2847                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2848                             (i * 4));
2849         }
2850
2851         return 0;
2852 }
2853
2854 /* Setup a VSI */
2855 struct i40e_vsi *
2856 i40e_vsi_setup(struct i40e_pf *pf,
2857                enum i40e_vsi_type type,
2858                struct i40e_vsi *uplink_vsi,
2859                uint16_t user_param)
2860 {
2861         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2862         struct i40e_vsi *vsi;
2863         struct i40e_mac_filter_info filter;
2864         int ret;
2865         struct i40e_vsi_context ctxt;
2866         struct ether_addr broadcast =
2867                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2868
2869         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2870                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2871                             "VSI link shouldn't be NULL");
2872                 return NULL;
2873         }
2874
2875         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2876                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2877                             "uplink VSI should be NULL");
2878                 return NULL;
2879         }
2880
2881         /* If uplink vsi didn't setup VEB, create one first */
2882         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2883                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2884
2885                 if (NULL == uplink_vsi->veb) {
2886                         PMD_DRV_LOG(ERR, "VEB setup failed");
2887                         return NULL;
2888                 }
2889         }
2890
2891         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2892         if (!vsi) {
2893                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2894                 return NULL;
2895         }
2896         TAILQ_INIT(&vsi->mac_list);
2897         vsi->type = type;
2898         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2899         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2900         vsi->parent_vsi = uplink_vsi;
2901         vsi->user_param = user_param;
2902         /* Allocate queues */
2903         switch (vsi->type) {
2904         case I40E_VSI_MAIN  :
2905                 vsi->nb_qps = pf->lan_nb_qps;
2906                 break;
2907         case I40E_VSI_SRIOV :
2908                 vsi->nb_qps = pf->vf_nb_qps;
2909                 break;
2910         case I40E_VSI_VMDQ2:
2911                 vsi->nb_qps = pf->vmdq_nb_qps;
2912                 break;
2913         case I40E_VSI_FDIR:
2914                 vsi->nb_qps = pf->fdir_nb_qps;
2915                 break;
2916         default:
2917                 goto fail_mem;
2918         }
2919         /*
2920          * The filter status descriptor is reported in rx queue 0,
2921          * while the tx queue for fdir filter programming has no
2922          * such constraints, can be non-zero queues.
2923          * To simplify it, choose FDIR vsi use queue 0 pair.
2924          * To make sure it will use queue 0 pair, queue allocation
2925          * need be done before this function is called
2926          */
2927         if (type != I40E_VSI_FDIR) {
2928                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2929                         if (ret < 0) {
2930                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2931                                                 vsi->seid, ret);
2932                                 goto fail_mem;
2933                         }
2934                         vsi->base_queue = ret;
2935         } else
2936                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2937
2938         /* VF has MSIX interrupt in VF range, don't allocate here */
2939         if (type != I40E_VSI_SRIOV) {
2940                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2941                 if (ret < 0) {
2942                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2943                         goto fail_queue_alloc;
2944                 }
2945                 vsi->msix_intr = ret;
2946         } else
2947                 vsi->msix_intr = 0;
2948         /* Add VSI */
2949         if (type == I40E_VSI_MAIN) {
2950                 /* For main VSI, no need to add since it's default one */
2951                 vsi->uplink_seid = pf->mac_seid;
2952                 vsi->seid = pf->main_vsi_seid;
2953                 /* Bind queues with specific MSIX interrupt */
2954                 /**
2955                  * Needs 2 interrupt at least, one for misc cause which will
2956                  * enabled from OS side, Another for queues binding the
2957                  * interrupt from device side only.
2958                  */
2959
2960                 /* Get default VSI parameters from hardware */
2961                 memset(&ctxt, 0, sizeof(ctxt));
2962                 ctxt.seid = vsi->seid;
2963                 ctxt.pf_num = hw->pf_id;
2964                 ctxt.uplink_seid = vsi->uplink_seid;
2965                 ctxt.vf_num = 0;
2966                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2967                 if (ret != I40E_SUCCESS) {
2968                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2969                         goto fail_msix_alloc;
2970                 }
2971                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2972                         sizeof(struct i40e_aqc_vsi_properties_data));
2973                 vsi->vsi_id = ctxt.vsi_number;
2974                 vsi->info.valid_sections = 0;
2975
2976                 /* Configure tc, enabled TC0 only */
2977                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2978                         I40E_SUCCESS) {
2979                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2980                         goto fail_msix_alloc;
2981                 }
2982
2983                 /* TC, queue mapping */
2984                 memset(&ctxt, 0, sizeof(ctxt));
2985                 vsi->info.valid_sections |=
2986                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2987                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2988                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2989                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2990                         sizeof(struct i40e_aqc_vsi_properties_data));
2991                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2992                                                 I40E_DEFAULT_TCMAP);
2993                 if (ret != I40E_SUCCESS) {
2994                         PMD_DRV_LOG(ERR, "Failed to configure "
2995                                     "TC queue mapping");
2996                         goto fail_msix_alloc;
2997                 }
2998                 ctxt.seid = vsi->seid;
2999                 ctxt.pf_num = hw->pf_id;
3000                 ctxt.uplink_seid = vsi->uplink_seid;
3001                 ctxt.vf_num = 0;
3002
3003                 /* Update VSI parameters */
3004                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3005                 if (ret != I40E_SUCCESS) {
3006                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3007                         goto fail_msix_alloc;
3008                 }
3009
3010                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3011                                                 sizeof(vsi->info.tc_mapping));
3012                 (void)rte_memcpy(&vsi->info.queue_mapping,
3013                                 &ctxt.info.queue_mapping,
3014                         sizeof(vsi->info.queue_mapping));
3015                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3016                 vsi->info.valid_sections = 0;
3017
3018                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3019                                 ETH_ADDR_LEN);
3020
3021                 /**
3022                  * Updating default filter settings are necessary to prevent
3023                  * reception of tagged packets.
3024                  * Some old firmware configurations load a default macvlan
3025                  * filter which accepts both tagged and untagged packets.
3026                  * The updating is to use a normal filter instead if needed.
3027                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3028                  * The firmware with correct configurations load the default
3029                  * macvlan filter which is expected and cannot be removed.
3030                  */
3031                 i40e_update_default_filter_setting(vsi);
3032         } else if (type == I40E_VSI_SRIOV) {
3033                 memset(&ctxt, 0, sizeof(ctxt));
3034                 /**
3035                  * For other VSI, the uplink_seid equals to uplink VSI's
3036                  * uplink_seid since they share same VEB
3037                  */
3038                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3039                 ctxt.pf_num = hw->pf_id;
3040                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3041                 ctxt.uplink_seid = vsi->uplink_seid;
3042                 ctxt.connection_type = 0x1;
3043                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3044
3045                 /* Configure switch ID */
3046                 ctxt.info.valid_sections |=
3047                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3048                 ctxt.info.switch_id =
3049                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3050                 /* Configure port/vlan */
3051                 ctxt.info.valid_sections |=
3052                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3053                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3054                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3055                                                 I40E_DEFAULT_TCMAP);
3056                 if (ret != I40E_SUCCESS) {
3057                         PMD_DRV_LOG(ERR, "Failed to configure "
3058                                     "TC queue mapping");
3059                         goto fail_msix_alloc;
3060                 }
3061                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3062                 ctxt.info.valid_sections |=
3063                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3064                 /**
3065                  * Since VSI is not created yet, only configure parameter,
3066                  * will add vsi below.
3067                  */
3068         } else if (type == I40E_VSI_VMDQ2) {
3069                 memset(&ctxt, 0, sizeof(ctxt));
3070                 /*
3071                  * For other VSI, the uplink_seid equals to uplink VSI's
3072                  * uplink_seid since they share same VEB
3073                  */
3074                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3075                 ctxt.pf_num = hw->pf_id;
3076                 ctxt.vf_num = 0;
3077                 ctxt.uplink_seid = vsi->uplink_seid;
3078                 ctxt.connection_type = 0x1;
3079                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3080
3081                 ctxt.info.valid_sections |=
3082                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3083                 /* user_param carries flag to enable loop back */
3084                 if (user_param) {
3085                         ctxt.info.switch_id =
3086                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3087                         ctxt.info.switch_id |=
3088                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3089                 }
3090
3091                 /* Configure port/vlan */
3092                 ctxt.info.valid_sections |=
3093                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3094                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3095                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3096                                                 I40E_DEFAULT_TCMAP);
3097                 if (ret != I40E_SUCCESS) {
3098                         PMD_DRV_LOG(ERR, "Failed to configure "
3099                                         "TC queue mapping");
3100                         goto fail_msix_alloc;
3101                 }
3102                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3103                 ctxt.info.valid_sections |=
3104                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3105         } else if (type == I40E_VSI_FDIR) {
3106                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3107                 ctxt.pf_num = hw->pf_id;
3108                 ctxt.vf_num = 0;
3109                 ctxt.uplink_seid = vsi->uplink_seid;
3110                 ctxt.connection_type = 0x1;     /* regular data port */
3111                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3112                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3113                                                 I40E_DEFAULT_TCMAP);
3114                 if (ret != I40E_SUCCESS) {
3115                         PMD_DRV_LOG(ERR, "Failed to configure "
3116                                         "TC queue mapping.");
3117                         goto fail_msix_alloc;
3118                 }
3119                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3120                 ctxt.info.valid_sections |=
3121                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3122         } else {
3123                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3124                 goto fail_msix_alloc;
3125         }
3126
3127         if (vsi->type != I40E_VSI_MAIN) {
3128                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3129                 if (ret) {
3130                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3131                                     hw->aq.asq_last_status);
3132                         goto fail_msix_alloc;
3133                 }
3134                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3135                 vsi->info.valid_sections = 0;
3136                 vsi->seid = ctxt.seid;
3137                 vsi->vsi_id = ctxt.vsi_number;
3138                 vsi->sib_vsi_list.vsi = vsi;
3139                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3140                                 &vsi->sib_vsi_list, list);
3141         }
3142
3143         /* MAC/VLAN configuration */
3144         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3145         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3146
3147         ret = i40e_vsi_add_mac(vsi, &filter);
3148         if (ret != I40E_SUCCESS) {
3149                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3150                 goto fail_msix_alloc;
3151         }
3152
3153         /* Get VSI BW information */
3154         i40e_vsi_dump_bw_config(vsi);
3155         return vsi;
3156 fail_msix_alloc:
3157         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3158 fail_queue_alloc:
3159         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3160 fail_mem:
3161         rte_free(vsi);
3162         return NULL;
3163 }
3164
3165 /* Configure vlan stripping on or off */
3166 int
3167 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3168 {
3169         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3170         struct i40e_vsi_context ctxt;
3171         uint8_t vlan_flags;
3172         int ret = I40E_SUCCESS;
3173
3174         /* Check if it has been already on or off */
3175         if (vsi->info.valid_sections &
3176                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3177                 if (on) {
3178                         if ((vsi->info.port_vlan_flags &
3179                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3180                                 return 0; /* already on */
3181                 } else {
3182                         if ((vsi->info.port_vlan_flags &
3183                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3184                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3185                                 return 0; /* already off */
3186                 }
3187         }
3188
3189         if (on)
3190                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3191         else
3192                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3193         vsi->info.valid_sections =
3194                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3195         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3196         vsi->info.port_vlan_flags |= vlan_flags;
3197         ctxt.seid = vsi->seid;
3198         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3199         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3200         if (ret)
3201                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3202                             on ? "enable" : "disable");
3203
3204         return ret;
3205 }
3206
3207 static int
3208 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3209 {
3210         struct rte_eth_dev_data *data = dev->data;
3211         int ret;
3212
3213         /* Apply vlan offload setting */
3214         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3215
3216         /* Apply double-vlan setting, not implemented yet */
3217
3218         /* Apply pvid setting */
3219         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3220                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3221         if (ret)
3222                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3223
3224         return ret;
3225 }
3226
3227 static int
3228 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3229 {
3230         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3231
3232         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3233 }
3234
3235 static int
3236 i40e_update_flow_control(struct i40e_hw *hw)
3237 {
3238 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3239         struct i40e_link_status link_status;
3240         uint32_t rxfc = 0, txfc = 0, reg;
3241         uint8_t an_info;
3242         int ret;
3243
3244         memset(&link_status, 0, sizeof(link_status));
3245         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3246         if (ret != I40E_SUCCESS) {
3247                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3248                 goto write_reg; /* Disable flow control */
3249         }
3250
3251         an_info = hw->phy.link_info.an_info;
3252         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3253                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3254                 ret = I40E_ERR_NOT_READY;
3255                 goto write_reg; /* Disable flow control */
3256         }
3257         /**
3258          * If link auto negotiation is enabled, flow control needs to
3259          * be configured according to it
3260          */
3261         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3262         case I40E_LINK_PAUSE_RXTX:
3263                 rxfc = 1;
3264                 txfc = 1;
3265                 hw->fc.current_mode = I40E_FC_FULL;
3266                 break;
3267         case I40E_AQ_LINK_PAUSE_RX:
3268                 rxfc = 1;
3269                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3270                 break;
3271         case I40E_AQ_LINK_PAUSE_TX:
3272                 txfc = 1;
3273                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3274                 break;
3275         default:
3276                 hw->fc.current_mode = I40E_FC_NONE;
3277                 break;
3278         }
3279
3280 write_reg:
3281         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3282                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3283         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3284         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3285         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3286         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3287
3288         return ret;
3289 }
3290
3291 /* PF setup */
3292 static int
3293 i40e_pf_setup(struct i40e_pf *pf)
3294 {
3295         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3296         struct i40e_filter_control_settings settings;
3297         struct i40e_vsi *vsi;
3298         int ret;
3299
3300         /* Clear all stats counters */
3301         pf->offset_loaded = FALSE;
3302         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3303         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3304
3305         ret = i40e_pf_get_switch_config(pf);
3306         if (ret != I40E_SUCCESS) {
3307                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3308                 return ret;
3309         }
3310         if (pf->flags & I40E_FLAG_FDIR) {
3311                 /* make queue allocated first, let FDIR use queue pair 0*/
3312                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3313                 if (ret != I40E_FDIR_QUEUE_ID) {
3314                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3315                                     " ret =%d", ret);
3316                         pf->flags &= ~I40E_FLAG_FDIR;
3317                 }
3318         }
3319         /*  main VSI setup */
3320         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3321         if (!vsi) {
3322                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3323                 return I40E_ERR_NOT_READY;
3324         }
3325         pf->main_vsi = vsi;
3326
3327         /* Configure filter control */
3328         memset(&settings, 0, sizeof(settings));
3329         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3330                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3331         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3332                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3333         else {
3334                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3335                                                 hw->func_caps.rss_table_size);
3336                 return I40E_ERR_PARAM;
3337         }
3338         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3339                         "size: %u\n", hw->func_caps.rss_table_size);
3340         pf->hash_lut_size = hw->func_caps.rss_table_size;
3341
3342         /* Enable ethtype and macvlan filters */
3343         settings.enable_ethtype = TRUE;
3344         settings.enable_macvlan = TRUE;
3345         ret = i40e_set_filter_control(hw, &settings);
3346         if (ret)
3347                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3348                                                                 ret);
3349
3350         /* Update flow control according to the auto negotiation */
3351         i40e_update_flow_control(hw);
3352
3353         return I40E_SUCCESS;
3354 }
3355
3356 int
3357 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3358 {
3359         uint32_t reg;
3360         uint16_t j;
3361
3362         /**
3363          * Set or clear TX Queue Disable flags,
3364          * which is required by hardware.
3365          */
3366         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3367         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3368
3369         /* Wait until the request is finished */
3370         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3371                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3372                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3373                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3374                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3375                                                         & 0x1))) {
3376                         break;
3377                 }
3378         }
3379         if (on) {
3380                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3381                         return I40E_SUCCESS; /* already on, skip next steps */
3382
3383                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3384                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3385         } else {
3386                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3387                         return I40E_SUCCESS; /* already off, skip next steps */
3388                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3389         }
3390         /* Write the register */
3391         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3392         /* Check the result */
3393         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3394                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3395                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3396                 if (on) {
3397                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3398                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3399                                 break;
3400                 } else {
3401                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3402                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3403                                 break;
3404                 }
3405         }
3406         /* Check if it is timeout */
3407         if (j >= I40E_CHK_Q_ENA_COUNT) {
3408                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3409                             (on ? "enable" : "disable"), q_idx);
3410                 return I40E_ERR_TIMEOUT;
3411         }
3412
3413         return I40E_SUCCESS;
3414 }
3415
3416 /* Swith on or off the tx queues */
3417 static int
3418 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3419 {
3420         struct rte_eth_dev_data *dev_data = pf->dev_data;
3421         struct i40e_tx_queue *txq;
3422         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3423         uint16_t i;
3424         int ret;
3425
3426         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3427                 txq = dev_data->tx_queues[i];
3428                 /* Don't operate the queue if not configured or
3429                  * if starting only per queue */
3430                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3431                         continue;
3432                 if (on)
3433                         ret = i40e_dev_tx_queue_start(dev, i);
3434                 else
3435                         ret = i40e_dev_tx_queue_stop(dev, i);
3436                 if ( ret != I40E_SUCCESS)
3437                         return ret;
3438         }
3439
3440         return I40E_SUCCESS;
3441 }
3442
3443 int
3444 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3445 {
3446         uint32_t reg;
3447         uint16_t j;
3448
3449         /* Wait until the request is finished */
3450         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3451                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3452                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3453                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3454                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3455                         break;
3456         }
3457
3458         if (on) {
3459                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3460                         return I40E_SUCCESS; /* Already on, skip next steps */
3461                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3462         } else {
3463                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3464                         return I40E_SUCCESS; /* Already off, skip next steps */
3465                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3466         }
3467
3468         /* Write the register */
3469         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3470         /* Check the result */
3471         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3472                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3473                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3474                 if (on) {
3475                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3476                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3477                                 break;
3478                 } else {
3479                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3480                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3481                                 break;
3482                 }
3483         }
3484
3485         /* Check if it is timeout */
3486         if (j >= I40E_CHK_Q_ENA_COUNT) {
3487                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3488                             (on ? "enable" : "disable"), q_idx);
3489                 return I40E_ERR_TIMEOUT;
3490         }
3491
3492         return I40E_SUCCESS;
3493 }
3494 /* Switch on or off the rx queues */
3495 static int
3496 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3497 {
3498         struct rte_eth_dev_data *dev_data = pf->dev_data;
3499         struct i40e_rx_queue *rxq;
3500         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3501         uint16_t i;
3502         int ret;
3503
3504         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3505                 rxq = dev_data->rx_queues[i];
3506                 /* Don't operate the queue if not configured or
3507                  * if starting only per queue */
3508                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3509                         continue;
3510                 if (on)
3511                         ret = i40e_dev_rx_queue_start(dev, i);
3512                 else
3513                         ret = i40e_dev_rx_queue_stop(dev, i);
3514                 if (ret != I40E_SUCCESS)
3515                         return ret;
3516         }
3517
3518         return I40E_SUCCESS;
3519 }
3520
3521 /* Switch on or off all the rx/tx queues */
3522 int
3523 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3524 {
3525         int ret;
3526
3527         if (on) {
3528                 /* enable rx queues before enabling tx queues */
3529                 ret = i40e_dev_switch_rx_queues(pf, on);
3530                 if (ret) {
3531                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3532                         return ret;
3533                 }
3534                 ret = i40e_dev_switch_tx_queues(pf, on);
3535         } else {
3536                 /* Stop tx queues before stopping rx queues */
3537                 ret = i40e_dev_switch_tx_queues(pf, on);
3538                 if (ret) {
3539                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3540                         return ret;
3541                 }
3542                 ret = i40e_dev_switch_rx_queues(pf, on);
3543         }
3544
3545         return ret;
3546 }
3547
3548 /* Initialize VSI for TX */
3549 static int
3550 i40e_dev_tx_init(struct i40e_pf *pf)
3551 {
3552         struct rte_eth_dev_data *data = pf->dev_data;
3553         uint16_t i;
3554         uint32_t ret = I40E_SUCCESS;
3555         struct i40e_tx_queue *txq;
3556
3557         for (i = 0; i < data->nb_tx_queues; i++) {
3558                 txq = data->tx_queues[i];
3559                 if (!txq || !txq->q_set)
3560                         continue;
3561                 ret = i40e_tx_queue_init(txq);
3562                 if (ret != I40E_SUCCESS)
3563                         break;
3564         }
3565
3566         return ret;
3567 }
3568
3569 /* Initialize VSI for RX */
3570 static int
3571 i40e_dev_rx_init(struct i40e_pf *pf)
3572 {
3573         struct rte_eth_dev_data *data = pf->dev_data;
3574         int ret = I40E_SUCCESS;
3575         uint16_t i;
3576         struct i40e_rx_queue *rxq;
3577
3578         i40e_pf_config_mq_rx(pf);
3579         for (i = 0; i < data->nb_rx_queues; i++) {
3580                 rxq = data->rx_queues[i];
3581                 if (!rxq || !rxq->q_set)
3582                         continue;
3583
3584                 ret = i40e_rx_queue_init(rxq);
3585                 if (ret != I40E_SUCCESS) {
3586                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3587                                     "initialization");
3588                         break;
3589                 }
3590         }
3591
3592         return ret;
3593 }
3594
3595 static int
3596 i40e_dev_rxtx_init(struct i40e_pf *pf)
3597 {
3598         int err;
3599
3600         err = i40e_dev_tx_init(pf);
3601         if (err) {
3602                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3603                 return err;
3604         }
3605         err = i40e_dev_rx_init(pf);
3606         if (err) {
3607                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3608                 return err;
3609         }
3610
3611         return err;
3612 }
3613
3614 static int
3615 i40e_vmdq_setup(struct rte_eth_dev *dev)
3616 {
3617         struct rte_eth_conf *conf = &dev->data->dev_conf;
3618         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3619         int i, err, conf_vsis, j, loop;
3620         struct i40e_vsi *vsi;
3621         struct i40e_vmdq_info *vmdq_info;
3622         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3623         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3624
3625         /*
3626          * Disable interrupt to avoid message from VF. Furthermore, it will
3627          * avoid race condition in VSI creation/destroy.
3628          */
3629         i40e_pf_disable_irq0(hw);
3630
3631         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3632                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3633                 return -ENOTSUP;
3634         }
3635
3636         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3637         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3638                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3639                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3640                         pf->max_nb_vmdq_vsi);
3641                 return -ENOTSUP;
3642         }
3643
3644         if (pf->vmdq != NULL) {
3645                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3646                 return 0;
3647         }
3648
3649         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3650                                 sizeof(*vmdq_info) * conf_vsis, 0);
3651
3652         if (pf->vmdq == NULL) {
3653                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3654                 return -ENOMEM;
3655         }
3656
3657         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3658
3659         /* Create VMDQ VSI */
3660         for (i = 0; i < conf_vsis; i++) {
3661                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3662                                 vmdq_conf->enable_loop_back);
3663                 if (vsi == NULL) {
3664                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3665                         err = -1;
3666                         goto err_vsi_setup;
3667                 }
3668                 vmdq_info = &pf->vmdq[i];
3669                 vmdq_info->pf = pf;
3670                 vmdq_info->vsi = vsi;
3671         }
3672         pf->nb_cfg_vmdq_vsi = conf_vsis;
3673
3674         /* Configure Vlan */
3675         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3676         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3677                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3678                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3679                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3680                                         vmdq_conf->pool_map[i].vlan_id, j);
3681
3682                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3683                                                 vmdq_conf->pool_map[i].vlan_id);
3684                                 if (err) {
3685                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3686                                         err = -1;
3687                                         goto err_vsi_setup;
3688                                 }
3689                         }
3690                 }
3691         }
3692
3693         i40e_pf_enable_irq0(hw);
3694
3695         return 0;
3696
3697 err_vsi_setup:
3698         for (i = 0; i < conf_vsis; i++)
3699                 if (pf->vmdq[i].vsi == NULL)
3700                         break;
3701                 else
3702                         i40e_vsi_release(pf->vmdq[i].vsi);
3703
3704         rte_free(pf->vmdq);
3705         pf->vmdq = NULL;
3706         i40e_pf_enable_irq0(hw);
3707         return err;
3708 }
3709
3710 static void
3711 i40e_stat_update_32(struct i40e_hw *hw,
3712                    uint32_t reg,
3713                    bool offset_loaded,
3714                    uint64_t *offset,
3715                    uint64_t *stat)
3716 {
3717         uint64_t new_data;
3718
3719         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3720         if (!offset_loaded)
3721                 *offset = new_data;
3722
3723         if (new_data >= *offset)
3724                 *stat = (uint64_t)(new_data - *offset);
3725         else
3726                 *stat = (uint64_t)((new_data +
3727                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3728 }
3729
3730 static void
3731 i40e_stat_update_48(struct i40e_hw *hw,
3732                    uint32_t hireg,
3733                    uint32_t loreg,
3734                    bool offset_loaded,
3735                    uint64_t *offset,
3736                    uint64_t *stat)
3737 {
3738         uint64_t new_data;
3739
3740         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3741         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3742                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3743
3744         if (!offset_loaded)
3745                 *offset = new_data;
3746
3747         if (new_data >= *offset)
3748                 *stat = new_data - *offset;
3749         else
3750                 *stat = (uint64_t)((new_data +
3751                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3752
3753         *stat &= I40E_48_BIT_MASK;
3754 }
3755
3756 /* Disable IRQ0 */
3757 void
3758 i40e_pf_disable_irq0(struct i40e_hw *hw)
3759 {
3760         /* Disable all interrupt types */
3761         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3762         I40E_WRITE_FLUSH(hw);
3763 }
3764
3765 /* Enable IRQ0 */
3766 void
3767 i40e_pf_enable_irq0(struct i40e_hw *hw)
3768 {
3769         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3770                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3771                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3772                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3773         I40E_WRITE_FLUSH(hw);
3774 }
3775
3776 static void
3777 i40e_pf_config_irq0(struct i40e_hw *hw)
3778 {
3779         /* read pending request and disable first */
3780         i40e_pf_disable_irq0(hw);
3781         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3782         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3783                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3784
3785         /* Link no queues with irq0 */
3786         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3787                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3788 }
3789
3790 static void
3791 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3792 {
3793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3795         int i;
3796         uint16_t abs_vf_id;
3797         uint32_t index, offset, val;
3798
3799         if (!pf->vfs)
3800                 return;
3801         /**
3802          * Try to find which VF trigger a reset, use absolute VF id to access
3803          * since the reg is global register.
3804          */
3805         for (i = 0; i < pf->vf_num; i++) {
3806                 abs_vf_id = hw->func_caps.vf_base_id + i;
3807                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3808                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3809                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3810                 /* VFR event occured */
3811                 if (val & (0x1 << offset)) {
3812                         int ret;
3813
3814                         /* Clear the event first */
3815                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3816                                                         (0x1 << offset));
3817                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3818                         /**
3819                          * Only notify a VF reset event occured,
3820                          * don't trigger another SW reset
3821                          */
3822                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3823                         if (ret != I40E_SUCCESS)
3824                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3825                 }
3826         }
3827 }
3828
3829 static void
3830 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3831 {
3832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3833         struct i40e_arq_event_info info;
3834         uint16_t pending, opcode;
3835         int ret;
3836
3837         info.buf_len = I40E_AQ_BUF_SZ;
3838         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3839         if (!info.msg_buf) {
3840                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3841                 return;
3842         }
3843
3844         pending = 1;
3845         while (pending) {
3846                 ret = i40e_clean_arq_element(hw, &info, &pending);
3847
3848                 if (ret != I40E_SUCCESS) {
3849                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3850                                     "aq_err: %u", hw->aq.asq_last_status);
3851                         break;
3852                 }
3853                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3854
3855                 switch (opcode) {
3856                 case i40e_aqc_opc_send_msg_to_pf:
3857                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3858                         i40e_pf_host_handle_vf_msg(dev,
3859                                         rte_le_to_cpu_16(info.desc.retval),
3860                                         rte_le_to_cpu_32(info.desc.cookie_high),
3861                                         rte_le_to_cpu_32(info.desc.cookie_low),
3862                                         info.msg_buf,
3863                                         info.msg_len);
3864                         break;
3865                 default:
3866                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3867                                     opcode);
3868                         break;
3869                 }
3870         }
3871         rte_free(info.msg_buf);
3872 }
3873
3874 /*
3875  * Interrupt handler is registered as the alarm callback for handling LSC
3876  * interrupt in a definite of time, in order to wait the NIC into a stable
3877  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3878  * no need for link down interrupt.
3879  */
3880 static void
3881 i40e_dev_interrupt_delayed_handler(void *param)
3882 {
3883         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885         uint32_t icr0;
3886
3887         /* read interrupt causes again */
3888         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3889
3890 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3891         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3892                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3893         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3894                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3895         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3896                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3897         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3898                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3899         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3900                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3901                                                                 "state\n");
3902         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3903                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3904         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3905                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3906 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3907
3908         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3909                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3910                 i40e_dev_handle_vfr_event(dev);
3911         }
3912         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3913                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3914                 i40e_dev_handle_aq_msg(dev);
3915         }
3916
3917         /* handle the link up interrupt in an alarm callback */
3918         i40e_dev_link_update(dev, 0);
3919         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3920
3921         i40e_pf_enable_irq0(hw);
3922         rte_intr_enable(&(dev->pci_dev->intr_handle));
3923 }
3924
3925 /**
3926  * Interrupt handler triggered by NIC  for handling
3927  * specific interrupt.
3928  *
3929  * @param handle
3930  *  Pointer to interrupt handle.
3931  * @param param
3932  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3933  *
3934  * @return
3935  *  void
3936  */
3937 static void
3938 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3939                            void *param)
3940 {
3941         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943         uint32_t icr0;
3944
3945         /* Disable interrupt */
3946         i40e_pf_disable_irq0(hw);
3947
3948         /* read out interrupt causes */
3949         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3950
3951         /* No interrupt event indicated */
3952         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3953                 PMD_DRV_LOG(INFO, "No interrupt event");
3954                 goto done;
3955         }
3956 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3957         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3958                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3959         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3960                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3961         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3962                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3963         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3964                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3965         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3966                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3967         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3968                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3969         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3970                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3971 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3972
3973         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3974                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3975                 i40e_dev_handle_vfr_event(dev);
3976         }
3977         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3978                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3979                 i40e_dev_handle_aq_msg(dev);
3980         }
3981
3982         /* Link Status Change interrupt */
3983         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3984 #define I40E_US_PER_SECOND 1000000
3985                 struct rte_eth_link link;
3986
3987                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3988                 memset(&link, 0, sizeof(link));
3989                 rte_i40e_dev_atomic_read_link_status(dev, &link);
3990                 i40e_dev_link_update(dev, 0);
3991
3992                 /*
3993                  * For link up interrupt, it needs to wait 1 second to let the
3994                  * hardware be a stable state. Otherwise several consecutive
3995                  * interrupts can be observed.
3996                  * For link down interrupt, no need to wait.
3997                  */
3998                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3999                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4000                         return;
4001                 else
4002                         _rte_eth_dev_callback_process(dev,
4003                                 RTE_ETH_EVENT_INTR_LSC);
4004         }
4005
4006 done:
4007         /* Enable interrupt */
4008         i40e_pf_enable_irq0(hw);
4009         rte_intr_enable(&(dev->pci_dev->intr_handle));
4010 }
4011
4012 static int
4013 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4014                          struct i40e_macvlan_filter *filter,
4015                          int total)
4016 {
4017         int ele_num, ele_buff_size;
4018         int num, actual_num, i;
4019         uint16_t flags;
4020         int ret = I40E_SUCCESS;
4021         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4022         struct i40e_aqc_add_macvlan_element_data *req_list;
4023
4024         if (filter == NULL  || total == 0)
4025                 return I40E_ERR_PARAM;
4026         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4027         ele_buff_size = hw->aq.asq_buf_size;
4028
4029         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4030         if (req_list == NULL) {
4031                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4032                 return I40E_ERR_NO_MEMORY;
4033         }
4034
4035         num = 0;
4036         do {
4037                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4038                 memset(req_list, 0, ele_buff_size);
4039
4040                 for (i = 0; i < actual_num; i++) {
4041                         (void)rte_memcpy(req_list[i].mac_addr,
4042                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4043                         req_list[i].vlan_tag =
4044                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4045
4046                         switch (filter[num + i].filter_type) {
4047                         case RTE_MAC_PERFECT_MATCH:
4048                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4049                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4050                                 break;
4051                         case RTE_MACVLAN_PERFECT_MATCH:
4052                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4053                                 break;
4054                         case RTE_MAC_HASH_MATCH:
4055                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4056                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4057                                 break;
4058                         case RTE_MACVLAN_HASH_MATCH:
4059                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4060                                 break;
4061                         default:
4062                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4063                                 ret = I40E_ERR_PARAM;
4064                                 goto DONE;
4065                         }
4066
4067                         req_list[i].queue_number = 0;
4068
4069                         req_list[i].flags = rte_cpu_to_le_16(flags);
4070                 }
4071
4072                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4073                                                 actual_num, NULL);
4074                 if (ret != I40E_SUCCESS) {
4075                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4076                         goto DONE;
4077                 }
4078                 num += actual_num;
4079         } while (num < total);
4080
4081 DONE:
4082         rte_free(req_list);
4083         return ret;
4084 }
4085
4086 static int
4087 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4088                             struct i40e_macvlan_filter *filter,
4089                             int total)
4090 {
4091         int ele_num, ele_buff_size;
4092         int num, actual_num, i;
4093         uint16_t flags;
4094         int ret = I40E_SUCCESS;
4095         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4096         struct i40e_aqc_remove_macvlan_element_data *req_list;
4097
4098         if (filter == NULL  || total == 0)
4099                 return I40E_ERR_PARAM;
4100
4101         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4102         ele_buff_size = hw->aq.asq_buf_size;
4103
4104         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4105         if (req_list == NULL) {
4106                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4107                 return I40E_ERR_NO_MEMORY;
4108         }
4109
4110         num = 0;
4111         do {
4112                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4113                 memset(req_list, 0, ele_buff_size);
4114
4115                 for (i = 0; i < actual_num; i++) {
4116                         (void)rte_memcpy(req_list[i].mac_addr,
4117                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4118                         req_list[i].vlan_tag =
4119                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4120
4121                         switch (filter[num + i].filter_type) {
4122                         case RTE_MAC_PERFECT_MATCH:
4123                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4124                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4125                                 break;
4126                         case RTE_MACVLAN_PERFECT_MATCH:
4127                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4128                                 break;
4129                         case RTE_MAC_HASH_MATCH:
4130                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4131                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4132                                 break;
4133                         case RTE_MACVLAN_HASH_MATCH:
4134                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4135                                 break;
4136                         default:
4137                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4138                                 ret = I40E_ERR_PARAM;
4139                                 goto DONE;
4140                         }
4141                         req_list[i].flags = rte_cpu_to_le_16(flags);
4142                 }
4143
4144                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4145                                                 actual_num, NULL);
4146                 if (ret != I40E_SUCCESS) {
4147                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4148                         goto DONE;
4149                 }
4150                 num += actual_num;
4151         } while (num < total);
4152
4153 DONE:
4154         rte_free(req_list);
4155         return ret;
4156 }
4157
4158 /* Find out specific MAC filter */
4159 static struct i40e_mac_filter *
4160 i40e_find_mac_filter(struct i40e_vsi *vsi,
4161                          struct ether_addr *macaddr)
4162 {
4163         struct i40e_mac_filter *f;
4164
4165         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4166                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4167                         return f;
4168         }
4169
4170         return NULL;
4171 }
4172
4173 static bool
4174 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4175                          uint16_t vlan_id)
4176 {
4177         uint32_t vid_idx, vid_bit;
4178
4179         if (vlan_id > ETH_VLAN_ID_MAX)
4180                 return 0;
4181
4182         vid_idx = I40E_VFTA_IDX(vlan_id);
4183         vid_bit = I40E_VFTA_BIT(vlan_id);
4184
4185         if (vsi->vfta[vid_idx] & vid_bit)
4186                 return 1;
4187         else
4188                 return 0;
4189 }
4190
4191 static void
4192 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4193                          uint16_t vlan_id, bool on)
4194 {
4195         uint32_t vid_idx, vid_bit;
4196
4197         if (vlan_id > ETH_VLAN_ID_MAX)
4198                 return;
4199
4200         vid_idx = I40E_VFTA_IDX(vlan_id);
4201         vid_bit = I40E_VFTA_BIT(vlan_id);
4202
4203         if (on)
4204                 vsi->vfta[vid_idx] |= vid_bit;
4205         else
4206                 vsi->vfta[vid_idx] &= ~vid_bit;
4207 }
4208
4209 /**
4210  * Find all vlan options for specific mac addr,
4211  * return with actual vlan found.
4212  */
4213 static inline int
4214 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4215                            struct i40e_macvlan_filter *mv_f,
4216                            int num, struct ether_addr *addr)
4217 {
4218         int i;
4219         uint32_t j, k;
4220
4221         /**
4222          * Not to use i40e_find_vlan_filter to decrease the loop time,
4223          * although the code looks complex.
4224           */
4225         if (num < vsi->vlan_num)
4226                 return I40E_ERR_PARAM;
4227
4228         i = 0;
4229         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4230                 if (vsi->vfta[j]) {
4231                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4232                                 if (vsi->vfta[j] & (1 << k)) {
4233                                         if (i > num - 1) {
4234                                                 PMD_DRV_LOG(ERR, "vlan number "
4235                                                             "not match");
4236                                                 return I40E_ERR_PARAM;
4237                                         }
4238                                         (void)rte_memcpy(&mv_f[i].macaddr,
4239                                                         addr, ETH_ADDR_LEN);
4240                                         mv_f[i].vlan_id =
4241                                                 j * I40E_UINT32_BIT_SIZE + k;
4242                                         i++;
4243                                 }
4244                         }
4245                 }
4246         }
4247         return I40E_SUCCESS;
4248 }
4249
4250 static inline int
4251 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4252                            struct i40e_macvlan_filter *mv_f,
4253                            int num,
4254                            uint16_t vlan)
4255 {
4256         int i = 0;
4257         struct i40e_mac_filter *f;
4258
4259         if (num < vsi->mac_num)
4260                 return I40E_ERR_PARAM;
4261
4262         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4263                 if (i > num - 1) {
4264                         PMD_DRV_LOG(ERR, "buffer number not match");
4265                         return I40E_ERR_PARAM;
4266                 }
4267                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4268                                 ETH_ADDR_LEN);
4269                 mv_f[i].vlan_id = vlan;
4270                 mv_f[i].filter_type = f->mac_info.filter_type;
4271                 i++;
4272         }
4273
4274         return I40E_SUCCESS;
4275 }
4276
4277 static int
4278 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4279 {
4280         int i, num;
4281         struct i40e_mac_filter *f;
4282         struct i40e_macvlan_filter *mv_f;
4283         int ret = I40E_SUCCESS;
4284
4285         if (vsi == NULL || vsi->mac_num == 0)
4286                 return I40E_ERR_PARAM;
4287
4288         /* Case that no vlan is set */
4289         if (vsi->vlan_num == 0)
4290                 num = vsi->mac_num;
4291         else
4292                 num = vsi->mac_num * vsi->vlan_num;
4293
4294         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4295         if (mv_f == NULL) {
4296                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4297                 return I40E_ERR_NO_MEMORY;
4298         }
4299
4300         i = 0;
4301         if (vsi->vlan_num == 0) {
4302                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4303                         (void)rte_memcpy(&mv_f[i].macaddr,
4304                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4305                         mv_f[i].vlan_id = 0;
4306                         i++;
4307                 }
4308         } else {
4309                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4310                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4311                                         vsi->vlan_num, &f->mac_info.mac_addr);
4312                         if (ret != I40E_SUCCESS)
4313                                 goto DONE;
4314                         i += vsi->vlan_num;
4315                 }
4316         }
4317
4318         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4319 DONE:
4320         rte_free(mv_f);
4321
4322         return ret;
4323 }
4324
4325 int
4326 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4327 {
4328         struct i40e_macvlan_filter *mv_f;
4329         int mac_num;
4330         int ret = I40E_SUCCESS;
4331
4332         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4333                 return I40E_ERR_PARAM;
4334
4335         /* If it's already set, just return */
4336         if (i40e_find_vlan_filter(vsi,vlan))
4337                 return I40E_SUCCESS;
4338
4339         mac_num = vsi->mac_num;
4340
4341         if (mac_num == 0) {
4342                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4343                 return I40E_ERR_PARAM;
4344         }
4345
4346         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4347
4348         if (mv_f == NULL) {
4349                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4350                 return I40E_ERR_NO_MEMORY;
4351         }
4352
4353         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4354
4355         if (ret != I40E_SUCCESS)
4356                 goto DONE;
4357
4358         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4359
4360         if (ret != I40E_SUCCESS)
4361                 goto DONE;
4362
4363         i40e_set_vlan_filter(vsi, vlan, 1);
4364
4365         vsi->vlan_num++;
4366         ret = I40E_SUCCESS;
4367 DONE:
4368         rte_free(mv_f);
4369         return ret;
4370 }
4371
4372 int
4373 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4374 {
4375         struct i40e_macvlan_filter *mv_f;
4376         int mac_num;
4377         int ret = I40E_SUCCESS;
4378
4379         /**
4380          * Vlan 0 is the generic filter for untagged packets
4381          * and can't be removed.
4382          */
4383         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4384                 return I40E_ERR_PARAM;
4385
4386         /* If can't find it, just return */
4387         if (!i40e_find_vlan_filter(vsi, vlan))
4388                 return I40E_ERR_PARAM;
4389
4390         mac_num = vsi->mac_num;
4391
4392         if (mac_num == 0) {
4393                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4394                 return I40E_ERR_PARAM;
4395         }
4396
4397         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4398
4399         if (mv_f == NULL) {
4400                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4401                 return I40E_ERR_NO_MEMORY;
4402         }
4403
4404         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4405
4406         if (ret != I40E_SUCCESS)
4407                 goto DONE;
4408
4409         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4410
4411         if (ret != I40E_SUCCESS)
4412                 goto DONE;
4413
4414         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4415         if (vsi->vlan_num == 1) {
4416                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4417                 if (ret != I40E_SUCCESS)
4418                         goto DONE;
4419
4420                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4421                 if (ret != I40E_SUCCESS)
4422                         goto DONE;
4423         }
4424
4425         i40e_set_vlan_filter(vsi, vlan, 0);
4426
4427         vsi->vlan_num--;
4428         ret = I40E_SUCCESS;
4429 DONE:
4430         rte_free(mv_f);
4431         return ret;
4432 }
4433
4434 int
4435 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4436 {
4437         struct i40e_mac_filter *f;
4438         struct i40e_macvlan_filter *mv_f;
4439         int i, vlan_num = 0;
4440         int ret = I40E_SUCCESS;
4441
4442         /* If it's add and we've config it, return */
4443         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4444         if (f != NULL)
4445                 return I40E_SUCCESS;
4446         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4447                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4448
4449                 /**
4450                  * If vlan_num is 0, that's the first time to add mac,
4451                  * set mask for vlan_id 0.
4452                  */
4453                 if (vsi->vlan_num == 0) {
4454                         i40e_set_vlan_filter(vsi, 0, 1);
4455                         vsi->vlan_num = 1;
4456                 }
4457                 vlan_num = vsi->vlan_num;
4458         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4459                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4460                 vlan_num = 1;
4461
4462         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4463         if (mv_f == NULL) {
4464                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4465                 return I40E_ERR_NO_MEMORY;
4466         }
4467
4468         for (i = 0; i < vlan_num; i++) {
4469                 mv_f[i].filter_type = mac_filter->filter_type;
4470                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4471                                 ETH_ADDR_LEN);
4472         }
4473
4474         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4475                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4476                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4477                                         &mac_filter->mac_addr);
4478                 if (ret != I40E_SUCCESS)
4479                         goto DONE;
4480         }
4481
4482         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4483         if (ret != I40E_SUCCESS)
4484                 goto DONE;
4485
4486         /* Add the mac addr into mac list */
4487         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4488         if (f == NULL) {
4489                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4490                 ret = I40E_ERR_NO_MEMORY;
4491                 goto DONE;
4492         }
4493         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4494                         ETH_ADDR_LEN);
4495         f->mac_info.filter_type = mac_filter->filter_type;
4496         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4497         vsi->mac_num++;
4498
4499         ret = I40E_SUCCESS;
4500 DONE:
4501         rte_free(mv_f);
4502
4503         return ret;
4504 }
4505
4506 int
4507 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4508 {
4509         struct i40e_mac_filter *f;
4510         struct i40e_macvlan_filter *mv_f;
4511         int i, vlan_num;
4512         enum rte_mac_filter_type filter_type;
4513         int ret = I40E_SUCCESS;
4514
4515         /* Can't find it, return an error */
4516         f = i40e_find_mac_filter(vsi, addr);
4517         if (f == NULL)
4518                 return I40E_ERR_PARAM;
4519
4520         vlan_num = vsi->vlan_num;
4521         filter_type = f->mac_info.filter_type;
4522         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4523                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4524                 if (vlan_num == 0) {
4525                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4526                         return I40E_ERR_PARAM;
4527                 }
4528         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4529                         filter_type == RTE_MAC_HASH_MATCH)
4530                 vlan_num = 1;
4531
4532         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4533         if (mv_f == NULL) {
4534                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4535                 return I40E_ERR_NO_MEMORY;
4536         }
4537
4538         for (i = 0; i < vlan_num; i++) {
4539                 mv_f[i].filter_type = filter_type;
4540                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4541                                 ETH_ADDR_LEN);
4542         }
4543         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4544                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4545                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4546                 if (ret != I40E_SUCCESS)
4547                         goto DONE;
4548         }
4549
4550         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4551         if (ret != I40E_SUCCESS)
4552                 goto DONE;
4553
4554         /* Remove the mac addr into mac list */
4555         TAILQ_REMOVE(&vsi->mac_list, f, next);
4556         rte_free(f);
4557         vsi->mac_num--;
4558
4559         ret = I40E_SUCCESS;
4560 DONE:
4561         rte_free(mv_f);
4562         return ret;
4563 }
4564
4565 /* Configure hash enable flags for RSS */
4566 uint64_t
4567 i40e_config_hena(uint64_t flags)
4568 {
4569         uint64_t hena = 0;
4570
4571         if (!flags)
4572                 return hena;
4573
4574         if (flags & ETH_RSS_NONF_IPV4_UDP)
4575                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4576         if (flags & ETH_RSS_NONF_IPV4_TCP)
4577                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4578         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4580         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4581                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4582         if (flags & ETH_RSS_FRAG_IPV4)
4583                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4584         if (flags & ETH_RSS_NONF_IPV6_UDP)
4585                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4586         if (flags & ETH_RSS_NONF_IPV6_TCP)
4587                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4588         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4589                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4590         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4591                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4592         if (flags & ETH_RSS_FRAG_IPV6)
4593                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4594         if (flags & ETH_RSS_L2_PAYLOAD)
4595                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4596
4597         return hena;
4598 }
4599
4600 /* Parse the hash enable flags */
4601 uint64_t
4602 i40e_parse_hena(uint64_t flags)
4603 {
4604         uint64_t rss_hf = 0;
4605
4606         if (!flags)
4607                 return rss_hf;
4608
4609         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4610                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4611         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4612                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4613         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4614                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4615         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4616                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4617         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4618                 rss_hf |= ETH_RSS_FRAG_IPV4;
4619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4620                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4622                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4623         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4624                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4626                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4627         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4628                 rss_hf |= ETH_RSS_FRAG_IPV6;
4629         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4630                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4631
4632         return rss_hf;
4633 }
4634
4635 /* Disable RSS */
4636 static void
4637 i40e_pf_disable_rss(struct i40e_pf *pf)
4638 {
4639         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4640         uint64_t hena;
4641
4642         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4643         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4644         hena &= ~I40E_RSS_HENA_ALL;
4645         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4646         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4647         I40E_WRITE_FLUSH(hw);
4648 }
4649
4650 static int
4651 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4652 {
4653         uint32_t *hash_key;
4654         uint8_t hash_key_len;
4655         uint64_t rss_hf;
4656         uint16_t i;
4657         uint64_t hena;
4658
4659         hash_key = (uint32_t *)(rss_conf->rss_key);
4660         hash_key_len = rss_conf->rss_key_len;
4661         if (hash_key != NULL && hash_key_len >=
4662                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4663                 /* Fill in RSS hash key */
4664                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4665                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4666         }
4667
4668         rss_hf = rss_conf->rss_hf;
4669         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4670         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4671         hena &= ~I40E_RSS_HENA_ALL;
4672         hena |= i40e_config_hena(rss_hf);
4673         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4674         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4675         I40E_WRITE_FLUSH(hw);
4676
4677         return 0;
4678 }
4679
4680 static int
4681 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4682                          struct rte_eth_rss_conf *rss_conf)
4683 {
4684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4686         uint64_t hena;
4687
4688         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4689         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4690         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4691                 if (rss_hf != 0) /* Enable RSS */
4692                         return -EINVAL;
4693                 return 0; /* Nothing to do */
4694         }
4695         /* RSS enabled */
4696         if (rss_hf == 0) /* Disable RSS */
4697                 return -EINVAL;
4698
4699         return i40e_hw_rss_hash_set(hw, rss_conf);
4700 }
4701
4702 static int
4703 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4704                            struct rte_eth_rss_conf *rss_conf)
4705 {
4706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4708         uint64_t hena;
4709         uint16_t i;
4710
4711         if (hash_key != NULL) {
4712                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4713                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4714                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4715         }
4716         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4717         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4718         rss_conf->rss_hf = i40e_parse_hena(hena);
4719
4720         return 0;
4721 }
4722
4723 static int
4724 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4725 {
4726         switch (filter_type) {
4727         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4728                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4729                 break;
4730         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4731                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4732                 break;
4733         case RTE_TUNNEL_FILTER_IMAC_TENID:
4734                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4735                 break;
4736         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4737                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4738                 break;
4739         case ETH_TUNNEL_FILTER_IMAC:
4740                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4741                 break;
4742         default:
4743                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4744                 return -EINVAL;
4745         }
4746
4747         return 0;
4748 }
4749
4750 static int
4751 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4752                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4753                         uint8_t add)
4754 {
4755         uint16_t ip_type;
4756         uint8_t tun_type = 0;
4757         int val, ret = 0;
4758         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4759         struct i40e_vsi *vsi = pf->main_vsi;
4760         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4761         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4762
4763         cld_filter = rte_zmalloc("tunnel_filter",
4764                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4765                 0);
4766
4767         if (NULL == cld_filter) {
4768                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4769                 return -EINVAL;
4770         }
4771         pfilter = cld_filter;
4772
4773         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4774                         sizeof(struct ether_addr));
4775         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4776                         sizeof(struct ether_addr));
4777
4778         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4779         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4780                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4781                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4782                                 &tunnel_filter->ip_addr,
4783                                 sizeof(pfilter->ipaddr.v4.data));
4784         } else {
4785                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4786                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4787                                 &tunnel_filter->ip_addr,
4788                                 sizeof(pfilter->ipaddr.v6.data));
4789         }
4790
4791         /* check tunneled type */
4792         switch (tunnel_filter->tunnel_type) {
4793         case RTE_TUNNEL_TYPE_VXLAN:
4794                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4795                 break;
4796         default:
4797                 /* Other tunnel types is not supported. */
4798                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4799                 rte_free(cld_filter);
4800                 return -EINVAL;
4801         }
4802
4803         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4804                                                 &pfilter->flags);
4805         if (val < 0) {
4806                 rte_free(cld_filter);
4807                 return -EINVAL;
4808         }
4809
4810         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4811                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4812         pfilter->tenant_id = tunnel_filter->tenant_id;
4813         pfilter->queue_number = tunnel_filter->queue_id;
4814
4815         if (add)
4816                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4817         else
4818                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4819                                                 cld_filter, 1);
4820
4821         rte_free(cld_filter);
4822         return ret;
4823 }
4824
4825 static int
4826 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4827 {
4828         uint8_t i;
4829
4830         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4831                 if (pf->vxlan_ports[i] == port)
4832                         return i;
4833         }
4834
4835         return -1;
4836 }
4837
4838 static int
4839 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4840 {
4841         int  idx, ret;
4842         uint8_t filter_idx;
4843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4844
4845         idx = i40e_get_vxlan_port_idx(pf, port);
4846
4847         /* Check if port already exists */
4848         if (idx >= 0) {
4849                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4850                 return -EINVAL;
4851         }
4852
4853         /* Now check if there is space to add the new port */
4854         idx = i40e_get_vxlan_port_idx(pf, 0);
4855         if (idx < 0) {
4856                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4857                         "not adding port %d", port);
4858                 return -ENOSPC;
4859         }
4860
4861         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4862                                         &filter_idx, NULL);
4863         if (ret < 0) {
4864                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4865                 return -1;
4866         }
4867
4868         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4869                          port,  filter_idx);
4870
4871         /* New port: add it and mark its index in the bitmap */
4872         pf->vxlan_ports[idx] = port;
4873         pf->vxlan_bitmap |= (1 << idx);
4874
4875         if (!(pf->flags & I40E_FLAG_VXLAN))
4876                 pf->flags |= I40E_FLAG_VXLAN;
4877
4878         return 0;
4879 }
4880
4881 static int
4882 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4883 {
4884         int idx;
4885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4886
4887         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4888                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4889                 return -EINVAL;
4890         }
4891
4892         idx = i40e_get_vxlan_port_idx(pf, port);
4893
4894         if (idx < 0) {
4895                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4896                 return -EINVAL;
4897         }
4898
4899         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4900                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4901                 return -1;
4902         }
4903
4904         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4905                         port, idx);
4906
4907         pf->vxlan_ports[idx] = 0;
4908         pf->vxlan_bitmap &= ~(1 << idx);
4909
4910         if (!pf->vxlan_bitmap)
4911                 pf->flags &= ~I40E_FLAG_VXLAN;
4912
4913         return 0;
4914 }
4915
4916 /* Add UDP tunneling port */
4917 static int
4918 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4919                         struct rte_eth_udp_tunnel *udp_tunnel)
4920 {
4921         int ret = 0;
4922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4923
4924         if (udp_tunnel == NULL)
4925                 return -EINVAL;
4926
4927         switch (udp_tunnel->prot_type) {
4928         case RTE_TUNNEL_TYPE_VXLAN:
4929                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4930                 break;
4931
4932         case RTE_TUNNEL_TYPE_GENEVE:
4933         case RTE_TUNNEL_TYPE_TEREDO:
4934                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4935                 ret = -1;
4936                 break;
4937
4938         default:
4939                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4940                 ret = -1;
4941                 break;
4942         }
4943
4944         return ret;
4945 }
4946
4947 /* Remove UDP tunneling port */
4948 static int
4949 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4950                         struct rte_eth_udp_tunnel *udp_tunnel)
4951 {
4952         int ret = 0;
4953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4954
4955         if (udp_tunnel == NULL)
4956                 return -EINVAL;
4957
4958         switch (udp_tunnel->prot_type) {
4959         case RTE_TUNNEL_TYPE_VXLAN:
4960                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4961                 break;
4962         case RTE_TUNNEL_TYPE_GENEVE:
4963         case RTE_TUNNEL_TYPE_TEREDO:
4964                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4965                 ret = -1;
4966                 break;
4967         default:
4968                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4969                 ret = -1;
4970                 break;
4971         }
4972
4973         return ret;
4974 }
4975
4976 /* Calculate the maximum number of contiguous PF queues that are configured */
4977 static int
4978 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4979 {
4980         struct rte_eth_dev_data *data = pf->dev_data;
4981         int i, num;
4982         struct i40e_rx_queue *rxq;
4983
4984         num = 0;
4985         for (i = 0; i < pf->lan_nb_qps; i++) {
4986                 rxq = data->rx_queues[i];
4987                 if (rxq && rxq->q_set)
4988                         num++;
4989                 else
4990                         break;
4991         }
4992
4993         return num;
4994 }
4995
4996 /* Configure RSS */
4997 static int
4998 i40e_pf_config_rss(struct i40e_pf *pf)
4999 {
5000         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5001         struct rte_eth_rss_conf rss_conf;
5002         uint32_t i, lut = 0;
5003         uint16_t j, num;
5004
5005         /*
5006          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5007          * It's necessary to calulate the actual PF queues that are configured.
5008          */
5009         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5010                 num = i40e_pf_calc_configured_queues_num(pf);
5011                 num = i40e_align_floor(num);
5012         } else
5013                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5014
5015         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5016                         num);
5017
5018         if (num == 0) {
5019                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5020                 return -ENOTSUP;
5021         }
5022
5023         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5024                 if (j == num)
5025                         j = 0;
5026                 lut = (lut << 8) | (j & ((0x1 <<
5027                         hw->func_caps.rss_table_entry_width) - 1));
5028                 if ((i & 3) == 3)
5029                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5030         }
5031
5032         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5033         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5034                 i40e_pf_disable_rss(pf);
5035                 return 0;
5036         }
5037         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5038                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5039                 /* Random default keys */
5040                 static uint32_t rss_key_default[] = {0x6b793944,
5041                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5042                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5043                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5044
5045                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5046                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5047                                                         sizeof(uint32_t);
5048         }
5049
5050         return i40e_hw_rss_hash_set(hw, &rss_conf);
5051 }
5052
5053 static int
5054 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5055                         struct rte_eth_tunnel_filter_conf *filter)
5056 {
5057         if (pf == NULL || filter == NULL) {
5058                 PMD_DRV_LOG(ERR, "Invalid parameter");
5059                 return -EINVAL;
5060         }
5061
5062         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5063                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5064                 return -EINVAL;
5065         }
5066
5067         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5068                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5069                 return -EINVAL;
5070         }
5071
5072         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5073                 (is_zero_ether_addr(filter->outer_mac))) {
5074                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5075                 return -EINVAL;
5076         }
5077
5078         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5079                 (is_zero_ether_addr(filter->inner_mac))) {
5080                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5081                 return -EINVAL;
5082         }
5083
5084         return 0;
5085 }
5086
5087 static int
5088 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5089                         void *arg)
5090 {
5091         struct rte_eth_tunnel_filter_conf *filter;
5092         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5093         int ret = I40E_SUCCESS;
5094
5095         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5096
5097         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5098                 return I40E_ERR_PARAM;
5099
5100         switch (filter_op) {
5101         case RTE_ETH_FILTER_NOP:
5102                 if (!(pf->flags & I40E_FLAG_VXLAN))
5103                         ret = I40E_NOT_SUPPORTED;
5104         case RTE_ETH_FILTER_ADD:
5105                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5106                 break;
5107         case RTE_ETH_FILTER_DELETE:
5108                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5109                 break;
5110         default:
5111                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5112                 ret = I40E_ERR_PARAM;
5113                 break;
5114         }
5115
5116         return ret;
5117 }
5118
5119 static int
5120 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5121 {
5122         int ret = 0;
5123         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5124
5125         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5126                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5127                 return -ENOTSUP;
5128         }
5129
5130         /* RSS setup */
5131         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5132                 ret = i40e_pf_config_rss(pf);
5133         else
5134                 i40e_pf_disable_rss(pf);
5135
5136         return ret;
5137 }
5138
5139 /*
5140  * Configure ethertype filter, which can director packet by filtering
5141  * with mac address and ether_type or only ether_type
5142  */
5143 static int
5144 i40e_ethertype_filter_set(struct i40e_pf *pf,
5145                         struct rte_eth_ethertype_filter *filter,
5146                         bool add)
5147 {
5148         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5149         struct i40e_control_filter_stats stats;
5150         uint16_t flags = 0;
5151         int ret;
5152
5153         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5154                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5155                 return -EINVAL;
5156         }
5157         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5158                 filter->ether_type == ETHER_TYPE_IPv6) {
5159                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5160                         " control packet filter.", filter->ether_type);
5161                 return -EINVAL;
5162         }
5163         if (filter->ether_type == ETHER_TYPE_VLAN)
5164                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5165                         " not supported.");
5166
5167         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5168                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5169         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5170                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5171         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5172
5173         memset(&stats, 0, sizeof(stats));
5174         ret = i40e_aq_add_rem_control_packet_filter(hw,
5175                         filter->mac_addr.addr_bytes,
5176                         filter->ether_type, flags,
5177                         pf->main_vsi->seid,
5178                         filter->queue, add, &stats, NULL);
5179
5180         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5181                          " mac_etype_used = %u, etype_used = %u,"
5182                          " mac_etype_free = %u, etype_free = %u\n",
5183                          ret, stats.mac_etype_used, stats.etype_used,
5184                          stats.mac_etype_free, stats.etype_free);
5185         if (ret < 0)
5186                 return -ENOSYS;
5187         return 0;
5188 }
5189
5190 /*
5191  * Handle operations for ethertype filter.
5192  */
5193 static int
5194 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5195                                 enum rte_filter_op filter_op,
5196                                 void *arg)
5197 {
5198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5199         int ret = 0;
5200
5201         if (filter_op == RTE_ETH_FILTER_NOP)
5202                 return ret;
5203
5204         if (arg == NULL) {
5205                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5206                             filter_op);
5207                 return -EINVAL;
5208         }
5209
5210         switch (filter_op) {
5211         case RTE_ETH_FILTER_ADD:
5212                 ret = i40e_ethertype_filter_set(pf,
5213                         (struct rte_eth_ethertype_filter *)arg,
5214                         TRUE);
5215                 break;
5216         case RTE_ETH_FILTER_DELETE:
5217                 ret = i40e_ethertype_filter_set(pf,
5218                         (struct rte_eth_ethertype_filter *)arg,
5219                         FALSE);
5220                 break;
5221         default:
5222                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5223                 ret = -ENOSYS;
5224                 break;
5225         }
5226         return ret;
5227 }
5228
5229 static int
5230 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5231                      enum rte_filter_type filter_type,
5232                      enum rte_filter_op filter_op,
5233                      void *arg)
5234 {
5235         int ret = 0;
5236
5237         if (dev == NULL)
5238                 return -EINVAL;
5239
5240         switch (filter_type) {
5241         case RTE_ETH_FILTER_MACVLAN:
5242                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5243                 break;
5244         case RTE_ETH_FILTER_ETHERTYPE:
5245                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5246                 break;
5247         case RTE_ETH_FILTER_TUNNEL:
5248                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5249                 break;
5250         case RTE_ETH_FILTER_FDIR:
5251                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5252                 break;
5253         default:
5254                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5255                                                         filter_type);
5256                 ret = -EINVAL;
5257                 break;
5258         }
5259
5260         return ret;
5261 }
5262
5263 enum i40e_filter_pctype
5264 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5265 {
5266         static const enum i40e_filter_pctype pctype_table[] = {
5267                 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5268                 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5269                 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5270                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5271                                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5272                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5273                                         I40E_FILTER_PCTYPE_FRAG_IPV4,
5274                 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5275                 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5276                 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5277                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5278                                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5279                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5280                                         I40E_FILTER_PCTYPE_FRAG_IPV6,
5281         };
5282
5283         return pctype_table[flow_type];
5284 }
5285
5286 enum rte_eth_flow_type
5287 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5288 {
5289         static const enum rte_eth_flow_type flowtype_table[] = {
5290                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5291                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5292                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5293                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5294                                         RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5295                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5296                                         RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5297                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5298                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5299                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5300                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5301                                         RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5302                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5303                                         RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5304         };
5305
5306         return flowtype_table[pctype];
5307 }
5308
5309 static int
5310 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5311 {
5312         struct i40e_aq_desc desc;
5313         enum i40e_status_code status;
5314
5315         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5316         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5317         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5318         if (status < 0)
5319                 return status;
5320
5321         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5322                                         (CHAR_BIT * sizeof(uint32_t))) +
5323                                 rte_le_to_cpu_32(desc.params.internal.param3);
5324
5325         return status;
5326 }
5327
5328 /*
5329  * On X710, performance number is far from the expectation on recent firmware
5330  * versions. The fix for this issue may not be integrated in the following
5331  * firmware version. So the workaround in software driver is needed. It needs
5332  * to modify the initial values of 3 internal only registers. Note that the
5333  * workaround can be removed when it is fixed in firmware in the future.
5334  */
5335 static void
5336 i40e_configure_registers(struct i40e_hw *hw)
5337 {
5338 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5339 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5340 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5341 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5342 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5343 #define I40E_GL_SWR_PM_UP_THR_VALUE      0x03030303
5344
5345         static const struct {
5346                 uint32_t addr;
5347                 uint64_t val;
5348         } reg_table[] = {
5349                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5350                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5351                 {I40E_GL_SWR_PM_UP_THR, I40E_GL_SWR_PM_UP_THR_VALUE},
5352         };
5353         uint64_t reg;
5354         uint32_t i;
5355         int ret;
5356
5357         /* Below fix is for X710 only */
5358         if (i40e_is_40G_device(hw->device_id))
5359                 return;
5360
5361         for (i = 0; i < RTE_DIM(reg_table); i++) {
5362                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5363                 if (ret < 0) {
5364                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5365                                                         reg_table[i].addr);
5366                         break;
5367                 }
5368                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5369                                                 reg_table[i].addr, reg);
5370                 if (reg == reg_table[i].val)
5371                         continue;
5372
5373                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5374                                                 reg_table[i].val, NULL);
5375                 if (ret < 0) {
5376                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5377                                 "address of 0x%"PRIx32, reg_table[i].val,
5378                                                         reg_table[i].addr);
5379                         break;
5380                 }
5381                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5382                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5383         }
5384 }