4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds*/
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 static int eth_i40e_dev_init(\
97 __attribute__((unused)) struct eth_driver *eth_drv,
98 struct rte_eth_dev *eth_dev);
99 static int i40e_dev_configure(struct rte_eth_dev *dev);
100 static int i40e_dev_start(struct rte_eth_dev *dev);
101 static void i40e_dev_stop(struct rte_eth_dev *dev);
102 static void i40e_dev_close(struct rte_eth_dev *dev);
103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
110 struct rte_eth_stats *stats);
111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
117 struct rte_eth_dev_info *dev_info);
118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
130 struct rte_eth_fc_conf *fc_conf);
131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_pfc_conf *pfc_conf);
133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
134 struct ether_addr *mac_addr,
137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
139 struct rte_eth_rss_reta_entry64 *reta_conf,
141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
142 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40e_get_cap(struct i40e_hw *hw);
146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
147 static int i40e_pf_setup(struct i40e_pf *pf);
148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
151 bool offset_loaded, uint64_t *offset, uint64_t *stat);
152 static void i40e_stat_update_48(struct i40e_hw *hw,
158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
159 static void i40e_dev_interrupt_handler(
160 __rte_unused struct rte_intr_handle *handle, void *param);
161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
162 uint32_t base, uint32_t num);
163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
169 static int i40e_veb_release(struct i40e_veb *veb);
170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
171 struct i40e_vsi *vsi);
172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
175 struct i40e_macvlan_filter *mv_f,
177 struct ether_addr *addr);
178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
179 struct i40e_macvlan_filter *mv_f,
182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
184 struct rte_eth_rss_conf *rss_conf);
185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
186 struct rte_eth_rss_conf *rss_conf);
187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
188 struct rte_eth_udp_tunnel *udp_tunnel);
189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
190 struct rte_eth_udp_tunnel *udp_tunnel);
191 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
192 enum rte_filter_type filter_type,
193 enum rte_filter_op filter_op,
196 /* Default hash key buffer for RSS */
197 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
199 static struct rte_pci_id pci_id_i40e_map[] = {
200 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
201 #include "rte_pci_dev_ids.h"
202 { .vendor_id = 0, /* sentinel */ },
205 static struct eth_dev_ops i40e_eth_dev_ops = {
206 .dev_configure = i40e_dev_configure,
207 .dev_start = i40e_dev_start,
208 .dev_stop = i40e_dev_stop,
209 .dev_close = i40e_dev_close,
210 .promiscuous_enable = i40e_dev_promiscuous_enable,
211 .promiscuous_disable = i40e_dev_promiscuous_disable,
212 .allmulticast_enable = i40e_dev_allmulticast_enable,
213 .allmulticast_disable = i40e_dev_allmulticast_disable,
214 .dev_set_link_up = i40e_dev_set_link_up,
215 .dev_set_link_down = i40e_dev_set_link_down,
216 .link_update = i40e_dev_link_update,
217 .stats_get = i40e_dev_stats_get,
218 .stats_reset = i40e_dev_stats_reset,
219 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
220 .dev_infos_get = i40e_dev_info_get,
221 .vlan_filter_set = i40e_vlan_filter_set,
222 .vlan_tpid_set = i40e_vlan_tpid_set,
223 .vlan_offload_set = i40e_vlan_offload_set,
224 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
225 .vlan_pvid_set = i40e_vlan_pvid_set,
226 .rx_queue_start = i40e_dev_rx_queue_start,
227 .rx_queue_stop = i40e_dev_rx_queue_stop,
228 .tx_queue_start = i40e_dev_tx_queue_start,
229 .tx_queue_stop = i40e_dev_tx_queue_stop,
230 .rx_queue_setup = i40e_dev_rx_queue_setup,
231 .rx_queue_release = i40e_dev_rx_queue_release,
232 .rx_queue_count = i40e_dev_rx_queue_count,
233 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
234 .tx_queue_setup = i40e_dev_tx_queue_setup,
235 .tx_queue_release = i40e_dev_tx_queue_release,
236 .dev_led_on = i40e_dev_led_on,
237 .dev_led_off = i40e_dev_led_off,
238 .flow_ctrl_set = i40e_flow_ctrl_set,
239 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
240 .mac_addr_add = i40e_macaddr_add,
241 .mac_addr_remove = i40e_macaddr_remove,
242 .reta_update = i40e_dev_rss_reta_update,
243 .reta_query = i40e_dev_rss_reta_query,
244 .rss_hash_update = i40e_dev_rss_hash_update,
245 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
246 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
247 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
248 .filter_ctrl = i40e_dev_filter_ctrl,
251 static struct eth_driver rte_i40e_pmd = {
253 .name = "rte_i40e_pmd",
254 .id_table = pci_id_i40e_map,
255 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
257 .eth_dev_init = eth_i40e_dev_init,
258 .dev_private_size = sizeof(struct i40e_adapter),
262 i40e_align_floor(int n)
266 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
270 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
271 struct rte_eth_link *link)
273 struct rte_eth_link *dst = link;
274 struct rte_eth_link *src = &(dev->data->dev_link);
276 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
277 *(uint64_t *)src) == 0)
284 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
285 struct rte_eth_link *link)
287 struct rte_eth_link *dst = &(dev->data->dev_link);
288 struct rte_eth_link *src = link;
290 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
291 *(uint64_t *)src) == 0)
298 * Driver initialization routine.
299 * Invoked once at EAL init time.
300 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
303 rte_i40e_pmd_init(const char *name __rte_unused,
304 const char *params __rte_unused)
306 PMD_INIT_FUNC_TRACE();
307 rte_eth_driver_register(&rte_i40e_pmd);
312 static struct rte_driver rte_i40e_driver = {
314 .init = rte_i40e_pmd_init,
317 PMD_REGISTER_DRIVER(rte_i40e_driver);
320 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
321 struct rte_eth_dev *dev)
323 struct rte_pci_device *pci_dev;
324 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
325 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
326 struct i40e_vsi *vsi;
331 PMD_INIT_FUNC_TRACE();
333 dev->dev_ops = &i40e_eth_dev_ops;
334 dev->rx_pkt_burst = i40e_recv_pkts;
335 dev->tx_pkt_burst = i40e_xmit_pkts;
337 /* for secondary processes, we don't initialise any further as primary
338 * has already done this work. Only check we don't need a different
340 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
341 if (dev->data->scattered_rx)
342 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
345 pci_dev = dev->pci_dev;
346 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
347 pf->adapter->eth_dev = dev;
348 pf->dev_data = dev->data;
350 hw->back = I40E_PF_TO_ADAPTER(pf);
351 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
353 PMD_INIT_LOG(ERR, "Hardware is not available, "
354 "as address is NULL");
358 hw->vendor_id = pci_dev->id.vendor_id;
359 hw->device_id = pci_dev->id.device_id;
360 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
361 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
362 hw->bus.device = pci_dev->addr.devid;
363 hw->bus.func = pci_dev->addr.function;
365 /* Make sure all is clean before doing PF reset */
368 /* Reset here to make sure all is clean for each PF */
369 ret = i40e_pf_reset(hw);
371 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
375 /* Initialize the shared code (base driver) */
376 ret = i40e_init_shared_code(hw);
378 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
382 /* Initialize the parameters for adminq */
383 i40e_init_adminq_parameter(hw);
384 ret = i40e_init_adminq(hw);
385 if (ret != I40E_SUCCESS) {
386 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
389 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
390 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
391 hw->aq.api_maj_ver, hw->aq.api_min_ver,
392 ((hw->nvm.version >> 12) & 0xf),
393 ((hw->nvm.version >> 4) & 0xff),
394 (hw->nvm.version & 0xf), hw->nvm.eetrack);
397 ret = i40e_aq_stop_lldp(hw, true, NULL);
398 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
399 PMD_INIT_LOG(INFO, "Failed to stop lldp");
402 i40e_clear_pxe_mode(hw);
404 /* Get hw capabilities */
405 ret = i40e_get_cap(hw);
406 if (ret != I40E_SUCCESS) {
407 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
408 goto err_get_capabilities;
411 /* Initialize parameters for PF */
412 ret = i40e_pf_parameter_init(dev);
414 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
415 goto err_parameter_init;
418 /* Initialize the queue management */
419 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
421 PMD_INIT_LOG(ERR, "Failed to init queue pool");
422 goto err_qp_pool_init;
424 ret = i40e_res_pool_init(&pf->msix_pool, 1,
425 hw->func_caps.num_msix_vectors - 1);
427 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
428 goto err_msix_pool_init;
431 /* Initialize lan hmc */
432 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
433 hw->func_caps.num_rx_qp, 0, 0);
434 if (ret != I40E_SUCCESS) {
435 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
436 goto err_init_lan_hmc;
439 /* Configure lan hmc */
440 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
441 if (ret != I40E_SUCCESS) {
442 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
443 goto err_configure_lan_hmc;
446 /* Get and check the mac address */
447 i40e_get_mac_addr(hw, hw->mac.addr);
448 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
449 PMD_INIT_LOG(ERR, "mac address is not valid");
451 goto err_get_mac_addr;
453 /* Copy the permanent MAC address */
454 ether_addr_copy((struct ether_addr *) hw->mac.addr,
455 (struct ether_addr *) hw->mac.perm_addr);
457 /* Disable flow control */
458 hw->fc.requested_mode = I40E_FC_NONE;
459 i40e_set_fc(hw, &aq_fail, TRUE);
461 /* PF setup, which includes VSI setup */
462 ret = i40e_pf_setup(pf);
464 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
465 goto err_setup_pf_switch;
470 /* Disable double vlan by default */
471 i40e_vsi_config_double_vlan(vsi, FALSE);
473 if (!vsi->max_macaddrs)
474 len = ETHER_ADDR_LEN;
476 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
478 /* Should be after VSI initialized */
479 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
480 if (!dev->data->mac_addrs) {
481 PMD_INIT_LOG(ERR, "Failed to allocated memory "
482 "for storing mac address");
485 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
486 &dev->data->mac_addrs[0]);
488 /* initialize pf host driver to setup SRIOV resource if applicable */
489 i40e_pf_host_init(dev);
491 /* register callback func to eal lib */
492 rte_intr_callback_register(&(pci_dev->intr_handle),
493 i40e_dev_interrupt_handler, (void *)dev);
495 /* configure and enable device interrupt */
496 i40e_pf_config_irq0(hw);
497 i40e_pf_enable_irq0(hw);
499 /* enable uio intr after callback register */
500 rte_intr_enable(&(pci_dev->intr_handle));
505 i40e_vsi_release(pf->main_vsi);
507 i40e_fdir_teardown(pf);
509 err_configure_lan_hmc:
510 (void)i40e_shutdown_lan_hmc(hw);
512 i40e_res_pool_destroy(&pf->msix_pool);
514 i40e_res_pool_destroy(&pf->qp_pool);
517 err_get_capabilities:
518 (void)i40e_shutdown_adminq(hw);
524 i40e_dev_configure(struct rte_eth_dev *dev)
527 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
530 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
531 * RSS setting have different requirements.
532 * General PMD driver call sequence are NIC init, configure,
533 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
534 * will try to lookup the VSI that specific queue belongs to if VMDQ
535 * applicable. So, VMDQ setting has to be done before
536 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
537 * For RSS setting, it will try to calculate actual configured RX queue
538 * number, which will be available after rx_queue_setup(). dev_start()
539 * function is good to place RSS setup.
541 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
542 ret = i40e_vmdq_setup(dev);
547 return i40e_dev_init_vlan(dev);
551 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
553 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
554 uint16_t msix_vect = vsi->msix_intr;
557 for (i = 0; i < vsi->nb_qps; i++) {
558 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
559 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
563 if (vsi->type != I40E_VSI_SRIOV) {
564 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
565 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
569 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
570 vsi->user_param + (msix_vect - 1);
572 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
574 I40E_WRITE_FLUSH(hw);
577 static inline uint16_t
578 i40e_calc_itr_interval(int16_t interval)
580 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
581 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
583 /* Convert to hardware count, as writing each 1 represents 2 us */
588 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
591 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
592 uint16_t msix_vect = vsi->msix_intr;
595 for (i = 0; i < vsi->nb_qps; i++)
596 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
598 /* Bind all RX queues to allocated MSIX interrupt */
599 for (i = 0; i < vsi->nb_qps; i++) {
600 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
601 I40E_QINT_RQCTL_ITR_INDX_MASK |
602 ((vsi->base_queue + i + 1) <<
603 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
604 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
605 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
607 if (i == vsi->nb_qps - 1)
608 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
609 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
612 /* Write first RX queue to Link list register as the head element */
613 if (vsi->type != I40E_VSI_SRIOV) {
615 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
617 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
619 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
620 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
622 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
623 msix_vect - 1), interval);
625 #ifndef I40E_GLINT_CTL
626 #define I40E_GLINT_CTL 0x0003F800
627 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
629 /* Disable auto-mask on enabling of all none-zero interrupt */
630 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
631 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
635 /* num_msix_vectors_vf needs to minus irq0 */
636 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
637 vsi->user_param + (msix_vect - 1);
639 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
640 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
641 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
644 I40E_WRITE_FLUSH(hw);
648 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
650 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
651 uint16_t interval = i40e_calc_itr_interval(\
652 RTE_LIBRTE_I40E_ITR_INTERVAL);
654 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
655 I40E_PFINT_DYN_CTLN_INTENA_MASK |
656 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
657 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
658 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
662 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
664 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
666 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
669 static inline uint8_t
670 i40e_parse_link_speed(uint16_t eth_link_speed)
672 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
674 switch (eth_link_speed) {
675 case ETH_LINK_SPEED_40G:
676 link_speed = I40E_LINK_SPEED_40GB;
678 case ETH_LINK_SPEED_20G:
679 link_speed = I40E_LINK_SPEED_20GB;
681 case ETH_LINK_SPEED_10G:
682 link_speed = I40E_LINK_SPEED_10GB;
684 case ETH_LINK_SPEED_1000:
685 link_speed = I40E_LINK_SPEED_1GB;
687 case ETH_LINK_SPEED_100:
688 link_speed = I40E_LINK_SPEED_100MB;
696 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
698 enum i40e_status_code status;
699 struct i40e_aq_get_phy_abilities_resp phy_ab;
700 struct i40e_aq_set_phy_config phy_conf;
701 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
702 I40E_AQ_PHY_FLAG_PAUSE_RX |
703 I40E_AQ_PHY_FLAG_LOW_POWER;
704 const uint8_t advt = I40E_LINK_SPEED_40GB |
705 I40E_LINK_SPEED_10GB |
706 I40E_LINK_SPEED_1GB |
707 I40E_LINK_SPEED_100MB;
710 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
715 memset(&phy_conf, 0, sizeof(phy_conf));
717 /* bits 0-2 use the values from get_phy_abilities_resp */
719 abilities |= phy_ab.abilities & mask;
721 /* update ablities and speed */
722 if (abilities & I40E_AQ_PHY_AN_ENABLED)
723 phy_conf.link_speed = advt;
725 phy_conf.link_speed = force_speed;
727 phy_conf.abilities = abilities;
729 /* use get_phy_abilities_resp value for the rest */
730 phy_conf.phy_type = phy_ab.phy_type;
731 phy_conf.eee_capability = phy_ab.eee_capability;
732 phy_conf.eeer = phy_ab.eeer_val;
733 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
735 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
736 phy_ab.abilities, phy_ab.link_speed);
737 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
738 phy_conf.abilities, phy_conf.link_speed);
740 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
748 i40e_apply_link_speed(struct rte_eth_dev *dev)
751 uint8_t abilities = 0;
752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
753 struct rte_eth_conf *conf = &dev->data->dev_conf;
755 speed = i40e_parse_link_speed(conf->link_speed);
756 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
757 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
758 abilities |= I40E_AQ_PHY_AN_ENABLED;
760 abilities |= I40E_AQ_PHY_LINK_ENABLED;
762 return i40e_phy_conf_link(hw, abilities, speed);
766 i40e_dev_start(struct rte_eth_dev *dev)
768 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
770 struct i40e_vsi *main_vsi = pf->main_vsi;
773 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
774 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
775 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
776 dev->data->dev_conf.link_duplex,
782 ret = i40e_dev_rxtx_init(pf);
783 if (ret != I40E_SUCCESS) {
784 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
788 /* Map queues with MSIX interrupt */
789 i40e_vsi_queues_bind_intr(main_vsi);
790 i40e_vsi_enable_queues_intr(main_vsi);
792 /* Map VMDQ VSI queues with MSIX interrupt */
793 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
794 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
795 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
798 ret = i40e_fdir_configure(dev);
800 PMD_DRV_LOG(ERR, "failed to configure fdir.");
804 /* enable FDIR MSIX interrupt */
805 if (pf->flags & I40E_FLAG_FDIR) {
806 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
807 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
810 /* Enable all queues which have been configured */
811 ret = i40e_dev_switch_queues(pf, TRUE);
812 if (ret != I40E_SUCCESS) {
813 PMD_DRV_LOG(ERR, "Failed to enable VSI");
817 /* Enable receiving broadcast packets */
818 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
819 if (ret != I40E_SUCCESS)
820 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
822 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
823 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
825 if (ret != I40E_SUCCESS)
826 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
829 /* Apply link configure */
830 ret = i40e_apply_link_speed(dev);
831 if (I40E_SUCCESS != ret) {
832 PMD_DRV_LOG(ERR, "Fail to apply link setting");
839 i40e_dev_switch_queues(pf, FALSE);
840 i40e_dev_clear_queues(dev);
846 i40e_dev_stop(struct rte_eth_dev *dev)
848 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
849 struct i40e_vsi *main_vsi = pf->main_vsi;
852 /* Disable all queues */
853 i40e_dev_switch_queues(pf, FALSE);
855 /* un-map queues with interrupt registers */
856 i40e_vsi_disable_queues_intr(main_vsi);
857 i40e_vsi_queues_unbind_intr(main_vsi);
859 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
860 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
861 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
864 if (pf->flags & I40E_FLAG_FDIR) {
865 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
866 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
868 /* Clear all queues and release memory */
869 i40e_dev_clear_queues(dev);
872 i40e_dev_set_link_down(dev);
877 i40e_dev_close(struct rte_eth_dev *dev)
879 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
883 PMD_INIT_FUNC_TRACE();
887 /* Disable interrupt */
888 i40e_pf_disable_irq0(hw);
889 rte_intr_disable(&(dev->pci_dev->intr_handle));
891 /* shutdown and destroy the HMC */
892 i40e_shutdown_lan_hmc(hw);
894 /* release all the existing VSIs and VEBs */
895 i40e_fdir_teardown(pf);
896 i40e_vsi_release(pf->main_vsi);
898 /* shutdown the adminq */
899 i40e_aq_queue_shutdown(hw, true);
900 i40e_shutdown_adminq(hw);
902 i40e_res_pool_destroy(&pf->qp_pool);
903 i40e_res_pool_destroy(&pf->msix_pool);
905 /* force a PF reset to clean anything leftover */
906 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
907 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
908 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
909 I40E_WRITE_FLUSH(hw);
913 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 struct i40e_vsi *vsi = pf->main_vsi;
920 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
922 if (status != I40E_SUCCESS)
923 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
925 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
927 if (status != I40E_SUCCESS)
928 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
933 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 struct i40e_vsi *vsi = pf->main_vsi;
940 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
942 if (status != I40E_SUCCESS)
943 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
945 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
947 if (status != I40E_SUCCESS)
948 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
952 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
954 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
955 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
956 struct i40e_vsi *vsi = pf->main_vsi;
959 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
960 if (ret != I40E_SUCCESS)
961 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
965 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
967 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
969 struct i40e_vsi *vsi = pf->main_vsi;
972 if (dev->data->promiscuous == 1)
973 return; /* must remain in all_multicast mode */
975 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
976 vsi->seid, FALSE, NULL);
977 if (ret != I40E_SUCCESS)
978 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
982 * Set device link up.
985 i40e_dev_set_link_up(struct rte_eth_dev *dev)
987 /* re-apply link speed setting */
988 return i40e_apply_link_speed(dev);
992 * Set device link down.
995 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
997 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
998 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
999 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001 return i40e_phy_conf_link(hw, abilities, speed);
1005 i40e_dev_link_update(struct rte_eth_dev *dev,
1006 __rte_unused int wait_to_complete)
1008 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1009 struct i40e_link_status link_status;
1010 struct rte_eth_link link, old;
1013 memset(&link, 0, sizeof(link));
1014 memset(&old, 0, sizeof(old));
1015 memset(&link_status, 0, sizeof(link_status));
1016 rte_i40e_dev_atomic_read_link_status(dev, &old);
1018 /* Get link status information from hardware */
1019 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1020 if (status != I40E_SUCCESS) {
1021 link.link_speed = ETH_LINK_SPEED_100;
1022 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1023 PMD_DRV_LOG(ERR, "Failed to get link info");
1027 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1029 if (!link.link_status)
1032 /* i40e uses full duplex only */
1033 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1035 /* Parse the link status */
1036 switch (link_status.link_speed) {
1037 case I40E_LINK_SPEED_100MB:
1038 link.link_speed = ETH_LINK_SPEED_100;
1040 case I40E_LINK_SPEED_1GB:
1041 link.link_speed = ETH_LINK_SPEED_1000;
1043 case I40E_LINK_SPEED_10GB:
1044 link.link_speed = ETH_LINK_SPEED_10G;
1046 case I40E_LINK_SPEED_20GB:
1047 link.link_speed = ETH_LINK_SPEED_20G;
1049 case I40E_LINK_SPEED_40GB:
1050 link.link_speed = ETH_LINK_SPEED_40G;
1053 link.link_speed = ETH_LINK_SPEED_100;
1058 rte_i40e_dev_atomic_write_link_status(dev, &link);
1059 if (link.link_status == old.link_status)
1065 /* Get all the statistics of a VSI */
1067 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1069 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1070 struct i40e_eth_stats *nes = &vsi->eth_stats;
1071 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1072 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1074 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1075 vsi->offset_loaded, &oes->rx_bytes,
1077 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1078 vsi->offset_loaded, &oes->rx_unicast,
1080 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1081 vsi->offset_loaded, &oes->rx_multicast,
1082 &nes->rx_multicast);
1083 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1084 vsi->offset_loaded, &oes->rx_broadcast,
1085 &nes->rx_broadcast);
1086 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1087 &oes->rx_discards, &nes->rx_discards);
1088 /* GLV_REPC not supported */
1089 /* GLV_RMPC not supported */
1090 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1091 &oes->rx_unknown_protocol,
1092 &nes->rx_unknown_protocol);
1093 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1094 vsi->offset_loaded, &oes->tx_bytes,
1096 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1097 vsi->offset_loaded, &oes->tx_unicast,
1099 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1100 vsi->offset_loaded, &oes->tx_multicast,
1101 &nes->tx_multicast);
1102 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1103 vsi->offset_loaded, &oes->tx_broadcast,
1104 &nes->tx_broadcast);
1105 /* GLV_TDPC not supported */
1106 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1107 &oes->tx_errors, &nes->tx_errors);
1108 vsi->offset_loaded = true;
1110 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1112 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1113 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1114 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1115 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1116 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1117 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1118 nes->rx_unknown_protocol);
1119 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1120 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1121 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1122 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1123 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1124 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1125 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1129 /* Get all statistics of a port */
1131 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1134 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1135 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1137 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1139 /* Get statistics of struct i40e_eth_stats */
1140 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1141 I40E_GLPRT_GORCL(hw->port),
1142 pf->offset_loaded, &os->eth.rx_bytes,
1144 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1145 I40E_GLPRT_UPRCL(hw->port),
1146 pf->offset_loaded, &os->eth.rx_unicast,
1147 &ns->eth.rx_unicast);
1148 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1149 I40E_GLPRT_MPRCL(hw->port),
1150 pf->offset_loaded, &os->eth.rx_multicast,
1151 &ns->eth.rx_multicast);
1152 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1153 I40E_GLPRT_BPRCL(hw->port),
1154 pf->offset_loaded, &os->eth.rx_broadcast,
1155 &ns->eth.rx_broadcast);
1156 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1157 pf->offset_loaded, &os->eth.rx_discards,
1158 &ns->eth.rx_discards);
1159 /* GLPRT_REPC not supported */
1160 /* GLPRT_RMPC not supported */
1161 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1163 &os->eth.rx_unknown_protocol,
1164 &ns->eth.rx_unknown_protocol);
1165 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1166 I40E_GLPRT_GOTCL(hw->port),
1167 pf->offset_loaded, &os->eth.tx_bytes,
1169 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1170 I40E_GLPRT_UPTCL(hw->port),
1171 pf->offset_loaded, &os->eth.tx_unicast,
1172 &ns->eth.tx_unicast);
1173 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1174 I40E_GLPRT_MPTCL(hw->port),
1175 pf->offset_loaded, &os->eth.tx_multicast,
1176 &ns->eth.tx_multicast);
1177 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1178 I40E_GLPRT_BPTCL(hw->port),
1179 pf->offset_loaded, &os->eth.tx_broadcast,
1180 &ns->eth.tx_broadcast);
1181 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1182 pf->offset_loaded, &os->eth.tx_discards,
1183 &ns->eth.tx_discards);
1184 /* GLPRT_TEPC not supported */
1186 /* additional port specific stats */
1187 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1188 pf->offset_loaded, &os->tx_dropped_link_down,
1189 &ns->tx_dropped_link_down);
1190 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1191 pf->offset_loaded, &os->crc_errors,
1193 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1194 pf->offset_loaded, &os->illegal_bytes,
1195 &ns->illegal_bytes);
1196 /* GLPRT_ERRBC not supported */
1197 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1198 pf->offset_loaded, &os->mac_local_faults,
1199 &ns->mac_local_faults);
1200 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1201 pf->offset_loaded, &os->mac_remote_faults,
1202 &ns->mac_remote_faults);
1203 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1204 pf->offset_loaded, &os->rx_length_errors,
1205 &ns->rx_length_errors);
1206 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1207 pf->offset_loaded, &os->link_xon_rx,
1209 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1210 pf->offset_loaded, &os->link_xoff_rx,
1212 for (i = 0; i < 8; i++) {
1213 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1215 &os->priority_xon_rx[i],
1216 &ns->priority_xon_rx[i]);
1217 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1219 &os->priority_xoff_rx[i],
1220 &ns->priority_xoff_rx[i]);
1222 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1223 pf->offset_loaded, &os->link_xon_tx,
1225 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1226 pf->offset_loaded, &os->link_xoff_tx,
1228 for (i = 0; i < 8; i++) {
1229 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1231 &os->priority_xon_tx[i],
1232 &ns->priority_xon_tx[i]);
1233 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1235 &os->priority_xoff_tx[i],
1236 &ns->priority_xoff_tx[i]);
1237 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1239 &os->priority_xon_2_xoff[i],
1240 &ns->priority_xon_2_xoff[i]);
1242 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1243 I40E_GLPRT_PRC64L(hw->port),
1244 pf->offset_loaded, &os->rx_size_64,
1246 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1247 I40E_GLPRT_PRC127L(hw->port),
1248 pf->offset_loaded, &os->rx_size_127,
1250 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1251 I40E_GLPRT_PRC255L(hw->port),
1252 pf->offset_loaded, &os->rx_size_255,
1254 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1255 I40E_GLPRT_PRC511L(hw->port),
1256 pf->offset_loaded, &os->rx_size_511,
1258 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1259 I40E_GLPRT_PRC1023L(hw->port),
1260 pf->offset_loaded, &os->rx_size_1023,
1262 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1263 I40E_GLPRT_PRC1522L(hw->port),
1264 pf->offset_loaded, &os->rx_size_1522,
1266 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1267 I40E_GLPRT_PRC9522L(hw->port),
1268 pf->offset_loaded, &os->rx_size_big,
1270 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1271 pf->offset_loaded, &os->rx_undersize,
1273 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1274 pf->offset_loaded, &os->rx_fragments,
1276 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1277 pf->offset_loaded, &os->rx_oversize,
1279 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1280 pf->offset_loaded, &os->rx_jabber,
1282 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1283 I40E_GLPRT_PTC64L(hw->port),
1284 pf->offset_loaded, &os->tx_size_64,
1286 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1287 I40E_GLPRT_PTC127L(hw->port),
1288 pf->offset_loaded, &os->tx_size_127,
1290 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1291 I40E_GLPRT_PTC255L(hw->port),
1292 pf->offset_loaded, &os->tx_size_255,
1294 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1295 I40E_GLPRT_PTC511L(hw->port),
1296 pf->offset_loaded, &os->tx_size_511,
1298 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1299 I40E_GLPRT_PTC1023L(hw->port),
1300 pf->offset_loaded, &os->tx_size_1023,
1302 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1303 I40E_GLPRT_PTC1522L(hw->port),
1304 pf->offset_loaded, &os->tx_size_1522,
1306 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1307 I40E_GLPRT_PTC9522L(hw->port),
1308 pf->offset_loaded, &os->tx_size_big,
1310 /* GLPRT_MSPDC not supported */
1311 /* GLPRT_XEC not supported */
1313 pf->offset_loaded = true;
1316 i40e_update_vsi_stats(pf->main_vsi);
1318 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1319 ns->eth.rx_broadcast;
1320 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1321 ns->eth.tx_broadcast;
1322 stats->ibytes = ns->eth.rx_bytes;
1323 stats->obytes = ns->eth.tx_bytes;
1324 stats->oerrors = ns->eth.tx_errors;
1325 stats->imcasts = ns->eth.rx_multicast;
1328 stats->ibadcrc = ns->crc_errors;
1329 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1330 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1331 stats->imissed = ns->eth.rx_discards;
1332 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1334 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1335 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1336 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1337 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1338 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1339 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1340 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1341 ns->eth.rx_unknown_protocol);
1342 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1343 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1344 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1345 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1346 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1347 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1349 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1350 ns->tx_dropped_link_down);
1351 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1352 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1354 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1355 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1356 ns->mac_local_faults);
1357 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1358 ns->mac_remote_faults);
1359 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1360 ns->rx_length_errors);
1361 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1362 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1363 for (i = 0; i < 8; i++) {
1364 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1365 i, ns->priority_xon_rx[i]);
1366 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1367 i, ns->priority_xoff_rx[i]);
1369 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1370 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1371 for (i = 0; i < 8; i++) {
1372 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1373 i, ns->priority_xon_tx[i]);
1374 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1375 i, ns->priority_xoff_tx[i]);
1376 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1377 i, ns->priority_xon_2_xoff[i]);
1379 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1380 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1381 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1382 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1383 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1384 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1385 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1386 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1387 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1388 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1389 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1390 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1391 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1392 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1393 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1394 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1395 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1396 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1397 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1398 ns->mac_short_packet_dropped);
1399 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1400 ns->checksum_error);
1401 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1404 /* Reset the statistics */
1406 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1408 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1410 /* It results in reloading the start point of each counter */
1411 pf->offset_loaded = false;
1415 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1416 __rte_unused uint16_t queue_id,
1417 __rte_unused uint8_t stat_idx,
1418 __rte_unused uint8_t is_rx)
1420 PMD_INIT_FUNC_TRACE();
1426 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1428 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1429 struct i40e_vsi *vsi = pf->main_vsi;
1431 dev_info->max_rx_queues = vsi->nb_qps;
1432 dev_info->max_tx_queues = vsi->nb_qps;
1433 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1434 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1435 dev_info->max_mac_addrs = vsi->max_macaddrs;
1436 dev_info->max_vfs = dev->pci_dev->max_vfs;
1437 dev_info->rx_offload_capa =
1438 DEV_RX_OFFLOAD_VLAN_STRIP |
1439 DEV_RX_OFFLOAD_IPV4_CKSUM |
1440 DEV_RX_OFFLOAD_UDP_CKSUM |
1441 DEV_RX_OFFLOAD_TCP_CKSUM;
1442 dev_info->tx_offload_capa =
1443 DEV_TX_OFFLOAD_VLAN_INSERT |
1444 DEV_TX_OFFLOAD_IPV4_CKSUM |
1445 DEV_TX_OFFLOAD_UDP_CKSUM |
1446 DEV_TX_OFFLOAD_TCP_CKSUM |
1447 DEV_TX_OFFLOAD_SCTP_CKSUM;
1448 dev_info->reta_size = pf->hash_lut_size;
1450 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1452 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1453 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1454 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1456 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1460 dev_info->default_txconf = (struct rte_eth_txconf) {
1462 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1463 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1464 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1466 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1467 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1468 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1469 ETH_TXQ_FLAGS_NOOFFLOADS,
1472 if (pf->flags | I40E_FLAG_VMDQ) {
1473 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1474 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1475 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1476 pf->max_nb_vmdq_vsi;
1477 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1478 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1479 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1484 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1487 struct i40e_vsi *vsi = pf->main_vsi;
1488 PMD_INIT_FUNC_TRACE();
1491 return i40e_vsi_add_vlan(vsi, vlan_id);
1493 return i40e_vsi_delete_vlan(vsi, vlan_id);
1497 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1498 __rte_unused uint16_t tpid)
1500 PMD_INIT_FUNC_TRACE();
1504 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1506 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1507 struct i40e_vsi *vsi = pf->main_vsi;
1509 if (mask & ETH_VLAN_STRIP_MASK) {
1510 /* Enable or disable VLAN stripping */
1511 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1512 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1514 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1517 if (mask & ETH_VLAN_EXTEND_MASK) {
1518 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1519 i40e_vsi_config_double_vlan(vsi, TRUE);
1521 i40e_vsi_config_double_vlan(vsi, FALSE);
1526 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1527 __rte_unused uint16_t queue,
1528 __rte_unused int on)
1530 PMD_INIT_FUNC_TRACE();
1534 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1536 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1537 struct i40e_vsi *vsi = pf->main_vsi;
1538 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1539 struct i40e_vsi_vlan_pvid_info info;
1541 memset(&info, 0, sizeof(info));
1544 info.config.pvid = pvid;
1546 info.config.reject.tagged =
1547 data->dev_conf.txmode.hw_vlan_reject_tagged;
1548 info.config.reject.untagged =
1549 data->dev_conf.txmode.hw_vlan_reject_untagged;
1552 return i40e_vsi_vlan_pvid_set(vsi, &info);
1556 i40e_dev_led_on(struct rte_eth_dev *dev)
1558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559 uint32_t mode = i40e_led_get(hw);
1562 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1568 i40e_dev_led_off(struct rte_eth_dev *dev)
1570 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571 uint32_t mode = i40e_led_get(hw);
1574 i40e_led_set(hw, 0, false);
1580 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1581 __rte_unused struct rte_eth_fc_conf *fc_conf)
1583 PMD_INIT_FUNC_TRACE();
1589 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1590 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1592 PMD_INIT_FUNC_TRACE();
1597 /* Add a MAC address, and update filters */
1599 i40e_macaddr_add(struct rte_eth_dev *dev,
1600 struct ether_addr *mac_addr,
1601 __rte_unused uint32_t index,
1604 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1605 struct i40e_mac_filter_info mac_filter;
1606 struct i40e_vsi *vsi;
1609 /* If VMDQ not enabled or configured, return */
1610 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1611 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1612 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1617 if (pool > pf->nb_cfg_vmdq_vsi) {
1618 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1619 pool, pf->nb_cfg_vmdq_vsi);
1623 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1624 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1629 vsi = pf->vmdq[pool - 1].vsi;
1631 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1632 if (ret != I40E_SUCCESS) {
1633 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1638 /* Remove a MAC address, and update filters */
1640 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1642 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1643 struct i40e_vsi *vsi;
1644 struct rte_eth_dev_data *data = dev->data;
1645 struct ether_addr *macaddr;
1650 macaddr = &(data->mac_addrs[index]);
1652 pool_sel = dev->data->mac_pool_sel[index];
1654 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1655 if (pool_sel & (1ULL << i)) {
1659 /* No VMDQ pool enabled or configured */
1660 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1661 (i > pf->nb_cfg_vmdq_vsi)) {
1662 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1666 vsi = pf->vmdq[i - 1].vsi;
1668 ret = i40e_vsi_delete_mac(vsi, macaddr);
1671 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1678 /* Set perfect match or hash match of MAC and VLAN for a VF */
1680 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1681 struct rte_eth_mac_filter *filter,
1685 struct i40e_mac_filter_info mac_filter;
1686 struct ether_addr old_mac;
1687 struct ether_addr *new_mac;
1688 struct i40e_pf_vf *vf = NULL;
1693 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1696 hw = I40E_PF_TO_HW(pf);
1698 if (filter == NULL) {
1699 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1703 new_mac = &filter->mac_addr;
1705 if (is_zero_ether_addr(new_mac)) {
1706 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1710 vf_id = filter->dst_id;
1712 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1713 PMD_DRV_LOG(ERR, "Invalid argument.");
1716 vf = &pf->vfs[vf_id];
1718 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1719 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1724 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1725 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1727 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1730 mac_filter.filter_type = filter->filter_type;
1731 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1732 if (ret != I40E_SUCCESS) {
1733 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1736 ether_addr_copy(new_mac, &pf->dev_addr);
1738 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1740 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1741 if (ret != I40E_SUCCESS) {
1742 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1746 /* Clear device address as it has been removed */
1747 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1748 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1754 /* MAC filter handle */
1756 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1759 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1760 struct rte_eth_mac_filter *filter;
1761 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1762 int ret = I40E_NOT_SUPPORTED;
1764 filter = (struct rte_eth_mac_filter *)(arg);
1766 switch (filter_op) {
1767 case RTE_ETH_FILTER_NOP:
1770 case RTE_ETH_FILTER_ADD:
1771 i40e_pf_disable_irq0(hw);
1773 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1774 i40e_pf_enable_irq0(hw);
1776 case RTE_ETH_FILTER_DELETE:
1777 i40e_pf_disable_irq0(hw);
1779 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1780 i40e_pf_enable_irq0(hw);
1783 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1784 ret = I40E_ERR_PARAM;
1792 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1793 struct rte_eth_rss_reta_entry64 *reta_conf,
1796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799 uint16_t i, j, lut_size = pf->hash_lut_size;
1800 uint16_t idx, shift;
1803 if (reta_size != lut_size ||
1804 reta_size > ETH_RSS_RETA_SIZE_512) {
1805 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1806 "(%d) doesn't match the number hardware can supported "
1807 "(%d)\n", reta_size, lut_size);
1811 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1812 idx = i / RTE_RETA_GROUP_SIZE;
1813 shift = i % RTE_RETA_GROUP_SIZE;
1814 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1818 if (mask == I40E_4_BIT_MASK)
1821 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1822 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1823 if (mask & (0x1 << j))
1824 lut |= reta_conf[idx].reta[shift + j] <<
1827 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1829 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1836 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1837 struct rte_eth_rss_reta_entry64 *reta_conf,
1840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 uint16_t i, j, lut_size = pf->hash_lut_size;
1844 uint16_t idx, shift;
1847 if (reta_size != lut_size ||
1848 reta_size > ETH_RSS_RETA_SIZE_512) {
1849 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1850 "(%d) doesn't match the number hardware can supported "
1851 "(%d)\n", reta_size, lut_size);
1855 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1856 idx = i / RTE_RETA_GROUP_SIZE;
1857 shift = i % RTE_RETA_GROUP_SIZE;
1858 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1863 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1864 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1865 if (mask & (0x1 << j))
1866 reta_conf[idx].reta[shift] = ((lut >>
1867 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1875 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1876 * @hw: pointer to the HW structure
1877 * @mem: pointer to mem struct to fill out
1878 * @size: size of memory requested
1879 * @alignment: what to align the allocation to
1881 enum i40e_status_code
1882 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1883 struct i40e_dma_mem *mem,
1887 static uint64_t id = 0;
1888 const struct rte_memzone *mz = NULL;
1889 char z_name[RTE_MEMZONE_NAMESIZE];
1892 return I40E_ERR_PARAM;
1895 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1896 #ifdef RTE_LIBRTE_XEN_DOM0
1897 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1900 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1903 return I40E_ERR_NO_MEMORY;
1908 #ifdef RTE_LIBRTE_XEN_DOM0
1909 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1911 mem->pa = mz->phys_addr;
1914 return I40E_SUCCESS;
1918 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1919 * @hw: pointer to the HW structure
1920 * @mem: ptr to mem struct to free
1922 enum i40e_status_code
1923 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1924 struct i40e_dma_mem *mem)
1926 if (!mem || !mem->va)
1927 return I40E_ERR_PARAM;
1932 return I40E_SUCCESS;
1936 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1937 * @hw: pointer to the HW structure
1938 * @mem: pointer to mem struct to fill out
1939 * @size: size of memory requested
1941 enum i40e_status_code
1942 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1943 struct i40e_virt_mem *mem,
1947 return I40E_ERR_PARAM;
1950 mem->va = rte_zmalloc("i40e", size, 0);
1953 return I40E_SUCCESS;
1955 return I40E_ERR_NO_MEMORY;
1959 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1960 * @hw: pointer to the HW structure
1961 * @mem: pointer to mem struct to free
1963 enum i40e_status_code
1964 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1965 struct i40e_virt_mem *mem)
1968 return I40E_ERR_PARAM;
1973 return I40E_SUCCESS;
1977 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1979 rte_spinlock_init(&sp->spinlock);
1983 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1985 rte_spinlock_lock(&sp->spinlock);
1989 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1991 rte_spinlock_unlock(&sp->spinlock);
1995 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2001 * Get the hardware capabilities, which will be parsed
2002 * and saved into struct i40e_hw.
2005 i40e_get_cap(struct i40e_hw *hw)
2007 struct i40e_aqc_list_capabilities_element_resp *buf;
2008 uint16_t len, size = 0;
2011 /* Calculate a huge enough buff for saving response data temporarily */
2012 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2013 I40E_MAX_CAP_ELE_NUM;
2014 buf = rte_zmalloc("i40e", len, 0);
2016 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2017 return I40E_ERR_NO_MEMORY;
2020 /* Get, parse the capabilities and save it to hw */
2021 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2022 i40e_aqc_opc_list_func_capabilities, NULL);
2023 if (ret != I40E_SUCCESS)
2024 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2026 /* Free the temporary buffer after being used */
2033 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2035 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2036 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2037 uint16_t sum_queues = 0, sum_vsis, left_queues;
2039 /* First check if FW support SRIOV */
2040 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2041 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2045 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2046 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2047 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2048 /* Allocate queues for pf */
2049 if (hw->func_caps.rss) {
2050 pf->flags |= I40E_FLAG_RSS;
2051 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2052 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2053 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2056 sum_queues = pf->lan_nb_qps;
2057 /* Default VSI is not counted in */
2059 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2061 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2062 pf->flags |= I40E_FLAG_SRIOV;
2063 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2064 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2065 PMD_INIT_LOG(ERR, "Config VF number %u, "
2066 "max supported %u.",
2067 dev->pci_dev->max_vfs,
2068 hw->func_caps.num_vfs);
2071 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2072 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2073 "max support %u queues.",
2074 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2077 pf->vf_num = dev->pci_dev->max_vfs;
2078 sum_queues += pf->vf_nb_qps * pf->vf_num;
2079 sum_vsis += pf->vf_num;
2080 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2081 pf->vf_num, pf->vf_nb_qps);
2085 if (hw->func_caps.vmdq) {
2086 pf->flags |= I40E_FLAG_VMDQ;
2087 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2088 pf->max_nb_vmdq_vsi = 1;
2090 * If VMDQ available, assume a single VSI can be created. Will adjust
2093 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2094 sum_vsis += pf->max_nb_vmdq_vsi;
2096 pf->vmdq_nb_qps = 0;
2097 pf->max_nb_vmdq_vsi = 0;
2099 pf->nb_cfg_vmdq_vsi = 0;
2101 if (hw->func_caps.fd) {
2102 pf->flags |= I40E_FLAG_FDIR;
2103 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2105 * Each flow director consumes one VSI and one queue,
2106 * but can't calculate out predictably here.
2110 if (sum_vsis > pf->max_num_vsi ||
2111 sum_queues > hw->func_caps.num_rx_qp) {
2112 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2113 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2114 pf->max_num_vsi, sum_vsis);
2115 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2116 hw->func_caps.num_rx_qp, sum_queues);
2120 /* Adjust VMDQ setting to support as many VMs as possible */
2121 if (pf->flags & I40E_FLAG_VMDQ) {
2122 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2124 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2125 pf->max_num_vsi - sum_vsis);
2127 /* Limit the max VMDQ number that rte_ether that can support */
2128 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2131 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2132 pf->max_nb_vmdq_vsi);
2133 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2136 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2138 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2139 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2140 sum_vsis, hw->func_caps.num_msix_vectors);
2143 return I40E_SUCCESS;
2147 i40e_pf_get_switch_config(struct i40e_pf *pf)
2149 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2150 struct i40e_aqc_get_switch_config_resp *switch_config;
2151 struct i40e_aqc_switch_config_element_resp *element;
2152 uint16_t start_seid = 0, num_reported;
2155 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2156 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2157 if (!switch_config) {
2158 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2162 /* Get the switch configurations */
2163 ret = i40e_aq_get_switch_config(hw, switch_config,
2164 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2165 if (ret != I40E_SUCCESS) {
2166 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2169 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2170 if (num_reported != 1) { /* The number should be 1 */
2171 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2175 /* Parse the switch configuration elements */
2176 element = &(switch_config->element[0]);
2177 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2178 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2179 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2181 PMD_DRV_LOG(INFO, "Unknown element type");
2184 rte_free(switch_config);
2190 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2193 struct pool_entry *entry;
2195 if (pool == NULL || num == 0)
2198 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2199 if (entry == NULL) {
2200 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2204 /* queue heap initialize */
2205 pool->num_free = num;
2206 pool->num_alloc = 0;
2208 LIST_INIT(&pool->alloc_list);
2209 LIST_INIT(&pool->free_list);
2211 /* Initialize element */
2215 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2220 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2222 struct pool_entry *entry;
2227 LIST_FOREACH(entry, &pool->alloc_list, next) {
2228 LIST_REMOVE(entry, next);
2232 LIST_FOREACH(entry, &pool->free_list, next) {
2233 LIST_REMOVE(entry, next);
2238 pool->num_alloc = 0;
2240 LIST_INIT(&pool->alloc_list);
2241 LIST_INIT(&pool->free_list);
2245 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2248 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2249 uint32_t pool_offset;
2253 PMD_DRV_LOG(ERR, "Invalid parameter");
2257 pool_offset = base - pool->base;
2258 /* Lookup in alloc list */
2259 LIST_FOREACH(entry, &pool->alloc_list, next) {
2260 if (entry->base == pool_offset) {
2261 valid_entry = entry;
2262 LIST_REMOVE(entry, next);
2267 /* Not find, return */
2268 if (valid_entry == NULL) {
2269 PMD_DRV_LOG(ERR, "Failed to find entry");
2274 * Found it, move it to free list and try to merge.
2275 * In order to make merge easier, always sort it by qbase.
2276 * Find adjacent prev and last entries.
2279 LIST_FOREACH(entry, &pool->free_list, next) {
2280 if (entry->base > valid_entry->base) {
2288 /* Try to merge with next one*/
2290 /* Merge with next one */
2291 if (valid_entry->base + valid_entry->len == next->base) {
2292 next->base = valid_entry->base;
2293 next->len += valid_entry->len;
2294 rte_free(valid_entry);
2301 /* Merge with previous one */
2302 if (prev->base + prev->len == valid_entry->base) {
2303 prev->len += valid_entry->len;
2304 /* If it merge with next one, remove next node */
2306 LIST_REMOVE(valid_entry, next);
2307 rte_free(valid_entry);
2309 rte_free(valid_entry);
2315 /* Not find any entry to merge, insert */
2318 LIST_INSERT_AFTER(prev, valid_entry, next);
2319 else if (next != NULL)
2320 LIST_INSERT_BEFORE(next, valid_entry, next);
2321 else /* It's empty list, insert to head */
2322 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2325 pool->num_free += valid_entry->len;
2326 pool->num_alloc -= valid_entry->len;
2332 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2335 struct pool_entry *entry, *valid_entry;
2337 if (pool == NULL || num == 0) {
2338 PMD_DRV_LOG(ERR, "Invalid parameter");
2342 if (pool->num_free < num) {
2343 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2344 num, pool->num_free);
2349 /* Lookup in free list and find most fit one */
2350 LIST_FOREACH(entry, &pool->free_list, next) {
2351 if (entry->len >= num) {
2353 if (entry->len == num) {
2354 valid_entry = entry;
2357 if (valid_entry == NULL || valid_entry->len > entry->len)
2358 valid_entry = entry;
2362 /* Not find one to satisfy the request, return */
2363 if (valid_entry == NULL) {
2364 PMD_DRV_LOG(ERR, "No valid entry found");
2368 * The entry have equal queue number as requested,
2369 * remove it from alloc_list.
2371 if (valid_entry->len == num) {
2372 LIST_REMOVE(valid_entry, next);
2375 * The entry have more numbers than requested,
2376 * create a new entry for alloc_list and minus its
2377 * queue base and number in free_list.
2379 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2380 if (entry == NULL) {
2381 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2385 entry->base = valid_entry->base;
2387 valid_entry->base += num;
2388 valid_entry->len -= num;
2389 valid_entry = entry;
2392 /* Insert it into alloc list, not sorted */
2393 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2395 pool->num_free -= valid_entry->len;
2396 pool->num_alloc += valid_entry->len;
2398 return (valid_entry->base + pool->base);
2402 * bitmap_is_subset - Check whether src2 is subset of src1
2405 bitmap_is_subset(uint8_t src1, uint8_t src2)
2407 return !((src1 ^ src2) & src2);
2411 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2413 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2415 /* If DCB is not supported, only default TC is supported */
2416 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2417 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2421 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2422 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2423 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2427 return I40E_SUCCESS;
2431 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2432 struct i40e_vsi_vlan_pvid_info *info)
2435 struct i40e_vsi_context ctxt;
2436 uint8_t vlan_flags = 0;
2439 if (vsi == NULL || info == NULL) {
2440 PMD_DRV_LOG(ERR, "invalid parameters");
2441 return I40E_ERR_PARAM;
2445 vsi->info.pvid = info->config.pvid;
2447 * If insert pvid is enabled, only tagged pkts are
2448 * allowed to be sent out.
2450 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2451 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2454 if (info->config.reject.tagged == 0)
2455 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2457 if (info->config.reject.untagged == 0)
2458 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2460 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2461 I40E_AQ_VSI_PVLAN_MODE_MASK);
2462 vsi->info.port_vlan_flags |= vlan_flags;
2463 vsi->info.valid_sections =
2464 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2465 memset(&ctxt, 0, sizeof(ctxt));
2466 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2467 ctxt.seid = vsi->seid;
2469 hw = I40E_VSI_TO_HW(vsi);
2470 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2471 if (ret != I40E_SUCCESS)
2472 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2478 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2480 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2482 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2484 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2485 if (ret != I40E_SUCCESS)
2489 PMD_DRV_LOG(ERR, "seid not valid");
2493 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2494 tc_bw_data.tc_valid_bits = enabled_tcmap;
2495 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2496 tc_bw_data.tc_bw_credits[i] =
2497 (enabled_tcmap & (1 << i)) ? 1 : 0;
2499 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2500 if (ret != I40E_SUCCESS) {
2501 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2505 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2506 sizeof(vsi->info.qs_handle));
2507 return I40E_SUCCESS;
2511 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2512 struct i40e_aqc_vsi_properties_data *info,
2513 uint8_t enabled_tcmap)
2515 int ret, total_tc = 0, i;
2516 uint16_t qpnum_per_tc, bsf, qp_idx;
2518 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2519 if (ret != I40E_SUCCESS)
2522 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2523 if (enabled_tcmap & (1 << i))
2525 vsi->enabled_tc = enabled_tcmap;
2527 /* Number of queues per enabled TC */
2528 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2529 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2530 bsf = rte_bsf32(qpnum_per_tc);
2532 /* Adjust the queue number to actual queues that can be applied */
2533 vsi->nb_qps = qpnum_per_tc * total_tc;
2536 * Configure TC and queue mapping parameters, for enabled TC,
2537 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2538 * default queue will serve it.
2541 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2542 if (vsi->enabled_tc & (1 << i)) {
2543 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2544 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2545 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2546 qp_idx += qpnum_per_tc;
2548 info->tc_mapping[i] = 0;
2551 /* Associate queue number with VSI */
2552 if (vsi->type == I40E_VSI_SRIOV) {
2553 info->mapping_flags |=
2554 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2555 for (i = 0; i < vsi->nb_qps; i++)
2556 info->queue_mapping[i] =
2557 rte_cpu_to_le_16(vsi->base_queue + i);
2559 info->mapping_flags |=
2560 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2561 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2563 info->valid_sections =
2564 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2566 return I40E_SUCCESS;
2570 i40e_veb_release(struct i40e_veb *veb)
2572 struct i40e_vsi *vsi;
2575 if (veb == NULL || veb->associate_vsi == NULL)
2578 if (!TAILQ_EMPTY(&veb->head)) {
2579 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2583 vsi = veb->associate_vsi;
2584 hw = I40E_VSI_TO_HW(vsi);
2586 vsi->uplink_seid = veb->uplink_seid;
2587 i40e_aq_delete_element(hw, veb->seid, NULL);
2590 return I40E_SUCCESS;
2594 static struct i40e_veb *
2595 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2597 struct i40e_veb *veb;
2601 if (NULL == pf || vsi == NULL) {
2602 PMD_DRV_LOG(ERR, "veb setup failed, "
2603 "associated VSI shouldn't null");
2606 hw = I40E_PF_TO_HW(pf);
2608 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2610 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2614 veb->associate_vsi = vsi;
2615 TAILQ_INIT(&veb->head);
2616 veb->uplink_seid = vsi->uplink_seid;
2618 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2619 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2621 if (ret != I40E_SUCCESS) {
2622 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2623 hw->aq.asq_last_status);
2627 /* get statistics index */
2628 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2629 &veb->stats_idx, NULL, NULL, NULL);
2630 if (ret != I40E_SUCCESS) {
2631 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2632 hw->aq.asq_last_status);
2636 /* Get VEB bandwidth, to be implemented */
2637 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2638 vsi->uplink_seid = veb->seid;
2647 i40e_vsi_release(struct i40e_vsi *vsi)
2651 struct i40e_vsi_list *vsi_list;
2653 struct i40e_mac_filter *f;
2656 return I40E_SUCCESS;
2658 pf = I40E_VSI_TO_PF(vsi);
2659 hw = I40E_VSI_TO_HW(vsi);
2661 /* VSI has child to attach, release child first */
2663 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2664 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2666 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2668 i40e_veb_release(vsi->veb);
2671 /* Remove all macvlan filters of the VSI */
2672 i40e_vsi_remove_all_macvlan_filter(vsi);
2673 TAILQ_FOREACH(f, &vsi->mac_list, next)
2676 if (vsi->type != I40E_VSI_MAIN) {
2677 /* Remove vsi from parent's sibling list */
2678 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2679 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2680 return I40E_ERR_PARAM;
2682 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2683 &vsi->sib_vsi_list, list);
2685 /* Remove all switch element of the VSI */
2686 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2687 if (ret != I40E_SUCCESS)
2688 PMD_DRV_LOG(ERR, "Failed to delete element");
2690 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2692 if (vsi->type != I40E_VSI_SRIOV)
2693 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2696 return I40E_SUCCESS;
2700 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2702 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2703 struct i40e_aqc_remove_macvlan_element_data def_filter;
2704 struct i40e_mac_filter_info filter;
2707 if (vsi->type != I40E_VSI_MAIN)
2708 return I40E_ERR_CONFIG;
2709 memset(&def_filter, 0, sizeof(def_filter));
2710 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2712 def_filter.vlan_tag = 0;
2713 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2714 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2715 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2716 if (ret != I40E_SUCCESS) {
2717 struct i40e_mac_filter *f;
2718 struct ether_addr *mac;
2720 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2722 /* It needs to add the permanent mac into mac list */
2723 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2725 PMD_DRV_LOG(ERR, "failed to allocate memory");
2726 return I40E_ERR_NO_MEMORY;
2728 mac = &f->mac_info.mac_addr;
2729 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2731 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2732 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2737 (void)rte_memcpy(&filter.mac_addr,
2738 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2739 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2740 return i40e_vsi_add_mac(vsi, &filter);
2744 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2746 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2747 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2748 struct i40e_hw *hw = &vsi->adapter->hw;
2752 memset(&bw_config, 0, sizeof(bw_config));
2753 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2754 if (ret != I40E_SUCCESS) {
2755 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2756 hw->aq.asq_last_status);
2760 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2761 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2762 &ets_sla_config, NULL);
2763 if (ret != I40E_SUCCESS) {
2764 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2765 "configuration %u", hw->aq.asq_last_status);
2769 /* Not store the info yet, just print out */
2770 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2771 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2772 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2773 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2774 ets_sla_config.share_credits[i]);
2775 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2776 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2777 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2778 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2787 i40e_vsi_setup(struct i40e_pf *pf,
2788 enum i40e_vsi_type type,
2789 struct i40e_vsi *uplink_vsi,
2790 uint16_t user_param)
2792 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2793 struct i40e_vsi *vsi;
2794 struct i40e_mac_filter_info filter;
2796 struct i40e_vsi_context ctxt;
2797 struct ether_addr broadcast =
2798 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2800 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2801 PMD_DRV_LOG(ERR, "VSI setup failed, "
2802 "VSI link shouldn't be NULL");
2806 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2807 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2808 "uplink VSI should be NULL");
2812 /* If uplink vsi didn't setup VEB, create one first */
2813 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2814 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2816 if (NULL == uplink_vsi->veb) {
2817 PMD_DRV_LOG(ERR, "VEB setup failed");
2822 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2824 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2827 TAILQ_INIT(&vsi->mac_list);
2829 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2830 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2831 vsi->parent_vsi = uplink_vsi;
2832 vsi->user_param = user_param;
2833 /* Allocate queues */
2834 switch (vsi->type) {
2835 case I40E_VSI_MAIN :
2836 vsi->nb_qps = pf->lan_nb_qps;
2838 case I40E_VSI_SRIOV :
2839 vsi->nb_qps = pf->vf_nb_qps;
2841 case I40E_VSI_VMDQ2:
2842 vsi->nb_qps = pf->vmdq_nb_qps;
2845 vsi->nb_qps = pf->fdir_nb_qps;
2851 * The filter status descriptor is reported in rx queue 0,
2852 * while the tx queue for fdir filter programming has no
2853 * such constraints, can be non-zero queues.
2854 * To simplify it, choose FDIR vsi use queue 0 pair.
2855 * To make sure it will use queue 0 pair, queue allocation
2856 * need be done before this function is called
2858 if (type != I40E_VSI_FDIR) {
2859 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2861 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2865 vsi->base_queue = ret;
2867 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2869 /* VF has MSIX interrupt in VF range, don't allocate here */
2870 if (type != I40E_VSI_SRIOV) {
2871 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2873 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2874 goto fail_queue_alloc;
2876 vsi->msix_intr = ret;
2880 if (type == I40E_VSI_MAIN) {
2881 /* For main VSI, no need to add since it's default one */
2882 vsi->uplink_seid = pf->mac_seid;
2883 vsi->seid = pf->main_vsi_seid;
2884 /* Bind queues with specific MSIX interrupt */
2886 * Needs 2 interrupt at least, one for misc cause which will
2887 * enabled from OS side, Another for queues binding the
2888 * interrupt from device side only.
2891 /* Get default VSI parameters from hardware */
2892 memset(&ctxt, 0, sizeof(ctxt));
2893 ctxt.seid = vsi->seid;
2894 ctxt.pf_num = hw->pf_id;
2895 ctxt.uplink_seid = vsi->uplink_seid;
2897 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2898 if (ret != I40E_SUCCESS) {
2899 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2900 goto fail_msix_alloc;
2902 (void)rte_memcpy(&vsi->info, &ctxt.info,
2903 sizeof(struct i40e_aqc_vsi_properties_data));
2904 vsi->vsi_id = ctxt.vsi_number;
2905 vsi->info.valid_sections = 0;
2907 /* Configure tc, enabled TC0 only */
2908 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2910 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2911 goto fail_msix_alloc;
2914 /* TC, queue mapping */
2915 memset(&ctxt, 0, sizeof(ctxt));
2916 vsi->info.valid_sections |=
2917 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2918 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2919 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2920 (void)rte_memcpy(&ctxt.info, &vsi->info,
2921 sizeof(struct i40e_aqc_vsi_properties_data));
2922 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2923 I40E_DEFAULT_TCMAP);
2924 if (ret != I40E_SUCCESS) {
2925 PMD_DRV_LOG(ERR, "Failed to configure "
2926 "TC queue mapping");
2927 goto fail_msix_alloc;
2929 ctxt.seid = vsi->seid;
2930 ctxt.pf_num = hw->pf_id;
2931 ctxt.uplink_seid = vsi->uplink_seid;
2934 /* Update VSI parameters */
2935 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2936 if (ret != I40E_SUCCESS) {
2937 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2938 goto fail_msix_alloc;
2941 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2942 sizeof(vsi->info.tc_mapping));
2943 (void)rte_memcpy(&vsi->info.queue_mapping,
2944 &ctxt.info.queue_mapping,
2945 sizeof(vsi->info.queue_mapping));
2946 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2947 vsi->info.valid_sections = 0;
2949 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2953 * Updating default filter settings are necessary to prevent
2954 * reception of tagged packets.
2955 * Some old firmware configurations load a default macvlan
2956 * filter which accepts both tagged and untagged packets.
2957 * The updating is to use a normal filter instead if needed.
2958 * For NVM 4.2.2 or after, the updating is not needed anymore.
2959 * The firmware with correct configurations load the default
2960 * macvlan filter which is expected and cannot be removed.
2962 i40e_update_default_filter_setting(vsi);
2963 } else if (type == I40E_VSI_SRIOV) {
2964 memset(&ctxt, 0, sizeof(ctxt));
2966 * For other VSI, the uplink_seid equals to uplink VSI's
2967 * uplink_seid since they share same VEB
2969 vsi->uplink_seid = uplink_vsi->uplink_seid;
2970 ctxt.pf_num = hw->pf_id;
2971 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2972 ctxt.uplink_seid = vsi->uplink_seid;
2973 ctxt.connection_type = 0x1;
2974 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2976 /* Configure switch ID */
2977 ctxt.info.valid_sections |=
2978 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2979 ctxt.info.switch_id =
2980 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2981 /* Configure port/vlan */
2982 ctxt.info.valid_sections |=
2983 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2984 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2985 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2986 I40E_DEFAULT_TCMAP);
2987 if (ret != I40E_SUCCESS) {
2988 PMD_DRV_LOG(ERR, "Failed to configure "
2989 "TC queue mapping");
2990 goto fail_msix_alloc;
2992 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2993 ctxt.info.valid_sections |=
2994 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2996 * Since VSI is not created yet, only configure parameter,
2997 * will add vsi below.
2999 } else if (type == I40E_VSI_VMDQ2) {
3000 memset(&ctxt, 0, sizeof(ctxt));
3002 * For other VSI, the uplink_seid equals to uplink VSI's
3003 * uplink_seid since they share same VEB
3005 vsi->uplink_seid = uplink_vsi->uplink_seid;
3006 ctxt.pf_num = hw->pf_id;
3008 ctxt.uplink_seid = vsi->uplink_seid;
3009 ctxt.connection_type = 0x1;
3010 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3012 ctxt.info.valid_sections |=
3013 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3014 /* user_param carries flag to enable loop back */
3016 ctxt.info.switch_id =
3017 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3018 ctxt.info.switch_id |=
3019 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3022 /* Configure port/vlan */
3023 ctxt.info.valid_sections |=
3024 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3025 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3026 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3027 I40E_DEFAULT_TCMAP);
3028 if (ret != I40E_SUCCESS) {
3029 PMD_DRV_LOG(ERR, "Failed to configure "
3030 "TC queue mapping");
3031 goto fail_msix_alloc;
3033 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3034 ctxt.info.valid_sections |=
3035 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3036 } else if (type == I40E_VSI_FDIR) {
3037 vsi->uplink_seid = uplink_vsi->uplink_seid;
3038 ctxt.pf_num = hw->pf_id;
3040 ctxt.uplink_seid = vsi->uplink_seid;
3041 ctxt.connection_type = 0x1; /* regular data port */
3042 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3043 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3044 I40E_DEFAULT_TCMAP);
3045 if (ret != I40E_SUCCESS) {
3046 PMD_DRV_LOG(ERR, "Failed to configure "
3047 "TC queue mapping.");
3048 goto fail_msix_alloc;
3050 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3051 ctxt.info.valid_sections |=
3052 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3054 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3055 goto fail_msix_alloc;
3058 if (vsi->type != I40E_VSI_MAIN) {
3059 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3061 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3062 hw->aq.asq_last_status);
3063 goto fail_msix_alloc;
3065 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3066 vsi->info.valid_sections = 0;
3067 vsi->seid = ctxt.seid;
3068 vsi->vsi_id = ctxt.vsi_number;
3069 vsi->sib_vsi_list.vsi = vsi;
3070 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3071 &vsi->sib_vsi_list, list);
3074 /* MAC/VLAN configuration */
3075 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3076 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3078 ret = i40e_vsi_add_mac(vsi, &filter);
3079 if (ret != I40E_SUCCESS) {
3080 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3081 goto fail_msix_alloc;
3084 /* Get VSI BW information */
3085 i40e_vsi_dump_bw_config(vsi);
3088 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3090 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3096 /* Configure vlan stripping on or off */
3098 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3100 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3101 struct i40e_vsi_context ctxt;
3103 int ret = I40E_SUCCESS;
3105 /* Check if it has been already on or off */
3106 if (vsi->info.valid_sections &
3107 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3109 if ((vsi->info.port_vlan_flags &
3110 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3111 return 0; /* already on */
3113 if ((vsi->info.port_vlan_flags &
3114 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3115 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3116 return 0; /* already off */
3121 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3123 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3124 vsi->info.valid_sections =
3125 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3126 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3127 vsi->info.port_vlan_flags |= vlan_flags;
3128 ctxt.seid = vsi->seid;
3129 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3130 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3132 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3133 on ? "enable" : "disable");
3139 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3141 struct rte_eth_dev_data *data = dev->data;
3144 /* Apply vlan offload setting */
3145 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3147 /* Apply double-vlan setting, not implemented yet */
3149 /* Apply pvid setting */
3150 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3151 data->dev_conf.txmode.hw_vlan_insert_pvid);
3153 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3159 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3161 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3163 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3167 i40e_update_flow_control(struct i40e_hw *hw)
3169 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3170 struct i40e_link_status link_status;
3171 uint32_t rxfc = 0, txfc = 0, reg;
3175 memset(&link_status, 0, sizeof(link_status));
3176 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3177 if (ret != I40E_SUCCESS) {
3178 PMD_DRV_LOG(ERR, "Failed to get link status information");
3179 goto write_reg; /* Disable flow control */
3182 an_info = hw->phy.link_info.an_info;
3183 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3184 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3185 ret = I40E_ERR_NOT_READY;
3186 goto write_reg; /* Disable flow control */
3189 * If link auto negotiation is enabled, flow control needs to
3190 * be configured according to it
3192 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3193 case I40E_LINK_PAUSE_RXTX:
3196 hw->fc.current_mode = I40E_FC_FULL;
3198 case I40E_AQ_LINK_PAUSE_RX:
3200 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3202 case I40E_AQ_LINK_PAUSE_TX:
3204 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3207 hw->fc.current_mode = I40E_FC_NONE;
3212 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3213 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3214 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3215 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3216 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3217 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3224 i40e_pf_setup(struct i40e_pf *pf)
3226 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3227 struct i40e_filter_control_settings settings;
3228 struct i40e_vsi *vsi;
3231 /* Clear all stats counters */
3232 pf->offset_loaded = FALSE;
3233 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3234 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3236 ret = i40e_pf_get_switch_config(pf);
3237 if (ret != I40E_SUCCESS) {
3238 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3241 if (pf->flags & I40E_FLAG_FDIR) {
3242 /* make queue allocated first, let FDIR use queue pair 0*/
3243 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3244 if (ret != I40E_FDIR_QUEUE_ID) {
3245 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3247 pf->flags &= ~I40E_FLAG_FDIR;
3250 /* main VSI setup */
3251 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3253 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3254 return I40E_ERR_NOT_READY;
3258 /* setup FDIR after main vsi created.*/
3259 if (pf->flags & I40E_FLAG_FDIR) {
3260 ret = i40e_fdir_setup(pf);
3261 if (ret != I40E_SUCCESS) {
3262 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
3263 pf->flags &= ~I40E_FLAG_FDIR;
3267 /* Configure filter control */
3268 memset(&settings, 0, sizeof(settings));
3269 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3270 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3271 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3272 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3274 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3275 hw->func_caps.rss_table_size);
3276 return I40E_ERR_PARAM;
3278 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3279 "size: %u\n", hw->func_caps.rss_table_size);
3280 pf->hash_lut_size = hw->func_caps.rss_table_size;
3282 /* Enable ethtype and macvlan filters */
3283 settings.enable_ethtype = TRUE;
3284 settings.enable_macvlan = TRUE;
3285 ret = i40e_set_filter_control(hw, &settings);
3287 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3290 /* Update flow control according to the auto negotiation */
3291 i40e_update_flow_control(hw);
3293 return I40E_SUCCESS;
3297 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3303 * Set or clear TX Queue Disable flags,
3304 * which is required by hardware.
3306 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3307 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3309 /* Wait until the request is finished */
3310 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3311 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3312 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3313 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3314 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3320 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3321 return I40E_SUCCESS; /* already on, skip next steps */
3323 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3324 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3326 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3327 return I40E_SUCCESS; /* already off, skip next steps */
3328 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3330 /* Write the register */
3331 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3332 /* Check the result */
3333 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3334 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3335 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3337 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3338 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3341 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3342 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3346 /* Check if it is timeout */
3347 if (j >= I40E_CHK_Q_ENA_COUNT) {
3348 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3349 (on ? "enable" : "disable"), q_idx);
3350 return I40E_ERR_TIMEOUT;
3353 return I40E_SUCCESS;
3356 /* Swith on or off the tx queues */
3358 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3360 struct rte_eth_dev_data *dev_data = pf->dev_data;
3361 struct i40e_tx_queue *txq;
3362 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3366 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3367 txq = dev_data->tx_queues[i];
3368 /* Don't operate the queue if not configured or
3369 * if starting only per queue */
3370 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3373 ret = i40e_dev_tx_queue_start(dev, i);
3375 ret = i40e_dev_tx_queue_stop(dev, i);
3376 if ( ret != I40E_SUCCESS)
3380 return I40E_SUCCESS;
3384 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3389 /* Wait until the request is finished */
3390 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3391 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3392 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3393 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3394 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3399 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3400 return I40E_SUCCESS; /* Already on, skip next steps */
3401 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3403 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3404 return I40E_SUCCESS; /* Already off, skip next steps */
3405 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3408 /* Write the register */
3409 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3410 /* Check the result */
3411 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3412 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3413 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3415 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3416 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3419 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3420 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3425 /* Check if it is timeout */
3426 if (j >= I40E_CHK_Q_ENA_COUNT) {
3427 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3428 (on ? "enable" : "disable"), q_idx);
3429 return I40E_ERR_TIMEOUT;
3432 return I40E_SUCCESS;
3434 /* Switch on or off the rx queues */
3436 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3438 struct rte_eth_dev_data *dev_data = pf->dev_data;
3439 struct i40e_rx_queue *rxq;
3440 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3444 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3445 rxq = dev_data->rx_queues[i];
3446 /* Don't operate the queue if not configured or
3447 * if starting only per queue */
3448 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3451 ret = i40e_dev_rx_queue_start(dev, i);
3453 ret = i40e_dev_rx_queue_stop(dev, i);
3454 if (ret != I40E_SUCCESS)
3458 return I40E_SUCCESS;
3461 /* Switch on or off all the rx/tx queues */
3463 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3468 /* enable rx queues before enabling tx queues */
3469 ret = i40e_dev_switch_rx_queues(pf, on);
3471 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3474 ret = i40e_dev_switch_tx_queues(pf, on);
3476 /* Stop tx queues before stopping rx queues */
3477 ret = i40e_dev_switch_tx_queues(pf, on);
3479 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3482 ret = i40e_dev_switch_rx_queues(pf, on);
3488 /* Initialize VSI for TX */
3490 i40e_dev_tx_init(struct i40e_pf *pf)
3492 struct rte_eth_dev_data *data = pf->dev_data;
3494 uint32_t ret = I40E_SUCCESS;
3495 struct i40e_tx_queue *txq;
3497 for (i = 0; i < data->nb_tx_queues; i++) {
3498 txq = data->tx_queues[i];
3499 if (!txq || !txq->q_set)
3501 ret = i40e_tx_queue_init(txq);
3502 if (ret != I40E_SUCCESS)
3509 /* Initialize VSI for RX */
3511 i40e_dev_rx_init(struct i40e_pf *pf)
3513 struct rte_eth_dev_data *data = pf->dev_data;
3514 int ret = I40E_SUCCESS;
3516 struct i40e_rx_queue *rxq;
3518 i40e_pf_config_mq_rx(pf);
3519 for (i = 0; i < data->nb_rx_queues; i++) {
3520 rxq = data->rx_queues[i];
3521 if (!rxq || !rxq->q_set)
3524 ret = i40e_rx_queue_init(rxq);
3525 if (ret != I40E_SUCCESS) {
3526 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3536 i40e_dev_rxtx_init(struct i40e_pf *pf)
3540 err = i40e_dev_tx_init(pf);
3542 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3545 err = i40e_dev_rx_init(pf);
3547 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3555 i40e_vmdq_setup(struct rte_eth_dev *dev)
3557 struct rte_eth_conf *conf = &dev->data->dev_conf;
3558 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3559 int i, err, conf_vsis, j, loop;
3560 struct i40e_vsi *vsi;
3561 struct i40e_vmdq_info *vmdq_info;
3562 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3563 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3566 * Disable interrupt to avoid message from VF. Furthermore, it will
3567 * avoid race condition in VSI creation/destroy.
3569 i40e_pf_disable_irq0(hw);
3571 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3572 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3576 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3577 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3578 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3579 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3580 pf->max_nb_vmdq_vsi);
3584 if (pf->vmdq != NULL) {
3585 PMD_INIT_LOG(INFO, "VMDQ already configured");
3589 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3590 sizeof(*vmdq_info) * conf_vsis, 0);
3592 if (pf->vmdq == NULL) {
3593 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3597 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3599 /* Create VMDQ VSI */
3600 for (i = 0; i < conf_vsis; i++) {
3601 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3602 vmdq_conf->enable_loop_back);
3604 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3608 vmdq_info = &pf->vmdq[i];
3610 vmdq_info->vsi = vsi;
3612 pf->nb_cfg_vmdq_vsi = conf_vsis;
3614 /* Configure Vlan */
3615 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3616 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3617 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3618 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3619 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3620 vmdq_conf->pool_map[i].vlan_id, j);
3622 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3623 vmdq_conf->pool_map[i].vlan_id);
3625 PMD_INIT_LOG(ERR, "Failed to add vlan");
3633 i40e_pf_enable_irq0(hw);
3638 for (i = 0; i < conf_vsis; i++)
3639 if (pf->vmdq[i].vsi == NULL)
3642 i40e_vsi_release(pf->vmdq[i].vsi);
3646 i40e_pf_enable_irq0(hw);
3651 i40e_stat_update_32(struct i40e_hw *hw,
3659 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3663 if (new_data >= *offset)
3664 *stat = (uint64_t)(new_data - *offset);
3666 *stat = (uint64_t)((new_data +
3667 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3671 i40e_stat_update_48(struct i40e_hw *hw,
3680 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3681 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3682 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3687 if (new_data >= *offset)
3688 *stat = new_data - *offset;
3690 *stat = (uint64_t)((new_data +
3691 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3693 *stat &= I40E_48_BIT_MASK;
3698 i40e_pf_disable_irq0(struct i40e_hw *hw)
3700 /* Disable all interrupt types */
3701 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3702 I40E_WRITE_FLUSH(hw);
3707 i40e_pf_enable_irq0(struct i40e_hw *hw)
3709 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3710 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3711 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3712 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3713 I40E_WRITE_FLUSH(hw);
3717 i40e_pf_config_irq0(struct i40e_hw *hw)
3719 /* read pending request and disable first */
3720 i40e_pf_disable_irq0(hw);
3721 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3722 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3723 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3725 /* Link no queues with irq0 */
3726 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3727 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3731 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3737 uint32_t index, offset, val;
3742 * Try to find which VF trigger a reset, use absolute VF id to access
3743 * since the reg is global register.
3745 for (i = 0; i < pf->vf_num; i++) {
3746 abs_vf_id = hw->func_caps.vf_base_id + i;
3747 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3748 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3749 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3750 /* VFR event occured */
3751 if (val & (0x1 << offset)) {
3754 /* Clear the event first */
3755 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3757 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3759 * Only notify a VF reset event occured,
3760 * don't trigger another SW reset
3762 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3763 if (ret != I40E_SUCCESS)
3764 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3770 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773 struct i40e_arq_event_info info;
3774 uint16_t pending, opcode;
3777 info.buf_len = I40E_AQ_BUF_SZ;
3778 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3779 if (!info.msg_buf) {
3780 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3786 ret = i40e_clean_arq_element(hw, &info, &pending);
3788 if (ret != I40E_SUCCESS) {
3789 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3790 "aq_err: %u", hw->aq.asq_last_status);
3793 opcode = rte_le_to_cpu_16(info.desc.opcode);
3796 case i40e_aqc_opc_send_msg_to_pf:
3797 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3798 i40e_pf_host_handle_vf_msg(dev,
3799 rte_le_to_cpu_16(info.desc.retval),
3800 rte_le_to_cpu_32(info.desc.cookie_high),
3801 rte_le_to_cpu_32(info.desc.cookie_low),
3806 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3811 rte_free(info.msg_buf);
3815 * Interrupt handler is registered as the alarm callback for handling LSC
3816 * interrupt in a definite of time, in order to wait the NIC into a stable
3817 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3818 * no need for link down interrupt.
3821 i40e_dev_interrupt_delayed_handler(void *param)
3823 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827 /* read interrupt causes again */
3828 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3830 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3831 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3832 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3833 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3834 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3835 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3836 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3837 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3838 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3839 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3840 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3842 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3843 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3844 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3845 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3846 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3848 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3849 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3850 i40e_dev_handle_vfr_event(dev);
3852 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3853 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3854 i40e_dev_handle_aq_msg(dev);
3857 /* handle the link up interrupt in an alarm callback */
3858 i40e_dev_link_update(dev, 0);
3859 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3861 i40e_pf_enable_irq0(hw);
3862 rte_intr_enable(&(dev->pci_dev->intr_handle));
3866 * Interrupt handler triggered by NIC for handling
3867 * specific interrupt.
3870 * Pointer to interrupt handle.
3872 * The address of parameter (struct rte_eth_dev *) regsitered before.
3878 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3881 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885 /* Disable interrupt */
3886 i40e_pf_disable_irq0(hw);
3888 /* read out interrupt causes */
3889 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3891 /* No interrupt event indicated */
3892 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3893 PMD_DRV_LOG(INFO, "No interrupt event");
3896 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3897 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3898 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3899 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3900 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3901 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3902 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3903 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3904 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3905 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3906 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3907 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3908 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3909 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3910 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3911 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3913 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3914 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3915 i40e_dev_handle_vfr_event(dev);
3917 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3918 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3919 i40e_dev_handle_aq_msg(dev);
3922 /* Link Status Change interrupt */
3923 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3924 #define I40E_US_PER_SECOND 1000000
3925 struct rte_eth_link link;
3927 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3928 memset(&link, 0, sizeof(link));
3929 rte_i40e_dev_atomic_read_link_status(dev, &link);
3930 i40e_dev_link_update(dev, 0);
3933 * For link up interrupt, it needs to wait 1 second to let the
3934 * hardware be a stable state. Otherwise several consecutive
3935 * interrupts can be observed.
3936 * For link down interrupt, no need to wait.
3938 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3939 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3942 _rte_eth_dev_callback_process(dev,
3943 RTE_ETH_EVENT_INTR_LSC);
3947 /* Enable interrupt */
3948 i40e_pf_enable_irq0(hw);
3949 rte_intr_enable(&(dev->pci_dev->intr_handle));
3953 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3954 struct i40e_macvlan_filter *filter,
3957 int ele_num, ele_buff_size;
3958 int num, actual_num, i;
3960 int ret = I40E_SUCCESS;
3961 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3962 struct i40e_aqc_add_macvlan_element_data *req_list;
3964 if (filter == NULL || total == 0)
3965 return I40E_ERR_PARAM;
3966 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3967 ele_buff_size = hw->aq.asq_buf_size;
3969 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3970 if (req_list == NULL) {
3971 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3972 return I40E_ERR_NO_MEMORY;
3977 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3978 memset(req_list, 0, ele_buff_size);
3980 for (i = 0; i < actual_num; i++) {
3981 (void)rte_memcpy(req_list[i].mac_addr,
3982 &filter[num + i].macaddr, ETH_ADDR_LEN);
3983 req_list[i].vlan_tag =
3984 rte_cpu_to_le_16(filter[num + i].vlan_id);
3986 switch (filter[num + i].filter_type) {
3987 case RTE_MAC_PERFECT_MATCH:
3988 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3989 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3991 case RTE_MACVLAN_PERFECT_MATCH:
3992 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3994 case RTE_MAC_HASH_MATCH:
3995 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3996 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3998 case RTE_MACVLAN_HASH_MATCH:
3999 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4002 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4003 ret = I40E_ERR_PARAM;
4007 req_list[i].queue_number = 0;
4009 req_list[i].flags = rte_cpu_to_le_16(flags);
4012 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4014 if (ret != I40E_SUCCESS) {
4015 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4019 } while (num < total);
4027 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4028 struct i40e_macvlan_filter *filter,
4031 int ele_num, ele_buff_size;
4032 int num, actual_num, i;
4034 int ret = I40E_SUCCESS;
4035 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4036 struct i40e_aqc_remove_macvlan_element_data *req_list;
4038 if (filter == NULL || total == 0)
4039 return I40E_ERR_PARAM;
4041 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4042 ele_buff_size = hw->aq.asq_buf_size;
4044 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4045 if (req_list == NULL) {
4046 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4047 return I40E_ERR_NO_MEMORY;
4052 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4053 memset(req_list, 0, ele_buff_size);
4055 for (i = 0; i < actual_num; i++) {
4056 (void)rte_memcpy(req_list[i].mac_addr,
4057 &filter[num + i].macaddr, ETH_ADDR_LEN);
4058 req_list[i].vlan_tag =
4059 rte_cpu_to_le_16(filter[num + i].vlan_id);
4061 switch (filter[num + i].filter_type) {
4062 case RTE_MAC_PERFECT_MATCH:
4063 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4064 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4066 case RTE_MACVLAN_PERFECT_MATCH:
4067 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4069 case RTE_MAC_HASH_MATCH:
4070 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4071 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4073 case RTE_MACVLAN_HASH_MATCH:
4074 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4077 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4078 ret = I40E_ERR_PARAM;
4081 req_list[i].flags = rte_cpu_to_le_16(flags);
4084 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4086 if (ret != I40E_SUCCESS) {
4087 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4091 } while (num < total);
4098 /* Find out specific MAC filter */
4099 static struct i40e_mac_filter *
4100 i40e_find_mac_filter(struct i40e_vsi *vsi,
4101 struct ether_addr *macaddr)
4103 struct i40e_mac_filter *f;
4105 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4106 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4114 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4117 uint32_t vid_idx, vid_bit;
4119 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4120 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4122 if (vsi->vfta[vid_idx] & vid_bit)
4129 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4130 uint16_t vlan_id, bool on)
4132 uint32_t vid_idx, vid_bit;
4134 #define UINT32_BIT_MASK 0x1F
4135 #define VALID_VLAN_BIT_MASK 0xFFF
4136 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4137 * element first, then find the bits it belongs to
4139 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4141 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4144 vsi->vfta[vid_idx] |= vid_bit;
4146 vsi->vfta[vid_idx] &= ~vid_bit;
4150 * Find all vlan options for specific mac addr,
4151 * return with actual vlan found.
4154 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4155 struct i40e_macvlan_filter *mv_f,
4156 int num, struct ether_addr *addr)
4162 * Not to use i40e_find_vlan_filter to decrease the loop time,
4163 * although the code looks complex.
4165 if (num < vsi->vlan_num)
4166 return I40E_ERR_PARAM;
4169 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4171 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4172 if (vsi->vfta[j] & (1 << k)) {
4174 PMD_DRV_LOG(ERR, "vlan number "
4176 return I40E_ERR_PARAM;
4178 (void)rte_memcpy(&mv_f[i].macaddr,
4179 addr, ETH_ADDR_LEN);
4181 j * I40E_UINT32_BIT_SIZE + k;
4187 return I40E_SUCCESS;
4191 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4192 struct i40e_macvlan_filter *mv_f,
4197 struct i40e_mac_filter *f;
4199 if (num < vsi->mac_num)
4200 return I40E_ERR_PARAM;
4202 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4204 PMD_DRV_LOG(ERR, "buffer number not match");
4205 return I40E_ERR_PARAM;
4207 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4209 mv_f[i].vlan_id = vlan;
4210 mv_f[i].filter_type = f->mac_info.filter_type;
4214 return I40E_SUCCESS;
4218 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4221 struct i40e_mac_filter *f;
4222 struct i40e_macvlan_filter *mv_f;
4223 int ret = I40E_SUCCESS;
4225 if (vsi == NULL || vsi->mac_num == 0)
4226 return I40E_ERR_PARAM;
4228 /* Case that no vlan is set */
4229 if (vsi->vlan_num == 0)
4232 num = vsi->mac_num * vsi->vlan_num;
4234 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4236 PMD_DRV_LOG(ERR, "failed to allocate memory");
4237 return I40E_ERR_NO_MEMORY;
4241 if (vsi->vlan_num == 0) {
4242 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4243 (void)rte_memcpy(&mv_f[i].macaddr,
4244 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4245 mv_f[i].vlan_id = 0;
4249 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4250 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4251 vsi->vlan_num, &f->mac_info.mac_addr);
4252 if (ret != I40E_SUCCESS)
4258 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4266 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4268 struct i40e_macvlan_filter *mv_f;
4270 int ret = I40E_SUCCESS;
4272 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4273 return I40E_ERR_PARAM;
4275 /* If it's already set, just return */
4276 if (i40e_find_vlan_filter(vsi,vlan))
4277 return I40E_SUCCESS;
4279 mac_num = vsi->mac_num;
4282 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4283 return I40E_ERR_PARAM;
4286 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4289 PMD_DRV_LOG(ERR, "failed to allocate memory");
4290 return I40E_ERR_NO_MEMORY;
4293 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4295 if (ret != I40E_SUCCESS)
4298 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4300 if (ret != I40E_SUCCESS)
4303 i40e_set_vlan_filter(vsi, vlan, 1);
4313 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4315 struct i40e_macvlan_filter *mv_f;
4317 int ret = I40E_SUCCESS;
4320 * Vlan 0 is the generic filter for untagged packets
4321 * and can't be removed.
4323 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4324 return I40E_ERR_PARAM;
4326 /* If can't find it, just return */
4327 if (!i40e_find_vlan_filter(vsi, vlan))
4328 return I40E_ERR_PARAM;
4330 mac_num = vsi->mac_num;
4333 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4334 return I40E_ERR_PARAM;
4337 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4340 PMD_DRV_LOG(ERR, "failed to allocate memory");
4341 return I40E_ERR_NO_MEMORY;
4344 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4346 if (ret != I40E_SUCCESS)
4349 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4351 if (ret != I40E_SUCCESS)
4354 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4355 if (vsi->vlan_num == 1) {
4356 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4357 if (ret != I40E_SUCCESS)
4360 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4361 if (ret != I40E_SUCCESS)
4365 i40e_set_vlan_filter(vsi, vlan, 0);
4375 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4377 struct i40e_mac_filter *f;
4378 struct i40e_macvlan_filter *mv_f;
4379 int i, vlan_num = 0;
4380 int ret = I40E_SUCCESS;
4382 /* If it's add and we've config it, return */
4383 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4385 return I40E_SUCCESS;
4386 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4387 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4390 * If vlan_num is 0, that's the first time to add mac,
4391 * set mask for vlan_id 0.
4393 if (vsi->vlan_num == 0) {
4394 i40e_set_vlan_filter(vsi, 0, 1);
4397 vlan_num = vsi->vlan_num;
4398 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4399 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4402 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4404 PMD_DRV_LOG(ERR, "failed to allocate memory");
4405 return I40E_ERR_NO_MEMORY;
4408 for (i = 0; i < vlan_num; i++) {
4409 mv_f[i].filter_type = mac_filter->filter_type;
4410 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4414 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4415 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4416 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4417 &mac_filter->mac_addr);
4418 if (ret != I40E_SUCCESS)
4422 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4423 if (ret != I40E_SUCCESS)
4426 /* Add the mac addr into mac list */
4427 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4429 PMD_DRV_LOG(ERR, "failed to allocate memory");
4430 ret = I40E_ERR_NO_MEMORY;
4433 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4435 f->mac_info.filter_type = mac_filter->filter_type;
4436 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4447 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4449 struct i40e_mac_filter *f;
4450 struct i40e_macvlan_filter *mv_f;
4452 enum rte_mac_filter_type filter_type;
4453 int ret = I40E_SUCCESS;
4455 /* Can't find it, return an error */
4456 f = i40e_find_mac_filter(vsi, addr);
4458 return I40E_ERR_PARAM;
4460 vlan_num = vsi->vlan_num;
4461 filter_type = f->mac_info.filter_type;
4462 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4463 filter_type == RTE_MACVLAN_HASH_MATCH) {
4464 if (vlan_num == 0) {
4465 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4466 return I40E_ERR_PARAM;
4468 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4469 filter_type == RTE_MAC_HASH_MATCH)
4472 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4474 PMD_DRV_LOG(ERR, "failed to allocate memory");
4475 return I40E_ERR_NO_MEMORY;
4478 for (i = 0; i < vlan_num; i++) {
4479 mv_f[i].filter_type = filter_type;
4480 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4483 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4484 filter_type == RTE_MACVLAN_HASH_MATCH) {
4485 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4486 if (ret != I40E_SUCCESS)
4490 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4491 if (ret != I40E_SUCCESS)
4494 /* Remove the mac addr into mac list */
4495 TAILQ_REMOVE(&vsi->mac_list, f, next);
4505 /* Configure hash enable flags for RSS */
4507 i40e_config_hena(uint64_t flags)
4514 if (flags & ETH_RSS_NONF_IPV4_UDP)
4515 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4516 if (flags & ETH_RSS_NONF_IPV4_TCP)
4517 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4518 if (flags & ETH_RSS_NONF_IPV4_SCTP)
4519 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4520 if (flags & ETH_RSS_NONF_IPV4_OTHER)
4521 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4522 if (flags & ETH_RSS_FRAG_IPV4)
4523 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4524 if (flags & ETH_RSS_NONF_IPV6_UDP)
4525 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4526 if (flags & ETH_RSS_NONF_IPV6_TCP)
4527 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4528 if (flags & ETH_RSS_NONF_IPV6_SCTP)
4529 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4530 if (flags & ETH_RSS_NONF_IPV6_OTHER)
4531 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4532 if (flags & ETH_RSS_FRAG_IPV6)
4533 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4534 if (flags & ETH_RSS_L2_PAYLOAD)
4535 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4540 /* Parse the hash enable flags */
4542 i40e_parse_hena(uint64_t flags)
4544 uint64_t rss_hf = 0;
4549 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4550 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4551 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4552 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4553 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4554 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4555 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4556 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4557 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4558 rss_hf |= ETH_RSS_FRAG_IPV4;
4559 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4560 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4561 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4562 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4563 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4564 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4565 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4566 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4567 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4568 rss_hf |= ETH_RSS_FRAG_IPV6;
4569 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4570 rss_hf |= ETH_RSS_L2_PAYLOAD;
4577 i40e_pf_disable_rss(struct i40e_pf *pf)
4579 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4582 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4583 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4584 hena &= ~I40E_RSS_HENA_ALL;
4585 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4586 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4587 I40E_WRITE_FLUSH(hw);
4591 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4594 uint8_t hash_key_len;
4599 hash_key = (uint32_t *)(rss_conf->rss_key);
4600 hash_key_len = rss_conf->rss_key_len;
4601 if (hash_key != NULL && hash_key_len >=
4602 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4603 /* Fill in RSS hash key */
4604 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4605 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4608 rss_hf = rss_conf->rss_hf;
4609 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4610 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4611 hena &= ~I40E_RSS_HENA_ALL;
4612 hena |= i40e_config_hena(rss_hf);
4613 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4614 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4615 I40E_WRITE_FLUSH(hw);
4621 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4622 struct rte_eth_rss_conf *rss_conf)
4624 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4628 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4629 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4630 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4631 if (rss_hf != 0) /* Enable RSS */
4633 return 0; /* Nothing to do */
4636 if (rss_hf == 0) /* Disable RSS */
4639 return i40e_hw_rss_hash_set(hw, rss_conf);
4643 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4644 struct rte_eth_rss_conf *rss_conf)
4646 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4651 if (hash_key != NULL) {
4652 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4653 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4654 rss_conf->rss_key_len = i * sizeof(uint32_t);
4656 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4657 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4658 rss_conf->rss_hf = i40e_parse_hena(hena);
4664 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4666 switch (filter_type) {
4667 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4668 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4670 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4671 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4673 case RTE_TUNNEL_FILTER_IMAC_TENID:
4674 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4676 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4677 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4679 case ETH_TUNNEL_FILTER_IMAC:
4680 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4683 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4691 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4692 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4696 uint8_t tun_type = 0;
4698 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4699 struct i40e_vsi *vsi = pf->main_vsi;
4700 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4701 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4703 cld_filter = rte_zmalloc("tunnel_filter",
4704 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4707 if (NULL == cld_filter) {
4708 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4711 pfilter = cld_filter;
4713 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4714 sizeof(struct ether_addr));
4715 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4716 sizeof(struct ether_addr));
4718 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4719 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4720 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4721 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4722 &tunnel_filter->ip_addr,
4723 sizeof(pfilter->ipaddr.v4.data));
4725 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4726 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4727 &tunnel_filter->ip_addr,
4728 sizeof(pfilter->ipaddr.v6.data));
4731 /* check tunneled type */
4732 switch (tunnel_filter->tunnel_type) {
4733 case RTE_TUNNEL_TYPE_VXLAN:
4734 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4737 /* Other tunnel types is not supported. */
4738 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4739 rte_free(cld_filter);
4743 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4746 rte_free(cld_filter);
4750 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4751 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4752 pfilter->tenant_id = tunnel_filter->tenant_id;
4753 pfilter->queue_number = tunnel_filter->queue_id;
4756 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4758 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4761 rte_free(cld_filter);
4766 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4770 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4771 if (pf->vxlan_ports[i] == port)
4779 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4785 idx = i40e_get_vxlan_port_idx(pf, port);
4787 /* Check if port already exists */
4789 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4793 /* Now check if there is space to add the new port */
4794 idx = i40e_get_vxlan_port_idx(pf, 0);
4796 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4797 "not adding port %d", port);
4801 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4804 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4808 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4811 /* New port: add it and mark its index in the bitmap */
4812 pf->vxlan_ports[idx] = port;
4813 pf->vxlan_bitmap |= (1 << idx);
4815 if (!(pf->flags & I40E_FLAG_VXLAN))
4816 pf->flags |= I40E_FLAG_VXLAN;
4822 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4825 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4827 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4828 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4832 idx = i40e_get_vxlan_port_idx(pf, port);
4835 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4839 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4840 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4844 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4847 pf->vxlan_ports[idx] = 0;
4848 pf->vxlan_bitmap &= ~(1 << idx);
4850 if (!pf->vxlan_bitmap)
4851 pf->flags &= ~I40E_FLAG_VXLAN;
4856 /* Add UDP tunneling port */
4858 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4859 struct rte_eth_udp_tunnel *udp_tunnel)
4862 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4864 if (udp_tunnel == NULL)
4867 switch (udp_tunnel->prot_type) {
4868 case RTE_TUNNEL_TYPE_VXLAN:
4869 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4872 case RTE_TUNNEL_TYPE_GENEVE:
4873 case RTE_TUNNEL_TYPE_TEREDO:
4874 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4879 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4887 /* Remove UDP tunneling port */
4889 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4890 struct rte_eth_udp_tunnel *udp_tunnel)
4893 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4895 if (udp_tunnel == NULL)
4898 switch (udp_tunnel->prot_type) {
4899 case RTE_TUNNEL_TYPE_VXLAN:
4900 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4902 case RTE_TUNNEL_TYPE_GENEVE:
4903 case RTE_TUNNEL_TYPE_TEREDO:
4904 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4908 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4916 /* Calculate the maximum number of contiguous PF queues that are configured */
4918 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4920 struct rte_eth_dev_data *data = pf->dev_data;
4922 struct i40e_rx_queue *rxq;
4925 for (i = 0; i < pf->lan_nb_qps; i++) {
4926 rxq = data->rx_queues[i];
4927 if (rxq && rxq->q_set)
4938 i40e_pf_config_rss(struct i40e_pf *pf)
4940 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4941 struct rte_eth_rss_conf rss_conf;
4942 uint32_t i, lut = 0;
4946 * If both VMDQ and RSS enabled, not all of PF queues are configured.
4947 * It's necessary to calulate the actual PF queues that are configured.
4949 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4950 num = i40e_pf_calc_configured_queues_num(pf);
4951 num = i40e_align_floor(num);
4953 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4955 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
4959 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
4963 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4966 lut = (lut << 8) | (j & ((0x1 <<
4967 hw->func_caps.rss_table_entry_width) - 1));
4969 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4972 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4973 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4974 i40e_pf_disable_rss(pf);
4977 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4978 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4979 /* Calculate the default hash key */
4980 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4981 rss_key_default[i] = (uint32_t)rte_rand();
4982 rss_conf.rss_key = (uint8_t *)rss_key_default;
4983 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4987 return i40e_hw_rss_hash_set(hw, &rss_conf);
4991 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4992 struct rte_eth_tunnel_filter_conf *filter)
4994 if (pf == NULL || filter == NULL) {
4995 PMD_DRV_LOG(ERR, "Invalid parameter");
4999 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5000 PMD_DRV_LOG(ERR, "Invalid queue ID");
5004 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5005 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5009 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5010 (is_zero_ether_addr(filter->outer_mac))) {
5011 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5015 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5016 (is_zero_ether_addr(filter->inner_mac))) {
5017 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5025 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5028 struct rte_eth_tunnel_filter_conf *filter;
5029 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5030 int ret = I40E_SUCCESS;
5032 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5034 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5035 return I40E_ERR_PARAM;
5037 switch (filter_op) {
5038 case RTE_ETH_FILTER_NOP:
5039 if (!(pf->flags & I40E_FLAG_VXLAN))
5040 ret = I40E_NOT_SUPPORTED;
5041 case RTE_ETH_FILTER_ADD:
5042 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5044 case RTE_ETH_FILTER_DELETE:
5045 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5048 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5049 ret = I40E_ERR_PARAM;
5057 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5060 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5062 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5063 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5068 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5069 ret = i40e_pf_config_rss(pf);
5071 i40e_pf_disable_rss(pf);
5077 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5078 enum rte_filter_type filter_type,
5079 enum rte_filter_op filter_op,
5087 switch (filter_type) {
5088 case RTE_ETH_FILTER_MACVLAN:
5089 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5091 case RTE_ETH_FILTER_TUNNEL:
5092 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5095 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",