lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_TYPE_UDPV4) | \
  98         (1UL << RTE_ETH_FLOW_TYPE_TCPV4) | \
  99         (1UL << RTE_ETH_FLOW_TYPE_SCTPV4) | \
 100         (1UL << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
 102         (1UL << RTE_ETH_FLOW_TYPE_UDPV6) | \
 103         (1UL << RTE_ETH_FLOW_TYPE_TCPV6) | \
 104         (1UL << RTE_ETH_FLOW_TYPE_SCTPV6) | \
 105         (1UL << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
 107
 108 static int eth_i40e_dev_init(\
 109                         __attribute__((unused)) struct eth_driver *eth_drv,
 110                         struct rte_eth_dev *eth_dev);
 111 static int i40e_dev_configure(struct rte_eth_dev *dev);
 112 static int i40e_dev_start(struct rte_eth_dev *dev);
 113 static void i40e_dev_stop(struct rte_eth_dev *dev);
 114 static void i40e_dev_close(struct rte_eth_dev *dev);
 115 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 116 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 117 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 118 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 119 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 120 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 121 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 122                                struct rte_eth_stats *stats);
 123 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 124 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 125                                             uint16_t queue_id,
 126                                             uint8_t stat_idx,
 127                                             uint8_t is_rx);
 128 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 129                               struct rte_eth_dev_info *dev_info);
 130 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 131                                 uint16_t vlan_id,
 132                                 int on);
 133 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 134 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 135 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 136                                       uint16_t queue,
 137                                       int on);
 138 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 139 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 140 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 141 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 142                               struct rte_eth_fc_conf *fc_conf);
 143 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 144                                        struct rte_eth_pfc_conf *pfc_conf);
 145 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 146                           struct ether_addr *mac_addr,
 147                           uint32_t index,
 148                           uint32_t pool);
 149 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 150 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 151                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 152                                     uint16_t reta_size);
 153 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 154                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 155                                    uint16_t reta_size);
 156
 157 static int i40e_get_cap(struct i40e_hw *hw);
 158 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 159 static int i40e_pf_setup(struct i40e_pf *pf);
 160 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 161 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 162 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 163                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 164 static void i40e_stat_update_48(struct i40e_hw *hw,
 165                                uint32_t hireg,
 166                                uint32_t loreg,
 167                                bool offset_loaded,
 168                                uint64_t *offset,
 169                                uint64_t *stat);
 170 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 171 static void i40e_dev_interrupt_handler(
 172                 __rte_unused struct rte_intr_handle *handle, void *param);
 173 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 174                                 uint32_t base, uint32_t num);
 175 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 176 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 177                         uint32_t base);
 178 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 179                         uint16_t num);
 180 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 181 static int i40e_veb_release(struct i40e_veb *veb);
 182 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 183                                                 struct i40e_vsi *vsi);
 184 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 185 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 186 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 187                                              struct i40e_macvlan_filter *mv_f,
 188                                              int num,
 189                                              struct ether_addr *addr);
 190 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 191                                              struct i40e_macvlan_filter *mv_f,
 192                                              int num,
 193                                              uint16_t vlan);
 194 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 195 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 196                                     struct rte_eth_rss_conf *rss_conf);
 197 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 198                                       struct rte_eth_rss_conf *rss_conf);
 199 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 200                                 struct rte_eth_udp_tunnel *udp_tunnel);
 201 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 202                                 struct rte_eth_udp_tunnel *udp_tunnel);
 203 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 204                         struct rte_eth_ethertype_filter *filter,
 205                         bool add);
 206 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 210                                 enum rte_filter_type filter_type,
 211                                 enum rte_filter_op filter_op,
 212                                 void *arg);
 213 static void i40e_configure_registers(struct i40e_hw *hw);
 214 static void i40e_hw_init(struct i40e_hw *hw);
 215
 216 static struct rte_pci_id pci_id_i40e_map[] = {
 217 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 218 #include "rte_pci_dev_ids.h"
 219 { .vendor_id = 0, /* sentinel */ },
 220 };
 221
 222 static struct eth_dev_ops i40e_eth_dev_ops = {
 223         .dev_configure                = i40e_dev_configure,
 224         .dev_start                    = i40e_dev_start,
 225         .dev_stop                     = i40e_dev_stop,
 226         .dev_close                    = i40e_dev_close,
 227         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 228         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 229         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 230         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 231         .dev_set_link_up              = i40e_dev_set_link_up,
 232         .dev_set_link_down            = i40e_dev_set_link_down,
 233         .link_update                  = i40e_dev_link_update,
 234         .stats_get                    = i40e_dev_stats_get,
 235         .stats_reset                  = i40e_dev_stats_reset,
 236         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 237         .dev_infos_get                = i40e_dev_info_get,
 238         .vlan_filter_set              = i40e_vlan_filter_set,
 239         .vlan_tpid_set                = i40e_vlan_tpid_set,
 240         .vlan_offload_set             = i40e_vlan_offload_set,
 241         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 242         .vlan_pvid_set                = i40e_vlan_pvid_set,
 243         .rx_queue_start               = i40e_dev_rx_queue_start,
 244         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 245         .tx_queue_start               = i40e_dev_tx_queue_start,
 246         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 247         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 248         .rx_queue_release             = i40e_dev_rx_queue_release,
 249         .rx_queue_count               = i40e_dev_rx_queue_count,
 250         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 251         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 252         .tx_queue_release             = i40e_dev_tx_queue_release,
 253         .dev_led_on                   = i40e_dev_led_on,
 254         .dev_led_off                  = i40e_dev_led_off,
 255         .flow_ctrl_set                = i40e_flow_ctrl_set,
 256         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 257         .mac_addr_add                 = i40e_macaddr_add,
 258         .mac_addr_remove              = i40e_macaddr_remove,
 259         .reta_update                  = i40e_dev_rss_reta_update,
 260         .reta_query                   = i40e_dev_rss_reta_query,
 261         .rss_hash_update              = i40e_dev_rss_hash_update,
 262         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 263         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 264         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 265         .filter_ctrl                  = i40e_dev_filter_ctrl,
 266 };
 267
 268 static struct eth_driver rte_i40e_pmd = {
 269         {
 270                 .name = "rte_i40e_pmd",
 271                 .id_table = pci_id_i40e_map,
 272                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 273         },
 274         .eth_dev_init = eth_i40e_dev_init,
 275         .dev_private_size = sizeof(struct i40e_adapter),
 276 };
 277
 278 static inline int
 279 i40e_align_floor(int n)
 280 {
 281         if (n == 0)
 282                 return 0;
 283         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 284 }
 285
 286 static inline int
 287 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 288                                      struct rte_eth_link *link)
 289 {
 290         struct rte_eth_link *dst = link;
 291         struct rte_eth_link *src = &(dev->data->dev_link);
 292
 293         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 294                                         *(uint64_t *)src) == 0)
 295                 return -1;
 296
 297         return 0;
 298 }
 299
 300 static inline int
 301 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 302                                       struct rte_eth_link *link)
 303 {
 304         struct rte_eth_link *dst = &(dev->data->dev_link);
 305         struct rte_eth_link *src = link;
 306
 307         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 308                                         *(uint64_t *)src) == 0)
 309                 return -1;
 310
 311         return 0;
 312 }
 313
 314 /*
 315  * Driver initialization routine.
 316  * Invoked once at EAL init time.
 317  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 318  */
 319 static int
 320 rte_i40e_pmd_init(const char *name __rte_unused,
 321                   const char *params __rte_unused)
 322 {
 323         PMD_INIT_FUNC_TRACE();
 324         rte_eth_driver_register(&rte_i40e_pmd);
 325
 326         return 0;
 327 }
 328
 329 static struct rte_driver rte_i40e_driver = {
 330         .type = PMD_PDEV,
 331         .init = rte_i40e_pmd_init,
 332 };
 333
 334 PMD_REGISTER_DRIVER(rte_i40e_driver);
 335
 336 /*
 337  * Initialize registers for flexible payload, which should be set by NVM.
 338  * This should be removed from code once it is fixed in NVM.
 339  */
 340 #ifndef I40E_GLQF_ORT
 341 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 342 #endif
 343 #ifndef I40E_GLQF_PIT
 344 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 345 #endif
 346
 347 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 348 {
 349         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 359
 360         /* GLQF_PIT Registers */
 361         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 362         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 363 }
 364
 365 static int
 366 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 367                   struct rte_eth_dev *dev)
 368 {
 369         struct rte_pci_device *pci_dev;
 370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 372         struct i40e_vsi *vsi;
 373         int ret;
 374         uint32_t len;
 375         uint8_t aq_fail = 0;
 376
 377         PMD_INIT_FUNC_TRACE();
 378
 379         dev->dev_ops = &i40e_eth_dev_ops;
 380         dev->rx_pkt_burst = i40e_recv_pkts;
 381         dev->tx_pkt_burst = i40e_xmit_pkts;
 382
 383         /* for secondary processes, we don't initialise any further as primary
 384          * has already done this work. Only check we don't need a different
 385          * RX function */
 386         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 387                 if (dev->data->scattered_rx)
 388                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 389                 return 0;
 390         }
 391         pci_dev = dev->pci_dev;
 392         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 393         pf->adapter->eth_dev = dev;
 394         pf->dev_data = dev->data;
 395
 396         hw->back = I40E_PF_TO_ADAPTER(pf);
 397         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 398         if (!hw->hw_addr) {
 399                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 400                              "as address is NULL");
 401                 return -ENODEV;
 402         }
 403
 404         hw->vendor_id = pci_dev->id.vendor_id;
 405         hw->device_id = pci_dev->id.device_id;
 406         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 407         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 408         hw->bus.device = pci_dev->addr.devid;
 409         hw->bus.func = pci_dev->addr.function;
 410
 411         /* Make sure all is clean before doing PF reset */
 412         i40e_clear_hw(hw);
 413
 414         /* Initialize the hardware */
 415         i40e_hw_init(hw);
 416
 417         /* Reset here to make sure all is clean for each PF */
 418         ret = i40e_pf_reset(hw);
 419         if (ret) {
 420                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 421                 return ret;
 422         }
 423
 424         /* Initialize the shared code (base driver) */
 425         ret = i40e_init_shared_code(hw);
 426         if (ret) {
 427                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 428                 return ret;
 429         }
 430
 431         /*
 432          * To work around the NVM issue,initialize registers
 433          * for flexible payload by software.
 434          * It should be removed once issues are fixed in NVM.
 435          */
 436         i40e_flex_payload_reg_init(hw);
 437
 438         /* Initialize the parameters for adminq */
 439         i40e_init_adminq_parameter(hw);
 440         ret = i40e_init_adminq(hw);
 441         if (ret != I40E_SUCCESS) {
 442                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 443                 return -EIO;
 444         }
 445         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 446                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 447                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 448                      ((hw->nvm.version >> 12) & 0xf),
 449                      ((hw->nvm.version >> 4) & 0xff),
 450                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 451
 452         /* Disable LLDP */
 453         ret = i40e_aq_stop_lldp(hw, true, NULL);
 454         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 455                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 456
 457         /* Clear PXE mode */
 458         i40e_clear_pxe_mode(hw);
 459
 460         /*
 461          * On X710, performance number is far from the expectation on recent
 462          * firmware versions. The fix for this issue may not be integrated in
 463          * the following firmware version. So the workaround in software driver
 464          * is needed. It needs to modify the initial values of 3 internal only
 465          * registers. Note that the workaround can be removed when it is fixed
 466          * in firmware in the future.
 467          */
 468         i40e_configure_registers(hw);
 469
 470         /* Get hw capabilities */
 471         ret = i40e_get_cap(hw);
 472         if (ret != I40E_SUCCESS) {
 473                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 474                 goto err_get_capabilities;
 475         }
 476
 477         /* Initialize parameters for PF */
 478         ret = i40e_pf_parameter_init(dev);
 479         if (ret != 0) {
 480                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 481                 goto err_parameter_init;
 482         }
 483
 484         /* Initialize the queue management */
 485         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 486         if (ret < 0) {
 487                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 488                 goto err_qp_pool_init;
 489         }
 490         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 491                                 hw->func_caps.num_msix_vectors - 1);
 492         if (ret < 0) {
 493                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 494                 goto err_msix_pool_init;
 495         }
 496
 497         /* Initialize lan hmc */
 498         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 499                                 hw->func_caps.num_rx_qp, 0, 0);
 500         if (ret != I40E_SUCCESS) {
 501                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 502                 goto err_init_lan_hmc;
 503         }
 504
 505         /* Configure lan hmc */
 506         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 507         if (ret != I40E_SUCCESS) {
 508                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 509                 goto err_configure_lan_hmc;
 510         }
 511
 512         /* Get and check the mac address */
 513         i40e_get_mac_addr(hw, hw->mac.addr);
 514         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 515                 PMD_INIT_LOG(ERR, "mac address is not valid");
 516                 ret = -EIO;
 517                 goto err_get_mac_addr;
 518         }
 519         /* Copy the permanent MAC address */
 520         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 521                         (struct ether_addr *) hw->mac.perm_addr);
 522
 523         /* Disable flow control */
 524         hw->fc.requested_mode = I40E_FC_NONE;
 525         i40e_set_fc(hw, &aq_fail, TRUE);
 526
 527         /* PF setup, which includes VSI setup */
 528         ret = i40e_pf_setup(pf);
 529         if (ret) {
 530                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 531                 goto err_setup_pf_switch;
 532         }
 533
 534         vsi = pf->main_vsi;
 535
 536         /* Disable double vlan by default */
 537         i40e_vsi_config_double_vlan(vsi, FALSE);
 538
 539         if (!vsi->max_macaddrs)
 540                 len = ETHER_ADDR_LEN;
 541         else
 542                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 543
 544         /* Should be after VSI initialized */
 545         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 546         if (!dev->data->mac_addrs) {
 547                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 548                                         "for storing mac address");
 549                 goto err_mac_alloc;
 550         }
 551         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 552                                         &dev->data->mac_addrs[0]);
 553
 554         /* initialize pf host driver to setup SRIOV resource if applicable */
 555         i40e_pf_host_init(dev);
 556
 557         /* register callback func to eal lib */
 558         rte_intr_callback_register(&(pci_dev->intr_handle),
 559                 i40e_dev_interrupt_handler, (void *)dev);
 560
 561         /* configure and enable device interrupt */
 562         i40e_pf_config_irq0(hw);
 563         i40e_pf_enable_irq0(hw);
 564
 565         /* enable uio intr after callback register */
 566         rte_intr_enable(&(pci_dev->intr_handle));
 567
 568         return 0;
 569
 570 err_mac_alloc:
 571         i40e_vsi_release(pf->main_vsi);
 572 err_setup_pf_switch:
 573 err_get_mac_addr:
 574 err_configure_lan_hmc:
 575         (void)i40e_shutdown_lan_hmc(hw);
 576 err_init_lan_hmc:
 577         i40e_res_pool_destroy(&pf->msix_pool);
 578 err_msix_pool_init:
 579         i40e_res_pool_destroy(&pf->qp_pool);
 580 err_qp_pool_init:
 581 err_parameter_init:
 582 err_get_capabilities:
 583         (void)i40e_shutdown_adminq(hw);
 584
 585         return ret;
 586 }
 587
 588 static int
 589 i40e_dev_configure(struct rte_eth_dev *dev)
 590 {
 591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 592         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 593         int ret;
 594
 595         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 596                 ret = i40e_fdir_setup(pf);
 597                 if (ret != I40E_SUCCESS) {
 598                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 599                         return -ENOTSUP;
 600                 }
 601                 ret = i40e_fdir_configure(dev);
 602                 if (ret < 0) {
 603                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 604                         goto err;
 605                 }
 606         } else
 607                 i40e_fdir_teardown(pf);
 608
 609         ret = i40e_dev_init_vlan(dev);
 610         if (ret < 0)
 611                 goto err;
 612
 613         /* VMDQ setup.
 614          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 615          *  RSS setting have different requirements.
 616          *  General PMD driver call sequence are NIC init, configure,
 617          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 618          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 619          *  applicable. So, VMDQ setting has to be done before
 620          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 621          *  For RSS setting, it will try to calculate actual configured RX queue
 622          *  number, which will be available after rx_queue_setup(). dev_start()
 623          *  function is good to place RSS setup.
 624          */
 625         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 626                 ret = i40e_vmdq_setup(dev);
 627                 if (ret)
 628                         goto err;
 629         }
 630         return 0;
 631 err:
 632         i40e_fdir_teardown(pf);
 633         return ret;
 634 }
 635
 636 void
 637 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 638 {
 639         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 640         uint16_t msix_vect = vsi->msix_intr;
 641         uint16_t i;
 642
 643         for (i = 0; i < vsi->nb_qps; i++) {
 644                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 645                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 646                 rte_wmb();
 647         }
 648
 649         if (vsi->type != I40E_VSI_SRIOV) {
 650                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 651                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 652                                 msix_vect - 1), 0);
 653         } else {
 654                 uint32_t reg;
 655                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 656                         vsi->user_param + (msix_vect - 1);
 657
 658                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 659         }
 660         I40E_WRITE_FLUSH(hw);
 661 }
 662
 663 static inline uint16_t
 664 i40e_calc_itr_interval(int16_t interval)
 665 {
 666         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 667                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 668
 669         /* Convert to hardware count, as writing each 1 represents 2 us */
 670         return (interval/2);
 671 }
 672
 673 void
 674 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 675 {
 676         uint32_t val;
 677         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 678         uint16_t msix_vect = vsi->msix_intr;
 679         int i;
 680
 681         for (i = 0; i < vsi->nb_qps; i++)
 682                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 683
 684         /* Bind all RX queues to allocated MSIX interrupt */
 685         for (i = 0; i < vsi->nb_qps; i++) {
 686                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 687                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 688                         ((vsi->base_queue + i + 1) <<
 689                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 690                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 691                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 692
 693                 if (i == vsi->nb_qps - 1)
 694                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 695                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 696         }
 697
 698         /* Write first RX queue to Link list register as the head element */
 699         if (vsi->type != I40E_VSI_SRIOV) {
 700                 uint16_t interval =
 701                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 702
 703                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 704                                                 (vsi->base_queue <<
 705                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 706                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 707
 708                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 709                                                 msix_vect - 1), interval);
 710
 711 #ifndef I40E_GLINT_CTL
 712 #define I40E_GLINT_CTL                     0x0003F800
 713 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 714 #endif
 715                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 716                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 717                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 718         } else {
 719                 uint32_t reg;
 720
 721                 /* num_msix_vectors_vf needs to minus irq0 */
 722                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 723                         vsi->user_param + (msix_vect - 1);
 724
 725                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 726                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 727                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 728         }
 729
 730         I40E_WRITE_FLUSH(hw);
 731 }
 732
 733 static void
 734 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 735 {
 736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 737         uint16_t interval = i40e_calc_itr_interval(\
 738                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 739
 740         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 741                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 742                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 743                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 744                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 745 }
 746
 747 static void
 748 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 749 {
 750         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 751
 752         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 753 }
 754
 755 static inline uint8_t
 756 i40e_parse_link_speed(uint16_t eth_link_speed)
 757 {
 758         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 759
 760         switch (eth_link_speed) {
 761         case ETH_LINK_SPEED_40G:
 762                 link_speed = I40E_LINK_SPEED_40GB;
 763                 break;
 764         case ETH_LINK_SPEED_20G:
 765                 link_speed = I40E_LINK_SPEED_20GB;
 766                 break;
 767         case ETH_LINK_SPEED_10G:
 768                 link_speed = I40E_LINK_SPEED_10GB;
 769                 break;
 770         case ETH_LINK_SPEED_1000:
 771                 link_speed = I40E_LINK_SPEED_1GB;
 772                 break;
 773         case ETH_LINK_SPEED_100:
 774                 link_speed = I40E_LINK_SPEED_100MB;
 775                 break;
 776         }
 777
 778         return link_speed;
 779 }
 780
 781 static int
 782 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 783 {
 784         enum i40e_status_code status;
 785         struct i40e_aq_get_phy_abilities_resp phy_ab;
 786         struct i40e_aq_set_phy_config phy_conf;
 787         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 788                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 789                         I40E_AQ_PHY_FLAG_LOW_POWER;
 790         const uint8_t advt = I40E_LINK_SPEED_40GB |
 791                         I40E_LINK_SPEED_10GB |
 792                         I40E_LINK_SPEED_1GB |
 793                         I40E_LINK_SPEED_100MB;
 794         int ret = -ENOTSUP;
 795
 796         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 797                                               NULL);
 798         if (status)
 799                 return ret;
 800
 801         memset(&phy_conf, 0, sizeof(phy_conf));
 802
 803         /* bits 0-2 use the values from get_phy_abilities_resp */
 804         abilities &= ~mask;
 805         abilities |= phy_ab.abilities & mask;
 806
 807         /* update ablities and speed */
 808         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 809                 phy_conf.link_speed = advt;
 810         else
 811                 phy_conf.link_speed = force_speed;
 812
 813         phy_conf.abilities = abilities;
 814
 815         /* use get_phy_abilities_resp value for the rest */
 816         phy_conf.phy_type = phy_ab.phy_type;
 817         phy_conf.eee_capability = phy_ab.eee_capability;
 818         phy_conf.eeer = phy_ab.eeer_val;
 819         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 820
 821         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 822                     phy_ab.abilities, phy_ab.link_speed);
 823         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 824                     phy_conf.abilities, phy_conf.link_speed);
 825
 826         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 827         if (status)
 828                 return ret;
 829
 830         return I40E_SUCCESS;
 831 }
 832
 833 static int
 834 i40e_apply_link_speed(struct rte_eth_dev *dev)
 835 {
 836         uint8_t speed;
 837         uint8_t abilities = 0;
 838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839         struct rte_eth_conf *conf = &dev->data->dev_conf;
 840
 841         speed = i40e_parse_link_speed(conf->link_speed);
 842         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 843         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 844                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 845         else
 846                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 847
 848         return i40e_phy_conf_link(hw, abilities, speed);
 849 }
 850
 851 static int
 852 i40e_dev_start(struct rte_eth_dev *dev)
 853 {
 854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 856         struct i40e_vsi *main_vsi = pf->main_vsi;
 857         int ret, i;
 858
 859         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 860                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 861                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 862                              dev->data->dev_conf.link_duplex,
 863                              dev->data->port_id);
 864                 return -EINVAL;
 865         }
 866
 867         /* Initialize VSI */
 868         ret = i40e_dev_rxtx_init(pf);
 869         if (ret != I40E_SUCCESS) {
 870                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 871                 goto err_up;
 872         }
 873
 874         /* Map queues with MSIX interrupt */
 875         i40e_vsi_queues_bind_intr(main_vsi);
 876         i40e_vsi_enable_queues_intr(main_vsi);
 877
 878         /* Map VMDQ VSI queues with MSIX interrupt */
 879         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 880                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 881                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 882         }
 883
 884         /* enable FDIR MSIX interrupt */
 885         if (pf->fdir.fdir_vsi) {
 886                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 887                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 888         }
 889
 890         /* Enable all queues which have been configured */
 891         ret = i40e_dev_switch_queues(pf, TRUE);
 892         if (ret != I40E_SUCCESS) {
 893                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 894                 goto err_up;
 895         }
 896
 897         /* Enable receiving broadcast packets */
 898         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 899         if (ret != I40E_SUCCESS)
 900                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 901
 902         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 903                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 904                                                 true, NULL);
 905                 if (ret != I40E_SUCCESS)
 906                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 907         }
 908
 909         /* Apply link configure */
 910         ret = i40e_apply_link_speed(dev);
 911         if (I40E_SUCCESS != ret) {
 912                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 913                 goto err_up;
 914         }
 915
 916         return I40E_SUCCESS;
 917
 918 err_up:
 919         i40e_dev_switch_queues(pf, FALSE);
 920         i40e_dev_clear_queues(dev);
 921
 922         return ret;
 923 }
 924
 925 static void
 926 i40e_dev_stop(struct rte_eth_dev *dev)
 927 {
 928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 929         struct i40e_vsi *main_vsi = pf->main_vsi;
 930         int i;
 931
 932         /* Disable all queues */
 933         i40e_dev_switch_queues(pf, FALSE);
 934
 935         /* un-map queues with interrupt registers */
 936         i40e_vsi_disable_queues_intr(main_vsi);
 937         i40e_vsi_queues_unbind_intr(main_vsi);
 938
 939         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 940                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 941                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 942         }
 943
 944         if (pf->fdir.fdir_vsi) {
 945                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 946                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 947         }
 948         /* Clear all queues and release memory */
 949         i40e_dev_clear_queues(dev);
 950
 951         /* Set link down */
 952         i40e_dev_set_link_down(dev);
 953
 954 }
 955
 956 static void
 957 i40e_dev_close(struct rte_eth_dev *dev)
 958 {
 959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         uint32_t reg;
 962
 963         PMD_INIT_FUNC_TRACE();
 964
 965         i40e_dev_stop(dev);
 966
 967         /* Disable interrupt */
 968         i40e_pf_disable_irq0(hw);
 969         rte_intr_disable(&(dev->pci_dev->intr_handle));
 970
 971         /* shutdown and destroy the HMC */
 972         i40e_shutdown_lan_hmc(hw);
 973
 974         /* release all the existing VSIs and VEBs */
 975         i40e_fdir_teardown(pf);
 976         i40e_vsi_release(pf->main_vsi);
 977
 978         /* shutdown the adminq */
 979         i40e_aq_queue_shutdown(hw, true);
 980         i40e_shutdown_adminq(hw);
 981
 982         i40e_res_pool_destroy(&pf->qp_pool);
 983         i40e_res_pool_destroy(&pf->msix_pool);
 984
 985         /* force a PF reset to clean anything leftover */
 986         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 987         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 988                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 989         I40E_WRITE_FLUSH(hw);
 990 }
 991
 992 static void
 993 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 994 {
 995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 996         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         struct i40e_vsi *vsi = pf->main_vsi;
 998         int status;
 999
1000         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1001                                                         true, NULL);
1002         if (status != I40E_SUCCESS)
1003                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1004
1005         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1006                                                         TRUE, NULL);
1007         if (status != I40E_SUCCESS)
1008                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1009
1010 }
1011
1012 static void
1013 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1014 {
1015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct i40e_vsi *vsi = pf->main_vsi;
1018         int status;
1019
1020         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1021                                                         false, NULL);
1022         if (status != I40E_SUCCESS)
1023                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1024
1025         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1026                                                         false, NULL);
1027         if (status != I40E_SUCCESS)
1028                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1029 }
1030
1031 static void
1032 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1033 {
1034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         struct i40e_vsi *vsi = pf->main_vsi;
1037         int ret;
1038
1039         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1040         if (ret != I40E_SUCCESS)
1041                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1042 }
1043
1044 static void
1045 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_vsi *vsi = pf->main_vsi;
1050         int ret;
1051
1052         if (dev->data->promiscuous == 1)
1053                 return; /* must remain in all_multicast mode */
1054
1055         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1056                                 vsi->seid, FALSE, NULL);
1057         if (ret != I40E_SUCCESS)
1058                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1059 }
1060
1061 /*
1062  * Set device link up.
1063  */
1064 static int
1065 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1066 {
1067         /* re-apply link speed setting */
1068         return i40e_apply_link_speed(dev);
1069 }
1070
1071 /*
1072  * Set device link down.
1073  */
1074 static int
1075 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1076 {
1077         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1078         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1080
1081         return i40e_phy_conf_link(hw, abilities, speed);
1082 }
1083
1084 int
1085 i40e_dev_link_update(struct rte_eth_dev *dev,
1086                      __rte_unused int wait_to_complete)
1087 {
1088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct i40e_link_status link_status;
1090         struct rte_eth_link link, old;
1091         int status;
1092
1093         memset(&link, 0, sizeof(link));
1094         memset(&old, 0, sizeof(old));
1095         memset(&link_status, 0, sizeof(link_status));
1096         rte_i40e_dev_atomic_read_link_status(dev, &old);
1097
1098         /* Get link status information from hardware */
1099         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1100         if (status != I40E_SUCCESS) {
1101                 link.link_speed = ETH_LINK_SPEED_100;
1102                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1103                 PMD_DRV_LOG(ERR, "Failed to get link info");
1104                 goto out;
1105         }
1106
1107         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1108
1109         if (!link.link_status)
1110                 goto out;
1111
1112         /* i40e uses full duplex only */
1113         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1114
1115         /* Parse the link status */
1116         switch (link_status.link_speed) {
1117         case I40E_LINK_SPEED_100MB:
1118                 link.link_speed = ETH_LINK_SPEED_100;
1119                 break;
1120         case I40E_LINK_SPEED_1GB:
1121                 link.link_speed = ETH_LINK_SPEED_1000;
1122                 break;
1123         case I40E_LINK_SPEED_10GB:
1124                 link.link_speed = ETH_LINK_SPEED_10G;
1125                 break;
1126         case I40E_LINK_SPEED_20GB:
1127                 link.link_speed = ETH_LINK_SPEED_20G;
1128                 break;
1129         case I40E_LINK_SPEED_40GB:
1130                 link.link_speed = ETH_LINK_SPEED_40G;
1131                 break;
1132         default:
1133                 link.link_speed = ETH_LINK_SPEED_100;
1134                 break;
1135         }
1136
1137 out:
1138         rte_i40e_dev_atomic_write_link_status(dev, &link);
1139         if (link.link_status == old.link_status)
1140                 return -1;
1141
1142         return 0;
1143 }
1144
1145 /* Get all the statistics of a VSI */
1146 void
1147 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1148 {
1149         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1150         struct i40e_eth_stats *nes = &vsi->eth_stats;
1151         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1152         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1153
1154         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1155                             vsi->offset_loaded, &oes->rx_bytes,
1156                             &nes->rx_bytes);
1157         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1158                             vsi->offset_loaded, &oes->rx_unicast,
1159                             &nes->rx_unicast);
1160         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1161                             vsi->offset_loaded, &oes->rx_multicast,
1162                             &nes->rx_multicast);
1163         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1164                             vsi->offset_loaded, &oes->rx_broadcast,
1165                             &nes->rx_broadcast);
1166         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1167                             &oes->rx_discards, &nes->rx_discards);
1168         /* GLV_REPC not supported */
1169         /* GLV_RMPC not supported */
1170         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1171                             &oes->rx_unknown_protocol,
1172                             &nes->rx_unknown_protocol);
1173         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1174                             vsi->offset_loaded, &oes->tx_bytes,
1175                             &nes->tx_bytes);
1176         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1177                             vsi->offset_loaded, &oes->tx_unicast,
1178                             &nes->tx_unicast);
1179         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1180                             vsi->offset_loaded, &oes->tx_multicast,
1181                             &nes->tx_multicast);
1182         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1183                             vsi->offset_loaded,  &oes->tx_broadcast,
1184                             &nes->tx_broadcast);
1185         /* GLV_TDPC not supported */
1186         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1187                             &oes->tx_errors, &nes->tx_errors);
1188         vsi->offset_loaded = true;
1189
1190         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1191                     vsi->vsi_id);
1192         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1193         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1194         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1195         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1196         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1197         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1198                     nes->rx_unknown_protocol);
1199         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1200         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1201         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1202         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1203         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1204         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1205         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1206                     vsi->vsi_id);
1207 }
1208
1209 /* Get all statistics of a port */
1210 static void
1211 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1212 {
1213         uint32_t i;
1214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1216         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1217         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1218
1219         /* Get statistics of struct i40e_eth_stats */
1220         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1221                             I40E_GLPRT_GORCL(hw->port),
1222                             pf->offset_loaded, &os->eth.rx_bytes,
1223                             &ns->eth.rx_bytes);
1224         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1225                             I40E_GLPRT_UPRCL(hw->port),
1226                             pf->offset_loaded, &os->eth.rx_unicast,
1227                             &ns->eth.rx_unicast);
1228         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1229                             I40E_GLPRT_MPRCL(hw->port),
1230                             pf->offset_loaded, &os->eth.rx_multicast,
1231                             &ns->eth.rx_multicast);
1232         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1233                             I40E_GLPRT_BPRCL(hw->port),
1234                             pf->offset_loaded, &os->eth.rx_broadcast,
1235                             &ns->eth.rx_broadcast);
1236         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1237                             pf->offset_loaded, &os->eth.rx_discards,
1238                             &ns->eth.rx_discards);
1239         /* GLPRT_REPC not supported */
1240         /* GLPRT_RMPC not supported */
1241         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1242                             pf->offset_loaded,
1243                             &os->eth.rx_unknown_protocol,
1244                             &ns->eth.rx_unknown_protocol);
1245         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1246                             I40E_GLPRT_GOTCL(hw->port),
1247                             pf->offset_loaded, &os->eth.tx_bytes,
1248                             &ns->eth.tx_bytes);
1249         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1250                             I40E_GLPRT_UPTCL(hw->port),
1251                             pf->offset_loaded, &os->eth.tx_unicast,
1252                             &ns->eth.tx_unicast);
1253         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1254                             I40E_GLPRT_MPTCL(hw->port),
1255                             pf->offset_loaded, &os->eth.tx_multicast,
1256                             &ns->eth.tx_multicast);
1257         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1258                             I40E_GLPRT_BPTCL(hw->port),
1259                             pf->offset_loaded, &os->eth.tx_broadcast,
1260                             &ns->eth.tx_broadcast);
1261         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1262                             pf->offset_loaded, &os->eth.tx_discards,
1263                             &ns->eth.tx_discards);
1264         /* GLPRT_TEPC not supported */
1265
1266         /* additional port specific stats */
1267         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1268                             pf->offset_loaded, &os->tx_dropped_link_down,
1269                             &ns->tx_dropped_link_down);
1270         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1271                             pf->offset_loaded, &os->crc_errors,
1272                             &ns->crc_errors);
1273         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1274                             pf->offset_loaded, &os->illegal_bytes,
1275                             &ns->illegal_bytes);
1276         /* GLPRT_ERRBC not supported */
1277         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1278                             pf->offset_loaded, &os->mac_local_faults,
1279                             &ns->mac_local_faults);
1280         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1281                             pf->offset_loaded, &os->mac_remote_faults,
1282                             &ns->mac_remote_faults);
1283         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1284                             pf->offset_loaded, &os->rx_length_errors,
1285                             &ns->rx_length_errors);
1286         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1287                             pf->offset_loaded, &os->link_xon_rx,
1288                             &ns->link_xon_rx);
1289         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1290                             pf->offset_loaded, &os->link_xoff_rx,
1291                             &ns->link_xoff_rx);
1292         for (i = 0; i < 8; i++) {
1293                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1294                                     pf->offset_loaded,
1295                                     &os->priority_xon_rx[i],
1296                                     &ns->priority_xon_rx[i]);
1297                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1298                                     pf->offset_loaded,
1299                                     &os->priority_xoff_rx[i],
1300                                     &ns->priority_xoff_rx[i]);
1301         }
1302         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1303                             pf->offset_loaded, &os->link_xon_tx,
1304                             &ns->link_xon_tx);
1305         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1306                             pf->offset_loaded, &os->link_xoff_tx,
1307                             &ns->link_xoff_tx);
1308         for (i = 0; i < 8; i++) {
1309                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1310                                     pf->offset_loaded,
1311                                     &os->priority_xon_tx[i],
1312                                     &ns->priority_xon_tx[i]);
1313                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1314                                     pf->offset_loaded,
1315                                     &os->priority_xoff_tx[i],
1316                                     &ns->priority_xoff_tx[i]);
1317                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1318                                     pf->offset_loaded,
1319                                     &os->priority_xon_2_xoff[i],
1320                                     &ns->priority_xon_2_xoff[i]);
1321         }
1322         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1323                             I40E_GLPRT_PRC64L(hw->port),
1324                             pf->offset_loaded, &os->rx_size_64,
1325                             &ns->rx_size_64);
1326         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1327                             I40E_GLPRT_PRC127L(hw->port),
1328                             pf->offset_loaded, &os->rx_size_127,
1329                             &ns->rx_size_127);
1330         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1331                             I40E_GLPRT_PRC255L(hw->port),
1332                             pf->offset_loaded, &os->rx_size_255,
1333                             &ns->rx_size_255);
1334         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1335                             I40E_GLPRT_PRC511L(hw->port),
1336                             pf->offset_loaded, &os->rx_size_511,
1337                             &ns->rx_size_511);
1338         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1339                             I40E_GLPRT_PRC1023L(hw->port),
1340                             pf->offset_loaded, &os->rx_size_1023,
1341                             &ns->rx_size_1023);
1342         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1343                             I40E_GLPRT_PRC1522L(hw->port),
1344                             pf->offset_loaded, &os->rx_size_1522,
1345                             &ns->rx_size_1522);
1346         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1347                             I40E_GLPRT_PRC9522L(hw->port),
1348                             pf->offset_loaded, &os->rx_size_big,
1349                             &ns->rx_size_big);
1350         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1351                             pf->offset_loaded, &os->rx_undersize,
1352                             &ns->rx_undersize);
1353         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1354                             pf->offset_loaded, &os->rx_fragments,
1355                             &ns->rx_fragments);
1356         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1357                             pf->offset_loaded, &os->rx_oversize,
1358                             &ns->rx_oversize);
1359         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1360                             pf->offset_loaded, &os->rx_jabber,
1361                             &ns->rx_jabber);
1362         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1363                             I40E_GLPRT_PTC64L(hw->port),
1364                             pf->offset_loaded, &os->tx_size_64,
1365                             &ns->tx_size_64);
1366         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1367                             I40E_GLPRT_PTC127L(hw->port),
1368                             pf->offset_loaded, &os->tx_size_127,
1369                             &ns->tx_size_127);
1370         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1371                             I40E_GLPRT_PTC255L(hw->port),
1372                             pf->offset_loaded, &os->tx_size_255,
1373                             &ns->tx_size_255);
1374         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1375                             I40E_GLPRT_PTC511L(hw->port),
1376                             pf->offset_loaded, &os->tx_size_511,
1377                             &ns->tx_size_511);
1378         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1379                             I40E_GLPRT_PTC1023L(hw->port),
1380                             pf->offset_loaded, &os->tx_size_1023,
1381                             &ns->tx_size_1023);
1382         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1383                             I40E_GLPRT_PTC1522L(hw->port),
1384                             pf->offset_loaded, &os->tx_size_1522,
1385                             &ns->tx_size_1522);
1386         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1387                             I40E_GLPRT_PTC9522L(hw->port),
1388                             pf->offset_loaded, &os->tx_size_big,
1389                             &ns->tx_size_big);
1390         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1391                            pf->offset_loaded,
1392                            &os->fd_sb_match, &ns->fd_sb_match);
1393         /* GLPRT_MSPDC not supported */
1394         /* GLPRT_XEC not supported */
1395
1396         pf->offset_loaded = true;
1397
1398         if (pf->main_vsi)
1399                 i40e_update_vsi_stats(pf->main_vsi);
1400
1401         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1402                                                 ns->eth.rx_broadcast;
1403         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1404                                                 ns->eth.tx_broadcast;
1405         stats->ibytes   = ns->eth.rx_bytes;
1406         stats->obytes   = ns->eth.tx_bytes;
1407         stats->oerrors  = ns->eth.tx_errors;
1408         stats->imcasts  = ns->eth.rx_multicast;
1409         stats->fdirmatch = ns->fd_sb_match;
1410
1411         /* Rx Errors */
1412         stats->ibadcrc  = ns->crc_errors;
1413         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1414                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1415         stats->imissed  = ns->eth.rx_discards;
1416         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1417
1418         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1419         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1420         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1421         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1422         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1423         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1424         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1425                     ns->eth.rx_unknown_protocol);
1426         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1427         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1428         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1429         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1430         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1431         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1432
1433         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1434                     ns->tx_dropped_link_down);
1435         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1436         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1437                     ns->illegal_bytes);
1438         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1439         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1440                     ns->mac_local_faults);
1441         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1442                     ns->mac_remote_faults);
1443         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1444                     ns->rx_length_errors);
1445         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1446         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1447         for (i = 0; i < 8; i++) {
1448                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1449                                 i, ns->priority_xon_rx[i]);
1450                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1451                                 i, ns->priority_xoff_rx[i]);
1452         }
1453         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1454         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1455         for (i = 0; i < 8; i++) {
1456                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1457                                 i, ns->priority_xon_tx[i]);
1458                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1459                                 i, ns->priority_xoff_tx[i]);
1460                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1461                                 i, ns->priority_xon_2_xoff[i]);
1462         }
1463         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1464         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1465         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1466         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1467         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1468         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1469         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1470         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1471         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1472         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1473         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1474         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1475         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1476         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1477         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1478         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1479         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1480         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1481         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1482                         ns->mac_short_packet_dropped);
1483         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1484                     ns->checksum_error);
1485         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1486         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1487 }
1488
1489 /* Reset the statistics */
1490 static void
1491 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1492 {
1493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1494
1495         /* It results in reloading the start point of each counter */
1496         pf->offset_loaded = false;
1497 }
1498
1499 static int
1500 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1501                                  __rte_unused uint16_t queue_id,
1502                                  __rte_unused uint8_t stat_idx,
1503                                  __rte_unused uint8_t is_rx)
1504 {
1505         PMD_INIT_FUNC_TRACE();
1506
1507         return -ENOSYS;
1508 }
1509
1510 static void
1511 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1512 {
1513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1514         struct i40e_vsi *vsi = pf->main_vsi;
1515
1516         dev_info->max_rx_queues = vsi->nb_qps;
1517         dev_info->max_tx_queues = vsi->nb_qps;
1518         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1519         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1520         dev_info->max_mac_addrs = vsi->max_macaddrs;
1521         dev_info->max_vfs = dev->pci_dev->max_vfs;
1522         dev_info->rx_offload_capa =
1523                 DEV_RX_OFFLOAD_VLAN_STRIP |
1524                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1525                 DEV_RX_OFFLOAD_UDP_CKSUM |
1526                 DEV_RX_OFFLOAD_TCP_CKSUM;
1527         dev_info->tx_offload_capa =
1528                 DEV_TX_OFFLOAD_VLAN_INSERT |
1529                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1530                 DEV_TX_OFFLOAD_UDP_CKSUM |
1531                 DEV_TX_OFFLOAD_TCP_CKSUM |
1532                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1533                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1534         dev_info->reta_size = pf->hash_lut_size;
1535
1536         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1537                 .rx_thresh = {
1538                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1539                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1540                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1541                 },
1542                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1543                 .rx_drop_en = 0,
1544         };
1545
1546         dev_info->default_txconf = (struct rte_eth_txconf) {
1547                 .tx_thresh = {
1548                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1549                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1550                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1551                 },
1552                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1553                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1554                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1555                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1556         };
1557
1558         if (pf->flags | I40E_FLAG_VMDQ) {
1559                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1560                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1561                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1562                                                 pf->max_nb_vmdq_vsi;
1563                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1564                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1565                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1566         }
1567 }
1568
1569 static int
1570 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1571 {
1572         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1573         struct i40e_vsi *vsi = pf->main_vsi;
1574         PMD_INIT_FUNC_TRACE();
1575
1576         if (on)
1577                 return i40e_vsi_add_vlan(vsi, vlan_id);
1578         else
1579                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1580 }
1581
1582 static void
1583 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1584                    __rte_unused uint16_t tpid)
1585 {
1586         PMD_INIT_FUNC_TRACE();
1587 }
1588
1589 static void
1590 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1591 {
1592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1593         struct i40e_vsi *vsi = pf->main_vsi;
1594
1595         if (mask & ETH_VLAN_STRIP_MASK) {
1596                 /* Enable or disable VLAN stripping */
1597                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1598                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1599                 else
1600                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1601         }
1602
1603         if (mask & ETH_VLAN_EXTEND_MASK) {
1604                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1605                         i40e_vsi_config_double_vlan(vsi, TRUE);
1606                 else
1607                         i40e_vsi_config_double_vlan(vsi, FALSE);
1608         }
1609 }
1610
1611 static void
1612 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1613                           __rte_unused uint16_t queue,
1614                           __rte_unused int on)
1615 {
1616         PMD_INIT_FUNC_TRACE();
1617 }
1618
1619 static int
1620 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1621 {
1622         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1623         struct i40e_vsi *vsi = pf->main_vsi;
1624         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1625         struct i40e_vsi_vlan_pvid_info info;
1626
1627         memset(&info, 0, sizeof(info));
1628         info.on = on;
1629         if (info.on)
1630                 info.config.pvid = pvid;
1631         else {
1632                 info.config.reject.tagged =
1633                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1634                 info.config.reject.untagged =
1635                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1636         }
1637
1638         return i40e_vsi_vlan_pvid_set(vsi, &info);
1639 }
1640
1641 static int
1642 i40e_dev_led_on(struct rte_eth_dev *dev)
1643 {
1644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         uint32_t mode = i40e_led_get(hw);
1646
1647         if (mode == 0)
1648                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1649
1650         return 0;
1651 }
1652
1653 static int
1654 i40e_dev_led_off(struct rte_eth_dev *dev)
1655 {
1656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         uint32_t mode = i40e_led_get(hw);
1658
1659         if (mode != 0)
1660                 i40e_led_set(hw, 0, false);
1661
1662         return 0;
1663 }
1664
1665 static int
1666 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1667                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1668 {
1669         PMD_INIT_FUNC_TRACE();
1670
1671         return -ENOSYS;
1672 }
1673
1674 static int
1675 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1676                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1677 {
1678         PMD_INIT_FUNC_TRACE();
1679
1680         return -ENOSYS;
1681 }
1682
1683 /* Add a MAC address, and update filters */
1684 static void
1685 i40e_macaddr_add(struct rte_eth_dev *dev,
1686                  struct ether_addr *mac_addr,
1687                  __rte_unused uint32_t index,
1688                  uint32_t pool)
1689 {
1690         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1691         struct i40e_mac_filter_info mac_filter;
1692         struct i40e_vsi *vsi;
1693         int ret;
1694
1695         /* If VMDQ not enabled or configured, return */
1696         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1697                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1698                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1699                         pool);
1700                 return;
1701         }
1702
1703         if (pool > pf->nb_cfg_vmdq_vsi) {
1704                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1705                                 pool, pf->nb_cfg_vmdq_vsi);
1706                 return;
1707         }
1708
1709         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1710         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1711
1712         if (pool == 0)
1713                 vsi = pf->main_vsi;
1714         else
1715                 vsi = pf->vmdq[pool - 1].vsi;
1716
1717         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1718         if (ret != I40E_SUCCESS) {
1719                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1720                 return;
1721         }
1722 }
1723
1724 /* Remove a MAC address, and update filters */
1725 static void
1726 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1727 {
1728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1729         struct i40e_vsi *vsi;
1730         struct rte_eth_dev_data *data = dev->data;
1731         struct ether_addr *macaddr;
1732         int ret;
1733         uint32_t i;
1734         uint64_t pool_sel;
1735
1736         macaddr = &(data->mac_addrs[index]);
1737
1738         pool_sel = dev->data->mac_pool_sel[index];
1739
1740         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1741                 if (pool_sel & (1ULL << i)) {
1742                         if (i == 0)
1743                                 vsi = pf->main_vsi;
1744                         else {
1745                                 /* No VMDQ pool enabled or configured */
1746                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1747                                         (i > pf->nb_cfg_vmdq_vsi)) {
1748                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1749                                                         "/configured");
1750                                         return;
1751                                 }
1752                                 vsi = pf->vmdq[i - 1].vsi;
1753                         }
1754                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1755
1756                         if (ret) {
1757                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1758                                 return;
1759                         }
1760                 }
1761         }
1762 }
1763
1764 /* Set perfect match or hash match of MAC and VLAN for a VF */
1765 static int
1766 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1767                  struct rte_eth_mac_filter *filter,
1768                  bool add)
1769 {
1770         struct i40e_hw *hw;
1771         struct i40e_mac_filter_info mac_filter;
1772         struct ether_addr old_mac;
1773         struct ether_addr *new_mac;
1774         struct i40e_pf_vf *vf = NULL;
1775         uint16_t vf_id;
1776         int ret;
1777
1778         if (pf == NULL) {
1779                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1780                 return -EINVAL;
1781         }
1782         hw = I40E_PF_TO_HW(pf);
1783
1784         if (filter == NULL) {
1785                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1786                 return -EINVAL;
1787         }
1788
1789         new_mac = &filter->mac_addr;
1790
1791         if (is_zero_ether_addr(new_mac)) {
1792                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1793                 return -EINVAL;
1794         }
1795
1796         vf_id = filter->dst_id;
1797
1798         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1799                 PMD_DRV_LOG(ERR, "Invalid argument.");
1800                 return -EINVAL;
1801         }
1802         vf = &pf->vfs[vf_id];
1803
1804         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1805                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1806                 return -EINVAL;
1807         }
1808
1809         if (add) {
1810                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1811                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1812                                 ETHER_ADDR_LEN);
1813                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1814                                  ETHER_ADDR_LEN);
1815
1816                 mac_filter.filter_type = filter->filter_type;
1817                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1818                 if (ret != I40E_SUCCESS) {
1819                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1820                         return -1;
1821                 }
1822                 ether_addr_copy(new_mac, &pf->dev_addr);
1823         } else {
1824                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1825                                 ETHER_ADDR_LEN);
1826                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1827                 if (ret != I40E_SUCCESS) {
1828                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1829                         return -1;
1830                 }
1831
1832                 /* Clear device address as it has been removed */
1833                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1834                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1835         }
1836
1837         return 0;
1838 }
1839
1840 /* MAC filter handle */
1841 static int
1842 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1843                 void *arg)
1844 {
1845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1846         struct rte_eth_mac_filter *filter;
1847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1848         int ret = I40E_NOT_SUPPORTED;
1849
1850         filter = (struct rte_eth_mac_filter *)(arg);
1851
1852         switch (filter_op) {
1853         case RTE_ETH_FILTER_NOP:
1854                 ret = I40E_SUCCESS;
1855                 break;
1856         case RTE_ETH_FILTER_ADD:
1857                 i40e_pf_disable_irq0(hw);
1858                 if (filter->is_vf)
1859                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1860                 i40e_pf_enable_irq0(hw);
1861                 break;
1862         case RTE_ETH_FILTER_DELETE:
1863                 i40e_pf_disable_irq0(hw);
1864                 if (filter->is_vf)
1865                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1866                 i40e_pf_enable_irq0(hw);
1867                 break;
1868         default:
1869                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1870                 ret = I40E_ERR_PARAM;
1871                 break;
1872         }
1873
1874         return ret;
1875 }
1876
1877 static int
1878 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1879                          struct rte_eth_rss_reta_entry64 *reta_conf,
1880                          uint16_t reta_size)
1881 {
1882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884         uint32_t lut, l;
1885         uint16_t i, j, lut_size = pf->hash_lut_size;
1886         uint16_t idx, shift;
1887         uint8_t mask;
1888
1889         if (reta_size != lut_size ||
1890                 reta_size > ETH_RSS_RETA_SIZE_512) {
1891                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1892                         "(%d) doesn't match the number hardware can supported "
1893                                         "(%d)\n", reta_size, lut_size);
1894                 return -EINVAL;
1895         }
1896
1897         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1898                 idx = i / RTE_RETA_GROUP_SIZE;
1899                 shift = i % RTE_RETA_GROUP_SIZE;
1900                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1901                                                 I40E_4_BIT_MASK);
1902                 if (!mask)
1903                         continue;
1904                 if (mask == I40E_4_BIT_MASK)
1905                         l = 0;
1906                 else
1907                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1908                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1909                         if (mask & (0x1 << j))
1910                                 lut |= reta_conf[idx].reta[shift + j] <<
1911                                                         (CHAR_BIT * j);
1912                         else
1913                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1914                 }
1915                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int
1922 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1923                         struct rte_eth_rss_reta_entry64 *reta_conf,
1924                         uint16_t reta_size)
1925 {
1926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         uint32_t lut;
1929         uint16_t i, j, lut_size = pf->hash_lut_size;
1930         uint16_t idx, shift;
1931         uint8_t mask;
1932
1933         if (reta_size != lut_size ||
1934                 reta_size > ETH_RSS_RETA_SIZE_512) {
1935                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1936                         "(%d) doesn't match the number hardware can supported "
1937                                         "(%d)\n", reta_size, lut_size);
1938                 return -EINVAL;
1939         }
1940
1941         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1942                 idx = i / RTE_RETA_GROUP_SIZE;
1943                 shift = i % RTE_RETA_GROUP_SIZE;
1944                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1945                                                 I40E_4_BIT_MASK);
1946                 if (!mask)
1947                         continue;
1948
1949                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1950                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1951                         if (mask & (0x1 << j))
1952                                 reta_conf[idx].reta[shift + j] = ((lut >>
1953                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1954                 }
1955         }
1956
1957         return 0;
1958 }
1959
1960 /**
1961  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1962  * @hw:   pointer to the HW structure
1963  * @mem:  pointer to mem struct to fill out
1964  * @size: size of memory requested
1965  * @alignment: what to align the allocation to
1966  **/
1967 enum i40e_status_code
1968 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1969                         struct i40e_dma_mem *mem,
1970                         u64 size,
1971                         u32 alignment)
1972 {
1973         static uint64_t id = 0;
1974         const struct rte_memzone *mz = NULL;
1975         char z_name[RTE_MEMZONE_NAMESIZE];
1976
1977         if (!mem)
1978                 return I40E_ERR_PARAM;
1979
1980         id++;
1981         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1982 #ifdef RTE_LIBRTE_XEN_DOM0
1983         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1984                                                         RTE_PGSIZE_2M);
1985 #else
1986         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1987 #endif
1988         if (!mz)
1989                 return I40E_ERR_NO_MEMORY;
1990
1991         mem->id = id;
1992         mem->size = size;
1993         mem->va = mz->addr;
1994 #ifdef RTE_LIBRTE_XEN_DOM0
1995         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1996 #else
1997         mem->pa = mz->phys_addr;
1998 #endif
1999
2000         return I40E_SUCCESS;
2001 }
2002
2003 /**
2004  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2005  * @hw:   pointer to the HW structure
2006  * @mem:  ptr to mem struct to free
2007  **/
2008 enum i40e_status_code
2009 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2010                     struct i40e_dma_mem *mem)
2011 {
2012         if (!mem || !mem->va)
2013                 return I40E_ERR_PARAM;
2014
2015         mem->va = NULL;
2016         mem->pa = (u64)0;
2017
2018         return I40E_SUCCESS;
2019 }
2020
2021 /**
2022  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2023  * @hw:   pointer to the HW structure
2024  * @mem:  pointer to mem struct to fill out
2025  * @size: size of memory requested
2026  **/
2027 enum i40e_status_code
2028 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2029                          struct i40e_virt_mem *mem,
2030                          u32 size)
2031 {
2032         if (!mem)
2033                 return I40E_ERR_PARAM;
2034
2035         mem->size = size;
2036         mem->va = rte_zmalloc("i40e", size, 0);
2037
2038         if (mem->va)
2039                 return I40E_SUCCESS;
2040         else
2041                 return I40E_ERR_NO_MEMORY;
2042 }
2043
2044 /**
2045  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2046  * @hw:   pointer to the HW structure
2047  * @mem:  pointer to mem struct to free
2048  **/
2049 enum i40e_status_code
2050 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2051                      struct i40e_virt_mem *mem)
2052 {
2053         if (!mem)
2054                 return I40E_ERR_PARAM;
2055
2056         rte_free(mem->va);
2057         mem->va = NULL;
2058
2059         return I40E_SUCCESS;
2060 }
2061
2062 void
2063 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2064 {
2065         rte_spinlock_init(&sp->spinlock);
2066 }
2067
2068 void
2069 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2070 {
2071         rte_spinlock_lock(&sp->spinlock);
2072 }
2073
2074 void
2075 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2076 {
2077         rte_spinlock_unlock(&sp->spinlock);
2078 }
2079
2080 void
2081 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2082 {
2083         return;
2084 }
2085
2086 /**
2087  * Get the hardware capabilities, which will be parsed
2088  * and saved into struct i40e_hw.
2089  */
2090 static int
2091 i40e_get_cap(struct i40e_hw *hw)
2092 {
2093         struct i40e_aqc_list_capabilities_element_resp *buf;
2094         uint16_t len, size = 0;
2095         int ret;
2096
2097         /* Calculate a huge enough buff for saving response data temporarily */
2098         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2099                                                 I40E_MAX_CAP_ELE_NUM;
2100         buf = rte_zmalloc("i40e", len, 0);
2101         if (!buf) {
2102                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2103                 return I40E_ERR_NO_MEMORY;
2104         }
2105
2106         /* Get, parse the capabilities and save it to hw */
2107         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2108                         i40e_aqc_opc_list_func_capabilities, NULL);
2109         if (ret != I40E_SUCCESS)
2110                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2111
2112         /* Free the temporary buffer after being used */
2113         rte_free(buf);
2114
2115         return ret;
2116 }
2117
2118 static int
2119 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2120 {
2121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2122         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2123         uint16_t sum_queues = 0, sum_vsis, left_queues;
2124
2125         /* First check if FW support SRIOV */
2126         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2127                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2128                 return -EINVAL;
2129         }
2130
2131         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2132         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2133         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2134         /* Allocate queues for pf */
2135         if (hw->func_caps.rss) {
2136                 pf->flags |= I40E_FLAG_RSS;
2137                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2138                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2139                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2140         } else
2141                 pf->lan_nb_qps = 1;
2142         sum_queues = pf->lan_nb_qps;
2143         /* Default VSI is not counted in */
2144         sum_vsis = 0;
2145         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2146
2147         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2148                 pf->flags |= I40E_FLAG_SRIOV;
2149                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2150                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2151                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2152                                      "max supported %u.",
2153                                      dev->pci_dev->max_vfs,
2154                                      hw->func_caps.num_vfs);
2155                         return -EINVAL;
2156                 }
2157                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2158                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2159                                      "max support %u queues.",
2160                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2161                         return -EINVAL;
2162                 }
2163                 pf->vf_num = dev->pci_dev->max_vfs;
2164                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2165                 sum_vsis   += pf->vf_num;
2166                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2167                              pf->vf_num, pf->vf_nb_qps);
2168         } else
2169                 pf->vf_num = 0;
2170
2171         if (hw->func_caps.vmdq) {
2172                 pf->flags |= I40E_FLAG_VMDQ;
2173                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2174                 pf->max_nb_vmdq_vsi = 1;
2175                 /*
2176                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2177                  * later.
2178                  */
2179                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2180                 sum_vsis += pf->max_nb_vmdq_vsi;
2181         } else {
2182                 pf->vmdq_nb_qps = 0;
2183                 pf->max_nb_vmdq_vsi = 0;
2184         }
2185         pf->nb_cfg_vmdq_vsi = 0;
2186
2187         if (hw->func_caps.fd) {
2188                 pf->flags |= I40E_FLAG_FDIR;
2189                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2190                 /**
2191                  * Each flow director consumes one VSI and one queue,
2192                  * but can't calculate out predictably here.
2193                  */
2194         }
2195
2196         if (sum_vsis > pf->max_num_vsi ||
2197                 sum_queues > hw->func_caps.num_rx_qp) {
2198                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2199                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2200                              pf->max_num_vsi, sum_vsis);
2201                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2202                              hw->func_caps.num_rx_qp, sum_queues);
2203                 return -EINVAL;
2204         }
2205
2206         /* Adjust VMDQ setting to support as many VMs as possible */
2207         if (pf->flags & I40E_FLAG_VMDQ) {
2208                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2209
2210                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2211                                         pf->max_num_vsi - sum_vsis);
2212
2213                 /* Limit the max VMDQ number that rte_ether that can support  */
2214                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2215                                         ETH_64_POOLS - 1);
2216
2217                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2218                                 pf->max_nb_vmdq_vsi);
2219                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2220         }
2221
2222         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2223          * cause */
2224         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2225                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2226                              sum_vsis, hw->func_caps.num_msix_vectors);
2227                 return -EINVAL;
2228         }
2229         return I40E_SUCCESS;
2230 }
2231
2232 static int
2233 i40e_pf_get_switch_config(struct i40e_pf *pf)
2234 {
2235         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2236         struct i40e_aqc_get_switch_config_resp *switch_config;
2237         struct i40e_aqc_switch_config_element_resp *element;
2238         uint16_t start_seid = 0, num_reported;
2239         int ret;
2240
2241         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2242                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2243         if (!switch_config) {
2244                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2245                 return -ENOMEM;
2246         }
2247
2248         /* Get the switch configurations */
2249         ret = i40e_aq_get_switch_config(hw, switch_config,
2250                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2251         if (ret != I40E_SUCCESS) {
2252                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2253                 goto fail;
2254         }
2255         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2256         if (num_reported != 1) { /* The number should be 1 */
2257                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2258                 goto fail;
2259         }
2260
2261         /* Parse the switch configuration elements */
2262         element = &(switch_config->element[0]);
2263         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2264                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2265                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2266         } else
2267                 PMD_DRV_LOG(INFO, "Unknown element type");
2268
2269 fail:
2270         rte_free(switch_config);
2271
2272         return ret;
2273 }
2274
2275 static int
2276 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2277                         uint32_t num)
2278 {
2279         struct pool_entry *entry;
2280
2281         if (pool == NULL || num == 0)
2282                 return -EINVAL;
2283
2284         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2285         if (entry == NULL) {
2286                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2287                 return -ENOMEM;
2288         }
2289
2290         /* queue heap initialize */
2291         pool->num_free = num;
2292         pool->num_alloc = 0;
2293         pool->base = base;
2294         LIST_INIT(&pool->alloc_list);
2295         LIST_INIT(&pool->free_list);
2296
2297         /* Initialize element  */
2298         entry->base = 0;
2299         entry->len = num;
2300
2301         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2302         return 0;
2303 }
2304
2305 static void
2306 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2307 {
2308         struct pool_entry *entry;
2309
2310         if (pool == NULL)
2311                 return;
2312
2313         LIST_FOREACH(entry, &pool->alloc_list, next) {
2314                 LIST_REMOVE(entry, next);
2315                 rte_free(entry);
2316         }
2317
2318         LIST_FOREACH(entry, &pool->free_list, next) {
2319                 LIST_REMOVE(entry, next);
2320                 rte_free(entry);
2321         }
2322
2323         pool->num_free = 0;
2324         pool->num_alloc = 0;
2325         pool->base = 0;
2326         LIST_INIT(&pool->alloc_list);
2327         LIST_INIT(&pool->free_list);
2328 }
2329
2330 static int
2331 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2332                        uint32_t base)
2333 {
2334         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2335         uint32_t pool_offset;
2336         int insert;
2337
2338         if (pool == NULL) {
2339                 PMD_DRV_LOG(ERR, "Invalid parameter");
2340                 return -EINVAL;
2341         }
2342
2343         pool_offset = base - pool->base;
2344         /* Lookup in alloc list */
2345         LIST_FOREACH(entry, &pool->alloc_list, next) {
2346                 if (entry->base == pool_offset) {
2347                         valid_entry = entry;
2348                         LIST_REMOVE(entry, next);
2349                         break;
2350                 }
2351         }
2352
2353         /* Not find, return */
2354         if (valid_entry == NULL) {
2355                 PMD_DRV_LOG(ERR, "Failed to find entry");
2356                 return -EINVAL;
2357         }
2358
2359         /**
2360          * Found it, move it to free list  and try to merge.
2361          * In order to make merge easier, always sort it by qbase.
2362          * Find adjacent prev and last entries.
2363          */
2364         prev = next = NULL;
2365         LIST_FOREACH(entry, &pool->free_list, next) {
2366                 if (entry->base > valid_entry->base) {
2367                         next = entry;
2368                         break;
2369                 }
2370                 prev = entry;
2371         }
2372
2373         insert = 0;
2374         /* Try to merge with next one*/
2375         if (next != NULL) {
2376                 /* Merge with next one */
2377                 if (valid_entry->base + valid_entry->len == next->base) {
2378                         next->base = valid_entry->base;
2379                         next->len += valid_entry->len;
2380                         rte_free(valid_entry);
2381                         valid_entry = next;
2382                         insert = 1;
2383                 }
2384         }
2385
2386         if (prev != NULL) {
2387                 /* Merge with previous one */
2388                 if (prev->base + prev->len == valid_entry->base) {
2389                         prev->len += valid_entry->len;
2390                         /* If it merge with next one, remove next node */
2391                         if (insert == 1) {
2392                                 LIST_REMOVE(valid_entry, next);
2393                                 rte_free(valid_entry);
2394                         } else {
2395                                 rte_free(valid_entry);
2396                                 insert = 1;
2397                         }
2398                 }
2399         }
2400
2401         /* Not find any entry to merge, insert */
2402         if (insert == 0) {
2403                 if (prev != NULL)
2404                         LIST_INSERT_AFTER(prev, valid_entry, next);
2405                 else if (next != NULL)
2406                         LIST_INSERT_BEFORE(next, valid_entry, next);
2407                 else /* It's empty list, insert to head */
2408                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2409         }
2410
2411         pool->num_free += valid_entry->len;
2412         pool->num_alloc -= valid_entry->len;
2413
2414         return 0;
2415 }
2416
2417 static int
2418 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2419                        uint16_t num)
2420 {
2421         struct pool_entry *entry, *valid_entry;
2422
2423         if (pool == NULL || num == 0) {
2424                 PMD_DRV_LOG(ERR, "Invalid parameter");
2425                 return -EINVAL;
2426         }
2427
2428         if (pool->num_free < num) {
2429                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2430                             num, pool->num_free);
2431                 return -ENOMEM;
2432         }
2433
2434         valid_entry = NULL;
2435         /* Lookup  in free list and find most fit one */
2436         LIST_FOREACH(entry, &pool->free_list, next) {
2437                 if (entry->len >= num) {
2438                         /* Find best one */
2439                         if (entry->len == num) {
2440                                 valid_entry = entry;
2441                                 break;
2442                         }
2443                         if (valid_entry == NULL || valid_entry->len > entry->len)
2444                                 valid_entry = entry;
2445                 }
2446         }
2447
2448         /* Not find one to satisfy the request, return */
2449         if (valid_entry == NULL) {
2450                 PMD_DRV_LOG(ERR, "No valid entry found");
2451                 return -ENOMEM;
2452         }
2453         /**
2454          * The entry have equal queue number as requested,
2455          * remove it from alloc_list.
2456          */
2457         if (valid_entry->len == num) {
2458                 LIST_REMOVE(valid_entry, next);
2459         } else {
2460                 /**
2461                  * The entry have more numbers than requested,
2462                  * create a new entry for alloc_list and minus its
2463                  * queue base and number in free_list.
2464                  */
2465                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2466                 if (entry == NULL) {
2467                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2468                                     "resource pool");
2469                         return -ENOMEM;
2470                 }
2471                 entry->base = valid_entry->base;
2472                 entry->len = num;
2473                 valid_entry->base += num;
2474                 valid_entry->len -= num;
2475                 valid_entry = entry;
2476         }
2477
2478         /* Insert it into alloc list, not sorted */
2479         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2480
2481         pool->num_free -= valid_entry->len;
2482         pool->num_alloc += valid_entry->len;
2483
2484         return (valid_entry->base + pool->base);
2485 }
2486
2487 /**
2488  * bitmap_is_subset - Check whether src2 is subset of src1
2489  **/
2490 static inline int
2491 bitmap_is_subset(uint8_t src1, uint8_t src2)
2492 {
2493         return !((src1 ^ src2) & src2);
2494 }
2495
2496 static int
2497 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2498 {
2499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2500
2501         /* If DCB is not supported, only default TC is supported */
2502         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2503                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2504                 return -EINVAL;
2505         }
2506
2507         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2508                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2509                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2510                             enabled_tcmap);
2511                 return -EINVAL;
2512         }
2513         return I40E_SUCCESS;
2514 }
2515
2516 int
2517 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2518                                 struct i40e_vsi_vlan_pvid_info *info)
2519 {
2520         struct i40e_hw *hw;
2521         struct i40e_vsi_context ctxt;
2522         uint8_t vlan_flags = 0;
2523         int ret;
2524
2525         if (vsi == NULL || info == NULL) {
2526                 PMD_DRV_LOG(ERR, "invalid parameters");
2527                 return I40E_ERR_PARAM;
2528         }
2529
2530         if (info->on) {
2531                 vsi->info.pvid = info->config.pvid;
2532                 /**
2533                  * If insert pvid is enabled, only tagged pkts are
2534                  * allowed to be sent out.
2535                  */
2536                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2537                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2538         } else {
2539                 vsi->info.pvid = 0;
2540                 if (info->config.reject.tagged == 0)
2541                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2542
2543                 if (info->config.reject.untagged == 0)
2544                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2545         }
2546         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2547                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2548         vsi->info.port_vlan_flags |= vlan_flags;
2549         vsi->info.valid_sections =
2550                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2551         memset(&ctxt, 0, sizeof(ctxt));
2552         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2553         ctxt.seid = vsi->seid;
2554
2555         hw = I40E_VSI_TO_HW(vsi);
2556         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2557         if (ret != I40E_SUCCESS)
2558                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2559
2560         return ret;
2561 }
2562
2563 static int
2564 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2565 {
2566         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2567         int i, ret;
2568         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2569
2570         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2571         if (ret != I40E_SUCCESS)
2572                 return ret;
2573
2574         if (!vsi->seid) {
2575                 PMD_DRV_LOG(ERR, "seid not valid");
2576                 return -EINVAL;
2577         }
2578
2579         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2580         tc_bw_data.tc_valid_bits = enabled_tcmap;
2581         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2582                 tc_bw_data.tc_bw_credits[i] =
2583                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2584
2585         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2586         if (ret != I40E_SUCCESS) {
2587                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2588                 return ret;
2589         }
2590
2591         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2592                                         sizeof(vsi->info.qs_handle));
2593         return I40E_SUCCESS;
2594 }
2595
2596 static int
2597 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2598                                  struct i40e_aqc_vsi_properties_data *info,
2599                                  uint8_t enabled_tcmap)
2600 {
2601         int ret, total_tc = 0, i;
2602         uint16_t qpnum_per_tc, bsf, qp_idx;
2603
2604         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2605         if (ret != I40E_SUCCESS)
2606                 return ret;
2607
2608         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2609                 if (enabled_tcmap & (1 << i))
2610                         total_tc++;
2611         vsi->enabled_tc = enabled_tcmap;
2612
2613         /* Number of queues per enabled TC */
2614         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2615         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2616         bsf = rte_bsf32(qpnum_per_tc);
2617
2618         /* Adjust the queue number to actual queues that can be applied */
2619         vsi->nb_qps = qpnum_per_tc * total_tc;
2620
2621         /**
2622          * Configure TC and queue mapping parameters, for enabled TC,
2623          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2624          * default queue will serve it.
2625          */
2626         qp_idx = 0;
2627         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2628                 if (vsi->enabled_tc & (1 << i)) {
2629                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2630                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2631                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2632                         qp_idx += qpnum_per_tc;
2633                 } else
2634                         info->tc_mapping[i] = 0;
2635         }
2636
2637         /* Associate queue number with VSI */
2638         if (vsi->type == I40E_VSI_SRIOV) {
2639                 info->mapping_flags |=
2640                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2641                 for (i = 0; i < vsi->nb_qps; i++)
2642                         info->queue_mapping[i] =
2643                                 rte_cpu_to_le_16(vsi->base_queue + i);
2644         } else {
2645                 info->mapping_flags |=
2646                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2647                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2648         }
2649         info->valid_sections =
2650                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2651
2652         return I40E_SUCCESS;
2653 }
2654
2655 static int
2656 i40e_veb_release(struct i40e_veb *veb)
2657 {
2658         struct i40e_vsi *vsi;
2659         struct i40e_hw *hw;
2660
2661         if (veb == NULL || veb->associate_vsi == NULL)
2662                 return -EINVAL;
2663
2664         if (!TAILQ_EMPTY(&veb->head)) {
2665                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2666                 return -EACCES;
2667         }
2668
2669         vsi = veb->associate_vsi;
2670         hw = I40E_VSI_TO_HW(vsi);
2671
2672         vsi->uplink_seid = veb->uplink_seid;
2673         i40e_aq_delete_element(hw, veb->seid, NULL);
2674         rte_free(veb);
2675         vsi->veb = NULL;
2676         return I40E_SUCCESS;
2677 }
2678
2679 /* Setup a veb */
2680 static struct i40e_veb *
2681 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2682 {
2683         struct i40e_veb *veb;
2684         int ret;
2685         struct i40e_hw *hw;
2686
2687         if (NULL == pf || vsi == NULL) {
2688                 PMD_DRV_LOG(ERR, "veb setup failed, "
2689                             "associated VSI shouldn't null");
2690                 return NULL;
2691         }
2692         hw = I40E_PF_TO_HW(pf);
2693
2694         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2695         if (!veb) {
2696                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2697                 goto fail;
2698         }
2699
2700         veb->associate_vsi = vsi;
2701         TAILQ_INIT(&veb->head);
2702         veb->uplink_seid = vsi->uplink_seid;
2703
2704         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2705                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2706
2707         if (ret != I40E_SUCCESS) {
2708                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2709                             hw->aq.asq_last_status);
2710                 goto fail;
2711         }
2712
2713         /* get statistics index */
2714         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2715                                 &veb->stats_idx, NULL, NULL, NULL);
2716         if (ret != I40E_SUCCESS) {
2717                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2718                             hw->aq.asq_last_status);
2719                 goto fail;
2720         }
2721
2722         /* Get VEB bandwidth, to be implemented */
2723         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2724         vsi->uplink_seid = veb->seid;
2725
2726         return veb;
2727 fail:
2728         rte_free(veb);
2729         return NULL;
2730 }
2731
2732 int
2733 i40e_vsi_release(struct i40e_vsi *vsi)
2734 {
2735         struct i40e_pf *pf;
2736         struct i40e_hw *hw;
2737         struct i40e_vsi_list *vsi_list;
2738         int ret;
2739         struct i40e_mac_filter *f;
2740
2741         if (!vsi)
2742                 return I40E_SUCCESS;
2743
2744         pf = I40E_VSI_TO_PF(vsi);
2745         hw = I40E_VSI_TO_HW(vsi);
2746
2747         /* VSI has child to attach, release child first */
2748         if (vsi->veb) {
2749                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2750                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2751                                 return -1;
2752                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2753                 }
2754                 i40e_veb_release(vsi->veb);
2755         }
2756
2757         /* Remove all macvlan filters of the VSI */
2758         i40e_vsi_remove_all_macvlan_filter(vsi);
2759         TAILQ_FOREACH(f, &vsi->mac_list, next)
2760                 rte_free(f);
2761
2762         if (vsi->type != I40E_VSI_MAIN) {
2763                 /* Remove vsi from parent's sibling list */
2764                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2765                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2766                         return I40E_ERR_PARAM;
2767                 }
2768                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2769                                 &vsi->sib_vsi_list, list);
2770
2771                 /* Remove all switch element of the VSI */
2772                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2773                 if (ret != I40E_SUCCESS)
2774                         PMD_DRV_LOG(ERR, "Failed to delete element");
2775         }
2776         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2777
2778         if (vsi->type != I40E_VSI_SRIOV)
2779                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2780         rte_free(vsi);
2781
2782         return I40E_SUCCESS;
2783 }
2784
2785 static int
2786 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2787 {
2788         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2789         struct i40e_aqc_remove_macvlan_element_data def_filter;
2790         struct i40e_mac_filter_info filter;
2791         int ret;
2792
2793         if (vsi->type != I40E_VSI_MAIN)
2794                 return I40E_ERR_CONFIG;
2795         memset(&def_filter, 0, sizeof(def_filter));
2796         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2797                                         ETH_ADDR_LEN);
2798         def_filter.vlan_tag = 0;
2799         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2800                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2801         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2802         if (ret != I40E_SUCCESS) {
2803                 struct i40e_mac_filter *f;
2804                 struct ether_addr *mac;
2805
2806                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2807                             "macvlan filter");
2808                 /* It needs to add the permanent mac into mac list */
2809                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2810                 if (f == NULL) {
2811                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2812                         return I40E_ERR_NO_MEMORY;
2813                 }
2814                 mac = &f->mac_info.mac_addr;
2815                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2816                                 ETH_ADDR_LEN);
2817                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2818                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2819                 vsi->mac_num++;
2820
2821                 return ret;
2822         }
2823         (void)rte_memcpy(&filter.mac_addr,
2824                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2825         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2826         return i40e_vsi_add_mac(vsi, &filter);
2827 }
2828
2829 static int
2830 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2831 {
2832         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2833         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2834         struct i40e_hw *hw = &vsi->adapter->hw;
2835         i40e_status ret;
2836         int i;
2837
2838         memset(&bw_config, 0, sizeof(bw_config));
2839         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2840         if (ret != I40E_SUCCESS) {
2841                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2842                             hw->aq.asq_last_status);
2843                 return ret;
2844         }
2845
2846         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2847         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2848                                         &ets_sla_config, NULL);
2849         if (ret != I40E_SUCCESS) {
2850                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2851                             "configuration %u", hw->aq.asq_last_status);
2852                 return ret;
2853         }
2854
2855         /* Not store the info yet, just print out */
2856         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2857         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2858         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2859                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2860                             ets_sla_config.share_credits[i]);
2861                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2862                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2863                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2864                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2865                             (i * 4));
2866         }
2867
2868         return 0;
2869 }
2870
2871 /* Setup a VSI */
2872 struct i40e_vsi *
2873 i40e_vsi_setup(struct i40e_pf *pf,
2874                enum i40e_vsi_type type,
2875                struct i40e_vsi *uplink_vsi,
2876                uint16_t user_param)
2877 {
2878         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2879         struct i40e_vsi *vsi;
2880         struct i40e_mac_filter_info filter;
2881         int ret;
2882         struct i40e_vsi_context ctxt;
2883         struct ether_addr broadcast =
2884                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2885
2886         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2887                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2888                             "VSI link shouldn't be NULL");
2889                 return NULL;
2890         }
2891
2892         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2893                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2894                             "uplink VSI should be NULL");
2895                 return NULL;
2896         }
2897
2898         /* If uplink vsi didn't setup VEB, create one first */
2899         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2900                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2901
2902                 if (NULL == uplink_vsi->veb) {
2903                         PMD_DRV_LOG(ERR, "VEB setup failed");
2904                         return NULL;
2905                 }
2906         }
2907
2908         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2909         if (!vsi) {
2910                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2911                 return NULL;
2912         }
2913         TAILQ_INIT(&vsi->mac_list);
2914         vsi->type = type;
2915         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2916         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2917         vsi->parent_vsi = uplink_vsi;
2918         vsi->user_param = user_param;
2919         /* Allocate queues */
2920         switch (vsi->type) {
2921         case I40E_VSI_MAIN  :
2922                 vsi->nb_qps = pf->lan_nb_qps;
2923                 break;
2924         case I40E_VSI_SRIOV :
2925                 vsi->nb_qps = pf->vf_nb_qps;
2926                 break;
2927         case I40E_VSI_VMDQ2:
2928                 vsi->nb_qps = pf->vmdq_nb_qps;
2929                 break;
2930         case I40E_VSI_FDIR:
2931                 vsi->nb_qps = pf->fdir_nb_qps;
2932                 break;
2933         default:
2934                 goto fail_mem;
2935         }
2936         /*
2937          * The filter status descriptor is reported in rx queue 0,
2938          * while the tx queue for fdir filter programming has no
2939          * such constraints, can be non-zero queues.
2940          * To simplify it, choose FDIR vsi use queue 0 pair.
2941          * To make sure it will use queue 0 pair, queue allocation
2942          * need be done before this function is called
2943          */
2944         if (type != I40E_VSI_FDIR) {
2945                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2946                         if (ret < 0) {
2947                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2948                                                 vsi->seid, ret);
2949                                 goto fail_mem;
2950                         }
2951                         vsi->base_queue = ret;
2952         } else
2953                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2954
2955         /* VF has MSIX interrupt in VF range, don't allocate here */
2956         if (type != I40E_VSI_SRIOV) {
2957                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2958                 if (ret < 0) {
2959                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2960                         goto fail_queue_alloc;
2961                 }
2962                 vsi->msix_intr = ret;
2963         } else
2964                 vsi->msix_intr = 0;
2965         /* Add VSI */
2966         if (type == I40E_VSI_MAIN) {
2967                 /* For main VSI, no need to add since it's default one */
2968                 vsi->uplink_seid = pf->mac_seid;
2969                 vsi->seid = pf->main_vsi_seid;
2970                 /* Bind queues with specific MSIX interrupt */
2971                 /**
2972                  * Needs 2 interrupt at least, one for misc cause which will
2973                  * enabled from OS side, Another for queues binding the
2974                  * interrupt from device side only.
2975                  */
2976
2977                 /* Get default VSI parameters from hardware */
2978                 memset(&ctxt, 0, sizeof(ctxt));
2979                 ctxt.seid = vsi->seid;
2980                 ctxt.pf_num = hw->pf_id;
2981                 ctxt.uplink_seid = vsi->uplink_seid;
2982                 ctxt.vf_num = 0;
2983                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2984                 if (ret != I40E_SUCCESS) {
2985                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2986                         goto fail_msix_alloc;
2987                 }
2988                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2989                         sizeof(struct i40e_aqc_vsi_properties_data));
2990                 vsi->vsi_id = ctxt.vsi_number;
2991                 vsi->info.valid_sections = 0;
2992
2993                 /* Configure tc, enabled TC0 only */
2994                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2995                         I40E_SUCCESS) {
2996                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2997                         goto fail_msix_alloc;
2998                 }
2999
3000                 /* TC, queue mapping */
3001                 memset(&ctxt, 0, sizeof(ctxt));
3002                 vsi->info.valid_sections |=
3003                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3004                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3005                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3006                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3007                         sizeof(struct i40e_aqc_vsi_properties_data));
3008                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3009                                                 I40E_DEFAULT_TCMAP);
3010                 if (ret != I40E_SUCCESS) {
3011                         PMD_DRV_LOG(ERR, "Failed to configure "
3012                                     "TC queue mapping");
3013                         goto fail_msix_alloc;
3014                 }
3015                 ctxt.seid = vsi->seid;
3016                 ctxt.pf_num = hw->pf_id;
3017                 ctxt.uplink_seid = vsi->uplink_seid;
3018                 ctxt.vf_num = 0;
3019
3020                 /* Update VSI parameters */
3021                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3022                 if (ret != I40E_SUCCESS) {
3023                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3024                         goto fail_msix_alloc;
3025                 }
3026
3027                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3028                                                 sizeof(vsi->info.tc_mapping));
3029                 (void)rte_memcpy(&vsi->info.queue_mapping,
3030                                 &ctxt.info.queue_mapping,
3031                         sizeof(vsi->info.queue_mapping));
3032                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3033                 vsi->info.valid_sections = 0;
3034
3035                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3036                                 ETH_ADDR_LEN);
3037
3038                 /**
3039                  * Updating default filter settings are necessary to prevent
3040                  * reception of tagged packets.
3041                  * Some old firmware configurations load a default macvlan
3042                  * filter which accepts both tagged and untagged packets.
3043                  * The updating is to use a normal filter instead if needed.
3044                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3045                  * The firmware with correct configurations load the default
3046                  * macvlan filter which is expected and cannot be removed.
3047                  */
3048                 i40e_update_default_filter_setting(vsi);
3049         } else if (type == I40E_VSI_SRIOV) {
3050                 memset(&ctxt, 0, sizeof(ctxt));
3051                 /**
3052                  * For other VSI, the uplink_seid equals to uplink VSI's
3053                  * uplink_seid since they share same VEB
3054                  */
3055                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3056                 ctxt.pf_num = hw->pf_id;
3057                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3058                 ctxt.uplink_seid = vsi->uplink_seid;
3059                 ctxt.connection_type = 0x1;
3060                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3061
3062                 /* Configure switch ID */
3063                 ctxt.info.valid_sections |=
3064                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3065                 ctxt.info.switch_id =
3066                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3067                 /* Configure port/vlan */
3068                 ctxt.info.valid_sections |=
3069                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3070                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3071                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3072                                                 I40E_DEFAULT_TCMAP);
3073                 if (ret != I40E_SUCCESS) {
3074                         PMD_DRV_LOG(ERR, "Failed to configure "
3075                                     "TC queue mapping");
3076                         goto fail_msix_alloc;
3077                 }
3078                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3079                 ctxt.info.valid_sections |=
3080                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3081                 /**
3082                  * Since VSI is not created yet, only configure parameter,
3083                  * will add vsi below.
3084                  */
3085         } else if (type == I40E_VSI_VMDQ2) {
3086                 memset(&ctxt, 0, sizeof(ctxt));
3087                 /*
3088                  * For other VSI, the uplink_seid equals to uplink VSI's
3089                  * uplink_seid since they share same VEB
3090                  */
3091                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3092                 ctxt.pf_num = hw->pf_id;
3093                 ctxt.vf_num = 0;
3094                 ctxt.uplink_seid = vsi->uplink_seid;
3095                 ctxt.connection_type = 0x1;
3096                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3097
3098                 ctxt.info.valid_sections |=
3099                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3100                 /* user_param carries flag to enable loop back */
3101                 if (user_param) {
3102                         ctxt.info.switch_id =
3103                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3104                         ctxt.info.switch_id |=
3105                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3106                 }
3107
3108                 /* Configure port/vlan */
3109                 ctxt.info.valid_sections |=
3110                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3111                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3112                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3113                                                 I40E_DEFAULT_TCMAP);
3114                 if (ret != I40E_SUCCESS) {
3115                         PMD_DRV_LOG(ERR, "Failed to configure "
3116                                         "TC queue mapping");
3117                         goto fail_msix_alloc;
3118                 }
3119                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3120                 ctxt.info.valid_sections |=
3121                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3122         } else if (type == I40E_VSI_FDIR) {
3123                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3124                 ctxt.pf_num = hw->pf_id;
3125                 ctxt.vf_num = 0;
3126                 ctxt.uplink_seid = vsi->uplink_seid;
3127                 ctxt.connection_type = 0x1;     /* regular data port */
3128                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3129                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3130                                                 I40E_DEFAULT_TCMAP);
3131                 if (ret != I40E_SUCCESS) {
3132                         PMD_DRV_LOG(ERR, "Failed to configure "
3133                                         "TC queue mapping.");
3134                         goto fail_msix_alloc;
3135                 }
3136                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3137                 ctxt.info.valid_sections |=
3138                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3139         } else {
3140                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3141                 goto fail_msix_alloc;
3142         }
3143
3144         if (vsi->type != I40E_VSI_MAIN) {
3145                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3146                 if (ret) {
3147                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3148                                     hw->aq.asq_last_status);
3149                         goto fail_msix_alloc;
3150                 }
3151                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3152                 vsi->info.valid_sections = 0;
3153                 vsi->seid = ctxt.seid;
3154                 vsi->vsi_id = ctxt.vsi_number;
3155                 vsi->sib_vsi_list.vsi = vsi;
3156                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3157                                 &vsi->sib_vsi_list, list);
3158         }
3159
3160         /* MAC/VLAN configuration */
3161         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3162         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3163
3164         ret = i40e_vsi_add_mac(vsi, &filter);
3165         if (ret != I40E_SUCCESS) {
3166                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3167                 goto fail_msix_alloc;
3168         }
3169
3170         /* Get VSI BW information */
3171         i40e_vsi_dump_bw_config(vsi);
3172         return vsi;
3173 fail_msix_alloc:
3174         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3175 fail_queue_alloc:
3176         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3177 fail_mem:
3178         rte_free(vsi);
3179         return NULL;
3180 }
3181
3182 /* Configure vlan stripping on or off */
3183 int
3184 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3185 {
3186         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3187         struct i40e_vsi_context ctxt;
3188         uint8_t vlan_flags;
3189         int ret = I40E_SUCCESS;
3190
3191         /* Check if it has been already on or off */
3192         if (vsi->info.valid_sections &
3193                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3194                 if (on) {
3195                         if ((vsi->info.port_vlan_flags &
3196                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3197                                 return 0; /* already on */
3198                 } else {
3199                         if ((vsi->info.port_vlan_flags &
3200                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3201                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3202                                 return 0; /* already off */
3203                 }
3204         }
3205
3206         if (on)
3207                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3208         else
3209                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3210         vsi->info.valid_sections =
3211                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3212         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3213         vsi->info.port_vlan_flags |= vlan_flags;
3214         ctxt.seid = vsi->seid;
3215         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3216         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3217         if (ret)
3218                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3219                             on ? "enable" : "disable");
3220
3221         return ret;
3222 }
3223
3224 static int
3225 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3226 {
3227         struct rte_eth_dev_data *data = dev->data;
3228         int ret;
3229
3230         /* Apply vlan offload setting */
3231         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3232
3233         /* Apply double-vlan setting, not implemented yet */
3234
3235         /* Apply pvid setting */
3236         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3237                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3238         if (ret)
3239                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3240
3241         return ret;
3242 }
3243
3244 static int
3245 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3246 {
3247         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3248
3249         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3250 }
3251
3252 static int
3253 i40e_update_flow_control(struct i40e_hw *hw)
3254 {
3255 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3256         struct i40e_link_status link_status;
3257         uint32_t rxfc = 0, txfc = 0, reg;
3258         uint8_t an_info;
3259         int ret;
3260
3261         memset(&link_status, 0, sizeof(link_status));
3262         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3263         if (ret != I40E_SUCCESS) {
3264                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3265                 goto write_reg; /* Disable flow control */
3266         }
3267
3268         an_info = hw->phy.link_info.an_info;
3269         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3270                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3271                 ret = I40E_ERR_NOT_READY;
3272                 goto write_reg; /* Disable flow control */
3273         }
3274         /**
3275          * If link auto negotiation is enabled, flow control needs to
3276          * be configured according to it
3277          */
3278         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3279         case I40E_LINK_PAUSE_RXTX:
3280                 rxfc = 1;
3281                 txfc = 1;
3282                 hw->fc.current_mode = I40E_FC_FULL;
3283                 break;
3284         case I40E_AQ_LINK_PAUSE_RX:
3285                 rxfc = 1;
3286                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3287                 break;
3288         case I40E_AQ_LINK_PAUSE_TX:
3289                 txfc = 1;
3290                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3291                 break;
3292         default:
3293                 hw->fc.current_mode = I40E_FC_NONE;
3294                 break;
3295         }
3296
3297 write_reg:
3298         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3299                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3300         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3301         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3302         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3303         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3304
3305         return ret;
3306 }
3307
3308 /* PF setup */
3309 static int
3310 i40e_pf_setup(struct i40e_pf *pf)
3311 {
3312         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3313         struct i40e_filter_control_settings settings;
3314         struct i40e_vsi *vsi;
3315         int ret;
3316
3317         /* Clear all stats counters */
3318         pf->offset_loaded = FALSE;
3319         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3320         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3321
3322         ret = i40e_pf_get_switch_config(pf);
3323         if (ret != I40E_SUCCESS) {
3324                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3325                 return ret;
3326         }
3327         if (pf->flags & I40E_FLAG_FDIR) {
3328                 /* make queue allocated first, let FDIR use queue pair 0*/
3329                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3330                 if (ret != I40E_FDIR_QUEUE_ID) {
3331                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3332                                     " ret =%d", ret);
3333                         pf->flags &= ~I40E_FLAG_FDIR;
3334                 }
3335         }
3336         /*  main VSI setup */
3337         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3338         if (!vsi) {
3339                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3340                 return I40E_ERR_NOT_READY;
3341         }
3342         pf->main_vsi = vsi;
3343
3344         /* Configure filter control */
3345         memset(&settings, 0, sizeof(settings));
3346         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3347                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3348         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3349                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3350         else {
3351                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3352                                                 hw->func_caps.rss_table_size);
3353                 return I40E_ERR_PARAM;
3354         }
3355         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3356                         "size: %u\n", hw->func_caps.rss_table_size);
3357         pf->hash_lut_size = hw->func_caps.rss_table_size;
3358
3359         /* Enable ethtype and macvlan filters */
3360         settings.enable_ethtype = TRUE;
3361         settings.enable_macvlan = TRUE;
3362         ret = i40e_set_filter_control(hw, &settings);
3363         if (ret)
3364                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3365                                                                 ret);
3366
3367         /* Update flow control according to the auto negotiation */
3368         i40e_update_flow_control(hw);
3369
3370         return I40E_SUCCESS;
3371 }
3372
3373 int
3374 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3375 {
3376         uint32_t reg;
3377         uint16_t j;
3378
3379         /**
3380          * Set or clear TX Queue Disable flags,
3381          * which is required by hardware.
3382          */
3383         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3384         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3385
3386         /* Wait until the request is finished */
3387         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3388                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3389                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3390                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3391                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3392                                                         & 0x1))) {
3393                         break;
3394                 }
3395         }
3396         if (on) {
3397                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3398                         return I40E_SUCCESS; /* already on, skip next steps */
3399
3400                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3401                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3402         } else {
3403                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3404                         return I40E_SUCCESS; /* already off, skip next steps */
3405                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3406         }
3407         /* Write the register */
3408         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3409         /* Check the result */
3410         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3411                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3412                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3413                 if (on) {
3414                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3415                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3416                                 break;
3417                 } else {
3418                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3419                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3420                                 break;
3421                 }
3422         }
3423         /* Check if it is timeout */
3424         if (j >= I40E_CHK_Q_ENA_COUNT) {
3425                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3426                             (on ? "enable" : "disable"), q_idx);
3427                 return I40E_ERR_TIMEOUT;
3428         }
3429
3430         return I40E_SUCCESS;
3431 }
3432
3433 /* Swith on or off the tx queues */
3434 static int
3435 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3436 {
3437         struct rte_eth_dev_data *dev_data = pf->dev_data;
3438         struct i40e_tx_queue *txq;
3439         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3440         uint16_t i;
3441         int ret;
3442
3443         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3444                 txq = dev_data->tx_queues[i];
3445                 /* Don't operate the queue if not configured or
3446                  * if starting only per queue */
3447                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3448                         continue;
3449                 if (on)
3450                         ret = i40e_dev_tx_queue_start(dev, i);
3451                 else
3452                         ret = i40e_dev_tx_queue_stop(dev, i);
3453                 if ( ret != I40E_SUCCESS)
3454                         return ret;
3455         }
3456
3457         return I40E_SUCCESS;
3458 }
3459
3460 int
3461 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3462 {
3463         uint32_t reg;
3464         uint16_t j;
3465
3466         /* Wait until the request is finished */
3467         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3468                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3469                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3470                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3471                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3472                         break;
3473         }
3474
3475         if (on) {
3476                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3477                         return I40E_SUCCESS; /* Already on, skip next steps */
3478                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3479         } else {
3480                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3481                         return I40E_SUCCESS; /* Already off, skip next steps */
3482                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3483         }
3484
3485         /* Write the register */
3486         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3487         /* Check the result */
3488         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3489                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3490                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3491                 if (on) {
3492                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3493                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3494                                 break;
3495                 } else {
3496                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3497                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3498                                 break;
3499                 }
3500         }
3501
3502         /* Check if it is timeout */
3503         if (j >= I40E_CHK_Q_ENA_COUNT) {
3504                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3505                             (on ? "enable" : "disable"), q_idx);
3506                 return I40E_ERR_TIMEOUT;
3507         }
3508
3509         return I40E_SUCCESS;
3510 }
3511 /* Switch on or off the rx queues */
3512 static int
3513 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3514 {
3515         struct rte_eth_dev_data *dev_data = pf->dev_data;
3516         struct i40e_rx_queue *rxq;
3517         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3518         uint16_t i;
3519         int ret;
3520
3521         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3522                 rxq = dev_data->rx_queues[i];
3523                 /* Don't operate the queue if not configured or
3524                  * if starting only per queue */
3525                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3526                         continue;
3527                 if (on)
3528                         ret = i40e_dev_rx_queue_start(dev, i);
3529                 else
3530                         ret = i40e_dev_rx_queue_stop(dev, i);
3531                 if (ret != I40E_SUCCESS)
3532                         return ret;
3533         }
3534
3535         return I40E_SUCCESS;
3536 }
3537
3538 /* Switch on or off all the rx/tx queues */
3539 int
3540 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3541 {
3542         int ret;
3543
3544         if (on) {
3545                 /* enable rx queues before enabling tx queues */
3546                 ret = i40e_dev_switch_rx_queues(pf, on);
3547                 if (ret) {
3548                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3549                         return ret;
3550                 }
3551                 ret = i40e_dev_switch_tx_queues(pf, on);
3552         } else {
3553                 /* Stop tx queues before stopping rx queues */
3554                 ret = i40e_dev_switch_tx_queues(pf, on);
3555                 if (ret) {
3556                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3557                         return ret;
3558                 }
3559                 ret = i40e_dev_switch_rx_queues(pf, on);
3560         }
3561
3562         return ret;
3563 }
3564
3565 /* Initialize VSI for TX */
3566 static int
3567 i40e_dev_tx_init(struct i40e_pf *pf)
3568 {
3569         struct rte_eth_dev_data *data = pf->dev_data;
3570         uint16_t i;
3571         uint32_t ret = I40E_SUCCESS;
3572         struct i40e_tx_queue *txq;
3573
3574         for (i = 0; i < data->nb_tx_queues; i++) {
3575                 txq = data->tx_queues[i];
3576                 if (!txq || !txq->q_set)
3577                         continue;
3578                 ret = i40e_tx_queue_init(txq);
3579                 if (ret != I40E_SUCCESS)
3580                         break;
3581         }
3582
3583         return ret;
3584 }
3585
3586 /* Initialize VSI for RX */
3587 static int
3588 i40e_dev_rx_init(struct i40e_pf *pf)
3589 {
3590         struct rte_eth_dev_data *data = pf->dev_data;
3591         int ret = I40E_SUCCESS;
3592         uint16_t i;
3593         struct i40e_rx_queue *rxq;
3594
3595         i40e_pf_config_mq_rx(pf);
3596         for (i = 0; i < data->nb_rx_queues; i++) {
3597                 rxq = data->rx_queues[i];
3598                 if (!rxq || !rxq->q_set)
3599                         continue;
3600
3601                 ret = i40e_rx_queue_init(rxq);
3602                 if (ret != I40E_SUCCESS) {
3603                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3604                                     "initialization");
3605                         break;
3606                 }
3607         }
3608
3609         return ret;
3610 }
3611
3612 static int
3613 i40e_dev_rxtx_init(struct i40e_pf *pf)
3614 {
3615         int err;
3616
3617         err = i40e_dev_tx_init(pf);
3618         if (err) {
3619                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3620                 return err;
3621         }
3622         err = i40e_dev_rx_init(pf);
3623         if (err) {
3624                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3625                 return err;
3626         }
3627
3628         return err;
3629 }
3630
3631 static int
3632 i40e_vmdq_setup(struct rte_eth_dev *dev)
3633 {
3634         struct rte_eth_conf *conf = &dev->data->dev_conf;
3635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3636         int i, err, conf_vsis, j, loop;
3637         struct i40e_vsi *vsi;
3638         struct i40e_vmdq_info *vmdq_info;
3639         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3640         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3641
3642         /*
3643          * Disable interrupt to avoid message from VF. Furthermore, it will
3644          * avoid race condition in VSI creation/destroy.
3645          */
3646         i40e_pf_disable_irq0(hw);
3647
3648         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3649                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3650                 return -ENOTSUP;
3651         }
3652
3653         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3654         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3655                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3656                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3657                         pf->max_nb_vmdq_vsi);
3658                 return -ENOTSUP;
3659         }
3660
3661         if (pf->vmdq != NULL) {
3662                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3663                 return 0;
3664         }
3665
3666         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3667                                 sizeof(*vmdq_info) * conf_vsis, 0);
3668
3669         if (pf->vmdq == NULL) {
3670                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3671                 return -ENOMEM;
3672         }
3673
3674         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3675
3676         /* Create VMDQ VSI */
3677         for (i = 0; i < conf_vsis; i++) {
3678                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3679                                 vmdq_conf->enable_loop_back);
3680                 if (vsi == NULL) {
3681                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3682                         err = -1;
3683                         goto err_vsi_setup;
3684                 }
3685                 vmdq_info = &pf->vmdq[i];
3686                 vmdq_info->pf = pf;
3687                 vmdq_info->vsi = vsi;
3688         }
3689         pf->nb_cfg_vmdq_vsi = conf_vsis;
3690
3691         /* Configure Vlan */
3692         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3693         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3694                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3695                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3696                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3697                                         vmdq_conf->pool_map[i].vlan_id, j);
3698
3699                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3700                                                 vmdq_conf->pool_map[i].vlan_id);
3701                                 if (err) {
3702                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3703                                         err = -1;
3704                                         goto err_vsi_setup;
3705                                 }
3706                         }
3707                 }
3708         }
3709
3710         i40e_pf_enable_irq0(hw);
3711
3712         return 0;
3713
3714 err_vsi_setup:
3715         for (i = 0; i < conf_vsis; i++)
3716                 if (pf->vmdq[i].vsi == NULL)
3717                         break;
3718                 else
3719                         i40e_vsi_release(pf->vmdq[i].vsi);
3720
3721         rte_free(pf->vmdq);
3722         pf->vmdq = NULL;
3723         i40e_pf_enable_irq0(hw);
3724         return err;
3725 }
3726
3727 static void
3728 i40e_stat_update_32(struct i40e_hw *hw,
3729                    uint32_t reg,
3730                    bool offset_loaded,
3731                    uint64_t *offset,
3732                    uint64_t *stat)
3733 {
3734         uint64_t new_data;
3735
3736         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3737         if (!offset_loaded)
3738                 *offset = new_data;
3739
3740         if (new_data >= *offset)
3741                 *stat = (uint64_t)(new_data - *offset);
3742         else
3743                 *stat = (uint64_t)((new_data +
3744                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3745 }
3746
3747 static void
3748 i40e_stat_update_48(struct i40e_hw *hw,
3749                    uint32_t hireg,
3750                    uint32_t loreg,
3751                    bool offset_loaded,
3752                    uint64_t *offset,
3753                    uint64_t *stat)
3754 {
3755         uint64_t new_data;
3756
3757         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3758         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3759                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3760
3761         if (!offset_loaded)
3762                 *offset = new_data;
3763
3764         if (new_data >= *offset)
3765                 *stat = new_data - *offset;
3766         else
3767                 *stat = (uint64_t)((new_data +
3768                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3769
3770         *stat &= I40E_48_BIT_MASK;
3771 }
3772
3773 /* Disable IRQ0 */
3774 void
3775 i40e_pf_disable_irq0(struct i40e_hw *hw)
3776 {
3777         /* Disable all interrupt types */
3778         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3779         I40E_WRITE_FLUSH(hw);
3780 }
3781
3782 /* Enable IRQ0 */
3783 void
3784 i40e_pf_enable_irq0(struct i40e_hw *hw)
3785 {
3786         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3787                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3788                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3789                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3790         I40E_WRITE_FLUSH(hw);
3791 }
3792
3793 static void
3794 i40e_pf_config_irq0(struct i40e_hw *hw)
3795 {
3796         /* read pending request and disable first */
3797         i40e_pf_disable_irq0(hw);
3798         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3799         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3800                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3801
3802         /* Link no queues with irq0 */
3803         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3804                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3805 }
3806
3807 static void
3808 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3809 {
3810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3812         int i;
3813         uint16_t abs_vf_id;
3814         uint32_t index, offset, val;
3815
3816         if (!pf->vfs)
3817                 return;
3818         /**
3819          * Try to find which VF trigger a reset, use absolute VF id to access
3820          * since the reg is global register.
3821          */
3822         for (i = 0; i < pf->vf_num; i++) {
3823                 abs_vf_id = hw->func_caps.vf_base_id + i;
3824                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3825                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3826                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3827                 /* VFR event occured */
3828                 if (val & (0x1 << offset)) {
3829                         int ret;
3830
3831                         /* Clear the event first */
3832                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3833                                                         (0x1 << offset));
3834                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3835                         /**
3836                          * Only notify a VF reset event occured,
3837                          * don't trigger another SW reset
3838                          */
3839                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3840                         if (ret != I40E_SUCCESS)
3841                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3842                 }
3843         }
3844 }
3845
3846 static void
3847 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3848 {
3849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850         struct i40e_arq_event_info info;
3851         uint16_t pending, opcode;
3852         int ret;
3853
3854         info.buf_len = I40E_AQ_BUF_SZ;
3855         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3856         if (!info.msg_buf) {
3857                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3858                 return;
3859         }
3860
3861         pending = 1;
3862         while (pending) {
3863                 ret = i40e_clean_arq_element(hw, &info, &pending);
3864
3865                 if (ret != I40E_SUCCESS) {
3866                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3867                                     "aq_err: %u", hw->aq.asq_last_status);
3868                         break;
3869                 }
3870                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3871
3872                 switch (opcode) {
3873                 case i40e_aqc_opc_send_msg_to_pf:
3874                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3875                         i40e_pf_host_handle_vf_msg(dev,
3876                                         rte_le_to_cpu_16(info.desc.retval),
3877                                         rte_le_to_cpu_32(info.desc.cookie_high),
3878                                         rte_le_to_cpu_32(info.desc.cookie_low),
3879                                         info.msg_buf,
3880                                         info.msg_len);
3881                         break;
3882                 default:
3883                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3884                                     opcode);
3885                         break;
3886                 }
3887         }
3888         rte_free(info.msg_buf);
3889 }
3890
3891 /*
3892  * Interrupt handler is registered as the alarm callback for handling LSC
3893  * interrupt in a definite of time, in order to wait the NIC into a stable
3894  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3895  * no need for link down interrupt.
3896  */
3897 static void
3898 i40e_dev_interrupt_delayed_handler(void *param)
3899 {
3900         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3902         uint32_t icr0;
3903
3904         /* read interrupt causes again */
3905         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3906
3907 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3908         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3909                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3910         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3911                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3912         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3913                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3914         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3915                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3916         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3917                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3918                                                                 "state\n");
3919         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3920                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3921         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3922                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3923 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3924
3925         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3926                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3927                 i40e_dev_handle_vfr_event(dev);
3928         }
3929         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3930                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3931                 i40e_dev_handle_aq_msg(dev);
3932         }
3933
3934         /* handle the link up interrupt in an alarm callback */
3935         i40e_dev_link_update(dev, 0);
3936         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3937
3938         i40e_pf_enable_irq0(hw);
3939         rte_intr_enable(&(dev->pci_dev->intr_handle));
3940 }
3941
3942 /**
3943  * Interrupt handler triggered by NIC  for handling
3944  * specific interrupt.
3945  *
3946  * @param handle
3947  *  Pointer to interrupt handle.
3948  * @param param
3949  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3950  *
3951  * @return
3952  *  void
3953  */
3954 static void
3955 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3956                            void *param)
3957 {
3958         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3959         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960         uint32_t icr0;
3961
3962         /* Disable interrupt */
3963         i40e_pf_disable_irq0(hw);
3964
3965         /* read out interrupt causes */
3966         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3967
3968         /* No interrupt event indicated */
3969         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3970                 PMD_DRV_LOG(INFO, "No interrupt event");
3971                 goto done;
3972         }
3973 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3974         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3975                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3976         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3977                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3978         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3979                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3980         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3981                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3982         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3983                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3984         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3985                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3986         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3987                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3988 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3989
3990         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3991                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3992                 i40e_dev_handle_vfr_event(dev);
3993         }
3994         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3995                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3996                 i40e_dev_handle_aq_msg(dev);
3997         }
3998
3999         /* Link Status Change interrupt */
4000         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4001 #define I40E_US_PER_SECOND 1000000
4002                 struct rte_eth_link link;
4003
4004                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4005                 memset(&link, 0, sizeof(link));
4006                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4007                 i40e_dev_link_update(dev, 0);
4008
4009                 /*
4010                  * For link up interrupt, it needs to wait 1 second to let the
4011                  * hardware be a stable state. Otherwise several consecutive
4012                  * interrupts can be observed.
4013                  * For link down interrupt, no need to wait.
4014                  */
4015                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4016                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4017                         return;
4018                 else
4019                         _rte_eth_dev_callback_process(dev,
4020                                 RTE_ETH_EVENT_INTR_LSC);
4021         }
4022
4023 done:
4024         /* Enable interrupt */
4025         i40e_pf_enable_irq0(hw);
4026         rte_intr_enable(&(dev->pci_dev->intr_handle));
4027 }
4028
4029 static int
4030 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4031                          struct i40e_macvlan_filter *filter,
4032                          int total)
4033 {
4034         int ele_num, ele_buff_size;
4035         int num, actual_num, i;
4036         uint16_t flags;
4037         int ret = I40E_SUCCESS;
4038         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4039         struct i40e_aqc_add_macvlan_element_data *req_list;
4040
4041         if (filter == NULL  || total == 0)
4042                 return I40E_ERR_PARAM;
4043         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4044         ele_buff_size = hw->aq.asq_buf_size;
4045
4046         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4047         if (req_list == NULL) {
4048                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4049                 return I40E_ERR_NO_MEMORY;
4050         }
4051
4052         num = 0;
4053         do {
4054                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4055                 memset(req_list, 0, ele_buff_size);
4056
4057                 for (i = 0; i < actual_num; i++) {
4058                         (void)rte_memcpy(req_list[i].mac_addr,
4059                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4060                         req_list[i].vlan_tag =
4061                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4062
4063                         switch (filter[num + i].filter_type) {
4064                         case RTE_MAC_PERFECT_MATCH:
4065                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4066                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4067                                 break;
4068                         case RTE_MACVLAN_PERFECT_MATCH:
4069                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4070                                 break;
4071                         case RTE_MAC_HASH_MATCH:
4072                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4073                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4074                                 break;
4075                         case RTE_MACVLAN_HASH_MATCH:
4076                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4077                                 break;
4078                         default:
4079                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4080                                 ret = I40E_ERR_PARAM;
4081                                 goto DONE;
4082                         }
4083
4084                         req_list[i].queue_number = 0;
4085
4086                         req_list[i].flags = rte_cpu_to_le_16(flags);
4087                 }
4088
4089                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4090                                                 actual_num, NULL);
4091                 if (ret != I40E_SUCCESS) {
4092                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4093                         goto DONE;
4094                 }
4095                 num += actual_num;
4096         } while (num < total);
4097
4098 DONE:
4099         rte_free(req_list);
4100         return ret;
4101 }
4102
4103 static int
4104 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4105                             struct i40e_macvlan_filter *filter,
4106                             int total)
4107 {
4108         int ele_num, ele_buff_size;
4109         int num, actual_num, i;
4110         uint16_t flags;
4111         int ret = I40E_SUCCESS;
4112         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4113         struct i40e_aqc_remove_macvlan_element_data *req_list;
4114
4115         if (filter == NULL  || total == 0)
4116                 return I40E_ERR_PARAM;
4117
4118         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4119         ele_buff_size = hw->aq.asq_buf_size;
4120
4121         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4122         if (req_list == NULL) {
4123                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4124                 return I40E_ERR_NO_MEMORY;
4125         }
4126
4127         num = 0;
4128         do {
4129                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4130                 memset(req_list, 0, ele_buff_size);
4131
4132                 for (i = 0; i < actual_num; i++) {
4133                         (void)rte_memcpy(req_list[i].mac_addr,
4134                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4135                         req_list[i].vlan_tag =
4136                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4137
4138                         switch (filter[num + i].filter_type) {
4139                         case RTE_MAC_PERFECT_MATCH:
4140                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4141                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4142                                 break;
4143                         case RTE_MACVLAN_PERFECT_MATCH:
4144                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4145                                 break;
4146                         case RTE_MAC_HASH_MATCH:
4147                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4148                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4149                                 break;
4150                         case RTE_MACVLAN_HASH_MATCH:
4151                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4152                                 break;
4153                         default:
4154                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4155                                 ret = I40E_ERR_PARAM;
4156                                 goto DONE;
4157                         }
4158                         req_list[i].flags = rte_cpu_to_le_16(flags);
4159                 }
4160
4161                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4162                                                 actual_num, NULL);
4163                 if (ret != I40E_SUCCESS) {
4164                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4165                         goto DONE;
4166                 }
4167                 num += actual_num;
4168         } while (num < total);
4169
4170 DONE:
4171         rte_free(req_list);
4172         return ret;
4173 }
4174
4175 /* Find out specific MAC filter */
4176 static struct i40e_mac_filter *
4177 i40e_find_mac_filter(struct i40e_vsi *vsi,
4178                          struct ether_addr *macaddr)
4179 {
4180         struct i40e_mac_filter *f;
4181
4182         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4183                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4184                         return f;
4185         }
4186
4187         return NULL;
4188 }
4189
4190 static bool
4191 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4192                          uint16_t vlan_id)
4193 {
4194         uint32_t vid_idx, vid_bit;
4195
4196         if (vlan_id > ETH_VLAN_ID_MAX)
4197                 return 0;
4198
4199         vid_idx = I40E_VFTA_IDX(vlan_id);
4200         vid_bit = I40E_VFTA_BIT(vlan_id);
4201
4202         if (vsi->vfta[vid_idx] & vid_bit)
4203                 return 1;
4204         else
4205                 return 0;
4206 }
4207
4208 static void
4209 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4210                          uint16_t vlan_id, bool on)
4211 {
4212         uint32_t vid_idx, vid_bit;
4213
4214         if (vlan_id > ETH_VLAN_ID_MAX)
4215                 return;
4216
4217         vid_idx = I40E_VFTA_IDX(vlan_id);
4218         vid_bit = I40E_VFTA_BIT(vlan_id);
4219
4220         if (on)
4221                 vsi->vfta[vid_idx] |= vid_bit;
4222         else
4223                 vsi->vfta[vid_idx] &= ~vid_bit;
4224 }
4225
4226 /**
4227  * Find all vlan options for specific mac addr,
4228  * return with actual vlan found.
4229  */
4230 static inline int
4231 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4232                            struct i40e_macvlan_filter *mv_f,
4233                            int num, struct ether_addr *addr)
4234 {
4235         int i;
4236         uint32_t j, k;
4237
4238         /**
4239          * Not to use i40e_find_vlan_filter to decrease the loop time,
4240          * although the code looks complex.
4241           */
4242         if (num < vsi->vlan_num)
4243                 return I40E_ERR_PARAM;
4244
4245         i = 0;
4246         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4247                 if (vsi->vfta[j]) {
4248                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4249                                 if (vsi->vfta[j] & (1 << k)) {
4250                                         if (i > num - 1) {
4251                                                 PMD_DRV_LOG(ERR, "vlan number "
4252                                                             "not match");
4253                                                 return I40E_ERR_PARAM;
4254                                         }
4255                                         (void)rte_memcpy(&mv_f[i].macaddr,
4256                                                         addr, ETH_ADDR_LEN);
4257                                         mv_f[i].vlan_id =
4258                                                 j * I40E_UINT32_BIT_SIZE + k;
4259                                         i++;
4260                                 }
4261                         }
4262                 }
4263         }
4264         return I40E_SUCCESS;
4265 }
4266
4267 static inline int
4268 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4269                            struct i40e_macvlan_filter *mv_f,
4270                            int num,
4271                            uint16_t vlan)
4272 {
4273         int i = 0;
4274         struct i40e_mac_filter *f;
4275
4276         if (num < vsi->mac_num)
4277                 return I40E_ERR_PARAM;
4278
4279         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4280                 if (i > num - 1) {
4281                         PMD_DRV_LOG(ERR, "buffer number not match");
4282                         return I40E_ERR_PARAM;
4283                 }
4284                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4285                                 ETH_ADDR_LEN);
4286                 mv_f[i].vlan_id = vlan;
4287                 mv_f[i].filter_type = f->mac_info.filter_type;
4288                 i++;
4289         }
4290
4291         return I40E_SUCCESS;
4292 }
4293
4294 static int
4295 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4296 {
4297         int i, num;
4298         struct i40e_mac_filter *f;
4299         struct i40e_macvlan_filter *mv_f;
4300         int ret = I40E_SUCCESS;
4301
4302         if (vsi == NULL || vsi->mac_num == 0)
4303                 return I40E_ERR_PARAM;
4304
4305         /* Case that no vlan is set */
4306         if (vsi->vlan_num == 0)
4307                 num = vsi->mac_num;
4308         else
4309                 num = vsi->mac_num * vsi->vlan_num;
4310
4311         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4312         if (mv_f == NULL) {
4313                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4314                 return I40E_ERR_NO_MEMORY;
4315         }
4316
4317         i = 0;
4318         if (vsi->vlan_num == 0) {
4319                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4320                         (void)rte_memcpy(&mv_f[i].macaddr,
4321                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4322                         mv_f[i].vlan_id = 0;
4323                         i++;
4324                 }
4325         } else {
4326                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4327                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4328                                         vsi->vlan_num, &f->mac_info.mac_addr);
4329                         if (ret != I40E_SUCCESS)
4330                                 goto DONE;
4331                         i += vsi->vlan_num;
4332                 }
4333         }
4334
4335         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4336 DONE:
4337         rte_free(mv_f);
4338
4339         return ret;
4340 }
4341
4342 int
4343 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4344 {
4345         struct i40e_macvlan_filter *mv_f;
4346         int mac_num;
4347         int ret = I40E_SUCCESS;
4348
4349         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4350                 return I40E_ERR_PARAM;
4351
4352         /* If it's already set, just return */
4353         if (i40e_find_vlan_filter(vsi,vlan))
4354                 return I40E_SUCCESS;
4355
4356         mac_num = vsi->mac_num;
4357
4358         if (mac_num == 0) {
4359                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4360                 return I40E_ERR_PARAM;
4361         }
4362
4363         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4364
4365         if (mv_f == NULL) {
4366                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4367                 return I40E_ERR_NO_MEMORY;
4368         }
4369
4370         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4371
4372         if (ret != I40E_SUCCESS)
4373                 goto DONE;
4374
4375         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4376
4377         if (ret != I40E_SUCCESS)
4378                 goto DONE;
4379
4380         i40e_set_vlan_filter(vsi, vlan, 1);
4381
4382         vsi->vlan_num++;
4383         ret = I40E_SUCCESS;
4384 DONE:
4385         rte_free(mv_f);
4386         return ret;
4387 }
4388
4389 int
4390 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4391 {
4392         struct i40e_macvlan_filter *mv_f;
4393         int mac_num;
4394         int ret = I40E_SUCCESS;
4395
4396         /**
4397          * Vlan 0 is the generic filter for untagged packets
4398          * and can't be removed.
4399          */
4400         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4401                 return I40E_ERR_PARAM;
4402
4403         /* If can't find it, just return */
4404         if (!i40e_find_vlan_filter(vsi, vlan))
4405                 return I40E_ERR_PARAM;
4406
4407         mac_num = vsi->mac_num;
4408
4409         if (mac_num == 0) {
4410                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4411                 return I40E_ERR_PARAM;
4412         }
4413
4414         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4415
4416         if (mv_f == NULL) {
4417                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4418                 return I40E_ERR_NO_MEMORY;
4419         }
4420
4421         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4422
4423         if (ret != I40E_SUCCESS)
4424                 goto DONE;
4425
4426         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4427
4428         if (ret != I40E_SUCCESS)
4429                 goto DONE;
4430
4431         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4432         if (vsi->vlan_num == 1) {
4433                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4434                 if (ret != I40E_SUCCESS)
4435                         goto DONE;
4436
4437                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4438                 if (ret != I40E_SUCCESS)
4439                         goto DONE;
4440         }
4441
4442         i40e_set_vlan_filter(vsi, vlan, 0);
4443
4444         vsi->vlan_num--;
4445         ret = I40E_SUCCESS;
4446 DONE:
4447         rte_free(mv_f);
4448         return ret;
4449 }
4450
4451 int
4452 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4453 {
4454         struct i40e_mac_filter *f;
4455         struct i40e_macvlan_filter *mv_f;
4456         int i, vlan_num = 0;
4457         int ret = I40E_SUCCESS;
4458
4459         /* If it's add and we've config it, return */
4460         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4461         if (f != NULL)
4462                 return I40E_SUCCESS;
4463         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4464                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4465
4466                 /**
4467                  * If vlan_num is 0, that's the first time to add mac,
4468                  * set mask for vlan_id 0.
4469                  */
4470                 if (vsi->vlan_num == 0) {
4471                         i40e_set_vlan_filter(vsi, 0, 1);
4472                         vsi->vlan_num = 1;
4473                 }
4474                 vlan_num = vsi->vlan_num;
4475         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4476                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4477                 vlan_num = 1;
4478
4479         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4480         if (mv_f == NULL) {
4481                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4482                 return I40E_ERR_NO_MEMORY;
4483         }
4484
4485         for (i = 0; i < vlan_num; i++) {
4486                 mv_f[i].filter_type = mac_filter->filter_type;
4487                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4488                                 ETH_ADDR_LEN);
4489         }
4490
4491         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4492                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4493                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4494                                         &mac_filter->mac_addr);
4495                 if (ret != I40E_SUCCESS)
4496                         goto DONE;
4497         }
4498
4499         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4500         if (ret != I40E_SUCCESS)
4501                 goto DONE;
4502
4503         /* Add the mac addr into mac list */
4504         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4505         if (f == NULL) {
4506                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4507                 ret = I40E_ERR_NO_MEMORY;
4508                 goto DONE;
4509         }
4510         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4511                         ETH_ADDR_LEN);
4512         f->mac_info.filter_type = mac_filter->filter_type;
4513         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4514         vsi->mac_num++;
4515
4516         ret = I40E_SUCCESS;
4517 DONE:
4518         rte_free(mv_f);
4519
4520         return ret;
4521 }
4522
4523 int
4524 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4525 {
4526         struct i40e_mac_filter *f;
4527         struct i40e_macvlan_filter *mv_f;
4528         int i, vlan_num;
4529         enum rte_mac_filter_type filter_type;
4530         int ret = I40E_SUCCESS;
4531
4532         /* Can't find it, return an error */
4533         f = i40e_find_mac_filter(vsi, addr);
4534         if (f == NULL)
4535                 return I40E_ERR_PARAM;
4536
4537         vlan_num = vsi->vlan_num;
4538         filter_type = f->mac_info.filter_type;
4539         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4540                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4541                 if (vlan_num == 0) {
4542                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4543                         return I40E_ERR_PARAM;
4544                 }
4545         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4546                         filter_type == RTE_MAC_HASH_MATCH)
4547                 vlan_num = 1;
4548
4549         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4550         if (mv_f == NULL) {
4551                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4552                 return I40E_ERR_NO_MEMORY;
4553         }
4554
4555         for (i = 0; i < vlan_num; i++) {
4556                 mv_f[i].filter_type = filter_type;
4557                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4558                                 ETH_ADDR_LEN);
4559         }
4560         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4561                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4562                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4563                 if (ret != I40E_SUCCESS)
4564                         goto DONE;
4565         }
4566
4567         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4568         if (ret != I40E_SUCCESS)
4569                 goto DONE;
4570
4571         /* Remove the mac addr into mac list */
4572         TAILQ_REMOVE(&vsi->mac_list, f, next);
4573         rte_free(f);
4574         vsi->mac_num--;
4575
4576         ret = I40E_SUCCESS;
4577 DONE:
4578         rte_free(mv_f);
4579         return ret;
4580 }
4581
4582 /* Configure hash enable flags for RSS */
4583 uint64_t
4584 i40e_config_hena(uint64_t flags)
4585 {
4586         uint64_t hena = 0;
4587
4588         if (!flags)
4589                 return hena;
4590
4591         if (flags & ETH_RSS_NONF_IPV4_UDP)
4592                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4593         if (flags & ETH_RSS_NONF_IPV4_TCP)
4594                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4595         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4596                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4597         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4598                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4599         if (flags & ETH_RSS_FRAG_IPV4)
4600                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4601         if (flags & ETH_RSS_NONF_IPV6_UDP)
4602                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4603         if (flags & ETH_RSS_NONF_IPV6_TCP)
4604                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4605         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4606                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4607         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4608                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4609         if (flags & ETH_RSS_FRAG_IPV6)
4610                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4611         if (flags & ETH_RSS_L2_PAYLOAD)
4612                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4613
4614         return hena;
4615 }
4616
4617 /* Parse the hash enable flags */
4618 uint64_t
4619 i40e_parse_hena(uint64_t flags)
4620 {
4621         uint64_t rss_hf = 0;
4622
4623         if (!flags)
4624                 return rss_hf;
4625
4626         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4627                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4628         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4629                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4630         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4631                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4632         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4633                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4634         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4635                 rss_hf |= ETH_RSS_FRAG_IPV4;
4636         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4637                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4638         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4639                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4640         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4641                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4642         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4643                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4644         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4645                 rss_hf |= ETH_RSS_FRAG_IPV6;
4646         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4647                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4648
4649         return rss_hf;
4650 }
4651
4652 /* Disable RSS */
4653 static void
4654 i40e_pf_disable_rss(struct i40e_pf *pf)
4655 {
4656         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4657         uint64_t hena;
4658
4659         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4660         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4661         hena &= ~I40E_RSS_HENA_ALL;
4662         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4663         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4664         I40E_WRITE_FLUSH(hw);
4665 }
4666
4667 static int
4668 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4669 {
4670         uint32_t *hash_key;
4671         uint8_t hash_key_len;
4672         uint64_t rss_hf;
4673         uint16_t i;
4674         uint64_t hena;
4675
4676         hash_key = (uint32_t *)(rss_conf->rss_key);
4677         hash_key_len = rss_conf->rss_key_len;
4678         if (hash_key != NULL && hash_key_len >=
4679                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4680                 /* Fill in RSS hash key */
4681                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4682                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4683         }
4684
4685         rss_hf = rss_conf->rss_hf;
4686         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4687         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4688         hena &= ~I40E_RSS_HENA_ALL;
4689         hena |= i40e_config_hena(rss_hf);
4690         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4691         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4692         I40E_WRITE_FLUSH(hw);
4693
4694         return 0;
4695 }
4696
4697 static int
4698 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4699                          struct rte_eth_rss_conf *rss_conf)
4700 {
4701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4703         uint64_t hena;
4704
4705         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4706         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4707         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4708                 if (rss_hf != 0) /* Enable RSS */
4709                         return -EINVAL;
4710                 return 0; /* Nothing to do */
4711         }
4712         /* RSS enabled */
4713         if (rss_hf == 0) /* Disable RSS */
4714                 return -EINVAL;
4715
4716         return i40e_hw_rss_hash_set(hw, rss_conf);
4717 }
4718
4719 static int
4720 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4721                            struct rte_eth_rss_conf *rss_conf)
4722 {
4723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4725         uint64_t hena;
4726         uint16_t i;
4727
4728         if (hash_key != NULL) {
4729                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4730                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4731                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4732         }
4733         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4734         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4735         rss_conf->rss_hf = i40e_parse_hena(hena);
4736
4737         return 0;
4738 }
4739
4740 static int
4741 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4742 {
4743         switch (filter_type) {
4744         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4745                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4746                 break;
4747         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4748                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4749                 break;
4750         case RTE_TUNNEL_FILTER_IMAC_TENID:
4751                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4752                 break;
4753         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4754                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4755                 break;
4756         case ETH_TUNNEL_FILTER_IMAC:
4757                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4758                 break;
4759         default:
4760                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4761                 return -EINVAL;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static int
4768 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4769                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4770                         uint8_t add)
4771 {
4772         uint16_t ip_type;
4773         uint8_t tun_type = 0;
4774         int val, ret = 0;
4775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4776         struct i40e_vsi *vsi = pf->main_vsi;
4777         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4778         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4779
4780         cld_filter = rte_zmalloc("tunnel_filter",
4781                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4782                 0);
4783
4784         if (NULL == cld_filter) {
4785                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4786                 return -EINVAL;
4787         }
4788         pfilter = cld_filter;
4789
4790         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4791                         sizeof(struct ether_addr));
4792         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4793                         sizeof(struct ether_addr));
4794
4795         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4796         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4797                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4798                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4799                                 &tunnel_filter->ip_addr,
4800                                 sizeof(pfilter->ipaddr.v4.data));
4801         } else {
4802                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4803                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4804                                 &tunnel_filter->ip_addr,
4805                                 sizeof(pfilter->ipaddr.v6.data));
4806         }
4807
4808         /* check tunneled type */
4809         switch (tunnel_filter->tunnel_type) {
4810         case RTE_TUNNEL_TYPE_VXLAN:
4811                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4812                 break;
4813         default:
4814                 /* Other tunnel types is not supported. */
4815                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4816                 rte_free(cld_filter);
4817                 return -EINVAL;
4818         }
4819
4820         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4821                                                 &pfilter->flags);
4822         if (val < 0) {
4823                 rte_free(cld_filter);
4824                 return -EINVAL;
4825         }
4826
4827         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4828                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4829         pfilter->tenant_id = tunnel_filter->tenant_id;
4830         pfilter->queue_number = tunnel_filter->queue_id;
4831
4832         if (add)
4833                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4834         else
4835                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4836                                                 cld_filter, 1);
4837
4838         rte_free(cld_filter);
4839         return ret;
4840 }
4841
4842 static int
4843 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4844 {
4845         uint8_t i;
4846
4847         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4848                 if (pf->vxlan_ports[i] == port)
4849                         return i;
4850         }
4851
4852         return -1;
4853 }
4854
4855 static int
4856 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4857 {
4858         int  idx, ret;
4859         uint8_t filter_idx;
4860         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4861
4862         idx = i40e_get_vxlan_port_idx(pf, port);
4863
4864         /* Check if port already exists */
4865         if (idx >= 0) {
4866                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4867                 return -EINVAL;
4868         }
4869
4870         /* Now check if there is space to add the new port */
4871         idx = i40e_get_vxlan_port_idx(pf, 0);
4872         if (idx < 0) {
4873                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4874                         "not adding port %d", port);
4875                 return -ENOSPC;
4876         }
4877
4878         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4879                                         &filter_idx, NULL);
4880         if (ret < 0) {
4881                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4882                 return -1;
4883         }
4884
4885         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4886                          port,  filter_idx);
4887
4888         /* New port: add it and mark its index in the bitmap */
4889         pf->vxlan_ports[idx] = port;
4890         pf->vxlan_bitmap |= (1 << idx);
4891
4892         if (!(pf->flags & I40E_FLAG_VXLAN))
4893                 pf->flags |= I40E_FLAG_VXLAN;
4894
4895         return 0;
4896 }
4897
4898 static int
4899 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4900 {
4901         int idx;
4902         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4903
4904         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4905                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4906                 return -EINVAL;
4907         }
4908
4909         idx = i40e_get_vxlan_port_idx(pf, port);
4910
4911         if (idx < 0) {
4912                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4913                 return -EINVAL;
4914         }
4915
4916         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4917                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4918                 return -1;
4919         }
4920
4921         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4922                         port, idx);
4923
4924         pf->vxlan_ports[idx] = 0;
4925         pf->vxlan_bitmap &= ~(1 << idx);
4926
4927         if (!pf->vxlan_bitmap)
4928                 pf->flags &= ~I40E_FLAG_VXLAN;
4929
4930         return 0;
4931 }
4932
4933 /* Add UDP tunneling port */
4934 static int
4935 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4936                         struct rte_eth_udp_tunnel *udp_tunnel)
4937 {
4938         int ret = 0;
4939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4940
4941         if (udp_tunnel == NULL)
4942                 return -EINVAL;
4943
4944         switch (udp_tunnel->prot_type) {
4945         case RTE_TUNNEL_TYPE_VXLAN:
4946                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4947                 break;
4948
4949         case RTE_TUNNEL_TYPE_GENEVE:
4950         case RTE_TUNNEL_TYPE_TEREDO:
4951                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4952                 ret = -1;
4953                 break;
4954
4955         default:
4956                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4957                 ret = -1;
4958                 break;
4959         }
4960
4961         return ret;
4962 }
4963
4964 /* Remove UDP tunneling port */
4965 static int
4966 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4967                         struct rte_eth_udp_tunnel *udp_tunnel)
4968 {
4969         int ret = 0;
4970         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4971
4972         if (udp_tunnel == NULL)
4973                 return -EINVAL;
4974
4975         switch (udp_tunnel->prot_type) {
4976         case RTE_TUNNEL_TYPE_VXLAN:
4977                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4978                 break;
4979         case RTE_TUNNEL_TYPE_GENEVE:
4980         case RTE_TUNNEL_TYPE_TEREDO:
4981                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4982                 ret = -1;
4983                 break;
4984         default:
4985                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4986                 ret = -1;
4987                 break;
4988         }
4989
4990         return ret;
4991 }
4992
4993 /* Calculate the maximum number of contiguous PF queues that are configured */
4994 static int
4995 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4996 {
4997         struct rte_eth_dev_data *data = pf->dev_data;
4998         int i, num;
4999         struct i40e_rx_queue *rxq;
5000
5001         num = 0;
5002         for (i = 0; i < pf->lan_nb_qps; i++) {
5003                 rxq = data->rx_queues[i];
5004                 if (rxq && rxq->q_set)
5005                         num++;
5006                 else
5007                         break;
5008         }
5009
5010         return num;
5011 }
5012
5013 /* Configure RSS */
5014 static int
5015 i40e_pf_config_rss(struct i40e_pf *pf)
5016 {
5017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5018         struct rte_eth_rss_conf rss_conf;
5019         uint32_t i, lut = 0;
5020         uint16_t j, num;
5021
5022         /*
5023          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5024          * It's necessary to calulate the actual PF queues that are configured.
5025          */
5026         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5027                 num = i40e_pf_calc_configured_queues_num(pf);
5028                 num = i40e_align_floor(num);
5029         } else
5030                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5031
5032         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5033                         num);
5034
5035         if (num == 0) {
5036                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5037                 return -ENOTSUP;
5038         }
5039
5040         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5041                 if (j == num)
5042                         j = 0;
5043                 lut = (lut << 8) | (j & ((0x1 <<
5044                         hw->func_caps.rss_table_entry_width) - 1));
5045                 if ((i & 3) == 3)
5046                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5047         }
5048
5049         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5050         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5051                 i40e_pf_disable_rss(pf);
5052                 return 0;
5053         }
5054         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5055                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5056                 /* Random default keys */
5057                 static uint32_t rss_key_default[] = {0x6b793944,
5058                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5059                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5060                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5061
5062                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5063                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5064                                                         sizeof(uint32_t);
5065         }
5066
5067         return i40e_hw_rss_hash_set(hw, &rss_conf);
5068 }
5069
5070 static int
5071 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5072                         struct rte_eth_tunnel_filter_conf *filter)
5073 {
5074         if (pf == NULL || filter == NULL) {
5075                 PMD_DRV_LOG(ERR, "Invalid parameter");
5076                 return -EINVAL;
5077         }
5078
5079         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5080                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5081                 return -EINVAL;
5082         }
5083
5084         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5085                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5086                 return -EINVAL;
5087         }
5088
5089         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5090                 (is_zero_ether_addr(filter->outer_mac))) {
5091                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5092                 return -EINVAL;
5093         }
5094
5095         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5096                 (is_zero_ether_addr(filter->inner_mac))) {
5097                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5098                 return -EINVAL;
5099         }
5100
5101         return 0;
5102 }
5103
5104 static int
5105 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5106                         void *arg)
5107 {
5108         struct rte_eth_tunnel_filter_conf *filter;
5109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5110         int ret = I40E_SUCCESS;
5111
5112         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5113
5114         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5115                 return I40E_ERR_PARAM;
5116
5117         switch (filter_op) {
5118         case RTE_ETH_FILTER_NOP:
5119                 if (!(pf->flags & I40E_FLAG_VXLAN))
5120                         ret = I40E_NOT_SUPPORTED;
5121         case RTE_ETH_FILTER_ADD:
5122                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5123                 break;
5124         case RTE_ETH_FILTER_DELETE:
5125                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5126                 break;
5127         default:
5128                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5129                 ret = I40E_ERR_PARAM;
5130                 break;
5131         }
5132
5133         return ret;
5134 }
5135
5136 static int
5137 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5138 {
5139         int ret = 0;
5140         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5141
5142         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5143                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5144                 return -ENOTSUP;
5145         }
5146
5147         /* RSS setup */
5148         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5149                 ret = i40e_pf_config_rss(pf);
5150         else
5151                 i40e_pf_disable_rss(pf);
5152
5153         return ret;
5154 }
5155
5156 /* Get the symmetric hash enable configurations per port */
5157 static void
5158 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5159 {
5160         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5161
5162         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5163 }
5164
5165 /* Set the symmetric hash enable configurations per port */
5166 static void
5167 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5168 {
5169         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5170
5171         if (enable > 0) {
5172                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5173                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5174                                                         "been enabled");
5175                         return;
5176                 }
5177                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5178         } else {
5179                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5180                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5181                                                         "been disabled");
5182                         return;
5183                 }
5184                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5185         }
5186         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5187         I40E_WRITE_FLUSH(hw);
5188 }
5189
5190 /*
5191  * Get global configurations of hash function type and symmetric hash enable
5192  * per flow type (pctype). Note that global configuration means it affects all
5193  * the ports on the same NIC.
5194  */
5195 static int
5196 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5197                                    struct rte_eth_hash_global_conf *g_cfg)
5198 {
5199         uint32_t reg, mask = I40E_FLOW_TYPES;
5200         uint32_t i;
5201         enum i40e_filter_pctype pctype;
5202
5203         memset(g_cfg, 0, sizeof(*g_cfg));
5204         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5205         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5206                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5207         else
5208                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5209         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5210                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5211
5212         for (i = 0; mask && i < RTE_ETH_FLOW_TYPE_MAX; i++) {
5213                 if (!(mask & (1UL << i)))
5214                         continue;
5215                 mask &= ~(1UL << i);
5216                 /* Bit set indicats the coresponding flow type is supported */
5217                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5218                 pctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);
5219                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5220                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5221                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5222         }
5223
5224         return 0;
5225 }
5226
5227 static int
5228 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5229 {
5230         uint32_t i;
5231         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5232
5233         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5234                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5235                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5236                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5237                                                 g_cfg->hash_func);
5238                 return -EINVAL;
5239         }
5240
5241         /*
5242          * As i40e supports less than 32 flow types, only first 32 bits need to
5243          * be checked.
5244          */
5245         mask0 = g_cfg->valid_bit_mask[0];
5246         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5247                 if (i == 0) {
5248                         /* Check if any unsupported flow type configured */
5249                         if ((mask0 | i40e_mask) ^ i40e_mask)
5250                                 goto mask_err;
5251                 } else {
5252                         if (g_cfg->valid_bit_mask[i])
5253                                 goto mask_err;
5254                 }
5255         }
5256
5257         return 0;
5258
5259 mask_err:
5260         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5261
5262         return -EINVAL;
5263 }
5264
5265 /*
5266  * Set global configurations of hash function type and symmetric hash enable
5267  * per flow type (pctype). Note any modifying global configuration will affect
5268  * all the ports on the same NIC.
5269  */
5270 static int
5271 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5272                                    struct rte_eth_hash_global_conf *g_cfg)
5273 {
5274         int ret;
5275         uint32_t i, reg;
5276         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5277         enum i40e_filter_pctype pctype;
5278
5279         /* Check the input parameters */
5280         ret = i40e_hash_global_config_check(g_cfg);
5281         if (ret < 0)
5282                 return ret;
5283
5284         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5285                 if (!(mask0 & (1UL << i)))
5286                         continue;
5287                 mask0 &= ~(1UL << i);
5288                 pctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);
5289                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5290                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5291                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5292         }
5293
5294         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5295         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5296                 /* Toeplitz */
5297                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5298                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5299                                                                 "Toeplitz");
5300                         goto out;
5301                 }
5302                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5303         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5304                 /* Simple XOR */
5305                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5306                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5307                                                         "Simple XOR");
5308                         goto out;
5309                 }
5310                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5311         } else
5312                 /* Use the default, and keep it as it is */
5313                 goto out;
5314
5315         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5316
5317 out:
5318         I40E_WRITE_FLUSH(hw);
5319
5320         return 0;
5321 }
5322
5323 static int
5324 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5325 {
5326         int ret = 0;
5327
5328         if (!hw || !info) {
5329                 PMD_DRV_LOG(ERR, "Invalid pointer");
5330                 return -EFAULT;
5331         }
5332
5333         switch (info->info_type) {
5334         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5335                 i40e_get_symmetric_hash_enable_per_port(hw,
5336                                         &(info->info.enable));
5337                 break;
5338         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5339                 ret = i40e_get_hash_filter_global_config(hw,
5340                                 &(info->info.global_conf));
5341                 break;
5342         default:
5343                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5344                                                         info->info_type);
5345                 ret = -EINVAL;
5346                 break;
5347         }
5348
5349         return ret;
5350 }
5351
5352 static int
5353 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5354 {
5355         int ret = 0;
5356
5357         if (!hw || !info) {
5358                 PMD_DRV_LOG(ERR, "Invalid pointer");
5359                 return -EFAULT;
5360         }
5361
5362         switch (info->info_type) {
5363         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5364                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5365                 break;
5366         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5367                 ret = i40e_set_hash_filter_global_config(hw,
5368                                 &(info->info.global_conf));
5369                 break;
5370         default:
5371                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5372                                                         info->info_type);
5373                 ret = -EINVAL;
5374                 break;
5375         }
5376
5377         return ret;
5378 }
5379
5380 /* Operations for hash function */
5381 static int
5382 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5383                       enum rte_filter_op filter_op,
5384                       void *arg)
5385 {
5386         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387         int ret = 0;
5388
5389         switch (filter_op) {
5390         case RTE_ETH_FILTER_NOP:
5391                 break;
5392         case RTE_ETH_FILTER_GET:
5393                 ret = i40e_hash_filter_get(hw,
5394                         (struct rte_eth_hash_filter_info *)arg);
5395                 break;
5396         case RTE_ETH_FILTER_SET:
5397                 ret = i40e_hash_filter_set(hw,
5398                         (struct rte_eth_hash_filter_info *)arg);
5399                 break;
5400         default:
5401                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5402                                                                 filter_op);
5403                 ret = -ENOTSUP;
5404                 break;
5405         }
5406
5407         return ret;
5408 }
5409
5410 /*
5411  * Configure ethertype filter, which can director packet by filtering
5412  * with mac address and ether_type or only ether_type
5413  */
5414 static int
5415 i40e_ethertype_filter_set(struct i40e_pf *pf,
5416                         struct rte_eth_ethertype_filter *filter,
5417                         bool add)
5418 {
5419         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5420         struct i40e_control_filter_stats stats;
5421         uint16_t flags = 0;
5422         int ret;
5423
5424         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5425                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5426                 return -EINVAL;
5427         }
5428         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5429                 filter->ether_type == ETHER_TYPE_IPv6) {
5430                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5431                         " control packet filter.", filter->ether_type);
5432                 return -EINVAL;
5433         }
5434         if (filter->ether_type == ETHER_TYPE_VLAN)
5435                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5436                         " not supported.");
5437
5438         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5439                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5440         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5441                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5442         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5443
5444         memset(&stats, 0, sizeof(stats));
5445         ret = i40e_aq_add_rem_control_packet_filter(hw,
5446                         filter->mac_addr.addr_bytes,
5447                         filter->ether_type, flags,
5448                         pf->main_vsi->seid,
5449                         filter->queue, add, &stats, NULL);
5450
5451         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5452                          " mac_etype_used = %u, etype_used = %u,"
5453                          " mac_etype_free = %u, etype_free = %u\n",
5454                          ret, stats.mac_etype_used, stats.etype_used,
5455                          stats.mac_etype_free, stats.etype_free);
5456         if (ret < 0)
5457                 return -ENOSYS;
5458         return 0;
5459 }
5460
5461 /*
5462  * Handle operations for ethertype filter.
5463  */
5464 static int
5465 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5466                                 enum rte_filter_op filter_op,
5467                                 void *arg)
5468 {
5469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5470         int ret = 0;
5471
5472         if (filter_op == RTE_ETH_FILTER_NOP)
5473                 return ret;
5474
5475         if (arg == NULL) {
5476                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5477                             filter_op);
5478                 return -EINVAL;
5479         }
5480
5481         switch (filter_op) {
5482         case RTE_ETH_FILTER_ADD:
5483                 ret = i40e_ethertype_filter_set(pf,
5484                         (struct rte_eth_ethertype_filter *)arg,
5485                         TRUE);
5486                 break;
5487         case RTE_ETH_FILTER_DELETE:
5488                 ret = i40e_ethertype_filter_set(pf,
5489                         (struct rte_eth_ethertype_filter *)arg,
5490                         FALSE);
5491                 break;
5492         default:
5493                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5494                 ret = -ENOSYS;
5495                 break;
5496         }
5497         return ret;
5498 }
5499
5500 static int
5501 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5502                      enum rte_filter_type filter_type,
5503                      enum rte_filter_op filter_op,
5504                      void *arg)
5505 {
5506         int ret = 0;
5507
5508         if (dev == NULL)
5509                 return -EINVAL;
5510
5511         switch (filter_type) {
5512         case RTE_ETH_FILTER_HASH:
5513                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5514                 break;
5515         case RTE_ETH_FILTER_MACVLAN:
5516                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5517                 break;
5518         case RTE_ETH_FILTER_ETHERTYPE:
5519                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5520                 break;
5521         case RTE_ETH_FILTER_TUNNEL:
5522                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5523                 break;
5524         case RTE_ETH_FILTER_FDIR:
5525                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5526                 break;
5527         default:
5528                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5529                                                         filter_type);
5530                 ret = -EINVAL;
5531                 break;
5532         }
5533
5534         return ret;
5535 }
5536
5537 /*
5538  * As some registers wouldn't be reset unless a global hardware reset,
5539  * hardware initialization is needed to put those registers into an
5540  * expected initial state.
5541  */
5542 static void
5543 i40e_hw_init(struct i40e_hw *hw)
5544 {
5545         /* clear the PF Queue Filter control register */
5546         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5547
5548         /* Disable symmetric hash per port */
5549         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5550 }
5551
5552 enum i40e_filter_pctype
5553 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5554 {
5555         static const enum i40e_filter_pctype
5556                 pctype_table[RTE_ETH_FLOW_TYPE_MAX] = {
5557                 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5558                 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5559                 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5560                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5561                                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5562                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5563                                         I40E_FILTER_PCTYPE_FRAG_IPV4,
5564                 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5565                 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5566                 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5567                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5568                                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5569                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5570                                         I40E_FILTER_PCTYPE_FRAG_IPV6,
5571         };
5572
5573         return pctype_table[flow_type];
5574 }
5575
5576 enum rte_eth_flow_type
5577 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5578 {
5579         static const enum rte_eth_flow_type
5580                 flowtype_table[RTE_ETH_FLOW_TYPE_MAX] = {
5581                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5582                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5583                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5584                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5585                                         RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5586                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5587                                         RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5588                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5589                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5590                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5591                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5592                                         RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5593                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5594                                         RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5595         };
5596
5597         return flowtype_table[pctype];
5598 }
5599
5600 static int
5601 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5602 {
5603         struct i40e_aq_desc desc;
5604         enum i40e_status_code status;
5605
5606         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5607         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5608         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5609         if (status < 0)
5610                 return status;
5611
5612         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5613                                         (CHAR_BIT * sizeof(uint32_t))) +
5614                                 rte_le_to_cpu_32(desc.params.internal.param3);
5615
5616         return status;
5617 }
5618
5619 /*
5620  * On X710, performance number is far from the expectation on recent firmware
5621  * versions. The fix for this issue may not be integrated in the following
5622  * firmware version. So the workaround in software driver is needed. It needs
5623  * to modify the initial values of 3 internal only registers. Note that the
5624  * workaround can be removed when it is fixed in firmware in the future.
5625  */
5626 static void
5627 i40e_configure_registers(struct i40e_hw *hw)
5628 {
5629 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5630 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5631 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5632 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5633 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5634 #define I40E_GL_SWR_PM_UP_THR_VALUE      0x03030303
5635
5636         static const struct {
5637                 uint32_t addr;
5638                 uint64_t val;
5639         } reg_table[] = {
5640                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5641                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5642                 {I40E_GL_SWR_PM_UP_THR, I40E_GL_SWR_PM_UP_THR_VALUE},
5643         };
5644         uint64_t reg;
5645         uint32_t i;
5646         int ret;
5647
5648         /* Below fix is for X710 only */
5649         if (i40e_is_40G_device(hw->device_id))
5650                 return;
5651
5652         for (i = 0; i < RTE_DIM(reg_table); i++) {
5653                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5654                 if (ret < 0) {
5655                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5656                                                         reg_table[i].addr);
5657                         break;
5658                 }
5659                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5660                                                 reg_table[i].addr, reg);
5661                 if (reg == reg_table[i].val)
5662                         continue;
5663
5664                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5665                                                 reg_table[i].val, NULL);
5666                 if (ret < 0) {
5667                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5668                                 "address of 0x%"PRIx32, reg_table[i].val,
5669                                                         reg_table[i].addr);
5670                         break;
5671                 }
5672                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5673                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5674         }
5675 }