4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds*/
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 static int eth_i40e_dev_init(\
97 __attribute__((unused)) struct eth_driver *eth_drv,
98 struct rte_eth_dev *eth_dev);
99 static int i40e_dev_configure(struct rte_eth_dev *dev);
100 static int i40e_dev_start(struct rte_eth_dev *dev);
101 static void i40e_dev_stop(struct rte_eth_dev *dev);
102 static void i40e_dev_close(struct rte_eth_dev *dev);
103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
110 struct rte_eth_stats *stats);
111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
117 struct rte_eth_dev_info *dev_info);
118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
130 struct rte_eth_fc_conf *fc_conf);
131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_pfc_conf *pfc_conf);
133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
134 struct ether_addr *mac_addr,
137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
139 struct rte_eth_rss_reta_entry64 *reta_conf,
141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
142 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40e_get_cap(struct i40e_hw *hw);
146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
147 static int i40e_pf_setup(struct i40e_pf *pf);
148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
151 bool offset_loaded, uint64_t *offset, uint64_t *stat);
152 static void i40e_stat_update_48(struct i40e_hw *hw,
158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
159 static void i40e_dev_interrupt_handler(
160 __rte_unused struct rte_intr_handle *handle, void *param);
161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
162 uint32_t base, uint32_t num);
163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
169 static int i40e_veb_release(struct i40e_veb *veb);
170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
171 struct i40e_vsi *vsi);
172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
175 struct i40e_macvlan_filter *mv_f,
177 struct ether_addr *addr);
178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
179 struct i40e_macvlan_filter *mv_f,
182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
184 struct rte_eth_rss_conf *rss_conf);
185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
186 struct rte_eth_rss_conf *rss_conf);
187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
188 struct rte_eth_udp_tunnel *udp_tunnel);
189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
190 struct rte_eth_udp_tunnel *udp_tunnel);
191 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
192 enum rte_filter_type filter_type,
193 enum rte_filter_op filter_op,
196 /* Default hash key buffer for RSS */
197 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
199 static struct rte_pci_id pci_id_i40e_map[] = {
200 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
201 #include "rte_pci_dev_ids.h"
202 { .vendor_id = 0, /* sentinel */ },
205 static struct eth_dev_ops i40e_eth_dev_ops = {
206 .dev_configure = i40e_dev_configure,
207 .dev_start = i40e_dev_start,
208 .dev_stop = i40e_dev_stop,
209 .dev_close = i40e_dev_close,
210 .promiscuous_enable = i40e_dev_promiscuous_enable,
211 .promiscuous_disable = i40e_dev_promiscuous_disable,
212 .allmulticast_enable = i40e_dev_allmulticast_enable,
213 .allmulticast_disable = i40e_dev_allmulticast_disable,
214 .dev_set_link_up = i40e_dev_set_link_up,
215 .dev_set_link_down = i40e_dev_set_link_down,
216 .link_update = i40e_dev_link_update,
217 .stats_get = i40e_dev_stats_get,
218 .stats_reset = i40e_dev_stats_reset,
219 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
220 .dev_infos_get = i40e_dev_info_get,
221 .vlan_filter_set = i40e_vlan_filter_set,
222 .vlan_tpid_set = i40e_vlan_tpid_set,
223 .vlan_offload_set = i40e_vlan_offload_set,
224 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
225 .vlan_pvid_set = i40e_vlan_pvid_set,
226 .rx_queue_start = i40e_dev_rx_queue_start,
227 .rx_queue_stop = i40e_dev_rx_queue_stop,
228 .tx_queue_start = i40e_dev_tx_queue_start,
229 .tx_queue_stop = i40e_dev_tx_queue_stop,
230 .rx_queue_setup = i40e_dev_rx_queue_setup,
231 .rx_queue_release = i40e_dev_rx_queue_release,
232 .rx_queue_count = i40e_dev_rx_queue_count,
233 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
234 .tx_queue_setup = i40e_dev_tx_queue_setup,
235 .tx_queue_release = i40e_dev_tx_queue_release,
236 .dev_led_on = i40e_dev_led_on,
237 .dev_led_off = i40e_dev_led_off,
238 .flow_ctrl_set = i40e_flow_ctrl_set,
239 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
240 .mac_addr_add = i40e_macaddr_add,
241 .mac_addr_remove = i40e_macaddr_remove,
242 .reta_update = i40e_dev_rss_reta_update,
243 .reta_query = i40e_dev_rss_reta_query,
244 .rss_hash_update = i40e_dev_rss_hash_update,
245 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
246 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
247 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
248 .filter_ctrl = i40e_dev_filter_ctrl,
251 static struct eth_driver rte_i40e_pmd = {
253 .name = "rte_i40e_pmd",
254 .id_table = pci_id_i40e_map,
255 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
257 .eth_dev_init = eth_i40e_dev_init,
258 .dev_private_size = sizeof(struct i40e_adapter),
262 i40e_align_floor(int n)
266 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
270 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
271 struct rte_eth_link *link)
273 struct rte_eth_link *dst = link;
274 struct rte_eth_link *src = &(dev->data->dev_link);
276 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
277 *(uint64_t *)src) == 0)
284 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
285 struct rte_eth_link *link)
287 struct rte_eth_link *dst = &(dev->data->dev_link);
288 struct rte_eth_link *src = link;
290 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
291 *(uint64_t *)src) == 0)
298 * Driver initialization routine.
299 * Invoked once at EAL init time.
300 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
303 rte_i40e_pmd_init(const char *name __rte_unused,
304 const char *params __rte_unused)
306 PMD_INIT_FUNC_TRACE();
307 rte_eth_driver_register(&rte_i40e_pmd);
312 static struct rte_driver rte_i40e_driver = {
314 .init = rte_i40e_pmd_init,
317 PMD_REGISTER_DRIVER(rte_i40e_driver);
320 * Initialize registers for flexible payload, which should be set by NVM.
321 * This should be removed from code once it is fixed in NVM.
323 #ifndef I40E_GLQF_ORT
324 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
326 #ifndef I40E_GLQF_PIT
327 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
330 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
332 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
333 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
334 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
335 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
336 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
337 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
338 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
339 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
340 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
341 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
343 /* GLQF_PIT Registers */
344 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
345 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
349 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
350 struct rte_eth_dev *dev)
352 struct rte_pci_device *pci_dev;
353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
355 struct i40e_vsi *vsi;
360 PMD_INIT_FUNC_TRACE();
362 dev->dev_ops = &i40e_eth_dev_ops;
363 dev->rx_pkt_burst = i40e_recv_pkts;
364 dev->tx_pkt_burst = i40e_xmit_pkts;
366 /* for secondary processes, we don't initialise any further as primary
367 * has already done this work. Only check we don't need a different
369 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
370 if (dev->data->scattered_rx)
371 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
374 pci_dev = dev->pci_dev;
375 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
376 pf->adapter->eth_dev = dev;
377 pf->dev_data = dev->data;
379 hw->back = I40E_PF_TO_ADAPTER(pf);
380 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
382 PMD_INIT_LOG(ERR, "Hardware is not available, "
383 "as address is NULL");
387 hw->vendor_id = pci_dev->id.vendor_id;
388 hw->device_id = pci_dev->id.device_id;
389 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
390 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
391 hw->bus.device = pci_dev->addr.devid;
392 hw->bus.func = pci_dev->addr.function;
394 /* Make sure all is clean before doing PF reset */
397 /* Reset here to make sure all is clean for each PF */
398 ret = i40e_pf_reset(hw);
400 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
404 /* Initialize the shared code (base driver) */
405 ret = i40e_init_shared_code(hw);
407 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
412 * To work around the NVM issue,initialize registers
413 * for flexible payload by software.
414 * It should be removed once issues are fixed in NVM.
416 i40e_flex_payload_reg_init(hw);
418 /* Initialize the parameters for adminq */
419 i40e_init_adminq_parameter(hw);
420 ret = i40e_init_adminq(hw);
421 if (ret != I40E_SUCCESS) {
422 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
425 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
426 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
427 hw->aq.api_maj_ver, hw->aq.api_min_ver,
428 ((hw->nvm.version >> 12) & 0xf),
429 ((hw->nvm.version >> 4) & 0xff),
430 (hw->nvm.version & 0xf), hw->nvm.eetrack);
433 ret = i40e_aq_stop_lldp(hw, true, NULL);
434 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
435 PMD_INIT_LOG(INFO, "Failed to stop lldp");
438 i40e_clear_pxe_mode(hw);
440 /* Get hw capabilities */
441 ret = i40e_get_cap(hw);
442 if (ret != I40E_SUCCESS) {
443 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
444 goto err_get_capabilities;
447 /* Initialize parameters for PF */
448 ret = i40e_pf_parameter_init(dev);
450 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
451 goto err_parameter_init;
454 /* Initialize the queue management */
455 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
457 PMD_INIT_LOG(ERR, "Failed to init queue pool");
458 goto err_qp_pool_init;
460 ret = i40e_res_pool_init(&pf->msix_pool, 1,
461 hw->func_caps.num_msix_vectors - 1);
463 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
464 goto err_msix_pool_init;
467 /* Initialize lan hmc */
468 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
469 hw->func_caps.num_rx_qp, 0, 0);
470 if (ret != I40E_SUCCESS) {
471 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
472 goto err_init_lan_hmc;
475 /* Configure lan hmc */
476 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
477 if (ret != I40E_SUCCESS) {
478 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
479 goto err_configure_lan_hmc;
482 /* Get and check the mac address */
483 i40e_get_mac_addr(hw, hw->mac.addr);
484 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
485 PMD_INIT_LOG(ERR, "mac address is not valid");
487 goto err_get_mac_addr;
489 /* Copy the permanent MAC address */
490 ether_addr_copy((struct ether_addr *) hw->mac.addr,
491 (struct ether_addr *) hw->mac.perm_addr);
493 /* Disable flow control */
494 hw->fc.requested_mode = I40E_FC_NONE;
495 i40e_set_fc(hw, &aq_fail, TRUE);
497 /* PF setup, which includes VSI setup */
498 ret = i40e_pf_setup(pf);
500 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
501 goto err_setup_pf_switch;
506 /* Disable double vlan by default */
507 i40e_vsi_config_double_vlan(vsi, FALSE);
509 if (!vsi->max_macaddrs)
510 len = ETHER_ADDR_LEN;
512 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
514 /* Should be after VSI initialized */
515 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
516 if (!dev->data->mac_addrs) {
517 PMD_INIT_LOG(ERR, "Failed to allocated memory "
518 "for storing mac address");
521 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
522 &dev->data->mac_addrs[0]);
524 /* initialize pf host driver to setup SRIOV resource if applicable */
525 i40e_pf_host_init(dev);
527 /* register callback func to eal lib */
528 rte_intr_callback_register(&(pci_dev->intr_handle),
529 i40e_dev_interrupt_handler, (void *)dev);
531 /* configure and enable device interrupt */
532 i40e_pf_config_irq0(hw);
533 i40e_pf_enable_irq0(hw);
535 /* enable uio intr after callback register */
536 rte_intr_enable(&(pci_dev->intr_handle));
541 i40e_vsi_release(pf->main_vsi);
543 i40e_fdir_teardown(pf);
545 err_configure_lan_hmc:
546 (void)i40e_shutdown_lan_hmc(hw);
548 i40e_res_pool_destroy(&pf->msix_pool);
550 i40e_res_pool_destroy(&pf->qp_pool);
553 err_get_capabilities:
554 (void)i40e_shutdown_adminq(hw);
560 i40e_dev_configure(struct rte_eth_dev *dev)
563 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
566 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
567 * RSS setting have different requirements.
568 * General PMD driver call sequence are NIC init, configure,
569 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
570 * will try to lookup the VSI that specific queue belongs to if VMDQ
571 * applicable. So, VMDQ setting has to be done before
572 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
573 * For RSS setting, it will try to calculate actual configured RX queue
574 * number, which will be available after rx_queue_setup(). dev_start()
575 * function is good to place RSS setup.
577 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
578 ret = i40e_vmdq_setup(dev);
583 return i40e_dev_init_vlan(dev);
587 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
589 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
590 uint16_t msix_vect = vsi->msix_intr;
593 for (i = 0; i < vsi->nb_qps; i++) {
594 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
595 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
599 if (vsi->type != I40E_VSI_SRIOV) {
600 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
601 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
605 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
606 vsi->user_param + (msix_vect - 1);
608 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
610 I40E_WRITE_FLUSH(hw);
613 static inline uint16_t
614 i40e_calc_itr_interval(int16_t interval)
616 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
617 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
619 /* Convert to hardware count, as writing each 1 represents 2 us */
624 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
627 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
628 uint16_t msix_vect = vsi->msix_intr;
631 for (i = 0; i < vsi->nb_qps; i++)
632 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
634 /* Bind all RX queues to allocated MSIX interrupt */
635 for (i = 0; i < vsi->nb_qps; i++) {
636 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
637 I40E_QINT_RQCTL_ITR_INDX_MASK |
638 ((vsi->base_queue + i + 1) <<
639 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
640 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
641 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
643 if (i == vsi->nb_qps - 1)
644 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
645 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
648 /* Write first RX queue to Link list register as the head element */
649 if (vsi->type != I40E_VSI_SRIOV) {
651 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
653 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
655 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
656 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
658 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
659 msix_vect - 1), interval);
661 #ifndef I40E_GLINT_CTL
662 #define I40E_GLINT_CTL 0x0003F800
663 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
665 /* Disable auto-mask on enabling of all none-zero interrupt */
666 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
667 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
671 /* num_msix_vectors_vf needs to minus irq0 */
672 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
673 vsi->user_param + (msix_vect - 1);
675 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
676 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
677 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
680 I40E_WRITE_FLUSH(hw);
684 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
686 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
687 uint16_t interval = i40e_calc_itr_interval(\
688 RTE_LIBRTE_I40E_ITR_INTERVAL);
690 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
691 I40E_PFINT_DYN_CTLN_INTENA_MASK |
692 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
693 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
694 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
698 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
700 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
702 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
705 static inline uint8_t
706 i40e_parse_link_speed(uint16_t eth_link_speed)
708 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
710 switch (eth_link_speed) {
711 case ETH_LINK_SPEED_40G:
712 link_speed = I40E_LINK_SPEED_40GB;
714 case ETH_LINK_SPEED_20G:
715 link_speed = I40E_LINK_SPEED_20GB;
717 case ETH_LINK_SPEED_10G:
718 link_speed = I40E_LINK_SPEED_10GB;
720 case ETH_LINK_SPEED_1000:
721 link_speed = I40E_LINK_SPEED_1GB;
723 case ETH_LINK_SPEED_100:
724 link_speed = I40E_LINK_SPEED_100MB;
732 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
734 enum i40e_status_code status;
735 struct i40e_aq_get_phy_abilities_resp phy_ab;
736 struct i40e_aq_set_phy_config phy_conf;
737 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
738 I40E_AQ_PHY_FLAG_PAUSE_RX |
739 I40E_AQ_PHY_FLAG_LOW_POWER;
740 const uint8_t advt = I40E_LINK_SPEED_40GB |
741 I40E_LINK_SPEED_10GB |
742 I40E_LINK_SPEED_1GB |
743 I40E_LINK_SPEED_100MB;
746 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
751 memset(&phy_conf, 0, sizeof(phy_conf));
753 /* bits 0-2 use the values from get_phy_abilities_resp */
755 abilities |= phy_ab.abilities & mask;
757 /* update ablities and speed */
758 if (abilities & I40E_AQ_PHY_AN_ENABLED)
759 phy_conf.link_speed = advt;
761 phy_conf.link_speed = force_speed;
763 phy_conf.abilities = abilities;
765 /* use get_phy_abilities_resp value for the rest */
766 phy_conf.phy_type = phy_ab.phy_type;
767 phy_conf.eee_capability = phy_ab.eee_capability;
768 phy_conf.eeer = phy_ab.eeer_val;
769 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
771 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
772 phy_ab.abilities, phy_ab.link_speed);
773 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
774 phy_conf.abilities, phy_conf.link_speed);
776 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
784 i40e_apply_link_speed(struct rte_eth_dev *dev)
787 uint8_t abilities = 0;
788 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
789 struct rte_eth_conf *conf = &dev->data->dev_conf;
791 speed = i40e_parse_link_speed(conf->link_speed);
792 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
793 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
794 abilities |= I40E_AQ_PHY_AN_ENABLED;
796 abilities |= I40E_AQ_PHY_LINK_ENABLED;
798 return i40e_phy_conf_link(hw, abilities, speed);
802 i40e_dev_start(struct rte_eth_dev *dev)
804 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
806 struct i40e_vsi *main_vsi = pf->main_vsi;
809 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
810 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
811 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
812 dev->data->dev_conf.link_duplex,
818 ret = i40e_dev_rxtx_init(pf);
819 if (ret != I40E_SUCCESS) {
820 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
824 /* Map queues with MSIX interrupt */
825 i40e_vsi_queues_bind_intr(main_vsi);
826 i40e_vsi_enable_queues_intr(main_vsi);
828 /* Map VMDQ VSI queues with MSIX interrupt */
829 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
830 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
831 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
834 ret = i40e_fdir_configure(dev);
836 PMD_DRV_LOG(ERR, "failed to configure fdir.");
840 /* enable FDIR MSIX interrupt */
841 if (pf->flags & I40E_FLAG_FDIR) {
842 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
843 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
846 /* Enable all queues which have been configured */
847 ret = i40e_dev_switch_queues(pf, TRUE);
848 if (ret != I40E_SUCCESS) {
849 PMD_DRV_LOG(ERR, "Failed to enable VSI");
853 /* Enable receiving broadcast packets */
854 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
855 if (ret != I40E_SUCCESS)
856 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
858 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
859 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
861 if (ret != I40E_SUCCESS)
862 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
865 /* Apply link configure */
866 ret = i40e_apply_link_speed(dev);
867 if (I40E_SUCCESS != ret) {
868 PMD_DRV_LOG(ERR, "Fail to apply link setting");
875 i40e_dev_switch_queues(pf, FALSE);
876 i40e_dev_clear_queues(dev);
882 i40e_dev_stop(struct rte_eth_dev *dev)
884 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
885 struct i40e_vsi *main_vsi = pf->main_vsi;
888 /* Disable all queues */
889 i40e_dev_switch_queues(pf, FALSE);
891 /* un-map queues with interrupt registers */
892 i40e_vsi_disable_queues_intr(main_vsi);
893 i40e_vsi_queues_unbind_intr(main_vsi);
895 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
896 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
897 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
900 if (pf->flags & I40E_FLAG_FDIR) {
901 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
902 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
904 /* Clear all queues and release memory */
905 i40e_dev_clear_queues(dev);
908 i40e_dev_set_link_down(dev);
913 i40e_dev_close(struct rte_eth_dev *dev)
915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
919 PMD_INIT_FUNC_TRACE();
923 /* Disable interrupt */
924 i40e_pf_disable_irq0(hw);
925 rte_intr_disable(&(dev->pci_dev->intr_handle));
927 /* shutdown and destroy the HMC */
928 i40e_shutdown_lan_hmc(hw);
930 /* release all the existing VSIs and VEBs */
931 i40e_fdir_teardown(pf);
932 i40e_vsi_release(pf->main_vsi);
934 /* shutdown the adminq */
935 i40e_aq_queue_shutdown(hw, true);
936 i40e_shutdown_adminq(hw);
938 i40e_res_pool_destroy(&pf->qp_pool);
939 i40e_res_pool_destroy(&pf->msix_pool);
941 /* force a PF reset to clean anything leftover */
942 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
943 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
944 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
945 I40E_WRITE_FLUSH(hw);
949 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
952 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
953 struct i40e_vsi *vsi = pf->main_vsi;
956 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
958 if (status != I40E_SUCCESS)
959 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
961 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
963 if (status != I40E_SUCCESS)
964 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
969 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
971 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
972 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 struct i40e_vsi *vsi = pf->main_vsi;
976 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
978 if (status != I40E_SUCCESS)
979 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
981 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
983 if (status != I40E_SUCCESS)
984 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
988 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
990 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
991 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
992 struct i40e_vsi *vsi = pf->main_vsi;
995 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
996 if (ret != I40E_SUCCESS)
997 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1001 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005 struct i40e_vsi *vsi = pf->main_vsi;
1008 if (dev->data->promiscuous == 1)
1009 return; /* must remain in all_multicast mode */
1011 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1012 vsi->seid, FALSE, NULL);
1013 if (ret != I40E_SUCCESS)
1014 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1018 * Set device link up.
1021 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1023 /* re-apply link speed setting */
1024 return i40e_apply_link_speed(dev);
1028 * Set device link down.
1031 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1033 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1034 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1035 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 return i40e_phy_conf_link(hw, abilities, speed);
1041 i40e_dev_link_update(struct rte_eth_dev *dev,
1042 __rte_unused int wait_to_complete)
1044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045 struct i40e_link_status link_status;
1046 struct rte_eth_link link, old;
1049 memset(&link, 0, sizeof(link));
1050 memset(&old, 0, sizeof(old));
1051 memset(&link_status, 0, sizeof(link_status));
1052 rte_i40e_dev_atomic_read_link_status(dev, &old);
1054 /* Get link status information from hardware */
1055 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1056 if (status != I40E_SUCCESS) {
1057 link.link_speed = ETH_LINK_SPEED_100;
1058 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1059 PMD_DRV_LOG(ERR, "Failed to get link info");
1063 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1065 if (!link.link_status)
1068 /* i40e uses full duplex only */
1069 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1071 /* Parse the link status */
1072 switch (link_status.link_speed) {
1073 case I40E_LINK_SPEED_100MB:
1074 link.link_speed = ETH_LINK_SPEED_100;
1076 case I40E_LINK_SPEED_1GB:
1077 link.link_speed = ETH_LINK_SPEED_1000;
1079 case I40E_LINK_SPEED_10GB:
1080 link.link_speed = ETH_LINK_SPEED_10G;
1082 case I40E_LINK_SPEED_20GB:
1083 link.link_speed = ETH_LINK_SPEED_20G;
1085 case I40E_LINK_SPEED_40GB:
1086 link.link_speed = ETH_LINK_SPEED_40G;
1089 link.link_speed = ETH_LINK_SPEED_100;
1094 rte_i40e_dev_atomic_write_link_status(dev, &link);
1095 if (link.link_status == old.link_status)
1101 /* Get all the statistics of a VSI */
1103 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1105 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1106 struct i40e_eth_stats *nes = &vsi->eth_stats;
1107 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1108 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1110 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1111 vsi->offset_loaded, &oes->rx_bytes,
1113 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1114 vsi->offset_loaded, &oes->rx_unicast,
1116 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1117 vsi->offset_loaded, &oes->rx_multicast,
1118 &nes->rx_multicast);
1119 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1120 vsi->offset_loaded, &oes->rx_broadcast,
1121 &nes->rx_broadcast);
1122 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1123 &oes->rx_discards, &nes->rx_discards);
1124 /* GLV_REPC not supported */
1125 /* GLV_RMPC not supported */
1126 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1127 &oes->rx_unknown_protocol,
1128 &nes->rx_unknown_protocol);
1129 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1130 vsi->offset_loaded, &oes->tx_bytes,
1132 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1133 vsi->offset_loaded, &oes->tx_unicast,
1135 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1136 vsi->offset_loaded, &oes->tx_multicast,
1137 &nes->tx_multicast);
1138 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1139 vsi->offset_loaded, &oes->tx_broadcast,
1140 &nes->tx_broadcast);
1141 /* GLV_TDPC not supported */
1142 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1143 &oes->tx_errors, &nes->tx_errors);
1144 vsi->offset_loaded = true;
1146 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1148 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1149 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1150 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1151 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1152 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1153 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1154 nes->rx_unknown_protocol);
1155 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1156 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1157 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1158 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1159 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1160 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1161 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1165 /* Get all statistics of a port */
1167 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1170 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1171 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1172 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1173 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1175 /* Get statistics of struct i40e_eth_stats */
1176 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1177 I40E_GLPRT_GORCL(hw->port),
1178 pf->offset_loaded, &os->eth.rx_bytes,
1180 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1181 I40E_GLPRT_UPRCL(hw->port),
1182 pf->offset_loaded, &os->eth.rx_unicast,
1183 &ns->eth.rx_unicast);
1184 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1185 I40E_GLPRT_MPRCL(hw->port),
1186 pf->offset_loaded, &os->eth.rx_multicast,
1187 &ns->eth.rx_multicast);
1188 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1189 I40E_GLPRT_BPRCL(hw->port),
1190 pf->offset_loaded, &os->eth.rx_broadcast,
1191 &ns->eth.rx_broadcast);
1192 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1193 pf->offset_loaded, &os->eth.rx_discards,
1194 &ns->eth.rx_discards);
1195 /* GLPRT_REPC not supported */
1196 /* GLPRT_RMPC not supported */
1197 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1199 &os->eth.rx_unknown_protocol,
1200 &ns->eth.rx_unknown_protocol);
1201 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1202 I40E_GLPRT_GOTCL(hw->port),
1203 pf->offset_loaded, &os->eth.tx_bytes,
1205 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1206 I40E_GLPRT_UPTCL(hw->port),
1207 pf->offset_loaded, &os->eth.tx_unicast,
1208 &ns->eth.tx_unicast);
1209 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1210 I40E_GLPRT_MPTCL(hw->port),
1211 pf->offset_loaded, &os->eth.tx_multicast,
1212 &ns->eth.tx_multicast);
1213 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1214 I40E_GLPRT_BPTCL(hw->port),
1215 pf->offset_loaded, &os->eth.tx_broadcast,
1216 &ns->eth.tx_broadcast);
1217 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1218 pf->offset_loaded, &os->eth.tx_discards,
1219 &ns->eth.tx_discards);
1220 /* GLPRT_TEPC not supported */
1222 /* additional port specific stats */
1223 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1224 pf->offset_loaded, &os->tx_dropped_link_down,
1225 &ns->tx_dropped_link_down);
1226 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1227 pf->offset_loaded, &os->crc_errors,
1229 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1230 pf->offset_loaded, &os->illegal_bytes,
1231 &ns->illegal_bytes);
1232 /* GLPRT_ERRBC not supported */
1233 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1234 pf->offset_loaded, &os->mac_local_faults,
1235 &ns->mac_local_faults);
1236 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1237 pf->offset_loaded, &os->mac_remote_faults,
1238 &ns->mac_remote_faults);
1239 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1240 pf->offset_loaded, &os->rx_length_errors,
1241 &ns->rx_length_errors);
1242 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1243 pf->offset_loaded, &os->link_xon_rx,
1245 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1246 pf->offset_loaded, &os->link_xoff_rx,
1248 for (i = 0; i < 8; i++) {
1249 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1251 &os->priority_xon_rx[i],
1252 &ns->priority_xon_rx[i]);
1253 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1255 &os->priority_xoff_rx[i],
1256 &ns->priority_xoff_rx[i]);
1258 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1259 pf->offset_loaded, &os->link_xon_tx,
1261 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1262 pf->offset_loaded, &os->link_xoff_tx,
1264 for (i = 0; i < 8; i++) {
1265 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1267 &os->priority_xon_tx[i],
1268 &ns->priority_xon_tx[i]);
1269 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1271 &os->priority_xoff_tx[i],
1272 &ns->priority_xoff_tx[i]);
1273 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1275 &os->priority_xon_2_xoff[i],
1276 &ns->priority_xon_2_xoff[i]);
1278 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1279 I40E_GLPRT_PRC64L(hw->port),
1280 pf->offset_loaded, &os->rx_size_64,
1282 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1283 I40E_GLPRT_PRC127L(hw->port),
1284 pf->offset_loaded, &os->rx_size_127,
1286 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1287 I40E_GLPRT_PRC255L(hw->port),
1288 pf->offset_loaded, &os->rx_size_255,
1290 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1291 I40E_GLPRT_PRC511L(hw->port),
1292 pf->offset_loaded, &os->rx_size_511,
1294 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1295 I40E_GLPRT_PRC1023L(hw->port),
1296 pf->offset_loaded, &os->rx_size_1023,
1298 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1299 I40E_GLPRT_PRC1522L(hw->port),
1300 pf->offset_loaded, &os->rx_size_1522,
1302 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1303 I40E_GLPRT_PRC9522L(hw->port),
1304 pf->offset_loaded, &os->rx_size_big,
1306 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1307 pf->offset_loaded, &os->rx_undersize,
1309 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1310 pf->offset_loaded, &os->rx_fragments,
1312 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1313 pf->offset_loaded, &os->rx_oversize,
1315 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1316 pf->offset_loaded, &os->rx_jabber,
1318 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1319 I40E_GLPRT_PTC64L(hw->port),
1320 pf->offset_loaded, &os->tx_size_64,
1322 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1323 I40E_GLPRT_PTC127L(hw->port),
1324 pf->offset_loaded, &os->tx_size_127,
1326 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1327 I40E_GLPRT_PTC255L(hw->port),
1328 pf->offset_loaded, &os->tx_size_255,
1330 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1331 I40E_GLPRT_PTC511L(hw->port),
1332 pf->offset_loaded, &os->tx_size_511,
1334 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1335 I40E_GLPRT_PTC1023L(hw->port),
1336 pf->offset_loaded, &os->tx_size_1023,
1338 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1339 I40E_GLPRT_PTC1522L(hw->port),
1340 pf->offset_loaded, &os->tx_size_1522,
1342 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1343 I40E_GLPRT_PTC9522L(hw->port),
1344 pf->offset_loaded, &os->tx_size_big,
1346 /* GLPRT_MSPDC not supported */
1347 /* GLPRT_XEC not supported */
1349 pf->offset_loaded = true;
1352 i40e_update_vsi_stats(pf->main_vsi);
1354 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1355 ns->eth.rx_broadcast;
1356 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1357 ns->eth.tx_broadcast;
1358 stats->ibytes = ns->eth.rx_bytes;
1359 stats->obytes = ns->eth.tx_bytes;
1360 stats->oerrors = ns->eth.tx_errors;
1361 stats->imcasts = ns->eth.rx_multicast;
1364 stats->ibadcrc = ns->crc_errors;
1365 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1366 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1367 stats->imissed = ns->eth.rx_discards;
1368 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1370 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1371 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1372 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1373 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1374 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1375 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1376 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1377 ns->eth.rx_unknown_protocol);
1378 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1379 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1380 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1381 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1382 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1383 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1385 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1386 ns->tx_dropped_link_down);
1387 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1388 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1390 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1391 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1392 ns->mac_local_faults);
1393 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1394 ns->mac_remote_faults);
1395 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1396 ns->rx_length_errors);
1397 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1398 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1399 for (i = 0; i < 8; i++) {
1400 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1401 i, ns->priority_xon_rx[i]);
1402 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1403 i, ns->priority_xoff_rx[i]);
1405 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1406 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1407 for (i = 0; i < 8; i++) {
1408 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1409 i, ns->priority_xon_tx[i]);
1410 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1411 i, ns->priority_xoff_tx[i]);
1412 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1413 i, ns->priority_xon_2_xoff[i]);
1415 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1416 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1417 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1418 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1419 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1420 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1421 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1422 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1423 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1424 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1425 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1426 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1427 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1428 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1429 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1430 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1431 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1432 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1433 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1434 ns->mac_short_packet_dropped);
1435 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1436 ns->checksum_error);
1437 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1440 /* Reset the statistics */
1442 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1446 /* It results in reloading the start point of each counter */
1447 pf->offset_loaded = false;
1451 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1452 __rte_unused uint16_t queue_id,
1453 __rte_unused uint8_t stat_idx,
1454 __rte_unused uint8_t is_rx)
1456 PMD_INIT_FUNC_TRACE();
1462 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1464 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1465 struct i40e_vsi *vsi = pf->main_vsi;
1467 dev_info->max_rx_queues = vsi->nb_qps;
1468 dev_info->max_tx_queues = vsi->nb_qps;
1469 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1470 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1471 dev_info->max_mac_addrs = vsi->max_macaddrs;
1472 dev_info->max_vfs = dev->pci_dev->max_vfs;
1473 dev_info->rx_offload_capa =
1474 DEV_RX_OFFLOAD_VLAN_STRIP |
1475 DEV_RX_OFFLOAD_IPV4_CKSUM |
1476 DEV_RX_OFFLOAD_UDP_CKSUM |
1477 DEV_RX_OFFLOAD_TCP_CKSUM;
1478 dev_info->tx_offload_capa =
1479 DEV_TX_OFFLOAD_VLAN_INSERT |
1480 DEV_TX_OFFLOAD_IPV4_CKSUM |
1481 DEV_TX_OFFLOAD_UDP_CKSUM |
1482 DEV_TX_OFFLOAD_TCP_CKSUM |
1483 DEV_TX_OFFLOAD_SCTP_CKSUM;
1484 dev_info->reta_size = pf->hash_lut_size;
1486 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1488 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1489 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1490 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1492 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1496 dev_info->default_txconf = (struct rte_eth_txconf) {
1498 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1499 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1500 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1502 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1503 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1504 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1505 ETH_TXQ_FLAGS_NOOFFLOADS,
1508 if (pf->flags | I40E_FLAG_VMDQ) {
1509 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1510 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1511 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1512 pf->max_nb_vmdq_vsi;
1513 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1514 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1515 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1520 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1523 struct i40e_vsi *vsi = pf->main_vsi;
1524 PMD_INIT_FUNC_TRACE();
1527 return i40e_vsi_add_vlan(vsi, vlan_id);
1529 return i40e_vsi_delete_vlan(vsi, vlan_id);
1533 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1534 __rte_unused uint16_t tpid)
1536 PMD_INIT_FUNC_TRACE();
1540 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1542 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1543 struct i40e_vsi *vsi = pf->main_vsi;
1545 if (mask & ETH_VLAN_STRIP_MASK) {
1546 /* Enable or disable VLAN stripping */
1547 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1548 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1550 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1553 if (mask & ETH_VLAN_EXTEND_MASK) {
1554 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1555 i40e_vsi_config_double_vlan(vsi, TRUE);
1557 i40e_vsi_config_double_vlan(vsi, FALSE);
1562 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1563 __rte_unused uint16_t queue,
1564 __rte_unused int on)
1566 PMD_INIT_FUNC_TRACE();
1570 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1573 struct i40e_vsi *vsi = pf->main_vsi;
1574 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1575 struct i40e_vsi_vlan_pvid_info info;
1577 memset(&info, 0, sizeof(info));
1580 info.config.pvid = pvid;
1582 info.config.reject.tagged =
1583 data->dev_conf.txmode.hw_vlan_reject_tagged;
1584 info.config.reject.untagged =
1585 data->dev_conf.txmode.hw_vlan_reject_untagged;
1588 return i40e_vsi_vlan_pvid_set(vsi, &info);
1592 i40e_dev_led_on(struct rte_eth_dev *dev)
1594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595 uint32_t mode = i40e_led_get(hw);
1598 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1604 i40e_dev_led_off(struct rte_eth_dev *dev)
1606 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607 uint32_t mode = i40e_led_get(hw);
1610 i40e_led_set(hw, 0, false);
1616 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1617 __rte_unused struct rte_eth_fc_conf *fc_conf)
1619 PMD_INIT_FUNC_TRACE();
1625 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1626 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1628 PMD_INIT_FUNC_TRACE();
1633 /* Add a MAC address, and update filters */
1635 i40e_macaddr_add(struct rte_eth_dev *dev,
1636 struct ether_addr *mac_addr,
1637 __rte_unused uint32_t index,
1640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1641 struct i40e_mac_filter_info mac_filter;
1642 struct i40e_vsi *vsi;
1645 /* If VMDQ not enabled or configured, return */
1646 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1647 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1648 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1653 if (pool > pf->nb_cfg_vmdq_vsi) {
1654 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1655 pool, pf->nb_cfg_vmdq_vsi);
1659 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1660 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1665 vsi = pf->vmdq[pool - 1].vsi;
1667 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1668 if (ret != I40E_SUCCESS) {
1669 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1674 /* Remove a MAC address, and update filters */
1676 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1678 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1679 struct i40e_vsi *vsi;
1680 struct rte_eth_dev_data *data = dev->data;
1681 struct ether_addr *macaddr;
1686 macaddr = &(data->mac_addrs[index]);
1688 pool_sel = dev->data->mac_pool_sel[index];
1690 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1691 if (pool_sel & (1ULL << i)) {
1695 /* No VMDQ pool enabled or configured */
1696 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1697 (i > pf->nb_cfg_vmdq_vsi)) {
1698 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1702 vsi = pf->vmdq[i - 1].vsi;
1704 ret = i40e_vsi_delete_mac(vsi, macaddr);
1707 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1714 /* Set perfect match or hash match of MAC and VLAN for a VF */
1716 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1717 struct rte_eth_mac_filter *filter,
1721 struct i40e_mac_filter_info mac_filter;
1722 struct ether_addr old_mac;
1723 struct ether_addr *new_mac;
1724 struct i40e_pf_vf *vf = NULL;
1729 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1732 hw = I40E_PF_TO_HW(pf);
1734 if (filter == NULL) {
1735 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1739 new_mac = &filter->mac_addr;
1741 if (is_zero_ether_addr(new_mac)) {
1742 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1746 vf_id = filter->dst_id;
1748 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1749 PMD_DRV_LOG(ERR, "Invalid argument.");
1752 vf = &pf->vfs[vf_id];
1754 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1755 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1760 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1761 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1763 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1766 mac_filter.filter_type = filter->filter_type;
1767 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1768 if (ret != I40E_SUCCESS) {
1769 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1772 ether_addr_copy(new_mac, &pf->dev_addr);
1774 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1776 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1777 if (ret != I40E_SUCCESS) {
1778 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1782 /* Clear device address as it has been removed */
1783 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1784 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1790 /* MAC filter handle */
1792 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1795 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1796 struct rte_eth_mac_filter *filter;
1797 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1798 int ret = I40E_NOT_SUPPORTED;
1800 filter = (struct rte_eth_mac_filter *)(arg);
1802 switch (filter_op) {
1803 case RTE_ETH_FILTER_NOP:
1806 case RTE_ETH_FILTER_ADD:
1807 i40e_pf_disable_irq0(hw);
1809 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1810 i40e_pf_enable_irq0(hw);
1812 case RTE_ETH_FILTER_DELETE:
1813 i40e_pf_disable_irq0(hw);
1815 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1816 i40e_pf_enable_irq0(hw);
1819 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1820 ret = I40E_ERR_PARAM;
1828 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1829 struct rte_eth_rss_reta_entry64 *reta_conf,
1832 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835 uint16_t i, j, lut_size = pf->hash_lut_size;
1836 uint16_t idx, shift;
1839 if (reta_size != lut_size ||
1840 reta_size > ETH_RSS_RETA_SIZE_512) {
1841 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1842 "(%d) doesn't match the number hardware can supported "
1843 "(%d)\n", reta_size, lut_size);
1847 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1848 idx = i / RTE_RETA_GROUP_SIZE;
1849 shift = i % RTE_RETA_GROUP_SIZE;
1850 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1854 if (mask == I40E_4_BIT_MASK)
1857 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1858 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1859 if (mask & (0x1 << j))
1860 lut |= reta_conf[idx].reta[shift + j] <<
1863 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1865 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1872 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1873 struct rte_eth_rss_reta_entry64 *reta_conf,
1876 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1877 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879 uint16_t i, j, lut_size = pf->hash_lut_size;
1880 uint16_t idx, shift;
1883 if (reta_size != lut_size ||
1884 reta_size > ETH_RSS_RETA_SIZE_512) {
1885 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1886 "(%d) doesn't match the number hardware can supported "
1887 "(%d)\n", reta_size, lut_size);
1891 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1892 idx = i / RTE_RETA_GROUP_SIZE;
1893 shift = i % RTE_RETA_GROUP_SIZE;
1894 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1899 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1900 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1901 if (mask & (0x1 << j))
1902 reta_conf[idx].reta[shift] = ((lut >>
1903 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1911 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1912 * @hw: pointer to the HW structure
1913 * @mem: pointer to mem struct to fill out
1914 * @size: size of memory requested
1915 * @alignment: what to align the allocation to
1917 enum i40e_status_code
1918 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1919 struct i40e_dma_mem *mem,
1923 static uint64_t id = 0;
1924 const struct rte_memzone *mz = NULL;
1925 char z_name[RTE_MEMZONE_NAMESIZE];
1928 return I40E_ERR_PARAM;
1931 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1932 #ifdef RTE_LIBRTE_XEN_DOM0
1933 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1936 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1939 return I40E_ERR_NO_MEMORY;
1944 #ifdef RTE_LIBRTE_XEN_DOM0
1945 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1947 mem->pa = mz->phys_addr;
1950 return I40E_SUCCESS;
1954 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1955 * @hw: pointer to the HW structure
1956 * @mem: ptr to mem struct to free
1958 enum i40e_status_code
1959 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1960 struct i40e_dma_mem *mem)
1962 if (!mem || !mem->va)
1963 return I40E_ERR_PARAM;
1968 return I40E_SUCCESS;
1972 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1973 * @hw: pointer to the HW structure
1974 * @mem: pointer to mem struct to fill out
1975 * @size: size of memory requested
1977 enum i40e_status_code
1978 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1979 struct i40e_virt_mem *mem,
1983 return I40E_ERR_PARAM;
1986 mem->va = rte_zmalloc("i40e", size, 0);
1989 return I40E_SUCCESS;
1991 return I40E_ERR_NO_MEMORY;
1995 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1996 * @hw: pointer to the HW structure
1997 * @mem: pointer to mem struct to free
1999 enum i40e_status_code
2000 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2001 struct i40e_virt_mem *mem)
2004 return I40E_ERR_PARAM;
2009 return I40E_SUCCESS;
2013 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2015 rte_spinlock_init(&sp->spinlock);
2019 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2021 rte_spinlock_lock(&sp->spinlock);
2025 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2027 rte_spinlock_unlock(&sp->spinlock);
2031 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2037 * Get the hardware capabilities, which will be parsed
2038 * and saved into struct i40e_hw.
2041 i40e_get_cap(struct i40e_hw *hw)
2043 struct i40e_aqc_list_capabilities_element_resp *buf;
2044 uint16_t len, size = 0;
2047 /* Calculate a huge enough buff for saving response data temporarily */
2048 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2049 I40E_MAX_CAP_ELE_NUM;
2050 buf = rte_zmalloc("i40e", len, 0);
2052 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2053 return I40E_ERR_NO_MEMORY;
2056 /* Get, parse the capabilities and save it to hw */
2057 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2058 i40e_aqc_opc_list_func_capabilities, NULL);
2059 if (ret != I40E_SUCCESS)
2060 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2062 /* Free the temporary buffer after being used */
2069 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2072 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2073 uint16_t sum_queues = 0, sum_vsis, left_queues;
2075 /* First check if FW support SRIOV */
2076 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2077 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2081 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2082 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2083 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2084 /* Allocate queues for pf */
2085 if (hw->func_caps.rss) {
2086 pf->flags |= I40E_FLAG_RSS;
2087 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2088 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2089 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2092 sum_queues = pf->lan_nb_qps;
2093 /* Default VSI is not counted in */
2095 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2097 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2098 pf->flags |= I40E_FLAG_SRIOV;
2099 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2100 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2101 PMD_INIT_LOG(ERR, "Config VF number %u, "
2102 "max supported %u.",
2103 dev->pci_dev->max_vfs,
2104 hw->func_caps.num_vfs);
2107 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2108 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2109 "max support %u queues.",
2110 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2113 pf->vf_num = dev->pci_dev->max_vfs;
2114 sum_queues += pf->vf_nb_qps * pf->vf_num;
2115 sum_vsis += pf->vf_num;
2116 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2117 pf->vf_num, pf->vf_nb_qps);
2121 if (hw->func_caps.vmdq) {
2122 pf->flags |= I40E_FLAG_VMDQ;
2123 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2124 pf->max_nb_vmdq_vsi = 1;
2126 * If VMDQ available, assume a single VSI can be created. Will adjust
2129 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2130 sum_vsis += pf->max_nb_vmdq_vsi;
2132 pf->vmdq_nb_qps = 0;
2133 pf->max_nb_vmdq_vsi = 0;
2135 pf->nb_cfg_vmdq_vsi = 0;
2137 if (hw->func_caps.fd) {
2138 pf->flags |= I40E_FLAG_FDIR;
2139 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2141 * Each flow director consumes one VSI and one queue,
2142 * but can't calculate out predictably here.
2146 if (sum_vsis > pf->max_num_vsi ||
2147 sum_queues > hw->func_caps.num_rx_qp) {
2148 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2149 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2150 pf->max_num_vsi, sum_vsis);
2151 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2152 hw->func_caps.num_rx_qp, sum_queues);
2156 /* Adjust VMDQ setting to support as many VMs as possible */
2157 if (pf->flags & I40E_FLAG_VMDQ) {
2158 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2160 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2161 pf->max_num_vsi - sum_vsis);
2163 /* Limit the max VMDQ number that rte_ether that can support */
2164 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2167 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2168 pf->max_nb_vmdq_vsi);
2169 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2172 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2174 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2175 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2176 sum_vsis, hw->func_caps.num_msix_vectors);
2179 return I40E_SUCCESS;
2183 i40e_pf_get_switch_config(struct i40e_pf *pf)
2185 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2186 struct i40e_aqc_get_switch_config_resp *switch_config;
2187 struct i40e_aqc_switch_config_element_resp *element;
2188 uint16_t start_seid = 0, num_reported;
2191 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2192 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2193 if (!switch_config) {
2194 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2198 /* Get the switch configurations */
2199 ret = i40e_aq_get_switch_config(hw, switch_config,
2200 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2201 if (ret != I40E_SUCCESS) {
2202 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2205 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2206 if (num_reported != 1) { /* The number should be 1 */
2207 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2211 /* Parse the switch configuration elements */
2212 element = &(switch_config->element[0]);
2213 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2214 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2215 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2217 PMD_DRV_LOG(INFO, "Unknown element type");
2220 rte_free(switch_config);
2226 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2229 struct pool_entry *entry;
2231 if (pool == NULL || num == 0)
2234 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2235 if (entry == NULL) {
2236 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2240 /* queue heap initialize */
2241 pool->num_free = num;
2242 pool->num_alloc = 0;
2244 LIST_INIT(&pool->alloc_list);
2245 LIST_INIT(&pool->free_list);
2247 /* Initialize element */
2251 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2256 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2258 struct pool_entry *entry;
2263 LIST_FOREACH(entry, &pool->alloc_list, next) {
2264 LIST_REMOVE(entry, next);
2268 LIST_FOREACH(entry, &pool->free_list, next) {
2269 LIST_REMOVE(entry, next);
2274 pool->num_alloc = 0;
2276 LIST_INIT(&pool->alloc_list);
2277 LIST_INIT(&pool->free_list);
2281 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2284 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2285 uint32_t pool_offset;
2289 PMD_DRV_LOG(ERR, "Invalid parameter");
2293 pool_offset = base - pool->base;
2294 /* Lookup in alloc list */
2295 LIST_FOREACH(entry, &pool->alloc_list, next) {
2296 if (entry->base == pool_offset) {
2297 valid_entry = entry;
2298 LIST_REMOVE(entry, next);
2303 /* Not find, return */
2304 if (valid_entry == NULL) {
2305 PMD_DRV_LOG(ERR, "Failed to find entry");
2310 * Found it, move it to free list and try to merge.
2311 * In order to make merge easier, always sort it by qbase.
2312 * Find adjacent prev and last entries.
2315 LIST_FOREACH(entry, &pool->free_list, next) {
2316 if (entry->base > valid_entry->base) {
2324 /* Try to merge with next one*/
2326 /* Merge with next one */
2327 if (valid_entry->base + valid_entry->len == next->base) {
2328 next->base = valid_entry->base;
2329 next->len += valid_entry->len;
2330 rte_free(valid_entry);
2337 /* Merge with previous one */
2338 if (prev->base + prev->len == valid_entry->base) {
2339 prev->len += valid_entry->len;
2340 /* If it merge with next one, remove next node */
2342 LIST_REMOVE(valid_entry, next);
2343 rte_free(valid_entry);
2345 rte_free(valid_entry);
2351 /* Not find any entry to merge, insert */
2354 LIST_INSERT_AFTER(prev, valid_entry, next);
2355 else if (next != NULL)
2356 LIST_INSERT_BEFORE(next, valid_entry, next);
2357 else /* It's empty list, insert to head */
2358 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2361 pool->num_free += valid_entry->len;
2362 pool->num_alloc -= valid_entry->len;
2368 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2371 struct pool_entry *entry, *valid_entry;
2373 if (pool == NULL || num == 0) {
2374 PMD_DRV_LOG(ERR, "Invalid parameter");
2378 if (pool->num_free < num) {
2379 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2380 num, pool->num_free);
2385 /* Lookup in free list and find most fit one */
2386 LIST_FOREACH(entry, &pool->free_list, next) {
2387 if (entry->len >= num) {
2389 if (entry->len == num) {
2390 valid_entry = entry;
2393 if (valid_entry == NULL || valid_entry->len > entry->len)
2394 valid_entry = entry;
2398 /* Not find one to satisfy the request, return */
2399 if (valid_entry == NULL) {
2400 PMD_DRV_LOG(ERR, "No valid entry found");
2404 * The entry have equal queue number as requested,
2405 * remove it from alloc_list.
2407 if (valid_entry->len == num) {
2408 LIST_REMOVE(valid_entry, next);
2411 * The entry have more numbers than requested,
2412 * create a new entry for alloc_list and minus its
2413 * queue base and number in free_list.
2415 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2416 if (entry == NULL) {
2417 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2421 entry->base = valid_entry->base;
2423 valid_entry->base += num;
2424 valid_entry->len -= num;
2425 valid_entry = entry;
2428 /* Insert it into alloc list, not sorted */
2429 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2431 pool->num_free -= valid_entry->len;
2432 pool->num_alloc += valid_entry->len;
2434 return (valid_entry->base + pool->base);
2438 * bitmap_is_subset - Check whether src2 is subset of src1
2441 bitmap_is_subset(uint8_t src1, uint8_t src2)
2443 return !((src1 ^ src2) & src2);
2447 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2449 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2451 /* If DCB is not supported, only default TC is supported */
2452 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2453 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2457 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2458 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2459 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2463 return I40E_SUCCESS;
2467 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2468 struct i40e_vsi_vlan_pvid_info *info)
2471 struct i40e_vsi_context ctxt;
2472 uint8_t vlan_flags = 0;
2475 if (vsi == NULL || info == NULL) {
2476 PMD_DRV_LOG(ERR, "invalid parameters");
2477 return I40E_ERR_PARAM;
2481 vsi->info.pvid = info->config.pvid;
2483 * If insert pvid is enabled, only tagged pkts are
2484 * allowed to be sent out.
2486 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2487 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2490 if (info->config.reject.tagged == 0)
2491 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2493 if (info->config.reject.untagged == 0)
2494 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2496 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2497 I40E_AQ_VSI_PVLAN_MODE_MASK);
2498 vsi->info.port_vlan_flags |= vlan_flags;
2499 vsi->info.valid_sections =
2500 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2501 memset(&ctxt, 0, sizeof(ctxt));
2502 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2503 ctxt.seid = vsi->seid;
2505 hw = I40E_VSI_TO_HW(vsi);
2506 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2507 if (ret != I40E_SUCCESS)
2508 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2514 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2516 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2518 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2520 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2521 if (ret != I40E_SUCCESS)
2525 PMD_DRV_LOG(ERR, "seid not valid");
2529 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2530 tc_bw_data.tc_valid_bits = enabled_tcmap;
2531 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2532 tc_bw_data.tc_bw_credits[i] =
2533 (enabled_tcmap & (1 << i)) ? 1 : 0;
2535 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2536 if (ret != I40E_SUCCESS) {
2537 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2541 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2542 sizeof(vsi->info.qs_handle));
2543 return I40E_SUCCESS;
2547 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2548 struct i40e_aqc_vsi_properties_data *info,
2549 uint8_t enabled_tcmap)
2551 int ret, total_tc = 0, i;
2552 uint16_t qpnum_per_tc, bsf, qp_idx;
2554 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2555 if (ret != I40E_SUCCESS)
2558 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2559 if (enabled_tcmap & (1 << i))
2561 vsi->enabled_tc = enabled_tcmap;
2563 /* Number of queues per enabled TC */
2564 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2565 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2566 bsf = rte_bsf32(qpnum_per_tc);
2568 /* Adjust the queue number to actual queues that can be applied */
2569 vsi->nb_qps = qpnum_per_tc * total_tc;
2572 * Configure TC and queue mapping parameters, for enabled TC,
2573 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2574 * default queue will serve it.
2577 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2578 if (vsi->enabled_tc & (1 << i)) {
2579 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2580 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2581 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2582 qp_idx += qpnum_per_tc;
2584 info->tc_mapping[i] = 0;
2587 /* Associate queue number with VSI */
2588 if (vsi->type == I40E_VSI_SRIOV) {
2589 info->mapping_flags |=
2590 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2591 for (i = 0; i < vsi->nb_qps; i++)
2592 info->queue_mapping[i] =
2593 rte_cpu_to_le_16(vsi->base_queue + i);
2595 info->mapping_flags |=
2596 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2597 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2599 info->valid_sections =
2600 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2602 return I40E_SUCCESS;
2606 i40e_veb_release(struct i40e_veb *veb)
2608 struct i40e_vsi *vsi;
2611 if (veb == NULL || veb->associate_vsi == NULL)
2614 if (!TAILQ_EMPTY(&veb->head)) {
2615 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2619 vsi = veb->associate_vsi;
2620 hw = I40E_VSI_TO_HW(vsi);
2622 vsi->uplink_seid = veb->uplink_seid;
2623 i40e_aq_delete_element(hw, veb->seid, NULL);
2626 return I40E_SUCCESS;
2630 static struct i40e_veb *
2631 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2633 struct i40e_veb *veb;
2637 if (NULL == pf || vsi == NULL) {
2638 PMD_DRV_LOG(ERR, "veb setup failed, "
2639 "associated VSI shouldn't null");
2642 hw = I40E_PF_TO_HW(pf);
2644 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2646 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2650 veb->associate_vsi = vsi;
2651 TAILQ_INIT(&veb->head);
2652 veb->uplink_seid = vsi->uplink_seid;
2654 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2655 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2657 if (ret != I40E_SUCCESS) {
2658 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2659 hw->aq.asq_last_status);
2663 /* get statistics index */
2664 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2665 &veb->stats_idx, NULL, NULL, NULL);
2666 if (ret != I40E_SUCCESS) {
2667 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2668 hw->aq.asq_last_status);
2672 /* Get VEB bandwidth, to be implemented */
2673 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2674 vsi->uplink_seid = veb->seid;
2683 i40e_vsi_release(struct i40e_vsi *vsi)
2687 struct i40e_vsi_list *vsi_list;
2689 struct i40e_mac_filter *f;
2692 return I40E_SUCCESS;
2694 pf = I40E_VSI_TO_PF(vsi);
2695 hw = I40E_VSI_TO_HW(vsi);
2697 /* VSI has child to attach, release child first */
2699 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2700 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2702 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2704 i40e_veb_release(vsi->veb);
2707 /* Remove all macvlan filters of the VSI */
2708 i40e_vsi_remove_all_macvlan_filter(vsi);
2709 TAILQ_FOREACH(f, &vsi->mac_list, next)
2712 if (vsi->type != I40E_VSI_MAIN) {
2713 /* Remove vsi from parent's sibling list */
2714 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2715 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2716 return I40E_ERR_PARAM;
2718 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2719 &vsi->sib_vsi_list, list);
2721 /* Remove all switch element of the VSI */
2722 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2723 if (ret != I40E_SUCCESS)
2724 PMD_DRV_LOG(ERR, "Failed to delete element");
2726 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2728 if (vsi->type != I40E_VSI_SRIOV)
2729 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2732 return I40E_SUCCESS;
2736 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2738 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2739 struct i40e_aqc_remove_macvlan_element_data def_filter;
2740 struct i40e_mac_filter_info filter;
2743 if (vsi->type != I40E_VSI_MAIN)
2744 return I40E_ERR_CONFIG;
2745 memset(&def_filter, 0, sizeof(def_filter));
2746 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2748 def_filter.vlan_tag = 0;
2749 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2750 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2751 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2752 if (ret != I40E_SUCCESS) {
2753 struct i40e_mac_filter *f;
2754 struct ether_addr *mac;
2756 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2758 /* It needs to add the permanent mac into mac list */
2759 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2761 PMD_DRV_LOG(ERR, "failed to allocate memory");
2762 return I40E_ERR_NO_MEMORY;
2764 mac = &f->mac_info.mac_addr;
2765 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2767 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2768 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2773 (void)rte_memcpy(&filter.mac_addr,
2774 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2775 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2776 return i40e_vsi_add_mac(vsi, &filter);
2780 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2782 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2783 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2784 struct i40e_hw *hw = &vsi->adapter->hw;
2788 memset(&bw_config, 0, sizeof(bw_config));
2789 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2790 if (ret != I40E_SUCCESS) {
2791 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2792 hw->aq.asq_last_status);
2796 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2797 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2798 &ets_sla_config, NULL);
2799 if (ret != I40E_SUCCESS) {
2800 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2801 "configuration %u", hw->aq.asq_last_status);
2805 /* Not store the info yet, just print out */
2806 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2807 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2808 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2809 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2810 ets_sla_config.share_credits[i]);
2811 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2812 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2813 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2814 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2823 i40e_vsi_setup(struct i40e_pf *pf,
2824 enum i40e_vsi_type type,
2825 struct i40e_vsi *uplink_vsi,
2826 uint16_t user_param)
2828 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2829 struct i40e_vsi *vsi;
2830 struct i40e_mac_filter_info filter;
2832 struct i40e_vsi_context ctxt;
2833 struct ether_addr broadcast =
2834 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2836 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2837 PMD_DRV_LOG(ERR, "VSI setup failed, "
2838 "VSI link shouldn't be NULL");
2842 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2843 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2844 "uplink VSI should be NULL");
2848 /* If uplink vsi didn't setup VEB, create one first */
2849 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2850 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2852 if (NULL == uplink_vsi->veb) {
2853 PMD_DRV_LOG(ERR, "VEB setup failed");
2858 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2860 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2863 TAILQ_INIT(&vsi->mac_list);
2865 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2866 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2867 vsi->parent_vsi = uplink_vsi;
2868 vsi->user_param = user_param;
2869 /* Allocate queues */
2870 switch (vsi->type) {
2871 case I40E_VSI_MAIN :
2872 vsi->nb_qps = pf->lan_nb_qps;
2874 case I40E_VSI_SRIOV :
2875 vsi->nb_qps = pf->vf_nb_qps;
2877 case I40E_VSI_VMDQ2:
2878 vsi->nb_qps = pf->vmdq_nb_qps;
2881 vsi->nb_qps = pf->fdir_nb_qps;
2887 * The filter status descriptor is reported in rx queue 0,
2888 * while the tx queue for fdir filter programming has no
2889 * such constraints, can be non-zero queues.
2890 * To simplify it, choose FDIR vsi use queue 0 pair.
2891 * To make sure it will use queue 0 pair, queue allocation
2892 * need be done before this function is called
2894 if (type != I40E_VSI_FDIR) {
2895 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2897 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2901 vsi->base_queue = ret;
2903 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2905 /* VF has MSIX interrupt in VF range, don't allocate here */
2906 if (type != I40E_VSI_SRIOV) {
2907 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2909 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2910 goto fail_queue_alloc;
2912 vsi->msix_intr = ret;
2916 if (type == I40E_VSI_MAIN) {
2917 /* For main VSI, no need to add since it's default one */
2918 vsi->uplink_seid = pf->mac_seid;
2919 vsi->seid = pf->main_vsi_seid;
2920 /* Bind queues with specific MSIX interrupt */
2922 * Needs 2 interrupt at least, one for misc cause which will
2923 * enabled from OS side, Another for queues binding the
2924 * interrupt from device side only.
2927 /* Get default VSI parameters from hardware */
2928 memset(&ctxt, 0, sizeof(ctxt));
2929 ctxt.seid = vsi->seid;
2930 ctxt.pf_num = hw->pf_id;
2931 ctxt.uplink_seid = vsi->uplink_seid;
2933 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2934 if (ret != I40E_SUCCESS) {
2935 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2936 goto fail_msix_alloc;
2938 (void)rte_memcpy(&vsi->info, &ctxt.info,
2939 sizeof(struct i40e_aqc_vsi_properties_data));
2940 vsi->vsi_id = ctxt.vsi_number;
2941 vsi->info.valid_sections = 0;
2943 /* Configure tc, enabled TC0 only */
2944 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2946 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2947 goto fail_msix_alloc;
2950 /* TC, queue mapping */
2951 memset(&ctxt, 0, sizeof(ctxt));
2952 vsi->info.valid_sections |=
2953 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2954 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2955 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2956 (void)rte_memcpy(&ctxt.info, &vsi->info,
2957 sizeof(struct i40e_aqc_vsi_properties_data));
2958 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2959 I40E_DEFAULT_TCMAP);
2960 if (ret != I40E_SUCCESS) {
2961 PMD_DRV_LOG(ERR, "Failed to configure "
2962 "TC queue mapping");
2963 goto fail_msix_alloc;
2965 ctxt.seid = vsi->seid;
2966 ctxt.pf_num = hw->pf_id;
2967 ctxt.uplink_seid = vsi->uplink_seid;
2970 /* Update VSI parameters */
2971 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2972 if (ret != I40E_SUCCESS) {
2973 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2974 goto fail_msix_alloc;
2977 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2978 sizeof(vsi->info.tc_mapping));
2979 (void)rte_memcpy(&vsi->info.queue_mapping,
2980 &ctxt.info.queue_mapping,
2981 sizeof(vsi->info.queue_mapping));
2982 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2983 vsi->info.valid_sections = 0;
2985 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2989 * Updating default filter settings are necessary to prevent
2990 * reception of tagged packets.
2991 * Some old firmware configurations load a default macvlan
2992 * filter which accepts both tagged and untagged packets.
2993 * The updating is to use a normal filter instead if needed.
2994 * For NVM 4.2.2 or after, the updating is not needed anymore.
2995 * The firmware with correct configurations load the default
2996 * macvlan filter which is expected and cannot be removed.
2998 i40e_update_default_filter_setting(vsi);
2999 } else if (type == I40E_VSI_SRIOV) {
3000 memset(&ctxt, 0, sizeof(ctxt));
3002 * For other VSI, the uplink_seid equals to uplink VSI's
3003 * uplink_seid since they share same VEB
3005 vsi->uplink_seid = uplink_vsi->uplink_seid;
3006 ctxt.pf_num = hw->pf_id;
3007 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3008 ctxt.uplink_seid = vsi->uplink_seid;
3009 ctxt.connection_type = 0x1;
3010 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3012 /* Configure switch ID */
3013 ctxt.info.valid_sections |=
3014 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3015 ctxt.info.switch_id =
3016 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3017 /* Configure port/vlan */
3018 ctxt.info.valid_sections |=
3019 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3020 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3021 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3022 I40E_DEFAULT_TCMAP);
3023 if (ret != I40E_SUCCESS) {
3024 PMD_DRV_LOG(ERR, "Failed to configure "
3025 "TC queue mapping");
3026 goto fail_msix_alloc;
3028 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3029 ctxt.info.valid_sections |=
3030 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3032 * Since VSI is not created yet, only configure parameter,
3033 * will add vsi below.
3035 } else if (type == I40E_VSI_VMDQ2) {
3036 memset(&ctxt, 0, sizeof(ctxt));
3038 * For other VSI, the uplink_seid equals to uplink VSI's
3039 * uplink_seid since they share same VEB
3041 vsi->uplink_seid = uplink_vsi->uplink_seid;
3042 ctxt.pf_num = hw->pf_id;
3044 ctxt.uplink_seid = vsi->uplink_seid;
3045 ctxt.connection_type = 0x1;
3046 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3048 ctxt.info.valid_sections |=
3049 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3050 /* user_param carries flag to enable loop back */
3052 ctxt.info.switch_id =
3053 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3054 ctxt.info.switch_id |=
3055 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3058 /* Configure port/vlan */
3059 ctxt.info.valid_sections |=
3060 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3061 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3062 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3063 I40E_DEFAULT_TCMAP);
3064 if (ret != I40E_SUCCESS) {
3065 PMD_DRV_LOG(ERR, "Failed to configure "
3066 "TC queue mapping");
3067 goto fail_msix_alloc;
3069 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3070 ctxt.info.valid_sections |=
3071 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3072 } else if (type == I40E_VSI_FDIR) {
3073 vsi->uplink_seid = uplink_vsi->uplink_seid;
3074 ctxt.pf_num = hw->pf_id;
3076 ctxt.uplink_seid = vsi->uplink_seid;
3077 ctxt.connection_type = 0x1; /* regular data port */
3078 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3079 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3080 I40E_DEFAULT_TCMAP);
3081 if (ret != I40E_SUCCESS) {
3082 PMD_DRV_LOG(ERR, "Failed to configure "
3083 "TC queue mapping.");
3084 goto fail_msix_alloc;
3086 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3087 ctxt.info.valid_sections |=
3088 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3090 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3091 goto fail_msix_alloc;
3094 if (vsi->type != I40E_VSI_MAIN) {
3095 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3097 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3098 hw->aq.asq_last_status);
3099 goto fail_msix_alloc;
3101 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3102 vsi->info.valid_sections = 0;
3103 vsi->seid = ctxt.seid;
3104 vsi->vsi_id = ctxt.vsi_number;
3105 vsi->sib_vsi_list.vsi = vsi;
3106 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3107 &vsi->sib_vsi_list, list);
3110 /* MAC/VLAN configuration */
3111 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3112 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3114 ret = i40e_vsi_add_mac(vsi, &filter);
3115 if (ret != I40E_SUCCESS) {
3116 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3117 goto fail_msix_alloc;
3120 /* Get VSI BW information */
3121 i40e_vsi_dump_bw_config(vsi);
3124 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3126 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3132 /* Configure vlan stripping on or off */
3134 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3136 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3137 struct i40e_vsi_context ctxt;
3139 int ret = I40E_SUCCESS;
3141 /* Check if it has been already on or off */
3142 if (vsi->info.valid_sections &
3143 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3145 if ((vsi->info.port_vlan_flags &
3146 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3147 return 0; /* already on */
3149 if ((vsi->info.port_vlan_flags &
3150 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3151 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3152 return 0; /* already off */
3157 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3159 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3160 vsi->info.valid_sections =
3161 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3162 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3163 vsi->info.port_vlan_flags |= vlan_flags;
3164 ctxt.seid = vsi->seid;
3165 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3166 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3168 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3169 on ? "enable" : "disable");
3175 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3177 struct rte_eth_dev_data *data = dev->data;
3180 /* Apply vlan offload setting */
3181 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3183 /* Apply double-vlan setting, not implemented yet */
3185 /* Apply pvid setting */
3186 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3187 data->dev_conf.txmode.hw_vlan_insert_pvid);
3189 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3195 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3197 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3199 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3203 i40e_update_flow_control(struct i40e_hw *hw)
3205 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3206 struct i40e_link_status link_status;
3207 uint32_t rxfc = 0, txfc = 0, reg;
3211 memset(&link_status, 0, sizeof(link_status));
3212 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3213 if (ret != I40E_SUCCESS) {
3214 PMD_DRV_LOG(ERR, "Failed to get link status information");
3215 goto write_reg; /* Disable flow control */
3218 an_info = hw->phy.link_info.an_info;
3219 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3220 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3221 ret = I40E_ERR_NOT_READY;
3222 goto write_reg; /* Disable flow control */
3225 * If link auto negotiation is enabled, flow control needs to
3226 * be configured according to it
3228 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3229 case I40E_LINK_PAUSE_RXTX:
3232 hw->fc.current_mode = I40E_FC_FULL;
3234 case I40E_AQ_LINK_PAUSE_RX:
3236 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3238 case I40E_AQ_LINK_PAUSE_TX:
3240 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3243 hw->fc.current_mode = I40E_FC_NONE;
3248 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3249 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3250 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3251 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3252 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3253 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3260 i40e_pf_setup(struct i40e_pf *pf)
3262 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3263 struct i40e_filter_control_settings settings;
3264 struct i40e_vsi *vsi;
3267 /* Clear all stats counters */
3268 pf->offset_loaded = FALSE;
3269 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3270 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3272 ret = i40e_pf_get_switch_config(pf);
3273 if (ret != I40E_SUCCESS) {
3274 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3277 if (pf->flags & I40E_FLAG_FDIR) {
3278 /* make queue allocated first, let FDIR use queue pair 0*/
3279 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3280 if (ret != I40E_FDIR_QUEUE_ID) {
3281 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3283 pf->flags &= ~I40E_FLAG_FDIR;
3286 /* main VSI setup */
3287 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3289 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3290 return I40E_ERR_NOT_READY;
3294 /* setup FDIR after main vsi created.*/
3295 if (pf->flags & I40E_FLAG_FDIR) {
3296 ret = i40e_fdir_setup(pf);
3297 if (ret != I40E_SUCCESS) {
3298 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
3299 pf->flags &= ~I40E_FLAG_FDIR;
3303 /* Configure filter control */
3304 memset(&settings, 0, sizeof(settings));
3305 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3306 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3307 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3308 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3310 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3311 hw->func_caps.rss_table_size);
3312 return I40E_ERR_PARAM;
3314 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3315 "size: %u\n", hw->func_caps.rss_table_size);
3316 pf->hash_lut_size = hw->func_caps.rss_table_size;
3318 /* Enable ethtype and macvlan filters */
3319 settings.enable_ethtype = TRUE;
3320 settings.enable_macvlan = TRUE;
3321 ret = i40e_set_filter_control(hw, &settings);
3323 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3326 /* Update flow control according to the auto negotiation */
3327 i40e_update_flow_control(hw);
3329 return I40E_SUCCESS;
3333 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3339 * Set or clear TX Queue Disable flags,
3340 * which is required by hardware.
3342 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3343 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3345 /* Wait until the request is finished */
3346 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3347 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3348 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3349 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3350 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3356 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3357 return I40E_SUCCESS; /* already on, skip next steps */
3359 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3360 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3362 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3363 return I40E_SUCCESS; /* already off, skip next steps */
3364 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3366 /* Write the register */
3367 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3368 /* Check the result */
3369 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3370 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3371 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3373 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3374 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3377 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3378 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3382 /* Check if it is timeout */
3383 if (j >= I40E_CHK_Q_ENA_COUNT) {
3384 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3385 (on ? "enable" : "disable"), q_idx);
3386 return I40E_ERR_TIMEOUT;
3389 return I40E_SUCCESS;
3392 /* Swith on or off the tx queues */
3394 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3396 struct rte_eth_dev_data *dev_data = pf->dev_data;
3397 struct i40e_tx_queue *txq;
3398 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3402 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3403 txq = dev_data->tx_queues[i];
3404 /* Don't operate the queue if not configured or
3405 * if starting only per queue */
3406 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3409 ret = i40e_dev_tx_queue_start(dev, i);
3411 ret = i40e_dev_tx_queue_stop(dev, i);
3412 if ( ret != I40E_SUCCESS)
3416 return I40E_SUCCESS;
3420 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3425 /* Wait until the request is finished */
3426 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3427 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3428 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3429 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3430 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3435 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3436 return I40E_SUCCESS; /* Already on, skip next steps */
3437 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3439 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3440 return I40E_SUCCESS; /* Already off, skip next steps */
3441 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3444 /* Write the register */
3445 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3446 /* Check the result */
3447 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3448 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3449 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3451 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3452 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3455 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3456 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3461 /* Check if it is timeout */
3462 if (j >= I40E_CHK_Q_ENA_COUNT) {
3463 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3464 (on ? "enable" : "disable"), q_idx);
3465 return I40E_ERR_TIMEOUT;
3468 return I40E_SUCCESS;
3470 /* Switch on or off the rx queues */
3472 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3474 struct rte_eth_dev_data *dev_data = pf->dev_data;
3475 struct i40e_rx_queue *rxq;
3476 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3480 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3481 rxq = dev_data->rx_queues[i];
3482 /* Don't operate the queue if not configured or
3483 * if starting only per queue */
3484 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3487 ret = i40e_dev_rx_queue_start(dev, i);
3489 ret = i40e_dev_rx_queue_stop(dev, i);
3490 if (ret != I40E_SUCCESS)
3494 return I40E_SUCCESS;
3497 /* Switch on or off all the rx/tx queues */
3499 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3504 /* enable rx queues before enabling tx queues */
3505 ret = i40e_dev_switch_rx_queues(pf, on);
3507 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3510 ret = i40e_dev_switch_tx_queues(pf, on);
3512 /* Stop tx queues before stopping rx queues */
3513 ret = i40e_dev_switch_tx_queues(pf, on);
3515 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3518 ret = i40e_dev_switch_rx_queues(pf, on);
3524 /* Initialize VSI for TX */
3526 i40e_dev_tx_init(struct i40e_pf *pf)
3528 struct rte_eth_dev_data *data = pf->dev_data;
3530 uint32_t ret = I40E_SUCCESS;
3531 struct i40e_tx_queue *txq;
3533 for (i = 0; i < data->nb_tx_queues; i++) {
3534 txq = data->tx_queues[i];
3535 if (!txq || !txq->q_set)
3537 ret = i40e_tx_queue_init(txq);
3538 if (ret != I40E_SUCCESS)
3545 /* Initialize VSI for RX */
3547 i40e_dev_rx_init(struct i40e_pf *pf)
3549 struct rte_eth_dev_data *data = pf->dev_data;
3550 int ret = I40E_SUCCESS;
3552 struct i40e_rx_queue *rxq;
3554 i40e_pf_config_mq_rx(pf);
3555 for (i = 0; i < data->nb_rx_queues; i++) {
3556 rxq = data->rx_queues[i];
3557 if (!rxq || !rxq->q_set)
3560 ret = i40e_rx_queue_init(rxq);
3561 if (ret != I40E_SUCCESS) {
3562 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3572 i40e_dev_rxtx_init(struct i40e_pf *pf)
3576 err = i40e_dev_tx_init(pf);
3578 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3581 err = i40e_dev_rx_init(pf);
3583 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3591 i40e_vmdq_setup(struct rte_eth_dev *dev)
3593 struct rte_eth_conf *conf = &dev->data->dev_conf;
3594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3595 int i, err, conf_vsis, j, loop;
3596 struct i40e_vsi *vsi;
3597 struct i40e_vmdq_info *vmdq_info;
3598 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3599 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3602 * Disable interrupt to avoid message from VF. Furthermore, it will
3603 * avoid race condition in VSI creation/destroy.
3605 i40e_pf_disable_irq0(hw);
3607 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3608 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3612 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3613 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3614 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3615 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3616 pf->max_nb_vmdq_vsi);
3620 if (pf->vmdq != NULL) {
3621 PMD_INIT_LOG(INFO, "VMDQ already configured");
3625 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3626 sizeof(*vmdq_info) * conf_vsis, 0);
3628 if (pf->vmdq == NULL) {
3629 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3633 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3635 /* Create VMDQ VSI */
3636 for (i = 0; i < conf_vsis; i++) {
3637 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3638 vmdq_conf->enable_loop_back);
3640 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3644 vmdq_info = &pf->vmdq[i];
3646 vmdq_info->vsi = vsi;
3648 pf->nb_cfg_vmdq_vsi = conf_vsis;
3650 /* Configure Vlan */
3651 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3652 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3653 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3654 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3655 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3656 vmdq_conf->pool_map[i].vlan_id, j);
3658 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3659 vmdq_conf->pool_map[i].vlan_id);
3661 PMD_INIT_LOG(ERR, "Failed to add vlan");
3669 i40e_pf_enable_irq0(hw);
3674 for (i = 0; i < conf_vsis; i++)
3675 if (pf->vmdq[i].vsi == NULL)
3678 i40e_vsi_release(pf->vmdq[i].vsi);
3682 i40e_pf_enable_irq0(hw);
3687 i40e_stat_update_32(struct i40e_hw *hw,
3695 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3699 if (new_data >= *offset)
3700 *stat = (uint64_t)(new_data - *offset);
3702 *stat = (uint64_t)((new_data +
3703 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3707 i40e_stat_update_48(struct i40e_hw *hw,
3716 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3717 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3718 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3723 if (new_data >= *offset)
3724 *stat = new_data - *offset;
3726 *stat = (uint64_t)((new_data +
3727 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3729 *stat &= I40E_48_BIT_MASK;
3734 i40e_pf_disable_irq0(struct i40e_hw *hw)
3736 /* Disable all interrupt types */
3737 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3738 I40E_WRITE_FLUSH(hw);
3743 i40e_pf_enable_irq0(struct i40e_hw *hw)
3745 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3746 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3747 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3748 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3749 I40E_WRITE_FLUSH(hw);
3753 i40e_pf_config_irq0(struct i40e_hw *hw)
3755 /* read pending request and disable first */
3756 i40e_pf_disable_irq0(hw);
3757 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3758 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3759 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3761 /* Link no queues with irq0 */
3762 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3763 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3767 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3773 uint32_t index, offset, val;
3778 * Try to find which VF trigger a reset, use absolute VF id to access
3779 * since the reg is global register.
3781 for (i = 0; i < pf->vf_num; i++) {
3782 abs_vf_id = hw->func_caps.vf_base_id + i;
3783 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3784 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3785 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3786 /* VFR event occured */
3787 if (val & (0x1 << offset)) {
3790 /* Clear the event first */
3791 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3793 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3795 * Only notify a VF reset event occured,
3796 * don't trigger another SW reset
3798 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3799 if (ret != I40E_SUCCESS)
3800 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3806 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809 struct i40e_arq_event_info info;
3810 uint16_t pending, opcode;
3813 info.buf_len = I40E_AQ_BUF_SZ;
3814 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3815 if (!info.msg_buf) {
3816 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3822 ret = i40e_clean_arq_element(hw, &info, &pending);
3824 if (ret != I40E_SUCCESS) {
3825 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3826 "aq_err: %u", hw->aq.asq_last_status);
3829 opcode = rte_le_to_cpu_16(info.desc.opcode);
3832 case i40e_aqc_opc_send_msg_to_pf:
3833 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3834 i40e_pf_host_handle_vf_msg(dev,
3835 rte_le_to_cpu_16(info.desc.retval),
3836 rte_le_to_cpu_32(info.desc.cookie_high),
3837 rte_le_to_cpu_32(info.desc.cookie_low),
3842 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3847 rte_free(info.msg_buf);
3851 * Interrupt handler is registered as the alarm callback for handling LSC
3852 * interrupt in a definite of time, in order to wait the NIC into a stable
3853 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3854 * no need for link down interrupt.
3857 i40e_dev_interrupt_delayed_handler(void *param)
3859 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863 /* read interrupt causes again */
3864 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3866 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3867 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3868 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3869 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3870 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3871 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3872 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3873 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3874 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3875 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3876 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3878 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3879 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3880 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3881 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3882 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3884 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3885 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3886 i40e_dev_handle_vfr_event(dev);
3888 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3889 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3890 i40e_dev_handle_aq_msg(dev);
3893 /* handle the link up interrupt in an alarm callback */
3894 i40e_dev_link_update(dev, 0);
3895 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3897 i40e_pf_enable_irq0(hw);
3898 rte_intr_enable(&(dev->pci_dev->intr_handle));
3902 * Interrupt handler triggered by NIC for handling
3903 * specific interrupt.
3906 * Pointer to interrupt handle.
3908 * The address of parameter (struct rte_eth_dev *) regsitered before.
3914 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3917 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3918 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 /* Disable interrupt */
3922 i40e_pf_disable_irq0(hw);
3924 /* read out interrupt causes */
3925 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3927 /* No interrupt event indicated */
3928 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3929 PMD_DRV_LOG(INFO, "No interrupt event");
3932 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3933 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3934 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3935 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3936 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3937 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3938 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3939 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3940 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3941 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3942 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3943 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3944 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3945 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3946 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3947 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3949 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3950 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3951 i40e_dev_handle_vfr_event(dev);
3953 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3954 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3955 i40e_dev_handle_aq_msg(dev);
3958 /* Link Status Change interrupt */
3959 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3960 #define I40E_US_PER_SECOND 1000000
3961 struct rte_eth_link link;
3963 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3964 memset(&link, 0, sizeof(link));
3965 rte_i40e_dev_atomic_read_link_status(dev, &link);
3966 i40e_dev_link_update(dev, 0);
3969 * For link up interrupt, it needs to wait 1 second to let the
3970 * hardware be a stable state. Otherwise several consecutive
3971 * interrupts can be observed.
3972 * For link down interrupt, no need to wait.
3974 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3975 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3978 _rte_eth_dev_callback_process(dev,
3979 RTE_ETH_EVENT_INTR_LSC);
3983 /* Enable interrupt */
3984 i40e_pf_enable_irq0(hw);
3985 rte_intr_enable(&(dev->pci_dev->intr_handle));
3989 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3990 struct i40e_macvlan_filter *filter,
3993 int ele_num, ele_buff_size;
3994 int num, actual_num, i;
3996 int ret = I40E_SUCCESS;
3997 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3998 struct i40e_aqc_add_macvlan_element_data *req_list;
4000 if (filter == NULL || total == 0)
4001 return I40E_ERR_PARAM;
4002 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4003 ele_buff_size = hw->aq.asq_buf_size;
4005 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4006 if (req_list == NULL) {
4007 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4008 return I40E_ERR_NO_MEMORY;
4013 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4014 memset(req_list, 0, ele_buff_size);
4016 for (i = 0; i < actual_num; i++) {
4017 (void)rte_memcpy(req_list[i].mac_addr,
4018 &filter[num + i].macaddr, ETH_ADDR_LEN);
4019 req_list[i].vlan_tag =
4020 rte_cpu_to_le_16(filter[num + i].vlan_id);
4022 switch (filter[num + i].filter_type) {
4023 case RTE_MAC_PERFECT_MATCH:
4024 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4025 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4027 case RTE_MACVLAN_PERFECT_MATCH:
4028 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4030 case RTE_MAC_HASH_MATCH:
4031 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4032 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4034 case RTE_MACVLAN_HASH_MATCH:
4035 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4038 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4039 ret = I40E_ERR_PARAM;
4043 req_list[i].queue_number = 0;
4045 req_list[i].flags = rte_cpu_to_le_16(flags);
4048 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4050 if (ret != I40E_SUCCESS) {
4051 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4055 } while (num < total);
4063 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4064 struct i40e_macvlan_filter *filter,
4067 int ele_num, ele_buff_size;
4068 int num, actual_num, i;
4070 int ret = I40E_SUCCESS;
4071 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4072 struct i40e_aqc_remove_macvlan_element_data *req_list;
4074 if (filter == NULL || total == 0)
4075 return I40E_ERR_PARAM;
4077 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4078 ele_buff_size = hw->aq.asq_buf_size;
4080 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4081 if (req_list == NULL) {
4082 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4083 return I40E_ERR_NO_MEMORY;
4088 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4089 memset(req_list, 0, ele_buff_size);
4091 for (i = 0; i < actual_num; i++) {
4092 (void)rte_memcpy(req_list[i].mac_addr,
4093 &filter[num + i].macaddr, ETH_ADDR_LEN);
4094 req_list[i].vlan_tag =
4095 rte_cpu_to_le_16(filter[num + i].vlan_id);
4097 switch (filter[num + i].filter_type) {
4098 case RTE_MAC_PERFECT_MATCH:
4099 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4100 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4102 case RTE_MACVLAN_PERFECT_MATCH:
4103 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4105 case RTE_MAC_HASH_MATCH:
4106 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4107 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4109 case RTE_MACVLAN_HASH_MATCH:
4110 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4113 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4114 ret = I40E_ERR_PARAM;
4117 req_list[i].flags = rte_cpu_to_le_16(flags);
4120 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4122 if (ret != I40E_SUCCESS) {
4123 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4127 } while (num < total);
4134 /* Find out specific MAC filter */
4135 static struct i40e_mac_filter *
4136 i40e_find_mac_filter(struct i40e_vsi *vsi,
4137 struct ether_addr *macaddr)
4139 struct i40e_mac_filter *f;
4141 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4142 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4150 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4153 uint32_t vid_idx, vid_bit;
4155 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4156 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4158 if (vsi->vfta[vid_idx] & vid_bit)
4165 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4166 uint16_t vlan_id, bool on)
4168 uint32_t vid_idx, vid_bit;
4170 #define UINT32_BIT_MASK 0x1F
4171 #define VALID_VLAN_BIT_MASK 0xFFF
4172 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4173 * element first, then find the bits it belongs to
4175 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4177 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4180 vsi->vfta[vid_idx] |= vid_bit;
4182 vsi->vfta[vid_idx] &= ~vid_bit;
4186 * Find all vlan options for specific mac addr,
4187 * return with actual vlan found.
4190 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4191 struct i40e_macvlan_filter *mv_f,
4192 int num, struct ether_addr *addr)
4198 * Not to use i40e_find_vlan_filter to decrease the loop time,
4199 * although the code looks complex.
4201 if (num < vsi->vlan_num)
4202 return I40E_ERR_PARAM;
4205 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4207 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4208 if (vsi->vfta[j] & (1 << k)) {
4210 PMD_DRV_LOG(ERR, "vlan number "
4212 return I40E_ERR_PARAM;
4214 (void)rte_memcpy(&mv_f[i].macaddr,
4215 addr, ETH_ADDR_LEN);
4217 j * I40E_UINT32_BIT_SIZE + k;
4223 return I40E_SUCCESS;
4227 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4228 struct i40e_macvlan_filter *mv_f,
4233 struct i40e_mac_filter *f;
4235 if (num < vsi->mac_num)
4236 return I40E_ERR_PARAM;
4238 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4240 PMD_DRV_LOG(ERR, "buffer number not match");
4241 return I40E_ERR_PARAM;
4243 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4245 mv_f[i].vlan_id = vlan;
4246 mv_f[i].filter_type = f->mac_info.filter_type;
4250 return I40E_SUCCESS;
4254 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4257 struct i40e_mac_filter *f;
4258 struct i40e_macvlan_filter *mv_f;
4259 int ret = I40E_SUCCESS;
4261 if (vsi == NULL || vsi->mac_num == 0)
4262 return I40E_ERR_PARAM;
4264 /* Case that no vlan is set */
4265 if (vsi->vlan_num == 0)
4268 num = vsi->mac_num * vsi->vlan_num;
4270 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4272 PMD_DRV_LOG(ERR, "failed to allocate memory");
4273 return I40E_ERR_NO_MEMORY;
4277 if (vsi->vlan_num == 0) {
4278 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4279 (void)rte_memcpy(&mv_f[i].macaddr,
4280 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4281 mv_f[i].vlan_id = 0;
4285 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4286 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4287 vsi->vlan_num, &f->mac_info.mac_addr);
4288 if (ret != I40E_SUCCESS)
4294 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4302 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4304 struct i40e_macvlan_filter *mv_f;
4306 int ret = I40E_SUCCESS;
4308 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4309 return I40E_ERR_PARAM;
4311 /* If it's already set, just return */
4312 if (i40e_find_vlan_filter(vsi,vlan))
4313 return I40E_SUCCESS;
4315 mac_num = vsi->mac_num;
4318 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4319 return I40E_ERR_PARAM;
4322 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4325 PMD_DRV_LOG(ERR, "failed to allocate memory");
4326 return I40E_ERR_NO_MEMORY;
4329 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4331 if (ret != I40E_SUCCESS)
4334 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4336 if (ret != I40E_SUCCESS)
4339 i40e_set_vlan_filter(vsi, vlan, 1);
4349 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4351 struct i40e_macvlan_filter *mv_f;
4353 int ret = I40E_SUCCESS;
4356 * Vlan 0 is the generic filter for untagged packets
4357 * and can't be removed.
4359 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4360 return I40E_ERR_PARAM;
4362 /* If can't find it, just return */
4363 if (!i40e_find_vlan_filter(vsi, vlan))
4364 return I40E_ERR_PARAM;
4366 mac_num = vsi->mac_num;
4369 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4370 return I40E_ERR_PARAM;
4373 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4376 PMD_DRV_LOG(ERR, "failed to allocate memory");
4377 return I40E_ERR_NO_MEMORY;
4380 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4382 if (ret != I40E_SUCCESS)
4385 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4387 if (ret != I40E_SUCCESS)
4390 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4391 if (vsi->vlan_num == 1) {
4392 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4393 if (ret != I40E_SUCCESS)
4396 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4397 if (ret != I40E_SUCCESS)
4401 i40e_set_vlan_filter(vsi, vlan, 0);
4411 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4413 struct i40e_mac_filter *f;
4414 struct i40e_macvlan_filter *mv_f;
4415 int i, vlan_num = 0;
4416 int ret = I40E_SUCCESS;
4418 /* If it's add and we've config it, return */
4419 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4421 return I40E_SUCCESS;
4422 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4423 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4426 * If vlan_num is 0, that's the first time to add mac,
4427 * set mask for vlan_id 0.
4429 if (vsi->vlan_num == 0) {
4430 i40e_set_vlan_filter(vsi, 0, 1);
4433 vlan_num = vsi->vlan_num;
4434 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4435 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4438 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4440 PMD_DRV_LOG(ERR, "failed to allocate memory");
4441 return I40E_ERR_NO_MEMORY;
4444 for (i = 0; i < vlan_num; i++) {
4445 mv_f[i].filter_type = mac_filter->filter_type;
4446 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4450 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4451 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4452 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4453 &mac_filter->mac_addr);
4454 if (ret != I40E_SUCCESS)
4458 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4459 if (ret != I40E_SUCCESS)
4462 /* Add the mac addr into mac list */
4463 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4465 PMD_DRV_LOG(ERR, "failed to allocate memory");
4466 ret = I40E_ERR_NO_MEMORY;
4469 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4471 f->mac_info.filter_type = mac_filter->filter_type;
4472 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4483 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4485 struct i40e_mac_filter *f;
4486 struct i40e_macvlan_filter *mv_f;
4488 enum rte_mac_filter_type filter_type;
4489 int ret = I40E_SUCCESS;
4491 /* Can't find it, return an error */
4492 f = i40e_find_mac_filter(vsi, addr);
4494 return I40E_ERR_PARAM;
4496 vlan_num = vsi->vlan_num;
4497 filter_type = f->mac_info.filter_type;
4498 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4499 filter_type == RTE_MACVLAN_HASH_MATCH) {
4500 if (vlan_num == 0) {
4501 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4502 return I40E_ERR_PARAM;
4504 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4505 filter_type == RTE_MAC_HASH_MATCH)
4508 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4510 PMD_DRV_LOG(ERR, "failed to allocate memory");
4511 return I40E_ERR_NO_MEMORY;
4514 for (i = 0; i < vlan_num; i++) {
4515 mv_f[i].filter_type = filter_type;
4516 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4519 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4520 filter_type == RTE_MACVLAN_HASH_MATCH) {
4521 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4522 if (ret != I40E_SUCCESS)
4526 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4527 if (ret != I40E_SUCCESS)
4530 /* Remove the mac addr into mac list */
4531 TAILQ_REMOVE(&vsi->mac_list, f, next);
4541 /* Configure hash enable flags for RSS */
4543 i40e_config_hena(uint64_t flags)
4550 if (flags & ETH_RSS_NONF_IPV4_UDP)
4551 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4552 if (flags & ETH_RSS_NONF_IPV4_TCP)
4553 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4554 if (flags & ETH_RSS_NONF_IPV4_SCTP)
4555 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4556 if (flags & ETH_RSS_NONF_IPV4_OTHER)
4557 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4558 if (flags & ETH_RSS_FRAG_IPV4)
4559 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4560 if (flags & ETH_RSS_NONF_IPV6_UDP)
4561 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4562 if (flags & ETH_RSS_NONF_IPV6_TCP)
4563 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4564 if (flags & ETH_RSS_NONF_IPV6_SCTP)
4565 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4566 if (flags & ETH_RSS_NONF_IPV6_OTHER)
4567 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4568 if (flags & ETH_RSS_FRAG_IPV6)
4569 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4570 if (flags & ETH_RSS_L2_PAYLOAD)
4571 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4576 /* Parse the hash enable flags */
4578 i40e_parse_hena(uint64_t flags)
4580 uint64_t rss_hf = 0;
4585 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4586 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4587 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4588 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4589 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4590 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4591 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4592 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4593 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4594 rss_hf |= ETH_RSS_FRAG_IPV4;
4595 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4596 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4597 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4598 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4599 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4600 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4601 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4602 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4603 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4604 rss_hf |= ETH_RSS_FRAG_IPV6;
4605 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4606 rss_hf |= ETH_RSS_L2_PAYLOAD;
4613 i40e_pf_disable_rss(struct i40e_pf *pf)
4615 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4618 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4619 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4620 hena &= ~I40E_RSS_HENA_ALL;
4621 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4622 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4623 I40E_WRITE_FLUSH(hw);
4627 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4630 uint8_t hash_key_len;
4635 hash_key = (uint32_t *)(rss_conf->rss_key);
4636 hash_key_len = rss_conf->rss_key_len;
4637 if (hash_key != NULL && hash_key_len >=
4638 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4639 /* Fill in RSS hash key */
4640 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4641 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4644 rss_hf = rss_conf->rss_hf;
4645 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4646 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4647 hena &= ~I40E_RSS_HENA_ALL;
4648 hena |= i40e_config_hena(rss_hf);
4649 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4650 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4651 I40E_WRITE_FLUSH(hw);
4657 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4658 struct rte_eth_rss_conf *rss_conf)
4660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4664 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4665 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4666 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4667 if (rss_hf != 0) /* Enable RSS */
4669 return 0; /* Nothing to do */
4672 if (rss_hf == 0) /* Disable RSS */
4675 return i40e_hw_rss_hash_set(hw, rss_conf);
4679 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4680 struct rte_eth_rss_conf *rss_conf)
4682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4683 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4687 if (hash_key != NULL) {
4688 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4689 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4690 rss_conf->rss_key_len = i * sizeof(uint32_t);
4692 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4693 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4694 rss_conf->rss_hf = i40e_parse_hena(hena);
4700 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4702 switch (filter_type) {
4703 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4704 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4706 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4707 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4709 case RTE_TUNNEL_FILTER_IMAC_TENID:
4710 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4712 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4713 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4715 case ETH_TUNNEL_FILTER_IMAC:
4716 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4719 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4727 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4728 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4732 uint8_t tun_type = 0;
4734 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4735 struct i40e_vsi *vsi = pf->main_vsi;
4736 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4737 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4739 cld_filter = rte_zmalloc("tunnel_filter",
4740 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4743 if (NULL == cld_filter) {
4744 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4747 pfilter = cld_filter;
4749 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4750 sizeof(struct ether_addr));
4751 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4752 sizeof(struct ether_addr));
4754 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4755 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4756 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4757 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4758 &tunnel_filter->ip_addr,
4759 sizeof(pfilter->ipaddr.v4.data));
4761 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4762 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4763 &tunnel_filter->ip_addr,
4764 sizeof(pfilter->ipaddr.v6.data));
4767 /* check tunneled type */
4768 switch (tunnel_filter->tunnel_type) {
4769 case RTE_TUNNEL_TYPE_VXLAN:
4770 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4773 /* Other tunnel types is not supported. */
4774 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4775 rte_free(cld_filter);
4779 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4782 rte_free(cld_filter);
4786 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4787 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4788 pfilter->tenant_id = tunnel_filter->tenant_id;
4789 pfilter->queue_number = tunnel_filter->queue_id;
4792 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4794 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4797 rte_free(cld_filter);
4802 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4806 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4807 if (pf->vxlan_ports[i] == port)
4815 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4819 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4821 idx = i40e_get_vxlan_port_idx(pf, port);
4823 /* Check if port already exists */
4825 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4829 /* Now check if there is space to add the new port */
4830 idx = i40e_get_vxlan_port_idx(pf, 0);
4832 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4833 "not adding port %d", port);
4837 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4840 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4844 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4847 /* New port: add it and mark its index in the bitmap */
4848 pf->vxlan_ports[idx] = port;
4849 pf->vxlan_bitmap |= (1 << idx);
4851 if (!(pf->flags & I40E_FLAG_VXLAN))
4852 pf->flags |= I40E_FLAG_VXLAN;
4858 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4861 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4863 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4864 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4868 idx = i40e_get_vxlan_port_idx(pf, port);
4871 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4875 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4876 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4880 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4883 pf->vxlan_ports[idx] = 0;
4884 pf->vxlan_bitmap &= ~(1 << idx);
4886 if (!pf->vxlan_bitmap)
4887 pf->flags &= ~I40E_FLAG_VXLAN;
4892 /* Add UDP tunneling port */
4894 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4895 struct rte_eth_udp_tunnel *udp_tunnel)
4898 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4900 if (udp_tunnel == NULL)
4903 switch (udp_tunnel->prot_type) {
4904 case RTE_TUNNEL_TYPE_VXLAN:
4905 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4908 case RTE_TUNNEL_TYPE_GENEVE:
4909 case RTE_TUNNEL_TYPE_TEREDO:
4910 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4915 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4923 /* Remove UDP tunneling port */
4925 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4926 struct rte_eth_udp_tunnel *udp_tunnel)
4929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4931 if (udp_tunnel == NULL)
4934 switch (udp_tunnel->prot_type) {
4935 case RTE_TUNNEL_TYPE_VXLAN:
4936 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4938 case RTE_TUNNEL_TYPE_GENEVE:
4939 case RTE_TUNNEL_TYPE_TEREDO:
4940 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4944 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4952 /* Calculate the maximum number of contiguous PF queues that are configured */
4954 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4956 struct rte_eth_dev_data *data = pf->dev_data;
4958 struct i40e_rx_queue *rxq;
4961 for (i = 0; i < pf->lan_nb_qps; i++) {
4962 rxq = data->rx_queues[i];
4963 if (rxq && rxq->q_set)
4974 i40e_pf_config_rss(struct i40e_pf *pf)
4976 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4977 struct rte_eth_rss_conf rss_conf;
4978 uint32_t i, lut = 0;
4982 * If both VMDQ and RSS enabled, not all of PF queues are configured.
4983 * It's necessary to calulate the actual PF queues that are configured.
4985 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4986 num = i40e_pf_calc_configured_queues_num(pf);
4987 num = i40e_align_floor(num);
4989 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4991 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
4995 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
4999 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5002 lut = (lut << 8) | (j & ((0x1 <<
5003 hw->func_caps.rss_table_entry_width) - 1));
5005 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5008 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5009 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5010 i40e_pf_disable_rss(pf);
5013 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5014 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5015 /* Calculate the default hash key */
5016 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5017 rss_key_default[i] = (uint32_t)rte_rand();
5018 rss_conf.rss_key = (uint8_t *)rss_key_default;
5019 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5023 return i40e_hw_rss_hash_set(hw, &rss_conf);
5027 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5028 struct rte_eth_tunnel_filter_conf *filter)
5030 if (pf == NULL || filter == NULL) {
5031 PMD_DRV_LOG(ERR, "Invalid parameter");
5035 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5036 PMD_DRV_LOG(ERR, "Invalid queue ID");
5040 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5041 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5045 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5046 (is_zero_ether_addr(filter->outer_mac))) {
5047 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5051 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5052 (is_zero_ether_addr(filter->inner_mac))) {
5053 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5061 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5064 struct rte_eth_tunnel_filter_conf *filter;
5065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5066 int ret = I40E_SUCCESS;
5068 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5070 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5071 return I40E_ERR_PARAM;
5073 switch (filter_op) {
5074 case RTE_ETH_FILTER_NOP:
5075 if (!(pf->flags & I40E_FLAG_VXLAN))
5076 ret = I40E_NOT_SUPPORTED;
5077 case RTE_ETH_FILTER_ADD:
5078 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5080 case RTE_ETH_FILTER_DELETE:
5081 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5084 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5085 ret = I40E_ERR_PARAM;
5093 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5096 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5098 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5099 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5104 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5105 ret = i40e_pf_config_rss(pf);
5107 i40e_pf_disable_rss(pf);
5113 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5114 enum rte_filter_type filter_type,
5115 enum rte_filter_op filter_op,
5123 switch (filter_type) {
5124 case RTE_ETH_FILTER_MACVLAN:
5125 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5127 case RTE_ETH_FILTER_TUNNEL:
5128 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5131 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",