lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 110 static int i40e_dev_configure(struct rte_eth_dev *dev);
 111 static int i40e_dev_start(struct rte_eth_dev *dev);
 112 static void i40e_dev_stop(struct rte_eth_dev *dev);
 113 static void i40e_dev_close(struct rte_eth_dev *dev);
 114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 121                                struct rte_eth_stats *stats);
 122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 124                                             uint16_t queue_id,
 125                                             uint8_t stat_idx,
 126                                             uint8_t is_rx);
 127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 128                               struct rte_eth_dev_info *dev_info);
 129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 130                                 uint16_t vlan_id,
 131                                 int on);
 132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 135                                       uint16_t queue,
 136                                       int on);
 137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 141                               struct rte_eth_fc_conf *fc_conf);
 142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                        struct rte_eth_pfc_conf *pfc_conf);
 144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 145                           struct ether_addr *mac_addr,
 146                           uint32_t index,
 147                           uint32_t pool);
 148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 150                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                     uint16_t reta_size);
 152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 153                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 154                                    uint16_t reta_size);
 155
 156 static int i40e_get_cap(struct i40e_hw *hw);
 157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 158 static int i40e_pf_setup(struct i40e_pf *pf);
 159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 162                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 163 static void i40e_stat_update_48(struct i40e_hw *hw,
 164                                uint32_t hireg,
 165                                uint32_t loreg,
 166                                bool offset_loaded,
 167                                uint64_t *offset,
 168                                uint64_t *stat);
 169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 170 static void i40e_dev_interrupt_handler(
 171                 __rte_unused struct rte_intr_handle *handle, void *param);
 172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 173                                 uint32_t base, uint32_t num);
 174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 176                         uint32_t base);
 177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 178                         uint16_t num);
 179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 180 static int i40e_veb_release(struct i40e_veb *veb);
 181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 182                                                 struct i40e_vsi *vsi);
 183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 186                                              struct i40e_macvlan_filter *mv_f,
 187                                              int num,
 188                                              struct ether_addr *addr);
 189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 190                                              struct i40e_macvlan_filter *mv_f,
 191                                              int num,
 192                                              uint16_t vlan);
 193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 195                                     struct rte_eth_rss_conf *rss_conf);
 196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 197                                       struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 199                                 struct rte_eth_udp_tunnel *udp_tunnel);
 200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 203                         struct rte_eth_ethertype_filter *filter,
 204                         bool add);
 205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 206                                 enum rte_filter_op filter_op,
 207                                 void *arg);
 208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 209                                 enum rte_filter_type filter_type,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static void i40e_configure_registers(struct i40e_hw *hw);
 213 static void i40e_hw_init(struct i40e_hw *hw);
 214
 215 static struct rte_pci_id pci_id_i40e_map[] = {
 216 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 217 #include "rte_pci_dev_ids.h"
 218 { .vendor_id = 0, /* sentinel */ },
 219 };
 220
 221 static struct eth_dev_ops i40e_eth_dev_ops = {
 222         .dev_configure                = i40e_dev_configure,
 223         .dev_start                    = i40e_dev_start,
 224         .dev_stop                     = i40e_dev_stop,
 225         .dev_close                    = i40e_dev_close,
 226         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 227         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 228         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 229         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 230         .dev_set_link_up              = i40e_dev_set_link_up,
 231         .dev_set_link_down            = i40e_dev_set_link_down,
 232         .link_update                  = i40e_dev_link_update,
 233         .stats_get                    = i40e_dev_stats_get,
 234         .stats_reset                  = i40e_dev_stats_reset,
 235         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 236         .dev_infos_get                = i40e_dev_info_get,
 237         .vlan_filter_set              = i40e_vlan_filter_set,
 238         .vlan_tpid_set                = i40e_vlan_tpid_set,
 239         .vlan_offload_set             = i40e_vlan_offload_set,
 240         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 241         .vlan_pvid_set                = i40e_vlan_pvid_set,
 242         .rx_queue_start               = i40e_dev_rx_queue_start,
 243         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 244         .tx_queue_start               = i40e_dev_tx_queue_start,
 245         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 246         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 247         .rx_queue_release             = i40e_dev_rx_queue_release,
 248         .rx_queue_count               = i40e_dev_rx_queue_count,
 249         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 250         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 251         .tx_queue_release             = i40e_dev_tx_queue_release,
 252         .dev_led_on                   = i40e_dev_led_on,
 253         .dev_led_off                  = i40e_dev_led_off,
 254         .flow_ctrl_set                = i40e_flow_ctrl_set,
 255         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 256         .mac_addr_add                 = i40e_macaddr_add,
 257         .mac_addr_remove              = i40e_macaddr_remove,
 258         .reta_update                  = i40e_dev_rss_reta_update,
 259         .reta_query                   = i40e_dev_rss_reta_query,
 260         .rss_hash_update              = i40e_dev_rss_hash_update,
 261         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 262         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 263         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 264         .filter_ctrl                  = i40e_dev_filter_ctrl,
 265 };
 266
 267 static struct eth_driver rte_i40e_pmd = {
 268         {
 269                 .name = "rte_i40e_pmd",
 270                 .id_table = pci_id_i40e_map,
 271                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 272         },
 273         .eth_dev_init = eth_i40e_dev_init,
 274         .dev_private_size = sizeof(struct i40e_adapter),
 275 };
 276
 277 static inline int
 278 i40e_align_floor(int n)
 279 {
 280         if (n == 0)
 281                 return 0;
 282         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 283 }
 284
 285 static inline int
 286 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 287                                      struct rte_eth_link *link)
 288 {
 289         struct rte_eth_link *dst = link;
 290         struct rte_eth_link *src = &(dev->data->dev_link);
 291
 292         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 293                                         *(uint64_t *)src) == 0)
 294                 return -1;
 295
 296         return 0;
 297 }
 298
 299 static inline int
 300 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 301                                       struct rte_eth_link *link)
 302 {
 303         struct rte_eth_link *dst = &(dev->data->dev_link);
 304         struct rte_eth_link *src = link;
 305
 306         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 307                                         *(uint64_t *)src) == 0)
 308                 return -1;
 309
 310         return 0;
 311 }
 312
 313 /*
 314  * Driver initialization routine.
 315  * Invoked once at EAL init time.
 316  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 317  */
 318 static int
 319 rte_i40e_pmd_init(const char *name __rte_unused,
 320                   const char *params __rte_unused)
 321 {
 322         PMD_INIT_FUNC_TRACE();
 323         rte_eth_driver_register(&rte_i40e_pmd);
 324
 325         return 0;
 326 }
 327
 328 static struct rte_driver rte_i40e_driver = {
 329         .type = PMD_PDEV,
 330         .init = rte_i40e_pmd_init,
 331 };
 332
 333 PMD_REGISTER_DRIVER(rte_i40e_driver);
 334
 335 /*
 336  * Initialize registers for flexible payload, which should be set by NVM.
 337  * This should be removed from code once it is fixed in NVM.
 338  */
 339 #ifndef I40E_GLQF_ORT
 340 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 341 #endif
 342 #ifndef I40E_GLQF_PIT
 343 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 344 #endif
 345
 346 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 347 {
 348         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 349         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 358
 359         /* GLQF_PIT Registers */
 360         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 361         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 362 }
 363
 364 static int
 365 eth_i40e_dev_init(struct rte_eth_dev *dev)
 366 {
 367         struct rte_pci_device *pci_dev;
 368         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 370         struct i40e_vsi *vsi;
 371         int ret;
 372         uint32_t len;
 373         uint8_t aq_fail = 0;
 374
 375         PMD_INIT_FUNC_TRACE();
 376
 377         dev->dev_ops = &i40e_eth_dev_ops;
 378         dev->rx_pkt_burst = i40e_recv_pkts;
 379         dev->tx_pkt_burst = i40e_xmit_pkts;
 380
 381         /* for secondary processes, we don't initialise any further as primary
 382          * has already done this work. Only check we don't need a different
 383          * RX function */
 384         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 385                 if (dev->data->scattered_rx)
 386                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 387                 return 0;
 388         }
 389         pci_dev = dev->pci_dev;
 390         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 391         pf->adapter->eth_dev = dev;
 392         pf->dev_data = dev->data;
 393
 394         hw->back = I40E_PF_TO_ADAPTER(pf);
 395         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 396         if (!hw->hw_addr) {
 397                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 398                              "as address is NULL");
 399                 return -ENODEV;
 400         }
 401
 402         hw->vendor_id = pci_dev->id.vendor_id;
 403         hw->device_id = pci_dev->id.device_id;
 404         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 405         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 406         hw->bus.device = pci_dev->addr.devid;
 407         hw->bus.func = pci_dev->addr.function;
 408
 409         /* Make sure all is clean before doing PF reset */
 410         i40e_clear_hw(hw);
 411
 412         /* Initialize the hardware */
 413         i40e_hw_init(hw);
 414
 415         /* Reset here to make sure all is clean for each PF */
 416         ret = i40e_pf_reset(hw);
 417         if (ret) {
 418                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 419                 return ret;
 420         }
 421
 422         /* Initialize the shared code (base driver) */
 423         ret = i40e_init_shared_code(hw);
 424         if (ret) {
 425                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 426                 return ret;
 427         }
 428
 429         /*
 430          * To work around the NVM issue,initialize registers
 431          * for flexible payload by software.
 432          * It should be removed once issues are fixed in NVM.
 433          */
 434         i40e_flex_payload_reg_init(hw);
 435
 436         /* Initialize the parameters for adminq */
 437         i40e_init_adminq_parameter(hw);
 438         ret = i40e_init_adminq(hw);
 439         if (ret != I40E_SUCCESS) {
 440                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 441                 return -EIO;
 442         }
 443         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 444                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 445                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 446                      ((hw->nvm.version >> 12) & 0xf),
 447                      ((hw->nvm.version >> 4) & 0xff),
 448                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 449
 450         /* Disable LLDP */
 451         ret = i40e_aq_stop_lldp(hw, true, NULL);
 452         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 453                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 454
 455         /* Clear PXE mode */
 456         i40e_clear_pxe_mode(hw);
 457
 458         /*
 459          * On X710, performance number is far from the expectation on recent
 460          * firmware versions. The fix for this issue may not be integrated in
 461          * the following firmware version. So the workaround in software driver
 462          * is needed. It needs to modify the initial values of 3 internal only
 463          * registers. Note that the workaround can be removed when it is fixed
 464          * in firmware in the future.
 465          */
 466         i40e_configure_registers(hw);
 467
 468         /* Get hw capabilities */
 469         ret = i40e_get_cap(hw);
 470         if (ret != I40E_SUCCESS) {
 471                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 472                 goto err_get_capabilities;
 473         }
 474
 475         /* Initialize parameters for PF */
 476         ret = i40e_pf_parameter_init(dev);
 477         if (ret != 0) {
 478                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 479                 goto err_parameter_init;
 480         }
 481
 482         /* Initialize the queue management */
 483         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 484         if (ret < 0) {
 485                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 486                 goto err_qp_pool_init;
 487         }
 488         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 489                                 hw->func_caps.num_msix_vectors - 1);
 490         if (ret < 0) {
 491                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 492                 goto err_msix_pool_init;
 493         }
 494
 495         /* Initialize lan hmc */
 496         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 497                                 hw->func_caps.num_rx_qp, 0, 0);
 498         if (ret != I40E_SUCCESS) {
 499                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 500                 goto err_init_lan_hmc;
 501         }
 502
 503         /* Configure lan hmc */
 504         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 505         if (ret != I40E_SUCCESS) {
 506                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 507                 goto err_configure_lan_hmc;
 508         }
 509
 510         /* Get and check the mac address */
 511         i40e_get_mac_addr(hw, hw->mac.addr);
 512         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 513                 PMD_INIT_LOG(ERR, "mac address is not valid");
 514                 ret = -EIO;
 515                 goto err_get_mac_addr;
 516         }
 517         /* Copy the permanent MAC address */
 518         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 519                         (struct ether_addr *) hw->mac.perm_addr);
 520
 521         /* Disable flow control */
 522         hw->fc.requested_mode = I40E_FC_NONE;
 523         i40e_set_fc(hw, &aq_fail, TRUE);
 524
 525         /* PF setup, which includes VSI setup */
 526         ret = i40e_pf_setup(pf);
 527         if (ret) {
 528                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 529                 goto err_setup_pf_switch;
 530         }
 531
 532         vsi = pf->main_vsi;
 533
 534         /* Disable double vlan by default */
 535         i40e_vsi_config_double_vlan(vsi, FALSE);
 536
 537         if (!vsi->max_macaddrs)
 538                 len = ETHER_ADDR_LEN;
 539         else
 540                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 541
 542         /* Should be after VSI initialized */
 543         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 544         if (!dev->data->mac_addrs) {
 545                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 546                                         "for storing mac address");
 547                 goto err_mac_alloc;
 548         }
 549         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 550                                         &dev->data->mac_addrs[0]);
 551
 552         /* initialize pf host driver to setup SRIOV resource if applicable */
 553         i40e_pf_host_init(dev);
 554
 555         /* register callback func to eal lib */
 556         rte_intr_callback_register(&(pci_dev->intr_handle),
 557                 i40e_dev_interrupt_handler, (void *)dev);
 558
 559         /* configure and enable device interrupt */
 560         i40e_pf_config_irq0(hw);
 561         i40e_pf_enable_irq0(hw);
 562
 563         /* enable uio intr after callback register */
 564         rte_intr_enable(&(pci_dev->intr_handle));
 565
 566         return 0;
 567
 568 err_mac_alloc:
 569         i40e_vsi_release(pf->main_vsi);
 570 err_setup_pf_switch:
 571 err_get_mac_addr:
 572 err_configure_lan_hmc:
 573         (void)i40e_shutdown_lan_hmc(hw);
 574 err_init_lan_hmc:
 575         i40e_res_pool_destroy(&pf->msix_pool);
 576 err_msix_pool_init:
 577         i40e_res_pool_destroy(&pf->qp_pool);
 578 err_qp_pool_init:
 579 err_parameter_init:
 580 err_get_capabilities:
 581         (void)i40e_shutdown_adminq(hw);
 582
 583         return ret;
 584 }
 585
 586 static int
 587 i40e_dev_configure(struct rte_eth_dev *dev)
 588 {
 589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 590         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 591         int ret;
 592
 593         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 594                 ret = i40e_fdir_setup(pf);
 595                 if (ret != I40E_SUCCESS) {
 596                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 597                         return -ENOTSUP;
 598                 }
 599                 ret = i40e_fdir_configure(dev);
 600                 if (ret < 0) {
 601                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 602                         goto err;
 603                 }
 604         } else
 605                 i40e_fdir_teardown(pf);
 606
 607         ret = i40e_dev_init_vlan(dev);
 608         if (ret < 0)
 609                 goto err;
 610
 611         /* VMDQ setup.
 612          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 613          *  RSS setting have different requirements.
 614          *  General PMD driver call sequence are NIC init, configure,
 615          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 616          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 617          *  applicable. So, VMDQ setting has to be done before
 618          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 619          *  For RSS setting, it will try to calculate actual configured RX queue
 620          *  number, which will be available after rx_queue_setup(). dev_start()
 621          *  function is good to place RSS setup.
 622          */
 623         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 624                 ret = i40e_vmdq_setup(dev);
 625                 if (ret)
 626                         goto err;
 627         }
 628         return 0;
 629 err:
 630         i40e_fdir_teardown(pf);
 631         return ret;
 632 }
 633
 634 void
 635 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 636 {
 637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 638         uint16_t msix_vect = vsi->msix_intr;
 639         uint16_t i;
 640
 641         for (i = 0; i < vsi->nb_qps; i++) {
 642                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 643                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 644                 rte_wmb();
 645         }
 646
 647         if (vsi->type != I40E_VSI_SRIOV) {
 648                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 649                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 650                                 msix_vect - 1), 0);
 651         } else {
 652                 uint32_t reg;
 653                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 654                         vsi->user_param + (msix_vect - 1);
 655
 656                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 657         }
 658         I40E_WRITE_FLUSH(hw);
 659 }
 660
 661 static inline uint16_t
 662 i40e_calc_itr_interval(int16_t interval)
 663 {
 664         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 665                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 666
 667         /* Convert to hardware count, as writing each 1 represents 2 us */
 668         return (interval/2);
 669 }
 670
 671 void
 672 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 673 {
 674         uint32_t val;
 675         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 676         uint16_t msix_vect = vsi->msix_intr;
 677         int i;
 678
 679         for (i = 0; i < vsi->nb_qps; i++)
 680                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 681
 682         /* Bind all RX queues to allocated MSIX interrupt */
 683         for (i = 0; i < vsi->nb_qps; i++) {
 684                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 685                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 686                         ((vsi->base_queue + i + 1) <<
 687                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 688                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 689                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 690
 691                 if (i == vsi->nb_qps - 1)
 692                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 693                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 694         }
 695
 696         /* Write first RX queue to Link list register as the head element */
 697         if (vsi->type != I40E_VSI_SRIOV) {
 698                 uint16_t interval =
 699                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 700
 701                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 702                                                 (vsi->base_queue <<
 703                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 704                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 705
 706                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 707                                                 msix_vect - 1), interval);
 708
 709 #ifndef I40E_GLINT_CTL
 710 #define I40E_GLINT_CTL                     0x0003F800
 711 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 712 #endif
 713                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 714                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 715                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 716         } else {
 717                 uint32_t reg;
 718
 719                 /* num_msix_vectors_vf needs to minus irq0 */
 720                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 721                         vsi->user_param + (msix_vect - 1);
 722
 723                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 724                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 725                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 726         }
 727
 728         I40E_WRITE_FLUSH(hw);
 729 }
 730
 731 static void
 732 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 733 {
 734         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 735         uint16_t interval = i40e_calc_itr_interval(\
 736                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 737
 738         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 739                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 740                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 741                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 742                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 743 }
 744
 745 static void
 746 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 747 {
 748         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 749
 750         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 751 }
 752
 753 static inline uint8_t
 754 i40e_parse_link_speed(uint16_t eth_link_speed)
 755 {
 756         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 757
 758         switch (eth_link_speed) {
 759         case ETH_LINK_SPEED_40G:
 760                 link_speed = I40E_LINK_SPEED_40GB;
 761                 break;
 762         case ETH_LINK_SPEED_20G:
 763                 link_speed = I40E_LINK_SPEED_20GB;
 764                 break;
 765         case ETH_LINK_SPEED_10G:
 766                 link_speed = I40E_LINK_SPEED_10GB;
 767                 break;
 768         case ETH_LINK_SPEED_1000:
 769                 link_speed = I40E_LINK_SPEED_1GB;
 770                 break;
 771         case ETH_LINK_SPEED_100:
 772                 link_speed = I40E_LINK_SPEED_100MB;
 773                 break;
 774         }
 775
 776         return link_speed;
 777 }
 778
 779 static int
 780 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 781 {
 782         enum i40e_status_code status;
 783         struct i40e_aq_get_phy_abilities_resp phy_ab;
 784         struct i40e_aq_set_phy_config phy_conf;
 785         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 786                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 787                         I40E_AQ_PHY_FLAG_LOW_POWER;
 788         const uint8_t advt = I40E_LINK_SPEED_40GB |
 789                         I40E_LINK_SPEED_10GB |
 790                         I40E_LINK_SPEED_1GB |
 791                         I40E_LINK_SPEED_100MB;
 792         int ret = -ENOTSUP;
 793
 794         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 795                                               NULL);
 796         if (status)
 797                 return ret;
 798
 799         memset(&phy_conf, 0, sizeof(phy_conf));
 800
 801         /* bits 0-2 use the values from get_phy_abilities_resp */
 802         abilities &= ~mask;
 803         abilities |= phy_ab.abilities & mask;
 804
 805         /* update ablities and speed */
 806         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 807                 phy_conf.link_speed = advt;
 808         else
 809                 phy_conf.link_speed = force_speed;
 810
 811         phy_conf.abilities = abilities;
 812
 813         /* use get_phy_abilities_resp value for the rest */
 814         phy_conf.phy_type = phy_ab.phy_type;
 815         phy_conf.eee_capability = phy_ab.eee_capability;
 816         phy_conf.eeer = phy_ab.eeer_val;
 817         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 818
 819         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 820                     phy_ab.abilities, phy_ab.link_speed);
 821         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 822                     phy_conf.abilities, phy_conf.link_speed);
 823
 824         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 825         if (status)
 826                 return ret;
 827
 828         return I40E_SUCCESS;
 829 }
 830
 831 static int
 832 i40e_apply_link_speed(struct rte_eth_dev *dev)
 833 {
 834         uint8_t speed;
 835         uint8_t abilities = 0;
 836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 837         struct rte_eth_conf *conf = &dev->data->dev_conf;
 838
 839         speed = i40e_parse_link_speed(conf->link_speed);
 840         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 841         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 842                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 843         else
 844                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 845
 846         return i40e_phy_conf_link(hw, abilities, speed);
 847 }
 848
 849 static int
 850 i40e_dev_start(struct rte_eth_dev *dev)
 851 {
 852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 853         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854         struct i40e_vsi *main_vsi = pf->main_vsi;
 855         int ret, i;
 856
 857         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 858                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 859                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 860                              dev->data->dev_conf.link_duplex,
 861                              dev->data->port_id);
 862                 return -EINVAL;
 863         }
 864
 865         /* Initialize VSI */
 866         ret = i40e_dev_rxtx_init(pf);
 867         if (ret != I40E_SUCCESS) {
 868                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 869                 goto err_up;
 870         }
 871
 872         /* Map queues with MSIX interrupt */
 873         i40e_vsi_queues_bind_intr(main_vsi);
 874         i40e_vsi_enable_queues_intr(main_vsi);
 875
 876         /* Map VMDQ VSI queues with MSIX interrupt */
 877         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 878                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 879                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 880         }
 881
 882         /* enable FDIR MSIX interrupt */
 883         if (pf->fdir.fdir_vsi) {
 884                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 885                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 886         }
 887
 888         /* Enable all queues which have been configured */
 889         ret = i40e_dev_switch_queues(pf, TRUE);
 890         if (ret != I40E_SUCCESS) {
 891                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 892                 goto err_up;
 893         }
 894
 895         /* Enable receiving broadcast packets */
 896         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 897         if (ret != I40E_SUCCESS)
 898                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 899
 900         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 901                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 902                                                 true, NULL);
 903                 if (ret != I40E_SUCCESS)
 904                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 905         }
 906
 907         /* Apply link configure */
 908         ret = i40e_apply_link_speed(dev);
 909         if (I40E_SUCCESS != ret) {
 910                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 911                 goto err_up;
 912         }
 913
 914         return I40E_SUCCESS;
 915
 916 err_up:
 917         i40e_dev_switch_queues(pf, FALSE);
 918         i40e_dev_clear_queues(dev);
 919
 920         return ret;
 921 }
 922
 923 static void
 924 i40e_dev_stop(struct rte_eth_dev *dev)
 925 {
 926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 927         struct i40e_vsi *main_vsi = pf->main_vsi;
 928         int i;
 929
 930         /* Disable all queues */
 931         i40e_dev_switch_queues(pf, FALSE);
 932
 933         /* un-map queues with interrupt registers */
 934         i40e_vsi_disable_queues_intr(main_vsi);
 935         i40e_vsi_queues_unbind_intr(main_vsi);
 936
 937         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 938                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 939                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 940         }
 941
 942         if (pf->fdir.fdir_vsi) {
 943                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 944                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 945         }
 946         /* Clear all queues and release memory */
 947         i40e_dev_clear_queues(dev);
 948
 949         /* Set link down */
 950         i40e_dev_set_link_down(dev);
 951
 952 }
 953
 954 static void
 955 i40e_dev_close(struct rte_eth_dev *dev)
 956 {
 957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 959         uint32_t reg;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         i40e_dev_stop(dev);
 964
 965         /* Disable interrupt */
 966         i40e_pf_disable_irq0(hw);
 967         rte_intr_disable(&(dev->pci_dev->intr_handle));
 968
 969         /* shutdown and destroy the HMC */
 970         i40e_shutdown_lan_hmc(hw);
 971
 972         /* release all the existing VSIs and VEBs */
 973         i40e_fdir_teardown(pf);
 974         i40e_vsi_release(pf->main_vsi);
 975
 976         /* shutdown the adminq */
 977         i40e_aq_queue_shutdown(hw, true);
 978         i40e_shutdown_adminq(hw);
 979
 980         i40e_res_pool_destroy(&pf->qp_pool);
 981         i40e_res_pool_destroy(&pf->msix_pool);
 982
 983         /* force a PF reset to clean anything leftover */
 984         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 985         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 986                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 987         I40E_WRITE_FLUSH(hw);
 988 }
 989
 990 static void
 991 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 992 {
 993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 994         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 995         struct i40e_vsi *vsi = pf->main_vsi;
 996         int status;
 997
 998         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 999                                                         true, NULL);
1000         if (status != I40E_SUCCESS)
1001                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1002
1003         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1004                                                         TRUE, NULL);
1005         if (status != I40E_SUCCESS)
1006                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1007
1008 }
1009
1010 static void
1011 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1012 {
1013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015         struct i40e_vsi *vsi = pf->main_vsi;
1016         int status;
1017
1018         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1019                                                         false, NULL);
1020         if (status != I40E_SUCCESS)
1021                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1022
1023         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1024                                                         false, NULL);
1025         if (status != I40E_SUCCESS)
1026                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1027 }
1028
1029 static void
1030 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1031 {
1032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034         struct i40e_vsi *vsi = pf->main_vsi;
1035         int ret;
1036
1037         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1038         if (ret != I40E_SUCCESS)
1039                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1040 }
1041
1042 static void
1043 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1044 {
1045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047         struct i40e_vsi *vsi = pf->main_vsi;
1048         int ret;
1049
1050         if (dev->data->promiscuous == 1)
1051                 return; /* must remain in all_multicast mode */
1052
1053         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1054                                 vsi->seid, FALSE, NULL);
1055         if (ret != I40E_SUCCESS)
1056                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1057 }
1058
1059 /*
1060  * Set device link up.
1061  */
1062 static int
1063 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1064 {
1065         /* re-apply link speed setting */
1066         return i40e_apply_link_speed(dev);
1067 }
1068
1069 /*
1070  * Set device link down.
1071  */
1072 static int
1073 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1074 {
1075         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1076         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1078
1079         return i40e_phy_conf_link(hw, abilities, speed);
1080 }
1081
1082 int
1083 i40e_dev_link_update(struct rte_eth_dev *dev,
1084                      __rte_unused int wait_to_complete)
1085 {
1086         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         struct i40e_link_status link_status;
1088         struct rte_eth_link link, old;
1089         int status;
1090
1091         memset(&link, 0, sizeof(link));
1092         memset(&old, 0, sizeof(old));
1093         memset(&link_status, 0, sizeof(link_status));
1094         rte_i40e_dev_atomic_read_link_status(dev, &old);
1095
1096         /* Get link status information from hardware */
1097         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1098         if (status != I40E_SUCCESS) {
1099                 link.link_speed = ETH_LINK_SPEED_100;
1100                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1101                 PMD_DRV_LOG(ERR, "Failed to get link info");
1102                 goto out;
1103         }
1104
1105         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1106
1107         if (!link.link_status)
1108                 goto out;
1109
1110         /* i40e uses full duplex only */
1111         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1112
1113         /* Parse the link status */
1114         switch (link_status.link_speed) {
1115         case I40E_LINK_SPEED_100MB:
1116                 link.link_speed = ETH_LINK_SPEED_100;
1117                 break;
1118         case I40E_LINK_SPEED_1GB:
1119                 link.link_speed = ETH_LINK_SPEED_1000;
1120                 break;
1121         case I40E_LINK_SPEED_10GB:
1122                 link.link_speed = ETH_LINK_SPEED_10G;
1123                 break;
1124         case I40E_LINK_SPEED_20GB:
1125                 link.link_speed = ETH_LINK_SPEED_20G;
1126                 break;
1127         case I40E_LINK_SPEED_40GB:
1128                 link.link_speed = ETH_LINK_SPEED_40G;
1129                 break;
1130         default:
1131                 link.link_speed = ETH_LINK_SPEED_100;
1132                 break;
1133         }
1134
1135 out:
1136         rte_i40e_dev_atomic_write_link_status(dev, &link);
1137         if (link.link_status == old.link_status)
1138                 return -1;
1139
1140         return 0;
1141 }
1142
1143 /* Get all the statistics of a VSI */
1144 void
1145 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1146 {
1147         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1148         struct i40e_eth_stats *nes = &vsi->eth_stats;
1149         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1150         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1151
1152         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1153                             vsi->offset_loaded, &oes->rx_bytes,
1154                             &nes->rx_bytes);
1155         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1156                             vsi->offset_loaded, &oes->rx_unicast,
1157                             &nes->rx_unicast);
1158         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1159                             vsi->offset_loaded, &oes->rx_multicast,
1160                             &nes->rx_multicast);
1161         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1162                             vsi->offset_loaded, &oes->rx_broadcast,
1163                             &nes->rx_broadcast);
1164         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1165                             &oes->rx_discards, &nes->rx_discards);
1166         /* GLV_REPC not supported */
1167         /* GLV_RMPC not supported */
1168         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1169                             &oes->rx_unknown_protocol,
1170                             &nes->rx_unknown_protocol);
1171         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1172                             vsi->offset_loaded, &oes->tx_bytes,
1173                             &nes->tx_bytes);
1174         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1175                             vsi->offset_loaded, &oes->tx_unicast,
1176                             &nes->tx_unicast);
1177         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1178                             vsi->offset_loaded, &oes->tx_multicast,
1179                             &nes->tx_multicast);
1180         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1181                             vsi->offset_loaded,  &oes->tx_broadcast,
1182                             &nes->tx_broadcast);
1183         /* GLV_TDPC not supported */
1184         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1185                             &oes->tx_errors, &nes->tx_errors);
1186         vsi->offset_loaded = true;
1187
1188         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1189                     vsi->vsi_id);
1190         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1191         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1192         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1193         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1194         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1195         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1196                     nes->rx_unknown_protocol);
1197         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1198         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1199         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1200         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1201         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1202         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1203         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1204                     vsi->vsi_id);
1205 }
1206
1207 /* Get all statistics of a port */
1208 static void
1209 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1210 {
1211         uint32_t i;
1212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1215         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1216
1217         /* Get statistics of struct i40e_eth_stats */
1218         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1219                             I40E_GLPRT_GORCL(hw->port),
1220                             pf->offset_loaded, &os->eth.rx_bytes,
1221                             &ns->eth.rx_bytes);
1222         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1223                             I40E_GLPRT_UPRCL(hw->port),
1224                             pf->offset_loaded, &os->eth.rx_unicast,
1225                             &ns->eth.rx_unicast);
1226         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1227                             I40E_GLPRT_MPRCL(hw->port),
1228                             pf->offset_loaded, &os->eth.rx_multicast,
1229                             &ns->eth.rx_multicast);
1230         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1231                             I40E_GLPRT_BPRCL(hw->port),
1232                             pf->offset_loaded, &os->eth.rx_broadcast,
1233                             &ns->eth.rx_broadcast);
1234         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1235                             pf->offset_loaded, &os->eth.rx_discards,
1236                             &ns->eth.rx_discards);
1237         /* GLPRT_REPC not supported */
1238         /* GLPRT_RMPC not supported */
1239         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1240                             pf->offset_loaded,
1241                             &os->eth.rx_unknown_protocol,
1242                             &ns->eth.rx_unknown_protocol);
1243         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1244                             I40E_GLPRT_GOTCL(hw->port),
1245                             pf->offset_loaded, &os->eth.tx_bytes,
1246                             &ns->eth.tx_bytes);
1247         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1248                             I40E_GLPRT_UPTCL(hw->port),
1249                             pf->offset_loaded, &os->eth.tx_unicast,
1250                             &ns->eth.tx_unicast);
1251         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1252                             I40E_GLPRT_MPTCL(hw->port),
1253                             pf->offset_loaded, &os->eth.tx_multicast,
1254                             &ns->eth.tx_multicast);
1255         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1256                             I40E_GLPRT_BPTCL(hw->port),
1257                             pf->offset_loaded, &os->eth.tx_broadcast,
1258                             &ns->eth.tx_broadcast);
1259         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1260                             pf->offset_loaded, &os->eth.tx_discards,
1261                             &ns->eth.tx_discards);
1262         /* GLPRT_TEPC not supported */
1263
1264         /* additional port specific stats */
1265         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1266                             pf->offset_loaded, &os->tx_dropped_link_down,
1267                             &ns->tx_dropped_link_down);
1268         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1269                             pf->offset_loaded, &os->crc_errors,
1270                             &ns->crc_errors);
1271         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1272                             pf->offset_loaded, &os->illegal_bytes,
1273                             &ns->illegal_bytes);
1274         /* GLPRT_ERRBC not supported */
1275         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1276                             pf->offset_loaded, &os->mac_local_faults,
1277                             &ns->mac_local_faults);
1278         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1279                             pf->offset_loaded, &os->mac_remote_faults,
1280                             &ns->mac_remote_faults);
1281         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1282                             pf->offset_loaded, &os->rx_length_errors,
1283                             &ns->rx_length_errors);
1284         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1285                             pf->offset_loaded, &os->link_xon_rx,
1286                             &ns->link_xon_rx);
1287         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1288                             pf->offset_loaded, &os->link_xoff_rx,
1289                             &ns->link_xoff_rx);
1290         for (i = 0; i < 8; i++) {
1291                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1292                                     pf->offset_loaded,
1293                                     &os->priority_xon_rx[i],
1294                                     &ns->priority_xon_rx[i]);
1295                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1296                                     pf->offset_loaded,
1297                                     &os->priority_xoff_rx[i],
1298                                     &ns->priority_xoff_rx[i]);
1299         }
1300         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1301                             pf->offset_loaded, &os->link_xon_tx,
1302                             &ns->link_xon_tx);
1303         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1304                             pf->offset_loaded, &os->link_xoff_tx,
1305                             &ns->link_xoff_tx);
1306         for (i = 0; i < 8; i++) {
1307                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1308                                     pf->offset_loaded,
1309                                     &os->priority_xon_tx[i],
1310                                     &ns->priority_xon_tx[i]);
1311                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1312                                     pf->offset_loaded,
1313                                     &os->priority_xoff_tx[i],
1314                                     &ns->priority_xoff_tx[i]);
1315                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1316                                     pf->offset_loaded,
1317                                     &os->priority_xon_2_xoff[i],
1318                                     &ns->priority_xon_2_xoff[i]);
1319         }
1320         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1321                             I40E_GLPRT_PRC64L(hw->port),
1322                             pf->offset_loaded, &os->rx_size_64,
1323                             &ns->rx_size_64);
1324         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1325                             I40E_GLPRT_PRC127L(hw->port),
1326                             pf->offset_loaded, &os->rx_size_127,
1327                             &ns->rx_size_127);
1328         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1329                             I40E_GLPRT_PRC255L(hw->port),
1330                             pf->offset_loaded, &os->rx_size_255,
1331                             &ns->rx_size_255);
1332         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1333                             I40E_GLPRT_PRC511L(hw->port),
1334                             pf->offset_loaded, &os->rx_size_511,
1335                             &ns->rx_size_511);
1336         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1337                             I40E_GLPRT_PRC1023L(hw->port),
1338                             pf->offset_loaded, &os->rx_size_1023,
1339                             &ns->rx_size_1023);
1340         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1341                             I40E_GLPRT_PRC1522L(hw->port),
1342                             pf->offset_loaded, &os->rx_size_1522,
1343                             &ns->rx_size_1522);
1344         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1345                             I40E_GLPRT_PRC9522L(hw->port),
1346                             pf->offset_loaded, &os->rx_size_big,
1347                             &ns->rx_size_big);
1348         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1349                             pf->offset_loaded, &os->rx_undersize,
1350                             &ns->rx_undersize);
1351         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1352                             pf->offset_loaded, &os->rx_fragments,
1353                             &ns->rx_fragments);
1354         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1355                             pf->offset_loaded, &os->rx_oversize,
1356                             &ns->rx_oversize);
1357         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1358                             pf->offset_loaded, &os->rx_jabber,
1359                             &ns->rx_jabber);
1360         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1361                             I40E_GLPRT_PTC64L(hw->port),
1362                             pf->offset_loaded, &os->tx_size_64,
1363                             &ns->tx_size_64);
1364         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1365                             I40E_GLPRT_PTC127L(hw->port),
1366                             pf->offset_loaded, &os->tx_size_127,
1367                             &ns->tx_size_127);
1368         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1369                             I40E_GLPRT_PTC255L(hw->port),
1370                             pf->offset_loaded, &os->tx_size_255,
1371                             &ns->tx_size_255);
1372         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1373                             I40E_GLPRT_PTC511L(hw->port),
1374                             pf->offset_loaded, &os->tx_size_511,
1375                             &ns->tx_size_511);
1376         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1377                             I40E_GLPRT_PTC1023L(hw->port),
1378                             pf->offset_loaded, &os->tx_size_1023,
1379                             &ns->tx_size_1023);
1380         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1381                             I40E_GLPRT_PTC1522L(hw->port),
1382                             pf->offset_loaded, &os->tx_size_1522,
1383                             &ns->tx_size_1522);
1384         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1385                             I40E_GLPRT_PTC9522L(hw->port),
1386                             pf->offset_loaded, &os->tx_size_big,
1387                             &ns->tx_size_big);
1388         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1389                            pf->offset_loaded,
1390                            &os->fd_sb_match, &ns->fd_sb_match);
1391         /* GLPRT_MSPDC not supported */
1392         /* GLPRT_XEC not supported */
1393
1394         pf->offset_loaded = true;
1395
1396         if (pf->main_vsi)
1397                 i40e_update_vsi_stats(pf->main_vsi);
1398
1399         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1400                                                 ns->eth.rx_broadcast;
1401         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1402                                                 ns->eth.tx_broadcast;
1403         stats->ibytes   = ns->eth.rx_bytes;
1404         stats->obytes   = ns->eth.tx_bytes;
1405         stats->oerrors  = ns->eth.tx_errors;
1406         stats->imcasts  = ns->eth.rx_multicast;
1407         stats->fdirmatch = ns->fd_sb_match;
1408
1409         /* Rx Errors */
1410         stats->ibadcrc  = ns->crc_errors;
1411         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1412                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1413         stats->imissed  = ns->eth.rx_discards;
1414         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1415
1416         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1417         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1418         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1419         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1420         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1421         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1422         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1423                     ns->eth.rx_unknown_protocol);
1424         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1425         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1426         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1427         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1428         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1429         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1430
1431         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1432                     ns->tx_dropped_link_down);
1433         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1434         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1435                     ns->illegal_bytes);
1436         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1437         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1438                     ns->mac_local_faults);
1439         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1440                     ns->mac_remote_faults);
1441         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1442                     ns->rx_length_errors);
1443         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1444         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1445         for (i = 0; i < 8; i++) {
1446                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1447                                 i, ns->priority_xon_rx[i]);
1448                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1449                                 i, ns->priority_xoff_rx[i]);
1450         }
1451         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1452         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1453         for (i = 0; i < 8; i++) {
1454                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1455                                 i, ns->priority_xon_tx[i]);
1456                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1457                                 i, ns->priority_xoff_tx[i]);
1458                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1459                                 i, ns->priority_xon_2_xoff[i]);
1460         }
1461         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1462         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1463         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1464         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1465         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1466         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1467         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1468         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1469         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1470         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1471         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1472         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1473         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1474         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1475         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1476         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1477         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1478         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1479         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1480                         ns->mac_short_packet_dropped);
1481         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1482                     ns->checksum_error);
1483         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1484         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1485 }
1486
1487 /* Reset the statistics */
1488 static void
1489 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1490 {
1491         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1492
1493         /* It results in reloading the start point of each counter */
1494         pf->offset_loaded = false;
1495 }
1496
1497 static int
1498 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1499                                  __rte_unused uint16_t queue_id,
1500                                  __rte_unused uint8_t stat_idx,
1501                                  __rte_unused uint8_t is_rx)
1502 {
1503         PMD_INIT_FUNC_TRACE();
1504
1505         return -ENOSYS;
1506 }
1507
1508 static void
1509 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1510 {
1511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1512         struct i40e_vsi *vsi = pf->main_vsi;
1513
1514         dev_info->max_rx_queues = vsi->nb_qps;
1515         dev_info->max_tx_queues = vsi->nb_qps;
1516         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1517         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1518         dev_info->max_mac_addrs = vsi->max_macaddrs;
1519         dev_info->max_vfs = dev->pci_dev->max_vfs;
1520         dev_info->rx_offload_capa =
1521                 DEV_RX_OFFLOAD_VLAN_STRIP |
1522                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1523                 DEV_RX_OFFLOAD_UDP_CKSUM |
1524                 DEV_RX_OFFLOAD_TCP_CKSUM;
1525         dev_info->tx_offload_capa =
1526                 DEV_TX_OFFLOAD_VLAN_INSERT |
1527                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1528                 DEV_TX_OFFLOAD_UDP_CKSUM |
1529                 DEV_TX_OFFLOAD_TCP_CKSUM |
1530                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1531                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1532                 DEV_TX_OFFLOAD_TCP_TSO;
1533         dev_info->reta_size = pf->hash_lut_size;
1534         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1535
1536         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1537                 .rx_thresh = {
1538                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1539                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1540                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1541                 },
1542                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1543                 .rx_drop_en = 0,
1544         };
1545
1546         dev_info->default_txconf = (struct rte_eth_txconf) {
1547                 .tx_thresh = {
1548                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1549                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1550                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1551                 },
1552                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1553                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1554                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1555                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1556         };
1557
1558         if (pf->flags | I40E_FLAG_VMDQ) {
1559                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1560                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1561                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1562                                                 pf->max_nb_vmdq_vsi;
1563                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1564                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1565                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1566         }
1567 }
1568
1569 static int
1570 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1571 {
1572         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1573         struct i40e_vsi *vsi = pf->main_vsi;
1574         PMD_INIT_FUNC_TRACE();
1575
1576         if (on)
1577                 return i40e_vsi_add_vlan(vsi, vlan_id);
1578         else
1579                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1580 }
1581
1582 static void
1583 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1584                    __rte_unused uint16_t tpid)
1585 {
1586         PMD_INIT_FUNC_TRACE();
1587 }
1588
1589 static void
1590 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1591 {
1592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1593         struct i40e_vsi *vsi = pf->main_vsi;
1594
1595         if (mask & ETH_VLAN_STRIP_MASK) {
1596                 /* Enable or disable VLAN stripping */
1597                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1598                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1599                 else
1600                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1601         }
1602
1603         if (mask & ETH_VLAN_EXTEND_MASK) {
1604                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1605                         i40e_vsi_config_double_vlan(vsi, TRUE);
1606                 else
1607                         i40e_vsi_config_double_vlan(vsi, FALSE);
1608         }
1609 }
1610
1611 static void
1612 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1613                           __rte_unused uint16_t queue,
1614                           __rte_unused int on)
1615 {
1616         PMD_INIT_FUNC_TRACE();
1617 }
1618
1619 static int
1620 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1621 {
1622         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1623         struct i40e_vsi *vsi = pf->main_vsi;
1624         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1625         struct i40e_vsi_vlan_pvid_info info;
1626
1627         memset(&info, 0, sizeof(info));
1628         info.on = on;
1629         if (info.on)
1630                 info.config.pvid = pvid;
1631         else {
1632                 info.config.reject.tagged =
1633                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1634                 info.config.reject.untagged =
1635                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1636         }
1637
1638         return i40e_vsi_vlan_pvid_set(vsi, &info);
1639 }
1640
1641 static int
1642 i40e_dev_led_on(struct rte_eth_dev *dev)
1643 {
1644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         uint32_t mode = i40e_led_get(hw);
1646
1647         if (mode == 0)
1648                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1649
1650         return 0;
1651 }
1652
1653 static int
1654 i40e_dev_led_off(struct rte_eth_dev *dev)
1655 {
1656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         uint32_t mode = i40e_led_get(hw);
1658
1659         if (mode != 0)
1660                 i40e_led_set(hw, 0, false);
1661
1662         return 0;
1663 }
1664
1665 static int
1666 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1667                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1668 {
1669         PMD_INIT_FUNC_TRACE();
1670
1671         return -ENOSYS;
1672 }
1673
1674 static int
1675 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1676                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1677 {
1678         PMD_INIT_FUNC_TRACE();
1679
1680         return -ENOSYS;
1681 }
1682
1683 /* Add a MAC address, and update filters */
1684 static void
1685 i40e_macaddr_add(struct rte_eth_dev *dev,
1686                  struct ether_addr *mac_addr,
1687                  __rte_unused uint32_t index,
1688                  uint32_t pool)
1689 {
1690         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1691         struct i40e_mac_filter_info mac_filter;
1692         struct i40e_vsi *vsi;
1693         int ret;
1694
1695         /* If VMDQ not enabled or configured, return */
1696         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1697                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1698                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1699                         pool);
1700                 return;
1701         }
1702
1703         if (pool > pf->nb_cfg_vmdq_vsi) {
1704                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1705                                 pool, pf->nb_cfg_vmdq_vsi);
1706                 return;
1707         }
1708
1709         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1710         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1711
1712         if (pool == 0)
1713                 vsi = pf->main_vsi;
1714         else
1715                 vsi = pf->vmdq[pool - 1].vsi;
1716
1717         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1718         if (ret != I40E_SUCCESS) {
1719                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1720                 return;
1721         }
1722 }
1723
1724 /* Remove a MAC address, and update filters */
1725 static void
1726 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1727 {
1728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1729         struct i40e_vsi *vsi;
1730         struct rte_eth_dev_data *data = dev->data;
1731         struct ether_addr *macaddr;
1732         int ret;
1733         uint32_t i;
1734         uint64_t pool_sel;
1735
1736         macaddr = &(data->mac_addrs[index]);
1737
1738         pool_sel = dev->data->mac_pool_sel[index];
1739
1740         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1741                 if (pool_sel & (1ULL << i)) {
1742                         if (i == 0)
1743                                 vsi = pf->main_vsi;
1744                         else {
1745                                 /* No VMDQ pool enabled or configured */
1746                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1747                                         (i > pf->nb_cfg_vmdq_vsi)) {
1748                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1749                                                         "/configured");
1750                                         return;
1751                                 }
1752                                 vsi = pf->vmdq[i - 1].vsi;
1753                         }
1754                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1755
1756                         if (ret) {
1757                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1758                                 return;
1759                         }
1760                 }
1761         }
1762 }
1763
1764 /* Set perfect match or hash match of MAC and VLAN for a VF */
1765 static int
1766 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1767                  struct rte_eth_mac_filter *filter,
1768                  bool add)
1769 {
1770         struct i40e_hw *hw;
1771         struct i40e_mac_filter_info mac_filter;
1772         struct ether_addr old_mac;
1773         struct ether_addr *new_mac;
1774         struct i40e_pf_vf *vf = NULL;
1775         uint16_t vf_id;
1776         int ret;
1777
1778         if (pf == NULL) {
1779                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1780                 return -EINVAL;
1781         }
1782         hw = I40E_PF_TO_HW(pf);
1783
1784         if (filter == NULL) {
1785                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1786                 return -EINVAL;
1787         }
1788
1789         new_mac = &filter->mac_addr;
1790
1791         if (is_zero_ether_addr(new_mac)) {
1792                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1793                 return -EINVAL;
1794         }
1795
1796         vf_id = filter->dst_id;
1797
1798         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1799                 PMD_DRV_LOG(ERR, "Invalid argument.");
1800                 return -EINVAL;
1801         }
1802         vf = &pf->vfs[vf_id];
1803
1804         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1805                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1806                 return -EINVAL;
1807         }
1808
1809         if (add) {
1810                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1811                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1812                                 ETHER_ADDR_LEN);
1813                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1814                                  ETHER_ADDR_LEN);
1815
1816                 mac_filter.filter_type = filter->filter_type;
1817                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1818                 if (ret != I40E_SUCCESS) {
1819                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1820                         return -1;
1821                 }
1822                 ether_addr_copy(new_mac, &pf->dev_addr);
1823         } else {
1824                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1825                                 ETHER_ADDR_LEN);
1826                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1827                 if (ret != I40E_SUCCESS) {
1828                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1829                         return -1;
1830                 }
1831
1832                 /* Clear device address as it has been removed */
1833                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1834                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1835         }
1836
1837         return 0;
1838 }
1839
1840 /* MAC filter handle */
1841 static int
1842 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1843                 void *arg)
1844 {
1845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1846         struct rte_eth_mac_filter *filter;
1847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1848         int ret = I40E_NOT_SUPPORTED;
1849
1850         filter = (struct rte_eth_mac_filter *)(arg);
1851
1852         switch (filter_op) {
1853         case RTE_ETH_FILTER_NOP:
1854                 ret = I40E_SUCCESS;
1855                 break;
1856         case RTE_ETH_FILTER_ADD:
1857                 i40e_pf_disable_irq0(hw);
1858                 if (filter->is_vf)
1859                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1860                 i40e_pf_enable_irq0(hw);
1861                 break;
1862         case RTE_ETH_FILTER_DELETE:
1863                 i40e_pf_disable_irq0(hw);
1864                 if (filter->is_vf)
1865                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1866                 i40e_pf_enable_irq0(hw);
1867                 break;
1868         default:
1869                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1870                 ret = I40E_ERR_PARAM;
1871                 break;
1872         }
1873
1874         return ret;
1875 }
1876
1877 static int
1878 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1879                          struct rte_eth_rss_reta_entry64 *reta_conf,
1880                          uint16_t reta_size)
1881 {
1882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884         uint32_t lut, l;
1885         uint16_t i, j, lut_size = pf->hash_lut_size;
1886         uint16_t idx, shift;
1887         uint8_t mask;
1888
1889         if (reta_size != lut_size ||
1890                 reta_size > ETH_RSS_RETA_SIZE_512) {
1891                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1892                         "(%d) doesn't match the number hardware can supported "
1893                                         "(%d)\n", reta_size, lut_size);
1894                 return -EINVAL;
1895         }
1896
1897         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1898                 idx = i / RTE_RETA_GROUP_SIZE;
1899                 shift = i % RTE_RETA_GROUP_SIZE;
1900                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1901                                                 I40E_4_BIT_MASK);
1902                 if (!mask)
1903                         continue;
1904                 if (mask == I40E_4_BIT_MASK)
1905                         l = 0;
1906                 else
1907                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1908                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1909                         if (mask & (0x1 << j))
1910                                 lut |= reta_conf[idx].reta[shift + j] <<
1911                                                         (CHAR_BIT * j);
1912                         else
1913                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1914                 }
1915                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int
1922 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1923                         struct rte_eth_rss_reta_entry64 *reta_conf,
1924                         uint16_t reta_size)
1925 {
1926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         uint32_t lut;
1929         uint16_t i, j, lut_size = pf->hash_lut_size;
1930         uint16_t idx, shift;
1931         uint8_t mask;
1932
1933         if (reta_size != lut_size ||
1934                 reta_size > ETH_RSS_RETA_SIZE_512) {
1935                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1936                         "(%d) doesn't match the number hardware can supported "
1937                                         "(%d)\n", reta_size, lut_size);
1938                 return -EINVAL;
1939         }
1940
1941         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1942                 idx = i / RTE_RETA_GROUP_SIZE;
1943                 shift = i % RTE_RETA_GROUP_SIZE;
1944                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1945                                                 I40E_4_BIT_MASK);
1946                 if (!mask)
1947                         continue;
1948
1949                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1950                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1951                         if (mask & (0x1 << j))
1952                                 reta_conf[idx].reta[shift + j] = ((lut >>
1953                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1954                 }
1955         }
1956
1957         return 0;
1958 }
1959
1960 /**
1961  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1962  * @hw:   pointer to the HW structure
1963  * @mem:  pointer to mem struct to fill out
1964  * @size: size of memory requested
1965  * @alignment: what to align the allocation to
1966  **/
1967 enum i40e_status_code
1968 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1969                         struct i40e_dma_mem *mem,
1970                         u64 size,
1971                         u32 alignment)
1972 {
1973         static uint64_t id = 0;
1974         const struct rte_memzone *mz = NULL;
1975         char z_name[RTE_MEMZONE_NAMESIZE];
1976
1977         if (!mem)
1978                 return I40E_ERR_PARAM;
1979
1980         id++;
1981         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1982 #ifdef RTE_LIBRTE_XEN_DOM0
1983         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1984                                                         RTE_PGSIZE_2M);
1985 #else
1986         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1987 #endif
1988         if (!mz)
1989                 return I40E_ERR_NO_MEMORY;
1990
1991         mem->id = id;
1992         mem->size = size;
1993         mem->va = mz->addr;
1994 #ifdef RTE_LIBRTE_XEN_DOM0
1995         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1996 #else
1997         mem->pa = mz->phys_addr;
1998 #endif
1999
2000         return I40E_SUCCESS;
2001 }
2002
2003 /**
2004  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2005  * @hw:   pointer to the HW structure
2006  * @mem:  ptr to mem struct to free
2007  **/
2008 enum i40e_status_code
2009 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2010                     struct i40e_dma_mem *mem)
2011 {
2012         if (!mem || !mem->va)
2013                 return I40E_ERR_PARAM;
2014
2015         mem->va = NULL;
2016         mem->pa = (u64)0;
2017
2018         return I40E_SUCCESS;
2019 }
2020
2021 /**
2022  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2023  * @hw:   pointer to the HW structure
2024  * @mem:  pointer to mem struct to fill out
2025  * @size: size of memory requested
2026  **/
2027 enum i40e_status_code
2028 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2029                          struct i40e_virt_mem *mem,
2030                          u32 size)
2031 {
2032         if (!mem)
2033                 return I40E_ERR_PARAM;
2034
2035         mem->size = size;
2036         mem->va = rte_zmalloc("i40e", size, 0);
2037
2038         if (mem->va)
2039                 return I40E_SUCCESS;
2040         else
2041                 return I40E_ERR_NO_MEMORY;
2042 }
2043
2044 /**
2045  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2046  * @hw:   pointer to the HW structure
2047  * @mem:  pointer to mem struct to free
2048  **/
2049 enum i40e_status_code
2050 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2051                      struct i40e_virt_mem *mem)
2052 {
2053         if (!mem)
2054                 return I40E_ERR_PARAM;
2055
2056         rte_free(mem->va);
2057         mem->va = NULL;
2058
2059         return I40E_SUCCESS;
2060 }
2061
2062 void
2063 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2064 {
2065         rte_spinlock_init(&sp->spinlock);
2066 }
2067
2068 void
2069 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2070 {
2071         rte_spinlock_lock(&sp->spinlock);
2072 }
2073
2074 void
2075 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2076 {
2077         rte_spinlock_unlock(&sp->spinlock);
2078 }
2079
2080 void
2081 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2082 {
2083         return;
2084 }
2085
2086 /**
2087  * Get the hardware capabilities, which will be parsed
2088  * and saved into struct i40e_hw.
2089  */
2090 static int
2091 i40e_get_cap(struct i40e_hw *hw)
2092 {
2093         struct i40e_aqc_list_capabilities_element_resp *buf;
2094         uint16_t len, size = 0;
2095         int ret;
2096
2097         /* Calculate a huge enough buff for saving response data temporarily */
2098         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2099                                                 I40E_MAX_CAP_ELE_NUM;
2100         buf = rte_zmalloc("i40e", len, 0);
2101         if (!buf) {
2102                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2103                 return I40E_ERR_NO_MEMORY;
2104         }
2105
2106         /* Get, parse the capabilities and save it to hw */
2107         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2108                         i40e_aqc_opc_list_func_capabilities, NULL);
2109         if (ret != I40E_SUCCESS)
2110                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2111
2112         /* Free the temporary buffer after being used */
2113         rte_free(buf);
2114
2115         return ret;
2116 }
2117
2118 static int
2119 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2120 {
2121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2122         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2123         uint16_t sum_queues = 0, sum_vsis, left_queues;
2124
2125         /* First check if FW support SRIOV */
2126         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2127                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2128                 return -EINVAL;
2129         }
2130
2131         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2132         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2133         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2134         /* Allocate queues for pf */
2135         if (hw->func_caps.rss) {
2136                 pf->flags |= I40E_FLAG_RSS;
2137                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2138                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2139                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2140         } else
2141                 pf->lan_nb_qps = 1;
2142         sum_queues = pf->lan_nb_qps;
2143         /* Default VSI is not counted in */
2144         sum_vsis = 0;
2145         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2146
2147         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2148                 pf->flags |= I40E_FLAG_SRIOV;
2149                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2150                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2151                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2152                                      "max supported %u.",
2153                                      dev->pci_dev->max_vfs,
2154                                      hw->func_caps.num_vfs);
2155                         return -EINVAL;
2156                 }
2157                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2158                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2159                                      "max support %u queues.",
2160                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2161                         return -EINVAL;
2162                 }
2163                 pf->vf_num = dev->pci_dev->max_vfs;
2164                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2165                 sum_vsis   += pf->vf_num;
2166                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2167                              pf->vf_num, pf->vf_nb_qps);
2168         } else
2169                 pf->vf_num = 0;
2170
2171         if (hw->func_caps.vmdq) {
2172                 pf->flags |= I40E_FLAG_VMDQ;
2173                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2174                 pf->max_nb_vmdq_vsi = 1;
2175                 /*
2176                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2177                  * later.
2178                  */
2179                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2180                 sum_vsis += pf->max_nb_vmdq_vsi;
2181         } else {
2182                 pf->vmdq_nb_qps = 0;
2183                 pf->max_nb_vmdq_vsi = 0;
2184         }
2185         pf->nb_cfg_vmdq_vsi = 0;
2186
2187         if (hw->func_caps.fd) {
2188                 pf->flags |= I40E_FLAG_FDIR;
2189                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2190                 /**
2191                  * Each flow director consumes one VSI and one queue,
2192                  * but can't calculate out predictably here.
2193                  */
2194         }
2195
2196         if (sum_vsis > pf->max_num_vsi ||
2197                 sum_queues > hw->func_caps.num_rx_qp) {
2198                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2199                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2200                              pf->max_num_vsi, sum_vsis);
2201                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2202                              hw->func_caps.num_rx_qp, sum_queues);
2203                 return -EINVAL;
2204         }
2205
2206         /* Adjust VMDQ setting to support as many VMs as possible */
2207         if (pf->flags & I40E_FLAG_VMDQ) {
2208                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2209
2210                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2211                                         pf->max_num_vsi - sum_vsis);
2212
2213                 /* Limit the max VMDQ number that rte_ether that can support  */
2214                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2215                                         ETH_64_POOLS - 1);
2216
2217                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2218                                 pf->max_nb_vmdq_vsi);
2219                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2220         }
2221
2222         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2223          * cause */
2224         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2225                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2226                              sum_vsis, hw->func_caps.num_msix_vectors);
2227                 return -EINVAL;
2228         }
2229         return I40E_SUCCESS;
2230 }
2231
2232 static int
2233 i40e_pf_get_switch_config(struct i40e_pf *pf)
2234 {
2235         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2236         struct i40e_aqc_get_switch_config_resp *switch_config;
2237         struct i40e_aqc_switch_config_element_resp *element;
2238         uint16_t start_seid = 0, num_reported;
2239         int ret;
2240
2241         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2242                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2243         if (!switch_config) {
2244                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2245                 return -ENOMEM;
2246         }
2247
2248         /* Get the switch configurations */
2249         ret = i40e_aq_get_switch_config(hw, switch_config,
2250                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2251         if (ret != I40E_SUCCESS) {
2252                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2253                 goto fail;
2254         }
2255         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2256         if (num_reported != 1) { /* The number should be 1 */
2257                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2258                 goto fail;
2259         }
2260
2261         /* Parse the switch configuration elements */
2262         element = &(switch_config->element[0]);
2263         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2264                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2265                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2266         } else
2267                 PMD_DRV_LOG(INFO, "Unknown element type");
2268
2269 fail:
2270         rte_free(switch_config);
2271
2272         return ret;
2273 }
2274
2275 static int
2276 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2277                         uint32_t num)
2278 {
2279         struct pool_entry *entry;
2280
2281         if (pool == NULL || num == 0)
2282                 return -EINVAL;
2283
2284         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2285         if (entry == NULL) {
2286                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2287                 return -ENOMEM;
2288         }
2289
2290         /* queue heap initialize */
2291         pool->num_free = num;
2292         pool->num_alloc = 0;
2293         pool->base = base;
2294         LIST_INIT(&pool->alloc_list);
2295         LIST_INIT(&pool->free_list);
2296
2297         /* Initialize element  */
2298         entry->base = 0;
2299         entry->len = num;
2300
2301         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2302         return 0;
2303 }
2304
2305 static void
2306 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2307 {
2308         struct pool_entry *entry;
2309
2310         if (pool == NULL)
2311                 return;
2312
2313         LIST_FOREACH(entry, &pool->alloc_list, next) {
2314                 LIST_REMOVE(entry, next);
2315                 rte_free(entry);
2316         }
2317
2318         LIST_FOREACH(entry, &pool->free_list, next) {
2319                 LIST_REMOVE(entry, next);
2320                 rte_free(entry);
2321         }
2322
2323         pool->num_free = 0;
2324         pool->num_alloc = 0;
2325         pool->base = 0;
2326         LIST_INIT(&pool->alloc_list);
2327         LIST_INIT(&pool->free_list);
2328 }
2329
2330 static int
2331 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2332                        uint32_t base)
2333 {
2334         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2335         uint32_t pool_offset;
2336         int insert;
2337
2338         if (pool == NULL) {
2339                 PMD_DRV_LOG(ERR, "Invalid parameter");
2340                 return -EINVAL;
2341         }
2342
2343         pool_offset = base - pool->base;
2344         /* Lookup in alloc list */
2345         LIST_FOREACH(entry, &pool->alloc_list, next) {
2346                 if (entry->base == pool_offset) {
2347                         valid_entry = entry;
2348                         LIST_REMOVE(entry, next);
2349                         break;
2350                 }
2351         }
2352
2353         /* Not find, return */
2354         if (valid_entry == NULL) {
2355                 PMD_DRV_LOG(ERR, "Failed to find entry");
2356                 return -EINVAL;
2357         }
2358
2359         /**
2360          * Found it, move it to free list  and try to merge.
2361          * In order to make merge easier, always sort it by qbase.
2362          * Find adjacent prev and last entries.
2363          */
2364         prev = next = NULL;
2365         LIST_FOREACH(entry, &pool->free_list, next) {
2366                 if (entry->base > valid_entry->base) {
2367                         next = entry;
2368                         break;
2369                 }
2370                 prev = entry;
2371         }
2372
2373         insert = 0;
2374         /* Try to merge with next one*/
2375         if (next != NULL) {
2376                 /* Merge with next one */
2377                 if (valid_entry->base + valid_entry->len == next->base) {
2378                         next->base = valid_entry->base;
2379                         next->len += valid_entry->len;
2380                         rte_free(valid_entry);
2381                         valid_entry = next;
2382                         insert = 1;
2383                 }
2384         }
2385
2386         if (prev != NULL) {
2387                 /* Merge with previous one */
2388                 if (prev->base + prev->len == valid_entry->base) {
2389                         prev->len += valid_entry->len;
2390                         /* If it merge with next one, remove next node */
2391                         if (insert == 1) {
2392                                 LIST_REMOVE(valid_entry, next);
2393                                 rte_free(valid_entry);
2394                         } else {
2395                                 rte_free(valid_entry);
2396                                 insert = 1;
2397                         }
2398                 }
2399         }
2400
2401         /* Not find any entry to merge, insert */
2402         if (insert == 0) {
2403                 if (prev != NULL)
2404                         LIST_INSERT_AFTER(prev, valid_entry, next);
2405                 else if (next != NULL)
2406                         LIST_INSERT_BEFORE(next, valid_entry, next);
2407                 else /* It's empty list, insert to head */
2408                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2409         }
2410
2411         pool->num_free += valid_entry->len;
2412         pool->num_alloc -= valid_entry->len;
2413
2414         return 0;
2415 }
2416
2417 static int
2418 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2419                        uint16_t num)
2420 {
2421         struct pool_entry *entry, *valid_entry;
2422
2423         if (pool == NULL || num == 0) {
2424                 PMD_DRV_LOG(ERR, "Invalid parameter");
2425                 return -EINVAL;
2426         }
2427
2428         if (pool->num_free < num) {
2429                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2430                             num, pool->num_free);
2431                 return -ENOMEM;
2432         }
2433
2434         valid_entry = NULL;
2435         /* Lookup  in free list and find most fit one */
2436         LIST_FOREACH(entry, &pool->free_list, next) {
2437                 if (entry->len >= num) {
2438                         /* Find best one */
2439                         if (entry->len == num) {
2440                                 valid_entry = entry;
2441                                 break;
2442                         }
2443                         if (valid_entry == NULL || valid_entry->len > entry->len)
2444                                 valid_entry = entry;
2445                 }
2446         }
2447
2448         /* Not find one to satisfy the request, return */
2449         if (valid_entry == NULL) {
2450                 PMD_DRV_LOG(ERR, "No valid entry found");
2451                 return -ENOMEM;
2452         }
2453         /**
2454          * The entry have equal queue number as requested,
2455          * remove it from alloc_list.
2456          */
2457         if (valid_entry->len == num) {
2458                 LIST_REMOVE(valid_entry, next);
2459         } else {
2460                 /**
2461                  * The entry have more numbers than requested,
2462                  * create a new entry for alloc_list and minus its
2463                  * queue base and number in free_list.
2464                  */
2465                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2466                 if (entry == NULL) {
2467                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2468                                     "resource pool");
2469                         return -ENOMEM;
2470                 }
2471                 entry->base = valid_entry->base;
2472                 entry->len = num;
2473                 valid_entry->base += num;
2474                 valid_entry->len -= num;
2475                 valid_entry = entry;
2476         }
2477
2478         /* Insert it into alloc list, not sorted */
2479         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2480
2481         pool->num_free -= valid_entry->len;
2482         pool->num_alloc += valid_entry->len;
2483
2484         return (valid_entry->base + pool->base);
2485 }
2486
2487 /**
2488  * bitmap_is_subset - Check whether src2 is subset of src1
2489  **/
2490 static inline int
2491 bitmap_is_subset(uint8_t src1, uint8_t src2)
2492 {
2493         return !((src1 ^ src2) & src2);
2494 }
2495
2496 static int
2497 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2498 {
2499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2500
2501         /* If DCB is not supported, only default TC is supported */
2502         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2503                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2504                 return -EINVAL;
2505         }
2506
2507         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2508                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2509                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2510                             enabled_tcmap);
2511                 return -EINVAL;
2512         }
2513         return I40E_SUCCESS;
2514 }
2515
2516 int
2517 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2518                                 struct i40e_vsi_vlan_pvid_info *info)
2519 {
2520         struct i40e_hw *hw;
2521         struct i40e_vsi_context ctxt;
2522         uint8_t vlan_flags = 0;
2523         int ret;
2524
2525         if (vsi == NULL || info == NULL) {
2526                 PMD_DRV_LOG(ERR, "invalid parameters");
2527                 return I40E_ERR_PARAM;
2528         }
2529
2530         if (info->on) {
2531                 vsi->info.pvid = info->config.pvid;
2532                 /**
2533                  * If insert pvid is enabled, only tagged pkts are
2534                  * allowed to be sent out.
2535                  */
2536                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2537                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2538         } else {
2539                 vsi->info.pvid = 0;
2540                 if (info->config.reject.tagged == 0)
2541                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2542
2543                 if (info->config.reject.untagged == 0)
2544                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2545         }
2546         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2547                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2548         vsi->info.port_vlan_flags |= vlan_flags;
2549         vsi->info.valid_sections =
2550                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2551         memset(&ctxt, 0, sizeof(ctxt));
2552         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2553         ctxt.seid = vsi->seid;
2554
2555         hw = I40E_VSI_TO_HW(vsi);
2556         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2557         if (ret != I40E_SUCCESS)
2558                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2559
2560         return ret;
2561 }
2562
2563 static int
2564 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2565 {
2566         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2567         int i, ret;
2568         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2569
2570         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2571         if (ret != I40E_SUCCESS)
2572                 return ret;
2573
2574         if (!vsi->seid) {
2575                 PMD_DRV_LOG(ERR, "seid not valid");
2576                 return -EINVAL;
2577         }
2578
2579         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2580         tc_bw_data.tc_valid_bits = enabled_tcmap;
2581         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2582                 tc_bw_data.tc_bw_credits[i] =
2583                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2584
2585         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2586         if (ret != I40E_SUCCESS) {
2587                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2588                 return ret;
2589         }
2590
2591         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2592                                         sizeof(vsi->info.qs_handle));
2593         return I40E_SUCCESS;
2594 }
2595
2596 static int
2597 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2598                                  struct i40e_aqc_vsi_properties_data *info,
2599                                  uint8_t enabled_tcmap)
2600 {
2601         int ret, total_tc = 0, i;
2602         uint16_t qpnum_per_tc, bsf, qp_idx;
2603
2604         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2605         if (ret != I40E_SUCCESS)
2606                 return ret;
2607
2608         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2609                 if (enabled_tcmap & (1 << i))
2610                         total_tc++;
2611         vsi->enabled_tc = enabled_tcmap;
2612
2613         /* Number of queues per enabled TC */
2614         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2615         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2616         bsf = rte_bsf32(qpnum_per_tc);
2617
2618         /* Adjust the queue number to actual queues that can be applied */
2619         vsi->nb_qps = qpnum_per_tc * total_tc;
2620
2621         /**
2622          * Configure TC and queue mapping parameters, for enabled TC,
2623          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2624          * default queue will serve it.
2625          */
2626         qp_idx = 0;
2627         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2628                 if (vsi->enabled_tc & (1 << i)) {
2629                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2630                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2631                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2632                         qp_idx += qpnum_per_tc;
2633                 } else
2634                         info->tc_mapping[i] = 0;
2635         }
2636
2637         /* Associate queue number with VSI */
2638         if (vsi->type == I40E_VSI_SRIOV) {
2639                 info->mapping_flags |=
2640                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2641                 for (i = 0; i < vsi->nb_qps; i++)
2642                         info->queue_mapping[i] =
2643                                 rte_cpu_to_le_16(vsi->base_queue + i);
2644         } else {
2645                 info->mapping_flags |=
2646                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2647                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2648         }
2649         info->valid_sections |=
2650                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2651
2652         return I40E_SUCCESS;
2653 }
2654
2655 static int
2656 i40e_veb_release(struct i40e_veb *veb)
2657 {
2658         struct i40e_vsi *vsi;
2659         struct i40e_hw *hw;
2660
2661         if (veb == NULL || veb->associate_vsi == NULL)
2662                 return -EINVAL;
2663
2664         if (!TAILQ_EMPTY(&veb->head)) {
2665                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2666                 return -EACCES;
2667         }
2668
2669         vsi = veb->associate_vsi;
2670         hw = I40E_VSI_TO_HW(vsi);
2671
2672         vsi->uplink_seid = veb->uplink_seid;
2673         i40e_aq_delete_element(hw, veb->seid, NULL);
2674         rte_free(veb);
2675         vsi->veb = NULL;
2676         return I40E_SUCCESS;
2677 }
2678
2679 /* Setup a veb */
2680 static struct i40e_veb *
2681 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2682 {
2683         struct i40e_veb *veb;
2684         int ret;
2685         struct i40e_hw *hw;
2686
2687         if (NULL == pf || vsi == NULL) {
2688                 PMD_DRV_LOG(ERR, "veb setup failed, "
2689                             "associated VSI shouldn't null");
2690                 return NULL;
2691         }
2692         hw = I40E_PF_TO_HW(pf);
2693
2694         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2695         if (!veb) {
2696                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2697                 goto fail;
2698         }
2699
2700         veb->associate_vsi = vsi;
2701         TAILQ_INIT(&veb->head);
2702         veb->uplink_seid = vsi->uplink_seid;
2703
2704         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2705                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2706
2707         if (ret != I40E_SUCCESS) {
2708                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2709                             hw->aq.asq_last_status);
2710                 goto fail;
2711         }
2712
2713         /* get statistics index */
2714         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2715                                 &veb->stats_idx, NULL, NULL, NULL);
2716         if (ret != I40E_SUCCESS) {
2717                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2718                             hw->aq.asq_last_status);
2719                 goto fail;
2720         }
2721
2722         /* Get VEB bandwidth, to be implemented */
2723         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2724         vsi->uplink_seid = veb->seid;
2725
2726         return veb;
2727 fail:
2728         rte_free(veb);
2729         return NULL;
2730 }
2731
2732 int
2733 i40e_vsi_release(struct i40e_vsi *vsi)
2734 {
2735         struct i40e_pf *pf;
2736         struct i40e_hw *hw;
2737         struct i40e_vsi_list *vsi_list;
2738         int ret;
2739         struct i40e_mac_filter *f;
2740
2741         if (!vsi)
2742                 return I40E_SUCCESS;
2743
2744         pf = I40E_VSI_TO_PF(vsi);
2745         hw = I40E_VSI_TO_HW(vsi);
2746
2747         /* VSI has child to attach, release child first */
2748         if (vsi->veb) {
2749                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2750                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2751                                 return -1;
2752                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2753                 }
2754                 i40e_veb_release(vsi->veb);
2755         }
2756
2757         /* Remove all macvlan filters of the VSI */
2758         i40e_vsi_remove_all_macvlan_filter(vsi);
2759         TAILQ_FOREACH(f, &vsi->mac_list, next)
2760                 rte_free(f);
2761
2762         if (vsi->type != I40E_VSI_MAIN) {
2763                 /* Remove vsi from parent's sibling list */
2764                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2765                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2766                         return I40E_ERR_PARAM;
2767                 }
2768                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2769                                 &vsi->sib_vsi_list, list);
2770
2771                 /* Remove all switch element of the VSI */
2772                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2773                 if (ret != I40E_SUCCESS)
2774                         PMD_DRV_LOG(ERR, "Failed to delete element");
2775         }
2776         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2777
2778         if (vsi->type != I40E_VSI_SRIOV)
2779                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2780         rte_free(vsi);
2781
2782         return I40E_SUCCESS;
2783 }
2784
2785 static int
2786 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2787 {
2788         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2789         struct i40e_aqc_remove_macvlan_element_data def_filter;
2790         struct i40e_mac_filter_info filter;
2791         int ret;
2792
2793         if (vsi->type != I40E_VSI_MAIN)
2794                 return I40E_ERR_CONFIG;
2795         memset(&def_filter, 0, sizeof(def_filter));
2796         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2797                                         ETH_ADDR_LEN);
2798         def_filter.vlan_tag = 0;
2799         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2800                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2801         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2802         if (ret != I40E_SUCCESS) {
2803                 struct i40e_mac_filter *f;
2804                 struct ether_addr *mac;
2805
2806                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2807                             "macvlan filter");
2808                 /* It needs to add the permanent mac into mac list */
2809                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2810                 if (f == NULL) {
2811                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2812                         return I40E_ERR_NO_MEMORY;
2813                 }
2814                 mac = &f->mac_info.mac_addr;
2815                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2816                                 ETH_ADDR_LEN);
2817                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2818                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2819                 vsi->mac_num++;
2820
2821                 return ret;
2822         }
2823         (void)rte_memcpy(&filter.mac_addr,
2824                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2825         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2826         return i40e_vsi_add_mac(vsi, &filter);
2827 }
2828
2829 static int
2830 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2831 {
2832         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2833         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2834         struct i40e_hw *hw = &vsi->adapter->hw;
2835         i40e_status ret;
2836         int i;
2837
2838         memset(&bw_config, 0, sizeof(bw_config));
2839         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2840         if (ret != I40E_SUCCESS) {
2841                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2842                             hw->aq.asq_last_status);
2843                 return ret;
2844         }
2845
2846         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2847         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2848                                         &ets_sla_config, NULL);
2849         if (ret != I40E_SUCCESS) {
2850                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2851                             "configuration %u", hw->aq.asq_last_status);
2852                 return ret;
2853         }
2854
2855         /* Not store the info yet, just print out */
2856         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2857         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2858         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2859                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2860                             ets_sla_config.share_credits[i]);
2861                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2862                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2863                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2864                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2865                             (i * 4));
2866         }
2867
2868         return 0;
2869 }
2870
2871 /* Setup a VSI */
2872 struct i40e_vsi *
2873 i40e_vsi_setup(struct i40e_pf *pf,
2874                enum i40e_vsi_type type,
2875                struct i40e_vsi *uplink_vsi,
2876                uint16_t user_param)
2877 {
2878         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2879         struct i40e_vsi *vsi;
2880         struct i40e_mac_filter_info filter;
2881         int ret;
2882         struct i40e_vsi_context ctxt;
2883         struct ether_addr broadcast =
2884                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2885
2886         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2887                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2888                             "VSI link shouldn't be NULL");
2889                 return NULL;
2890         }
2891
2892         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2893                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2894                             "uplink VSI should be NULL");
2895                 return NULL;
2896         }
2897
2898         /* If uplink vsi didn't setup VEB, create one first */
2899         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2900                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2901
2902                 if (NULL == uplink_vsi->veb) {
2903                         PMD_DRV_LOG(ERR, "VEB setup failed");
2904                         return NULL;
2905                 }
2906         }
2907
2908         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2909         if (!vsi) {
2910                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2911                 return NULL;
2912         }
2913         TAILQ_INIT(&vsi->mac_list);
2914         vsi->type = type;
2915         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2916         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2917         vsi->parent_vsi = uplink_vsi;
2918         vsi->user_param = user_param;
2919         /* Allocate queues */
2920         switch (vsi->type) {
2921         case I40E_VSI_MAIN  :
2922                 vsi->nb_qps = pf->lan_nb_qps;
2923                 break;
2924         case I40E_VSI_SRIOV :
2925                 vsi->nb_qps = pf->vf_nb_qps;
2926                 break;
2927         case I40E_VSI_VMDQ2:
2928                 vsi->nb_qps = pf->vmdq_nb_qps;
2929                 break;
2930         case I40E_VSI_FDIR:
2931                 vsi->nb_qps = pf->fdir_nb_qps;
2932                 break;
2933         default:
2934                 goto fail_mem;
2935         }
2936         /*
2937          * The filter status descriptor is reported in rx queue 0,
2938          * while the tx queue for fdir filter programming has no
2939          * such constraints, can be non-zero queues.
2940          * To simplify it, choose FDIR vsi use queue 0 pair.
2941          * To make sure it will use queue 0 pair, queue allocation
2942          * need be done before this function is called
2943          */
2944         if (type != I40E_VSI_FDIR) {
2945                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2946                         if (ret < 0) {
2947                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2948                                                 vsi->seid, ret);
2949                                 goto fail_mem;
2950                         }
2951                         vsi->base_queue = ret;
2952         } else
2953                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2954
2955         /* VF has MSIX interrupt in VF range, don't allocate here */
2956         if (type != I40E_VSI_SRIOV) {
2957                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2958                 if (ret < 0) {
2959                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2960                         goto fail_queue_alloc;
2961                 }
2962                 vsi->msix_intr = ret;
2963         } else
2964                 vsi->msix_intr = 0;
2965         /* Add VSI */
2966         if (type == I40E_VSI_MAIN) {
2967                 /* For main VSI, no need to add since it's default one */
2968                 vsi->uplink_seid = pf->mac_seid;
2969                 vsi->seid = pf->main_vsi_seid;
2970                 /* Bind queues with specific MSIX interrupt */
2971                 /**
2972                  * Needs 2 interrupt at least, one for misc cause which will
2973                  * enabled from OS side, Another for queues binding the
2974                  * interrupt from device side only.
2975                  */
2976
2977                 /* Get default VSI parameters from hardware */
2978                 memset(&ctxt, 0, sizeof(ctxt));
2979                 ctxt.seid = vsi->seid;
2980                 ctxt.pf_num = hw->pf_id;
2981                 ctxt.uplink_seid = vsi->uplink_seid;
2982                 ctxt.vf_num = 0;
2983                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2984                 if (ret != I40E_SUCCESS) {
2985                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2986                         goto fail_msix_alloc;
2987                 }
2988                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2989                         sizeof(struct i40e_aqc_vsi_properties_data));
2990                 vsi->vsi_id = ctxt.vsi_number;
2991                 vsi->info.valid_sections = 0;
2992
2993                 /* Configure tc, enabled TC0 only */
2994                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2995                         I40E_SUCCESS) {
2996                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2997                         goto fail_msix_alloc;
2998                 }
2999
3000                 /* TC, queue mapping */
3001                 memset(&ctxt, 0, sizeof(ctxt));
3002                 vsi->info.valid_sections |=
3003                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3004                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3005                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3006                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3007                         sizeof(struct i40e_aqc_vsi_properties_data));
3008                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3009                                                 I40E_DEFAULT_TCMAP);
3010                 if (ret != I40E_SUCCESS) {
3011                         PMD_DRV_LOG(ERR, "Failed to configure "
3012                                     "TC queue mapping");
3013                         goto fail_msix_alloc;
3014                 }
3015                 ctxt.seid = vsi->seid;
3016                 ctxt.pf_num = hw->pf_id;
3017                 ctxt.uplink_seid = vsi->uplink_seid;
3018                 ctxt.vf_num = 0;
3019
3020                 /* Update VSI parameters */
3021                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3022                 if (ret != I40E_SUCCESS) {
3023                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3024                         goto fail_msix_alloc;
3025                 }
3026
3027                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3028                                                 sizeof(vsi->info.tc_mapping));
3029                 (void)rte_memcpy(&vsi->info.queue_mapping,
3030                                 &ctxt.info.queue_mapping,
3031                         sizeof(vsi->info.queue_mapping));
3032                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3033                 vsi->info.valid_sections = 0;
3034
3035                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3036                                 ETH_ADDR_LEN);
3037
3038                 /**
3039                  * Updating default filter settings are necessary to prevent
3040                  * reception of tagged packets.
3041                  * Some old firmware configurations load a default macvlan
3042                  * filter which accepts both tagged and untagged packets.
3043                  * The updating is to use a normal filter instead if needed.
3044                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3045                  * The firmware with correct configurations load the default
3046                  * macvlan filter which is expected and cannot be removed.
3047                  */
3048                 i40e_update_default_filter_setting(vsi);
3049         } else if (type == I40E_VSI_SRIOV) {
3050                 memset(&ctxt, 0, sizeof(ctxt));
3051                 /**
3052                  * For other VSI, the uplink_seid equals to uplink VSI's
3053                  * uplink_seid since they share same VEB
3054                  */
3055                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3056                 ctxt.pf_num = hw->pf_id;
3057                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3058                 ctxt.uplink_seid = vsi->uplink_seid;
3059                 ctxt.connection_type = 0x1;
3060                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3061
3062                 /* Configure switch ID */
3063                 ctxt.info.valid_sections |=
3064                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3065                 ctxt.info.switch_id =
3066                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3067                 /* Configure port/vlan */
3068                 ctxt.info.valid_sections |=
3069                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3070                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3071                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3072                                                 I40E_DEFAULT_TCMAP);
3073                 if (ret != I40E_SUCCESS) {
3074                         PMD_DRV_LOG(ERR, "Failed to configure "
3075                                     "TC queue mapping");
3076                         goto fail_msix_alloc;
3077                 }
3078                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3079                 ctxt.info.valid_sections |=
3080                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3081                 /**
3082                  * Since VSI is not created yet, only configure parameter,
3083                  * will add vsi below.
3084                  */
3085         } else if (type == I40E_VSI_VMDQ2) {
3086                 memset(&ctxt, 0, sizeof(ctxt));
3087                 /*
3088                  * For other VSI, the uplink_seid equals to uplink VSI's
3089                  * uplink_seid since they share same VEB
3090                  */
3091                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3092                 ctxt.pf_num = hw->pf_id;
3093                 ctxt.vf_num = 0;
3094                 ctxt.uplink_seid = vsi->uplink_seid;
3095                 ctxt.connection_type = 0x1;
3096                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3097
3098                 ctxt.info.valid_sections |=
3099                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3100                 /* user_param carries flag to enable loop back */
3101                 if (user_param) {
3102                         ctxt.info.switch_id =
3103                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3104                         ctxt.info.switch_id |=
3105                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3106                 }
3107
3108                 /* Configure port/vlan */
3109                 ctxt.info.valid_sections |=
3110                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3111                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3112                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3113                                                 I40E_DEFAULT_TCMAP);
3114                 if (ret != I40E_SUCCESS) {
3115                         PMD_DRV_LOG(ERR, "Failed to configure "
3116                                         "TC queue mapping");
3117                         goto fail_msix_alloc;
3118                 }
3119                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3120                 ctxt.info.valid_sections |=
3121                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3122         } else if (type == I40E_VSI_FDIR) {
3123                 memset(&ctxt, 0, sizeof(ctxt));
3124                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3125                 ctxt.pf_num = hw->pf_id;
3126                 ctxt.vf_num = 0;
3127                 ctxt.uplink_seid = vsi->uplink_seid;
3128                 ctxt.connection_type = 0x1;     /* regular data port */
3129                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3130                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3131                                                 I40E_DEFAULT_TCMAP);
3132                 if (ret != I40E_SUCCESS) {
3133                         PMD_DRV_LOG(ERR, "Failed to configure "
3134                                         "TC queue mapping.");
3135                         goto fail_msix_alloc;
3136                 }
3137                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3138                 ctxt.info.valid_sections |=
3139                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3140         } else {
3141                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3142                 goto fail_msix_alloc;
3143         }
3144
3145         if (vsi->type != I40E_VSI_MAIN) {
3146                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3147                 if (ret != I40E_SUCCESS) {
3148                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3149                                     hw->aq.asq_last_status);
3150                         goto fail_msix_alloc;
3151                 }
3152                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3153                 vsi->info.valid_sections = 0;
3154                 vsi->seid = ctxt.seid;
3155                 vsi->vsi_id = ctxt.vsi_number;
3156                 vsi->sib_vsi_list.vsi = vsi;
3157                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3158                                 &vsi->sib_vsi_list, list);
3159         }
3160
3161         /* MAC/VLAN configuration */
3162         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3163         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3164
3165         ret = i40e_vsi_add_mac(vsi, &filter);
3166         if (ret != I40E_SUCCESS) {
3167                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3168                 goto fail_msix_alloc;
3169         }
3170
3171         /* Get VSI BW information */
3172         i40e_vsi_dump_bw_config(vsi);
3173         return vsi;
3174 fail_msix_alloc:
3175         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3176 fail_queue_alloc:
3177         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3178 fail_mem:
3179         rte_free(vsi);
3180         return NULL;
3181 }
3182
3183 /* Configure vlan stripping on or off */
3184 int
3185 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3186 {
3187         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3188         struct i40e_vsi_context ctxt;
3189         uint8_t vlan_flags;
3190         int ret = I40E_SUCCESS;
3191
3192         /* Check if it has been already on or off */
3193         if (vsi->info.valid_sections &
3194                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3195                 if (on) {
3196                         if ((vsi->info.port_vlan_flags &
3197                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3198                                 return 0; /* already on */
3199                 } else {
3200                         if ((vsi->info.port_vlan_flags &
3201                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3202                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3203                                 return 0; /* already off */
3204                 }
3205         }
3206
3207         if (on)
3208                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3209         else
3210                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3211         vsi->info.valid_sections =
3212                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3213         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3214         vsi->info.port_vlan_flags |= vlan_flags;
3215         ctxt.seid = vsi->seid;
3216         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3217         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3218         if (ret)
3219                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3220                             on ? "enable" : "disable");
3221
3222         return ret;
3223 }
3224
3225 static int
3226 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3227 {
3228         struct rte_eth_dev_data *data = dev->data;
3229         int ret;
3230
3231         /* Apply vlan offload setting */
3232         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3233
3234         /* Apply double-vlan setting, not implemented yet */
3235
3236         /* Apply pvid setting */
3237         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3238                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3239         if (ret)
3240                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3241
3242         return ret;
3243 }
3244
3245 static int
3246 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3247 {
3248         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3249
3250         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3251 }
3252
3253 static int
3254 i40e_update_flow_control(struct i40e_hw *hw)
3255 {
3256 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3257         struct i40e_link_status link_status;
3258         uint32_t rxfc = 0, txfc = 0, reg;
3259         uint8_t an_info;
3260         int ret;
3261
3262         memset(&link_status, 0, sizeof(link_status));
3263         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3264         if (ret != I40E_SUCCESS) {
3265                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3266                 goto write_reg; /* Disable flow control */
3267         }
3268
3269         an_info = hw->phy.link_info.an_info;
3270         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3271                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3272                 ret = I40E_ERR_NOT_READY;
3273                 goto write_reg; /* Disable flow control */
3274         }
3275         /**
3276          * If link auto negotiation is enabled, flow control needs to
3277          * be configured according to it
3278          */
3279         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3280         case I40E_LINK_PAUSE_RXTX:
3281                 rxfc = 1;
3282                 txfc = 1;
3283                 hw->fc.current_mode = I40E_FC_FULL;
3284                 break;
3285         case I40E_AQ_LINK_PAUSE_RX:
3286                 rxfc = 1;
3287                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3288                 break;
3289         case I40E_AQ_LINK_PAUSE_TX:
3290                 txfc = 1;
3291                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3292                 break;
3293         default:
3294                 hw->fc.current_mode = I40E_FC_NONE;
3295                 break;
3296         }
3297
3298 write_reg:
3299         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3300                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3301         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3302         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3303         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3304         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3305
3306         return ret;
3307 }
3308
3309 /* PF setup */
3310 static int
3311 i40e_pf_setup(struct i40e_pf *pf)
3312 {
3313         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3314         struct i40e_filter_control_settings settings;
3315         struct i40e_vsi *vsi;
3316         int ret;
3317
3318         /* Clear all stats counters */
3319         pf->offset_loaded = FALSE;
3320         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3321         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3322
3323         ret = i40e_pf_get_switch_config(pf);
3324         if (ret != I40E_SUCCESS) {
3325                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3326                 return ret;
3327         }
3328         if (pf->flags & I40E_FLAG_FDIR) {
3329                 /* make queue allocated first, let FDIR use queue pair 0*/
3330                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3331                 if (ret != I40E_FDIR_QUEUE_ID) {
3332                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3333                                     " ret =%d", ret);
3334                         pf->flags &= ~I40E_FLAG_FDIR;
3335                 }
3336         }
3337         /*  main VSI setup */
3338         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3339         if (!vsi) {
3340                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3341                 return I40E_ERR_NOT_READY;
3342         }
3343         pf->main_vsi = vsi;
3344
3345         /* Configure filter control */
3346         memset(&settings, 0, sizeof(settings));
3347         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3348                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3349         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3350                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3351         else {
3352                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3353                                                 hw->func_caps.rss_table_size);
3354                 return I40E_ERR_PARAM;
3355         }
3356         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3357                         "size: %u\n", hw->func_caps.rss_table_size);
3358         pf->hash_lut_size = hw->func_caps.rss_table_size;
3359
3360         /* Enable ethtype and macvlan filters */
3361         settings.enable_ethtype = TRUE;
3362         settings.enable_macvlan = TRUE;
3363         ret = i40e_set_filter_control(hw, &settings);
3364         if (ret)
3365                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3366                                                                 ret);
3367
3368         /* Update flow control according to the auto negotiation */
3369         i40e_update_flow_control(hw);
3370
3371         return I40E_SUCCESS;
3372 }
3373
3374 int
3375 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3376 {
3377         uint32_t reg;
3378         uint16_t j;
3379
3380         /**
3381          * Set or clear TX Queue Disable flags,
3382          * which is required by hardware.
3383          */
3384         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3385         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3386
3387         /* Wait until the request is finished */
3388         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3389                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3390                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3391                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3392                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3393                                                         & 0x1))) {
3394                         break;
3395                 }
3396         }
3397         if (on) {
3398                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3399                         return I40E_SUCCESS; /* already on, skip next steps */
3400
3401                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3402                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3403         } else {
3404                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3405                         return I40E_SUCCESS; /* already off, skip next steps */
3406                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3407         }
3408         /* Write the register */
3409         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3410         /* Check the result */
3411         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3412                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3413                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3414                 if (on) {
3415                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3416                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3417                                 break;
3418                 } else {
3419                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3420                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3421                                 break;
3422                 }
3423         }
3424         /* Check if it is timeout */
3425         if (j >= I40E_CHK_Q_ENA_COUNT) {
3426                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3427                             (on ? "enable" : "disable"), q_idx);
3428                 return I40E_ERR_TIMEOUT;
3429         }
3430
3431         return I40E_SUCCESS;
3432 }
3433
3434 /* Swith on or off the tx queues */
3435 static int
3436 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3437 {
3438         struct rte_eth_dev_data *dev_data = pf->dev_data;
3439         struct i40e_tx_queue *txq;
3440         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3441         uint16_t i;
3442         int ret;
3443
3444         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3445                 txq = dev_data->tx_queues[i];
3446                 /* Don't operate the queue if not configured or
3447                  * if starting only per queue */
3448                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3449                         continue;
3450                 if (on)
3451                         ret = i40e_dev_tx_queue_start(dev, i);
3452                 else
3453                         ret = i40e_dev_tx_queue_stop(dev, i);
3454                 if ( ret != I40E_SUCCESS)
3455                         return ret;
3456         }
3457
3458         return I40E_SUCCESS;
3459 }
3460
3461 int
3462 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3463 {
3464         uint32_t reg;
3465         uint16_t j;
3466
3467         /* Wait until the request is finished */
3468         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3469                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3470                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3471                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3472                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3473                         break;
3474         }
3475
3476         if (on) {
3477                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3478                         return I40E_SUCCESS; /* Already on, skip next steps */
3479                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3480         } else {
3481                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3482                         return I40E_SUCCESS; /* Already off, skip next steps */
3483                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3484         }
3485
3486         /* Write the register */
3487         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3488         /* Check the result */
3489         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3490                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3491                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3492                 if (on) {
3493                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3494                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3495                                 break;
3496                 } else {
3497                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3498                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3499                                 break;
3500                 }
3501         }
3502
3503         /* Check if it is timeout */
3504         if (j >= I40E_CHK_Q_ENA_COUNT) {
3505                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3506                             (on ? "enable" : "disable"), q_idx);
3507                 return I40E_ERR_TIMEOUT;
3508         }
3509
3510         return I40E_SUCCESS;
3511 }
3512 /* Switch on or off the rx queues */
3513 static int
3514 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3515 {
3516         struct rte_eth_dev_data *dev_data = pf->dev_data;
3517         struct i40e_rx_queue *rxq;
3518         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3519         uint16_t i;
3520         int ret;
3521
3522         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3523                 rxq = dev_data->rx_queues[i];
3524                 /* Don't operate the queue if not configured or
3525                  * if starting only per queue */
3526                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3527                         continue;
3528                 if (on)
3529                         ret = i40e_dev_rx_queue_start(dev, i);
3530                 else
3531                         ret = i40e_dev_rx_queue_stop(dev, i);
3532                 if (ret != I40E_SUCCESS)
3533                         return ret;
3534         }
3535
3536         return I40E_SUCCESS;
3537 }
3538
3539 /* Switch on or off all the rx/tx queues */
3540 int
3541 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3542 {
3543         int ret;
3544
3545         if (on) {
3546                 /* enable rx queues before enabling tx queues */
3547                 ret = i40e_dev_switch_rx_queues(pf, on);
3548                 if (ret) {
3549                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3550                         return ret;
3551                 }
3552                 ret = i40e_dev_switch_tx_queues(pf, on);
3553         } else {
3554                 /* Stop tx queues before stopping rx queues */
3555                 ret = i40e_dev_switch_tx_queues(pf, on);
3556                 if (ret) {
3557                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3558                         return ret;
3559                 }
3560                 ret = i40e_dev_switch_rx_queues(pf, on);
3561         }
3562
3563         return ret;
3564 }
3565
3566 /* Initialize VSI for TX */
3567 static int
3568 i40e_dev_tx_init(struct i40e_pf *pf)
3569 {
3570         struct rte_eth_dev_data *data = pf->dev_data;
3571         uint16_t i;
3572         uint32_t ret = I40E_SUCCESS;
3573         struct i40e_tx_queue *txq;
3574
3575         for (i = 0; i < data->nb_tx_queues; i++) {
3576                 txq = data->tx_queues[i];
3577                 if (!txq || !txq->q_set)
3578                         continue;
3579                 ret = i40e_tx_queue_init(txq);
3580                 if (ret != I40E_SUCCESS)
3581                         break;
3582         }
3583
3584         return ret;
3585 }
3586
3587 /* Initialize VSI for RX */
3588 static int
3589 i40e_dev_rx_init(struct i40e_pf *pf)
3590 {
3591         struct rte_eth_dev_data *data = pf->dev_data;
3592         int ret = I40E_SUCCESS;
3593         uint16_t i;
3594         struct i40e_rx_queue *rxq;
3595
3596         i40e_pf_config_mq_rx(pf);
3597         for (i = 0; i < data->nb_rx_queues; i++) {
3598                 rxq = data->rx_queues[i];
3599                 if (!rxq || !rxq->q_set)
3600                         continue;
3601
3602                 ret = i40e_rx_queue_init(rxq);
3603                 if (ret != I40E_SUCCESS) {
3604                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3605                                     "initialization");
3606                         break;
3607                 }
3608         }
3609
3610         return ret;
3611 }
3612
3613 static int
3614 i40e_dev_rxtx_init(struct i40e_pf *pf)
3615 {
3616         int err;
3617
3618         err = i40e_dev_tx_init(pf);
3619         if (err) {
3620                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3621                 return err;
3622         }
3623         err = i40e_dev_rx_init(pf);
3624         if (err) {
3625                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3626                 return err;
3627         }
3628
3629         return err;
3630 }
3631
3632 static int
3633 i40e_vmdq_setup(struct rte_eth_dev *dev)
3634 {
3635         struct rte_eth_conf *conf = &dev->data->dev_conf;
3636         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3637         int i, err, conf_vsis, j, loop;
3638         struct i40e_vsi *vsi;
3639         struct i40e_vmdq_info *vmdq_info;
3640         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3641         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3642
3643         /*
3644          * Disable interrupt to avoid message from VF. Furthermore, it will
3645          * avoid race condition in VSI creation/destroy.
3646          */
3647         i40e_pf_disable_irq0(hw);
3648
3649         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3650                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3651                 return -ENOTSUP;
3652         }
3653
3654         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3655         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3656                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3657                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3658                         pf->max_nb_vmdq_vsi);
3659                 return -ENOTSUP;
3660         }
3661
3662         if (pf->vmdq != NULL) {
3663                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3664                 return 0;
3665         }
3666
3667         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3668                                 sizeof(*vmdq_info) * conf_vsis, 0);
3669
3670         if (pf->vmdq == NULL) {
3671                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3672                 return -ENOMEM;
3673         }
3674
3675         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3676
3677         /* Create VMDQ VSI */
3678         for (i = 0; i < conf_vsis; i++) {
3679                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3680                                 vmdq_conf->enable_loop_back);
3681                 if (vsi == NULL) {
3682                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3683                         err = -1;
3684                         goto err_vsi_setup;
3685                 }
3686                 vmdq_info = &pf->vmdq[i];
3687                 vmdq_info->pf = pf;
3688                 vmdq_info->vsi = vsi;
3689         }
3690         pf->nb_cfg_vmdq_vsi = conf_vsis;
3691
3692         /* Configure Vlan */
3693         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3694         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3695                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3696                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3697                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3698                                         vmdq_conf->pool_map[i].vlan_id, j);
3699
3700                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3701                                                 vmdq_conf->pool_map[i].vlan_id);
3702                                 if (err) {
3703                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3704                                         err = -1;
3705                                         goto err_vsi_setup;
3706                                 }
3707                         }
3708                 }
3709         }
3710
3711         i40e_pf_enable_irq0(hw);
3712
3713         return 0;
3714
3715 err_vsi_setup:
3716         for (i = 0; i < conf_vsis; i++)
3717                 if (pf->vmdq[i].vsi == NULL)
3718                         break;
3719                 else
3720                         i40e_vsi_release(pf->vmdq[i].vsi);
3721
3722         rte_free(pf->vmdq);
3723         pf->vmdq = NULL;
3724         i40e_pf_enable_irq0(hw);
3725         return err;
3726 }
3727
3728 static void
3729 i40e_stat_update_32(struct i40e_hw *hw,
3730                    uint32_t reg,
3731                    bool offset_loaded,
3732                    uint64_t *offset,
3733                    uint64_t *stat)
3734 {
3735         uint64_t new_data;
3736
3737         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3738         if (!offset_loaded)
3739                 *offset = new_data;
3740
3741         if (new_data >= *offset)
3742                 *stat = (uint64_t)(new_data - *offset);
3743         else
3744                 *stat = (uint64_t)((new_data +
3745                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3746 }
3747
3748 static void
3749 i40e_stat_update_48(struct i40e_hw *hw,
3750                    uint32_t hireg,
3751                    uint32_t loreg,
3752                    bool offset_loaded,
3753                    uint64_t *offset,
3754                    uint64_t *stat)
3755 {
3756         uint64_t new_data;
3757
3758         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3759         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3760                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3761
3762         if (!offset_loaded)
3763                 *offset = new_data;
3764
3765         if (new_data >= *offset)
3766                 *stat = new_data - *offset;
3767         else
3768                 *stat = (uint64_t)((new_data +
3769                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3770
3771         *stat &= I40E_48_BIT_MASK;
3772 }
3773
3774 /* Disable IRQ0 */
3775 void
3776 i40e_pf_disable_irq0(struct i40e_hw *hw)
3777 {
3778         /* Disable all interrupt types */
3779         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3780         I40E_WRITE_FLUSH(hw);
3781 }
3782
3783 /* Enable IRQ0 */
3784 void
3785 i40e_pf_enable_irq0(struct i40e_hw *hw)
3786 {
3787         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3788                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3789                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3790                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3791         I40E_WRITE_FLUSH(hw);
3792 }
3793
3794 static void
3795 i40e_pf_config_irq0(struct i40e_hw *hw)
3796 {
3797         /* read pending request and disable first */
3798         i40e_pf_disable_irq0(hw);
3799         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3800         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3801                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3802
3803         /* Link no queues with irq0 */
3804         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3805                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3806 }
3807
3808 static void
3809 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3810 {
3811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3813         int i;
3814         uint16_t abs_vf_id;
3815         uint32_t index, offset, val;
3816
3817         if (!pf->vfs)
3818                 return;
3819         /**
3820          * Try to find which VF trigger a reset, use absolute VF id to access
3821          * since the reg is global register.
3822          */
3823         for (i = 0; i < pf->vf_num; i++) {
3824                 abs_vf_id = hw->func_caps.vf_base_id + i;
3825                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3826                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3827                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3828                 /* VFR event occured */
3829                 if (val & (0x1 << offset)) {
3830                         int ret;
3831
3832                         /* Clear the event first */
3833                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3834                                                         (0x1 << offset));
3835                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3836                         /**
3837                          * Only notify a VF reset event occured,
3838                          * don't trigger another SW reset
3839                          */
3840                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3841                         if (ret != I40E_SUCCESS)
3842                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3843                 }
3844         }
3845 }
3846
3847 static void
3848 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3849 {
3850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851         struct i40e_arq_event_info info;
3852         uint16_t pending, opcode;
3853         int ret;
3854
3855         info.buf_len = I40E_AQ_BUF_SZ;
3856         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3857         if (!info.msg_buf) {
3858                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3859                 return;
3860         }
3861
3862         pending = 1;
3863         while (pending) {
3864                 ret = i40e_clean_arq_element(hw, &info, &pending);
3865
3866                 if (ret != I40E_SUCCESS) {
3867                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3868                                     "aq_err: %u", hw->aq.asq_last_status);
3869                         break;
3870                 }
3871                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3872
3873                 switch (opcode) {
3874                 case i40e_aqc_opc_send_msg_to_pf:
3875                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3876                         i40e_pf_host_handle_vf_msg(dev,
3877                                         rte_le_to_cpu_16(info.desc.retval),
3878                                         rte_le_to_cpu_32(info.desc.cookie_high),
3879                                         rte_le_to_cpu_32(info.desc.cookie_low),
3880                                         info.msg_buf,
3881                                         info.msg_len);
3882                         break;
3883                 default:
3884                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3885                                     opcode);
3886                         break;
3887                 }
3888         }
3889         rte_free(info.msg_buf);
3890 }
3891
3892 /*
3893  * Interrupt handler is registered as the alarm callback for handling LSC
3894  * interrupt in a definite of time, in order to wait the NIC into a stable
3895  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3896  * no need for link down interrupt.
3897  */
3898 static void
3899 i40e_dev_interrupt_delayed_handler(void *param)
3900 {
3901         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903         uint32_t icr0;
3904
3905         /* read interrupt causes again */
3906         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3907
3908 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3909         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3910                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3911         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3912                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3913         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3914                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3915         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3916                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3917         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3918                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3919                                                                 "state\n");
3920         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3921                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3922         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3923                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3924 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3925
3926         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3927                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3928                 i40e_dev_handle_vfr_event(dev);
3929         }
3930         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3931                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3932                 i40e_dev_handle_aq_msg(dev);
3933         }
3934
3935         /* handle the link up interrupt in an alarm callback */
3936         i40e_dev_link_update(dev, 0);
3937         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3938
3939         i40e_pf_enable_irq0(hw);
3940         rte_intr_enable(&(dev->pci_dev->intr_handle));
3941 }
3942
3943 /**
3944  * Interrupt handler triggered by NIC  for handling
3945  * specific interrupt.
3946  *
3947  * @param handle
3948  *  Pointer to interrupt handle.
3949  * @param param
3950  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3951  *
3952  * @return
3953  *  void
3954  */
3955 static void
3956 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3957                            void *param)
3958 {
3959         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961         uint32_t icr0;
3962
3963         /* Disable interrupt */
3964         i40e_pf_disable_irq0(hw);
3965
3966         /* read out interrupt causes */
3967         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3968
3969         /* No interrupt event indicated */
3970         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3971                 PMD_DRV_LOG(INFO, "No interrupt event");
3972                 goto done;
3973         }
3974 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3975         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3976                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3977         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3978                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3979         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3980                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3981         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3982                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3983         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3984                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3985         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3986                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3987         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3988                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3989 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3990
3991         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3992                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3993                 i40e_dev_handle_vfr_event(dev);
3994         }
3995         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3996                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3997                 i40e_dev_handle_aq_msg(dev);
3998         }
3999
4000         /* Link Status Change interrupt */
4001         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4002 #define I40E_US_PER_SECOND 1000000
4003                 struct rte_eth_link link;
4004
4005                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4006                 memset(&link, 0, sizeof(link));
4007                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4008                 i40e_dev_link_update(dev, 0);
4009
4010                 /*
4011                  * For link up interrupt, it needs to wait 1 second to let the
4012                  * hardware be a stable state. Otherwise several consecutive
4013                  * interrupts can be observed.
4014                  * For link down interrupt, no need to wait.
4015                  */
4016                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4017                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4018                         return;
4019                 else
4020                         _rte_eth_dev_callback_process(dev,
4021                                 RTE_ETH_EVENT_INTR_LSC);
4022         }
4023
4024 done:
4025         /* Enable interrupt */
4026         i40e_pf_enable_irq0(hw);
4027         rte_intr_enable(&(dev->pci_dev->intr_handle));
4028 }
4029
4030 static int
4031 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4032                          struct i40e_macvlan_filter *filter,
4033                          int total)
4034 {
4035         int ele_num, ele_buff_size;
4036         int num, actual_num, i;
4037         uint16_t flags;
4038         int ret = I40E_SUCCESS;
4039         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4040         struct i40e_aqc_add_macvlan_element_data *req_list;
4041
4042         if (filter == NULL  || total == 0)
4043                 return I40E_ERR_PARAM;
4044         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4045         ele_buff_size = hw->aq.asq_buf_size;
4046
4047         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4048         if (req_list == NULL) {
4049                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4050                 return I40E_ERR_NO_MEMORY;
4051         }
4052
4053         num = 0;
4054         do {
4055                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4056                 memset(req_list, 0, ele_buff_size);
4057
4058                 for (i = 0; i < actual_num; i++) {
4059                         (void)rte_memcpy(req_list[i].mac_addr,
4060                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4061                         req_list[i].vlan_tag =
4062                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4063
4064                         switch (filter[num + i].filter_type) {
4065                         case RTE_MAC_PERFECT_MATCH:
4066                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4067                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4068                                 break;
4069                         case RTE_MACVLAN_PERFECT_MATCH:
4070                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4071                                 break;
4072                         case RTE_MAC_HASH_MATCH:
4073                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4074                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4075                                 break;
4076                         case RTE_MACVLAN_HASH_MATCH:
4077                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4078                                 break;
4079                         default:
4080                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4081                                 ret = I40E_ERR_PARAM;
4082                                 goto DONE;
4083                         }
4084
4085                         req_list[i].queue_number = 0;
4086
4087                         req_list[i].flags = rte_cpu_to_le_16(flags);
4088                 }
4089
4090                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4091                                                 actual_num, NULL);
4092                 if (ret != I40E_SUCCESS) {
4093                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4094                         goto DONE;
4095                 }
4096                 num += actual_num;
4097         } while (num < total);
4098
4099 DONE:
4100         rte_free(req_list);
4101         return ret;
4102 }
4103
4104 static int
4105 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4106                             struct i40e_macvlan_filter *filter,
4107                             int total)
4108 {
4109         int ele_num, ele_buff_size;
4110         int num, actual_num, i;
4111         uint16_t flags;
4112         int ret = I40E_SUCCESS;
4113         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4114         struct i40e_aqc_remove_macvlan_element_data *req_list;
4115
4116         if (filter == NULL  || total == 0)
4117                 return I40E_ERR_PARAM;
4118
4119         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4120         ele_buff_size = hw->aq.asq_buf_size;
4121
4122         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4123         if (req_list == NULL) {
4124                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4125                 return I40E_ERR_NO_MEMORY;
4126         }
4127
4128         num = 0;
4129         do {
4130                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4131                 memset(req_list, 0, ele_buff_size);
4132
4133                 for (i = 0; i < actual_num; i++) {
4134                         (void)rte_memcpy(req_list[i].mac_addr,
4135                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4136                         req_list[i].vlan_tag =
4137                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4138
4139                         switch (filter[num + i].filter_type) {
4140                         case RTE_MAC_PERFECT_MATCH:
4141                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4142                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4143                                 break;
4144                         case RTE_MACVLAN_PERFECT_MATCH:
4145                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4146                                 break;
4147                         case RTE_MAC_HASH_MATCH:
4148                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4149                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4150                                 break;
4151                         case RTE_MACVLAN_HASH_MATCH:
4152                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4153                                 break;
4154                         default:
4155                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4156                                 ret = I40E_ERR_PARAM;
4157                                 goto DONE;
4158                         }
4159                         req_list[i].flags = rte_cpu_to_le_16(flags);
4160                 }
4161
4162                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4163                                                 actual_num, NULL);
4164                 if (ret != I40E_SUCCESS) {
4165                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4166                         goto DONE;
4167                 }
4168                 num += actual_num;
4169         } while (num < total);
4170
4171 DONE:
4172         rte_free(req_list);
4173         return ret;
4174 }
4175
4176 /* Find out specific MAC filter */
4177 static struct i40e_mac_filter *
4178 i40e_find_mac_filter(struct i40e_vsi *vsi,
4179                          struct ether_addr *macaddr)
4180 {
4181         struct i40e_mac_filter *f;
4182
4183         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4184                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4185                         return f;
4186         }
4187
4188         return NULL;
4189 }
4190
4191 static bool
4192 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4193                          uint16_t vlan_id)
4194 {
4195         uint32_t vid_idx, vid_bit;
4196
4197         if (vlan_id > ETH_VLAN_ID_MAX)
4198                 return 0;
4199
4200         vid_idx = I40E_VFTA_IDX(vlan_id);
4201         vid_bit = I40E_VFTA_BIT(vlan_id);
4202
4203         if (vsi->vfta[vid_idx] & vid_bit)
4204                 return 1;
4205         else
4206                 return 0;
4207 }
4208
4209 static void
4210 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4211                          uint16_t vlan_id, bool on)
4212 {
4213         uint32_t vid_idx, vid_bit;
4214
4215         if (vlan_id > ETH_VLAN_ID_MAX)
4216                 return;
4217
4218         vid_idx = I40E_VFTA_IDX(vlan_id);
4219         vid_bit = I40E_VFTA_BIT(vlan_id);
4220
4221         if (on)
4222                 vsi->vfta[vid_idx] |= vid_bit;
4223         else
4224                 vsi->vfta[vid_idx] &= ~vid_bit;
4225 }
4226
4227 /**
4228  * Find all vlan options for specific mac addr,
4229  * return with actual vlan found.
4230  */
4231 static inline int
4232 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4233                            struct i40e_macvlan_filter *mv_f,
4234                            int num, struct ether_addr *addr)
4235 {
4236         int i;
4237         uint32_t j, k;
4238
4239         /**
4240          * Not to use i40e_find_vlan_filter to decrease the loop time,
4241          * although the code looks complex.
4242           */
4243         if (num < vsi->vlan_num)
4244                 return I40E_ERR_PARAM;
4245
4246         i = 0;
4247         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4248                 if (vsi->vfta[j]) {
4249                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4250                                 if (vsi->vfta[j] & (1 << k)) {
4251                                         if (i > num - 1) {
4252                                                 PMD_DRV_LOG(ERR, "vlan number "
4253                                                             "not match");
4254                                                 return I40E_ERR_PARAM;
4255                                         }
4256                                         (void)rte_memcpy(&mv_f[i].macaddr,
4257                                                         addr, ETH_ADDR_LEN);
4258                                         mv_f[i].vlan_id =
4259                                                 j * I40E_UINT32_BIT_SIZE + k;
4260                                         i++;
4261                                 }
4262                         }
4263                 }
4264         }
4265         return I40E_SUCCESS;
4266 }
4267
4268 static inline int
4269 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4270                            struct i40e_macvlan_filter *mv_f,
4271                            int num,
4272                            uint16_t vlan)
4273 {
4274         int i = 0;
4275         struct i40e_mac_filter *f;
4276
4277         if (num < vsi->mac_num)
4278                 return I40E_ERR_PARAM;
4279
4280         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4281                 if (i > num - 1) {
4282                         PMD_DRV_LOG(ERR, "buffer number not match");
4283                         return I40E_ERR_PARAM;
4284                 }
4285                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4286                                 ETH_ADDR_LEN);
4287                 mv_f[i].vlan_id = vlan;
4288                 mv_f[i].filter_type = f->mac_info.filter_type;
4289                 i++;
4290         }
4291
4292         return I40E_SUCCESS;
4293 }
4294
4295 static int
4296 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4297 {
4298         int i, num;
4299         struct i40e_mac_filter *f;
4300         struct i40e_macvlan_filter *mv_f;
4301         int ret = I40E_SUCCESS;
4302
4303         if (vsi == NULL || vsi->mac_num == 0)
4304                 return I40E_ERR_PARAM;
4305
4306         /* Case that no vlan is set */
4307         if (vsi->vlan_num == 0)
4308                 num = vsi->mac_num;
4309         else
4310                 num = vsi->mac_num * vsi->vlan_num;
4311
4312         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4313         if (mv_f == NULL) {
4314                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4315                 return I40E_ERR_NO_MEMORY;
4316         }
4317
4318         i = 0;
4319         if (vsi->vlan_num == 0) {
4320                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4321                         (void)rte_memcpy(&mv_f[i].macaddr,
4322                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4323                         mv_f[i].vlan_id = 0;
4324                         i++;
4325                 }
4326         } else {
4327                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4328                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4329                                         vsi->vlan_num, &f->mac_info.mac_addr);
4330                         if (ret != I40E_SUCCESS)
4331                                 goto DONE;
4332                         i += vsi->vlan_num;
4333                 }
4334         }
4335
4336         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4337 DONE:
4338         rte_free(mv_f);
4339
4340         return ret;
4341 }
4342
4343 int
4344 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4345 {
4346         struct i40e_macvlan_filter *mv_f;
4347         int mac_num;
4348         int ret = I40E_SUCCESS;
4349
4350         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4351                 return I40E_ERR_PARAM;
4352
4353         /* If it's already set, just return */
4354         if (i40e_find_vlan_filter(vsi,vlan))
4355                 return I40E_SUCCESS;
4356
4357         mac_num = vsi->mac_num;
4358
4359         if (mac_num == 0) {
4360                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4361                 return I40E_ERR_PARAM;
4362         }
4363
4364         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4365
4366         if (mv_f == NULL) {
4367                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4368                 return I40E_ERR_NO_MEMORY;
4369         }
4370
4371         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4372
4373         if (ret != I40E_SUCCESS)
4374                 goto DONE;
4375
4376         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4377
4378         if (ret != I40E_SUCCESS)
4379                 goto DONE;
4380
4381         i40e_set_vlan_filter(vsi, vlan, 1);
4382
4383         vsi->vlan_num++;
4384         ret = I40E_SUCCESS;
4385 DONE:
4386         rte_free(mv_f);
4387         return ret;
4388 }
4389
4390 int
4391 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4392 {
4393         struct i40e_macvlan_filter *mv_f;
4394         int mac_num;
4395         int ret = I40E_SUCCESS;
4396
4397         /**
4398          * Vlan 0 is the generic filter for untagged packets
4399          * and can't be removed.
4400          */
4401         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4402                 return I40E_ERR_PARAM;
4403
4404         /* If can't find it, just return */
4405         if (!i40e_find_vlan_filter(vsi, vlan))
4406                 return I40E_ERR_PARAM;
4407
4408         mac_num = vsi->mac_num;
4409
4410         if (mac_num == 0) {
4411                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4412                 return I40E_ERR_PARAM;
4413         }
4414
4415         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4416
4417         if (mv_f == NULL) {
4418                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4419                 return I40E_ERR_NO_MEMORY;
4420         }
4421
4422         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4423
4424         if (ret != I40E_SUCCESS)
4425                 goto DONE;
4426
4427         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4428
4429         if (ret != I40E_SUCCESS)
4430                 goto DONE;
4431
4432         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4433         if (vsi->vlan_num == 1) {
4434                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4435                 if (ret != I40E_SUCCESS)
4436                         goto DONE;
4437
4438                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4439                 if (ret != I40E_SUCCESS)
4440                         goto DONE;
4441         }
4442
4443         i40e_set_vlan_filter(vsi, vlan, 0);
4444
4445         vsi->vlan_num--;
4446         ret = I40E_SUCCESS;
4447 DONE:
4448         rte_free(mv_f);
4449         return ret;
4450 }
4451
4452 int
4453 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4454 {
4455         struct i40e_mac_filter *f;
4456         struct i40e_macvlan_filter *mv_f;
4457         int i, vlan_num = 0;
4458         int ret = I40E_SUCCESS;
4459
4460         /* If it's add and we've config it, return */
4461         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4462         if (f != NULL)
4463                 return I40E_SUCCESS;
4464         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4465                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4466
4467                 /**
4468                  * If vlan_num is 0, that's the first time to add mac,
4469                  * set mask for vlan_id 0.
4470                  */
4471                 if (vsi->vlan_num == 0) {
4472                         i40e_set_vlan_filter(vsi, 0, 1);
4473                         vsi->vlan_num = 1;
4474                 }
4475                 vlan_num = vsi->vlan_num;
4476         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4477                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4478                 vlan_num = 1;
4479
4480         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4481         if (mv_f == NULL) {
4482                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4483                 return I40E_ERR_NO_MEMORY;
4484         }
4485
4486         for (i = 0; i < vlan_num; i++) {
4487                 mv_f[i].filter_type = mac_filter->filter_type;
4488                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4489                                 ETH_ADDR_LEN);
4490         }
4491
4492         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4493                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4494                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4495                                         &mac_filter->mac_addr);
4496                 if (ret != I40E_SUCCESS)
4497                         goto DONE;
4498         }
4499
4500         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4501         if (ret != I40E_SUCCESS)
4502                 goto DONE;
4503
4504         /* Add the mac addr into mac list */
4505         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4506         if (f == NULL) {
4507                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4508                 ret = I40E_ERR_NO_MEMORY;
4509                 goto DONE;
4510         }
4511         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4512                         ETH_ADDR_LEN);
4513         f->mac_info.filter_type = mac_filter->filter_type;
4514         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4515         vsi->mac_num++;
4516
4517         ret = I40E_SUCCESS;
4518 DONE:
4519         rte_free(mv_f);
4520
4521         return ret;
4522 }
4523
4524 int
4525 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4526 {
4527         struct i40e_mac_filter *f;
4528         struct i40e_macvlan_filter *mv_f;
4529         int i, vlan_num;
4530         enum rte_mac_filter_type filter_type;
4531         int ret = I40E_SUCCESS;
4532
4533         /* Can't find it, return an error */
4534         f = i40e_find_mac_filter(vsi, addr);
4535         if (f == NULL)
4536                 return I40E_ERR_PARAM;
4537
4538         vlan_num = vsi->vlan_num;
4539         filter_type = f->mac_info.filter_type;
4540         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4541                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4542                 if (vlan_num == 0) {
4543                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4544                         return I40E_ERR_PARAM;
4545                 }
4546         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4547                         filter_type == RTE_MAC_HASH_MATCH)
4548                 vlan_num = 1;
4549
4550         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4551         if (mv_f == NULL) {
4552                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4553                 return I40E_ERR_NO_MEMORY;
4554         }
4555
4556         for (i = 0; i < vlan_num; i++) {
4557                 mv_f[i].filter_type = filter_type;
4558                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4559                                 ETH_ADDR_LEN);
4560         }
4561         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4562                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4563                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4564                 if (ret != I40E_SUCCESS)
4565                         goto DONE;
4566         }
4567
4568         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4569         if (ret != I40E_SUCCESS)
4570                 goto DONE;
4571
4572         /* Remove the mac addr into mac list */
4573         TAILQ_REMOVE(&vsi->mac_list, f, next);
4574         rte_free(f);
4575         vsi->mac_num--;
4576
4577         ret = I40E_SUCCESS;
4578 DONE:
4579         rte_free(mv_f);
4580         return ret;
4581 }
4582
4583 /* Configure hash enable flags for RSS */
4584 uint64_t
4585 i40e_config_hena(uint64_t flags)
4586 {
4587         uint64_t hena = 0;
4588
4589         if (!flags)
4590                 return hena;
4591
4592         if (flags & ETH_RSS_FRAG_IPV4)
4593                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4594         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4595                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4596         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4597                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4598         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4599                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4600         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4601                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4602         if (flags & ETH_RSS_FRAG_IPV6)
4603                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4604         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4605                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4606         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4607                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4608         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4609                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4610         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4611                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4612         if (flags & ETH_RSS_L2_PAYLOAD)
4613                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4614
4615         return hena;
4616 }
4617
4618 /* Parse the hash enable flags */
4619 uint64_t
4620 i40e_parse_hena(uint64_t flags)
4621 {
4622         uint64_t rss_hf = 0;
4623
4624         if (!flags)
4625                 return rss_hf;
4626         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4627                 rss_hf |= ETH_RSS_FRAG_IPV4;
4628         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4629                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4630         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4631                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4632         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4633                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4634         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4635                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4636         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4637                 rss_hf |= ETH_RSS_FRAG_IPV6;
4638         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4639                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4640         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4641                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4642         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4643                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4644         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4645                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4646         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4647                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4648
4649         return rss_hf;
4650 }
4651
4652 /* Disable RSS */
4653 static void
4654 i40e_pf_disable_rss(struct i40e_pf *pf)
4655 {
4656         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4657         uint64_t hena;
4658
4659         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4660         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4661         hena &= ~I40E_RSS_HENA_ALL;
4662         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4663         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4664         I40E_WRITE_FLUSH(hw);
4665 }
4666
4667 static int
4668 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4669 {
4670         uint32_t *hash_key;
4671         uint8_t hash_key_len;
4672         uint64_t rss_hf;
4673         uint16_t i;
4674         uint64_t hena;
4675
4676         hash_key = (uint32_t *)(rss_conf->rss_key);
4677         hash_key_len = rss_conf->rss_key_len;
4678         if (hash_key != NULL && hash_key_len >=
4679                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4680                 /* Fill in RSS hash key */
4681                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4682                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4683         }
4684
4685         rss_hf = rss_conf->rss_hf;
4686         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4687         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4688         hena &= ~I40E_RSS_HENA_ALL;
4689         hena |= i40e_config_hena(rss_hf);
4690         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4691         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4692         I40E_WRITE_FLUSH(hw);
4693
4694         return 0;
4695 }
4696
4697 static int
4698 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4699                          struct rte_eth_rss_conf *rss_conf)
4700 {
4701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4703         uint64_t hena;
4704
4705         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4706         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4707         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4708                 if (rss_hf != 0) /* Enable RSS */
4709                         return -EINVAL;
4710                 return 0; /* Nothing to do */
4711         }
4712         /* RSS enabled */
4713         if (rss_hf == 0) /* Disable RSS */
4714                 return -EINVAL;
4715
4716         return i40e_hw_rss_hash_set(hw, rss_conf);
4717 }
4718
4719 static int
4720 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4721                            struct rte_eth_rss_conf *rss_conf)
4722 {
4723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4725         uint64_t hena;
4726         uint16_t i;
4727
4728         if (hash_key != NULL) {
4729                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4730                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4731                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4732         }
4733         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4734         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4735         rss_conf->rss_hf = i40e_parse_hena(hena);
4736
4737         return 0;
4738 }
4739
4740 static int
4741 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4742 {
4743         switch (filter_type) {
4744         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4745                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4746                 break;
4747         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4748                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4749                 break;
4750         case RTE_TUNNEL_FILTER_IMAC_TENID:
4751                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4752                 break;
4753         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4754                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4755                 break;
4756         case ETH_TUNNEL_FILTER_IMAC:
4757                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4758                 break;
4759         default:
4760                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4761                 return -EINVAL;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static int
4768 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4769                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4770                         uint8_t add)
4771 {
4772         uint16_t ip_type;
4773         uint8_t tun_type = 0;
4774         int val, ret = 0;
4775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4776         struct i40e_vsi *vsi = pf->main_vsi;
4777         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4778         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4779
4780         cld_filter = rte_zmalloc("tunnel_filter",
4781                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4782                 0);
4783
4784         if (NULL == cld_filter) {
4785                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4786                 return -EINVAL;
4787         }
4788         pfilter = cld_filter;
4789
4790         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4791                         sizeof(struct ether_addr));
4792         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4793                         sizeof(struct ether_addr));
4794
4795         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4796         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4797                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4798                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4799                                 &tunnel_filter->ip_addr,
4800                                 sizeof(pfilter->ipaddr.v4.data));
4801         } else {
4802                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4803                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4804                                 &tunnel_filter->ip_addr,
4805                                 sizeof(pfilter->ipaddr.v6.data));
4806         }
4807
4808         /* check tunneled type */
4809         switch (tunnel_filter->tunnel_type) {
4810         case RTE_TUNNEL_TYPE_VXLAN:
4811                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4812                 break;
4813         case RTE_TUNNEL_TYPE_NVGRE:
4814                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4815                 break;
4816         default:
4817                 /* Other tunnel types is not supported. */
4818                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4819                 rte_free(cld_filter);
4820                 return -EINVAL;
4821         }
4822
4823         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4824                                                 &pfilter->flags);
4825         if (val < 0) {
4826                 rte_free(cld_filter);
4827                 return -EINVAL;
4828         }
4829
4830         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4831                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4832         pfilter->tenant_id = tunnel_filter->tenant_id;
4833         pfilter->queue_number = tunnel_filter->queue_id;
4834
4835         if (add)
4836                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4837         else
4838                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4839                                                 cld_filter, 1);
4840
4841         rte_free(cld_filter);
4842         return ret;
4843 }
4844
4845 static int
4846 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4847 {
4848         uint8_t i;
4849
4850         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4851                 if (pf->vxlan_ports[i] == port)
4852                         return i;
4853         }
4854
4855         return -1;
4856 }
4857
4858 static int
4859 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4860 {
4861         int  idx, ret;
4862         uint8_t filter_idx;
4863         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4864
4865         idx = i40e_get_vxlan_port_idx(pf, port);
4866
4867         /* Check if port already exists */
4868         if (idx >= 0) {
4869                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4870                 return -EINVAL;
4871         }
4872
4873         /* Now check if there is space to add the new port */
4874         idx = i40e_get_vxlan_port_idx(pf, 0);
4875         if (idx < 0) {
4876                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4877                         "not adding port %d", port);
4878                 return -ENOSPC;
4879         }
4880
4881         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4882                                         &filter_idx, NULL);
4883         if (ret < 0) {
4884                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4885                 return -1;
4886         }
4887
4888         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4889                          port,  filter_idx);
4890
4891         /* New port: add it and mark its index in the bitmap */
4892         pf->vxlan_ports[idx] = port;
4893         pf->vxlan_bitmap |= (1 << idx);
4894
4895         if (!(pf->flags & I40E_FLAG_VXLAN))
4896                 pf->flags |= I40E_FLAG_VXLAN;
4897
4898         return 0;
4899 }
4900
4901 static int
4902 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4903 {
4904         int idx;
4905         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4906
4907         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4908                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4909                 return -EINVAL;
4910         }
4911
4912         idx = i40e_get_vxlan_port_idx(pf, port);
4913
4914         if (idx < 0) {
4915                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4916                 return -EINVAL;
4917         }
4918
4919         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4920                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4921                 return -1;
4922         }
4923
4924         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4925                         port, idx);
4926
4927         pf->vxlan_ports[idx] = 0;
4928         pf->vxlan_bitmap &= ~(1 << idx);
4929
4930         if (!pf->vxlan_bitmap)
4931                 pf->flags &= ~I40E_FLAG_VXLAN;
4932
4933         return 0;
4934 }
4935
4936 /* Add UDP tunneling port */
4937 static int
4938 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4939                         struct rte_eth_udp_tunnel *udp_tunnel)
4940 {
4941         int ret = 0;
4942         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4943
4944         if (udp_tunnel == NULL)
4945                 return -EINVAL;
4946
4947         switch (udp_tunnel->prot_type) {
4948         case RTE_TUNNEL_TYPE_VXLAN:
4949                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4950                 break;
4951
4952         case RTE_TUNNEL_TYPE_GENEVE:
4953         case RTE_TUNNEL_TYPE_TEREDO:
4954                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4955                 ret = -1;
4956                 break;
4957
4958         default:
4959                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4960                 ret = -1;
4961                 break;
4962         }
4963
4964         return ret;
4965 }
4966
4967 /* Remove UDP tunneling port */
4968 static int
4969 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4970                         struct rte_eth_udp_tunnel *udp_tunnel)
4971 {
4972         int ret = 0;
4973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4974
4975         if (udp_tunnel == NULL)
4976                 return -EINVAL;
4977
4978         switch (udp_tunnel->prot_type) {
4979         case RTE_TUNNEL_TYPE_VXLAN:
4980                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4981                 break;
4982         case RTE_TUNNEL_TYPE_GENEVE:
4983         case RTE_TUNNEL_TYPE_TEREDO:
4984                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4985                 ret = -1;
4986                 break;
4987         default:
4988                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4989                 ret = -1;
4990                 break;
4991         }
4992
4993         return ret;
4994 }
4995
4996 /* Calculate the maximum number of contiguous PF queues that are configured */
4997 static int
4998 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4999 {
5000         struct rte_eth_dev_data *data = pf->dev_data;
5001         int i, num;
5002         struct i40e_rx_queue *rxq;
5003
5004         num = 0;
5005         for (i = 0; i < pf->lan_nb_qps; i++) {
5006                 rxq = data->rx_queues[i];
5007                 if (rxq && rxq->q_set)
5008                         num++;
5009                 else
5010                         break;
5011         }
5012
5013         return num;
5014 }
5015
5016 /* Configure RSS */
5017 static int
5018 i40e_pf_config_rss(struct i40e_pf *pf)
5019 {
5020         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5021         struct rte_eth_rss_conf rss_conf;
5022         uint32_t i, lut = 0;
5023         uint16_t j, num;
5024
5025         /*
5026          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5027          * It's necessary to calulate the actual PF queues that are configured.
5028          */
5029         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5030                 num = i40e_pf_calc_configured_queues_num(pf);
5031                 num = i40e_align_floor(num);
5032         } else
5033                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5034
5035         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5036                         num);
5037
5038         if (num == 0) {
5039                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5040                 return -ENOTSUP;
5041         }
5042
5043         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5044                 if (j == num)
5045                         j = 0;
5046                 lut = (lut << 8) | (j & ((0x1 <<
5047                         hw->func_caps.rss_table_entry_width) - 1));
5048                 if ((i & 3) == 3)
5049                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5050         }
5051
5052         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5053         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5054                 i40e_pf_disable_rss(pf);
5055                 return 0;
5056         }
5057         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5058                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5059                 /* Random default keys */
5060                 static uint32_t rss_key_default[] = {0x6b793944,
5061                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5062                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5063                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5064
5065                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5066                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5067                                                         sizeof(uint32_t);
5068         }
5069
5070         return i40e_hw_rss_hash_set(hw, &rss_conf);
5071 }
5072
5073 static int
5074 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5075                         struct rte_eth_tunnel_filter_conf *filter)
5076 {
5077         if (pf == NULL || filter == NULL) {
5078                 PMD_DRV_LOG(ERR, "Invalid parameter");
5079                 return -EINVAL;
5080         }
5081
5082         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5083                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5084                 return -EINVAL;
5085         }
5086
5087         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5088                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5089                 return -EINVAL;
5090         }
5091
5092         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5093                 (is_zero_ether_addr(filter->outer_mac))) {
5094                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5095                 return -EINVAL;
5096         }
5097
5098         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5099                 (is_zero_ether_addr(filter->inner_mac))) {
5100                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5101                 return -EINVAL;
5102         }
5103
5104         return 0;
5105 }
5106
5107 static int
5108 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5109                         void *arg)
5110 {
5111         struct rte_eth_tunnel_filter_conf *filter;
5112         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5113         int ret = I40E_SUCCESS;
5114
5115         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5116
5117         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5118                 return I40E_ERR_PARAM;
5119
5120         switch (filter_op) {
5121         case RTE_ETH_FILTER_NOP:
5122                 if (!(pf->flags & I40E_FLAG_VXLAN))
5123                         ret = I40E_NOT_SUPPORTED;
5124         case RTE_ETH_FILTER_ADD:
5125                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5126                 break;
5127         case RTE_ETH_FILTER_DELETE:
5128                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5129                 break;
5130         default:
5131                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5132                 ret = I40E_ERR_PARAM;
5133                 break;
5134         }
5135
5136         return ret;
5137 }
5138
5139 static int
5140 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5141 {
5142         int ret = 0;
5143         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5144
5145         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5146                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5147                 return -ENOTSUP;
5148         }
5149
5150         /* RSS setup */
5151         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5152                 ret = i40e_pf_config_rss(pf);
5153         else
5154                 i40e_pf_disable_rss(pf);
5155
5156         return ret;
5157 }
5158
5159 /* Get the symmetric hash enable configurations per port */
5160 static void
5161 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5162 {
5163         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5164
5165         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5166 }
5167
5168 /* Set the symmetric hash enable configurations per port */
5169 static void
5170 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5171 {
5172         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5173
5174         if (enable > 0) {
5175                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5176                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5177                                                         "been enabled");
5178                         return;
5179                 }
5180                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5181         } else {
5182                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5183                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5184                                                         "been disabled");
5185                         return;
5186                 }
5187                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5188         }
5189         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5190         I40E_WRITE_FLUSH(hw);
5191 }
5192
5193 /*
5194  * Get global configurations of hash function type and symmetric hash enable
5195  * per flow type (pctype). Note that global configuration means it affects all
5196  * the ports on the same NIC.
5197  */
5198 static int
5199 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5200                                    struct rte_eth_hash_global_conf *g_cfg)
5201 {
5202         uint32_t reg, mask = I40E_FLOW_TYPES;
5203         uint16_t i;
5204         enum i40e_filter_pctype pctype;
5205
5206         memset(g_cfg, 0, sizeof(*g_cfg));
5207         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5208         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5209                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5210         else
5211                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5212         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5213                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5214
5215         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5216                 if (!(mask & (1UL << i)))
5217                         continue;
5218                 mask &= ~(1UL << i);
5219                 /* Bit set indicats the coresponding flow type is supported */
5220                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5221                 pctype = i40e_flowtype_to_pctype(i);
5222                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5223                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5224                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5225         }
5226
5227         return 0;
5228 }
5229
5230 static int
5231 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5232 {
5233         uint32_t i;
5234         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5235
5236         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5237                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5238                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5239                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5240                                                 g_cfg->hash_func);
5241                 return -EINVAL;
5242         }
5243
5244         /*
5245          * As i40e supports less than 32 flow types, only first 32 bits need to
5246          * be checked.
5247          */
5248         mask0 = g_cfg->valid_bit_mask[0];
5249         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5250                 if (i == 0) {
5251                         /* Check if any unsupported flow type configured */
5252                         if ((mask0 | i40e_mask) ^ i40e_mask)
5253                                 goto mask_err;
5254                 } else {
5255                         if (g_cfg->valid_bit_mask[i])
5256                                 goto mask_err;
5257                 }
5258         }
5259
5260         return 0;
5261
5262 mask_err:
5263         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5264
5265         return -EINVAL;
5266 }
5267
5268 /*
5269  * Set global configurations of hash function type and symmetric hash enable
5270  * per flow type (pctype). Note any modifying global configuration will affect
5271  * all the ports on the same NIC.
5272  */
5273 static int
5274 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5275                                    struct rte_eth_hash_global_conf *g_cfg)
5276 {
5277         int ret;
5278         uint16_t i;
5279         uint32_t reg;
5280         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5281         enum i40e_filter_pctype pctype;
5282
5283         /* Check the input parameters */
5284         ret = i40e_hash_global_config_check(g_cfg);
5285         if (ret < 0)
5286                 return ret;
5287
5288         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5289                 if (!(mask0 & (1UL << i)))
5290                         continue;
5291                 mask0 &= ~(1UL << i);
5292                 pctype = i40e_flowtype_to_pctype(i);
5293                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5294                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5295                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5296         }
5297
5298         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5299         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5300                 /* Toeplitz */
5301                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5302                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5303                                                                 "Toeplitz");
5304                         goto out;
5305                 }
5306                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5307         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5308                 /* Simple XOR */
5309                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5310                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5311                                                         "Simple XOR");
5312                         goto out;
5313                 }
5314                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5315         } else
5316                 /* Use the default, and keep it as it is */
5317                 goto out;
5318
5319         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5320
5321 out:
5322         I40E_WRITE_FLUSH(hw);
5323
5324         return 0;
5325 }
5326
5327 static int
5328 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5329 {
5330         int ret = 0;
5331
5332         if (!hw || !info) {
5333                 PMD_DRV_LOG(ERR, "Invalid pointer");
5334                 return -EFAULT;
5335         }
5336
5337         switch (info->info_type) {
5338         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5339                 i40e_get_symmetric_hash_enable_per_port(hw,
5340                                         &(info->info.enable));
5341                 break;
5342         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5343                 ret = i40e_get_hash_filter_global_config(hw,
5344                                 &(info->info.global_conf));
5345                 break;
5346         default:
5347                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5348                                                         info->info_type);
5349                 ret = -EINVAL;
5350                 break;
5351         }
5352
5353         return ret;
5354 }
5355
5356 static int
5357 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5358 {
5359         int ret = 0;
5360
5361         if (!hw || !info) {
5362                 PMD_DRV_LOG(ERR, "Invalid pointer");
5363                 return -EFAULT;
5364         }
5365
5366         switch (info->info_type) {
5367         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5368                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5369                 break;
5370         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5371                 ret = i40e_set_hash_filter_global_config(hw,
5372                                 &(info->info.global_conf));
5373                 break;
5374         default:
5375                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5376                                                         info->info_type);
5377                 ret = -EINVAL;
5378                 break;
5379         }
5380
5381         return ret;
5382 }
5383
5384 /* Operations for hash function */
5385 static int
5386 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5387                       enum rte_filter_op filter_op,
5388                       void *arg)
5389 {
5390         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391         int ret = 0;
5392
5393         switch (filter_op) {
5394         case RTE_ETH_FILTER_NOP:
5395                 break;
5396         case RTE_ETH_FILTER_GET:
5397                 ret = i40e_hash_filter_get(hw,
5398                         (struct rte_eth_hash_filter_info *)arg);
5399                 break;
5400         case RTE_ETH_FILTER_SET:
5401                 ret = i40e_hash_filter_set(hw,
5402                         (struct rte_eth_hash_filter_info *)arg);
5403                 break;
5404         default:
5405                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5406                                                                 filter_op);
5407                 ret = -ENOTSUP;
5408                 break;
5409         }
5410
5411         return ret;
5412 }
5413
5414 /*
5415  * Configure ethertype filter, which can director packet by filtering
5416  * with mac address and ether_type or only ether_type
5417  */
5418 static int
5419 i40e_ethertype_filter_set(struct i40e_pf *pf,
5420                         struct rte_eth_ethertype_filter *filter,
5421                         bool add)
5422 {
5423         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5424         struct i40e_control_filter_stats stats;
5425         uint16_t flags = 0;
5426         int ret;
5427
5428         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5429                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5430                 return -EINVAL;
5431         }
5432         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5433                 filter->ether_type == ETHER_TYPE_IPv6) {
5434                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5435                         " control packet filter.", filter->ether_type);
5436                 return -EINVAL;
5437         }
5438         if (filter->ether_type == ETHER_TYPE_VLAN)
5439                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5440                         " not supported.");
5441
5442         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5443                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5444         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5445                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5446         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5447
5448         memset(&stats, 0, sizeof(stats));
5449         ret = i40e_aq_add_rem_control_packet_filter(hw,
5450                         filter->mac_addr.addr_bytes,
5451                         filter->ether_type, flags,
5452                         pf->main_vsi->seid,
5453                         filter->queue, add, &stats, NULL);
5454
5455         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5456                          " mac_etype_used = %u, etype_used = %u,"
5457                          " mac_etype_free = %u, etype_free = %u\n",
5458                          ret, stats.mac_etype_used, stats.etype_used,
5459                          stats.mac_etype_free, stats.etype_free);
5460         if (ret < 0)
5461                 return -ENOSYS;
5462         return 0;
5463 }
5464
5465 /*
5466  * Handle operations for ethertype filter.
5467  */
5468 static int
5469 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5470                                 enum rte_filter_op filter_op,
5471                                 void *arg)
5472 {
5473         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5474         int ret = 0;
5475
5476         if (filter_op == RTE_ETH_FILTER_NOP)
5477                 return ret;
5478
5479         if (arg == NULL) {
5480                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5481                             filter_op);
5482                 return -EINVAL;
5483         }
5484
5485         switch (filter_op) {
5486         case RTE_ETH_FILTER_ADD:
5487                 ret = i40e_ethertype_filter_set(pf,
5488                         (struct rte_eth_ethertype_filter *)arg,
5489                         TRUE);
5490                 break;
5491         case RTE_ETH_FILTER_DELETE:
5492                 ret = i40e_ethertype_filter_set(pf,
5493                         (struct rte_eth_ethertype_filter *)arg,
5494                         FALSE);
5495                 break;
5496         default:
5497                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5498                 ret = -ENOSYS;
5499                 break;
5500         }
5501         return ret;
5502 }
5503
5504 static int
5505 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5506                      enum rte_filter_type filter_type,
5507                      enum rte_filter_op filter_op,
5508                      void *arg)
5509 {
5510         int ret = 0;
5511
5512         if (dev == NULL)
5513                 return -EINVAL;
5514
5515         switch (filter_type) {
5516         case RTE_ETH_FILTER_HASH:
5517                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5518                 break;
5519         case RTE_ETH_FILTER_MACVLAN:
5520                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5521                 break;
5522         case RTE_ETH_FILTER_ETHERTYPE:
5523                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5524                 break;
5525         case RTE_ETH_FILTER_TUNNEL:
5526                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5527                 break;
5528         case RTE_ETH_FILTER_FDIR:
5529                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5530                 break;
5531         default:
5532                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5533                                                         filter_type);
5534                 ret = -EINVAL;
5535                 break;
5536         }
5537
5538         return ret;
5539 }
5540
5541 /*
5542  * As some registers wouldn't be reset unless a global hardware reset,
5543  * hardware initialization is needed to put those registers into an
5544  * expected initial state.
5545  */
5546 static void
5547 i40e_hw_init(struct i40e_hw *hw)
5548 {
5549         /* clear the PF Queue Filter control register */
5550         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5551
5552         /* Disable symmetric hash per port */
5553         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5554 }
5555
5556 enum i40e_filter_pctype
5557 i40e_flowtype_to_pctype(uint16_t flow_type)
5558 {
5559         static const enum i40e_filter_pctype pctype_table[] = {
5560                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5561                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5562                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5563                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5564                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5565                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5566                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5567                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5568                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5569                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5570                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5571                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5572                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5573                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5574                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5575                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5576                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5577                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5578                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5579         };
5580
5581         return pctype_table[flow_type];
5582 }
5583
5584 uint16_t
5585 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5586 {
5587         static const uint16_t flowtype_table[] = {
5588                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5589                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5590                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5591                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5592                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5593                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5594                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5595                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5596                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5597                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5598                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5599                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5600                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5601                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5602                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5603                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5604                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5605                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5606                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5607         };
5608
5609         return flowtype_table[pctype];
5610 }
5611
5612 static int
5613 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5614 {
5615         struct i40e_aq_desc desc;
5616         enum i40e_status_code status;
5617
5618         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5619         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5620         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5621         if (status < 0)
5622                 return status;
5623
5624         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5625                                         (CHAR_BIT * sizeof(uint32_t))) +
5626                                 rte_le_to_cpu_32(desc.params.internal.param3);
5627
5628         return status;
5629 }
5630
5631 /*
5632  * On X710, performance number is far from the expectation on recent firmware
5633  * versions; on XL710, performance number is also far from the expectation on
5634  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5635  * mode is enabled and port MAC address is equal to the packet destination MAC
5636  * address. The fix for this issue may not be integrated in the following
5637  * firmware version. So the workaround in software driver is needed. It needs
5638  * to modify the initial values of 3 internal only registers for both X710 and
5639  * XL710. Note that the values for X710 or XL710 could be different, and the
5640  * workaround can be removed when it is fixed in firmware in the future.
5641  */
5642
5643 /* For both X710 and XL710 */
5644 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5645 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5646
5647 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5648 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5649
5650 /* For X710 */
5651 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5652 /* For XL710 */
5653 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5654 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5655
5656 static void
5657 i40e_configure_registers(struct i40e_hw *hw)
5658 {
5659         static struct {
5660                 uint32_t addr;
5661                 uint64_t val;
5662         } reg_table[] = {
5663                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5664                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5665                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5666         };
5667         uint64_t reg;
5668         uint32_t i;
5669         int ret;
5670
5671         for (i = 0; i < RTE_DIM(reg_table); i++) {
5672                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5673                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5674                                 reg_table[i].val =
5675                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5676                         else /* For X710 */
5677                                 reg_table[i].val =
5678                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5679                 }
5680
5681                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5682                 if (ret < 0) {
5683                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5684                                                         reg_table[i].addr);
5685                         break;
5686                 }
5687                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5688                                                 reg_table[i].addr, reg);
5689                 if (reg == reg_table[i].val)
5690                         continue;
5691
5692                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5693                                                 reg_table[i].val, NULL);
5694                 if (ret < 0) {
5695                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5696                                 "address of 0x%"PRIx32, reg_table[i].val,
5697                                                         reg_table[i].addr);
5698                         break;
5699                 }
5700                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5701                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5702         }
5703 }