4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds*/
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 static int eth_i40e_dev_init(\
97 __attribute__((unused)) struct eth_driver *eth_drv,
98 struct rte_eth_dev *eth_dev);
99 static int i40e_dev_configure(struct rte_eth_dev *dev);
100 static int i40e_dev_start(struct rte_eth_dev *dev);
101 static void i40e_dev_stop(struct rte_eth_dev *dev);
102 static void i40e_dev_close(struct rte_eth_dev *dev);
103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
110 struct rte_eth_stats *stats);
111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
117 struct rte_eth_dev_info *dev_info);
118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
130 struct rte_eth_fc_conf *fc_conf);
131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_pfc_conf *pfc_conf);
133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
134 struct ether_addr *mac_addr,
137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
139 struct rte_eth_rss_reta_entry64 *reta_conf,
141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
142 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40e_get_cap(struct i40e_hw *hw);
146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
147 static int i40e_pf_setup(struct i40e_pf *pf);
148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
151 bool offset_loaded, uint64_t *offset, uint64_t *stat);
152 static void i40e_stat_update_48(struct i40e_hw *hw,
158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
159 static void i40e_dev_interrupt_handler(
160 __rte_unused struct rte_intr_handle *handle, void *param);
161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
162 uint32_t base, uint32_t num);
163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
169 static int i40e_veb_release(struct i40e_veb *veb);
170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
171 struct i40e_vsi *vsi);
172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
175 struct i40e_macvlan_filter *mv_f,
177 struct ether_addr *addr);
178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
179 struct i40e_macvlan_filter *mv_f,
182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
184 struct rte_eth_rss_conf *rss_conf);
185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
186 struct rte_eth_rss_conf *rss_conf);
187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
188 struct rte_eth_udp_tunnel *udp_tunnel);
189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
190 struct rte_eth_udp_tunnel *udp_tunnel);
191 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
192 struct rte_eth_ethertype_filter *filter,
194 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
195 enum rte_filter_op filter_op,
197 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
198 enum rte_filter_type filter_type,
199 enum rte_filter_op filter_op,
202 /* Default hash key buffer for RSS */
203 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
205 static struct rte_pci_id pci_id_i40e_map[] = {
206 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
207 #include "rte_pci_dev_ids.h"
208 { .vendor_id = 0, /* sentinel */ },
211 static struct eth_dev_ops i40e_eth_dev_ops = {
212 .dev_configure = i40e_dev_configure,
213 .dev_start = i40e_dev_start,
214 .dev_stop = i40e_dev_stop,
215 .dev_close = i40e_dev_close,
216 .promiscuous_enable = i40e_dev_promiscuous_enable,
217 .promiscuous_disable = i40e_dev_promiscuous_disable,
218 .allmulticast_enable = i40e_dev_allmulticast_enable,
219 .allmulticast_disable = i40e_dev_allmulticast_disable,
220 .dev_set_link_up = i40e_dev_set_link_up,
221 .dev_set_link_down = i40e_dev_set_link_down,
222 .link_update = i40e_dev_link_update,
223 .stats_get = i40e_dev_stats_get,
224 .stats_reset = i40e_dev_stats_reset,
225 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
226 .dev_infos_get = i40e_dev_info_get,
227 .vlan_filter_set = i40e_vlan_filter_set,
228 .vlan_tpid_set = i40e_vlan_tpid_set,
229 .vlan_offload_set = i40e_vlan_offload_set,
230 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
231 .vlan_pvid_set = i40e_vlan_pvid_set,
232 .rx_queue_start = i40e_dev_rx_queue_start,
233 .rx_queue_stop = i40e_dev_rx_queue_stop,
234 .tx_queue_start = i40e_dev_tx_queue_start,
235 .tx_queue_stop = i40e_dev_tx_queue_stop,
236 .rx_queue_setup = i40e_dev_rx_queue_setup,
237 .rx_queue_release = i40e_dev_rx_queue_release,
238 .rx_queue_count = i40e_dev_rx_queue_count,
239 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
240 .tx_queue_setup = i40e_dev_tx_queue_setup,
241 .tx_queue_release = i40e_dev_tx_queue_release,
242 .dev_led_on = i40e_dev_led_on,
243 .dev_led_off = i40e_dev_led_off,
244 .flow_ctrl_set = i40e_flow_ctrl_set,
245 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
246 .mac_addr_add = i40e_macaddr_add,
247 .mac_addr_remove = i40e_macaddr_remove,
248 .reta_update = i40e_dev_rss_reta_update,
249 .reta_query = i40e_dev_rss_reta_query,
250 .rss_hash_update = i40e_dev_rss_hash_update,
251 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
252 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
253 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
254 .filter_ctrl = i40e_dev_filter_ctrl,
257 static struct eth_driver rte_i40e_pmd = {
259 .name = "rte_i40e_pmd",
260 .id_table = pci_id_i40e_map,
261 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
263 .eth_dev_init = eth_i40e_dev_init,
264 .dev_private_size = sizeof(struct i40e_adapter),
268 i40e_align_floor(int n)
272 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
276 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
277 struct rte_eth_link *link)
279 struct rte_eth_link *dst = link;
280 struct rte_eth_link *src = &(dev->data->dev_link);
282 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
283 *(uint64_t *)src) == 0)
290 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
291 struct rte_eth_link *link)
293 struct rte_eth_link *dst = &(dev->data->dev_link);
294 struct rte_eth_link *src = link;
296 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
297 *(uint64_t *)src) == 0)
304 * Driver initialization routine.
305 * Invoked once at EAL init time.
306 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
309 rte_i40e_pmd_init(const char *name __rte_unused,
310 const char *params __rte_unused)
312 PMD_INIT_FUNC_TRACE();
313 rte_eth_driver_register(&rte_i40e_pmd);
318 static struct rte_driver rte_i40e_driver = {
320 .init = rte_i40e_pmd_init,
323 PMD_REGISTER_DRIVER(rte_i40e_driver);
326 * Initialize registers for flexible payload, which should be set by NVM.
327 * This should be removed from code once it is fixed in NVM.
329 #ifndef I40E_GLQF_ORT
330 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
332 #ifndef I40E_GLQF_PIT
333 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
336 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
338 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
339 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
340 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
341 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
342 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
343 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
344 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
345 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
346 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
347 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
349 /* GLQF_PIT Registers */
350 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
351 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
355 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
356 struct rte_eth_dev *dev)
358 struct rte_pci_device *pci_dev;
359 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
360 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
361 struct i40e_vsi *vsi;
366 PMD_INIT_FUNC_TRACE();
368 dev->dev_ops = &i40e_eth_dev_ops;
369 dev->rx_pkt_burst = i40e_recv_pkts;
370 dev->tx_pkt_burst = i40e_xmit_pkts;
372 /* for secondary processes, we don't initialise any further as primary
373 * has already done this work. Only check we don't need a different
375 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
376 if (dev->data->scattered_rx)
377 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
380 pci_dev = dev->pci_dev;
381 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
382 pf->adapter->eth_dev = dev;
383 pf->dev_data = dev->data;
385 hw->back = I40E_PF_TO_ADAPTER(pf);
386 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
388 PMD_INIT_LOG(ERR, "Hardware is not available, "
389 "as address is NULL");
393 hw->vendor_id = pci_dev->id.vendor_id;
394 hw->device_id = pci_dev->id.device_id;
395 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
396 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
397 hw->bus.device = pci_dev->addr.devid;
398 hw->bus.func = pci_dev->addr.function;
400 /* Make sure all is clean before doing PF reset */
403 /* Reset here to make sure all is clean for each PF */
404 ret = i40e_pf_reset(hw);
406 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
410 /* Initialize the shared code (base driver) */
411 ret = i40e_init_shared_code(hw);
413 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
418 * To work around the NVM issue,initialize registers
419 * for flexible payload by software.
420 * It should be removed once issues are fixed in NVM.
422 i40e_flex_payload_reg_init(hw);
424 /* Initialize the parameters for adminq */
425 i40e_init_adminq_parameter(hw);
426 ret = i40e_init_adminq(hw);
427 if (ret != I40E_SUCCESS) {
428 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
431 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
432 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
433 hw->aq.api_maj_ver, hw->aq.api_min_ver,
434 ((hw->nvm.version >> 12) & 0xf),
435 ((hw->nvm.version >> 4) & 0xff),
436 (hw->nvm.version & 0xf), hw->nvm.eetrack);
439 ret = i40e_aq_stop_lldp(hw, true, NULL);
440 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
441 PMD_INIT_LOG(INFO, "Failed to stop lldp");
444 i40e_clear_pxe_mode(hw);
446 /* Get hw capabilities */
447 ret = i40e_get_cap(hw);
448 if (ret != I40E_SUCCESS) {
449 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
450 goto err_get_capabilities;
453 /* Initialize parameters for PF */
454 ret = i40e_pf_parameter_init(dev);
456 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
457 goto err_parameter_init;
460 /* Initialize the queue management */
461 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
463 PMD_INIT_LOG(ERR, "Failed to init queue pool");
464 goto err_qp_pool_init;
466 ret = i40e_res_pool_init(&pf->msix_pool, 1,
467 hw->func_caps.num_msix_vectors - 1);
469 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
470 goto err_msix_pool_init;
473 /* Initialize lan hmc */
474 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
475 hw->func_caps.num_rx_qp, 0, 0);
476 if (ret != I40E_SUCCESS) {
477 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
478 goto err_init_lan_hmc;
481 /* Configure lan hmc */
482 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
483 if (ret != I40E_SUCCESS) {
484 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
485 goto err_configure_lan_hmc;
488 /* Get and check the mac address */
489 i40e_get_mac_addr(hw, hw->mac.addr);
490 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
491 PMD_INIT_LOG(ERR, "mac address is not valid");
493 goto err_get_mac_addr;
495 /* Copy the permanent MAC address */
496 ether_addr_copy((struct ether_addr *) hw->mac.addr,
497 (struct ether_addr *) hw->mac.perm_addr);
499 /* Disable flow control */
500 hw->fc.requested_mode = I40E_FC_NONE;
501 i40e_set_fc(hw, &aq_fail, TRUE);
503 /* PF setup, which includes VSI setup */
504 ret = i40e_pf_setup(pf);
506 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
507 goto err_setup_pf_switch;
512 /* Disable double vlan by default */
513 i40e_vsi_config_double_vlan(vsi, FALSE);
515 if (!vsi->max_macaddrs)
516 len = ETHER_ADDR_LEN;
518 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
520 /* Should be after VSI initialized */
521 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
522 if (!dev->data->mac_addrs) {
523 PMD_INIT_LOG(ERR, "Failed to allocated memory "
524 "for storing mac address");
527 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
528 &dev->data->mac_addrs[0]);
530 /* initialize pf host driver to setup SRIOV resource if applicable */
531 i40e_pf_host_init(dev);
533 /* register callback func to eal lib */
534 rte_intr_callback_register(&(pci_dev->intr_handle),
535 i40e_dev_interrupt_handler, (void *)dev);
537 /* configure and enable device interrupt */
538 i40e_pf_config_irq0(hw);
539 i40e_pf_enable_irq0(hw);
541 /* enable uio intr after callback register */
542 rte_intr_enable(&(pci_dev->intr_handle));
547 i40e_vsi_release(pf->main_vsi);
549 i40e_fdir_teardown(pf);
551 err_configure_lan_hmc:
552 (void)i40e_shutdown_lan_hmc(hw);
554 i40e_res_pool_destroy(&pf->msix_pool);
556 i40e_res_pool_destroy(&pf->qp_pool);
559 err_get_capabilities:
560 (void)i40e_shutdown_adminq(hw);
566 i40e_dev_configure(struct rte_eth_dev *dev)
569 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
572 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
573 * RSS setting have different requirements.
574 * General PMD driver call sequence are NIC init, configure,
575 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
576 * will try to lookup the VSI that specific queue belongs to if VMDQ
577 * applicable. So, VMDQ setting has to be done before
578 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
579 * For RSS setting, it will try to calculate actual configured RX queue
580 * number, which will be available after rx_queue_setup(). dev_start()
581 * function is good to place RSS setup.
583 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
584 ret = i40e_vmdq_setup(dev);
589 return i40e_dev_init_vlan(dev);
593 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
595 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
596 uint16_t msix_vect = vsi->msix_intr;
599 for (i = 0; i < vsi->nb_qps; i++) {
600 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
601 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
605 if (vsi->type != I40E_VSI_SRIOV) {
606 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
607 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
611 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
612 vsi->user_param + (msix_vect - 1);
614 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
616 I40E_WRITE_FLUSH(hw);
619 static inline uint16_t
620 i40e_calc_itr_interval(int16_t interval)
622 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
623 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
625 /* Convert to hardware count, as writing each 1 represents 2 us */
630 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
633 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
634 uint16_t msix_vect = vsi->msix_intr;
637 for (i = 0; i < vsi->nb_qps; i++)
638 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
640 /* Bind all RX queues to allocated MSIX interrupt */
641 for (i = 0; i < vsi->nb_qps; i++) {
642 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
643 I40E_QINT_RQCTL_ITR_INDX_MASK |
644 ((vsi->base_queue + i + 1) <<
645 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
646 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
647 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
649 if (i == vsi->nb_qps - 1)
650 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
651 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
654 /* Write first RX queue to Link list register as the head element */
655 if (vsi->type != I40E_VSI_SRIOV) {
657 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
659 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
661 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
662 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
664 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
665 msix_vect - 1), interval);
667 #ifndef I40E_GLINT_CTL
668 #define I40E_GLINT_CTL 0x0003F800
669 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
671 /* Disable auto-mask on enabling of all none-zero interrupt */
672 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
673 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
677 /* num_msix_vectors_vf needs to minus irq0 */
678 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
679 vsi->user_param + (msix_vect - 1);
681 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
682 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
683 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
686 I40E_WRITE_FLUSH(hw);
690 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
692 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
693 uint16_t interval = i40e_calc_itr_interval(\
694 RTE_LIBRTE_I40E_ITR_INTERVAL);
696 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
697 I40E_PFINT_DYN_CTLN_INTENA_MASK |
698 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
699 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
700 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
704 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
706 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
708 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
711 static inline uint8_t
712 i40e_parse_link_speed(uint16_t eth_link_speed)
714 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
716 switch (eth_link_speed) {
717 case ETH_LINK_SPEED_40G:
718 link_speed = I40E_LINK_SPEED_40GB;
720 case ETH_LINK_SPEED_20G:
721 link_speed = I40E_LINK_SPEED_20GB;
723 case ETH_LINK_SPEED_10G:
724 link_speed = I40E_LINK_SPEED_10GB;
726 case ETH_LINK_SPEED_1000:
727 link_speed = I40E_LINK_SPEED_1GB;
729 case ETH_LINK_SPEED_100:
730 link_speed = I40E_LINK_SPEED_100MB;
738 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
740 enum i40e_status_code status;
741 struct i40e_aq_get_phy_abilities_resp phy_ab;
742 struct i40e_aq_set_phy_config phy_conf;
743 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
744 I40E_AQ_PHY_FLAG_PAUSE_RX |
745 I40E_AQ_PHY_FLAG_LOW_POWER;
746 const uint8_t advt = I40E_LINK_SPEED_40GB |
747 I40E_LINK_SPEED_10GB |
748 I40E_LINK_SPEED_1GB |
749 I40E_LINK_SPEED_100MB;
752 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
757 memset(&phy_conf, 0, sizeof(phy_conf));
759 /* bits 0-2 use the values from get_phy_abilities_resp */
761 abilities |= phy_ab.abilities & mask;
763 /* update ablities and speed */
764 if (abilities & I40E_AQ_PHY_AN_ENABLED)
765 phy_conf.link_speed = advt;
767 phy_conf.link_speed = force_speed;
769 phy_conf.abilities = abilities;
771 /* use get_phy_abilities_resp value for the rest */
772 phy_conf.phy_type = phy_ab.phy_type;
773 phy_conf.eee_capability = phy_ab.eee_capability;
774 phy_conf.eeer = phy_ab.eeer_val;
775 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
777 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
778 phy_ab.abilities, phy_ab.link_speed);
779 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
780 phy_conf.abilities, phy_conf.link_speed);
782 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
790 i40e_apply_link_speed(struct rte_eth_dev *dev)
793 uint8_t abilities = 0;
794 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
795 struct rte_eth_conf *conf = &dev->data->dev_conf;
797 speed = i40e_parse_link_speed(conf->link_speed);
798 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
799 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
800 abilities |= I40E_AQ_PHY_AN_ENABLED;
802 abilities |= I40E_AQ_PHY_LINK_ENABLED;
804 return i40e_phy_conf_link(hw, abilities, speed);
808 i40e_dev_start(struct rte_eth_dev *dev)
810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
812 struct i40e_vsi *main_vsi = pf->main_vsi;
815 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
816 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
817 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
818 dev->data->dev_conf.link_duplex,
824 ret = i40e_dev_rxtx_init(pf);
825 if (ret != I40E_SUCCESS) {
826 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
830 /* Map queues with MSIX interrupt */
831 i40e_vsi_queues_bind_intr(main_vsi);
832 i40e_vsi_enable_queues_intr(main_vsi);
834 /* Map VMDQ VSI queues with MSIX interrupt */
835 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
836 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
837 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
840 ret = i40e_fdir_configure(dev);
842 PMD_DRV_LOG(ERR, "failed to configure fdir.");
846 /* enable FDIR MSIX interrupt */
847 if (pf->flags & I40E_FLAG_FDIR) {
848 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
849 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
852 /* Enable all queues which have been configured */
853 ret = i40e_dev_switch_queues(pf, TRUE);
854 if (ret != I40E_SUCCESS) {
855 PMD_DRV_LOG(ERR, "Failed to enable VSI");
859 /* Enable receiving broadcast packets */
860 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
861 if (ret != I40E_SUCCESS)
862 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
864 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
865 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
867 if (ret != I40E_SUCCESS)
868 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
871 /* Apply link configure */
872 ret = i40e_apply_link_speed(dev);
873 if (I40E_SUCCESS != ret) {
874 PMD_DRV_LOG(ERR, "Fail to apply link setting");
881 i40e_dev_switch_queues(pf, FALSE);
882 i40e_dev_clear_queues(dev);
888 i40e_dev_stop(struct rte_eth_dev *dev)
890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
891 struct i40e_vsi *main_vsi = pf->main_vsi;
894 /* Disable all queues */
895 i40e_dev_switch_queues(pf, FALSE);
897 /* un-map queues with interrupt registers */
898 i40e_vsi_disable_queues_intr(main_vsi);
899 i40e_vsi_queues_unbind_intr(main_vsi);
901 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
902 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
903 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
906 if (pf->flags & I40E_FLAG_FDIR) {
907 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
908 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
910 /* Clear all queues and release memory */
911 i40e_dev_clear_queues(dev);
914 i40e_dev_set_link_down(dev);
919 i40e_dev_close(struct rte_eth_dev *dev)
921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
925 PMD_INIT_FUNC_TRACE();
929 /* Disable interrupt */
930 i40e_pf_disable_irq0(hw);
931 rte_intr_disable(&(dev->pci_dev->intr_handle));
933 /* shutdown and destroy the HMC */
934 i40e_shutdown_lan_hmc(hw);
936 /* release all the existing VSIs and VEBs */
937 i40e_fdir_teardown(pf);
938 i40e_vsi_release(pf->main_vsi);
940 /* shutdown the adminq */
941 i40e_aq_queue_shutdown(hw, true);
942 i40e_shutdown_adminq(hw);
944 i40e_res_pool_destroy(&pf->qp_pool);
945 i40e_res_pool_destroy(&pf->msix_pool);
947 /* force a PF reset to clean anything leftover */
948 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
949 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
950 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
951 I40E_WRITE_FLUSH(hw);
955 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
959 struct i40e_vsi *vsi = pf->main_vsi;
962 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
964 if (status != I40E_SUCCESS)
965 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
967 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
969 if (status != I40E_SUCCESS)
970 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
975 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
977 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
978 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
979 struct i40e_vsi *vsi = pf->main_vsi;
982 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
984 if (status != I40E_SUCCESS)
985 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
987 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
989 if (status != I40E_SUCCESS)
990 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
994 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
998 struct i40e_vsi *vsi = pf->main_vsi;
1001 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1002 if (ret != I40E_SUCCESS)
1003 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1007 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1009 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011 struct i40e_vsi *vsi = pf->main_vsi;
1014 if (dev->data->promiscuous == 1)
1015 return; /* must remain in all_multicast mode */
1017 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1018 vsi->seid, FALSE, NULL);
1019 if (ret != I40E_SUCCESS)
1020 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1024 * Set device link up.
1027 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1029 /* re-apply link speed setting */
1030 return i40e_apply_link_speed(dev);
1034 * Set device link down.
1037 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1039 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1040 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1041 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 return i40e_phy_conf_link(hw, abilities, speed);
1047 i40e_dev_link_update(struct rte_eth_dev *dev,
1048 __rte_unused int wait_to_complete)
1050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 struct i40e_link_status link_status;
1052 struct rte_eth_link link, old;
1055 memset(&link, 0, sizeof(link));
1056 memset(&old, 0, sizeof(old));
1057 memset(&link_status, 0, sizeof(link_status));
1058 rte_i40e_dev_atomic_read_link_status(dev, &old);
1060 /* Get link status information from hardware */
1061 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1062 if (status != I40E_SUCCESS) {
1063 link.link_speed = ETH_LINK_SPEED_100;
1064 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1065 PMD_DRV_LOG(ERR, "Failed to get link info");
1069 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1071 if (!link.link_status)
1074 /* i40e uses full duplex only */
1075 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1077 /* Parse the link status */
1078 switch (link_status.link_speed) {
1079 case I40E_LINK_SPEED_100MB:
1080 link.link_speed = ETH_LINK_SPEED_100;
1082 case I40E_LINK_SPEED_1GB:
1083 link.link_speed = ETH_LINK_SPEED_1000;
1085 case I40E_LINK_SPEED_10GB:
1086 link.link_speed = ETH_LINK_SPEED_10G;
1088 case I40E_LINK_SPEED_20GB:
1089 link.link_speed = ETH_LINK_SPEED_20G;
1091 case I40E_LINK_SPEED_40GB:
1092 link.link_speed = ETH_LINK_SPEED_40G;
1095 link.link_speed = ETH_LINK_SPEED_100;
1100 rte_i40e_dev_atomic_write_link_status(dev, &link);
1101 if (link.link_status == old.link_status)
1107 /* Get all the statistics of a VSI */
1109 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1111 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1112 struct i40e_eth_stats *nes = &vsi->eth_stats;
1113 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1114 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1116 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1117 vsi->offset_loaded, &oes->rx_bytes,
1119 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1120 vsi->offset_loaded, &oes->rx_unicast,
1122 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1123 vsi->offset_loaded, &oes->rx_multicast,
1124 &nes->rx_multicast);
1125 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1126 vsi->offset_loaded, &oes->rx_broadcast,
1127 &nes->rx_broadcast);
1128 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1129 &oes->rx_discards, &nes->rx_discards);
1130 /* GLV_REPC not supported */
1131 /* GLV_RMPC not supported */
1132 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1133 &oes->rx_unknown_protocol,
1134 &nes->rx_unknown_protocol);
1135 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1136 vsi->offset_loaded, &oes->tx_bytes,
1138 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1139 vsi->offset_loaded, &oes->tx_unicast,
1141 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1142 vsi->offset_loaded, &oes->tx_multicast,
1143 &nes->tx_multicast);
1144 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1145 vsi->offset_loaded, &oes->tx_broadcast,
1146 &nes->tx_broadcast);
1147 /* GLV_TDPC not supported */
1148 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1149 &oes->tx_errors, &nes->tx_errors);
1150 vsi->offset_loaded = true;
1152 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1154 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1155 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1156 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1157 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1158 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1159 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1160 nes->rx_unknown_protocol);
1161 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1162 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1163 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1164 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1165 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1166 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1167 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1171 /* Get all statistics of a port */
1173 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1176 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1177 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1179 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1181 /* Get statistics of struct i40e_eth_stats */
1182 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1183 I40E_GLPRT_GORCL(hw->port),
1184 pf->offset_loaded, &os->eth.rx_bytes,
1186 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1187 I40E_GLPRT_UPRCL(hw->port),
1188 pf->offset_loaded, &os->eth.rx_unicast,
1189 &ns->eth.rx_unicast);
1190 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1191 I40E_GLPRT_MPRCL(hw->port),
1192 pf->offset_loaded, &os->eth.rx_multicast,
1193 &ns->eth.rx_multicast);
1194 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1195 I40E_GLPRT_BPRCL(hw->port),
1196 pf->offset_loaded, &os->eth.rx_broadcast,
1197 &ns->eth.rx_broadcast);
1198 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1199 pf->offset_loaded, &os->eth.rx_discards,
1200 &ns->eth.rx_discards);
1201 /* GLPRT_REPC not supported */
1202 /* GLPRT_RMPC not supported */
1203 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1205 &os->eth.rx_unknown_protocol,
1206 &ns->eth.rx_unknown_protocol);
1207 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1208 I40E_GLPRT_GOTCL(hw->port),
1209 pf->offset_loaded, &os->eth.tx_bytes,
1211 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1212 I40E_GLPRT_UPTCL(hw->port),
1213 pf->offset_loaded, &os->eth.tx_unicast,
1214 &ns->eth.tx_unicast);
1215 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1216 I40E_GLPRT_MPTCL(hw->port),
1217 pf->offset_loaded, &os->eth.tx_multicast,
1218 &ns->eth.tx_multicast);
1219 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1220 I40E_GLPRT_BPTCL(hw->port),
1221 pf->offset_loaded, &os->eth.tx_broadcast,
1222 &ns->eth.tx_broadcast);
1223 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1224 pf->offset_loaded, &os->eth.tx_discards,
1225 &ns->eth.tx_discards);
1226 /* GLPRT_TEPC not supported */
1228 /* additional port specific stats */
1229 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1230 pf->offset_loaded, &os->tx_dropped_link_down,
1231 &ns->tx_dropped_link_down);
1232 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1233 pf->offset_loaded, &os->crc_errors,
1235 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1236 pf->offset_loaded, &os->illegal_bytes,
1237 &ns->illegal_bytes);
1238 /* GLPRT_ERRBC not supported */
1239 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1240 pf->offset_loaded, &os->mac_local_faults,
1241 &ns->mac_local_faults);
1242 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1243 pf->offset_loaded, &os->mac_remote_faults,
1244 &ns->mac_remote_faults);
1245 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1246 pf->offset_loaded, &os->rx_length_errors,
1247 &ns->rx_length_errors);
1248 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1249 pf->offset_loaded, &os->link_xon_rx,
1251 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1252 pf->offset_loaded, &os->link_xoff_rx,
1254 for (i = 0; i < 8; i++) {
1255 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1257 &os->priority_xon_rx[i],
1258 &ns->priority_xon_rx[i]);
1259 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1261 &os->priority_xoff_rx[i],
1262 &ns->priority_xoff_rx[i]);
1264 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1265 pf->offset_loaded, &os->link_xon_tx,
1267 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1268 pf->offset_loaded, &os->link_xoff_tx,
1270 for (i = 0; i < 8; i++) {
1271 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1273 &os->priority_xon_tx[i],
1274 &ns->priority_xon_tx[i]);
1275 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1277 &os->priority_xoff_tx[i],
1278 &ns->priority_xoff_tx[i]);
1279 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1281 &os->priority_xon_2_xoff[i],
1282 &ns->priority_xon_2_xoff[i]);
1284 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1285 I40E_GLPRT_PRC64L(hw->port),
1286 pf->offset_loaded, &os->rx_size_64,
1288 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1289 I40E_GLPRT_PRC127L(hw->port),
1290 pf->offset_loaded, &os->rx_size_127,
1292 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1293 I40E_GLPRT_PRC255L(hw->port),
1294 pf->offset_loaded, &os->rx_size_255,
1296 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1297 I40E_GLPRT_PRC511L(hw->port),
1298 pf->offset_loaded, &os->rx_size_511,
1300 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1301 I40E_GLPRT_PRC1023L(hw->port),
1302 pf->offset_loaded, &os->rx_size_1023,
1304 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1305 I40E_GLPRT_PRC1522L(hw->port),
1306 pf->offset_loaded, &os->rx_size_1522,
1308 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1309 I40E_GLPRT_PRC9522L(hw->port),
1310 pf->offset_loaded, &os->rx_size_big,
1312 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1313 pf->offset_loaded, &os->rx_undersize,
1315 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1316 pf->offset_loaded, &os->rx_fragments,
1318 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1319 pf->offset_loaded, &os->rx_oversize,
1321 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1322 pf->offset_loaded, &os->rx_jabber,
1324 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1325 I40E_GLPRT_PTC64L(hw->port),
1326 pf->offset_loaded, &os->tx_size_64,
1328 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1329 I40E_GLPRT_PTC127L(hw->port),
1330 pf->offset_loaded, &os->tx_size_127,
1332 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1333 I40E_GLPRT_PTC255L(hw->port),
1334 pf->offset_loaded, &os->tx_size_255,
1336 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1337 I40E_GLPRT_PTC511L(hw->port),
1338 pf->offset_loaded, &os->tx_size_511,
1340 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1341 I40E_GLPRT_PTC1023L(hw->port),
1342 pf->offset_loaded, &os->tx_size_1023,
1344 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1345 I40E_GLPRT_PTC1522L(hw->port),
1346 pf->offset_loaded, &os->tx_size_1522,
1348 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1349 I40E_GLPRT_PTC9522L(hw->port),
1350 pf->offset_loaded, &os->tx_size_big,
1352 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1354 &os->fd_sb_match, &ns->fd_sb_match);
1355 /* GLPRT_MSPDC not supported */
1356 /* GLPRT_XEC not supported */
1358 pf->offset_loaded = true;
1361 i40e_update_vsi_stats(pf->main_vsi);
1363 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1364 ns->eth.rx_broadcast;
1365 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1366 ns->eth.tx_broadcast;
1367 stats->ibytes = ns->eth.rx_bytes;
1368 stats->obytes = ns->eth.tx_bytes;
1369 stats->oerrors = ns->eth.tx_errors;
1370 stats->imcasts = ns->eth.rx_multicast;
1371 stats->fdirmatch = ns->fd_sb_match;
1374 stats->ibadcrc = ns->crc_errors;
1375 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1376 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1377 stats->imissed = ns->eth.rx_discards;
1378 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1380 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1381 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1382 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1383 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1384 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1385 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1386 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1387 ns->eth.rx_unknown_protocol);
1388 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1389 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1390 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1391 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1392 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1393 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1395 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1396 ns->tx_dropped_link_down);
1397 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1398 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1400 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1401 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1402 ns->mac_local_faults);
1403 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1404 ns->mac_remote_faults);
1405 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1406 ns->rx_length_errors);
1407 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1408 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1409 for (i = 0; i < 8; i++) {
1410 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1411 i, ns->priority_xon_rx[i]);
1412 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1413 i, ns->priority_xoff_rx[i]);
1415 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1416 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1417 for (i = 0; i < 8; i++) {
1418 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1419 i, ns->priority_xon_tx[i]);
1420 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1421 i, ns->priority_xoff_tx[i]);
1422 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1423 i, ns->priority_xon_2_xoff[i]);
1425 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1426 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1427 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1428 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1429 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1430 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1431 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1432 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1433 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1434 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1435 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1436 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1437 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1438 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1439 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1440 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1441 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1442 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1443 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1444 ns->mac_short_packet_dropped);
1445 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1446 ns->checksum_error);
1447 PMD_DRV_LOG(DEBUG, "fdir_match: %lu", ns->fd_sb_match);
1448 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1451 /* Reset the statistics */
1453 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1455 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1457 /* It results in reloading the start point of each counter */
1458 pf->offset_loaded = false;
1462 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1463 __rte_unused uint16_t queue_id,
1464 __rte_unused uint8_t stat_idx,
1465 __rte_unused uint8_t is_rx)
1467 PMD_INIT_FUNC_TRACE();
1473 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476 struct i40e_vsi *vsi = pf->main_vsi;
1478 dev_info->max_rx_queues = vsi->nb_qps;
1479 dev_info->max_tx_queues = vsi->nb_qps;
1480 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1481 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1482 dev_info->max_mac_addrs = vsi->max_macaddrs;
1483 dev_info->max_vfs = dev->pci_dev->max_vfs;
1484 dev_info->rx_offload_capa =
1485 DEV_RX_OFFLOAD_VLAN_STRIP |
1486 DEV_RX_OFFLOAD_IPV4_CKSUM |
1487 DEV_RX_OFFLOAD_UDP_CKSUM |
1488 DEV_RX_OFFLOAD_TCP_CKSUM;
1489 dev_info->tx_offload_capa =
1490 DEV_TX_OFFLOAD_VLAN_INSERT |
1491 DEV_TX_OFFLOAD_IPV4_CKSUM |
1492 DEV_TX_OFFLOAD_UDP_CKSUM |
1493 DEV_TX_OFFLOAD_TCP_CKSUM |
1494 DEV_TX_OFFLOAD_SCTP_CKSUM;
1495 dev_info->reta_size = pf->hash_lut_size;
1497 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1499 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1500 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1501 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1503 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1507 dev_info->default_txconf = (struct rte_eth_txconf) {
1509 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1510 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1511 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1513 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1514 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1515 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1516 ETH_TXQ_FLAGS_NOOFFLOADS,
1519 if (pf->flags | I40E_FLAG_VMDQ) {
1520 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1521 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1522 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1523 pf->max_nb_vmdq_vsi;
1524 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1525 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1526 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1531 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1534 struct i40e_vsi *vsi = pf->main_vsi;
1535 PMD_INIT_FUNC_TRACE();
1538 return i40e_vsi_add_vlan(vsi, vlan_id);
1540 return i40e_vsi_delete_vlan(vsi, vlan_id);
1544 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1545 __rte_unused uint16_t tpid)
1547 PMD_INIT_FUNC_TRACE();
1551 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1554 struct i40e_vsi *vsi = pf->main_vsi;
1556 if (mask & ETH_VLAN_STRIP_MASK) {
1557 /* Enable or disable VLAN stripping */
1558 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1559 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1561 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1564 if (mask & ETH_VLAN_EXTEND_MASK) {
1565 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1566 i40e_vsi_config_double_vlan(vsi, TRUE);
1568 i40e_vsi_config_double_vlan(vsi, FALSE);
1573 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1574 __rte_unused uint16_t queue,
1575 __rte_unused int on)
1577 PMD_INIT_FUNC_TRACE();
1581 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1583 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1584 struct i40e_vsi *vsi = pf->main_vsi;
1585 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1586 struct i40e_vsi_vlan_pvid_info info;
1588 memset(&info, 0, sizeof(info));
1591 info.config.pvid = pvid;
1593 info.config.reject.tagged =
1594 data->dev_conf.txmode.hw_vlan_reject_tagged;
1595 info.config.reject.untagged =
1596 data->dev_conf.txmode.hw_vlan_reject_untagged;
1599 return i40e_vsi_vlan_pvid_set(vsi, &info);
1603 i40e_dev_led_on(struct rte_eth_dev *dev)
1605 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 uint32_t mode = i40e_led_get(hw);
1609 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1615 i40e_dev_led_off(struct rte_eth_dev *dev)
1617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618 uint32_t mode = i40e_led_get(hw);
1621 i40e_led_set(hw, 0, false);
1627 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1628 __rte_unused struct rte_eth_fc_conf *fc_conf)
1630 PMD_INIT_FUNC_TRACE();
1636 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1637 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1639 PMD_INIT_FUNC_TRACE();
1644 /* Add a MAC address, and update filters */
1646 i40e_macaddr_add(struct rte_eth_dev *dev,
1647 struct ether_addr *mac_addr,
1648 __rte_unused uint32_t index,
1651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652 struct i40e_mac_filter_info mac_filter;
1653 struct i40e_vsi *vsi;
1656 /* If VMDQ not enabled or configured, return */
1657 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1658 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1659 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1664 if (pool > pf->nb_cfg_vmdq_vsi) {
1665 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1666 pool, pf->nb_cfg_vmdq_vsi);
1670 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1671 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1676 vsi = pf->vmdq[pool - 1].vsi;
1678 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1679 if (ret != I40E_SUCCESS) {
1680 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1685 /* Remove a MAC address, and update filters */
1687 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1689 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1690 struct i40e_vsi *vsi;
1691 struct rte_eth_dev_data *data = dev->data;
1692 struct ether_addr *macaddr;
1697 macaddr = &(data->mac_addrs[index]);
1699 pool_sel = dev->data->mac_pool_sel[index];
1701 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1702 if (pool_sel & (1ULL << i)) {
1706 /* No VMDQ pool enabled or configured */
1707 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1708 (i > pf->nb_cfg_vmdq_vsi)) {
1709 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1713 vsi = pf->vmdq[i - 1].vsi;
1715 ret = i40e_vsi_delete_mac(vsi, macaddr);
1718 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1725 /* Set perfect match or hash match of MAC and VLAN for a VF */
1727 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1728 struct rte_eth_mac_filter *filter,
1732 struct i40e_mac_filter_info mac_filter;
1733 struct ether_addr old_mac;
1734 struct ether_addr *new_mac;
1735 struct i40e_pf_vf *vf = NULL;
1740 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1743 hw = I40E_PF_TO_HW(pf);
1745 if (filter == NULL) {
1746 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1750 new_mac = &filter->mac_addr;
1752 if (is_zero_ether_addr(new_mac)) {
1753 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1757 vf_id = filter->dst_id;
1759 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1760 PMD_DRV_LOG(ERR, "Invalid argument.");
1763 vf = &pf->vfs[vf_id];
1765 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1766 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1771 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1772 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1774 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1777 mac_filter.filter_type = filter->filter_type;
1778 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1779 if (ret != I40E_SUCCESS) {
1780 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1783 ether_addr_copy(new_mac, &pf->dev_addr);
1785 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1787 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1788 if (ret != I40E_SUCCESS) {
1789 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1793 /* Clear device address as it has been removed */
1794 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1795 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1801 /* MAC filter handle */
1803 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1806 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1807 struct rte_eth_mac_filter *filter;
1808 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1809 int ret = I40E_NOT_SUPPORTED;
1811 filter = (struct rte_eth_mac_filter *)(arg);
1813 switch (filter_op) {
1814 case RTE_ETH_FILTER_NOP:
1817 case RTE_ETH_FILTER_ADD:
1818 i40e_pf_disable_irq0(hw);
1820 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1821 i40e_pf_enable_irq0(hw);
1823 case RTE_ETH_FILTER_DELETE:
1824 i40e_pf_disable_irq0(hw);
1826 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1827 i40e_pf_enable_irq0(hw);
1830 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1831 ret = I40E_ERR_PARAM;
1839 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1840 struct rte_eth_rss_reta_entry64 *reta_conf,
1843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846 uint16_t i, j, lut_size = pf->hash_lut_size;
1847 uint16_t idx, shift;
1850 if (reta_size != lut_size ||
1851 reta_size > ETH_RSS_RETA_SIZE_512) {
1852 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1853 "(%d) doesn't match the number hardware can supported "
1854 "(%d)\n", reta_size, lut_size);
1858 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1859 idx = i / RTE_RETA_GROUP_SIZE;
1860 shift = i % RTE_RETA_GROUP_SIZE;
1861 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1865 if (mask == I40E_4_BIT_MASK)
1868 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1869 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1870 if (mask & (0x1 << j))
1871 lut |= reta_conf[idx].reta[shift + j] <<
1874 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1876 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1883 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1884 struct rte_eth_rss_reta_entry64 *reta_conf,
1887 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890 uint16_t i, j, lut_size = pf->hash_lut_size;
1891 uint16_t idx, shift;
1894 if (reta_size != lut_size ||
1895 reta_size > ETH_RSS_RETA_SIZE_512) {
1896 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1897 "(%d) doesn't match the number hardware can supported "
1898 "(%d)\n", reta_size, lut_size);
1902 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1903 idx = i / RTE_RETA_GROUP_SIZE;
1904 shift = i % RTE_RETA_GROUP_SIZE;
1905 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1910 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1911 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1912 if (mask & (0x1 << j))
1913 reta_conf[idx].reta[shift] = ((lut >>
1914 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1922 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1923 * @hw: pointer to the HW structure
1924 * @mem: pointer to mem struct to fill out
1925 * @size: size of memory requested
1926 * @alignment: what to align the allocation to
1928 enum i40e_status_code
1929 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1930 struct i40e_dma_mem *mem,
1934 static uint64_t id = 0;
1935 const struct rte_memzone *mz = NULL;
1936 char z_name[RTE_MEMZONE_NAMESIZE];
1939 return I40E_ERR_PARAM;
1942 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1943 #ifdef RTE_LIBRTE_XEN_DOM0
1944 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1947 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1950 return I40E_ERR_NO_MEMORY;
1955 #ifdef RTE_LIBRTE_XEN_DOM0
1956 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1958 mem->pa = mz->phys_addr;
1961 return I40E_SUCCESS;
1965 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1966 * @hw: pointer to the HW structure
1967 * @mem: ptr to mem struct to free
1969 enum i40e_status_code
1970 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1971 struct i40e_dma_mem *mem)
1973 if (!mem || !mem->va)
1974 return I40E_ERR_PARAM;
1979 return I40E_SUCCESS;
1983 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1984 * @hw: pointer to the HW structure
1985 * @mem: pointer to mem struct to fill out
1986 * @size: size of memory requested
1988 enum i40e_status_code
1989 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1990 struct i40e_virt_mem *mem,
1994 return I40E_ERR_PARAM;
1997 mem->va = rte_zmalloc("i40e", size, 0);
2000 return I40E_SUCCESS;
2002 return I40E_ERR_NO_MEMORY;
2006 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2007 * @hw: pointer to the HW structure
2008 * @mem: pointer to mem struct to free
2010 enum i40e_status_code
2011 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2012 struct i40e_virt_mem *mem)
2015 return I40E_ERR_PARAM;
2020 return I40E_SUCCESS;
2024 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2026 rte_spinlock_init(&sp->spinlock);
2030 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2032 rte_spinlock_lock(&sp->spinlock);
2036 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2038 rte_spinlock_unlock(&sp->spinlock);
2042 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2048 * Get the hardware capabilities, which will be parsed
2049 * and saved into struct i40e_hw.
2052 i40e_get_cap(struct i40e_hw *hw)
2054 struct i40e_aqc_list_capabilities_element_resp *buf;
2055 uint16_t len, size = 0;
2058 /* Calculate a huge enough buff for saving response data temporarily */
2059 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2060 I40E_MAX_CAP_ELE_NUM;
2061 buf = rte_zmalloc("i40e", len, 0);
2063 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2064 return I40E_ERR_NO_MEMORY;
2067 /* Get, parse the capabilities and save it to hw */
2068 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2069 i40e_aqc_opc_list_func_capabilities, NULL);
2070 if (ret != I40E_SUCCESS)
2071 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2073 /* Free the temporary buffer after being used */
2080 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2082 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2083 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2084 uint16_t sum_queues = 0, sum_vsis, left_queues;
2086 /* First check if FW support SRIOV */
2087 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2088 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2092 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2093 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2094 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2095 /* Allocate queues for pf */
2096 if (hw->func_caps.rss) {
2097 pf->flags |= I40E_FLAG_RSS;
2098 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2099 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2100 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2103 sum_queues = pf->lan_nb_qps;
2104 /* Default VSI is not counted in */
2106 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2108 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2109 pf->flags |= I40E_FLAG_SRIOV;
2110 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2111 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2112 PMD_INIT_LOG(ERR, "Config VF number %u, "
2113 "max supported %u.",
2114 dev->pci_dev->max_vfs,
2115 hw->func_caps.num_vfs);
2118 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2119 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2120 "max support %u queues.",
2121 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2124 pf->vf_num = dev->pci_dev->max_vfs;
2125 sum_queues += pf->vf_nb_qps * pf->vf_num;
2126 sum_vsis += pf->vf_num;
2127 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2128 pf->vf_num, pf->vf_nb_qps);
2132 if (hw->func_caps.vmdq) {
2133 pf->flags |= I40E_FLAG_VMDQ;
2134 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2135 pf->max_nb_vmdq_vsi = 1;
2137 * If VMDQ available, assume a single VSI can be created. Will adjust
2140 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2141 sum_vsis += pf->max_nb_vmdq_vsi;
2143 pf->vmdq_nb_qps = 0;
2144 pf->max_nb_vmdq_vsi = 0;
2146 pf->nb_cfg_vmdq_vsi = 0;
2148 if (hw->func_caps.fd) {
2149 pf->flags |= I40E_FLAG_FDIR;
2150 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2152 * Each flow director consumes one VSI and one queue,
2153 * but can't calculate out predictably here.
2157 if (sum_vsis > pf->max_num_vsi ||
2158 sum_queues > hw->func_caps.num_rx_qp) {
2159 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2160 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2161 pf->max_num_vsi, sum_vsis);
2162 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2163 hw->func_caps.num_rx_qp, sum_queues);
2167 /* Adjust VMDQ setting to support as many VMs as possible */
2168 if (pf->flags & I40E_FLAG_VMDQ) {
2169 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2171 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2172 pf->max_num_vsi - sum_vsis);
2174 /* Limit the max VMDQ number that rte_ether that can support */
2175 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2178 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2179 pf->max_nb_vmdq_vsi);
2180 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2183 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2185 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2186 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2187 sum_vsis, hw->func_caps.num_msix_vectors);
2190 return I40E_SUCCESS;
2194 i40e_pf_get_switch_config(struct i40e_pf *pf)
2196 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2197 struct i40e_aqc_get_switch_config_resp *switch_config;
2198 struct i40e_aqc_switch_config_element_resp *element;
2199 uint16_t start_seid = 0, num_reported;
2202 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2203 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2204 if (!switch_config) {
2205 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2209 /* Get the switch configurations */
2210 ret = i40e_aq_get_switch_config(hw, switch_config,
2211 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2212 if (ret != I40E_SUCCESS) {
2213 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2216 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2217 if (num_reported != 1) { /* The number should be 1 */
2218 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2222 /* Parse the switch configuration elements */
2223 element = &(switch_config->element[0]);
2224 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2225 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2226 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2228 PMD_DRV_LOG(INFO, "Unknown element type");
2231 rte_free(switch_config);
2237 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2240 struct pool_entry *entry;
2242 if (pool == NULL || num == 0)
2245 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2246 if (entry == NULL) {
2247 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2251 /* queue heap initialize */
2252 pool->num_free = num;
2253 pool->num_alloc = 0;
2255 LIST_INIT(&pool->alloc_list);
2256 LIST_INIT(&pool->free_list);
2258 /* Initialize element */
2262 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2267 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2269 struct pool_entry *entry;
2274 LIST_FOREACH(entry, &pool->alloc_list, next) {
2275 LIST_REMOVE(entry, next);
2279 LIST_FOREACH(entry, &pool->free_list, next) {
2280 LIST_REMOVE(entry, next);
2285 pool->num_alloc = 0;
2287 LIST_INIT(&pool->alloc_list);
2288 LIST_INIT(&pool->free_list);
2292 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2295 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2296 uint32_t pool_offset;
2300 PMD_DRV_LOG(ERR, "Invalid parameter");
2304 pool_offset = base - pool->base;
2305 /* Lookup in alloc list */
2306 LIST_FOREACH(entry, &pool->alloc_list, next) {
2307 if (entry->base == pool_offset) {
2308 valid_entry = entry;
2309 LIST_REMOVE(entry, next);
2314 /* Not find, return */
2315 if (valid_entry == NULL) {
2316 PMD_DRV_LOG(ERR, "Failed to find entry");
2321 * Found it, move it to free list and try to merge.
2322 * In order to make merge easier, always sort it by qbase.
2323 * Find adjacent prev and last entries.
2326 LIST_FOREACH(entry, &pool->free_list, next) {
2327 if (entry->base > valid_entry->base) {
2335 /* Try to merge with next one*/
2337 /* Merge with next one */
2338 if (valid_entry->base + valid_entry->len == next->base) {
2339 next->base = valid_entry->base;
2340 next->len += valid_entry->len;
2341 rte_free(valid_entry);
2348 /* Merge with previous one */
2349 if (prev->base + prev->len == valid_entry->base) {
2350 prev->len += valid_entry->len;
2351 /* If it merge with next one, remove next node */
2353 LIST_REMOVE(valid_entry, next);
2354 rte_free(valid_entry);
2356 rte_free(valid_entry);
2362 /* Not find any entry to merge, insert */
2365 LIST_INSERT_AFTER(prev, valid_entry, next);
2366 else if (next != NULL)
2367 LIST_INSERT_BEFORE(next, valid_entry, next);
2368 else /* It's empty list, insert to head */
2369 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2372 pool->num_free += valid_entry->len;
2373 pool->num_alloc -= valid_entry->len;
2379 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2382 struct pool_entry *entry, *valid_entry;
2384 if (pool == NULL || num == 0) {
2385 PMD_DRV_LOG(ERR, "Invalid parameter");
2389 if (pool->num_free < num) {
2390 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2391 num, pool->num_free);
2396 /* Lookup in free list and find most fit one */
2397 LIST_FOREACH(entry, &pool->free_list, next) {
2398 if (entry->len >= num) {
2400 if (entry->len == num) {
2401 valid_entry = entry;
2404 if (valid_entry == NULL || valid_entry->len > entry->len)
2405 valid_entry = entry;
2409 /* Not find one to satisfy the request, return */
2410 if (valid_entry == NULL) {
2411 PMD_DRV_LOG(ERR, "No valid entry found");
2415 * The entry have equal queue number as requested,
2416 * remove it from alloc_list.
2418 if (valid_entry->len == num) {
2419 LIST_REMOVE(valid_entry, next);
2422 * The entry have more numbers than requested,
2423 * create a new entry for alloc_list and minus its
2424 * queue base and number in free_list.
2426 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2427 if (entry == NULL) {
2428 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2432 entry->base = valid_entry->base;
2434 valid_entry->base += num;
2435 valid_entry->len -= num;
2436 valid_entry = entry;
2439 /* Insert it into alloc list, not sorted */
2440 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2442 pool->num_free -= valid_entry->len;
2443 pool->num_alloc += valid_entry->len;
2445 return (valid_entry->base + pool->base);
2449 * bitmap_is_subset - Check whether src2 is subset of src1
2452 bitmap_is_subset(uint8_t src1, uint8_t src2)
2454 return !((src1 ^ src2) & src2);
2458 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2460 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2462 /* If DCB is not supported, only default TC is supported */
2463 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2464 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2468 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2469 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2470 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2474 return I40E_SUCCESS;
2478 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2479 struct i40e_vsi_vlan_pvid_info *info)
2482 struct i40e_vsi_context ctxt;
2483 uint8_t vlan_flags = 0;
2486 if (vsi == NULL || info == NULL) {
2487 PMD_DRV_LOG(ERR, "invalid parameters");
2488 return I40E_ERR_PARAM;
2492 vsi->info.pvid = info->config.pvid;
2494 * If insert pvid is enabled, only tagged pkts are
2495 * allowed to be sent out.
2497 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2498 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2501 if (info->config.reject.tagged == 0)
2502 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2504 if (info->config.reject.untagged == 0)
2505 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2507 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2508 I40E_AQ_VSI_PVLAN_MODE_MASK);
2509 vsi->info.port_vlan_flags |= vlan_flags;
2510 vsi->info.valid_sections =
2511 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2512 memset(&ctxt, 0, sizeof(ctxt));
2513 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2514 ctxt.seid = vsi->seid;
2516 hw = I40E_VSI_TO_HW(vsi);
2517 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2518 if (ret != I40E_SUCCESS)
2519 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2525 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2527 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2529 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2531 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2532 if (ret != I40E_SUCCESS)
2536 PMD_DRV_LOG(ERR, "seid not valid");
2540 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2541 tc_bw_data.tc_valid_bits = enabled_tcmap;
2542 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2543 tc_bw_data.tc_bw_credits[i] =
2544 (enabled_tcmap & (1 << i)) ? 1 : 0;
2546 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2547 if (ret != I40E_SUCCESS) {
2548 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2552 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2553 sizeof(vsi->info.qs_handle));
2554 return I40E_SUCCESS;
2558 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2559 struct i40e_aqc_vsi_properties_data *info,
2560 uint8_t enabled_tcmap)
2562 int ret, total_tc = 0, i;
2563 uint16_t qpnum_per_tc, bsf, qp_idx;
2565 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2566 if (ret != I40E_SUCCESS)
2569 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2570 if (enabled_tcmap & (1 << i))
2572 vsi->enabled_tc = enabled_tcmap;
2574 /* Number of queues per enabled TC */
2575 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2576 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2577 bsf = rte_bsf32(qpnum_per_tc);
2579 /* Adjust the queue number to actual queues that can be applied */
2580 vsi->nb_qps = qpnum_per_tc * total_tc;
2583 * Configure TC and queue mapping parameters, for enabled TC,
2584 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2585 * default queue will serve it.
2588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2589 if (vsi->enabled_tc & (1 << i)) {
2590 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2591 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2592 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2593 qp_idx += qpnum_per_tc;
2595 info->tc_mapping[i] = 0;
2598 /* Associate queue number with VSI */
2599 if (vsi->type == I40E_VSI_SRIOV) {
2600 info->mapping_flags |=
2601 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2602 for (i = 0; i < vsi->nb_qps; i++)
2603 info->queue_mapping[i] =
2604 rte_cpu_to_le_16(vsi->base_queue + i);
2606 info->mapping_flags |=
2607 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2608 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2610 info->valid_sections =
2611 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2613 return I40E_SUCCESS;
2617 i40e_veb_release(struct i40e_veb *veb)
2619 struct i40e_vsi *vsi;
2622 if (veb == NULL || veb->associate_vsi == NULL)
2625 if (!TAILQ_EMPTY(&veb->head)) {
2626 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2630 vsi = veb->associate_vsi;
2631 hw = I40E_VSI_TO_HW(vsi);
2633 vsi->uplink_seid = veb->uplink_seid;
2634 i40e_aq_delete_element(hw, veb->seid, NULL);
2637 return I40E_SUCCESS;
2641 static struct i40e_veb *
2642 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2644 struct i40e_veb *veb;
2648 if (NULL == pf || vsi == NULL) {
2649 PMD_DRV_LOG(ERR, "veb setup failed, "
2650 "associated VSI shouldn't null");
2653 hw = I40E_PF_TO_HW(pf);
2655 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2657 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2661 veb->associate_vsi = vsi;
2662 TAILQ_INIT(&veb->head);
2663 veb->uplink_seid = vsi->uplink_seid;
2665 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2666 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2668 if (ret != I40E_SUCCESS) {
2669 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2670 hw->aq.asq_last_status);
2674 /* get statistics index */
2675 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2676 &veb->stats_idx, NULL, NULL, NULL);
2677 if (ret != I40E_SUCCESS) {
2678 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2679 hw->aq.asq_last_status);
2683 /* Get VEB bandwidth, to be implemented */
2684 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2685 vsi->uplink_seid = veb->seid;
2694 i40e_vsi_release(struct i40e_vsi *vsi)
2698 struct i40e_vsi_list *vsi_list;
2700 struct i40e_mac_filter *f;
2703 return I40E_SUCCESS;
2705 pf = I40E_VSI_TO_PF(vsi);
2706 hw = I40E_VSI_TO_HW(vsi);
2708 /* VSI has child to attach, release child first */
2710 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2711 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2713 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2715 i40e_veb_release(vsi->veb);
2718 /* Remove all macvlan filters of the VSI */
2719 i40e_vsi_remove_all_macvlan_filter(vsi);
2720 TAILQ_FOREACH(f, &vsi->mac_list, next)
2723 if (vsi->type != I40E_VSI_MAIN) {
2724 /* Remove vsi from parent's sibling list */
2725 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2726 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2727 return I40E_ERR_PARAM;
2729 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2730 &vsi->sib_vsi_list, list);
2732 /* Remove all switch element of the VSI */
2733 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2734 if (ret != I40E_SUCCESS)
2735 PMD_DRV_LOG(ERR, "Failed to delete element");
2737 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2739 if (vsi->type != I40E_VSI_SRIOV)
2740 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2743 return I40E_SUCCESS;
2747 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2749 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2750 struct i40e_aqc_remove_macvlan_element_data def_filter;
2751 struct i40e_mac_filter_info filter;
2754 if (vsi->type != I40E_VSI_MAIN)
2755 return I40E_ERR_CONFIG;
2756 memset(&def_filter, 0, sizeof(def_filter));
2757 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2759 def_filter.vlan_tag = 0;
2760 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2761 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2762 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2763 if (ret != I40E_SUCCESS) {
2764 struct i40e_mac_filter *f;
2765 struct ether_addr *mac;
2767 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2769 /* It needs to add the permanent mac into mac list */
2770 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2772 PMD_DRV_LOG(ERR, "failed to allocate memory");
2773 return I40E_ERR_NO_MEMORY;
2775 mac = &f->mac_info.mac_addr;
2776 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2778 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2779 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2784 (void)rte_memcpy(&filter.mac_addr,
2785 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2786 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2787 return i40e_vsi_add_mac(vsi, &filter);
2791 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2793 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2794 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2795 struct i40e_hw *hw = &vsi->adapter->hw;
2799 memset(&bw_config, 0, sizeof(bw_config));
2800 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2801 if (ret != I40E_SUCCESS) {
2802 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2803 hw->aq.asq_last_status);
2807 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2808 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2809 &ets_sla_config, NULL);
2810 if (ret != I40E_SUCCESS) {
2811 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2812 "configuration %u", hw->aq.asq_last_status);
2816 /* Not store the info yet, just print out */
2817 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2818 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2819 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2820 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2821 ets_sla_config.share_credits[i]);
2822 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2823 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2824 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2825 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2834 i40e_vsi_setup(struct i40e_pf *pf,
2835 enum i40e_vsi_type type,
2836 struct i40e_vsi *uplink_vsi,
2837 uint16_t user_param)
2839 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2840 struct i40e_vsi *vsi;
2841 struct i40e_mac_filter_info filter;
2843 struct i40e_vsi_context ctxt;
2844 struct ether_addr broadcast =
2845 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2847 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2848 PMD_DRV_LOG(ERR, "VSI setup failed, "
2849 "VSI link shouldn't be NULL");
2853 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2854 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2855 "uplink VSI should be NULL");
2859 /* If uplink vsi didn't setup VEB, create one first */
2860 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2861 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2863 if (NULL == uplink_vsi->veb) {
2864 PMD_DRV_LOG(ERR, "VEB setup failed");
2869 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2871 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2874 TAILQ_INIT(&vsi->mac_list);
2876 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2877 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2878 vsi->parent_vsi = uplink_vsi;
2879 vsi->user_param = user_param;
2880 /* Allocate queues */
2881 switch (vsi->type) {
2882 case I40E_VSI_MAIN :
2883 vsi->nb_qps = pf->lan_nb_qps;
2885 case I40E_VSI_SRIOV :
2886 vsi->nb_qps = pf->vf_nb_qps;
2888 case I40E_VSI_VMDQ2:
2889 vsi->nb_qps = pf->vmdq_nb_qps;
2892 vsi->nb_qps = pf->fdir_nb_qps;
2898 * The filter status descriptor is reported in rx queue 0,
2899 * while the tx queue for fdir filter programming has no
2900 * such constraints, can be non-zero queues.
2901 * To simplify it, choose FDIR vsi use queue 0 pair.
2902 * To make sure it will use queue 0 pair, queue allocation
2903 * need be done before this function is called
2905 if (type != I40E_VSI_FDIR) {
2906 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2908 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2912 vsi->base_queue = ret;
2914 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2916 /* VF has MSIX interrupt in VF range, don't allocate here */
2917 if (type != I40E_VSI_SRIOV) {
2918 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2920 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2921 goto fail_queue_alloc;
2923 vsi->msix_intr = ret;
2927 if (type == I40E_VSI_MAIN) {
2928 /* For main VSI, no need to add since it's default one */
2929 vsi->uplink_seid = pf->mac_seid;
2930 vsi->seid = pf->main_vsi_seid;
2931 /* Bind queues with specific MSIX interrupt */
2933 * Needs 2 interrupt at least, one for misc cause which will
2934 * enabled from OS side, Another for queues binding the
2935 * interrupt from device side only.
2938 /* Get default VSI parameters from hardware */
2939 memset(&ctxt, 0, sizeof(ctxt));
2940 ctxt.seid = vsi->seid;
2941 ctxt.pf_num = hw->pf_id;
2942 ctxt.uplink_seid = vsi->uplink_seid;
2944 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2945 if (ret != I40E_SUCCESS) {
2946 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2947 goto fail_msix_alloc;
2949 (void)rte_memcpy(&vsi->info, &ctxt.info,
2950 sizeof(struct i40e_aqc_vsi_properties_data));
2951 vsi->vsi_id = ctxt.vsi_number;
2952 vsi->info.valid_sections = 0;
2954 /* Configure tc, enabled TC0 only */
2955 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2957 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2958 goto fail_msix_alloc;
2961 /* TC, queue mapping */
2962 memset(&ctxt, 0, sizeof(ctxt));
2963 vsi->info.valid_sections |=
2964 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2965 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2966 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2967 (void)rte_memcpy(&ctxt.info, &vsi->info,
2968 sizeof(struct i40e_aqc_vsi_properties_data));
2969 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2970 I40E_DEFAULT_TCMAP);
2971 if (ret != I40E_SUCCESS) {
2972 PMD_DRV_LOG(ERR, "Failed to configure "
2973 "TC queue mapping");
2974 goto fail_msix_alloc;
2976 ctxt.seid = vsi->seid;
2977 ctxt.pf_num = hw->pf_id;
2978 ctxt.uplink_seid = vsi->uplink_seid;
2981 /* Update VSI parameters */
2982 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2983 if (ret != I40E_SUCCESS) {
2984 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2985 goto fail_msix_alloc;
2988 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2989 sizeof(vsi->info.tc_mapping));
2990 (void)rte_memcpy(&vsi->info.queue_mapping,
2991 &ctxt.info.queue_mapping,
2992 sizeof(vsi->info.queue_mapping));
2993 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2994 vsi->info.valid_sections = 0;
2996 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3000 * Updating default filter settings are necessary to prevent
3001 * reception of tagged packets.
3002 * Some old firmware configurations load a default macvlan
3003 * filter which accepts both tagged and untagged packets.
3004 * The updating is to use a normal filter instead if needed.
3005 * For NVM 4.2.2 or after, the updating is not needed anymore.
3006 * The firmware with correct configurations load the default
3007 * macvlan filter which is expected and cannot be removed.
3009 i40e_update_default_filter_setting(vsi);
3010 } else if (type == I40E_VSI_SRIOV) {
3011 memset(&ctxt, 0, sizeof(ctxt));
3013 * For other VSI, the uplink_seid equals to uplink VSI's
3014 * uplink_seid since they share same VEB
3016 vsi->uplink_seid = uplink_vsi->uplink_seid;
3017 ctxt.pf_num = hw->pf_id;
3018 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3019 ctxt.uplink_seid = vsi->uplink_seid;
3020 ctxt.connection_type = 0x1;
3021 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3023 /* Configure switch ID */
3024 ctxt.info.valid_sections |=
3025 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3026 ctxt.info.switch_id =
3027 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3028 /* Configure port/vlan */
3029 ctxt.info.valid_sections |=
3030 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3031 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3032 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3033 I40E_DEFAULT_TCMAP);
3034 if (ret != I40E_SUCCESS) {
3035 PMD_DRV_LOG(ERR, "Failed to configure "
3036 "TC queue mapping");
3037 goto fail_msix_alloc;
3039 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3040 ctxt.info.valid_sections |=
3041 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3043 * Since VSI is not created yet, only configure parameter,
3044 * will add vsi below.
3046 } else if (type == I40E_VSI_VMDQ2) {
3047 memset(&ctxt, 0, sizeof(ctxt));
3049 * For other VSI, the uplink_seid equals to uplink VSI's
3050 * uplink_seid since they share same VEB
3052 vsi->uplink_seid = uplink_vsi->uplink_seid;
3053 ctxt.pf_num = hw->pf_id;
3055 ctxt.uplink_seid = vsi->uplink_seid;
3056 ctxt.connection_type = 0x1;
3057 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3059 ctxt.info.valid_sections |=
3060 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3061 /* user_param carries flag to enable loop back */
3063 ctxt.info.switch_id =
3064 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3065 ctxt.info.switch_id |=
3066 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3069 /* Configure port/vlan */
3070 ctxt.info.valid_sections |=
3071 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3072 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3073 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3074 I40E_DEFAULT_TCMAP);
3075 if (ret != I40E_SUCCESS) {
3076 PMD_DRV_LOG(ERR, "Failed to configure "
3077 "TC queue mapping");
3078 goto fail_msix_alloc;
3080 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3081 ctxt.info.valid_sections |=
3082 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3083 } else if (type == I40E_VSI_FDIR) {
3084 vsi->uplink_seid = uplink_vsi->uplink_seid;
3085 ctxt.pf_num = hw->pf_id;
3087 ctxt.uplink_seid = vsi->uplink_seid;
3088 ctxt.connection_type = 0x1; /* regular data port */
3089 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3090 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3091 I40E_DEFAULT_TCMAP);
3092 if (ret != I40E_SUCCESS) {
3093 PMD_DRV_LOG(ERR, "Failed to configure "
3094 "TC queue mapping.");
3095 goto fail_msix_alloc;
3097 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3098 ctxt.info.valid_sections |=
3099 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3101 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3102 goto fail_msix_alloc;
3105 if (vsi->type != I40E_VSI_MAIN) {
3106 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3108 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3109 hw->aq.asq_last_status);
3110 goto fail_msix_alloc;
3112 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3113 vsi->info.valid_sections = 0;
3114 vsi->seid = ctxt.seid;
3115 vsi->vsi_id = ctxt.vsi_number;
3116 vsi->sib_vsi_list.vsi = vsi;
3117 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3118 &vsi->sib_vsi_list, list);
3121 /* MAC/VLAN configuration */
3122 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3123 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3125 ret = i40e_vsi_add_mac(vsi, &filter);
3126 if (ret != I40E_SUCCESS) {
3127 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3128 goto fail_msix_alloc;
3131 /* Get VSI BW information */
3132 i40e_vsi_dump_bw_config(vsi);
3135 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3137 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3143 /* Configure vlan stripping on or off */
3145 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3147 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3148 struct i40e_vsi_context ctxt;
3150 int ret = I40E_SUCCESS;
3152 /* Check if it has been already on or off */
3153 if (vsi->info.valid_sections &
3154 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3156 if ((vsi->info.port_vlan_flags &
3157 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3158 return 0; /* already on */
3160 if ((vsi->info.port_vlan_flags &
3161 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3162 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3163 return 0; /* already off */
3168 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3170 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3171 vsi->info.valid_sections =
3172 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3173 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3174 vsi->info.port_vlan_flags |= vlan_flags;
3175 ctxt.seid = vsi->seid;
3176 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3177 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3179 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3180 on ? "enable" : "disable");
3186 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3188 struct rte_eth_dev_data *data = dev->data;
3191 /* Apply vlan offload setting */
3192 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3194 /* Apply double-vlan setting, not implemented yet */
3196 /* Apply pvid setting */
3197 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3198 data->dev_conf.txmode.hw_vlan_insert_pvid);
3200 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3206 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3208 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3210 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3214 i40e_update_flow_control(struct i40e_hw *hw)
3216 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3217 struct i40e_link_status link_status;
3218 uint32_t rxfc = 0, txfc = 0, reg;
3222 memset(&link_status, 0, sizeof(link_status));
3223 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3224 if (ret != I40E_SUCCESS) {
3225 PMD_DRV_LOG(ERR, "Failed to get link status information");
3226 goto write_reg; /* Disable flow control */
3229 an_info = hw->phy.link_info.an_info;
3230 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3231 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3232 ret = I40E_ERR_NOT_READY;
3233 goto write_reg; /* Disable flow control */
3236 * If link auto negotiation is enabled, flow control needs to
3237 * be configured according to it
3239 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3240 case I40E_LINK_PAUSE_RXTX:
3243 hw->fc.current_mode = I40E_FC_FULL;
3245 case I40E_AQ_LINK_PAUSE_RX:
3247 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3249 case I40E_AQ_LINK_PAUSE_TX:
3251 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3254 hw->fc.current_mode = I40E_FC_NONE;
3259 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3260 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3261 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3262 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3263 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3264 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3271 i40e_pf_setup(struct i40e_pf *pf)
3273 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3274 struct i40e_filter_control_settings settings;
3275 struct i40e_vsi *vsi;
3278 /* Clear all stats counters */
3279 pf->offset_loaded = FALSE;
3280 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3281 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3283 ret = i40e_pf_get_switch_config(pf);
3284 if (ret != I40E_SUCCESS) {
3285 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3288 if (pf->flags & I40E_FLAG_FDIR) {
3289 /* make queue allocated first, let FDIR use queue pair 0*/
3290 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3291 if (ret != I40E_FDIR_QUEUE_ID) {
3292 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3294 pf->flags &= ~I40E_FLAG_FDIR;
3297 /* main VSI setup */
3298 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3300 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3301 return I40E_ERR_NOT_READY;
3305 /* setup FDIR after main vsi created.*/
3306 if (pf->flags & I40E_FLAG_FDIR) {
3307 ret = i40e_fdir_setup(pf);
3308 if (ret != I40E_SUCCESS) {
3309 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
3310 pf->flags &= ~I40E_FLAG_FDIR;
3314 /* Configure filter control */
3315 memset(&settings, 0, sizeof(settings));
3316 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3317 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3318 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3319 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3321 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3322 hw->func_caps.rss_table_size);
3323 return I40E_ERR_PARAM;
3325 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3326 "size: %u\n", hw->func_caps.rss_table_size);
3327 pf->hash_lut_size = hw->func_caps.rss_table_size;
3329 /* Enable ethtype and macvlan filters */
3330 settings.enable_ethtype = TRUE;
3331 settings.enable_macvlan = TRUE;
3332 ret = i40e_set_filter_control(hw, &settings);
3334 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3337 /* Update flow control according to the auto negotiation */
3338 i40e_update_flow_control(hw);
3340 return I40E_SUCCESS;
3344 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3350 * Set or clear TX Queue Disable flags,
3351 * which is required by hardware.
3353 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3354 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3356 /* Wait until the request is finished */
3357 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3358 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3359 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3360 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3361 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3367 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3368 return I40E_SUCCESS; /* already on, skip next steps */
3370 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3371 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3373 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3374 return I40E_SUCCESS; /* already off, skip next steps */
3375 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3377 /* Write the register */
3378 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3379 /* Check the result */
3380 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3381 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3382 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3384 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3385 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3388 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3389 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3393 /* Check if it is timeout */
3394 if (j >= I40E_CHK_Q_ENA_COUNT) {
3395 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3396 (on ? "enable" : "disable"), q_idx);
3397 return I40E_ERR_TIMEOUT;
3400 return I40E_SUCCESS;
3403 /* Swith on or off the tx queues */
3405 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3407 struct rte_eth_dev_data *dev_data = pf->dev_data;
3408 struct i40e_tx_queue *txq;
3409 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3413 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3414 txq = dev_data->tx_queues[i];
3415 /* Don't operate the queue if not configured or
3416 * if starting only per queue */
3417 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3420 ret = i40e_dev_tx_queue_start(dev, i);
3422 ret = i40e_dev_tx_queue_stop(dev, i);
3423 if ( ret != I40E_SUCCESS)
3427 return I40E_SUCCESS;
3431 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3436 /* Wait until the request is finished */
3437 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3438 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3439 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3440 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3441 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3446 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3447 return I40E_SUCCESS; /* Already on, skip next steps */
3448 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3450 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3451 return I40E_SUCCESS; /* Already off, skip next steps */
3452 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3455 /* Write the register */
3456 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3457 /* Check the result */
3458 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3459 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3460 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3462 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3463 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3466 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3467 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3472 /* Check if it is timeout */
3473 if (j >= I40E_CHK_Q_ENA_COUNT) {
3474 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3475 (on ? "enable" : "disable"), q_idx);
3476 return I40E_ERR_TIMEOUT;
3479 return I40E_SUCCESS;
3481 /* Switch on or off the rx queues */
3483 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3485 struct rte_eth_dev_data *dev_data = pf->dev_data;
3486 struct i40e_rx_queue *rxq;
3487 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3491 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3492 rxq = dev_data->rx_queues[i];
3493 /* Don't operate the queue if not configured or
3494 * if starting only per queue */
3495 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3498 ret = i40e_dev_rx_queue_start(dev, i);
3500 ret = i40e_dev_rx_queue_stop(dev, i);
3501 if (ret != I40E_SUCCESS)
3505 return I40E_SUCCESS;
3508 /* Switch on or off all the rx/tx queues */
3510 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3515 /* enable rx queues before enabling tx queues */
3516 ret = i40e_dev_switch_rx_queues(pf, on);
3518 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3521 ret = i40e_dev_switch_tx_queues(pf, on);
3523 /* Stop tx queues before stopping rx queues */
3524 ret = i40e_dev_switch_tx_queues(pf, on);
3526 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3529 ret = i40e_dev_switch_rx_queues(pf, on);
3535 /* Initialize VSI for TX */
3537 i40e_dev_tx_init(struct i40e_pf *pf)
3539 struct rte_eth_dev_data *data = pf->dev_data;
3541 uint32_t ret = I40E_SUCCESS;
3542 struct i40e_tx_queue *txq;
3544 for (i = 0; i < data->nb_tx_queues; i++) {
3545 txq = data->tx_queues[i];
3546 if (!txq || !txq->q_set)
3548 ret = i40e_tx_queue_init(txq);
3549 if (ret != I40E_SUCCESS)
3556 /* Initialize VSI for RX */
3558 i40e_dev_rx_init(struct i40e_pf *pf)
3560 struct rte_eth_dev_data *data = pf->dev_data;
3561 int ret = I40E_SUCCESS;
3563 struct i40e_rx_queue *rxq;
3565 i40e_pf_config_mq_rx(pf);
3566 for (i = 0; i < data->nb_rx_queues; i++) {
3567 rxq = data->rx_queues[i];
3568 if (!rxq || !rxq->q_set)
3571 ret = i40e_rx_queue_init(rxq);
3572 if (ret != I40E_SUCCESS) {
3573 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3583 i40e_dev_rxtx_init(struct i40e_pf *pf)
3587 err = i40e_dev_tx_init(pf);
3589 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3592 err = i40e_dev_rx_init(pf);
3594 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3602 i40e_vmdq_setup(struct rte_eth_dev *dev)
3604 struct rte_eth_conf *conf = &dev->data->dev_conf;
3605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3606 int i, err, conf_vsis, j, loop;
3607 struct i40e_vsi *vsi;
3608 struct i40e_vmdq_info *vmdq_info;
3609 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3610 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3613 * Disable interrupt to avoid message from VF. Furthermore, it will
3614 * avoid race condition in VSI creation/destroy.
3616 i40e_pf_disable_irq0(hw);
3618 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3619 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3623 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3624 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3625 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3626 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3627 pf->max_nb_vmdq_vsi);
3631 if (pf->vmdq != NULL) {
3632 PMD_INIT_LOG(INFO, "VMDQ already configured");
3636 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3637 sizeof(*vmdq_info) * conf_vsis, 0);
3639 if (pf->vmdq == NULL) {
3640 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3644 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3646 /* Create VMDQ VSI */
3647 for (i = 0; i < conf_vsis; i++) {
3648 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3649 vmdq_conf->enable_loop_back);
3651 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3655 vmdq_info = &pf->vmdq[i];
3657 vmdq_info->vsi = vsi;
3659 pf->nb_cfg_vmdq_vsi = conf_vsis;
3661 /* Configure Vlan */
3662 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3663 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3664 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3665 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3666 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3667 vmdq_conf->pool_map[i].vlan_id, j);
3669 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3670 vmdq_conf->pool_map[i].vlan_id);
3672 PMD_INIT_LOG(ERR, "Failed to add vlan");
3680 i40e_pf_enable_irq0(hw);
3685 for (i = 0; i < conf_vsis; i++)
3686 if (pf->vmdq[i].vsi == NULL)
3689 i40e_vsi_release(pf->vmdq[i].vsi);
3693 i40e_pf_enable_irq0(hw);
3698 i40e_stat_update_32(struct i40e_hw *hw,
3706 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3710 if (new_data >= *offset)
3711 *stat = (uint64_t)(new_data - *offset);
3713 *stat = (uint64_t)((new_data +
3714 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3718 i40e_stat_update_48(struct i40e_hw *hw,
3727 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3728 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3729 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3734 if (new_data >= *offset)
3735 *stat = new_data - *offset;
3737 *stat = (uint64_t)((new_data +
3738 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3740 *stat &= I40E_48_BIT_MASK;
3745 i40e_pf_disable_irq0(struct i40e_hw *hw)
3747 /* Disable all interrupt types */
3748 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3749 I40E_WRITE_FLUSH(hw);
3754 i40e_pf_enable_irq0(struct i40e_hw *hw)
3756 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3757 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3758 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3759 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3760 I40E_WRITE_FLUSH(hw);
3764 i40e_pf_config_irq0(struct i40e_hw *hw)
3766 /* read pending request and disable first */
3767 i40e_pf_disable_irq0(hw);
3768 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3769 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3770 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3772 /* Link no queues with irq0 */
3773 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3774 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3778 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3784 uint32_t index, offset, val;
3789 * Try to find which VF trigger a reset, use absolute VF id to access
3790 * since the reg is global register.
3792 for (i = 0; i < pf->vf_num; i++) {
3793 abs_vf_id = hw->func_caps.vf_base_id + i;
3794 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3795 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3796 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3797 /* VFR event occured */
3798 if (val & (0x1 << offset)) {
3801 /* Clear the event first */
3802 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3804 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3806 * Only notify a VF reset event occured,
3807 * don't trigger another SW reset
3809 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3810 if (ret != I40E_SUCCESS)
3811 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3817 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3820 struct i40e_arq_event_info info;
3821 uint16_t pending, opcode;
3824 info.buf_len = I40E_AQ_BUF_SZ;
3825 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3826 if (!info.msg_buf) {
3827 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3833 ret = i40e_clean_arq_element(hw, &info, &pending);
3835 if (ret != I40E_SUCCESS) {
3836 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3837 "aq_err: %u", hw->aq.asq_last_status);
3840 opcode = rte_le_to_cpu_16(info.desc.opcode);
3843 case i40e_aqc_opc_send_msg_to_pf:
3844 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3845 i40e_pf_host_handle_vf_msg(dev,
3846 rte_le_to_cpu_16(info.desc.retval),
3847 rte_le_to_cpu_32(info.desc.cookie_high),
3848 rte_le_to_cpu_32(info.desc.cookie_low),
3853 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3858 rte_free(info.msg_buf);
3862 * Interrupt handler is registered as the alarm callback for handling LSC
3863 * interrupt in a definite of time, in order to wait the NIC into a stable
3864 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3865 * no need for link down interrupt.
3868 i40e_dev_interrupt_delayed_handler(void *param)
3870 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874 /* read interrupt causes again */
3875 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3877 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3878 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3879 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3880 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3881 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3882 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3883 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3884 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3885 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3886 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3887 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3889 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3890 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3891 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3892 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3893 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3895 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3896 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3897 i40e_dev_handle_vfr_event(dev);
3899 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3900 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3901 i40e_dev_handle_aq_msg(dev);
3904 /* handle the link up interrupt in an alarm callback */
3905 i40e_dev_link_update(dev, 0);
3906 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3908 i40e_pf_enable_irq0(hw);
3909 rte_intr_enable(&(dev->pci_dev->intr_handle));
3913 * Interrupt handler triggered by NIC for handling
3914 * specific interrupt.
3917 * Pointer to interrupt handle.
3919 * The address of parameter (struct rte_eth_dev *) regsitered before.
3925 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3928 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3929 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932 /* Disable interrupt */
3933 i40e_pf_disable_irq0(hw);
3935 /* read out interrupt causes */
3936 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3938 /* No interrupt event indicated */
3939 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3940 PMD_DRV_LOG(INFO, "No interrupt event");
3943 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3944 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3945 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3946 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3947 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3948 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3949 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3950 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3951 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3952 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3953 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3954 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3955 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3956 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3957 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3958 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3960 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3961 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3962 i40e_dev_handle_vfr_event(dev);
3964 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3965 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3966 i40e_dev_handle_aq_msg(dev);
3969 /* Link Status Change interrupt */
3970 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3971 #define I40E_US_PER_SECOND 1000000
3972 struct rte_eth_link link;
3974 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3975 memset(&link, 0, sizeof(link));
3976 rte_i40e_dev_atomic_read_link_status(dev, &link);
3977 i40e_dev_link_update(dev, 0);
3980 * For link up interrupt, it needs to wait 1 second to let the
3981 * hardware be a stable state. Otherwise several consecutive
3982 * interrupts can be observed.
3983 * For link down interrupt, no need to wait.
3985 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3986 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3989 _rte_eth_dev_callback_process(dev,
3990 RTE_ETH_EVENT_INTR_LSC);
3994 /* Enable interrupt */
3995 i40e_pf_enable_irq0(hw);
3996 rte_intr_enable(&(dev->pci_dev->intr_handle));
4000 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4001 struct i40e_macvlan_filter *filter,
4004 int ele_num, ele_buff_size;
4005 int num, actual_num, i;
4007 int ret = I40E_SUCCESS;
4008 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4009 struct i40e_aqc_add_macvlan_element_data *req_list;
4011 if (filter == NULL || total == 0)
4012 return I40E_ERR_PARAM;
4013 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4014 ele_buff_size = hw->aq.asq_buf_size;
4016 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4017 if (req_list == NULL) {
4018 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4019 return I40E_ERR_NO_MEMORY;
4024 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4025 memset(req_list, 0, ele_buff_size);
4027 for (i = 0; i < actual_num; i++) {
4028 (void)rte_memcpy(req_list[i].mac_addr,
4029 &filter[num + i].macaddr, ETH_ADDR_LEN);
4030 req_list[i].vlan_tag =
4031 rte_cpu_to_le_16(filter[num + i].vlan_id);
4033 switch (filter[num + i].filter_type) {
4034 case RTE_MAC_PERFECT_MATCH:
4035 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4036 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4038 case RTE_MACVLAN_PERFECT_MATCH:
4039 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4041 case RTE_MAC_HASH_MATCH:
4042 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4043 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4045 case RTE_MACVLAN_HASH_MATCH:
4046 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4049 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4050 ret = I40E_ERR_PARAM;
4054 req_list[i].queue_number = 0;
4056 req_list[i].flags = rte_cpu_to_le_16(flags);
4059 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4061 if (ret != I40E_SUCCESS) {
4062 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4066 } while (num < total);
4074 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4075 struct i40e_macvlan_filter *filter,
4078 int ele_num, ele_buff_size;
4079 int num, actual_num, i;
4081 int ret = I40E_SUCCESS;
4082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4083 struct i40e_aqc_remove_macvlan_element_data *req_list;
4085 if (filter == NULL || total == 0)
4086 return I40E_ERR_PARAM;
4088 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4089 ele_buff_size = hw->aq.asq_buf_size;
4091 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4092 if (req_list == NULL) {
4093 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4094 return I40E_ERR_NO_MEMORY;
4099 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4100 memset(req_list, 0, ele_buff_size);
4102 for (i = 0; i < actual_num; i++) {
4103 (void)rte_memcpy(req_list[i].mac_addr,
4104 &filter[num + i].macaddr, ETH_ADDR_LEN);
4105 req_list[i].vlan_tag =
4106 rte_cpu_to_le_16(filter[num + i].vlan_id);
4108 switch (filter[num + i].filter_type) {
4109 case RTE_MAC_PERFECT_MATCH:
4110 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4111 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4113 case RTE_MACVLAN_PERFECT_MATCH:
4114 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4116 case RTE_MAC_HASH_MATCH:
4117 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4118 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4120 case RTE_MACVLAN_HASH_MATCH:
4121 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4124 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4125 ret = I40E_ERR_PARAM;
4128 req_list[i].flags = rte_cpu_to_le_16(flags);
4131 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4133 if (ret != I40E_SUCCESS) {
4134 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4138 } while (num < total);
4145 /* Find out specific MAC filter */
4146 static struct i40e_mac_filter *
4147 i40e_find_mac_filter(struct i40e_vsi *vsi,
4148 struct ether_addr *macaddr)
4150 struct i40e_mac_filter *f;
4152 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4153 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4161 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4164 uint32_t vid_idx, vid_bit;
4166 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4167 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4169 if (vsi->vfta[vid_idx] & vid_bit)
4176 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4177 uint16_t vlan_id, bool on)
4179 uint32_t vid_idx, vid_bit;
4181 #define UINT32_BIT_MASK 0x1F
4182 #define VALID_VLAN_BIT_MASK 0xFFF
4183 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4184 * element first, then find the bits it belongs to
4186 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4188 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4191 vsi->vfta[vid_idx] |= vid_bit;
4193 vsi->vfta[vid_idx] &= ~vid_bit;
4197 * Find all vlan options for specific mac addr,
4198 * return with actual vlan found.
4201 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4202 struct i40e_macvlan_filter *mv_f,
4203 int num, struct ether_addr *addr)
4209 * Not to use i40e_find_vlan_filter to decrease the loop time,
4210 * although the code looks complex.
4212 if (num < vsi->vlan_num)
4213 return I40E_ERR_PARAM;
4216 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4218 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4219 if (vsi->vfta[j] & (1 << k)) {
4221 PMD_DRV_LOG(ERR, "vlan number "
4223 return I40E_ERR_PARAM;
4225 (void)rte_memcpy(&mv_f[i].macaddr,
4226 addr, ETH_ADDR_LEN);
4228 j * I40E_UINT32_BIT_SIZE + k;
4234 return I40E_SUCCESS;
4238 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4239 struct i40e_macvlan_filter *mv_f,
4244 struct i40e_mac_filter *f;
4246 if (num < vsi->mac_num)
4247 return I40E_ERR_PARAM;
4249 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4251 PMD_DRV_LOG(ERR, "buffer number not match");
4252 return I40E_ERR_PARAM;
4254 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4256 mv_f[i].vlan_id = vlan;
4257 mv_f[i].filter_type = f->mac_info.filter_type;
4261 return I40E_SUCCESS;
4265 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4268 struct i40e_mac_filter *f;
4269 struct i40e_macvlan_filter *mv_f;
4270 int ret = I40E_SUCCESS;
4272 if (vsi == NULL || vsi->mac_num == 0)
4273 return I40E_ERR_PARAM;
4275 /* Case that no vlan is set */
4276 if (vsi->vlan_num == 0)
4279 num = vsi->mac_num * vsi->vlan_num;
4281 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4283 PMD_DRV_LOG(ERR, "failed to allocate memory");
4284 return I40E_ERR_NO_MEMORY;
4288 if (vsi->vlan_num == 0) {
4289 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4290 (void)rte_memcpy(&mv_f[i].macaddr,
4291 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4292 mv_f[i].vlan_id = 0;
4296 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4297 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4298 vsi->vlan_num, &f->mac_info.mac_addr);
4299 if (ret != I40E_SUCCESS)
4305 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4313 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4315 struct i40e_macvlan_filter *mv_f;
4317 int ret = I40E_SUCCESS;
4319 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4320 return I40E_ERR_PARAM;
4322 /* If it's already set, just return */
4323 if (i40e_find_vlan_filter(vsi,vlan))
4324 return I40E_SUCCESS;
4326 mac_num = vsi->mac_num;
4329 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4330 return I40E_ERR_PARAM;
4333 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4336 PMD_DRV_LOG(ERR, "failed to allocate memory");
4337 return I40E_ERR_NO_MEMORY;
4340 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4342 if (ret != I40E_SUCCESS)
4345 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4347 if (ret != I40E_SUCCESS)
4350 i40e_set_vlan_filter(vsi, vlan, 1);
4360 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4362 struct i40e_macvlan_filter *mv_f;
4364 int ret = I40E_SUCCESS;
4367 * Vlan 0 is the generic filter for untagged packets
4368 * and can't be removed.
4370 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4371 return I40E_ERR_PARAM;
4373 /* If can't find it, just return */
4374 if (!i40e_find_vlan_filter(vsi, vlan))
4375 return I40E_ERR_PARAM;
4377 mac_num = vsi->mac_num;
4380 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4381 return I40E_ERR_PARAM;
4384 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4387 PMD_DRV_LOG(ERR, "failed to allocate memory");
4388 return I40E_ERR_NO_MEMORY;
4391 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4393 if (ret != I40E_SUCCESS)
4396 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4398 if (ret != I40E_SUCCESS)
4401 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4402 if (vsi->vlan_num == 1) {
4403 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4404 if (ret != I40E_SUCCESS)
4407 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4408 if (ret != I40E_SUCCESS)
4412 i40e_set_vlan_filter(vsi, vlan, 0);
4422 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4424 struct i40e_mac_filter *f;
4425 struct i40e_macvlan_filter *mv_f;
4426 int i, vlan_num = 0;
4427 int ret = I40E_SUCCESS;
4429 /* If it's add and we've config it, return */
4430 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4432 return I40E_SUCCESS;
4433 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4434 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4437 * If vlan_num is 0, that's the first time to add mac,
4438 * set mask for vlan_id 0.
4440 if (vsi->vlan_num == 0) {
4441 i40e_set_vlan_filter(vsi, 0, 1);
4444 vlan_num = vsi->vlan_num;
4445 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4446 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4449 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4451 PMD_DRV_LOG(ERR, "failed to allocate memory");
4452 return I40E_ERR_NO_MEMORY;
4455 for (i = 0; i < vlan_num; i++) {
4456 mv_f[i].filter_type = mac_filter->filter_type;
4457 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4461 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4462 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4463 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4464 &mac_filter->mac_addr);
4465 if (ret != I40E_SUCCESS)
4469 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4470 if (ret != I40E_SUCCESS)
4473 /* Add the mac addr into mac list */
4474 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4476 PMD_DRV_LOG(ERR, "failed to allocate memory");
4477 ret = I40E_ERR_NO_MEMORY;
4480 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4482 f->mac_info.filter_type = mac_filter->filter_type;
4483 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4494 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4496 struct i40e_mac_filter *f;
4497 struct i40e_macvlan_filter *mv_f;
4499 enum rte_mac_filter_type filter_type;
4500 int ret = I40E_SUCCESS;
4502 /* Can't find it, return an error */
4503 f = i40e_find_mac_filter(vsi, addr);
4505 return I40E_ERR_PARAM;
4507 vlan_num = vsi->vlan_num;
4508 filter_type = f->mac_info.filter_type;
4509 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4510 filter_type == RTE_MACVLAN_HASH_MATCH) {
4511 if (vlan_num == 0) {
4512 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4513 return I40E_ERR_PARAM;
4515 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4516 filter_type == RTE_MAC_HASH_MATCH)
4519 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4521 PMD_DRV_LOG(ERR, "failed to allocate memory");
4522 return I40E_ERR_NO_MEMORY;
4525 for (i = 0; i < vlan_num; i++) {
4526 mv_f[i].filter_type = filter_type;
4527 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4530 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4531 filter_type == RTE_MACVLAN_HASH_MATCH) {
4532 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4533 if (ret != I40E_SUCCESS)
4537 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4538 if (ret != I40E_SUCCESS)
4541 /* Remove the mac addr into mac list */
4542 TAILQ_REMOVE(&vsi->mac_list, f, next);
4552 /* Configure hash enable flags for RSS */
4554 i40e_config_hena(uint64_t flags)
4561 if (flags & ETH_RSS_NONF_IPV4_UDP)
4562 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4563 if (flags & ETH_RSS_NONF_IPV4_TCP)
4564 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4565 if (flags & ETH_RSS_NONF_IPV4_SCTP)
4566 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4567 if (flags & ETH_RSS_NONF_IPV4_OTHER)
4568 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4569 if (flags & ETH_RSS_FRAG_IPV4)
4570 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4571 if (flags & ETH_RSS_NONF_IPV6_UDP)
4572 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4573 if (flags & ETH_RSS_NONF_IPV6_TCP)
4574 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4575 if (flags & ETH_RSS_NONF_IPV6_SCTP)
4576 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4577 if (flags & ETH_RSS_NONF_IPV6_OTHER)
4578 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4579 if (flags & ETH_RSS_FRAG_IPV6)
4580 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4581 if (flags & ETH_RSS_L2_PAYLOAD)
4582 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4587 /* Parse the hash enable flags */
4589 i40e_parse_hena(uint64_t flags)
4591 uint64_t rss_hf = 0;
4596 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4597 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4598 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4599 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4600 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4601 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4602 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4603 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4604 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4605 rss_hf |= ETH_RSS_FRAG_IPV4;
4606 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4607 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4608 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4609 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4610 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4611 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4612 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4613 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4614 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4615 rss_hf |= ETH_RSS_FRAG_IPV6;
4616 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4617 rss_hf |= ETH_RSS_L2_PAYLOAD;
4624 i40e_pf_disable_rss(struct i40e_pf *pf)
4626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4629 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4630 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4631 hena &= ~I40E_RSS_HENA_ALL;
4632 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4633 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4634 I40E_WRITE_FLUSH(hw);
4638 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4641 uint8_t hash_key_len;
4646 hash_key = (uint32_t *)(rss_conf->rss_key);
4647 hash_key_len = rss_conf->rss_key_len;
4648 if (hash_key != NULL && hash_key_len >=
4649 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4650 /* Fill in RSS hash key */
4651 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4652 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4655 rss_hf = rss_conf->rss_hf;
4656 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4657 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4658 hena &= ~I40E_RSS_HENA_ALL;
4659 hena |= i40e_config_hena(rss_hf);
4660 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4661 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4662 I40E_WRITE_FLUSH(hw);
4668 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4669 struct rte_eth_rss_conf *rss_conf)
4671 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4675 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4676 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4677 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4678 if (rss_hf != 0) /* Enable RSS */
4680 return 0; /* Nothing to do */
4683 if (rss_hf == 0) /* Disable RSS */
4686 return i40e_hw_rss_hash_set(hw, rss_conf);
4690 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4691 struct rte_eth_rss_conf *rss_conf)
4693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4698 if (hash_key != NULL) {
4699 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4700 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4701 rss_conf->rss_key_len = i * sizeof(uint32_t);
4703 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4704 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4705 rss_conf->rss_hf = i40e_parse_hena(hena);
4711 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4713 switch (filter_type) {
4714 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4715 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4717 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4718 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4720 case RTE_TUNNEL_FILTER_IMAC_TENID:
4721 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4723 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4724 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4726 case ETH_TUNNEL_FILTER_IMAC:
4727 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4730 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4738 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4739 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4743 uint8_t tun_type = 0;
4745 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4746 struct i40e_vsi *vsi = pf->main_vsi;
4747 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4748 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4750 cld_filter = rte_zmalloc("tunnel_filter",
4751 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4754 if (NULL == cld_filter) {
4755 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4758 pfilter = cld_filter;
4760 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4761 sizeof(struct ether_addr));
4762 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4763 sizeof(struct ether_addr));
4765 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4766 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4767 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4768 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4769 &tunnel_filter->ip_addr,
4770 sizeof(pfilter->ipaddr.v4.data));
4772 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4773 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4774 &tunnel_filter->ip_addr,
4775 sizeof(pfilter->ipaddr.v6.data));
4778 /* check tunneled type */
4779 switch (tunnel_filter->tunnel_type) {
4780 case RTE_TUNNEL_TYPE_VXLAN:
4781 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4784 /* Other tunnel types is not supported. */
4785 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4786 rte_free(cld_filter);
4790 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4793 rte_free(cld_filter);
4797 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4798 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4799 pfilter->tenant_id = tunnel_filter->tenant_id;
4800 pfilter->queue_number = tunnel_filter->queue_id;
4803 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4805 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4808 rte_free(cld_filter);
4813 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4817 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4818 if (pf->vxlan_ports[i] == port)
4826 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4830 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4832 idx = i40e_get_vxlan_port_idx(pf, port);
4834 /* Check if port already exists */
4836 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4840 /* Now check if there is space to add the new port */
4841 idx = i40e_get_vxlan_port_idx(pf, 0);
4843 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4844 "not adding port %d", port);
4848 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4851 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4855 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4858 /* New port: add it and mark its index in the bitmap */
4859 pf->vxlan_ports[idx] = port;
4860 pf->vxlan_bitmap |= (1 << idx);
4862 if (!(pf->flags & I40E_FLAG_VXLAN))
4863 pf->flags |= I40E_FLAG_VXLAN;
4869 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4872 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4874 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4875 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4879 idx = i40e_get_vxlan_port_idx(pf, port);
4882 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4886 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4887 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4891 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4894 pf->vxlan_ports[idx] = 0;
4895 pf->vxlan_bitmap &= ~(1 << idx);
4897 if (!pf->vxlan_bitmap)
4898 pf->flags &= ~I40E_FLAG_VXLAN;
4903 /* Add UDP tunneling port */
4905 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4906 struct rte_eth_udp_tunnel *udp_tunnel)
4909 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4911 if (udp_tunnel == NULL)
4914 switch (udp_tunnel->prot_type) {
4915 case RTE_TUNNEL_TYPE_VXLAN:
4916 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4919 case RTE_TUNNEL_TYPE_GENEVE:
4920 case RTE_TUNNEL_TYPE_TEREDO:
4921 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4926 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4934 /* Remove UDP tunneling port */
4936 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4937 struct rte_eth_udp_tunnel *udp_tunnel)
4940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4942 if (udp_tunnel == NULL)
4945 switch (udp_tunnel->prot_type) {
4946 case RTE_TUNNEL_TYPE_VXLAN:
4947 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4949 case RTE_TUNNEL_TYPE_GENEVE:
4950 case RTE_TUNNEL_TYPE_TEREDO:
4951 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4955 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4963 /* Calculate the maximum number of contiguous PF queues that are configured */
4965 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4967 struct rte_eth_dev_data *data = pf->dev_data;
4969 struct i40e_rx_queue *rxq;
4972 for (i = 0; i < pf->lan_nb_qps; i++) {
4973 rxq = data->rx_queues[i];
4974 if (rxq && rxq->q_set)
4985 i40e_pf_config_rss(struct i40e_pf *pf)
4987 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4988 struct rte_eth_rss_conf rss_conf;
4989 uint32_t i, lut = 0;
4993 * If both VMDQ and RSS enabled, not all of PF queues are configured.
4994 * It's necessary to calulate the actual PF queues that are configured.
4996 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4997 num = i40e_pf_calc_configured_queues_num(pf);
4998 num = i40e_align_floor(num);
5000 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5002 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5006 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5010 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5013 lut = (lut << 8) | (j & ((0x1 <<
5014 hw->func_caps.rss_table_entry_width) - 1));
5016 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5019 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5020 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5021 i40e_pf_disable_rss(pf);
5024 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5025 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5026 /* Calculate the default hash key */
5027 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5028 rss_key_default[i] = (uint32_t)rte_rand();
5029 rss_conf.rss_key = (uint8_t *)rss_key_default;
5030 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5034 return i40e_hw_rss_hash_set(hw, &rss_conf);
5038 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5039 struct rte_eth_tunnel_filter_conf *filter)
5041 if (pf == NULL || filter == NULL) {
5042 PMD_DRV_LOG(ERR, "Invalid parameter");
5046 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5047 PMD_DRV_LOG(ERR, "Invalid queue ID");
5051 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5052 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5056 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5057 (is_zero_ether_addr(filter->outer_mac))) {
5058 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5062 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5063 (is_zero_ether_addr(filter->inner_mac))) {
5064 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5072 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5075 struct rte_eth_tunnel_filter_conf *filter;
5076 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5077 int ret = I40E_SUCCESS;
5079 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5081 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5082 return I40E_ERR_PARAM;
5084 switch (filter_op) {
5085 case RTE_ETH_FILTER_NOP:
5086 if (!(pf->flags & I40E_FLAG_VXLAN))
5087 ret = I40E_NOT_SUPPORTED;
5088 case RTE_ETH_FILTER_ADD:
5089 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5091 case RTE_ETH_FILTER_DELETE:
5092 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5095 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5096 ret = I40E_ERR_PARAM;
5104 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5107 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5109 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5110 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5115 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5116 ret = i40e_pf_config_rss(pf);
5118 i40e_pf_disable_rss(pf);
5124 * Configure ethertype filter, which can director packet by filtering
5125 * with mac address and ether_type or only ether_type
5128 i40e_ethertype_filter_set(struct i40e_pf *pf,
5129 struct rte_eth_ethertype_filter *filter,
5132 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5133 struct i40e_control_filter_stats stats;
5137 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5138 PMD_DRV_LOG(ERR, "Invalid queue ID");
5141 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5142 filter->ether_type == ETHER_TYPE_IPv6) {
5143 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5144 " control packet filter.", filter->ether_type);
5147 if (filter->ether_type == ETHER_TYPE_VLAN)
5148 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5151 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5152 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5153 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5154 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5155 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5157 memset(&stats, 0, sizeof(stats));
5158 ret = i40e_aq_add_rem_control_packet_filter(hw,
5159 filter->mac_addr.addr_bytes,
5160 filter->ether_type, flags,
5162 filter->queue, add, &stats, NULL);
5164 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5165 " mac_etype_used = %u, etype_used = %u,"
5166 " mac_etype_free = %u, etype_free = %u\n",
5167 ret, stats.mac_etype_used, stats.etype_used,
5168 stats.mac_etype_free, stats.etype_free);
5175 * Handle operations for ethertype filter.
5178 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5179 enum rte_filter_op filter_op,
5182 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5185 if (filter_op == RTE_ETH_FILTER_NOP)
5189 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5194 switch (filter_op) {
5195 case RTE_ETH_FILTER_ADD:
5196 ret = i40e_ethertype_filter_set(pf,
5197 (struct rte_eth_ethertype_filter *)arg,
5200 case RTE_ETH_FILTER_DELETE:
5201 ret = i40e_ethertype_filter_set(pf,
5202 (struct rte_eth_ethertype_filter *)arg,
5206 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5214 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5215 enum rte_filter_type filter_type,
5216 enum rte_filter_op filter_op,
5224 switch (filter_type) {
5225 case RTE_ETH_FILTER_MACVLAN:
5226 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5228 case RTE_ETH_FILTER_ETHERTYPE:
5229 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5231 case RTE_ETH_FILTER_TUNNEL:
5232 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5234 case RTE_ETH_FILTER_FDIR:
5235 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5238 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5247 enum i40e_filter_pctype
5248 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5250 static const enum i40e_filter_pctype pctype_table[] = {
5251 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5252 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5253 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5254 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5255 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5256 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5257 I40E_FILTER_PCTYPE_FRAG_IPV4,
5258 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5259 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5260 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5261 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5262 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5263 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5264 I40E_FILTER_PCTYPE_FRAG_IPV6,
5267 return pctype_table[flow_type];
5270 enum rte_eth_flow_type
5271 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5273 static const enum rte_eth_flow_type flowtype_table[] = {
5274 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5275 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5276 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5277 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5278 RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5279 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5280 RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5281 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5282 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5283 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5284 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5285 RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5286 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5287 RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5290 return flowtype_table[pctype];