lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_TYPE_UDPV4) | \
  98         (1UL << RTE_ETH_FLOW_TYPE_TCPV4) | \
  99         (1UL << RTE_ETH_FLOW_TYPE_SCTPV4) | \
 100         (1UL << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
 102         (1UL << RTE_ETH_FLOW_TYPE_UDPV6) | \
 103         (1UL << RTE_ETH_FLOW_TYPE_TCPV6) | \
 104         (1UL << RTE_ETH_FLOW_TYPE_SCTPV6) | \
 105         (1UL << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
 107
 108 static int eth_i40e_dev_init(\
 109                         __attribute__((unused)) struct eth_driver *eth_drv,
 110                         struct rte_eth_dev *eth_dev);
 111 static int i40e_dev_configure(struct rte_eth_dev *dev);
 112 static int i40e_dev_start(struct rte_eth_dev *dev);
 113 static void i40e_dev_stop(struct rte_eth_dev *dev);
 114 static void i40e_dev_close(struct rte_eth_dev *dev);
 115 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 116 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 117 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 118 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 119 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 120 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 121 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 122                                struct rte_eth_stats *stats);
 123 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 124 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 125                                             uint16_t queue_id,
 126                                             uint8_t stat_idx,
 127                                             uint8_t is_rx);
 128 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 129                               struct rte_eth_dev_info *dev_info);
 130 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 131                                 uint16_t vlan_id,
 132                                 int on);
 133 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 134 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 135 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 136                                       uint16_t queue,
 137                                       int on);
 138 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 139 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 140 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 141 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 142                               struct rte_eth_fc_conf *fc_conf);
 143 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 144                                        struct rte_eth_pfc_conf *pfc_conf);
 145 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 146                           struct ether_addr *mac_addr,
 147                           uint32_t index,
 148                           uint32_t pool);
 149 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 150 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 151                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 152                                     uint16_t reta_size);
 153 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 154                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 155                                    uint16_t reta_size);
 156
 157 static int i40e_get_cap(struct i40e_hw *hw);
 158 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 159 static int i40e_pf_setup(struct i40e_pf *pf);
 160 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 161 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 162 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 163                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 164 static void i40e_stat_update_48(struct i40e_hw *hw,
 165                                uint32_t hireg,
 166                                uint32_t loreg,
 167                                bool offset_loaded,
 168                                uint64_t *offset,
 169                                uint64_t *stat);
 170 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 171 static void i40e_dev_interrupt_handler(
 172                 __rte_unused struct rte_intr_handle *handle, void *param);
 173 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 174                                 uint32_t base, uint32_t num);
 175 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 176 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 177                         uint32_t base);
 178 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 179                         uint16_t num);
 180 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 181 static int i40e_veb_release(struct i40e_veb *veb);
 182 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 183                                                 struct i40e_vsi *vsi);
 184 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 185 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 186 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 187                                              struct i40e_macvlan_filter *mv_f,
 188                                              int num,
 189                                              struct ether_addr *addr);
 190 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 191                                              struct i40e_macvlan_filter *mv_f,
 192                                              int num,
 193                                              uint16_t vlan);
 194 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 195 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 196                                     struct rte_eth_rss_conf *rss_conf);
 197 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 198                                       struct rte_eth_rss_conf *rss_conf);
 199 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 200                                 struct rte_eth_udp_tunnel *udp_tunnel);
 201 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 202                                 struct rte_eth_udp_tunnel *udp_tunnel);
 203 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 204                         struct rte_eth_ethertype_filter *filter,
 205                         bool add);
 206 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 210                                 enum rte_filter_type filter_type,
 211                                 enum rte_filter_op filter_op,
 212                                 void *arg);
 213 static void i40e_configure_registers(struct i40e_hw *hw);
 214 static void i40e_hw_init(struct i40e_hw *hw);
 215
 216 static struct rte_pci_id pci_id_i40e_map[] = {
 217 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 218 #include "rte_pci_dev_ids.h"
 219 { .vendor_id = 0, /* sentinel */ },
 220 };
 221
 222 static struct eth_dev_ops i40e_eth_dev_ops = {
 223         .dev_configure                = i40e_dev_configure,
 224         .dev_start                    = i40e_dev_start,
 225         .dev_stop                     = i40e_dev_stop,
 226         .dev_close                    = i40e_dev_close,
 227         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 228         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 229         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 230         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 231         .dev_set_link_up              = i40e_dev_set_link_up,
 232         .dev_set_link_down            = i40e_dev_set_link_down,
 233         .link_update                  = i40e_dev_link_update,
 234         .stats_get                    = i40e_dev_stats_get,
 235         .stats_reset                  = i40e_dev_stats_reset,
 236         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 237         .dev_infos_get                = i40e_dev_info_get,
 238         .vlan_filter_set              = i40e_vlan_filter_set,
 239         .vlan_tpid_set                = i40e_vlan_tpid_set,
 240         .vlan_offload_set             = i40e_vlan_offload_set,
 241         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 242         .vlan_pvid_set                = i40e_vlan_pvid_set,
 243         .rx_queue_start               = i40e_dev_rx_queue_start,
 244         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 245         .tx_queue_start               = i40e_dev_tx_queue_start,
 246         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 247         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 248         .rx_queue_release             = i40e_dev_rx_queue_release,
 249         .rx_queue_count               = i40e_dev_rx_queue_count,
 250         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 251         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 252         .tx_queue_release             = i40e_dev_tx_queue_release,
 253         .dev_led_on                   = i40e_dev_led_on,
 254         .dev_led_off                  = i40e_dev_led_off,
 255         .flow_ctrl_set                = i40e_flow_ctrl_set,
 256         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 257         .mac_addr_add                 = i40e_macaddr_add,
 258         .mac_addr_remove              = i40e_macaddr_remove,
 259         .reta_update                  = i40e_dev_rss_reta_update,
 260         .reta_query                   = i40e_dev_rss_reta_query,
 261         .rss_hash_update              = i40e_dev_rss_hash_update,
 262         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 263         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 264         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 265         .filter_ctrl                  = i40e_dev_filter_ctrl,
 266 };
 267
 268 static struct eth_driver rte_i40e_pmd = {
 269         {
 270                 .name = "rte_i40e_pmd",
 271                 .id_table = pci_id_i40e_map,
 272                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 273         },
 274         .eth_dev_init = eth_i40e_dev_init,
 275         .dev_private_size = sizeof(struct i40e_adapter),
 276 };
 277
 278 static inline int
 279 i40e_align_floor(int n)
 280 {
 281         if (n == 0)
 282                 return 0;
 283         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 284 }
 285
 286 static inline int
 287 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 288                                      struct rte_eth_link *link)
 289 {
 290         struct rte_eth_link *dst = link;
 291         struct rte_eth_link *src = &(dev->data->dev_link);
 292
 293         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 294                                         *(uint64_t *)src) == 0)
 295                 return -1;
 296
 297         return 0;
 298 }
 299
 300 static inline int
 301 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 302                                       struct rte_eth_link *link)
 303 {
 304         struct rte_eth_link *dst = &(dev->data->dev_link);
 305         struct rte_eth_link *src = link;
 306
 307         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 308                                         *(uint64_t *)src) == 0)
 309                 return -1;
 310
 311         return 0;
 312 }
 313
 314 /*
 315  * Driver initialization routine.
 316  * Invoked once at EAL init time.
 317  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 318  */
 319 static int
 320 rte_i40e_pmd_init(const char *name __rte_unused,
 321                   const char *params __rte_unused)
 322 {
 323         PMD_INIT_FUNC_TRACE();
 324         rte_eth_driver_register(&rte_i40e_pmd);
 325
 326         return 0;
 327 }
 328
 329 static struct rte_driver rte_i40e_driver = {
 330         .type = PMD_PDEV,
 331         .init = rte_i40e_pmd_init,
 332 };
 333
 334 PMD_REGISTER_DRIVER(rte_i40e_driver);
 335
 336 /*
 337  * Initialize registers for flexible payload, which should be set by NVM.
 338  * This should be removed from code once it is fixed in NVM.
 339  */
 340 #ifndef I40E_GLQF_ORT
 341 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 342 #endif
 343 #ifndef I40E_GLQF_PIT
 344 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 345 #endif
 346
 347 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 348 {
 349         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 359
 360         /* GLQF_PIT Registers */
 361         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 362         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 363 }
 364
 365 static int
 366 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 367                   struct rte_eth_dev *dev)
 368 {
 369         struct rte_pci_device *pci_dev;
 370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 372         struct i40e_vsi *vsi;
 373         int ret;
 374         uint32_t len;
 375         uint8_t aq_fail = 0;
 376
 377         PMD_INIT_FUNC_TRACE();
 378
 379         dev->dev_ops = &i40e_eth_dev_ops;
 380         dev->rx_pkt_burst = i40e_recv_pkts;
 381         dev->tx_pkt_burst = i40e_xmit_pkts;
 382
 383         /* for secondary processes, we don't initialise any further as primary
 384          * has already done this work. Only check we don't need a different
 385          * RX function */
 386         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 387                 if (dev->data->scattered_rx)
 388                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 389                 return 0;
 390         }
 391         pci_dev = dev->pci_dev;
 392         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 393         pf->adapter->eth_dev = dev;
 394         pf->dev_data = dev->data;
 395
 396         hw->back = I40E_PF_TO_ADAPTER(pf);
 397         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 398         if (!hw->hw_addr) {
 399                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 400                              "as address is NULL");
 401                 return -ENODEV;
 402         }
 403
 404         hw->vendor_id = pci_dev->id.vendor_id;
 405         hw->device_id = pci_dev->id.device_id;
 406         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 407         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 408         hw->bus.device = pci_dev->addr.devid;
 409         hw->bus.func = pci_dev->addr.function;
 410
 411         /* Make sure all is clean before doing PF reset */
 412         i40e_clear_hw(hw);
 413
 414         /* Initialize the hardware */
 415         i40e_hw_init(hw);
 416
 417         /* Reset here to make sure all is clean for each PF */
 418         ret = i40e_pf_reset(hw);
 419         if (ret) {
 420                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 421                 return ret;
 422         }
 423
 424         /* Initialize the shared code (base driver) */
 425         ret = i40e_init_shared_code(hw);
 426         if (ret) {
 427                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 428                 return ret;
 429         }
 430
 431         /*
 432          * To work around the NVM issue,initialize registers
 433          * for flexible payload by software.
 434          * It should be removed once issues are fixed in NVM.
 435          */
 436         i40e_flex_payload_reg_init(hw);
 437
 438         /* Initialize the parameters for adminq */
 439         i40e_init_adminq_parameter(hw);
 440         ret = i40e_init_adminq(hw);
 441         if (ret != I40E_SUCCESS) {
 442                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 443                 return -EIO;
 444         }
 445         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 446                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 447                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 448                      ((hw->nvm.version >> 12) & 0xf),
 449                      ((hw->nvm.version >> 4) & 0xff),
 450                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 451
 452         /* Disable LLDP */
 453         ret = i40e_aq_stop_lldp(hw, true, NULL);
 454         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 455                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 456
 457         /* Clear PXE mode */
 458         i40e_clear_pxe_mode(hw);
 459
 460         /*
 461          * On X710, performance number is far from the expectation on recent
 462          * firmware versions. The fix for this issue may not be integrated in
 463          * the following firmware version. So the workaround in software driver
 464          * is needed. It needs to modify the initial values of 3 internal only
 465          * registers. Note that the workaround can be removed when it is fixed
 466          * in firmware in the future.
 467          */
 468         i40e_configure_registers(hw);
 469
 470         /* Get hw capabilities */
 471         ret = i40e_get_cap(hw);
 472         if (ret != I40E_SUCCESS) {
 473                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 474                 goto err_get_capabilities;
 475         }
 476
 477         /* Initialize parameters for PF */
 478         ret = i40e_pf_parameter_init(dev);
 479         if (ret != 0) {
 480                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 481                 goto err_parameter_init;
 482         }
 483
 484         /* Initialize the queue management */
 485         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 486         if (ret < 0) {
 487                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 488                 goto err_qp_pool_init;
 489         }
 490         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 491                                 hw->func_caps.num_msix_vectors - 1);
 492         if (ret < 0) {
 493                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 494                 goto err_msix_pool_init;
 495         }
 496
 497         /* Initialize lan hmc */
 498         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 499                                 hw->func_caps.num_rx_qp, 0, 0);
 500         if (ret != I40E_SUCCESS) {
 501                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 502                 goto err_init_lan_hmc;
 503         }
 504
 505         /* Configure lan hmc */
 506         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 507         if (ret != I40E_SUCCESS) {
 508                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 509                 goto err_configure_lan_hmc;
 510         }
 511
 512         /* Get and check the mac address */
 513         i40e_get_mac_addr(hw, hw->mac.addr);
 514         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 515                 PMD_INIT_LOG(ERR, "mac address is not valid");
 516                 ret = -EIO;
 517                 goto err_get_mac_addr;
 518         }
 519         /* Copy the permanent MAC address */
 520         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 521                         (struct ether_addr *) hw->mac.perm_addr);
 522
 523         /* Disable flow control */
 524         hw->fc.requested_mode = I40E_FC_NONE;
 525         i40e_set_fc(hw, &aq_fail, TRUE);
 526
 527         /* PF setup, which includes VSI setup */
 528         ret = i40e_pf_setup(pf);
 529         if (ret) {
 530                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 531                 goto err_setup_pf_switch;
 532         }
 533
 534         vsi = pf->main_vsi;
 535
 536         /* Disable double vlan by default */
 537         i40e_vsi_config_double_vlan(vsi, FALSE);
 538
 539         if (!vsi->max_macaddrs)
 540                 len = ETHER_ADDR_LEN;
 541         else
 542                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 543
 544         /* Should be after VSI initialized */
 545         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 546         if (!dev->data->mac_addrs) {
 547                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 548                                         "for storing mac address");
 549                 goto err_mac_alloc;
 550         }
 551         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 552                                         &dev->data->mac_addrs[0]);
 553
 554         /* initialize pf host driver to setup SRIOV resource if applicable */
 555         i40e_pf_host_init(dev);
 556
 557         /* register callback func to eal lib */
 558         rte_intr_callback_register(&(pci_dev->intr_handle),
 559                 i40e_dev_interrupt_handler, (void *)dev);
 560
 561         /* configure and enable device interrupt */
 562         i40e_pf_config_irq0(hw);
 563         i40e_pf_enable_irq0(hw);
 564
 565         /* enable uio intr after callback register */
 566         rte_intr_enable(&(pci_dev->intr_handle));
 567
 568         return 0;
 569
 570 err_mac_alloc:
 571         i40e_vsi_release(pf->main_vsi);
 572 err_setup_pf_switch:
 573 err_get_mac_addr:
 574 err_configure_lan_hmc:
 575         (void)i40e_shutdown_lan_hmc(hw);
 576 err_init_lan_hmc:
 577         i40e_res_pool_destroy(&pf->msix_pool);
 578 err_msix_pool_init:
 579         i40e_res_pool_destroy(&pf->qp_pool);
 580 err_qp_pool_init:
 581 err_parameter_init:
 582 err_get_capabilities:
 583         (void)i40e_shutdown_adminq(hw);
 584
 585         return ret;
 586 }
 587
 588 static int
 589 i40e_dev_configure(struct rte_eth_dev *dev)
 590 {
 591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 592         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 593         int ret;
 594
 595         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 596                 ret = i40e_fdir_setup(pf);
 597                 if (ret != I40E_SUCCESS) {
 598                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 599                         return -ENOTSUP;
 600                 }
 601                 ret = i40e_fdir_configure(dev);
 602                 if (ret < 0) {
 603                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 604                         goto err;
 605                 }
 606         } else
 607                 i40e_fdir_teardown(pf);
 608
 609         ret = i40e_dev_init_vlan(dev);
 610         if (ret < 0)
 611                 goto err;
 612
 613         /* VMDQ setup.
 614          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 615          *  RSS setting have different requirements.
 616          *  General PMD driver call sequence are NIC init, configure,
 617          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 618          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 619          *  applicable. So, VMDQ setting has to be done before
 620          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 621          *  For RSS setting, it will try to calculate actual configured RX queue
 622          *  number, which will be available after rx_queue_setup(). dev_start()
 623          *  function is good to place RSS setup.
 624          */
 625         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 626                 ret = i40e_vmdq_setup(dev);
 627                 if (ret)
 628                         goto err;
 629         }
 630         return 0;
 631 err:
 632         i40e_fdir_teardown(pf);
 633         return ret;
 634 }
 635
 636 void
 637 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 638 {
 639         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 640         uint16_t msix_vect = vsi->msix_intr;
 641         uint16_t i;
 642
 643         for (i = 0; i < vsi->nb_qps; i++) {
 644                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 645                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 646                 rte_wmb();
 647         }
 648
 649         if (vsi->type != I40E_VSI_SRIOV) {
 650                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 651                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 652                                 msix_vect - 1), 0);
 653         } else {
 654                 uint32_t reg;
 655                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 656                         vsi->user_param + (msix_vect - 1);
 657
 658                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 659         }
 660         I40E_WRITE_FLUSH(hw);
 661 }
 662
 663 static inline uint16_t
 664 i40e_calc_itr_interval(int16_t interval)
 665 {
 666         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 667                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 668
 669         /* Convert to hardware count, as writing each 1 represents 2 us */
 670         return (interval/2);
 671 }
 672
 673 void
 674 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 675 {
 676         uint32_t val;
 677         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 678         uint16_t msix_vect = vsi->msix_intr;
 679         int i;
 680
 681         for (i = 0; i < vsi->nb_qps; i++)
 682                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 683
 684         /* Bind all RX queues to allocated MSIX interrupt */
 685         for (i = 0; i < vsi->nb_qps; i++) {
 686                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 687                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 688                         ((vsi->base_queue + i + 1) <<
 689                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 690                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 691                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 692
 693                 if (i == vsi->nb_qps - 1)
 694                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 695                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 696         }
 697
 698         /* Write first RX queue to Link list register as the head element */
 699         if (vsi->type != I40E_VSI_SRIOV) {
 700                 uint16_t interval =
 701                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 702
 703                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 704                                                 (vsi->base_queue <<
 705                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 706                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 707
 708                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 709                                                 msix_vect - 1), interval);
 710
 711 #ifndef I40E_GLINT_CTL
 712 #define I40E_GLINT_CTL                     0x0003F800
 713 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 714 #endif
 715                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 716                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 717                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 718         } else {
 719                 uint32_t reg;
 720
 721                 /* num_msix_vectors_vf needs to minus irq0 */
 722                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 723                         vsi->user_param + (msix_vect - 1);
 724
 725                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 726                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 727                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 728         }
 729
 730         I40E_WRITE_FLUSH(hw);
 731 }
 732
 733 static void
 734 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 735 {
 736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 737         uint16_t interval = i40e_calc_itr_interval(\
 738                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 739
 740         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 741                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 742                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 743                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 744                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 745 }
 746
 747 static void
 748 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 749 {
 750         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 751
 752         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 753 }
 754
 755 static inline uint8_t
 756 i40e_parse_link_speed(uint16_t eth_link_speed)
 757 {
 758         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 759
 760         switch (eth_link_speed) {
 761         case ETH_LINK_SPEED_40G:
 762                 link_speed = I40E_LINK_SPEED_40GB;
 763                 break;
 764         case ETH_LINK_SPEED_20G:
 765                 link_speed = I40E_LINK_SPEED_20GB;
 766                 break;
 767         case ETH_LINK_SPEED_10G:
 768                 link_speed = I40E_LINK_SPEED_10GB;
 769                 break;
 770         case ETH_LINK_SPEED_1000:
 771                 link_speed = I40E_LINK_SPEED_1GB;
 772                 break;
 773         case ETH_LINK_SPEED_100:
 774                 link_speed = I40E_LINK_SPEED_100MB;
 775                 break;
 776         }
 777
 778         return link_speed;
 779 }
 780
 781 static int
 782 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 783 {
 784         enum i40e_status_code status;
 785         struct i40e_aq_get_phy_abilities_resp phy_ab;
 786         struct i40e_aq_set_phy_config phy_conf;
 787         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 788                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 789                         I40E_AQ_PHY_FLAG_LOW_POWER;
 790         const uint8_t advt = I40E_LINK_SPEED_40GB |
 791                         I40E_LINK_SPEED_10GB |
 792                         I40E_LINK_SPEED_1GB |
 793                         I40E_LINK_SPEED_100MB;
 794         int ret = -ENOTSUP;
 795
 796         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 797                                               NULL);
 798         if (status)
 799                 return ret;
 800
 801         memset(&phy_conf, 0, sizeof(phy_conf));
 802
 803         /* bits 0-2 use the values from get_phy_abilities_resp */
 804         abilities &= ~mask;
 805         abilities |= phy_ab.abilities & mask;
 806
 807         /* update ablities and speed */
 808         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 809                 phy_conf.link_speed = advt;
 810         else
 811                 phy_conf.link_speed = force_speed;
 812
 813         phy_conf.abilities = abilities;
 814
 815         /* use get_phy_abilities_resp value for the rest */
 816         phy_conf.phy_type = phy_ab.phy_type;
 817         phy_conf.eee_capability = phy_ab.eee_capability;
 818         phy_conf.eeer = phy_ab.eeer_val;
 819         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 820
 821         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 822                     phy_ab.abilities, phy_ab.link_speed);
 823         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 824                     phy_conf.abilities, phy_conf.link_speed);
 825
 826         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 827         if (status)
 828                 return ret;
 829
 830         return I40E_SUCCESS;
 831 }
 832
 833 static int
 834 i40e_apply_link_speed(struct rte_eth_dev *dev)
 835 {
 836         uint8_t speed;
 837         uint8_t abilities = 0;
 838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839         struct rte_eth_conf *conf = &dev->data->dev_conf;
 840
 841         speed = i40e_parse_link_speed(conf->link_speed);
 842         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 843         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 844                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 845         else
 846                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 847
 848         return i40e_phy_conf_link(hw, abilities, speed);
 849 }
 850
 851 static int
 852 i40e_dev_start(struct rte_eth_dev *dev)
 853 {
 854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 856         struct i40e_vsi *main_vsi = pf->main_vsi;
 857         int ret, i;
 858
 859         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 860                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 861                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 862                              dev->data->dev_conf.link_duplex,
 863                              dev->data->port_id);
 864                 return -EINVAL;
 865         }
 866
 867         /* Initialize VSI */
 868         ret = i40e_dev_rxtx_init(pf);
 869         if (ret != I40E_SUCCESS) {
 870                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 871                 goto err_up;
 872         }
 873
 874         /* Map queues with MSIX interrupt */
 875         i40e_vsi_queues_bind_intr(main_vsi);
 876         i40e_vsi_enable_queues_intr(main_vsi);
 877
 878         /* Map VMDQ VSI queues with MSIX interrupt */
 879         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 880                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 881                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 882         }
 883
 884         /* enable FDIR MSIX interrupt */
 885         if (pf->fdir.fdir_vsi) {
 886                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 887                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 888         }
 889
 890         /* Enable all queues which have been configured */
 891         ret = i40e_dev_switch_queues(pf, TRUE);
 892         if (ret != I40E_SUCCESS) {
 893                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 894                 goto err_up;
 895         }
 896
 897         /* Enable receiving broadcast packets */
 898         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 899         if (ret != I40E_SUCCESS)
 900                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 901
 902         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 903                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 904                                                 true, NULL);
 905                 if (ret != I40E_SUCCESS)
 906                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 907         }
 908
 909         /* Apply link configure */
 910         ret = i40e_apply_link_speed(dev);
 911         if (I40E_SUCCESS != ret) {
 912                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 913                 goto err_up;
 914         }
 915
 916         return I40E_SUCCESS;
 917
 918 err_up:
 919         i40e_dev_switch_queues(pf, FALSE);
 920         i40e_dev_clear_queues(dev);
 921
 922         return ret;
 923 }
 924
 925 static void
 926 i40e_dev_stop(struct rte_eth_dev *dev)
 927 {
 928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 929         struct i40e_vsi *main_vsi = pf->main_vsi;
 930         int i;
 931
 932         /* Disable all queues */
 933         i40e_dev_switch_queues(pf, FALSE);
 934
 935         /* un-map queues with interrupt registers */
 936         i40e_vsi_disable_queues_intr(main_vsi);
 937         i40e_vsi_queues_unbind_intr(main_vsi);
 938
 939         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 940                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 941                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 942         }
 943
 944         if (pf->fdir.fdir_vsi) {
 945                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 946                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 947         }
 948         /* Clear all queues and release memory */
 949         i40e_dev_clear_queues(dev);
 950
 951         /* Set link down */
 952         i40e_dev_set_link_down(dev);
 953
 954 }
 955
 956 static void
 957 i40e_dev_close(struct rte_eth_dev *dev)
 958 {
 959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         uint32_t reg;
 962
 963         PMD_INIT_FUNC_TRACE();
 964
 965         i40e_dev_stop(dev);
 966
 967         /* Disable interrupt */
 968         i40e_pf_disable_irq0(hw);
 969         rte_intr_disable(&(dev->pci_dev->intr_handle));
 970
 971         /* shutdown and destroy the HMC */
 972         i40e_shutdown_lan_hmc(hw);
 973
 974         /* release all the existing VSIs and VEBs */
 975         i40e_fdir_teardown(pf);
 976         i40e_vsi_release(pf->main_vsi);
 977
 978         /* shutdown the adminq */
 979         i40e_aq_queue_shutdown(hw, true);
 980         i40e_shutdown_adminq(hw);
 981
 982         i40e_res_pool_destroy(&pf->qp_pool);
 983         i40e_res_pool_destroy(&pf->msix_pool);
 984
 985         /* force a PF reset to clean anything leftover */
 986         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 987         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 988                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 989         I40E_WRITE_FLUSH(hw);
 990 }
 991
 992 static void
 993 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 994 {
 995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 996         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         struct i40e_vsi *vsi = pf->main_vsi;
 998         int status;
 999
1000         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1001                                                         true, NULL);
1002         if (status != I40E_SUCCESS)
1003                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1004
1005         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1006                                                         TRUE, NULL);
1007         if (status != I40E_SUCCESS)
1008                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1009
1010 }
1011
1012 static void
1013 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1014 {
1015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct i40e_vsi *vsi = pf->main_vsi;
1018         int status;
1019
1020         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1021                                                         false, NULL);
1022         if (status != I40E_SUCCESS)
1023                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1024
1025         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1026                                                         false, NULL);
1027         if (status != I40E_SUCCESS)
1028                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1029 }
1030
1031 static void
1032 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1033 {
1034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         struct i40e_vsi *vsi = pf->main_vsi;
1037         int ret;
1038
1039         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1040         if (ret != I40E_SUCCESS)
1041                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1042 }
1043
1044 static void
1045 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_vsi *vsi = pf->main_vsi;
1050         int ret;
1051
1052         if (dev->data->promiscuous == 1)
1053                 return; /* must remain in all_multicast mode */
1054
1055         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1056                                 vsi->seid, FALSE, NULL);
1057         if (ret != I40E_SUCCESS)
1058                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1059 }
1060
1061 /*
1062  * Set device link up.
1063  */
1064 static int
1065 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1066 {
1067         /* re-apply link speed setting */
1068         return i40e_apply_link_speed(dev);
1069 }
1070
1071 /*
1072  * Set device link down.
1073  */
1074 static int
1075 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1076 {
1077         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1078         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1080
1081         return i40e_phy_conf_link(hw, abilities, speed);
1082 }
1083
1084 int
1085 i40e_dev_link_update(struct rte_eth_dev *dev,
1086                      __rte_unused int wait_to_complete)
1087 {
1088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct i40e_link_status link_status;
1090         struct rte_eth_link link, old;
1091         int status;
1092
1093         memset(&link, 0, sizeof(link));
1094         memset(&old, 0, sizeof(old));
1095         memset(&link_status, 0, sizeof(link_status));
1096         rte_i40e_dev_atomic_read_link_status(dev, &old);
1097
1098         /* Get link status information from hardware */
1099         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1100         if (status != I40E_SUCCESS) {
1101                 link.link_speed = ETH_LINK_SPEED_100;
1102                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1103                 PMD_DRV_LOG(ERR, "Failed to get link info");
1104                 goto out;
1105         }
1106
1107         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1108
1109         if (!link.link_status)
1110                 goto out;
1111
1112         /* i40e uses full duplex only */
1113         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1114
1115         /* Parse the link status */
1116         switch (link_status.link_speed) {
1117         case I40E_LINK_SPEED_100MB:
1118                 link.link_speed = ETH_LINK_SPEED_100;
1119                 break;
1120         case I40E_LINK_SPEED_1GB:
1121                 link.link_speed = ETH_LINK_SPEED_1000;
1122                 break;
1123         case I40E_LINK_SPEED_10GB:
1124                 link.link_speed = ETH_LINK_SPEED_10G;
1125                 break;
1126         case I40E_LINK_SPEED_20GB:
1127                 link.link_speed = ETH_LINK_SPEED_20G;
1128                 break;
1129         case I40E_LINK_SPEED_40GB:
1130                 link.link_speed = ETH_LINK_SPEED_40G;
1131                 break;
1132         default:
1133                 link.link_speed = ETH_LINK_SPEED_100;
1134                 break;
1135         }
1136
1137 out:
1138         rte_i40e_dev_atomic_write_link_status(dev, &link);
1139         if (link.link_status == old.link_status)
1140                 return -1;
1141
1142         return 0;
1143 }
1144
1145 /* Get all the statistics of a VSI */
1146 void
1147 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1148 {
1149         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1150         struct i40e_eth_stats *nes = &vsi->eth_stats;
1151         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1152         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1153
1154         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1155                             vsi->offset_loaded, &oes->rx_bytes,
1156                             &nes->rx_bytes);
1157         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1158                             vsi->offset_loaded, &oes->rx_unicast,
1159                             &nes->rx_unicast);
1160         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1161                             vsi->offset_loaded, &oes->rx_multicast,
1162                             &nes->rx_multicast);
1163         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1164                             vsi->offset_loaded, &oes->rx_broadcast,
1165                             &nes->rx_broadcast);
1166         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1167                             &oes->rx_discards, &nes->rx_discards);
1168         /* GLV_REPC not supported */
1169         /* GLV_RMPC not supported */
1170         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1171                             &oes->rx_unknown_protocol,
1172                             &nes->rx_unknown_protocol);
1173         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1174                             vsi->offset_loaded, &oes->tx_bytes,
1175                             &nes->tx_bytes);
1176         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1177                             vsi->offset_loaded, &oes->tx_unicast,
1178                             &nes->tx_unicast);
1179         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1180                             vsi->offset_loaded, &oes->tx_multicast,
1181                             &nes->tx_multicast);
1182         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1183                             vsi->offset_loaded,  &oes->tx_broadcast,
1184                             &nes->tx_broadcast);
1185         /* GLV_TDPC not supported */
1186         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1187                             &oes->tx_errors, &nes->tx_errors);
1188         vsi->offset_loaded = true;
1189
1190         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1191                     vsi->vsi_id);
1192         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1193         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1194         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1195         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1196         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1197         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1198                     nes->rx_unknown_protocol);
1199         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1200         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1201         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1202         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1203         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1204         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1205         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1206                     vsi->vsi_id);
1207 }
1208
1209 /* Get all statistics of a port */
1210 static void
1211 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1212 {
1213         uint32_t i;
1214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1216         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1217         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1218
1219         /* Get statistics of struct i40e_eth_stats */
1220         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1221                             I40E_GLPRT_GORCL(hw->port),
1222                             pf->offset_loaded, &os->eth.rx_bytes,
1223                             &ns->eth.rx_bytes);
1224         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1225                             I40E_GLPRT_UPRCL(hw->port),
1226                             pf->offset_loaded, &os->eth.rx_unicast,
1227                             &ns->eth.rx_unicast);
1228         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1229                             I40E_GLPRT_MPRCL(hw->port),
1230                             pf->offset_loaded, &os->eth.rx_multicast,
1231                             &ns->eth.rx_multicast);
1232         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1233                             I40E_GLPRT_BPRCL(hw->port),
1234                             pf->offset_loaded, &os->eth.rx_broadcast,
1235                             &ns->eth.rx_broadcast);
1236         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1237                             pf->offset_loaded, &os->eth.rx_discards,
1238                             &ns->eth.rx_discards);
1239         /* GLPRT_REPC not supported */
1240         /* GLPRT_RMPC not supported */
1241         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1242                             pf->offset_loaded,
1243                             &os->eth.rx_unknown_protocol,
1244                             &ns->eth.rx_unknown_protocol);
1245         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1246                             I40E_GLPRT_GOTCL(hw->port),
1247                             pf->offset_loaded, &os->eth.tx_bytes,
1248                             &ns->eth.tx_bytes);
1249         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1250                             I40E_GLPRT_UPTCL(hw->port),
1251                             pf->offset_loaded, &os->eth.tx_unicast,
1252                             &ns->eth.tx_unicast);
1253         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1254                             I40E_GLPRT_MPTCL(hw->port),
1255                             pf->offset_loaded, &os->eth.tx_multicast,
1256                             &ns->eth.tx_multicast);
1257         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1258                             I40E_GLPRT_BPTCL(hw->port),
1259                             pf->offset_loaded, &os->eth.tx_broadcast,
1260                             &ns->eth.tx_broadcast);
1261         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1262                             pf->offset_loaded, &os->eth.tx_discards,
1263                             &ns->eth.tx_discards);
1264         /* GLPRT_TEPC not supported */
1265
1266         /* additional port specific stats */
1267         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1268                             pf->offset_loaded, &os->tx_dropped_link_down,
1269                             &ns->tx_dropped_link_down);
1270         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1271                             pf->offset_loaded, &os->crc_errors,
1272                             &ns->crc_errors);
1273         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1274                             pf->offset_loaded, &os->illegal_bytes,
1275                             &ns->illegal_bytes);
1276         /* GLPRT_ERRBC not supported */
1277         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1278                             pf->offset_loaded, &os->mac_local_faults,
1279                             &ns->mac_local_faults);
1280         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1281                             pf->offset_loaded, &os->mac_remote_faults,
1282                             &ns->mac_remote_faults);
1283         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1284                             pf->offset_loaded, &os->rx_length_errors,
1285                             &ns->rx_length_errors);
1286         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1287                             pf->offset_loaded, &os->link_xon_rx,
1288                             &ns->link_xon_rx);
1289         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1290                             pf->offset_loaded, &os->link_xoff_rx,
1291                             &ns->link_xoff_rx);
1292         for (i = 0; i < 8; i++) {
1293                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1294                                     pf->offset_loaded,
1295                                     &os->priority_xon_rx[i],
1296                                     &ns->priority_xon_rx[i]);
1297                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1298                                     pf->offset_loaded,
1299                                     &os->priority_xoff_rx[i],
1300                                     &ns->priority_xoff_rx[i]);
1301         }
1302         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1303                             pf->offset_loaded, &os->link_xon_tx,
1304                             &ns->link_xon_tx);
1305         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1306                             pf->offset_loaded, &os->link_xoff_tx,
1307                             &ns->link_xoff_tx);
1308         for (i = 0; i < 8; i++) {
1309                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1310                                     pf->offset_loaded,
1311                                     &os->priority_xon_tx[i],
1312                                     &ns->priority_xon_tx[i]);
1313                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1314                                     pf->offset_loaded,
1315                                     &os->priority_xoff_tx[i],
1316                                     &ns->priority_xoff_tx[i]);
1317                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1318                                     pf->offset_loaded,
1319                                     &os->priority_xon_2_xoff[i],
1320                                     &ns->priority_xon_2_xoff[i]);
1321         }
1322         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1323                             I40E_GLPRT_PRC64L(hw->port),
1324                             pf->offset_loaded, &os->rx_size_64,
1325                             &ns->rx_size_64);
1326         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1327                             I40E_GLPRT_PRC127L(hw->port),
1328                             pf->offset_loaded, &os->rx_size_127,
1329                             &ns->rx_size_127);
1330         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1331                             I40E_GLPRT_PRC255L(hw->port),
1332                             pf->offset_loaded, &os->rx_size_255,
1333                             &ns->rx_size_255);
1334         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1335                             I40E_GLPRT_PRC511L(hw->port),
1336                             pf->offset_loaded, &os->rx_size_511,
1337                             &ns->rx_size_511);
1338         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1339                             I40E_GLPRT_PRC1023L(hw->port),
1340                             pf->offset_loaded, &os->rx_size_1023,
1341                             &ns->rx_size_1023);
1342         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1343                             I40E_GLPRT_PRC1522L(hw->port),
1344                             pf->offset_loaded, &os->rx_size_1522,
1345                             &ns->rx_size_1522);
1346         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1347                             I40E_GLPRT_PRC9522L(hw->port),
1348                             pf->offset_loaded, &os->rx_size_big,
1349                             &ns->rx_size_big);
1350         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1351                             pf->offset_loaded, &os->rx_undersize,
1352                             &ns->rx_undersize);
1353         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1354                             pf->offset_loaded, &os->rx_fragments,
1355                             &ns->rx_fragments);
1356         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1357                             pf->offset_loaded, &os->rx_oversize,
1358                             &ns->rx_oversize);
1359         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1360                             pf->offset_loaded, &os->rx_jabber,
1361                             &ns->rx_jabber);
1362         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1363                             I40E_GLPRT_PTC64L(hw->port),
1364                             pf->offset_loaded, &os->tx_size_64,
1365                             &ns->tx_size_64);
1366         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1367                             I40E_GLPRT_PTC127L(hw->port),
1368                             pf->offset_loaded, &os->tx_size_127,
1369                             &ns->tx_size_127);
1370         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1371                             I40E_GLPRT_PTC255L(hw->port),
1372                             pf->offset_loaded, &os->tx_size_255,
1373                             &ns->tx_size_255);
1374         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1375                             I40E_GLPRT_PTC511L(hw->port),
1376                             pf->offset_loaded, &os->tx_size_511,
1377                             &ns->tx_size_511);
1378         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1379                             I40E_GLPRT_PTC1023L(hw->port),
1380                             pf->offset_loaded, &os->tx_size_1023,
1381                             &ns->tx_size_1023);
1382         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1383                             I40E_GLPRT_PTC1522L(hw->port),
1384                             pf->offset_loaded, &os->tx_size_1522,
1385                             &ns->tx_size_1522);
1386         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1387                             I40E_GLPRT_PTC9522L(hw->port),
1388                             pf->offset_loaded, &os->tx_size_big,
1389                             &ns->tx_size_big);
1390         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1391                            pf->offset_loaded,
1392                            &os->fd_sb_match, &ns->fd_sb_match);
1393         /* GLPRT_MSPDC not supported */
1394         /* GLPRT_XEC not supported */
1395
1396         pf->offset_loaded = true;
1397
1398         if (pf->main_vsi)
1399                 i40e_update_vsi_stats(pf->main_vsi);
1400
1401         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1402                                                 ns->eth.rx_broadcast;
1403         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1404                                                 ns->eth.tx_broadcast;
1405         stats->ibytes   = ns->eth.rx_bytes;
1406         stats->obytes   = ns->eth.tx_bytes;
1407         stats->oerrors  = ns->eth.tx_errors;
1408         stats->imcasts  = ns->eth.rx_multicast;
1409         stats->fdirmatch = ns->fd_sb_match;
1410
1411         /* Rx Errors */
1412         stats->ibadcrc  = ns->crc_errors;
1413         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1414                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1415         stats->imissed  = ns->eth.rx_discards;
1416         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1417
1418         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1419         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1420         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1421         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1422         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1423         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1424         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1425                     ns->eth.rx_unknown_protocol);
1426         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1427         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1428         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1429         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1430         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1431         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1432
1433         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1434                     ns->tx_dropped_link_down);
1435         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1436         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1437                     ns->illegal_bytes);
1438         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1439         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1440                     ns->mac_local_faults);
1441         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1442                     ns->mac_remote_faults);
1443         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1444                     ns->rx_length_errors);
1445         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1446         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1447         for (i = 0; i < 8; i++) {
1448                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1449                                 i, ns->priority_xon_rx[i]);
1450                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1451                                 i, ns->priority_xoff_rx[i]);
1452         }
1453         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1454         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1455         for (i = 0; i < 8; i++) {
1456                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1457                                 i, ns->priority_xon_tx[i]);
1458                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1459                                 i, ns->priority_xoff_tx[i]);
1460                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1461                                 i, ns->priority_xon_2_xoff[i]);
1462         }
1463         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1464         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1465         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1466         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1467         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1468         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1469         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1470         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1471         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1472         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1473         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1474         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1475         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1476         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1477         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1478         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1479         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1480         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1481         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1482                         ns->mac_short_packet_dropped);
1483         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1484                     ns->checksum_error);
1485         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1486         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1487 }
1488
1489 /* Reset the statistics */
1490 static void
1491 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1492 {
1493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1494
1495         /* It results in reloading the start point of each counter */
1496         pf->offset_loaded = false;
1497 }
1498
1499 static int
1500 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1501                                  __rte_unused uint16_t queue_id,
1502                                  __rte_unused uint8_t stat_idx,
1503                                  __rte_unused uint8_t is_rx)
1504 {
1505         PMD_INIT_FUNC_TRACE();
1506
1507         return -ENOSYS;
1508 }
1509
1510 static void
1511 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1512 {
1513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1514         struct i40e_vsi *vsi = pf->main_vsi;
1515
1516         dev_info->max_rx_queues = vsi->nb_qps;
1517         dev_info->max_tx_queues = vsi->nb_qps;
1518         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1519         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1520         dev_info->max_mac_addrs = vsi->max_macaddrs;
1521         dev_info->max_vfs = dev->pci_dev->max_vfs;
1522         dev_info->rx_offload_capa =
1523                 DEV_RX_OFFLOAD_VLAN_STRIP |
1524                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1525                 DEV_RX_OFFLOAD_UDP_CKSUM |
1526                 DEV_RX_OFFLOAD_TCP_CKSUM;
1527         dev_info->tx_offload_capa =
1528                 DEV_TX_OFFLOAD_VLAN_INSERT |
1529                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1530                 DEV_TX_OFFLOAD_UDP_CKSUM |
1531                 DEV_TX_OFFLOAD_TCP_CKSUM |
1532                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1533         dev_info->reta_size = pf->hash_lut_size;
1534
1535         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1536                 .rx_thresh = {
1537                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1538                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1539                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1540                 },
1541                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1542                 .rx_drop_en = 0,
1543         };
1544
1545         dev_info->default_txconf = (struct rte_eth_txconf) {
1546                 .tx_thresh = {
1547                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1548                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1549                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1550                 },
1551                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1552                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1553                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1554                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1555         };
1556
1557         if (pf->flags | I40E_FLAG_VMDQ) {
1558                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1559                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1560                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1561                                                 pf->max_nb_vmdq_vsi;
1562                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1563                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1564                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1565         }
1566 }
1567
1568 static int
1569 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1570 {
1571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1572         struct i40e_vsi *vsi = pf->main_vsi;
1573         PMD_INIT_FUNC_TRACE();
1574
1575         if (on)
1576                 return i40e_vsi_add_vlan(vsi, vlan_id);
1577         else
1578                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1579 }
1580
1581 static void
1582 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1583                    __rte_unused uint16_t tpid)
1584 {
1585         PMD_INIT_FUNC_TRACE();
1586 }
1587
1588 static void
1589 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1590 {
1591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1592         struct i40e_vsi *vsi = pf->main_vsi;
1593
1594         if (mask & ETH_VLAN_STRIP_MASK) {
1595                 /* Enable or disable VLAN stripping */
1596                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1597                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1598                 else
1599                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1600         }
1601
1602         if (mask & ETH_VLAN_EXTEND_MASK) {
1603                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1604                         i40e_vsi_config_double_vlan(vsi, TRUE);
1605                 else
1606                         i40e_vsi_config_double_vlan(vsi, FALSE);
1607         }
1608 }
1609
1610 static void
1611 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1612                           __rte_unused uint16_t queue,
1613                           __rte_unused int on)
1614 {
1615         PMD_INIT_FUNC_TRACE();
1616 }
1617
1618 static int
1619 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1620 {
1621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1622         struct i40e_vsi *vsi = pf->main_vsi;
1623         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1624         struct i40e_vsi_vlan_pvid_info info;
1625
1626         memset(&info, 0, sizeof(info));
1627         info.on = on;
1628         if (info.on)
1629                 info.config.pvid = pvid;
1630         else {
1631                 info.config.reject.tagged =
1632                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1633                 info.config.reject.untagged =
1634                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1635         }
1636
1637         return i40e_vsi_vlan_pvid_set(vsi, &info);
1638 }
1639
1640 static int
1641 i40e_dev_led_on(struct rte_eth_dev *dev)
1642 {
1643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644         uint32_t mode = i40e_led_get(hw);
1645
1646         if (mode == 0)
1647                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1648
1649         return 0;
1650 }
1651
1652 static int
1653 i40e_dev_led_off(struct rte_eth_dev *dev)
1654 {
1655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         uint32_t mode = i40e_led_get(hw);
1657
1658         if (mode != 0)
1659                 i40e_led_set(hw, 0, false);
1660
1661         return 0;
1662 }
1663
1664 static int
1665 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1666                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1667 {
1668         PMD_INIT_FUNC_TRACE();
1669
1670         return -ENOSYS;
1671 }
1672
1673 static int
1674 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1675                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1676 {
1677         PMD_INIT_FUNC_TRACE();
1678
1679         return -ENOSYS;
1680 }
1681
1682 /* Add a MAC address, and update filters */
1683 static void
1684 i40e_macaddr_add(struct rte_eth_dev *dev,
1685                  struct ether_addr *mac_addr,
1686                  __rte_unused uint32_t index,
1687                  uint32_t pool)
1688 {
1689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1690         struct i40e_mac_filter_info mac_filter;
1691         struct i40e_vsi *vsi;
1692         int ret;
1693
1694         /* If VMDQ not enabled or configured, return */
1695         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1696                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1697                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1698                         pool);
1699                 return;
1700         }
1701
1702         if (pool > pf->nb_cfg_vmdq_vsi) {
1703                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1704                                 pool, pf->nb_cfg_vmdq_vsi);
1705                 return;
1706         }
1707
1708         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1709         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1710
1711         if (pool == 0)
1712                 vsi = pf->main_vsi;
1713         else
1714                 vsi = pf->vmdq[pool - 1].vsi;
1715
1716         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1717         if (ret != I40E_SUCCESS) {
1718                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1719                 return;
1720         }
1721 }
1722
1723 /* Remove a MAC address, and update filters */
1724 static void
1725 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1726 {
1727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1728         struct i40e_vsi *vsi;
1729         struct rte_eth_dev_data *data = dev->data;
1730         struct ether_addr *macaddr;
1731         int ret;
1732         uint32_t i;
1733         uint64_t pool_sel;
1734
1735         macaddr = &(data->mac_addrs[index]);
1736
1737         pool_sel = dev->data->mac_pool_sel[index];
1738
1739         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1740                 if (pool_sel & (1ULL << i)) {
1741                         if (i == 0)
1742                                 vsi = pf->main_vsi;
1743                         else {
1744                                 /* No VMDQ pool enabled or configured */
1745                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1746                                         (i > pf->nb_cfg_vmdq_vsi)) {
1747                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1748                                                         "/configured");
1749                                         return;
1750                                 }
1751                                 vsi = pf->vmdq[i - 1].vsi;
1752                         }
1753                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1754
1755                         if (ret) {
1756                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1757                                 return;
1758                         }
1759                 }
1760         }
1761 }
1762
1763 /* Set perfect match or hash match of MAC and VLAN for a VF */
1764 static int
1765 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1766                  struct rte_eth_mac_filter *filter,
1767                  bool add)
1768 {
1769         struct i40e_hw *hw;
1770         struct i40e_mac_filter_info mac_filter;
1771         struct ether_addr old_mac;
1772         struct ether_addr *new_mac;
1773         struct i40e_pf_vf *vf = NULL;
1774         uint16_t vf_id;
1775         int ret;
1776
1777         if (pf == NULL) {
1778                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1779                 return -EINVAL;
1780         }
1781         hw = I40E_PF_TO_HW(pf);
1782
1783         if (filter == NULL) {
1784                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1785                 return -EINVAL;
1786         }
1787
1788         new_mac = &filter->mac_addr;
1789
1790         if (is_zero_ether_addr(new_mac)) {
1791                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1792                 return -EINVAL;
1793         }
1794
1795         vf_id = filter->dst_id;
1796
1797         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1798                 PMD_DRV_LOG(ERR, "Invalid argument.");
1799                 return -EINVAL;
1800         }
1801         vf = &pf->vfs[vf_id];
1802
1803         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1804                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1805                 return -EINVAL;
1806         }
1807
1808         if (add) {
1809                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1810                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1811                                 ETHER_ADDR_LEN);
1812                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1813                                  ETHER_ADDR_LEN);
1814
1815                 mac_filter.filter_type = filter->filter_type;
1816                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1817                 if (ret != I40E_SUCCESS) {
1818                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1819                         return -1;
1820                 }
1821                 ether_addr_copy(new_mac, &pf->dev_addr);
1822         } else {
1823                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1824                                 ETHER_ADDR_LEN);
1825                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1826                 if (ret != I40E_SUCCESS) {
1827                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1828                         return -1;
1829                 }
1830
1831                 /* Clear device address as it has been removed */
1832                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1833                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1834         }
1835
1836         return 0;
1837 }
1838
1839 /* MAC filter handle */
1840 static int
1841 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1842                 void *arg)
1843 {
1844         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1845         struct rte_eth_mac_filter *filter;
1846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1847         int ret = I40E_NOT_SUPPORTED;
1848
1849         filter = (struct rte_eth_mac_filter *)(arg);
1850
1851         switch (filter_op) {
1852         case RTE_ETH_FILTER_NOP:
1853                 ret = I40E_SUCCESS;
1854                 break;
1855         case RTE_ETH_FILTER_ADD:
1856                 i40e_pf_disable_irq0(hw);
1857                 if (filter->is_vf)
1858                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1859                 i40e_pf_enable_irq0(hw);
1860                 break;
1861         case RTE_ETH_FILTER_DELETE:
1862                 i40e_pf_disable_irq0(hw);
1863                 if (filter->is_vf)
1864                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1865                 i40e_pf_enable_irq0(hw);
1866                 break;
1867         default:
1868                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1869                 ret = I40E_ERR_PARAM;
1870                 break;
1871         }
1872
1873         return ret;
1874 }
1875
1876 static int
1877 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1878                          struct rte_eth_rss_reta_entry64 *reta_conf,
1879                          uint16_t reta_size)
1880 {
1881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         uint32_t lut, l;
1884         uint16_t i, j, lut_size = pf->hash_lut_size;
1885         uint16_t idx, shift;
1886         uint8_t mask;
1887
1888         if (reta_size != lut_size ||
1889                 reta_size > ETH_RSS_RETA_SIZE_512) {
1890                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1891                         "(%d) doesn't match the number hardware can supported "
1892                                         "(%d)\n", reta_size, lut_size);
1893                 return -EINVAL;
1894         }
1895
1896         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1897                 idx = i / RTE_RETA_GROUP_SIZE;
1898                 shift = i % RTE_RETA_GROUP_SIZE;
1899                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1900                                                 I40E_4_BIT_MASK);
1901                 if (!mask)
1902                         continue;
1903                 if (mask == I40E_4_BIT_MASK)
1904                         l = 0;
1905                 else
1906                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1907                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1908                         if (mask & (0x1 << j))
1909                                 lut |= reta_conf[idx].reta[shift + j] <<
1910                                                         (CHAR_BIT * j);
1911                         else
1912                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1913                 }
1914                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1915         }
1916
1917         return 0;
1918 }
1919
1920 static int
1921 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1922                         struct rte_eth_rss_reta_entry64 *reta_conf,
1923                         uint16_t reta_size)
1924 {
1925         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         uint32_t lut;
1928         uint16_t i, j, lut_size = pf->hash_lut_size;
1929         uint16_t idx, shift;
1930         uint8_t mask;
1931
1932         if (reta_size != lut_size ||
1933                 reta_size > ETH_RSS_RETA_SIZE_512) {
1934                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1935                         "(%d) doesn't match the number hardware can supported "
1936                                         "(%d)\n", reta_size, lut_size);
1937                 return -EINVAL;
1938         }
1939
1940         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1941                 idx = i / RTE_RETA_GROUP_SIZE;
1942                 shift = i % RTE_RETA_GROUP_SIZE;
1943                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1944                                                 I40E_4_BIT_MASK);
1945                 if (!mask)
1946                         continue;
1947
1948                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1949                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1950                         if (mask & (0x1 << j))
1951                                 reta_conf[idx].reta[shift + j] = ((lut >>
1952                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1953                 }
1954         }
1955
1956         return 0;
1957 }
1958
1959 /**
1960  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1961  * @hw:   pointer to the HW structure
1962  * @mem:  pointer to mem struct to fill out
1963  * @size: size of memory requested
1964  * @alignment: what to align the allocation to
1965  **/
1966 enum i40e_status_code
1967 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1968                         struct i40e_dma_mem *mem,
1969                         u64 size,
1970                         u32 alignment)
1971 {
1972         static uint64_t id = 0;
1973         const struct rte_memzone *mz = NULL;
1974         char z_name[RTE_MEMZONE_NAMESIZE];
1975
1976         if (!mem)
1977                 return I40E_ERR_PARAM;
1978
1979         id++;
1980         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1981 #ifdef RTE_LIBRTE_XEN_DOM0
1982         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1983                                                         RTE_PGSIZE_2M);
1984 #else
1985         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1986 #endif
1987         if (!mz)
1988                 return I40E_ERR_NO_MEMORY;
1989
1990         mem->id = id;
1991         mem->size = size;
1992         mem->va = mz->addr;
1993 #ifdef RTE_LIBRTE_XEN_DOM0
1994         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1995 #else
1996         mem->pa = mz->phys_addr;
1997 #endif
1998
1999         return I40E_SUCCESS;
2000 }
2001
2002 /**
2003  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2004  * @hw:   pointer to the HW structure
2005  * @mem:  ptr to mem struct to free
2006  **/
2007 enum i40e_status_code
2008 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2009                     struct i40e_dma_mem *mem)
2010 {
2011         if (!mem || !mem->va)
2012                 return I40E_ERR_PARAM;
2013
2014         mem->va = NULL;
2015         mem->pa = (u64)0;
2016
2017         return I40E_SUCCESS;
2018 }
2019
2020 /**
2021  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2022  * @hw:   pointer to the HW structure
2023  * @mem:  pointer to mem struct to fill out
2024  * @size: size of memory requested
2025  **/
2026 enum i40e_status_code
2027 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2028                          struct i40e_virt_mem *mem,
2029                          u32 size)
2030 {
2031         if (!mem)
2032                 return I40E_ERR_PARAM;
2033
2034         mem->size = size;
2035         mem->va = rte_zmalloc("i40e", size, 0);
2036
2037         if (mem->va)
2038                 return I40E_SUCCESS;
2039         else
2040                 return I40E_ERR_NO_MEMORY;
2041 }
2042
2043 /**
2044  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2045  * @hw:   pointer to the HW structure
2046  * @mem:  pointer to mem struct to free
2047  **/
2048 enum i40e_status_code
2049 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2050                      struct i40e_virt_mem *mem)
2051 {
2052         if (!mem)
2053                 return I40E_ERR_PARAM;
2054
2055         rte_free(mem->va);
2056         mem->va = NULL;
2057
2058         return I40E_SUCCESS;
2059 }
2060
2061 void
2062 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2063 {
2064         rte_spinlock_init(&sp->spinlock);
2065 }
2066
2067 void
2068 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2069 {
2070         rte_spinlock_lock(&sp->spinlock);
2071 }
2072
2073 void
2074 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2075 {
2076         rte_spinlock_unlock(&sp->spinlock);
2077 }
2078
2079 void
2080 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2081 {
2082         return;
2083 }
2084
2085 /**
2086  * Get the hardware capabilities, which will be parsed
2087  * and saved into struct i40e_hw.
2088  */
2089 static int
2090 i40e_get_cap(struct i40e_hw *hw)
2091 {
2092         struct i40e_aqc_list_capabilities_element_resp *buf;
2093         uint16_t len, size = 0;
2094         int ret;
2095
2096         /* Calculate a huge enough buff for saving response data temporarily */
2097         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2098                                                 I40E_MAX_CAP_ELE_NUM;
2099         buf = rte_zmalloc("i40e", len, 0);
2100         if (!buf) {
2101                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2102                 return I40E_ERR_NO_MEMORY;
2103         }
2104
2105         /* Get, parse the capabilities and save it to hw */
2106         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2107                         i40e_aqc_opc_list_func_capabilities, NULL);
2108         if (ret != I40E_SUCCESS)
2109                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2110
2111         /* Free the temporary buffer after being used */
2112         rte_free(buf);
2113
2114         return ret;
2115 }
2116
2117 static int
2118 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2119 {
2120         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2121         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2122         uint16_t sum_queues = 0, sum_vsis, left_queues;
2123
2124         /* First check if FW support SRIOV */
2125         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2126                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2127                 return -EINVAL;
2128         }
2129
2130         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2131         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2132         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2133         /* Allocate queues for pf */
2134         if (hw->func_caps.rss) {
2135                 pf->flags |= I40E_FLAG_RSS;
2136                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2137                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2138                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2139         } else
2140                 pf->lan_nb_qps = 1;
2141         sum_queues = pf->lan_nb_qps;
2142         /* Default VSI is not counted in */
2143         sum_vsis = 0;
2144         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2145
2146         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2147                 pf->flags |= I40E_FLAG_SRIOV;
2148                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2149                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2150                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2151                                      "max supported %u.",
2152                                      dev->pci_dev->max_vfs,
2153                                      hw->func_caps.num_vfs);
2154                         return -EINVAL;
2155                 }
2156                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2157                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2158                                      "max support %u queues.",
2159                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2160                         return -EINVAL;
2161                 }
2162                 pf->vf_num = dev->pci_dev->max_vfs;
2163                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2164                 sum_vsis   += pf->vf_num;
2165                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2166                              pf->vf_num, pf->vf_nb_qps);
2167         } else
2168                 pf->vf_num = 0;
2169
2170         if (hw->func_caps.vmdq) {
2171                 pf->flags |= I40E_FLAG_VMDQ;
2172                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2173                 pf->max_nb_vmdq_vsi = 1;
2174                 /*
2175                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2176                  * later.
2177                  */
2178                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2179                 sum_vsis += pf->max_nb_vmdq_vsi;
2180         } else {
2181                 pf->vmdq_nb_qps = 0;
2182                 pf->max_nb_vmdq_vsi = 0;
2183         }
2184         pf->nb_cfg_vmdq_vsi = 0;
2185
2186         if (hw->func_caps.fd) {
2187                 pf->flags |= I40E_FLAG_FDIR;
2188                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2189                 /**
2190                  * Each flow director consumes one VSI and one queue,
2191                  * but can't calculate out predictably here.
2192                  */
2193         }
2194
2195         if (sum_vsis > pf->max_num_vsi ||
2196                 sum_queues > hw->func_caps.num_rx_qp) {
2197                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2198                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2199                              pf->max_num_vsi, sum_vsis);
2200                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2201                              hw->func_caps.num_rx_qp, sum_queues);
2202                 return -EINVAL;
2203         }
2204
2205         /* Adjust VMDQ setting to support as many VMs as possible */
2206         if (pf->flags & I40E_FLAG_VMDQ) {
2207                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2208
2209                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2210                                         pf->max_num_vsi - sum_vsis);
2211
2212                 /* Limit the max VMDQ number that rte_ether that can support  */
2213                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2214                                         ETH_64_POOLS - 1);
2215
2216                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2217                                 pf->max_nb_vmdq_vsi);
2218                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2219         }
2220
2221         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2222          * cause */
2223         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2224                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2225                              sum_vsis, hw->func_caps.num_msix_vectors);
2226                 return -EINVAL;
2227         }
2228         return I40E_SUCCESS;
2229 }
2230
2231 static int
2232 i40e_pf_get_switch_config(struct i40e_pf *pf)
2233 {
2234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2235         struct i40e_aqc_get_switch_config_resp *switch_config;
2236         struct i40e_aqc_switch_config_element_resp *element;
2237         uint16_t start_seid = 0, num_reported;
2238         int ret;
2239
2240         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2241                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2242         if (!switch_config) {
2243                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2244                 return -ENOMEM;
2245         }
2246
2247         /* Get the switch configurations */
2248         ret = i40e_aq_get_switch_config(hw, switch_config,
2249                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2250         if (ret != I40E_SUCCESS) {
2251                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2252                 goto fail;
2253         }
2254         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2255         if (num_reported != 1) { /* The number should be 1 */
2256                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2257                 goto fail;
2258         }
2259
2260         /* Parse the switch configuration elements */
2261         element = &(switch_config->element[0]);
2262         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2263                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2264                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2265         } else
2266                 PMD_DRV_LOG(INFO, "Unknown element type");
2267
2268 fail:
2269         rte_free(switch_config);
2270
2271         return ret;
2272 }
2273
2274 static int
2275 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2276                         uint32_t num)
2277 {
2278         struct pool_entry *entry;
2279
2280         if (pool == NULL || num == 0)
2281                 return -EINVAL;
2282
2283         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2284         if (entry == NULL) {
2285                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2286                 return -ENOMEM;
2287         }
2288
2289         /* queue heap initialize */
2290         pool->num_free = num;
2291         pool->num_alloc = 0;
2292         pool->base = base;
2293         LIST_INIT(&pool->alloc_list);
2294         LIST_INIT(&pool->free_list);
2295
2296         /* Initialize element  */
2297         entry->base = 0;
2298         entry->len = num;
2299
2300         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2301         return 0;
2302 }
2303
2304 static void
2305 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2306 {
2307         struct pool_entry *entry;
2308
2309         if (pool == NULL)
2310                 return;
2311
2312         LIST_FOREACH(entry, &pool->alloc_list, next) {
2313                 LIST_REMOVE(entry, next);
2314                 rte_free(entry);
2315         }
2316
2317         LIST_FOREACH(entry, &pool->free_list, next) {
2318                 LIST_REMOVE(entry, next);
2319                 rte_free(entry);
2320         }
2321
2322         pool->num_free = 0;
2323         pool->num_alloc = 0;
2324         pool->base = 0;
2325         LIST_INIT(&pool->alloc_list);
2326         LIST_INIT(&pool->free_list);
2327 }
2328
2329 static int
2330 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2331                        uint32_t base)
2332 {
2333         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2334         uint32_t pool_offset;
2335         int insert;
2336
2337         if (pool == NULL) {
2338                 PMD_DRV_LOG(ERR, "Invalid parameter");
2339                 return -EINVAL;
2340         }
2341
2342         pool_offset = base - pool->base;
2343         /* Lookup in alloc list */
2344         LIST_FOREACH(entry, &pool->alloc_list, next) {
2345                 if (entry->base == pool_offset) {
2346                         valid_entry = entry;
2347                         LIST_REMOVE(entry, next);
2348                         break;
2349                 }
2350         }
2351
2352         /* Not find, return */
2353         if (valid_entry == NULL) {
2354                 PMD_DRV_LOG(ERR, "Failed to find entry");
2355                 return -EINVAL;
2356         }
2357
2358         /**
2359          * Found it, move it to free list  and try to merge.
2360          * In order to make merge easier, always sort it by qbase.
2361          * Find adjacent prev and last entries.
2362          */
2363         prev = next = NULL;
2364         LIST_FOREACH(entry, &pool->free_list, next) {
2365                 if (entry->base > valid_entry->base) {
2366                         next = entry;
2367                         break;
2368                 }
2369                 prev = entry;
2370         }
2371
2372         insert = 0;
2373         /* Try to merge with next one*/
2374         if (next != NULL) {
2375                 /* Merge with next one */
2376                 if (valid_entry->base + valid_entry->len == next->base) {
2377                         next->base = valid_entry->base;
2378                         next->len += valid_entry->len;
2379                         rte_free(valid_entry);
2380                         valid_entry = next;
2381                         insert = 1;
2382                 }
2383         }
2384
2385         if (prev != NULL) {
2386                 /* Merge with previous one */
2387                 if (prev->base + prev->len == valid_entry->base) {
2388                         prev->len += valid_entry->len;
2389                         /* If it merge with next one, remove next node */
2390                         if (insert == 1) {
2391                                 LIST_REMOVE(valid_entry, next);
2392                                 rte_free(valid_entry);
2393                         } else {
2394                                 rte_free(valid_entry);
2395                                 insert = 1;
2396                         }
2397                 }
2398         }
2399
2400         /* Not find any entry to merge, insert */
2401         if (insert == 0) {
2402                 if (prev != NULL)
2403                         LIST_INSERT_AFTER(prev, valid_entry, next);
2404                 else if (next != NULL)
2405                         LIST_INSERT_BEFORE(next, valid_entry, next);
2406                 else /* It's empty list, insert to head */
2407                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2408         }
2409
2410         pool->num_free += valid_entry->len;
2411         pool->num_alloc -= valid_entry->len;
2412
2413         return 0;
2414 }
2415
2416 static int
2417 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2418                        uint16_t num)
2419 {
2420         struct pool_entry *entry, *valid_entry;
2421
2422         if (pool == NULL || num == 0) {
2423                 PMD_DRV_LOG(ERR, "Invalid parameter");
2424                 return -EINVAL;
2425         }
2426
2427         if (pool->num_free < num) {
2428                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2429                             num, pool->num_free);
2430                 return -ENOMEM;
2431         }
2432
2433         valid_entry = NULL;
2434         /* Lookup  in free list and find most fit one */
2435         LIST_FOREACH(entry, &pool->free_list, next) {
2436                 if (entry->len >= num) {
2437                         /* Find best one */
2438                         if (entry->len == num) {
2439                                 valid_entry = entry;
2440                                 break;
2441                         }
2442                         if (valid_entry == NULL || valid_entry->len > entry->len)
2443                                 valid_entry = entry;
2444                 }
2445         }
2446
2447         /* Not find one to satisfy the request, return */
2448         if (valid_entry == NULL) {
2449                 PMD_DRV_LOG(ERR, "No valid entry found");
2450                 return -ENOMEM;
2451         }
2452         /**
2453          * The entry have equal queue number as requested,
2454          * remove it from alloc_list.
2455          */
2456         if (valid_entry->len == num) {
2457                 LIST_REMOVE(valid_entry, next);
2458         } else {
2459                 /**
2460                  * The entry have more numbers than requested,
2461                  * create a new entry for alloc_list and minus its
2462                  * queue base and number in free_list.
2463                  */
2464                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2465                 if (entry == NULL) {
2466                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2467                                     "resource pool");
2468                         return -ENOMEM;
2469                 }
2470                 entry->base = valid_entry->base;
2471                 entry->len = num;
2472                 valid_entry->base += num;
2473                 valid_entry->len -= num;
2474                 valid_entry = entry;
2475         }
2476
2477         /* Insert it into alloc list, not sorted */
2478         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2479
2480         pool->num_free -= valid_entry->len;
2481         pool->num_alloc += valid_entry->len;
2482
2483         return (valid_entry->base + pool->base);
2484 }
2485
2486 /**
2487  * bitmap_is_subset - Check whether src2 is subset of src1
2488  **/
2489 static inline int
2490 bitmap_is_subset(uint8_t src1, uint8_t src2)
2491 {
2492         return !((src1 ^ src2) & src2);
2493 }
2494
2495 static int
2496 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2497 {
2498         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2499
2500         /* If DCB is not supported, only default TC is supported */
2501         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2502                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2503                 return -EINVAL;
2504         }
2505
2506         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2507                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2508                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2509                             enabled_tcmap);
2510                 return -EINVAL;
2511         }
2512         return I40E_SUCCESS;
2513 }
2514
2515 int
2516 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2517                                 struct i40e_vsi_vlan_pvid_info *info)
2518 {
2519         struct i40e_hw *hw;
2520         struct i40e_vsi_context ctxt;
2521         uint8_t vlan_flags = 0;
2522         int ret;
2523
2524         if (vsi == NULL || info == NULL) {
2525                 PMD_DRV_LOG(ERR, "invalid parameters");
2526                 return I40E_ERR_PARAM;
2527         }
2528
2529         if (info->on) {
2530                 vsi->info.pvid = info->config.pvid;
2531                 /**
2532                  * If insert pvid is enabled, only tagged pkts are
2533                  * allowed to be sent out.
2534                  */
2535                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2536                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2537         } else {
2538                 vsi->info.pvid = 0;
2539                 if (info->config.reject.tagged == 0)
2540                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2541
2542                 if (info->config.reject.untagged == 0)
2543                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2544         }
2545         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2546                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2547         vsi->info.port_vlan_flags |= vlan_flags;
2548         vsi->info.valid_sections =
2549                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2550         memset(&ctxt, 0, sizeof(ctxt));
2551         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2552         ctxt.seid = vsi->seid;
2553
2554         hw = I40E_VSI_TO_HW(vsi);
2555         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2556         if (ret != I40E_SUCCESS)
2557                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2558
2559         return ret;
2560 }
2561
2562 static int
2563 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2564 {
2565         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2566         int i, ret;
2567         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2568
2569         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2570         if (ret != I40E_SUCCESS)
2571                 return ret;
2572
2573         if (!vsi->seid) {
2574                 PMD_DRV_LOG(ERR, "seid not valid");
2575                 return -EINVAL;
2576         }
2577
2578         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2579         tc_bw_data.tc_valid_bits = enabled_tcmap;
2580         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2581                 tc_bw_data.tc_bw_credits[i] =
2582                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2583
2584         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2585         if (ret != I40E_SUCCESS) {
2586                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2587                 return ret;
2588         }
2589
2590         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2591                                         sizeof(vsi->info.qs_handle));
2592         return I40E_SUCCESS;
2593 }
2594
2595 static int
2596 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2597                                  struct i40e_aqc_vsi_properties_data *info,
2598                                  uint8_t enabled_tcmap)
2599 {
2600         int ret, total_tc = 0, i;
2601         uint16_t qpnum_per_tc, bsf, qp_idx;
2602
2603         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2604         if (ret != I40E_SUCCESS)
2605                 return ret;
2606
2607         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2608                 if (enabled_tcmap & (1 << i))
2609                         total_tc++;
2610         vsi->enabled_tc = enabled_tcmap;
2611
2612         /* Number of queues per enabled TC */
2613         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2614         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2615         bsf = rte_bsf32(qpnum_per_tc);
2616
2617         /* Adjust the queue number to actual queues that can be applied */
2618         vsi->nb_qps = qpnum_per_tc * total_tc;
2619
2620         /**
2621          * Configure TC and queue mapping parameters, for enabled TC,
2622          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2623          * default queue will serve it.
2624          */
2625         qp_idx = 0;
2626         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2627                 if (vsi->enabled_tc & (1 << i)) {
2628                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2629                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2630                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2631                         qp_idx += qpnum_per_tc;
2632                 } else
2633                         info->tc_mapping[i] = 0;
2634         }
2635
2636         /* Associate queue number with VSI */
2637         if (vsi->type == I40E_VSI_SRIOV) {
2638                 info->mapping_flags |=
2639                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2640                 for (i = 0; i < vsi->nb_qps; i++)
2641                         info->queue_mapping[i] =
2642                                 rte_cpu_to_le_16(vsi->base_queue + i);
2643         } else {
2644                 info->mapping_flags |=
2645                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2646                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2647         }
2648         info->valid_sections =
2649                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2650
2651         return I40E_SUCCESS;
2652 }
2653
2654 static int
2655 i40e_veb_release(struct i40e_veb *veb)
2656 {
2657         struct i40e_vsi *vsi;
2658         struct i40e_hw *hw;
2659
2660         if (veb == NULL || veb->associate_vsi == NULL)
2661                 return -EINVAL;
2662
2663         if (!TAILQ_EMPTY(&veb->head)) {
2664                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2665                 return -EACCES;
2666         }
2667
2668         vsi = veb->associate_vsi;
2669         hw = I40E_VSI_TO_HW(vsi);
2670
2671         vsi->uplink_seid = veb->uplink_seid;
2672         i40e_aq_delete_element(hw, veb->seid, NULL);
2673         rte_free(veb);
2674         vsi->veb = NULL;
2675         return I40E_SUCCESS;
2676 }
2677
2678 /* Setup a veb */
2679 static struct i40e_veb *
2680 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2681 {
2682         struct i40e_veb *veb;
2683         int ret;
2684         struct i40e_hw *hw;
2685
2686         if (NULL == pf || vsi == NULL) {
2687                 PMD_DRV_LOG(ERR, "veb setup failed, "
2688                             "associated VSI shouldn't null");
2689                 return NULL;
2690         }
2691         hw = I40E_PF_TO_HW(pf);
2692
2693         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2694         if (!veb) {
2695                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2696                 goto fail;
2697         }
2698
2699         veb->associate_vsi = vsi;
2700         TAILQ_INIT(&veb->head);
2701         veb->uplink_seid = vsi->uplink_seid;
2702
2703         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2704                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2705
2706         if (ret != I40E_SUCCESS) {
2707                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2708                             hw->aq.asq_last_status);
2709                 goto fail;
2710         }
2711
2712         /* get statistics index */
2713         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2714                                 &veb->stats_idx, NULL, NULL, NULL);
2715         if (ret != I40E_SUCCESS) {
2716                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2717                             hw->aq.asq_last_status);
2718                 goto fail;
2719         }
2720
2721         /* Get VEB bandwidth, to be implemented */
2722         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2723         vsi->uplink_seid = veb->seid;
2724
2725         return veb;
2726 fail:
2727         rte_free(veb);
2728         return NULL;
2729 }
2730
2731 int
2732 i40e_vsi_release(struct i40e_vsi *vsi)
2733 {
2734         struct i40e_pf *pf;
2735         struct i40e_hw *hw;
2736         struct i40e_vsi_list *vsi_list;
2737         int ret;
2738         struct i40e_mac_filter *f;
2739
2740         if (!vsi)
2741                 return I40E_SUCCESS;
2742
2743         pf = I40E_VSI_TO_PF(vsi);
2744         hw = I40E_VSI_TO_HW(vsi);
2745
2746         /* VSI has child to attach, release child first */
2747         if (vsi->veb) {
2748                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2749                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2750                                 return -1;
2751                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2752                 }
2753                 i40e_veb_release(vsi->veb);
2754         }
2755
2756         /* Remove all macvlan filters of the VSI */
2757         i40e_vsi_remove_all_macvlan_filter(vsi);
2758         TAILQ_FOREACH(f, &vsi->mac_list, next)
2759                 rte_free(f);
2760
2761         if (vsi->type != I40E_VSI_MAIN) {
2762                 /* Remove vsi from parent's sibling list */
2763                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2764                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2765                         return I40E_ERR_PARAM;
2766                 }
2767                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2768                                 &vsi->sib_vsi_list, list);
2769
2770                 /* Remove all switch element of the VSI */
2771                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2772                 if (ret != I40E_SUCCESS)
2773                         PMD_DRV_LOG(ERR, "Failed to delete element");
2774         }
2775         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2776
2777         if (vsi->type != I40E_VSI_SRIOV)
2778                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2779         rte_free(vsi);
2780
2781         return I40E_SUCCESS;
2782 }
2783
2784 static int
2785 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2786 {
2787         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2788         struct i40e_aqc_remove_macvlan_element_data def_filter;
2789         struct i40e_mac_filter_info filter;
2790         int ret;
2791
2792         if (vsi->type != I40E_VSI_MAIN)
2793                 return I40E_ERR_CONFIG;
2794         memset(&def_filter, 0, sizeof(def_filter));
2795         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2796                                         ETH_ADDR_LEN);
2797         def_filter.vlan_tag = 0;
2798         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2799                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2800         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2801         if (ret != I40E_SUCCESS) {
2802                 struct i40e_mac_filter *f;
2803                 struct ether_addr *mac;
2804
2805                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2806                             "macvlan filter");
2807                 /* It needs to add the permanent mac into mac list */
2808                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2809                 if (f == NULL) {
2810                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2811                         return I40E_ERR_NO_MEMORY;
2812                 }
2813                 mac = &f->mac_info.mac_addr;
2814                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2815                                 ETH_ADDR_LEN);
2816                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2817                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2818                 vsi->mac_num++;
2819
2820                 return ret;
2821         }
2822         (void)rte_memcpy(&filter.mac_addr,
2823                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2824         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2825         return i40e_vsi_add_mac(vsi, &filter);
2826 }
2827
2828 static int
2829 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2830 {
2831         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2832         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2833         struct i40e_hw *hw = &vsi->adapter->hw;
2834         i40e_status ret;
2835         int i;
2836
2837         memset(&bw_config, 0, sizeof(bw_config));
2838         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2839         if (ret != I40E_SUCCESS) {
2840                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2841                             hw->aq.asq_last_status);
2842                 return ret;
2843         }
2844
2845         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2846         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2847                                         &ets_sla_config, NULL);
2848         if (ret != I40E_SUCCESS) {
2849                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2850                             "configuration %u", hw->aq.asq_last_status);
2851                 return ret;
2852         }
2853
2854         /* Not store the info yet, just print out */
2855         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2856         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2857         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2858                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2859                             ets_sla_config.share_credits[i]);
2860                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2861                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2862                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2863                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2864                             (i * 4));
2865         }
2866
2867         return 0;
2868 }
2869
2870 /* Setup a VSI */
2871 struct i40e_vsi *
2872 i40e_vsi_setup(struct i40e_pf *pf,
2873                enum i40e_vsi_type type,
2874                struct i40e_vsi *uplink_vsi,
2875                uint16_t user_param)
2876 {
2877         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2878         struct i40e_vsi *vsi;
2879         struct i40e_mac_filter_info filter;
2880         int ret;
2881         struct i40e_vsi_context ctxt;
2882         struct ether_addr broadcast =
2883                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2884
2885         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2886                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2887                             "VSI link shouldn't be NULL");
2888                 return NULL;
2889         }
2890
2891         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2892                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2893                             "uplink VSI should be NULL");
2894                 return NULL;
2895         }
2896
2897         /* If uplink vsi didn't setup VEB, create one first */
2898         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2899                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2900
2901                 if (NULL == uplink_vsi->veb) {
2902                         PMD_DRV_LOG(ERR, "VEB setup failed");
2903                         return NULL;
2904                 }
2905         }
2906
2907         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2908         if (!vsi) {
2909                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2910                 return NULL;
2911         }
2912         TAILQ_INIT(&vsi->mac_list);
2913         vsi->type = type;
2914         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2915         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2916         vsi->parent_vsi = uplink_vsi;
2917         vsi->user_param = user_param;
2918         /* Allocate queues */
2919         switch (vsi->type) {
2920         case I40E_VSI_MAIN  :
2921                 vsi->nb_qps = pf->lan_nb_qps;
2922                 break;
2923         case I40E_VSI_SRIOV :
2924                 vsi->nb_qps = pf->vf_nb_qps;
2925                 break;
2926         case I40E_VSI_VMDQ2:
2927                 vsi->nb_qps = pf->vmdq_nb_qps;
2928                 break;
2929         case I40E_VSI_FDIR:
2930                 vsi->nb_qps = pf->fdir_nb_qps;
2931                 break;
2932         default:
2933                 goto fail_mem;
2934         }
2935         /*
2936          * The filter status descriptor is reported in rx queue 0,
2937          * while the tx queue for fdir filter programming has no
2938          * such constraints, can be non-zero queues.
2939          * To simplify it, choose FDIR vsi use queue 0 pair.
2940          * To make sure it will use queue 0 pair, queue allocation
2941          * need be done before this function is called
2942          */
2943         if (type != I40E_VSI_FDIR) {
2944                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2945                         if (ret < 0) {
2946                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2947                                                 vsi->seid, ret);
2948                                 goto fail_mem;
2949                         }
2950                         vsi->base_queue = ret;
2951         } else
2952                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2953
2954         /* VF has MSIX interrupt in VF range, don't allocate here */
2955         if (type != I40E_VSI_SRIOV) {
2956                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2957                 if (ret < 0) {
2958                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2959                         goto fail_queue_alloc;
2960                 }
2961                 vsi->msix_intr = ret;
2962         } else
2963                 vsi->msix_intr = 0;
2964         /* Add VSI */
2965         if (type == I40E_VSI_MAIN) {
2966                 /* For main VSI, no need to add since it's default one */
2967                 vsi->uplink_seid = pf->mac_seid;
2968                 vsi->seid = pf->main_vsi_seid;
2969                 /* Bind queues with specific MSIX interrupt */
2970                 /**
2971                  * Needs 2 interrupt at least, one for misc cause which will
2972                  * enabled from OS side, Another for queues binding the
2973                  * interrupt from device side only.
2974                  */
2975
2976                 /* Get default VSI parameters from hardware */
2977                 memset(&ctxt, 0, sizeof(ctxt));
2978                 ctxt.seid = vsi->seid;
2979                 ctxt.pf_num = hw->pf_id;
2980                 ctxt.uplink_seid = vsi->uplink_seid;
2981                 ctxt.vf_num = 0;
2982                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2983                 if (ret != I40E_SUCCESS) {
2984                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2985                         goto fail_msix_alloc;
2986                 }
2987                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2988                         sizeof(struct i40e_aqc_vsi_properties_data));
2989                 vsi->vsi_id = ctxt.vsi_number;
2990                 vsi->info.valid_sections = 0;
2991
2992                 /* Configure tc, enabled TC0 only */
2993                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2994                         I40E_SUCCESS) {
2995                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2996                         goto fail_msix_alloc;
2997                 }
2998
2999                 /* TC, queue mapping */
3000                 memset(&ctxt, 0, sizeof(ctxt));
3001                 vsi->info.valid_sections |=
3002                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3003                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3004                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3005                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3006                         sizeof(struct i40e_aqc_vsi_properties_data));
3007                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3008                                                 I40E_DEFAULT_TCMAP);
3009                 if (ret != I40E_SUCCESS) {
3010                         PMD_DRV_LOG(ERR, "Failed to configure "
3011                                     "TC queue mapping");
3012                         goto fail_msix_alloc;
3013                 }
3014                 ctxt.seid = vsi->seid;
3015                 ctxt.pf_num = hw->pf_id;
3016                 ctxt.uplink_seid = vsi->uplink_seid;
3017                 ctxt.vf_num = 0;
3018
3019                 /* Update VSI parameters */
3020                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3021                 if (ret != I40E_SUCCESS) {
3022                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3023                         goto fail_msix_alloc;
3024                 }
3025
3026                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3027                                                 sizeof(vsi->info.tc_mapping));
3028                 (void)rte_memcpy(&vsi->info.queue_mapping,
3029                                 &ctxt.info.queue_mapping,
3030                         sizeof(vsi->info.queue_mapping));
3031                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3032                 vsi->info.valid_sections = 0;
3033
3034                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3035                                 ETH_ADDR_LEN);
3036
3037                 /**
3038                  * Updating default filter settings are necessary to prevent
3039                  * reception of tagged packets.
3040                  * Some old firmware configurations load a default macvlan
3041                  * filter which accepts both tagged and untagged packets.
3042                  * The updating is to use a normal filter instead if needed.
3043                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3044                  * The firmware with correct configurations load the default
3045                  * macvlan filter which is expected and cannot be removed.
3046                  */
3047                 i40e_update_default_filter_setting(vsi);
3048         } else if (type == I40E_VSI_SRIOV) {
3049                 memset(&ctxt, 0, sizeof(ctxt));
3050                 /**
3051                  * For other VSI, the uplink_seid equals to uplink VSI's
3052                  * uplink_seid since they share same VEB
3053                  */
3054                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3055                 ctxt.pf_num = hw->pf_id;
3056                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3057                 ctxt.uplink_seid = vsi->uplink_seid;
3058                 ctxt.connection_type = 0x1;
3059                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3060
3061                 /* Configure switch ID */
3062                 ctxt.info.valid_sections |=
3063                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3064                 ctxt.info.switch_id =
3065                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3066                 /* Configure port/vlan */
3067                 ctxt.info.valid_sections |=
3068                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3069                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3070                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3071                                                 I40E_DEFAULT_TCMAP);
3072                 if (ret != I40E_SUCCESS) {
3073                         PMD_DRV_LOG(ERR, "Failed to configure "
3074                                     "TC queue mapping");
3075                         goto fail_msix_alloc;
3076                 }
3077                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3078                 ctxt.info.valid_sections |=
3079                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3080                 /**
3081                  * Since VSI is not created yet, only configure parameter,
3082                  * will add vsi below.
3083                  */
3084         } else if (type == I40E_VSI_VMDQ2) {
3085                 memset(&ctxt, 0, sizeof(ctxt));
3086                 /*
3087                  * For other VSI, the uplink_seid equals to uplink VSI's
3088                  * uplink_seid since they share same VEB
3089                  */
3090                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3091                 ctxt.pf_num = hw->pf_id;
3092                 ctxt.vf_num = 0;
3093                 ctxt.uplink_seid = vsi->uplink_seid;
3094                 ctxt.connection_type = 0x1;
3095                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3096
3097                 ctxt.info.valid_sections |=
3098                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3099                 /* user_param carries flag to enable loop back */
3100                 if (user_param) {
3101                         ctxt.info.switch_id =
3102                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3103                         ctxt.info.switch_id |=
3104                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3105                 }
3106
3107                 /* Configure port/vlan */
3108                 ctxt.info.valid_sections |=
3109                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3110                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3111                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3112                                                 I40E_DEFAULT_TCMAP);
3113                 if (ret != I40E_SUCCESS) {
3114                         PMD_DRV_LOG(ERR, "Failed to configure "
3115                                         "TC queue mapping");
3116                         goto fail_msix_alloc;
3117                 }
3118                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3119                 ctxt.info.valid_sections |=
3120                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3121         } else if (type == I40E_VSI_FDIR) {
3122                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3123                 ctxt.pf_num = hw->pf_id;
3124                 ctxt.vf_num = 0;
3125                 ctxt.uplink_seid = vsi->uplink_seid;
3126                 ctxt.connection_type = 0x1;     /* regular data port */
3127                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3128                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3129                                                 I40E_DEFAULT_TCMAP);
3130                 if (ret != I40E_SUCCESS) {
3131                         PMD_DRV_LOG(ERR, "Failed to configure "
3132                                         "TC queue mapping.");
3133                         goto fail_msix_alloc;
3134                 }
3135                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3136                 ctxt.info.valid_sections |=
3137                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3138         } else {
3139                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3140                 goto fail_msix_alloc;
3141         }
3142
3143         if (vsi->type != I40E_VSI_MAIN) {
3144                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3145                 if (ret) {
3146                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3147                                     hw->aq.asq_last_status);
3148                         goto fail_msix_alloc;
3149                 }
3150                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3151                 vsi->info.valid_sections = 0;
3152                 vsi->seid = ctxt.seid;
3153                 vsi->vsi_id = ctxt.vsi_number;
3154                 vsi->sib_vsi_list.vsi = vsi;
3155                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3156                                 &vsi->sib_vsi_list, list);
3157         }
3158
3159         /* MAC/VLAN configuration */
3160         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3161         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3162
3163         ret = i40e_vsi_add_mac(vsi, &filter);
3164         if (ret != I40E_SUCCESS) {
3165                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3166                 goto fail_msix_alloc;
3167         }
3168
3169         /* Get VSI BW information */
3170         i40e_vsi_dump_bw_config(vsi);
3171         return vsi;
3172 fail_msix_alloc:
3173         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3174 fail_queue_alloc:
3175         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3176 fail_mem:
3177         rte_free(vsi);
3178         return NULL;
3179 }
3180
3181 /* Configure vlan stripping on or off */
3182 int
3183 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3184 {
3185         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3186         struct i40e_vsi_context ctxt;
3187         uint8_t vlan_flags;
3188         int ret = I40E_SUCCESS;
3189
3190         /* Check if it has been already on or off */
3191         if (vsi->info.valid_sections &
3192                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3193                 if (on) {
3194                         if ((vsi->info.port_vlan_flags &
3195                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3196                                 return 0; /* already on */
3197                 } else {
3198                         if ((vsi->info.port_vlan_flags &
3199                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3200                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3201                                 return 0; /* already off */
3202                 }
3203         }
3204
3205         if (on)
3206                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3207         else
3208                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3209         vsi->info.valid_sections =
3210                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3211         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3212         vsi->info.port_vlan_flags |= vlan_flags;
3213         ctxt.seid = vsi->seid;
3214         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3215         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3216         if (ret)
3217                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3218                             on ? "enable" : "disable");
3219
3220         return ret;
3221 }
3222
3223 static int
3224 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3225 {
3226         struct rte_eth_dev_data *data = dev->data;
3227         int ret;
3228
3229         /* Apply vlan offload setting */
3230         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3231
3232         /* Apply double-vlan setting, not implemented yet */
3233
3234         /* Apply pvid setting */
3235         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3236                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3237         if (ret)
3238                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3239
3240         return ret;
3241 }
3242
3243 static int
3244 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3245 {
3246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3247
3248         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3249 }
3250
3251 static int
3252 i40e_update_flow_control(struct i40e_hw *hw)
3253 {
3254 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3255         struct i40e_link_status link_status;
3256         uint32_t rxfc = 0, txfc = 0, reg;
3257         uint8_t an_info;
3258         int ret;
3259
3260         memset(&link_status, 0, sizeof(link_status));
3261         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3262         if (ret != I40E_SUCCESS) {
3263                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3264                 goto write_reg; /* Disable flow control */
3265         }
3266
3267         an_info = hw->phy.link_info.an_info;
3268         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3269                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3270                 ret = I40E_ERR_NOT_READY;
3271                 goto write_reg; /* Disable flow control */
3272         }
3273         /**
3274          * If link auto negotiation is enabled, flow control needs to
3275          * be configured according to it
3276          */
3277         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3278         case I40E_LINK_PAUSE_RXTX:
3279                 rxfc = 1;
3280                 txfc = 1;
3281                 hw->fc.current_mode = I40E_FC_FULL;
3282                 break;
3283         case I40E_AQ_LINK_PAUSE_RX:
3284                 rxfc = 1;
3285                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3286                 break;
3287         case I40E_AQ_LINK_PAUSE_TX:
3288                 txfc = 1;
3289                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3290                 break;
3291         default:
3292                 hw->fc.current_mode = I40E_FC_NONE;
3293                 break;
3294         }
3295
3296 write_reg:
3297         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3298                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3299         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3300         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3301         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3302         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3303
3304         return ret;
3305 }
3306
3307 /* PF setup */
3308 static int
3309 i40e_pf_setup(struct i40e_pf *pf)
3310 {
3311         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3312         struct i40e_filter_control_settings settings;
3313         struct i40e_vsi *vsi;
3314         int ret;
3315
3316         /* Clear all stats counters */
3317         pf->offset_loaded = FALSE;
3318         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3319         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3320
3321         ret = i40e_pf_get_switch_config(pf);
3322         if (ret != I40E_SUCCESS) {
3323                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3324                 return ret;
3325         }
3326         if (pf->flags & I40E_FLAG_FDIR) {
3327                 /* make queue allocated first, let FDIR use queue pair 0*/
3328                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3329                 if (ret != I40E_FDIR_QUEUE_ID) {
3330                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3331                                     " ret =%d", ret);
3332                         pf->flags &= ~I40E_FLAG_FDIR;
3333                 }
3334         }
3335         /*  main VSI setup */
3336         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3337         if (!vsi) {
3338                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3339                 return I40E_ERR_NOT_READY;
3340         }
3341         pf->main_vsi = vsi;
3342
3343         /* Configure filter control */
3344         memset(&settings, 0, sizeof(settings));
3345         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3346                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3347         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3348                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3349         else {
3350                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3351                                                 hw->func_caps.rss_table_size);
3352                 return I40E_ERR_PARAM;
3353         }
3354         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3355                         "size: %u\n", hw->func_caps.rss_table_size);
3356         pf->hash_lut_size = hw->func_caps.rss_table_size;
3357
3358         /* Enable ethtype and macvlan filters */
3359         settings.enable_ethtype = TRUE;
3360         settings.enable_macvlan = TRUE;
3361         ret = i40e_set_filter_control(hw, &settings);
3362         if (ret)
3363                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3364                                                                 ret);
3365
3366         /* Update flow control according to the auto negotiation */
3367         i40e_update_flow_control(hw);
3368
3369         return I40E_SUCCESS;
3370 }
3371
3372 int
3373 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3374 {
3375         uint32_t reg;
3376         uint16_t j;
3377
3378         /**
3379          * Set or clear TX Queue Disable flags,
3380          * which is required by hardware.
3381          */
3382         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3383         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3384
3385         /* Wait until the request is finished */
3386         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3387                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3388                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3389                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3390                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3391                                                         & 0x1))) {
3392                         break;
3393                 }
3394         }
3395         if (on) {
3396                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3397                         return I40E_SUCCESS; /* already on, skip next steps */
3398
3399                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3400                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3401         } else {
3402                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3403                         return I40E_SUCCESS; /* already off, skip next steps */
3404                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3405         }
3406         /* Write the register */
3407         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3408         /* Check the result */
3409         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3410                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3411                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3412                 if (on) {
3413                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3414                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3415                                 break;
3416                 } else {
3417                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3418                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3419                                 break;
3420                 }
3421         }
3422         /* Check if it is timeout */
3423         if (j >= I40E_CHK_Q_ENA_COUNT) {
3424                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3425                             (on ? "enable" : "disable"), q_idx);
3426                 return I40E_ERR_TIMEOUT;
3427         }
3428
3429         return I40E_SUCCESS;
3430 }
3431
3432 /* Swith on or off the tx queues */
3433 static int
3434 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3435 {
3436         struct rte_eth_dev_data *dev_data = pf->dev_data;
3437         struct i40e_tx_queue *txq;
3438         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3439         uint16_t i;
3440         int ret;
3441
3442         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3443                 txq = dev_data->tx_queues[i];
3444                 /* Don't operate the queue if not configured or
3445                  * if starting only per queue */
3446                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3447                         continue;
3448                 if (on)
3449                         ret = i40e_dev_tx_queue_start(dev, i);
3450                 else
3451                         ret = i40e_dev_tx_queue_stop(dev, i);
3452                 if ( ret != I40E_SUCCESS)
3453                         return ret;
3454         }
3455
3456         return I40E_SUCCESS;
3457 }
3458
3459 int
3460 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3461 {
3462         uint32_t reg;
3463         uint16_t j;
3464
3465         /* Wait until the request is finished */
3466         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3467                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3468                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3469                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3470                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3471                         break;
3472         }
3473
3474         if (on) {
3475                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3476                         return I40E_SUCCESS; /* Already on, skip next steps */
3477                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3478         } else {
3479                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3480                         return I40E_SUCCESS; /* Already off, skip next steps */
3481                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3482         }
3483
3484         /* Write the register */
3485         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3486         /* Check the result */
3487         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3488                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3489                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3490                 if (on) {
3491                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3492                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3493                                 break;
3494                 } else {
3495                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3496                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3497                                 break;
3498                 }
3499         }
3500
3501         /* Check if it is timeout */
3502         if (j >= I40E_CHK_Q_ENA_COUNT) {
3503                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3504                             (on ? "enable" : "disable"), q_idx);
3505                 return I40E_ERR_TIMEOUT;
3506         }
3507
3508         return I40E_SUCCESS;
3509 }
3510 /* Switch on or off the rx queues */
3511 static int
3512 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3513 {
3514         struct rte_eth_dev_data *dev_data = pf->dev_data;
3515         struct i40e_rx_queue *rxq;
3516         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3517         uint16_t i;
3518         int ret;
3519
3520         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3521                 rxq = dev_data->rx_queues[i];
3522                 /* Don't operate the queue if not configured or
3523                  * if starting only per queue */
3524                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3525                         continue;
3526                 if (on)
3527                         ret = i40e_dev_rx_queue_start(dev, i);
3528                 else
3529                         ret = i40e_dev_rx_queue_stop(dev, i);
3530                 if (ret != I40E_SUCCESS)
3531                         return ret;
3532         }
3533
3534         return I40E_SUCCESS;
3535 }
3536
3537 /* Switch on or off all the rx/tx queues */
3538 int
3539 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3540 {
3541         int ret;
3542
3543         if (on) {
3544                 /* enable rx queues before enabling tx queues */
3545                 ret = i40e_dev_switch_rx_queues(pf, on);
3546                 if (ret) {
3547                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3548                         return ret;
3549                 }
3550                 ret = i40e_dev_switch_tx_queues(pf, on);
3551         } else {
3552                 /* Stop tx queues before stopping rx queues */
3553                 ret = i40e_dev_switch_tx_queues(pf, on);
3554                 if (ret) {
3555                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3556                         return ret;
3557                 }
3558                 ret = i40e_dev_switch_rx_queues(pf, on);
3559         }
3560
3561         return ret;
3562 }
3563
3564 /* Initialize VSI for TX */
3565 static int
3566 i40e_dev_tx_init(struct i40e_pf *pf)
3567 {
3568         struct rte_eth_dev_data *data = pf->dev_data;
3569         uint16_t i;
3570         uint32_t ret = I40E_SUCCESS;
3571         struct i40e_tx_queue *txq;
3572
3573         for (i = 0; i < data->nb_tx_queues; i++) {
3574                 txq = data->tx_queues[i];
3575                 if (!txq || !txq->q_set)
3576                         continue;
3577                 ret = i40e_tx_queue_init(txq);
3578                 if (ret != I40E_SUCCESS)
3579                         break;
3580         }
3581
3582         return ret;
3583 }
3584
3585 /* Initialize VSI for RX */
3586 static int
3587 i40e_dev_rx_init(struct i40e_pf *pf)
3588 {
3589         struct rte_eth_dev_data *data = pf->dev_data;
3590         int ret = I40E_SUCCESS;
3591         uint16_t i;
3592         struct i40e_rx_queue *rxq;
3593
3594         i40e_pf_config_mq_rx(pf);
3595         for (i = 0; i < data->nb_rx_queues; i++) {
3596                 rxq = data->rx_queues[i];
3597                 if (!rxq || !rxq->q_set)
3598                         continue;
3599
3600                 ret = i40e_rx_queue_init(rxq);
3601                 if (ret != I40E_SUCCESS) {
3602                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3603                                     "initialization");
3604                         break;
3605                 }
3606         }
3607
3608         return ret;
3609 }
3610
3611 static int
3612 i40e_dev_rxtx_init(struct i40e_pf *pf)
3613 {
3614         int err;
3615
3616         err = i40e_dev_tx_init(pf);
3617         if (err) {
3618                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3619                 return err;
3620         }
3621         err = i40e_dev_rx_init(pf);
3622         if (err) {
3623                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3624                 return err;
3625         }
3626
3627         return err;
3628 }
3629
3630 static int
3631 i40e_vmdq_setup(struct rte_eth_dev *dev)
3632 {
3633         struct rte_eth_conf *conf = &dev->data->dev_conf;
3634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3635         int i, err, conf_vsis, j, loop;
3636         struct i40e_vsi *vsi;
3637         struct i40e_vmdq_info *vmdq_info;
3638         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3639         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3640
3641         /*
3642          * Disable interrupt to avoid message from VF. Furthermore, it will
3643          * avoid race condition in VSI creation/destroy.
3644          */
3645         i40e_pf_disable_irq0(hw);
3646
3647         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3648                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3649                 return -ENOTSUP;
3650         }
3651
3652         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3653         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3654                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3655                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3656                         pf->max_nb_vmdq_vsi);
3657                 return -ENOTSUP;
3658         }
3659
3660         if (pf->vmdq != NULL) {
3661                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3662                 return 0;
3663         }
3664
3665         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3666                                 sizeof(*vmdq_info) * conf_vsis, 0);
3667
3668         if (pf->vmdq == NULL) {
3669                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3670                 return -ENOMEM;
3671         }
3672
3673         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3674
3675         /* Create VMDQ VSI */
3676         for (i = 0; i < conf_vsis; i++) {
3677                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3678                                 vmdq_conf->enable_loop_back);
3679                 if (vsi == NULL) {
3680                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3681                         err = -1;
3682                         goto err_vsi_setup;
3683                 }
3684                 vmdq_info = &pf->vmdq[i];
3685                 vmdq_info->pf = pf;
3686                 vmdq_info->vsi = vsi;
3687         }
3688         pf->nb_cfg_vmdq_vsi = conf_vsis;
3689
3690         /* Configure Vlan */
3691         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3692         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3693                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3694                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3695                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3696                                         vmdq_conf->pool_map[i].vlan_id, j);
3697
3698                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3699                                                 vmdq_conf->pool_map[i].vlan_id);
3700                                 if (err) {
3701                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3702                                         err = -1;
3703                                         goto err_vsi_setup;
3704                                 }
3705                         }
3706                 }
3707         }
3708
3709         i40e_pf_enable_irq0(hw);
3710
3711         return 0;
3712
3713 err_vsi_setup:
3714         for (i = 0; i < conf_vsis; i++)
3715                 if (pf->vmdq[i].vsi == NULL)
3716                         break;
3717                 else
3718                         i40e_vsi_release(pf->vmdq[i].vsi);
3719
3720         rte_free(pf->vmdq);
3721         pf->vmdq = NULL;
3722         i40e_pf_enable_irq0(hw);
3723         return err;
3724 }
3725
3726 static void
3727 i40e_stat_update_32(struct i40e_hw *hw,
3728                    uint32_t reg,
3729                    bool offset_loaded,
3730                    uint64_t *offset,
3731                    uint64_t *stat)
3732 {
3733         uint64_t new_data;
3734
3735         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3736         if (!offset_loaded)
3737                 *offset = new_data;
3738
3739         if (new_data >= *offset)
3740                 *stat = (uint64_t)(new_data - *offset);
3741         else
3742                 *stat = (uint64_t)((new_data +
3743                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3744 }
3745
3746 static void
3747 i40e_stat_update_48(struct i40e_hw *hw,
3748                    uint32_t hireg,
3749                    uint32_t loreg,
3750                    bool offset_loaded,
3751                    uint64_t *offset,
3752                    uint64_t *stat)
3753 {
3754         uint64_t new_data;
3755
3756         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3757         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3758                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3759
3760         if (!offset_loaded)
3761                 *offset = new_data;
3762
3763         if (new_data >= *offset)
3764                 *stat = new_data - *offset;
3765         else
3766                 *stat = (uint64_t)((new_data +
3767                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3768
3769         *stat &= I40E_48_BIT_MASK;
3770 }
3771
3772 /* Disable IRQ0 */
3773 void
3774 i40e_pf_disable_irq0(struct i40e_hw *hw)
3775 {
3776         /* Disable all interrupt types */
3777         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3778         I40E_WRITE_FLUSH(hw);
3779 }
3780
3781 /* Enable IRQ0 */
3782 void
3783 i40e_pf_enable_irq0(struct i40e_hw *hw)
3784 {
3785         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3786                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3787                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3788                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3789         I40E_WRITE_FLUSH(hw);
3790 }
3791
3792 static void
3793 i40e_pf_config_irq0(struct i40e_hw *hw)
3794 {
3795         /* read pending request and disable first */
3796         i40e_pf_disable_irq0(hw);
3797         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3798         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3799                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3800
3801         /* Link no queues with irq0 */
3802         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3803                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3804 }
3805
3806 static void
3807 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3808 {
3809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3811         int i;
3812         uint16_t abs_vf_id;
3813         uint32_t index, offset, val;
3814
3815         if (!pf->vfs)
3816                 return;
3817         /**
3818          * Try to find which VF trigger a reset, use absolute VF id to access
3819          * since the reg is global register.
3820          */
3821         for (i = 0; i < pf->vf_num; i++) {
3822                 abs_vf_id = hw->func_caps.vf_base_id + i;
3823                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3824                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3825                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3826                 /* VFR event occured */
3827                 if (val & (0x1 << offset)) {
3828                         int ret;
3829
3830                         /* Clear the event first */
3831                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3832                                                         (0x1 << offset));
3833                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3834                         /**
3835                          * Only notify a VF reset event occured,
3836                          * don't trigger another SW reset
3837                          */
3838                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3839                         if (ret != I40E_SUCCESS)
3840                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3841                 }
3842         }
3843 }
3844
3845 static void
3846 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3847 {
3848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         struct i40e_arq_event_info info;
3850         uint16_t pending, opcode;
3851         int ret;
3852
3853         info.buf_len = I40E_AQ_BUF_SZ;
3854         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3855         if (!info.msg_buf) {
3856                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3857                 return;
3858         }
3859
3860         pending = 1;
3861         while (pending) {
3862                 ret = i40e_clean_arq_element(hw, &info, &pending);
3863
3864                 if (ret != I40E_SUCCESS) {
3865                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3866                                     "aq_err: %u", hw->aq.asq_last_status);
3867                         break;
3868                 }
3869                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3870
3871                 switch (opcode) {
3872                 case i40e_aqc_opc_send_msg_to_pf:
3873                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3874                         i40e_pf_host_handle_vf_msg(dev,
3875                                         rte_le_to_cpu_16(info.desc.retval),
3876                                         rte_le_to_cpu_32(info.desc.cookie_high),
3877                                         rte_le_to_cpu_32(info.desc.cookie_low),
3878                                         info.msg_buf,
3879                                         info.msg_len);
3880                         break;
3881                 default:
3882                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3883                                     opcode);
3884                         break;
3885                 }
3886         }
3887         rte_free(info.msg_buf);
3888 }
3889
3890 /*
3891  * Interrupt handler is registered as the alarm callback for handling LSC
3892  * interrupt in a definite of time, in order to wait the NIC into a stable
3893  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3894  * no need for link down interrupt.
3895  */
3896 static void
3897 i40e_dev_interrupt_delayed_handler(void *param)
3898 {
3899         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3901         uint32_t icr0;
3902
3903         /* read interrupt causes again */
3904         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3905
3906 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3907         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3908                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3909         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3910                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3911         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3912                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3913         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3914                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3915         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3916                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3917                                                                 "state\n");
3918         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3919                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3920         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3921                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3922 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3923
3924         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3925                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3926                 i40e_dev_handle_vfr_event(dev);
3927         }
3928         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3929                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3930                 i40e_dev_handle_aq_msg(dev);
3931         }
3932
3933         /* handle the link up interrupt in an alarm callback */
3934         i40e_dev_link_update(dev, 0);
3935         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3936
3937         i40e_pf_enable_irq0(hw);
3938         rte_intr_enable(&(dev->pci_dev->intr_handle));
3939 }
3940
3941 /**
3942  * Interrupt handler triggered by NIC  for handling
3943  * specific interrupt.
3944  *
3945  * @param handle
3946  *  Pointer to interrupt handle.
3947  * @param param
3948  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3949  *
3950  * @return
3951  *  void
3952  */
3953 static void
3954 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3955                            void *param)
3956 {
3957         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959         uint32_t icr0;
3960
3961         /* Disable interrupt */
3962         i40e_pf_disable_irq0(hw);
3963
3964         /* read out interrupt causes */
3965         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3966
3967         /* No interrupt event indicated */
3968         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3969                 PMD_DRV_LOG(INFO, "No interrupt event");
3970                 goto done;
3971         }
3972 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3973         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3974                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3975         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3976                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3977         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3978                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3979         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3980                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3981         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3982                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3983         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3984                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3985         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3986                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3987 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3988
3989         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3990                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3991                 i40e_dev_handle_vfr_event(dev);
3992         }
3993         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3994                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3995                 i40e_dev_handle_aq_msg(dev);
3996         }
3997
3998         /* Link Status Change interrupt */
3999         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4000 #define I40E_US_PER_SECOND 1000000
4001                 struct rte_eth_link link;
4002
4003                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4004                 memset(&link, 0, sizeof(link));
4005                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4006                 i40e_dev_link_update(dev, 0);
4007
4008                 /*
4009                  * For link up interrupt, it needs to wait 1 second to let the
4010                  * hardware be a stable state. Otherwise several consecutive
4011                  * interrupts can be observed.
4012                  * For link down interrupt, no need to wait.
4013                  */
4014                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4015                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4016                         return;
4017                 else
4018                         _rte_eth_dev_callback_process(dev,
4019                                 RTE_ETH_EVENT_INTR_LSC);
4020         }
4021
4022 done:
4023         /* Enable interrupt */
4024         i40e_pf_enable_irq0(hw);
4025         rte_intr_enable(&(dev->pci_dev->intr_handle));
4026 }
4027
4028 static int
4029 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4030                          struct i40e_macvlan_filter *filter,
4031                          int total)
4032 {
4033         int ele_num, ele_buff_size;
4034         int num, actual_num, i;
4035         uint16_t flags;
4036         int ret = I40E_SUCCESS;
4037         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4038         struct i40e_aqc_add_macvlan_element_data *req_list;
4039
4040         if (filter == NULL  || total == 0)
4041                 return I40E_ERR_PARAM;
4042         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4043         ele_buff_size = hw->aq.asq_buf_size;
4044
4045         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4046         if (req_list == NULL) {
4047                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4048                 return I40E_ERR_NO_MEMORY;
4049         }
4050
4051         num = 0;
4052         do {
4053                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4054                 memset(req_list, 0, ele_buff_size);
4055
4056                 for (i = 0; i < actual_num; i++) {
4057                         (void)rte_memcpy(req_list[i].mac_addr,
4058                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4059                         req_list[i].vlan_tag =
4060                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4061
4062                         switch (filter[num + i].filter_type) {
4063                         case RTE_MAC_PERFECT_MATCH:
4064                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4065                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4066                                 break;
4067                         case RTE_MACVLAN_PERFECT_MATCH:
4068                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4069                                 break;
4070                         case RTE_MAC_HASH_MATCH:
4071                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4072                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4073                                 break;
4074                         case RTE_MACVLAN_HASH_MATCH:
4075                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4076                                 break;
4077                         default:
4078                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4079                                 ret = I40E_ERR_PARAM;
4080                                 goto DONE;
4081                         }
4082
4083                         req_list[i].queue_number = 0;
4084
4085                         req_list[i].flags = rte_cpu_to_le_16(flags);
4086                 }
4087
4088                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4089                                                 actual_num, NULL);
4090                 if (ret != I40E_SUCCESS) {
4091                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4092                         goto DONE;
4093                 }
4094                 num += actual_num;
4095         } while (num < total);
4096
4097 DONE:
4098         rte_free(req_list);
4099         return ret;
4100 }
4101
4102 static int
4103 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4104                             struct i40e_macvlan_filter *filter,
4105                             int total)
4106 {
4107         int ele_num, ele_buff_size;
4108         int num, actual_num, i;
4109         uint16_t flags;
4110         int ret = I40E_SUCCESS;
4111         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4112         struct i40e_aqc_remove_macvlan_element_data *req_list;
4113
4114         if (filter == NULL  || total == 0)
4115                 return I40E_ERR_PARAM;
4116
4117         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4118         ele_buff_size = hw->aq.asq_buf_size;
4119
4120         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4121         if (req_list == NULL) {
4122                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4123                 return I40E_ERR_NO_MEMORY;
4124         }
4125
4126         num = 0;
4127         do {
4128                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4129                 memset(req_list, 0, ele_buff_size);
4130
4131                 for (i = 0; i < actual_num; i++) {
4132                         (void)rte_memcpy(req_list[i].mac_addr,
4133                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4134                         req_list[i].vlan_tag =
4135                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4136
4137                         switch (filter[num + i].filter_type) {
4138                         case RTE_MAC_PERFECT_MATCH:
4139                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4140                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4141                                 break;
4142                         case RTE_MACVLAN_PERFECT_MATCH:
4143                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4144                                 break;
4145                         case RTE_MAC_HASH_MATCH:
4146                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4147                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4148                                 break;
4149                         case RTE_MACVLAN_HASH_MATCH:
4150                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4151                                 break;
4152                         default:
4153                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4154                                 ret = I40E_ERR_PARAM;
4155                                 goto DONE;
4156                         }
4157                         req_list[i].flags = rte_cpu_to_le_16(flags);
4158                 }
4159
4160                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4161                                                 actual_num, NULL);
4162                 if (ret != I40E_SUCCESS) {
4163                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4164                         goto DONE;
4165                 }
4166                 num += actual_num;
4167         } while (num < total);
4168
4169 DONE:
4170         rte_free(req_list);
4171         return ret;
4172 }
4173
4174 /* Find out specific MAC filter */
4175 static struct i40e_mac_filter *
4176 i40e_find_mac_filter(struct i40e_vsi *vsi,
4177                          struct ether_addr *macaddr)
4178 {
4179         struct i40e_mac_filter *f;
4180
4181         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4182                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4183                         return f;
4184         }
4185
4186         return NULL;
4187 }
4188
4189 static bool
4190 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4191                          uint16_t vlan_id)
4192 {
4193         uint32_t vid_idx, vid_bit;
4194
4195         if (vlan_id > ETH_VLAN_ID_MAX)
4196                 return 0;
4197
4198         vid_idx = I40E_VFTA_IDX(vlan_id);
4199         vid_bit = I40E_VFTA_BIT(vlan_id);
4200
4201         if (vsi->vfta[vid_idx] & vid_bit)
4202                 return 1;
4203         else
4204                 return 0;
4205 }
4206
4207 static void
4208 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4209                          uint16_t vlan_id, bool on)
4210 {
4211         uint32_t vid_idx, vid_bit;
4212
4213         if (vlan_id > ETH_VLAN_ID_MAX)
4214                 return;
4215
4216         vid_idx = I40E_VFTA_IDX(vlan_id);
4217         vid_bit = I40E_VFTA_BIT(vlan_id);
4218
4219         if (on)
4220                 vsi->vfta[vid_idx] |= vid_bit;
4221         else
4222                 vsi->vfta[vid_idx] &= ~vid_bit;
4223 }
4224
4225 /**
4226  * Find all vlan options for specific mac addr,
4227  * return with actual vlan found.
4228  */
4229 static inline int
4230 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4231                            struct i40e_macvlan_filter *mv_f,
4232                            int num, struct ether_addr *addr)
4233 {
4234         int i;
4235         uint32_t j, k;
4236
4237         /**
4238          * Not to use i40e_find_vlan_filter to decrease the loop time,
4239          * although the code looks complex.
4240           */
4241         if (num < vsi->vlan_num)
4242                 return I40E_ERR_PARAM;
4243
4244         i = 0;
4245         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4246                 if (vsi->vfta[j]) {
4247                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4248                                 if (vsi->vfta[j] & (1 << k)) {
4249                                         if (i > num - 1) {
4250                                                 PMD_DRV_LOG(ERR, "vlan number "
4251                                                             "not match");
4252                                                 return I40E_ERR_PARAM;
4253                                         }
4254                                         (void)rte_memcpy(&mv_f[i].macaddr,
4255                                                         addr, ETH_ADDR_LEN);
4256                                         mv_f[i].vlan_id =
4257                                                 j * I40E_UINT32_BIT_SIZE + k;
4258                                         i++;
4259                                 }
4260                         }
4261                 }
4262         }
4263         return I40E_SUCCESS;
4264 }
4265
4266 static inline int
4267 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4268                            struct i40e_macvlan_filter *mv_f,
4269                            int num,
4270                            uint16_t vlan)
4271 {
4272         int i = 0;
4273         struct i40e_mac_filter *f;
4274
4275         if (num < vsi->mac_num)
4276                 return I40E_ERR_PARAM;
4277
4278         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4279                 if (i > num - 1) {
4280                         PMD_DRV_LOG(ERR, "buffer number not match");
4281                         return I40E_ERR_PARAM;
4282                 }
4283                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4284                                 ETH_ADDR_LEN);
4285                 mv_f[i].vlan_id = vlan;
4286                 mv_f[i].filter_type = f->mac_info.filter_type;
4287                 i++;
4288         }
4289
4290         return I40E_SUCCESS;
4291 }
4292
4293 static int
4294 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4295 {
4296         int i, num;
4297         struct i40e_mac_filter *f;
4298         struct i40e_macvlan_filter *mv_f;
4299         int ret = I40E_SUCCESS;
4300
4301         if (vsi == NULL || vsi->mac_num == 0)
4302                 return I40E_ERR_PARAM;
4303
4304         /* Case that no vlan is set */
4305         if (vsi->vlan_num == 0)
4306                 num = vsi->mac_num;
4307         else
4308                 num = vsi->mac_num * vsi->vlan_num;
4309
4310         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4311         if (mv_f == NULL) {
4312                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4313                 return I40E_ERR_NO_MEMORY;
4314         }
4315
4316         i = 0;
4317         if (vsi->vlan_num == 0) {
4318                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4319                         (void)rte_memcpy(&mv_f[i].macaddr,
4320                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4321                         mv_f[i].vlan_id = 0;
4322                         i++;
4323                 }
4324         } else {
4325                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4326                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4327                                         vsi->vlan_num, &f->mac_info.mac_addr);
4328                         if (ret != I40E_SUCCESS)
4329                                 goto DONE;
4330                         i += vsi->vlan_num;
4331                 }
4332         }
4333
4334         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4335 DONE:
4336         rte_free(mv_f);
4337
4338         return ret;
4339 }
4340
4341 int
4342 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4343 {
4344         struct i40e_macvlan_filter *mv_f;
4345         int mac_num;
4346         int ret = I40E_SUCCESS;
4347
4348         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4349                 return I40E_ERR_PARAM;
4350
4351         /* If it's already set, just return */
4352         if (i40e_find_vlan_filter(vsi,vlan))
4353                 return I40E_SUCCESS;
4354
4355         mac_num = vsi->mac_num;
4356
4357         if (mac_num == 0) {
4358                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4359                 return I40E_ERR_PARAM;
4360         }
4361
4362         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4363
4364         if (mv_f == NULL) {
4365                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4366                 return I40E_ERR_NO_MEMORY;
4367         }
4368
4369         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4370
4371         if (ret != I40E_SUCCESS)
4372                 goto DONE;
4373
4374         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4375
4376         if (ret != I40E_SUCCESS)
4377                 goto DONE;
4378
4379         i40e_set_vlan_filter(vsi, vlan, 1);
4380
4381         vsi->vlan_num++;
4382         ret = I40E_SUCCESS;
4383 DONE:
4384         rte_free(mv_f);
4385         return ret;
4386 }
4387
4388 int
4389 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4390 {
4391         struct i40e_macvlan_filter *mv_f;
4392         int mac_num;
4393         int ret = I40E_SUCCESS;
4394
4395         /**
4396          * Vlan 0 is the generic filter for untagged packets
4397          * and can't be removed.
4398          */
4399         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4400                 return I40E_ERR_PARAM;
4401
4402         /* If can't find it, just return */
4403         if (!i40e_find_vlan_filter(vsi, vlan))
4404                 return I40E_ERR_PARAM;
4405
4406         mac_num = vsi->mac_num;
4407
4408         if (mac_num == 0) {
4409                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4410                 return I40E_ERR_PARAM;
4411         }
4412
4413         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4414
4415         if (mv_f == NULL) {
4416                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4417                 return I40E_ERR_NO_MEMORY;
4418         }
4419
4420         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4421
4422         if (ret != I40E_SUCCESS)
4423                 goto DONE;
4424
4425         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4426
4427         if (ret != I40E_SUCCESS)
4428                 goto DONE;
4429
4430         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4431         if (vsi->vlan_num == 1) {
4432                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4433                 if (ret != I40E_SUCCESS)
4434                         goto DONE;
4435
4436                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4437                 if (ret != I40E_SUCCESS)
4438                         goto DONE;
4439         }
4440
4441         i40e_set_vlan_filter(vsi, vlan, 0);
4442
4443         vsi->vlan_num--;
4444         ret = I40E_SUCCESS;
4445 DONE:
4446         rte_free(mv_f);
4447         return ret;
4448 }
4449
4450 int
4451 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4452 {
4453         struct i40e_mac_filter *f;
4454         struct i40e_macvlan_filter *mv_f;
4455         int i, vlan_num = 0;
4456         int ret = I40E_SUCCESS;
4457
4458         /* If it's add and we've config it, return */
4459         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4460         if (f != NULL)
4461                 return I40E_SUCCESS;
4462         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4463                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4464
4465                 /**
4466                  * If vlan_num is 0, that's the first time to add mac,
4467                  * set mask for vlan_id 0.
4468                  */
4469                 if (vsi->vlan_num == 0) {
4470                         i40e_set_vlan_filter(vsi, 0, 1);
4471                         vsi->vlan_num = 1;
4472                 }
4473                 vlan_num = vsi->vlan_num;
4474         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4475                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4476                 vlan_num = 1;
4477
4478         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4479         if (mv_f == NULL) {
4480                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4481                 return I40E_ERR_NO_MEMORY;
4482         }
4483
4484         for (i = 0; i < vlan_num; i++) {
4485                 mv_f[i].filter_type = mac_filter->filter_type;
4486                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4487                                 ETH_ADDR_LEN);
4488         }
4489
4490         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4491                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4492                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4493                                         &mac_filter->mac_addr);
4494                 if (ret != I40E_SUCCESS)
4495                         goto DONE;
4496         }
4497
4498         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4499         if (ret != I40E_SUCCESS)
4500                 goto DONE;
4501
4502         /* Add the mac addr into mac list */
4503         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4504         if (f == NULL) {
4505                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4506                 ret = I40E_ERR_NO_MEMORY;
4507                 goto DONE;
4508         }
4509         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4510                         ETH_ADDR_LEN);
4511         f->mac_info.filter_type = mac_filter->filter_type;
4512         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4513         vsi->mac_num++;
4514
4515         ret = I40E_SUCCESS;
4516 DONE:
4517         rte_free(mv_f);
4518
4519         return ret;
4520 }
4521
4522 int
4523 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4524 {
4525         struct i40e_mac_filter *f;
4526         struct i40e_macvlan_filter *mv_f;
4527         int i, vlan_num;
4528         enum rte_mac_filter_type filter_type;
4529         int ret = I40E_SUCCESS;
4530
4531         /* Can't find it, return an error */
4532         f = i40e_find_mac_filter(vsi, addr);
4533         if (f == NULL)
4534                 return I40E_ERR_PARAM;
4535
4536         vlan_num = vsi->vlan_num;
4537         filter_type = f->mac_info.filter_type;
4538         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4539                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4540                 if (vlan_num == 0) {
4541                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4542                         return I40E_ERR_PARAM;
4543                 }
4544         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4545                         filter_type == RTE_MAC_HASH_MATCH)
4546                 vlan_num = 1;
4547
4548         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4549         if (mv_f == NULL) {
4550                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4551                 return I40E_ERR_NO_MEMORY;
4552         }
4553
4554         for (i = 0; i < vlan_num; i++) {
4555                 mv_f[i].filter_type = filter_type;
4556                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4557                                 ETH_ADDR_LEN);
4558         }
4559         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4560                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4561                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4562                 if (ret != I40E_SUCCESS)
4563                         goto DONE;
4564         }
4565
4566         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4567         if (ret != I40E_SUCCESS)
4568                 goto DONE;
4569
4570         /* Remove the mac addr into mac list */
4571         TAILQ_REMOVE(&vsi->mac_list, f, next);
4572         rte_free(f);
4573         vsi->mac_num--;
4574
4575         ret = I40E_SUCCESS;
4576 DONE:
4577         rte_free(mv_f);
4578         return ret;
4579 }
4580
4581 /* Configure hash enable flags for RSS */
4582 uint64_t
4583 i40e_config_hena(uint64_t flags)
4584 {
4585         uint64_t hena = 0;
4586
4587         if (!flags)
4588                 return hena;
4589
4590         if (flags & ETH_RSS_NONF_IPV4_UDP)
4591                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4592         if (flags & ETH_RSS_NONF_IPV4_TCP)
4593                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4594         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4595                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4596         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4597                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4598         if (flags & ETH_RSS_FRAG_IPV4)
4599                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4600         if (flags & ETH_RSS_NONF_IPV6_UDP)
4601                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4602         if (flags & ETH_RSS_NONF_IPV6_TCP)
4603                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4604         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4605                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4606         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4607                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4608         if (flags & ETH_RSS_FRAG_IPV6)
4609                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4610         if (flags & ETH_RSS_L2_PAYLOAD)
4611                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4612
4613         return hena;
4614 }
4615
4616 /* Parse the hash enable flags */
4617 uint64_t
4618 i40e_parse_hena(uint64_t flags)
4619 {
4620         uint64_t rss_hf = 0;
4621
4622         if (!flags)
4623                 return rss_hf;
4624
4625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4626                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4628                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4630                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4631         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4632                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4633         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4634                 rss_hf |= ETH_RSS_FRAG_IPV4;
4635         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4636                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4637         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4638                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4639         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4640                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4641         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4642                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4643         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4644                 rss_hf |= ETH_RSS_FRAG_IPV6;
4645         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4646                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4647
4648         return rss_hf;
4649 }
4650
4651 /* Disable RSS */
4652 static void
4653 i40e_pf_disable_rss(struct i40e_pf *pf)
4654 {
4655         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4656         uint64_t hena;
4657
4658         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4659         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4660         hena &= ~I40E_RSS_HENA_ALL;
4661         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4662         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4663         I40E_WRITE_FLUSH(hw);
4664 }
4665
4666 static int
4667 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4668 {
4669         uint32_t *hash_key;
4670         uint8_t hash_key_len;
4671         uint64_t rss_hf;
4672         uint16_t i;
4673         uint64_t hena;
4674
4675         hash_key = (uint32_t *)(rss_conf->rss_key);
4676         hash_key_len = rss_conf->rss_key_len;
4677         if (hash_key != NULL && hash_key_len >=
4678                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4679                 /* Fill in RSS hash key */
4680                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4681                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4682         }
4683
4684         rss_hf = rss_conf->rss_hf;
4685         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4686         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4687         hena &= ~I40E_RSS_HENA_ALL;
4688         hena |= i40e_config_hena(rss_hf);
4689         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4690         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4691         I40E_WRITE_FLUSH(hw);
4692
4693         return 0;
4694 }
4695
4696 static int
4697 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4698                          struct rte_eth_rss_conf *rss_conf)
4699 {
4700         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4702         uint64_t hena;
4703
4704         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4705         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4706         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4707                 if (rss_hf != 0) /* Enable RSS */
4708                         return -EINVAL;
4709                 return 0; /* Nothing to do */
4710         }
4711         /* RSS enabled */
4712         if (rss_hf == 0) /* Disable RSS */
4713                 return -EINVAL;
4714
4715         return i40e_hw_rss_hash_set(hw, rss_conf);
4716 }
4717
4718 static int
4719 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4720                            struct rte_eth_rss_conf *rss_conf)
4721 {
4722         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4724         uint64_t hena;
4725         uint16_t i;
4726
4727         if (hash_key != NULL) {
4728                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4729                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4730                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4731         }
4732         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4733         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4734         rss_conf->rss_hf = i40e_parse_hena(hena);
4735
4736         return 0;
4737 }
4738
4739 static int
4740 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4741 {
4742         switch (filter_type) {
4743         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4744                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4745                 break;
4746         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4747                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4748                 break;
4749         case RTE_TUNNEL_FILTER_IMAC_TENID:
4750                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4751                 break;
4752         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4753                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4754                 break;
4755         case ETH_TUNNEL_FILTER_IMAC:
4756                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4757                 break;
4758         default:
4759                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4760                 return -EINVAL;
4761         }
4762
4763         return 0;
4764 }
4765
4766 static int
4767 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4768                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4769                         uint8_t add)
4770 {
4771         uint16_t ip_type;
4772         uint8_t tun_type = 0;
4773         int val, ret = 0;
4774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4775         struct i40e_vsi *vsi = pf->main_vsi;
4776         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4777         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4778
4779         cld_filter = rte_zmalloc("tunnel_filter",
4780                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4781                 0);
4782
4783         if (NULL == cld_filter) {
4784                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4785                 return -EINVAL;
4786         }
4787         pfilter = cld_filter;
4788
4789         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4790                         sizeof(struct ether_addr));
4791         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4792                         sizeof(struct ether_addr));
4793
4794         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4795         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4796                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4797                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4798                                 &tunnel_filter->ip_addr,
4799                                 sizeof(pfilter->ipaddr.v4.data));
4800         } else {
4801                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4802                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4803                                 &tunnel_filter->ip_addr,
4804                                 sizeof(pfilter->ipaddr.v6.data));
4805         }
4806
4807         /* check tunneled type */
4808         switch (tunnel_filter->tunnel_type) {
4809         case RTE_TUNNEL_TYPE_VXLAN:
4810                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4811                 break;
4812         default:
4813                 /* Other tunnel types is not supported. */
4814                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4815                 rte_free(cld_filter);
4816                 return -EINVAL;
4817         }
4818
4819         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4820                                                 &pfilter->flags);
4821         if (val < 0) {
4822                 rte_free(cld_filter);
4823                 return -EINVAL;
4824         }
4825
4826         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4827                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4828         pfilter->tenant_id = tunnel_filter->tenant_id;
4829         pfilter->queue_number = tunnel_filter->queue_id;
4830
4831         if (add)
4832                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4833         else
4834                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4835                                                 cld_filter, 1);
4836
4837         rte_free(cld_filter);
4838         return ret;
4839 }
4840
4841 static int
4842 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4843 {
4844         uint8_t i;
4845
4846         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4847                 if (pf->vxlan_ports[i] == port)
4848                         return i;
4849         }
4850
4851         return -1;
4852 }
4853
4854 static int
4855 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4856 {
4857         int  idx, ret;
4858         uint8_t filter_idx;
4859         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4860
4861         idx = i40e_get_vxlan_port_idx(pf, port);
4862
4863         /* Check if port already exists */
4864         if (idx >= 0) {
4865                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4866                 return -EINVAL;
4867         }
4868
4869         /* Now check if there is space to add the new port */
4870         idx = i40e_get_vxlan_port_idx(pf, 0);
4871         if (idx < 0) {
4872                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4873                         "not adding port %d", port);
4874                 return -ENOSPC;
4875         }
4876
4877         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4878                                         &filter_idx, NULL);
4879         if (ret < 0) {
4880                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4881                 return -1;
4882         }
4883
4884         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4885                          port,  filter_idx);
4886
4887         /* New port: add it and mark its index in the bitmap */
4888         pf->vxlan_ports[idx] = port;
4889         pf->vxlan_bitmap |= (1 << idx);
4890
4891         if (!(pf->flags & I40E_FLAG_VXLAN))
4892                 pf->flags |= I40E_FLAG_VXLAN;
4893
4894         return 0;
4895 }
4896
4897 static int
4898 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4899 {
4900         int idx;
4901         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4902
4903         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4904                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4905                 return -EINVAL;
4906         }
4907
4908         idx = i40e_get_vxlan_port_idx(pf, port);
4909
4910         if (idx < 0) {
4911                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4912                 return -EINVAL;
4913         }
4914
4915         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4916                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4917                 return -1;
4918         }
4919
4920         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4921                         port, idx);
4922
4923         pf->vxlan_ports[idx] = 0;
4924         pf->vxlan_bitmap &= ~(1 << idx);
4925
4926         if (!pf->vxlan_bitmap)
4927                 pf->flags &= ~I40E_FLAG_VXLAN;
4928
4929         return 0;
4930 }
4931
4932 /* Add UDP tunneling port */
4933 static int
4934 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4935                         struct rte_eth_udp_tunnel *udp_tunnel)
4936 {
4937         int ret = 0;
4938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4939
4940         if (udp_tunnel == NULL)
4941                 return -EINVAL;
4942
4943         switch (udp_tunnel->prot_type) {
4944         case RTE_TUNNEL_TYPE_VXLAN:
4945                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4946                 break;
4947
4948         case RTE_TUNNEL_TYPE_GENEVE:
4949         case RTE_TUNNEL_TYPE_TEREDO:
4950                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4951                 ret = -1;
4952                 break;
4953
4954         default:
4955                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4956                 ret = -1;
4957                 break;
4958         }
4959
4960         return ret;
4961 }
4962
4963 /* Remove UDP tunneling port */
4964 static int
4965 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4966                         struct rte_eth_udp_tunnel *udp_tunnel)
4967 {
4968         int ret = 0;
4969         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4970
4971         if (udp_tunnel == NULL)
4972                 return -EINVAL;
4973
4974         switch (udp_tunnel->prot_type) {
4975         case RTE_TUNNEL_TYPE_VXLAN:
4976                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4977                 break;
4978         case RTE_TUNNEL_TYPE_GENEVE:
4979         case RTE_TUNNEL_TYPE_TEREDO:
4980                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4981                 ret = -1;
4982                 break;
4983         default:
4984                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4985                 ret = -1;
4986                 break;
4987         }
4988
4989         return ret;
4990 }
4991
4992 /* Calculate the maximum number of contiguous PF queues that are configured */
4993 static int
4994 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4995 {
4996         struct rte_eth_dev_data *data = pf->dev_data;
4997         int i, num;
4998         struct i40e_rx_queue *rxq;
4999
5000         num = 0;
5001         for (i = 0; i < pf->lan_nb_qps; i++) {
5002                 rxq = data->rx_queues[i];
5003                 if (rxq && rxq->q_set)
5004                         num++;
5005                 else
5006                         break;
5007         }
5008
5009         return num;
5010 }
5011
5012 /* Configure RSS */
5013 static int
5014 i40e_pf_config_rss(struct i40e_pf *pf)
5015 {
5016         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5017         struct rte_eth_rss_conf rss_conf;
5018         uint32_t i, lut = 0;
5019         uint16_t j, num;
5020
5021         /*
5022          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5023          * It's necessary to calulate the actual PF queues that are configured.
5024          */
5025         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5026                 num = i40e_pf_calc_configured_queues_num(pf);
5027                 num = i40e_align_floor(num);
5028         } else
5029                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5030
5031         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5032                         num);
5033
5034         if (num == 0) {
5035                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5036                 return -ENOTSUP;
5037         }
5038
5039         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5040                 if (j == num)
5041                         j = 0;
5042                 lut = (lut << 8) | (j & ((0x1 <<
5043                         hw->func_caps.rss_table_entry_width) - 1));
5044                 if ((i & 3) == 3)
5045                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5046         }
5047
5048         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5049         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5050                 i40e_pf_disable_rss(pf);
5051                 return 0;
5052         }
5053         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5054                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5055                 /* Random default keys */
5056                 static uint32_t rss_key_default[] = {0x6b793944,
5057                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5058                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5059                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5060
5061                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5062                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5063                                                         sizeof(uint32_t);
5064         }
5065
5066         return i40e_hw_rss_hash_set(hw, &rss_conf);
5067 }
5068
5069 static int
5070 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5071                         struct rte_eth_tunnel_filter_conf *filter)
5072 {
5073         if (pf == NULL || filter == NULL) {
5074                 PMD_DRV_LOG(ERR, "Invalid parameter");
5075                 return -EINVAL;
5076         }
5077
5078         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5079                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5080                 return -EINVAL;
5081         }
5082
5083         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5084                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5085                 return -EINVAL;
5086         }
5087
5088         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5089                 (is_zero_ether_addr(filter->outer_mac))) {
5090                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5091                 return -EINVAL;
5092         }
5093
5094         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5095                 (is_zero_ether_addr(filter->inner_mac))) {
5096                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5097                 return -EINVAL;
5098         }
5099
5100         return 0;
5101 }
5102
5103 static int
5104 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5105                         void *arg)
5106 {
5107         struct rte_eth_tunnel_filter_conf *filter;
5108         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5109         int ret = I40E_SUCCESS;
5110
5111         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5112
5113         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5114                 return I40E_ERR_PARAM;
5115
5116         switch (filter_op) {
5117         case RTE_ETH_FILTER_NOP:
5118                 if (!(pf->flags & I40E_FLAG_VXLAN))
5119                         ret = I40E_NOT_SUPPORTED;
5120         case RTE_ETH_FILTER_ADD:
5121                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5122                 break;
5123         case RTE_ETH_FILTER_DELETE:
5124                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5125                 break;
5126         default:
5127                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5128                 ret = I40E_ERR_PARAM;
5129                 break;
5130         }
5131
5132         return ret;
5133 }
5134
5135 static int
5136 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5137 {
5138         int ret = 0;
5139         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5140
5141         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5142                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5143                 return -ENOTSUP;
5144         }
5145
5146         /* RSS setup */
5147         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5148                 ret = i40e_pf_config_rss(pf);
5149         else
5150                 i40e_pf_disable_rss(pf);
5151
5152         return ret;
5153 }
5154
5155 /* Get the symmetric hash enable configurations per port */
5156 static void
5157 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5158 {
5159         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5160
5161         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5162 }
5163
5164 /* Set the symmetric hash enable configurations per port */
5165 static void
5166 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5167 {
5168         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5169
5170         if (enable > 0) {
5171                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5172                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5173                                                         "been enabled");
5174                         return;
5175                 }
5176                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5177         } else {
5178                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5179                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5180                                                         "been disabled");
5181                         return;
5182                 }
5183                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5184         }
5185         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5186         I40E_WRITE_FLUSH(hw);
5187 }
5188
5189 /*
5190  * Get global configurations of hash function type and symmetric hash enable
5191  * per flow type (pctype). Note that global configuration means it affects all
5192  * the ports on the same NIC.
5193  */
5194 static int
5195 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5196                                    struct rte_eth_hash_global_conf *g_cfg)
5197 {
5198         uint32_t reg, mask = I40E_FLOW_TYPES;
5199         uint32_t i;
5200         enum i40e_filter_pctype pctype;
5201
5202         memset(g_cfg, 0, sizeof(*g_cfg));
5203         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5204         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5205                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5206         else
5207                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5208         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5209                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5210
5211         for (i = 0; mask && i < RTE_ETH_FLOW_TYPE_MAX; i++) {
5212                 if (!(mask & (1UL << i)))
5213                         continue;
5214                 mask &= ~(1UL << i);
5215                 /* Bit set indicats the coresponding flow type is supported */
5216                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5217                 pctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);
5218                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5219                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5220                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5221         }
5222
5223         return 0;
5224 }
5225
5226 static int
5227 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5228 {
5229         uint32_t i;
5230         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5231
5232         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5233                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5234                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5235                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5236                                                 g_cfg->hash_func);
5237                 return -EINVAL;
5238         }
5239
5240         /*
5241          * As i40e supports less than 32 flow types, only first 32 bits need to
5242          * be checked.
5243          */
5244         mask0 = g_cfg->valid_bit_mask[0];
5245         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5246                 if (i == 0) {
5247                         /* Check if any unsupported flow type configured */
5248                         if ((mask0 | i40e_mask) ^ i40e_mask)
5249                                 goto mask_err;
5250                 } else {
5251                         if (g_cfg->valid_bit_mask[i])
5252                                 goto mask_err;
5253                 }
5254         }
5255
5256         return 0;
5257
5258 mask_err:
5259         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5260
5261         return -EINVAL;
5262 }
5263
5264 /*
5265  * Set global configurations of hash function type and symmetric hash enable
5266  * per flow type (pctype). Note any modifying global configuration will affect
5267  * all the ports on the same NIC.
5268  */
5269 static int
5270 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5271                                    struct rte_eth_hash_global_conf *g_cfg)
5272 {
5273         int ret;
5274         uint32_t i, reg;
5275         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5276         enum i40e_filter_pctype pctype;
5277
5278         /* Check the input parameters */
5279         ret = i40e_hash_global_config_check(g_cfg);
5280         if (ret < 0)
5281                 return ret;
5282
5283         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5284                 if (!(mask0 & (1UL << i)))
5285                         continue;
5286                 mask0 &= ~(1UL << i);
5287                 pctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);
5288                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5289                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5290                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5291         }
5292
5293         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5294         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5295                 /* Toeplitz */
5296                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5297                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5298                                                                 "Toeplitz");
5299                         goto out;
5300                 }
5301                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5302         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5303                 /* Simple XOR */
5304                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5305                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5306                                                         "Simple XOR");
5307                         goto out;
5308                 }
5309                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5310         } else
5311                 /* Use the default, and keep it as it is */
5312                 goto out;
5313
5314         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5315
5316 out:
5317         I40E_WRITE_FLUSH(hw);
5318
5319         return 0;
5320 }
5321
5322 static int
5323 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5324 {
5325         int ret = 0;
5326
5327         if (!hw || !info) {
5328                 PMD_DRV_LOG(ERR, "Invalid pointer");
5329                 return -EFAULT;
5330         }
5331
5332         switch (info->info_type) {
5333         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5334                 i40e_get_symmetric_hash_enable_per_port(hw,
5335                                         &(info->info.enable));
5336                 break;
5337         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5338                 ret = i40e_get_hash_filter_global_config(hw,
5339                                 &(info->info.global_conf));
5340                 break;
5341         default:
5342                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5343                                                         info->info_type);
5344                 ret = -EINVAL;
5345                 break;
5346         }
5347
5348         return ret;
5349 }
5350
5351 static int
5352 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5353 {
5354         int ret = 0;
5355
5356         if (!hw || !info) {
5357                 PMD_DRV_LOG(ERR, "Invalid pointer");
5358                 return -EFAULT;
5359         }
5360
5361         switch (info->info_type) {
5362         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5363                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5364                 break;
5365         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5366                 ret = i40e_set_hash_filter_global_config(hw,
5367                                 &(info->info.global_conf));
5368                 break;
5369         default:
5370                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5371                                                         info->info_type);
5372                 ret = -EINVAL;
5373                 break;
5374         }
5375
5376         return ret;
5377 }
5378
5379 /* Operations for hash function */
5380 static int
5381 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5382                       enum rte_filter_op filter_op,
5383                       void *arg)
5384 {
5385         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5386         int ret = 0;
5387
5388         switch (filter_op) {
5389         case RTE_ETH_FILTER_NOP:
5390                 break;
5391         case RTE_ETH_FILTER_GET:
5392                 ret = i40e_hash_filter_get(hw,
5393                         (struct rte_eth_hash_filter_info *)arg);
5394                 break;
5395         case RTE_ETH_FILTER_SET:
5396                 ret = i40e_hash_filter_set(hw,
5397                         (struct rte_eth_hash_filter_info *)arg);
5398                 break;
5399         default:
5400                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5401                                                                 filter_op);
5402                 ret = -ENOTSUP;
5403                 break;
5404         }
5405
5406         return ret;
5407 }
5408
5409 /*
5410  * Configure ethertype filter, which can director packet by filtering
5411  * with mac address and ether_type or only ether_type
5412  */
5413 static int
5414 i40e_ethertype_filter_set(struct i40e_pf *pf,
5415                         struct rte_eth_ethertype_filter *filter,
5416                         bool add)
5417 {
5418         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5419         struct i40e_control_filter_stats stats;
5420         uint16_t flags = 0;
5421         int ret;
5422
5423         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5424                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5425                 return -EINVAL;
5426         }
5427         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5428                 filter->ether_type == ETHER_TYPE_IPv6) {
5429                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5430                         " control packet filter.", filter->ether_type);
5431                 return -EINVAL;
5432         }
5433         if (filter->ether_type == ETHER_TYPE_VLAN)
5434                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5435                         " not supported.");
5436
5437         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5438                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5439         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5440                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5441         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5442
5443         memset(&stats, 0, sizeof(stats));
5444         ret = i40e_aq_add_rem_control_packet_filter(hw,
5445                         filter->mac_addr.addr_bytes,
5446                         filter->ether_type, flags,
5447                         pf->main_vsi->seid,
5448                         filter->queue, add, &stats, NULL);
5449
5450         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5451                          " mac_etype_used = %u, etype_used = %u,"
5452                          " mac_etype_free = %u, etype_free = %u\n",
5453                          ret, stats.mac_etype_used, stats.etype_used,
5454                          stats.mac_etype_free, stats.etype_free);
5455         if (ret < 0)
5456                 return -ENOSYS;
5457         return 0;
5458 }
5459
5460 /*
5461  * Handle operations for ethertype filter.
5462  */
5463 static int
5464 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5465                                 enum rte_filter_op filter_op,
5466                                 void *arg)
5467 {
5468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5469         int ret = 0;
5470
5471         if (filter_op == RTE_ETH_FILTER_NOP)
5472                 return ret;
5473
5474         if (arg == NULL) {
5475                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5476                             filter_op);
5477                 return -EINVAL;
5478         }
5479
5480         switch (filter_op) {
5481         case RTE_ETH_FILTER_ADD:
5482                 ret = i40e_ethertype_filter_set(pf,
5483                         (struct rte_eth_ethertype_filter *)arg,
5484                         TRUE);
5485                 break;
5486         case RTE_ETH_FILTER_DELETE:
5487                 ret = i40e_ethertype_filter_set(pf,
5488                         (struct rte_eth_ethertype_filter *)arg,
5489                         FALSE);
5490                 break;
5491         default:
5492                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5493                 ret = -ENOSYS;
5494                 break;
5495         }
5496         return ret;
5497 }
5498
5499 static int
5500 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5501                      enum rte_filter_type filter_type,
5502                      enum rte_filter_op filter_op,
5503                      void *arg)
5504 {
5505         int ret = 0;
5506
5507         if (dev == NULL)
5508                 return -EINVAL;
5509
5510         switch (filter_type) {
5511         case RTE_ETH_FILTER_HASH:
5512                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5513                 break;
5514         case RTE_ETH_FILTER_MACVLAN:
5515                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5516                 break;
5517         case RTE_ETH_FILTER_ETHERTYPE:
5518                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5519                 break;
5520         case RTE_ETH_FILTER_TUNNEL:
5521                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5522                 break;
5523         case RTE_ETH_FILTER_FDIR:
5524                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5525                 break;
5526         default:
5527                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5528                                                         filter_type);
5529                 ret = -EINVAL;
5530                 break;
5531         }
5532
5533         return ret;
5534 }
5535
5536 /*
5537  * As some registers wouldn't be reset unless a global hardware reset,
5538  * hardware initialization is needed to put those registers into an
5539  * expected initial state.
5540  */
5541 static void
5542 i40e_hw_init(struct i40e_hw *hw)
5543 {
5544         /* clear the PF Queue Filter control register */
5545         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5546
5547         /* Disable symmetric hash per port */
5548         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5549 }
5550
5551 enum i40e_filter_pctype
5552 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5553 {
5554         static const enum i40e_filter_pctype
5555                 pctype_table[RTE_ETH_FLOW_TYPE_MAX] = {
5556                 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5557                 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5558                 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5559                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5560                                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5561                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5562                                         I40E_FILTER_PCTYPE_FRAG_IPV4,
5563                 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5564                 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5565                 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5566                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5567                                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5568                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5569                                         I40E_FILTER_PCTYPE_FRAG_IPV6,
5570         };
5571
5572         return pctype_table[flow_type];
5573 }
5574
5575 enum rte_eth_flow_type
5576 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5577 {
5578         static const enum rte_eth_flow_type
5579                 flowtype_table[RTE_ETH_FLOW_TYPE_MAX] = {
5580                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5581                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5582                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5583                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5584                                         RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5585                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5586                                         RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5587                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5588                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5589                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5590                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5591                                         RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5592                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5593                                         RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5594         };
5595
5596         return flowtype_table[pctype];
5597 }
5598
5599 static int
5600 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5601 {
5602         struct i40e_aq_desc desc;
5603         enum i40e_status_code status;
5604
5605         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5606         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5607         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5608         if (status < 0)
5609                 return status;
5610
5611         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5612                                         (CHAR_BIT * sizeof(uint32_t))) +
5613                                 rte_le_to_cpu_32(desc.params.internal.param3);
5614
5615         return status;
5616 }
5617
5618 /*
5619  * On X710, performance number is far from the expectation on recent firmware
5620  * versions. The fix for this issue may not be integrated in the following
5621  * firmware version. So the workaround in software driver is needed. It needs
5622  * to modify the initial values of 3 internal only registers. Note that the
5623  * workaround can be removed when it is fixed in firmware in the future.
5624  */
5625 static void
5626 i40e_configure_registers(struct i40e_hw *hw)
5627 {
5628 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5629 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5630 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5631 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5632 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5633 #define I40E_GL_SWR_PM_UP_THR_VALUE      0x03030303
5634
5635         static const struct {
5636                 uint32_t addr;
5637                 uint64_t val;
5638         } reg_table[] = {
5639                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5640                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5641                 {I40E_GL_SWR_PM_UP_THR, I40E_GL_SWR_PM_UP_THR_VALUE},
5642         };
5643         uint64_t reg;
5644         uint32_t i;
5645         int ret;
5646
5647         /* Below fix is for X710 only */
5648         if (i40e_is_40G_device(hw->device_id))
5649                 return;
5650
5651         for (i = 0; i < RTE_DIM(reg_table); i++) {
5652                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5653                 if (ret < 0) {
5654                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5655                                                         reg_table[i].addr);
5656                         break;
5657                 }
5658                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5659                                                 reg_table[i].addr, reg);
5660                 if (reg == reg_table[i].val)
5661                         continue;
5662
5663                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5664                                                 reg_table[i].val, NULL);
5665                 if (ret < 0) {
5666                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5667                                 "address of 0x%"PRIx32, reg_table[i].val,
5668                                                         reg_table[i].addr);
5669                         break;
5670                 }
5671                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5672                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5673         }
5674 }