lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51 #include <rte_eth_ctrl.h>
  52
  53 #include "i40e_logs.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 #define I40E_DEFAULT_RX_FREE_THRESH  32
  62 #define I40E_DEFAULT_RX_PTHRESH      8
  63 #define I40E_DEFAULT_RX_HTHRESH      8
  64 #define I40E_DEFAULT_RX_WTHRESH      0
  65
  66 #define I40E_DEFAULT_TX_FREE_THRESH  32
  67 #define I40E_DEFAULT_TX_PTHRESH      32
  68 #define I40E_DEFAULT_TX_HTHRESH      0
  69 #define I40E_DEFAULT_TX_WTHRESH      0
  70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  71
  72 /* Maximun number of MAC addresses */
  73 #define I40E_NUM_MACADDR_MAX       64
  74 #define I40E_CLEAR_PXE_WAIT_MS     200
  75
  76 /* Maximun number of capability elements */
  77 #define I40E_MAX_CAP_ELE_NUM       128
  78
  79 /* Wait count and inteval */
  80 #define I40E_CHK_Q_ENA_COUNT       1000
  81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  82
  83 /* Maximun number of VSI */
  84 #define I40E_MAX_NUM_VSIS          (384UL)
  85
  86 /* Bit shift and mask */
  87 #define I40E_16_BIT_SHIFT 16
  88 #define I40E_16_BIT_MASK  0xFFFF
  89 #define I40E_32_BIT_SHIFT 32
  90 #define I40E_32_BIT_MASK  0xFFFFFFFF
  91 #define I40E_48_BIT_SHIFT 48
  92 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  93
  94 /* Default queue interrupt throttling time in microseconds*/
  95 #define I40E_ITR_INDEX_DEFAULT          0
  96 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  97 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  98
  99 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 100
 101 static int eth_i40e_dev_init(\
 102                         __attribute__((unused)) struct eth_driver *eth_drv,
 103                         struct rte_eth_dev *eth_dev);
 104 static int i40e_dev_configure(struct rte_eth_dev *dev);
 105 static int i40e_dev_start(struct rte_eth_dev *dev);
 106 static void i40e_dev_stop(struct rte_eth_dev *dev);
 107 static void i40e_dev_close(struct rte_eth_dev *dev);
 108 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 113 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 114 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 115                                struct rte_eth_stats *stats);
 116 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 117 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 118                                             uint16_t queue_id,
 119                                             uint8_t stat_idx,
 120                                             uint8_t is_rx);
 121 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 122                               struct rte_eth_dev_info *dev_info);
 123 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 124                                 uint16_t vlan_id,
 125                                 int on);
 126 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 127 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 128 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 129                                       uint16_t queue,
 130                                       int on);
 131 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 132 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 133 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 134 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 135                               struct rte_eth_fc_conf *fc_conf);
 136 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 137                                        struct rte_eth_pfc_conf *pfc_conf);
 138 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 139                           struct ether_addr *mac_addr,
 140                           uint32_t index,
 141                           uint32_t pool);
 142 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                                     struct rte_eth_rss_reta *reta_conf);
 145 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                                    struct rte_eth_rss_reta *reta_conf);
 147
 148 static int i40e_get_cap(struct i40e_hw *hw);
 149 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 150 static int i40e_pf_setup(struct i40e_pf *pf);
 151 static int i40e_vsi_init(struct i40e_vsi *vsi);
 152 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 153                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 154 static void i40e_stat_update_48(struct i40e_hw *hw,
 155                                uint32_t hireg,
 156                                uint32_t loreg,
 157                                bool offset_loaded,
 158                                uint64_t *offset,
 159                                uint64_t *stat);
 160 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 161 static void i40e_dev_interrupt_handler(
 162                 __rte_unused struct rte_intr_handle *handle, void *param);
 163 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 164                                 uint32_t base, uint32_t num);
 165 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 166 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 167                         uint32_t base);
 168 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 169                         uint16_t num);
 170 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 171 static int i40e_veb_release(struct i40e_veb *veb);
 172 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 173                                                 struct i40e_vsi *vsi);
 174 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 175 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 176 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 177                                              struct i40e_macvlan_filter *mv_f,
 178                                              int num,
 179                                              struct ether_addr *addr);
 180 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 181                                              struct i40e_macvlan_filter *mv_f,
 182                                              int num,
 183                                              uint16_t vlan);
 184 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 185 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 186                                     struct rte_eth_rss_conf *rss_conf);
 187 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 188                                       struct rte_eth_rss_conf *rss_conf);
 189 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 190                                 struct rte_eth_udp_tunnel *udp_tunnel);
 191 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 192                                 struct rte_eth_udp_tunnel *udp_tunnel);
 193 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 194                                 enum rte_filter_type filter_type,
 195                                 enum rte_filter_op filter_op,
 196                                 void *arg);
 197
 198 /* Default hash key buffer for RSS */
 199 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 200
 201 static struct rte_pci_id pci_id_i40e_map[] = {
 202 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 203 #include "rte_pci_dev_ids.h"
 204 { .vendor_id = 0, /* sentinel */ },
 205 };
 206
 207 static struct eth_dev_ops i40e_eth_dev_ops = {
 208         .dev_configure                = i40e_dev_configure,
 209         .dev_start                    = i40e_dev_start,
 210         .dev_stop                     = i40e_dev_stop,
 211         .dev_close                    = i40e_dev_close,
 212         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 213         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 214         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 215         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 216         .dev_set_link_up              = i40e_dev_set_link_up,
 217         .dev_set_link_down            = i40e_dev_set_link_down,
 218         .link_update                  = i40e_dev_link_update,
 219         .stats_get                    = i40e_dev_stats_get,
 220         .stats_reset                  = i40e_dev_stats_reset,
 221         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 222         .dev_infos_get                = i40e_dev_info_get,
 223         .vlan_filter_set              = i40e_vlan_filter_set,
 224         .vlan_tpid_set                = i40e_vlan_tpid_set,
 225         .vlan_offload_set             = i40e_vlan_offload_set,
 226         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 227         .vlan_pvid_set                = i40e_vlan_pvid_set,
 228         .rx_queue_start               = i40e_dev_rx_queue_start,
 229         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 230         .tx_queue_start               = i40e_dev_tx_queue_start,
 231         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 232         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 233         .rx_queue_release             = i40e_dev_rx_queue_release,
 234         .rx_queue_count               = i40e_dev_rx_queue_count,
 235         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 236         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 237         .tx_queue_release             = i40e_dev_tx_queue_release,
 238         .dev_led_on                   = i40e_dev_led_on,
 239         .dev_led_off                  = i40e_dev_led_off,
 240         .flow_ctrl_set                = i40e_flow_ctrl_set,
 241         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 242         .mac_addr_add                 = i40e_macaddr_add,
 243         .mac_addr_remove              = i40e_macaddr_remove,
 244         .reta_update                  = i40e_dev_rss_reta_update,
 245         .reta_query                   = i40e_dev_rss_reta_query,
 246         .rss_hash_update              = i40e_dev_rss_hash_update,
 247         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 248         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 249         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 250         .filter_ctrl                  = i40e_dev_filter_ctrl,
 251 };
 252
 253 static struct eth_driver rte_i40e_pmd = {
 254         {
 255                 .name = "rte_i40e_pmd",
 256                 .id_table = pci_id_i40e_map,
 257                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 258         },
 259         .eth_dev_init = eth_i40e_dev_init,
 260         .dev_private_size = sizeof(struct i40e_adapter),
 261 };
 262
 263 static inline int
 264 i40e_prev_power_of_2(int n)
 265 {
 266        int p = n;
 267
 268        --p;
 269        p |= p >> 1;
 270        p |= p >> 2;
 271        p |= p >> 4;
 272        p |= p >> 8;
 273        p |= p >> 16;
 274        if (p == (n - 1))
 275                return n;
 276        p >>= 1;
 277
 278        return ++p;
 279 }
 280
 281 static inline int
 282 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 283                                      struct rte_eth_link *link)
 284 {
 285         struct rte_eth_link *dst = link;
 286         struct rte_eth_link *src = &(dev->data->dev_link);
 287
 288         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 289                                         *(uint64_t *)src) == 0)
 290                 return -1;
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 297                                       struct rte_eth_link *link)
 298 {
 299         struct rte_eth_link *dst = &(dev->data->dev_link);
 300         struct rte_eth_link *src = link;
 301
 302         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 303                                         *(uint64_t *)src) == 0)
 304                 return -1;
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * Driver initialization routine.
 311  * Invoked once at EAL init time.
 312  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 313  */
 314 static int
 315 rte_i40e_pmd_init(const char *name __rte_unused,
 316                   const char *params __rte_unused)
 317 {
 318         PMD_INIT_FUNC_TRACE();
 319         rte_eth_driver_register(&rte_i40e_pmd);
 320
 321         return 0;
 322 }
 323
 324 static struct rte_driver rte_i40e_driver = {
 325         .type = PMD_PDEV,
 326         .init = rte_i40e_pmd_init,
 327 };
 328
 329 PMD_REGISTER_DRIVER(rte_i40e_driver);
 330
 331 static int
 332 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 333                   struct rte_eth_dev *dev)
 334 {
 335         struct rte_pci_device *pci_dev;
 336         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vsi *vsi;
 339         int ret;
 340         uint32_t len;
 341         uint8_t aq_fail = 0;
 342
 343         PMD_INIT_FUNC_TRACE();
 344
 345         dev->dev_ops = &i40e_eth_dev_ops;
 346         dev->rx_pkt_burst = i40e_recv_pkts;
 347         dev->tx_pkt_burst = i40e_xmit_pkts;
 348
 349         /* for secondary processes, we don't initialise any further as primary
 350          * has already done this work. Only check we don't need a different
 351          * RX function */
 352         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 353                 if (dev->data->scattered_rx)
 354                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 355                 return 0;
 356         }
 357         pci_dev = dev->pci_dev;
 358         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 359         pf->adapter->eth_dev = dev;
 360         pf->dev_data = dev->data;
 361
 362         hw->back = I40E_PF_TO_ADAPTER(pf);
 363         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 364         if (!hw->hw_addr) {
 365                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 366                              "as address is NULL");
 367                 return -ENODEV;
 368         }
 369
 370         hw->vendor_id = pci_dev->id.vendor_id;
 371         hw->device_id = pci_dev->id.device_id;
 372         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 373         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 374         hw->bus.device = pci_dev->addr.devid;
 375         hw->bus.func = pci_dev->addr.function;
 376
 377         /* Make sure all is clean before doing PF reset */
 378         i40e_clear_hw(hw);
 379
 380         /* Reset here to make sure all is clean for each PF */
 381         ret = i40e_pf_reset(hw);
 382         if (ret) {
 383                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 384                 return ret;
 385         }
 386
 387         /* Initialize the shared code (base driver) */
 388         ret = i40e_init_shared_code(hw);
 389         if (ret) {
 390                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 391                 return ret;
 392         }
 393
 394         /* Initialize the parameters for adminq */
 395         i40e_init_adminq_parameter(hw);
 396         ret = i40e_init_adminq(hw);
 397         if (ret != I40E_SUCCESS) {
 398                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 399                 return -EIO;
 400         }
 401         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 402                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 403                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 404                      ((hw->nvm.version >> 12) & 0xf),
 405                      ((hw->nvm.version >> 4) & 0xff),
 406                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 407
 408         /* Disable LLDP */
 409         ret = i40e_aq_stop_lldp(hw, true, NULL);
 410         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 411                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 412
 413         /* Clear PXE mode */
 414         i40e_clear_pxe_mode(hw);
 415
 416         /* Get hw capabilities */
 417         ret = i40e_get_cap(hw);
 418         if (ret != I40E_SUCCESS) {
 419                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 420                 goto err_get_capabilities;
 421         }
 422
 423         /* Initialize parameters for PF */
 424         ret = i40e_pf_parameter_init(dev);
 425         if (ret != 0) {
 426                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 427                 goto err_parameter_init;
 428         }
 429
 430         /* Initialize the queue management */
 431         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 432         if (ret < 0) {
 433                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 434                 goto err_qp_pool_init;
 435         }
 436         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 437                                 hw->func_caps.num_msix_vectors - 1);
 438         if (ret < 0) {
 439                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 440                 goto err_msix_pool_init;
 441         }
 442
 443         /* Initialize lan hmc */
 444         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 445                                 hw->func_caps.num_rx_qp, 0, 0);
 446         if (ret != I40E_SUCCESS) {
 447                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 448                 goto err_init_lan_hmc;
 449         }
 450
 451         /* Configure lan hmc */
 452         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 453         if (ret != I40E_SUCCESS) {
 454                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 455                 goto err_configure_lan_hmc;
 456         }
 457
 458         /* Get and check the mac address */
 459         i40e_get_mac_addr(hw, hw->mac.addr);
 460         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 461                 PMD_INIT_LOG(ERR, "mac address is not valid");
 462                 ret = -EIO;
 463                 goto err_get_mac_addr;
 464         }
 465         /* Copy the permanent MAC address */
 466         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 467                         (struct ether_addr *) hw->mac.perm_addr);
 468
 469         /* Disable flow control */
 470         hw->fc.requested_mode = I40E_FC_NONE;
 471         i40e_set_fc(hw, &aq_fail, TRUE);
 472
 473         /* PF setup, which includes VSI setup */
 474         ret = i40e_pf_setup(pf);
 475         if (ret) {
 476                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 477                 goto err_setup_pf_switch;
 478         }
 479
 480         vsi = pf->main_vsi;
 481
 482         /* Disable double vlan by default */
 483         i40e_vsi_config_double_vlan(vsi, FALSE);
 484
 485         if (!vsi->max_macaddrs)
 486                 len = ETHER_ADDR_LEN;
 487         else
 488                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 489
 490         /* Should be after VSI initialized */
 491         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 492         if (!dev->data->mac_addrs) {
 493                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 494                                         "for storing mac address");
 495                 goto err_get_mac_addr;
 496         }
 497         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 498                                         &dev->data->mac_addrs[0]);
 499
 500         /* initialize pf host driver to setup SRIOV resource if applicable */
 501         i40e_pf_host_init(dev);
 502
 503         /* register callback func to eal lib */
 504         rte_intr_callback_register(&(pci_dev->intr_handle),
 505                 i40e_dev_interrupt_handler, (void *)dev);
 506
 507         /* configure and enable device interrupt */
 508         i40e_pf_config_irq0(hw);
 509         i40e_pf_enable_irq0(hw);
 510
 511         /* enable uio intr after callback register */
 512         rte_intr_enable(&(pci_dev->intr_handle));
 513
 514         return 0;
 515
 516 err_setup_pf_switch:
 517         rte_free(pf->main_vsi);
 518 err_get_mac_addr:
 519 err_configure_lan_hmc:
 520         (void)i40e_shutdown_lan_hmc(hw);
 521 err_init_lan_hmc:
 522         i40e_res_pool_destroy(&pf->msix_pool);
 523 err_msix_pool_init:
 524         i40e_res_pool_destroy(&pf->qp_pool);
 525 err_qp_pool_init:
 526 err_parameter_init:
 527 err_get_capabilities:
 528         (void)i40e_shutdown_adminq(hw);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 i40e_dev_configure(struct rte_eth_dev *dev)
 535 {
 536         return i40e_dev_init_vlan(dev);
 537 }
 538
 539 void
 540 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 541 {
 542         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 543         uint16_t msix_vect = vsi->msix_intr;
 544         uint16_t i;
 545
 546         for (i = 0; i < vsi->nb_qps; i++) {
 547                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 548                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 549                 rte_wmb();
 550         }
 551
 552         if (vsi->type != I40E_VSI_SRIOV) {
 553                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 554                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 555                                 msix_vect - 1), 0);
 556         } else {
 557                 uint32_t reg;
 558                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 559                         vsi->user_param + (msix_vect - 1);
 560
 561                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 562         }
 563         I40E_WRITE_FLUSH(hw);
 564 }
 565
 566 static inline uint16_t
 567 i40e_calc_itr_interval(int16_t interval)
 568 {
 569         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 570                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 571
 572         /* Convert to hardware count, as writing each 1 represents 2 us */
 573         return (interval/2);
 574 }
 575
 576 void
 577 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 578 {
 579         uint32_t val;
 580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 581         uint16_t msix_vect = vsi->msix_intr;
 582         int i;
 583
 584         for (i = 0; i < vsi->nb_qps; i++)
 585                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 586
 587         /* Bind all RX queues to allocated MSIX interrupt */
 588         for (i = 0; i < vsi->nb_qps; i++) {
 589                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 590                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 591                         ((vsi->base_queue + i + 1) <<
 592                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 593                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 594                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 595
 596                 if (i == vsi->nb_qps - 1)
 597                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 598                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 599         }
 600
 601         /* Write first RX queue to Link list register as the head element */
 602         if (vsi->type != I40E_VSI_SRIOV) {
 603                 uint16_t interval =
 604                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 605
 606                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 607                                                 (vsi->base_queue <<
 608                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 609                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 610
 611                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 612                                                 msix_vect - 1), interval);
 613
 614 #ifndef I40E_GLINT_CTL
 615 #define I40E_GLINT_CTL                     0x0003F800
 616 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 617 #endif
 618                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 619                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 620                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 621         } else {
 622                 uint32_t reg;
 623
 624                 /* num_msix_vectors_vf needs to minus irq0 */
 625                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 626                         vsi->user_param + (msix_vect - 1);
 627
 628                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 629                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 630                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 631         }
 632
 633         I40E_WRITE_FLUSH(hw);
 634 }
 635
 636 static void
 637 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 638 {
 639         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 640         uint16_t interval = i40e_calc_itr_interval(\
 641                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 642
 643         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 644                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 645                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 646                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 647                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 648 }
 649
 650 static void
 651 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 652 {
 653         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 654
 655         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 656 }
 657
 658 static inline uint8_t
 659 i40e_parse_link_speed(uint16_t eth_link_speed)
 660 {
 661         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 662
 663         switch (eth_link_speed) {
 664         case ETH_LINK_SPEED_40G:
 665                 link_speed = I40E_LINK_SPEED_40GB;
 666                 break;
 667         case ETH_LINK_SPEED_20G:
 668                 link_speed = I40E_LINK_SPEED_20GB;
 669                 break;
 670         case ETH_LINK_SPEED_10G:
 671                 link_speed = I40E_LINK_SPEED_10GB;
 672                 break;
 673         case ETH_LINK_SPEED_1000:
 674                 link_speed = I40E_LINK_SPEED_1GB;
 675                 break;
 676         case ETH_LINK_SPEED_100:
 677                 link_speed = I40E_LINK_SPEED_100MB;
 678                 break;
 679         }
 680
 681         return link_speed;
 682 }
 683
 684 static int
 685 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 686 {
 687         enum i40e_status_code status;
 688         struct i40e_aq_get_phy_abilities_resp phy_ab;
 689         struct i40e_aq_set_phy_config phy_conf;
 690         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 691                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 692                         I40E_AQ_PHY_FLAG_LOW_POWER;
 693         const uint8_t advt = I40E_LINK_SPEED_40GB |
 694                         I40E_LINK_SPEED_10GB |
 695                         I40E_LINK_SPEED_1GB |
 696                         I40E_LINK_SPEED_100MB;
 697         int ret = -ENOTSUP;
 698
 699         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 700                                               NULL);
 701         if (status)
 702                 return ret;
 703
 704         memset(&phy_conf, 0, sizeof(phy_conf));
 705
 706         /* bits 0-2 use the values from get_phy_abilities_resp */
 707         abilities &= ~mask;
 708         abilities |= phy_ab.abilities & mask;
 709
 710         /* update ablities and speed */
 711         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 712                 phy_conf.link_speed = advt;
 713         else
 714                 phy_conf.link_speed = force_speed;
 715
 716         phy_conf.abilities = abilities;
 717
 718         /* use get_phy_abilities_resp value for the rest */
 719         phy_conf.phy_type = phy_ab.phy_type;
 720         phy_conf.eee_capability = phy_ab.eee_capability;
 721         phy_conf.eeer = phy_ab.eeer_val;
 722         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 723
 724         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 725                     phy_ab.abilities, phy_ab.link_speed);
 726         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 727                     phy_conf.abilities, phy_conf.link_speed);
 728
 729         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 730         if (status)
 731                 return ret;
 732
 733         return I40E_SUCCESS;
 734 }
 735
 736 static int
 737 i40e_apply_link_speed(struct rte_eth_dev *dev)
 738 {
 739         uint8_t speed;
 740         uint8_t abilities = 0;
 741         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 742         struct rte_eth_conf *conf = &dev->data->dev_conf;
 743
 744         speed = i40e_parse_link_speed(conf->link_speed);
 745         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 746         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 747                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 748         else
 749                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 750
 751         return i40e_phy_conf_link(hw, abilities, speed);
 752 }
 753
 754 static int
 755 i40e_dev_start(struct rte_eth_dev *dev)
 756 {
 757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 759         struct i40e_vsi *vsi = pf->main_vsi;
 760         int ret;
 761
 762         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 763                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 764                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 765                              dev->data->dev_conf.link_duplex,
 766                              dev->data->port_id);
 767                 return -EINVAL;
 768         }
 769
 770         /* Initialize VSI */
 771         ret = i40e_vsi_init(vsi);
 772         if (ret != I40E_SUCCESS) {
 773                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 774                 goto err_up;
 775         }
 776
 777         /* Map queues with MSIX interrupt */
 778         i40e_vsi_queues_bind_intr(vsi);
 779         i40e_vsi_enable_queues_intr(vsi);
 780
 781         /* Enable all queues which have been configured */
 782         ret = i40e_vsi_switch_queues(vsi, TRUE);
 783         if (ret != I40E_SUCCESS) {
 784                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 785                 goto err_up;
 786         }
 787
 788         /* Enable receiving broadcast packets */
 789         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 790                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 791                 if (ret != I40E_SUCCESS)
 792                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 793         }
 794
 795         /* Apply link configure */
 796         ret = i40e_apply_link_speed(dev);
 797         if (I40E_SUCCESS != ret) {
 798                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 799                 goto err_up;
 800         }
 801
 802         return I40E_SUCCESS;
 803
 804 err_up:
 805         i40e_vsi_switch_queues(vsi, FALSE);
 806
 807         return ret;
 808 }
 809
 810 static void
 811 i40e_dev_stop(struct rte_eth_dev *dev)
 812 {
 813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 814         struct i40e_vsi *vsi = pf->main_vsi;
 815
 816         /* Disable all queues */
 817         i40e_vsi_switch_queues(vsi, FALSE);
 818
 819         /* Set link down */
 820         i40e_dev_set_link_down(dev);
 821
 822         /* un-map queues with interrupt registers */
 823         i40e_vsi_disable_queues_intr(vsi);
 824         i40e_vsi_queues_unbind_intr(vsi);
 825 }
 826
 827 static void
 828 i40e_dev_close(struct rte_eth_dev *dev)
 829 {
 830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 832         uint32_t reg;
 833
 834         PMD_INIT_FUNC_TRACE();
 835
 836         i40e_dev_stop(dev);
 837
 838         /* Disable interrupt */
 839         i40e_pf_disable_irq0(hw);
 840         rte_intr_disable(&(dev->pci_dev->intr_handle));
 841
 842         /* shutdown and destroy the HMC */
 843         i40e_shutdown_lan_hmc(hw);
 844
 845         /* release all the existing VSIs and VEBs */
 846         i40e_vsi_release(pf->main_vsi);
 847
 848         /* shutdown the adminq */
 849         i40e_aq_queue_shutdown(hw, true);
 850         i40e_shutdown_adminq(hw);
 851
 852         i40e_res_pool_destroy(&pf->qp_pool);
 853         i40e_res_pool_destroy(&pf->msix_pool);
 854
 855         /* force a PF reset to clean anything leftover */
 856         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 857         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 858                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 859         I40E_WRITE_FLUSH(hw);
 860 }
 861
 862 static void
 863 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 864 {
 865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 867         struct i40e_vsi *vsi = pf->main_vsi;
 868         int status;
 869
 870         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 871                                                         true, NULL);
 872         if (status != I40E_SUCCESS)
 873                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 874
 875         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 876                                                         TRUE, NULL);
 877         if (status != I40E_SUCCESS)
 878                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 879
 880 }
 881
 882 static void
 883 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 884 {
 885         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 887         struct i40e_vsi *vsi = pf->main_vsi;
 888         int status;
 889
 890         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 891                                                         false, NULL);
 892         if (status != I40E_SUCCESS)
 893                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 894
 895         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 896                                                         false, NULL);
 897         if (status != I40E_SUCCESS)
 898                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 899 }
 900
 901 static void
 902 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 903 {
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906         struct i40e_vsi *vsi = pf->main_vsi;
 907         int ret;
 908
 909         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 910         if (ret != I40E_SUCCESS)
 911                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 912 }
 913
 914 static void
 915 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 916 {
 917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919         struct i40e_vsi *vsi = pf->main_vsi;
 920         int ret;
 921
 922         if (dev->data->promiscuous == 1)
 923                 return; /* must remain in all_multicast mode */
 924
 925         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 926                                 vsi->seid, FALSE, NULL);
 927         if (ret != I40E_SUCCESS)
 928                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 929 }
 930
 931 /*
 932  * Set device link up.
 933  */
 934 static int
 935 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 936 {
 937         /* re-apply link speed setting */
 938         return i40e_apply_link_speed(dev);
 939 }
 940
 941 /*
 942  * Set device link down.
 943  */
 944 static int
 945 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 946 {
 947         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 948         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950
 951         return i40e_phy_conf_link(hw, abilities, speed);
 952 }
 953
 954 int
 955 i40e_dev_link_update(struct rte_eth_dev *dev,
 956                      __rte_unused int wait_to_complete)
 957 {
 958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 959         struct i40e_link_status link_status;
 960         struct rte_eth_link link, old;
 961         int status;
 962
 963         memset(&link, 0, sizeof(link));
 964         memset(&old, 0, sizeof(old));
 965         memset(&link_status, 0, sizeof(link_status));
 966         rte_i40e_dev_atomic_read_link_status(dev, &old);
 967
 968         /* Get link status information from hardware */
 969         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 970         if (status != I40E_SUCCESS) {
 971                 link.link_speed = ETH_LINK_SPEED_100;
 972                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 973                 PMD_DRV_LOG(ERR, "Failed to get link info");
 974                 goto out;
 975         }
 976
 977         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 978
 979         if (!link.link_status)
 980                 goto out;
 981
 982         /* i40e uses full duplex only */
 983         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 984
 985         /* Parse the link status */
 986         switch (link_status.link_speed) {
 987         case I40E_LINK_SPEED_100MB:
 988                 link.link_speed = ETH_LINK_SPEED_100;
 989                 break;
 990         case I40E_LINK_SPEED_1GB:
 991                 link.link_speed = ETH_LINK_SPEED_1000;
 992                 break;
 993         case I40E_LINK_SPEED_10GB:
 994                 link.link_speed = ETH_LINK_SPEED_10G;
 995                 break;
 996         case I40E_LINK_SPEED_20GB:
 997                 link.link_speed = ETH_LINK_SPEED_20G;
 998                 break;
 999         case I40E_LINK_SPEED_40GB:
1000                 link.link_speed = ETH_LINK_SPEED_40G;
1001                 break;
1002         default:
1003                 link.link_speed = ETH_LINK_SPEED_100;
1004                 break;
1005         }
1006
1007 out:
1008         rte_i40e_dev_atomic_write_link_status(dev, &link);
1009         if (link.link_status == old.link_status)
1010                 return -1;
1011
1012         return 0;
1013 }
1014
1015 /* Get all the statistics of a VSI */
1016 void
1017 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1018 {
1019         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1020         struct i40e_eth_stats *nes = &vsi->eth_stats;
1021         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1022         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1023
1024         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1025                             vsi->offset_loaded, &oes->rx_bytes,
1026                             &nes->rx_bytes);
1027         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1028                             vsi->offset_loaded, &oes->rx_unicast,
1029                             &nes->rx_unicast);
1030         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1031                             vsi->offset_loaded, &oes->rx_multicast,
1032                             &nes->rx_multicast);
1033         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1034                             vsi->offset_loaded, &oes->rx_broadcast,
1035                             &nes->rx_broadcast);
1036         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1037                             &oes->rx_discards, &nes->rx_discards);
1038         /* GLV_REPC not supported */
1039         /* GLV_RMPC not supported */
1040         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1041                             &oes->rx_unknown_protocol,
1042                             &nes->rx_unknown_protocol);
1043         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1044                             vsi->offset_loaded, &oes->tx_bytes,
1045                             &nes->tx_bytes);
1046         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1047                             vsi->offset_loaded, &oes->tx_unicast,
1048                             &nes->tx_unicast);
1049         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1050                             vsi->offset_loaded, &oes->tx_multicast,
1051                             &nes->tx_multicast);
1052         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1053                             vsi->offset_loaded,  &oes->tx_broadcast,
1054                             &nes->tx_broadcast);
1055         /* GLV_TDPC not supported */
1056         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1057                             &oes->tx_errors, &nes->tx_errors);
1058         vsi->offset_loaded = true;
1059
1060         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1061                     vsi->vsi_id);
1062         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1063         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1064         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1065         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1066         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1067         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1068                     nes->rx_unknown_protocol);
1069         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1070         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1071         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1072         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1073         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1074         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1075         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1076                     vsi->vsi_id);
1077 }
1078
1079 /* Get all statistics of a port */
1080 static void
1081 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1082 {
1083         uint32_t i;
1084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1087         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1088
1089         /* Get statistics of struct i40e_eth_stats */
1090         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1091                             I40E_GLPRT_GORCL(hw->port),
1092                             pf->offset_loaded, &os->eth.rx_bytes,
1093                             &ns->eth.rx_bytes);
1094         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1095                             I40E_GLPRT_UPRCL(hw->port),
1096                             pf->offset_loaded, &os->eth.rx_unicast,
1097                             &ns->eth.rx_unicast);
1098         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1099                             I40E_GLPRT_MPRCL(hw->port),
1100                             pf->offset_loaded, &os->eth.rx_multicast,
1101                             &ns->eth.rx_multicast);
1102         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1103                             I40E_GLPRT_BPRCL(hw->port),
1104                             pf->offset_loaded, &os->eth.rx_broadcast,
1105                             &ns->eth.rx_broadcast);
1106         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1107                             pf->offset_loaded, &os->eth.rx_discards,
1108                             &ns->eth.rx_discards);
1109         /* GLPRT_REPC not supported */
1110         /* GLPRT_RMPC not supported */
1111         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1112                             pf->offset_loaded,
1113                             &os->eth.rx_unknown_protocol,
1114                             &ns->eth.rx_unknown_protocol);
1115         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1116                             I40E_GLPRT_GOTCL(hw->port),
1117                             pf->offset_loaded, &os->eth.tx_bytes,
1118                             &ns->eth.tx_bytes);
1119         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1120                             I40E_GLPRT_UPTCL(hw->port),
1121                             pf->offset_loaded, &os->eth.tx_unicast,
1122                             &ns->eth.tx_unicast);
1123         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1124                             I40E_GLPRT_MPTCL(hw->port),
1125                             pf->offset_loaded, &os->eth.tx_multicast,
1126                             &ns->eth.tx_multicast);
1127         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1128                             I40E_GLPRT_BPTCL(hw->port),
1129                             pf->offset_loaded, &os->eth.tx_broadcast,
1130                             &ns->eth.tx_broadcast);
1131         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1132                             pf->offset_loaded, &os->eth.tx_discards,
1133                             &ns->eth.tx_discards);
1134         /* GLPRT_TEPC not supported */
1135
1136         /* additional port specific stats */
1137         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1138                             pf->offset_loaded, &os->tx_dropped_link_down,
1139                             &ns->tx_dropped_link_down);
1140         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1141                             pf->offset_loaded, &os->crc_errors,
1142                             &ns->crc_errors);
1143         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1144                             pf->offset_loaded, &os->illegal_bytes,
1145                             &ns->illegal_bytes);
1146         /* GLPRT_ERRBC not supported */
1147         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1148                             pf->offset_loaded, &os->mac_local_faults,
1149                             &ns->mac_local_faults);
1150         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1151                             pf->offset_loaded, &os->mac_remote_faults,
1152                             &ns->mac_remote_faults);
1153         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1154                             pf->offset_loaded, &os->rx_length_errors,
1155                             &ns->rx_length_errors);
1156         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1157                             pf->offset_loaded, &os->link_xon_rx,
1158                             &ns->link_xon_rx);
1159         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1160                             pf->offset_loaded, &os->link_xoff_rx,
1161                             &ns->link_xoff_rx);
1162         for (i = 0; i < 8; i++) {
1163                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1164                                     pf->offset_loaded,
1165                                     &os->priority_xon_rx[i],
1166                                     &ns->priority_xon_rx[i]);
1167                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1168                                     pf->offset_loaded,
1169                                     &os->priority_xoff_rx[i],
1170                                     &ns->priority_xoff_rx[i]);
1171         }
1172         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1173                             pf->offset_loaded, &os->link_xon_tx,
1174                             &ns->link_xon_tx);
1175         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1176                             pf->offset_loaded, &os->link_xoff_tx,
1177                             &ns->link_xoff_tx);
1178         for (i = 0; i < 8; i++) {
1179                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1180                                     pf->offset_loaded,
1181                                     &os->priority_xon_tx[i],
1182                                     &ns->priority_xon_tx[i]);
1183                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1184                                     pf->offset_loaded,
1185                                     &os->priority_xoff_tx[i],
1186                                     &ns->priority_xoff_tx[i]);
1187                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1188                                     pf->offset_loaded,
1189                                     &os->priority_xon_2_xoff[i],
1190                                     &ns->priority_xon_2_xoff[i]);
1191         }
1192         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1193                             I40E_GLPRT_PRC64L(hw->port),
1194                             pf->offset_loaded, &os->rx_size_64,
1195                             &ns->rx_size_64);
1196         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1197                             I40E_GLPRT_PRC127L(hw->port),
1198                             pf->offset_loaded, &os->rx_size_127,
1199                             &ns->rx_size_127);
1200         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1201                             I40E_GLPRT_PRC255L(hw->port),
1202                             pf->offset_loaded, &os->rx_size_255,
1203                             &ns->rx_size_255);
1204         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1205                             I40E_GLPRT_PRC511L(hw->port),
1206                             pf->offset_loaded, &os->rx_size_511,
1207                             &ns->rx_size_511);
1208         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1209                             I40E_GLPRT_PRC1023L(hw->port),
1210                             pf->offset_loaded, &os->rx_size_1023,
1211                             &ns->rx_size_1023);
1212         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1213                             I40E_GLPRT_PRC1522L(hw->port),
1214                             pf->offset_loaded, &os->rx_size_1522,
1215                             &ns->rx_size_1522);
1216         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1217                             I40E_GLPRT_PRC9522L(hw->port),
1218                             pf->offset_loaded, &os->rx_size_big,
1219                             &ns->rx_size_big);
1220         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1221                             pf->offset_loaded, &os->rx_undersize,
1222                             &ns->rx_undersize);
1223         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1224                             pf->offset_loaded, &os->rx_fragments,
1225                             &ns->rx_fragments);
1226         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1227                             pf->offset_loaded, &os->rx_oversize,
1228                             &ns->rx_oversize);
1229         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1230                             pf->offset_loaded, &os->rx_jabber,
1231                             &ns->rx_jabber);
1232         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1233                             I40E_GLPRT_PTC64L(hw->port),
1234                             pf->offset_loaded, &os->tx_size_64,
1235                             &ns->tx_size_64);
1236         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1237                             I40E_GLPRT_PTC127L(hw->port),
1238                             pf->offset_loaded, &os->tx_size_127,
1239                             &ns->tx_size_127);
1240         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1241                             I40E_GLPRT_PTC255L(hw->port),
1242                             pf->offset_loaded, &os->tx_size_255,
1243                             &ns->tx_size_255);
1244         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1245                             I40E_GLPRT_PTC511L(hw->port),
1246                             pf->offset_loaded, &os->tx_size_511,
1247                             &ns->tx_size_511);
1248         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1249                             I40E_GLPRT_PTC1023L(hw->port),
1250                             pf->offset_loaded, &os->tx_size_1023,
1251                             &ns->tx_size_1023);
1252         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1253                             I40E_GLPRT_PTC1522L(hw->port),
1254                             pf->offset_loaded, &os->tx_size_1522,
1255                             &ns->tx_size_1522);
1256         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1257                             I40E_GLPRT_PTC9522L(hw->port),
1258                             pf->offset_loaded, &os->tx_size_big,
1259                             &ns->tx_size_big);
1260         /* GLPRT_MSPDC not supported */
1261         /* GLPRT_XEC not supported */
1262
1263         pf->offset_loaded = true;
1264
1265         if (pf->main_vsi)
1266                 i40e_update_vsi_stats(pf->main_vsi);
1267
1268         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1269                                                 ns->eth.rx_broadcast;
1270         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1271                                                 ns->eth.tx_broadcast;
1272         stats->ibytes   = ns->eth.rx_bytes;
1273         stats->obytes   = ns->eth.tx_bytes;
1274         stats->oerrors  = ns->eth.tx_errors;
1275         stats->imcasts  = ns->eth.rx_multicast;
1276
1277         /* Rx Errors */
1278         stats->ibadcrc  = ns->crc_errors;
1279         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1280                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1281         stats->imissed  = ns->eth.rx_discards;
1282         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1283
1284         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1285         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1286         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1287         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1288         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1289         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1290         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1291                     ns->eth.rx_unknown_protocol);
1292         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1293         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1294         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1295         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1296         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1297         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1298
1299         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1300                     ns->tx_dropped_link_down);
1301         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1302         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1303                     ns->illegal_bytes);
1304         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1305         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1306                     ns->mac_local_faults);
1307         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1308                     ns->mac_remote_faults);
1309         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1310                     ns->rx_length_errors);
1311         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1312         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1313         for (i = 0; i < 8; i++) {
1314                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1315                                 i, ns->priority_xon_rx[i]);
1316                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1317                                 i, ns->priority_xoff_rx[i]);
1318         }
1319         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1320         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1321         for (i = 0; i < 8; i++) {
1322                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1323                                 i, ns->priority_xon_tx[i]);
1324                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1325                                 i, ns->priority_xoff_tx[i]);
1326                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1327                                 i, ns->priority_xon_2_xoff[i]);
1328         }
1329         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1330         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1331         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1332         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1333         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1334         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1335         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1336         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1337         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1338         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1339         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1340         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1341         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1342         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1343         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1344         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1345         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1346         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1347         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1348                         ns->mac_short_packet_dropped);
1349         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1350                     ns->checksum_error);
1351         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1352 }
1353
1354 /* Reset the statistics */
1355 static void
1356 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1357 {
1358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1359
1360         /* It results in reloading the start point of each counter */
1361         pf->offset_loaded = false;
1362 }
1363
1364 static int
1365 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1366                                  __rte_unused uint16_t queue_id,
1367                                  __rte_unused uint8_t stat_idx,
1368                                  __rte_unused uint8_t is_rx)
1369 {
1370         PMD_INIT_FUNC_TRACE();
1371
1372         return -ENOSYS;
1373 }
1374
1375 static void
1376 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1377 {
1378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1379         struct i40e_vsi *vsi = pf->main_vsi;
1380
1381         dev_info->max_rx_queues = vsi->nb_qps;
1382         dev_info->max_tx_queues = vsi->nb_qps;
1383         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1384         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1385         dev_info->max_mac_addrs = vsi->max_macaddrs;
1386         dev_info->max_vfs = dev->pci_dev->max_vfs;
1387         dev_info->rx_offload_capa =
1388                 DEV_RX_OFFLOAD_VLAN_STRIP |
1389                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1390                 DEV_RX_OFFLOAD_UDP_CKSUM |
1391                 DEV_RX_OFFLOAD_TCP_CKSUM;
1392         dev_info->tx_offload_capa =
1393                 DEV_TX_OFFLOAD_VLAN_INSERT |
1394                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1395                 DEV_TX_OFFLOAD_UDP_CKSUM |
1396                 DEV_TX_OFFLOAD_TCP_CKSUM |
1397                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1398
1399         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1400                 .rx_thresh = {
1401                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1402                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1403                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1404                 },
1405                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1406                 .rx_drop_en = 0,
1407         };
1408
1409         dev_info->default_txconf = (struct rte_eth_txconf) {
1410                 .tx_thresh = {
1411                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1412                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1413                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1414                 },
1415                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1416                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1417                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1418         };
1419
1420 }
1421
1422 static int
1423 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1424 {
1425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1426         struct i40e_vsi *vsi = pf->main_vsi;
1427         PMD_INIT_FUNC_TRACE();
1428
1429         if (on)
1430                 return i40e_vsi_add_vlan(vsi, vlan_id);
1431         else
1432                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1433 }
1434
1435 static void
1436 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1437                    __rte_unused uint16_t tpid)
1438 {
1439         PMD_INIT_FUNC_TRACE();
1440 }
1441
1442 static void
1443 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1444 {
1445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1446         struct i40e_vsi *vsi = pf->main_vsi;
1447
1448         if (mask & ETH_VLAN_STRIP_MASK) {
1449                 /* Enable or disable VLAN stripping */
1450                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1451                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1452                 else
1453                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1454         }
1455
1456         if (mask & ETH_VLAN_EXTEND_MASK) {
1457                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1458                         i40e_vsi_config_double_vlan(vsi, TRUE);
1459                 else
1460                         i40e_vsi_config_double_vlan(vsi, FALSE);
1461         }
1462 }
1463
1464 static void
1465 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1466                           __rte_unused uint16_t queue,
1467                           __rte_unused int on)
1468 {
1469         PMD_INIT_FUNC_TRACE();
1470 }
1471
1472 static int
1473 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1474 {
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_vsi *vsi = pf->main_vsi;
1477         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1478         struct i40e_vsi_vlan_pvid_info info;
1479
1480         memset(&info, 0, sizeof(info));
1481         info.on = on;
1482         if (info.on)
1483                 info.config.pvid = pvid;
1484         else {
1485                 info.config.reject.tagged =
1486                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1487                 info.config.reject.untagged =
1488                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1489         }
1490
1491         return i40e_vsi_vlan_pvid_set(vsi, &info);
1492 }
1493
1494 static int
1495 i40e_dev_led_on(struct rte_eth_dev *dev)
1496 {
1497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1498         uint32_t mode = i40e_led_get(hw);
1499
1500         if (mode == 0)
1501                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1502
1503         return 0;
1504 }
1505
1506 static int
1507 i40e_dev_led_off(struct rte_eth_dev *dev)
1508 {
1509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510         uint32_t mode = i40e_led_get(hw);
1511
1512         if (mode != 0)
1513                 i40e_led_set(hw, 0, false);
1514
1515         return 0;
1516 }
1517
1518 static int
1519 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1520                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1521 {
1522         PMD_INIT_FUNC_TRACE();
1523
1524         return -ENOSYS;
1525 }
1526
1527 static int
1528 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1529                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1530 {
1531         PMD_INIT_FUNC_TRACE();
1532
1533         return -ENOSYS;
1534 }
1535
1536 /* Add a MAC address, and update filters */
1537 static void
1538 i40e_macaddr_add(struct rte_eth_dev *dev,
1539                  struct ether_addr *mac_addr,
1540                  __attribute__((unused)) uint32_t index,
1541                  __attribute__((unused)) uint32_t pool)
1542 {
1543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1544         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1545         struct i40e_mac_filter_info mac_filter;
1546         struct i40e_vsi *vsi = pf->main_vsi;
1547         struct ether_addr old_mac;
1548         int ret;
1549
1550         if (!is_valid_assigned_ether_addr(mac_addr)) {
1551                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1552                 return;
1553         }
1554
1555         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1556                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1557                 return;
1558         }
1559
1560         /* Write mac address */
1561         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1562                                         mac_addr->addr_bytes, NULL);
1563         if (ret != I40E_SUCCESS) {
1564                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1565                 return;
1566         }
1567
1568         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1569         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1570                         ETHER_ADDR_LEN);
1571         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1572         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1573
1574         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1575         if (ret != I40E_SUCCESS) {
1576                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1577                 return;
1578         }
1579
1580         ether_addr_copy(mac_addr, &pf->dev_addr);
1581         i40e_vsi_delete_mac(vsi, &old_mac);
1582 }
1583
1584 /* Remove a MAC address, and update filters */
1585 static void
1586 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1587 {
1588         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1589         struct i40e_vsi *vsi = pf->main_vsi;
1590         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1591         struct ether_addr *macaddr;
1592         int ret;
1593         struct i40e_hw *hw =
1594                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595
1596         if (index >= vsi->max_macaddrs)
1597                 return;
1598
1599         macaddr = &(data->mac_addrs[index]);
1600         if (!is_valid_assigned_ether_addr(macaddr))
1601                 return;
1602
1603         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1604                                         hw->mac.perm_addr, NULL);
1605         if (ret != I40E_SUCCESS) {
1606                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1607                 return;
1608         }
1609
1610         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1611
1612         ret = i40e_vsi_delete_mac(vsi, macaddr);
1613         if (ret != I40E_SUCCESS)
1614                 return;
1615
1616         /* Clear device address as it has been removed */
1617         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1618                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1619 }
1620
1621 static int
1622 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1623                          struct rte_eth_rss_reta *reta_conf)
1624 {
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         uint32_t lut, l;
1627         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1628
1629         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1630                 if (i < max)
1631                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1632                 else
1633                         mask = (uint8_t)((reta_conf->mask_hi >>
1634                                                 (i - max)) & 0xF);
1635
1636                 if (!mask)
1637                         continue;
1638
1639                 if (mask == 0xF)
1640                         l = 0;
1641                 else
1642                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1643
1644                 for (j = 0, lut = 0; j < 4; j++) {
1645                         if (mask & (0x1 << j))
1646                                 lut |= reta_conf->reta[i + j] << (8 * j);
1647                         else
1648                                 lut |= l & (0xFF << (8 * j));
1649                 }
1650                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1651         }
1652
1653         return 0;
1654 }
1655
1656 static int
1657 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1658                         struct rte_eth_rss_reta *reta_conf)
1659 {
1660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         uint32_t lut;
1662         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1663
1664         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1665                 if (i < max)
1666                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1667                 else
1668                         mask = (uint8_t)((reta_conf->mask_hi >>
1669                                                 (i - max)) & 0xF);
1670
1671                 if (!mask)
1672                         continue;
1673
1674                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1675                 for (j = 0; j < 4; j++) {
1676                         if (mask & (0x1 << j))
1677                                 reta_conf->reta[i + j] =
1678                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1679                 }
1680         }
1681
1682         return 0;
1683 }
1684
1685 /**
1686  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1687  * @hw:   pointer to the HW structure
1688  * @mem:  pointer to mem struct to fill out
1689  * @size: size of memory requested
1690  * @alignment: what to align the allocation to
1691  **/
1692 enum i40e_status_code
1693 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1694                         struct i40e_dma_mem *mem,
1695                         u64 size,
1696                         u32 alignment)
1697 {
1698         static uint64_t id = 0;
1699         const struct rte_memzone *mz = NULL;
1700         char z_name[RTE_MEMZONE_NAMESIZE];
1701
1702         if (!mem)
1703                 return I40E_ERR_PARAM;
1704
1705         id++;
1706         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1707 #ifdef RTE_LIBRTE_XEN_DOM0
1708         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1709                                                         RTE_PGSIZE_2M);
1710 #else
1711         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1712 #endif
1713         if (!mz)
1714                 return I40E_ERR_NO_MEMORY;
1715
1716         mem->id = id;
1717         mem->size = size;
1718         mem->va = mz->addr;
1719 #ifdef RTE_LIBRTE_XEN_DOM0
1720         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1721 #else
1722         mem->pa = mz->phys_addr;
1723 #endif
1724
1725         return I40E_SUCCESS;
1726 }
1727
1728 /**
1729  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1730  * @hw:   pointer to the HW structure
1731  * @mem:  ptr to mem struct to free
1732  **/
1733 enum i40e_status_code
1734 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1735                     struct i40e_dma_mem *mem)
1736 {
1737         if (!mem || !mem->va)
1738                 return I40E_ERR_PARAM;
1739
1740         mem->va = NULL;
1741         mem->pa = (u64)0;
1742
1743         return I40E_SUCCESS;
1744 }
1745
1746 /**
1747  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1748  * @hw:   pointer to the HW structure
1749  * @mem:  pointer to mem struct to fill out
1750  * @size: size of memory requested
1751  **/
1752 enum i40e_status_code
1753 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1754                          struct i40e_virt_mem *mem,
1755                          u32 size)
1756 {
1757         if (!mem)
1758                 return I40E_ERR_PARAM;
1759
1760         mem->size = size;
1761         mem->va = rte_zmalloc("i40e", size, 0);
1762
1763         if (mem->va)
1764                 return I40E_SUCCESS;
1765         else
1766                 return I40E_ERR_NO_MEMORY;
1767 }
1768
1769 /**
1770  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1771  * @hw:   pointer to the HW structure
1772  * @mem:  pointer to mem struct to free
1773  **/
1774 enum i40e_status_code
1775 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1776                      struct i40e_virt_mem *mem)
1777 {
1778         if (!mem)
1779                 return I40E_ERR_PARAM;
1780
1781         rte_free(mem->va);
1782         mem->va = NULL;
1783
1784         return I40E_SUCCESS;
1785 }
1786
1787 void
1788 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1789 {
1790         rte_spinlock_init(&sp->spinlock);
1791 }
1792
1793 void
1794 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1795 {
1796         rte_spinlock_lock(&sp->spinlock);
1797 }
1798
1799 void
1800 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1801 {
1802         rte_spinlock_unlock(&sp->spinlock);
1803 }
1804
1805 void
1806 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1807 {
1808         return;
1809 }
1810
1811 /**
1812  * Get the hardware capabilities, which will be parsed
1813  * and saved into struct i40e_hw.
1814  */
1815 static int
1816 i40e_get_cap(struct i40e_hw *hw)
1817 {
1818         struct i40e_aqc_list_capabilities_element_resp *buf;
1819         uint16_t len, size = 0;
1820         int ret;
1821
1822         /* Calculate a huge enough buff for saving response data temporarily */
1823         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1824                                                 I40E_MAX_CAP_ELE_NUM;
1825         buf = rte_zmalloc("i40e", len, 0);
1826         if (!buf) {
1827                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1828                 return I40E_ERR_NO_MEMORY;
1829         }
1830
1831         /* Get, parse the capabilities and save it to hw */
1832         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1833                         i40e_aqc_opc_list_func_capabilities, NULL);
1834         if (ret != I40E_SUCCESS)
1835                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1836
1837         /* Free the temporary buffer after being used */
1838         rte_free(buf);
1839
1840         return ret;
1841 }
1842
1843 static int
1844 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1845 {
1846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1848         uint16_t sum_queues = 0, sum_vsis;
1849
1850         /* First check if FW support SRIOV */
1851         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1852                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1853                 return -EINVAL;
1854         }
1855
1856         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1857         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1858         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1859         /* Allocate queues for pf */
1860         if (hw->func_caps.rss) {
1861                 pf->flags |= I40E_FLAG_RSS;
1862                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1863                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1864                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1865         } else
1866                 pf->lan_nb_qps = 1;
1867         sum_queues = pf->lan_nb_qps;
1868         /* Default VSI is not counted in */
1869         sum_vsis = 0;
1870         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1871
1872         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1873                 pf->flags |= I40E_FLAG_SRIOV;
1874                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1875                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1876                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1877                                      "max supported %u.",
1878                                      dev->pci_dev->max_vfs,
1879                                      hw->func_caps.num_vfs);
1880                         return -EINVAL;
1881                 }
1882                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1883                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1884                                      "max support %u queues.",
1885                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1886                         return -EINVAL;
1887                 }
1888                 pf->vf_num = dev->pci_dev->max_vfs;
1889                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1890                 sum_vsis   += pf->vf_num;
1891                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1892                              pf->vf_num, pf->vf_nb_qps);
1893         } else
1894                 pf->vf_num = 0;
1895
1896         if (hw->func_caps.vmdq) {
1897                 pf->flags |= I40E_FLAG_VMDQ;
1898                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1899                 sum_queues += pf->vmdq_nb_qps;
1900                 sum_vsis += 1;
1901                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1902         }
1903
1904         if (hw->func_caps.fd) {
1905                 pf->flags |= I40E_FLAG_FDIR;
1906                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1907                 /**
1908                  * Each flow director consumes one VSI and one queue,
1909                  * but can't calculate out predictably here.
1910                  */
1911         }
1912
1913         if (sum_vsis > pf->max_num_vsi ||
1914                 sum_queues > hw->func_caps.num_rx_qp) {
1915                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1916                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1917                              pf->max_num_vsi, sum_vsis);
1918                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1919                              hw->func_caps.num_rx_qp, sum_queues);
1920                 return -EINVAL;
1921         }
1922
1923         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1924          * cause */
1925         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1926                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1927                              sum_vsis, hw->func_caps.num_msix_vectors);
1928                 return -EINVAL;
1929         }
1930         return I40E_SUCCESS;
1931 }
1932
1933 static int
1934 i40e_pf_get_switch_config(struct i40e_pf *pf)
1935 {
1936         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1937         struct i40e_aqc_get_switch_config_resp *switch_config;
1938         struct i40e_aqc_switch_config_element_resp *element;
1939         uint16_t start_seid = 0, num_reported;
1940         int ret;
1941
1942         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1943                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1944         if (!switch_config) {
1945                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1946                 return -ENOMEM;
1947         }
1948
1949         /* Get the switch configurations */
1950         ret = i40e_aq_get_switch_config(hw, switch_config,
1951                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1952         if (ret != I40E_SUCCESS) {
1953                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1954                 goto fail;
1955         }
1956         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1957         if (num_reported != 1) { /* The number should be 1 */
1958                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1959                 goto fail;
1960         }
1961
1962         /* Parse the switch configuration elements */
1963         element = &(switch_config->element[0]);
1964         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1965                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1966                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1967         } else
1968                 PMD_DRV_LOG(INFO, "Unknown element type");
1969
1970 fail:
1971         rte_free(switch_config);
1972
1973         return ret;
1974 }
1975
1976 static int
1977 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1978                         uint32_t num)
1979 {
1980         struct pool_entry *entry;
1981
1982         if (pool == NULL || num == 0)
1983                 return -EINVAL;
1984
1985         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1986         if (entry == NULL) {
1987                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1988                 return -ENOMEM;
1989         }
1990
1991         /* queue heap initialize */
1992         pool->num_free = num;
1993         pool->num_alloc = 0;
1994         pool->base = base;
1995         LIST_INIT(&pool->alloc_list);
1996         LIST_INIT(&pool->free_list);
1997
1998         /* Initialize element  */
1999         entry->base = 0;
2000         entry->len = num;
2001
2002         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2003         return 0;
2004 }
2005
2006 static void
2007 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2008 {
2009         struct pool_entry *entry;
2010
2011         if (pool == NULL)
2012                 return;
2013
2014         LIST_FOREACH(entry, &pool->alloc_list, next) {
2015                 LIST_REMOVE(entry, next);
2016                 rte_free(entry);
2017         }
2018
2019         LIST_FOREACH(entry, &pool->free_list, next) {
2020                 LIST_REMOVE(entry, next);
2021                 rte_free(entry);
2022         }
2023
2024         pool->num_free = 0;
2025         pool->num_alloc = 0;
2026         pool->base = 0;
2027         LIST_INIT(&pool->alloc_list);
2028         LIST_INIT(&pool->free_list);
2029 }
2030
2031 static int
2032 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2033                        uint32_t base)
2034 {
2035         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2036         uint32_t pool_offset;
2037         int insert;
2038
2039         if (pool == NULL) {
2040                 PMD_DRV_LOG(ERR, "Invalid parameter");
2041                 return -EINVAL;
2042         }
2043
2044         pool_offset = base - pool->base;
2045         /* Lookup in alloc list */
2046         LIST_FOREACH(entry, &pool->alloc_list, next) {
2047                 if (entry->base == pool_offset) {
2048                         valid_entry = entry;
2049                         LIST_REMOVE(entry, next);
2050                         break;
2051                 }
2052         }
2053
2054         /* Not find, return */
2055         if (valid_entry == NULL) {
2056                 PMD_DRV_LOG(ERR, "Failed to find entry");
2057                 return -EINVAL;
2058         }
2059
2060         /**
2061          * Found it, move it to free list  and try to merge.
2062          * In order to make merge easier, always sort it by qbase.
2063          * Find adjacent prev and last entries.
2064          */
2065         prev = next = NULL;
2066         LIST_FOREACH(entry, &pool->free_list, next) {
2067                 if (entry->base > valid_entry->base) {
2068                         next = entry;
2069                         break;
2070                 }
2071                 prev = entry;
2072         }
2073
2074         insert = 0;
2075         /* Try to merge with next one*/
2076         if (next != NULL) {
2077                 /* Merge with next one */
2078                 if (valid_entry->base + valid_entry->len == next->base) {
2079                         next->base = valid_entry->base;
2080                         next->len += valid_entry->len;
2081                         rte_free(valid_entry);
2082                         valid_entry = next;
2083                         insert = 1;
2084                 }
2085         }
2086
2087         if (prev != NULL) {
2088                 /* Merge with previous one */
2089                 if (prev->base + prev->len == valid_entry->base) {
2090                         prev->len += valid_entry->len;
2091                         /* If it merge with next one, remove next node */
2092                         if (insert == 1) {
2093                                 LIST_REMOVE(valid_entry, next);
2094                                 rte_free(valid_entry);
2095                         } else {
2096                                 rte_free(valid_entry);
2097                                 insert = 1;
2098                         }
2099                 }
2100         }
2101
2102         /* Not find any entry to merge, insert */
2103         if (insert == 0) {
2104                 if (prev != NULL)
2105                         LIST_INSERT_AFTER(prev, valid_entry, next);
2106                 else if (next != NULL)
2107                         LIST_INSERT_BEFORE(next, valid_entry, next);
2108                 else /* It's empty list, insert to head */
2109                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2110         }
2111
2112         pool->num_free += valid_entry->len;
2113         pool->num_alloc -= valid_entry->len;
2114
2115         return 0;
2116 }
2117
2118 static int
2119 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2120                        uint16_t num)
2121 {
2122         struct pool_entry *entry, *valid_entry;
2123
2124         if (pool == NULL || num == 0) {
2125                 PMD_DRV_LOG(ERR, "Invalid parameter");
2126                 return -EINVAL;
2127         }
2128
2129         if (pool->num_free < num) {
2130                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2131                             num, pool->num_free);
2132                 return -ENOMEM;
2133         }
2134
2135         valid_entry = NULL;
2136         /* Lookup  in free list and find most fit one */
2137         LIST_FOREACH(entry, &pool->free_list, next) {
2138                 if (entry->len >= num) {
2139                         /* Find best one */
2140                         if (entry->len == num) {
2141                                 valid_entry = entry;
2142                                 break;
2143                         }
2144                         if (valid_entry == NULL || valid_entry->len > entry->len)
2145                                 valid_entry = entry;
2146                 }
2147         }
2148
2149         /* Not find one to satisfy the request, return */
2150         if (valid_entry == NULL) {
2151                 PMD_DRV_LOG(ERR, "No valid entry found");
2152                 return -ENOMEM;
2153         }
2154         /**
2155          * The entry have equal queue number as requested,
2156          * remove it from alloc_list.
2157          */
2158         if (valid_entry->len == num) {
2159                 LIST_REMOVE(valid_entry, next);
2160         } else {
2161                 /**
2162                  * The entry have more numbers than requested,
2163                  * create a new entry for alloc_list and minus its
2164                  * queue base and number in free_list.
2165                  */
2166                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2167                 if (entry == NULL) {
2168                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2169                                     "resource pool");
2170                         return -ENOMEM;
2171                 }
2172                 entry->base = valid_entry->base;
2173                 entry->len = num;
2174                 valid_entry->base += num;
2175                 valid_entry->len -= num;
2176                 valid_entry = entry;
2177         }
2178
2179         /* Insert it into alloc list, not sorted */
2180         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2181
2182         pool->num_free -= valid_entry->len;
2183         pool->num_alloc += valid_entry->len;
2184
2185         return (valid_entry->base + pool->base);
2186 }
2187
2188 /**
2189  * bitmap_is_subset - Check whether src2 is subset of src1
2190  **/
2191 static inline int
2192 bitmap_is_subset(uint8_t src1, uint8_t src2)
2193 {
2194         return !((src1 ^ src2) & src2);
2195 }
2196
2197 static int
2198 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2199 {
2200         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2201
2202         /* If DCB is not supported, only default TC is supported */
2203         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2204                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2205                 return -EINVAL;
2206         }
2207
2208         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2209                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2210                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2211                             enabled_tcmap);
2212                 return -EINVAL;
2213         }
2214         return I40E_SUCCESS;
2215 }
2216
2217 int
2218 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2219                                 struct i40e_vsi_vlan_pvid_info *info)
2220 {
2221         struct i40e_hw *hw;
2222         struct i40e_vsi_context ctxt;
2223         uint8_t vlan_flags = 0;
2224         int ret;
2225
2226         if (vsi == NULL || info == NULL) {
2227                 PMD_DRV_LOG(ERR, "invalid parameters");
2228                 return I40E_ERR_PARAM;
2229         }
2230
2231         if (info->on) {
2232                 vsi->info.pvid = info->config.pvid;
2233                 /**
2234                  * If insert pvid is enabled, only tagged pkts are
2235                  * allowed to be sent out.
2236                  */
2237                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2238                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2239         } else {
2240                 vsi->info.pvid = 0;
2241                 if (info->config.reject.tagged == 0)
2242                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2243
2244                 if (info->config.reject.untagged == 0)
2245                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2246         }
2247         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2248                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2249         vsi->info.port_vlan_flags |= vlan_flags;
2250         vsi->info.valid_sections =
2251                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2252         memset(&ctxt, 0, sizeof(ctxt));
2253         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2254         ctxt.seid = vsi->seid;
2255
2256         hw = I40E_VSI_TO_HW(vsi);
2257         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2258         if (ret != I40E_SUCCESS)
2259                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2260
2261         return ret;
2262 }
2263
2264 static int
2265 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2266 {
2267         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2268         int i, ret;
2269         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2270
2271         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2272         if (ret != I40E_SUCCESS)
2273                 return ret;
2274
2275         if (!vsi->seid) {
2276                 PMD_DRV_LOG(ERR, "seid not valid");
2277                 return -EINVAL;
2278         }
2279
2280         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2281         tc_bw_data.tc_valid_bits = enabled_tcmap;
2282         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2283                 tc_bw_data.tc_bw_credits[i] =
2284                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2285
2286         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2287         if (ret != I40E_SUCCESS) {
2288                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2289                 return ret;
2290         }
2291
2292         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2293                                         sizeof(vsi->info.qs_handle));
2294         return I40E_SUCCESS;
2295 }
2296
2297 static int
2298 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2299                                  struct i40e_aqc_vsi_properties_data *info,
2300                                  uint8_t enabled_tcmap)
2301 {
2302         int ret, total_tc = 0, i;
2303         uint16_t qpnum_per_tc, bsf, qp_idx;
2304
2305         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2306         if (ret != I40E_SUCCESS)
2307                 return ret;
2308
2309         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2310                 if (enabled_tcmap & (1 << i))
2311                         total_tc++;
2312         vsi->enabled_tc = enabled_tcmap;
2313
2314         /* Number of queues per enabled TC */
2315         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2316         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2317         bsf = rte_bsf32(qpnum_per_tc);
2318
2319         /* Adjust the queue number to actual queues that can be applied */
2320         vsi->nb_qps = qpnum_per_tc * total_tc;
2321
2322         /**
2323          * Configure TC and queue mapping parameters, for enabled TC,
2324          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2325          * default queue will serve it.
2326          */
2327         qp_idx = 0;
2328         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2329                 if (vsi->enabled_tc & (1 << i)) {
2330                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2331                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2332                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2333                         qp_idx += qpnum_per_tc;
2334                 } else
2335                         info->tc_mapping[i] = 0;
2336         }
2337
2338         /* Associate queue number with VSI */
2339         if (vsi->type == I40E_VSI_SRIOV) {
2340                 info->mapping_flags |=
2341                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2342                 for (i = 0; i < vsi->nb_qps; i++)
2343                         info->queue_mapping[i] =
2344                                 rte_cpu_to_le_16(vsi->base_queue + i);
2345         } else {
2346                 info->mapping_flags |=
2347                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2348                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2349         }
2350         info->valid_sections =
2351                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2352
2353         return I40E_SUCCESS;
2354 }
2355
2356 static int
2357 i40e_veb_release(struct i40e_veb *veb)
2358 {
2359         struct i40e_vsi *vsi;
2360         struct i40e_hw *hw;
2361
2362         if (veb == NULL || veb->associate_vsi == NULL)
2363                 return -EINVAL;
2364
2365         if (!TAILQ_EMPTY(&veb->head)) {
2366                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2367                 return -EACCES;
2368         }
2369
2370         vsi = veb->associate_vsi;
2371         hw = I40E_VSI_TO_HW(vsi);
2372
2373         vsi->uplink_seid = veb->uplink_seid;
2374         i40e_aq_delete_element(hw, veb->seid, NULL);
2375         rte_free(veb);
2376         vsi->veb = NULL;
2377         return I40E_SUCCESS;
2378 }
2379
2380 /* Setup a veb */
2381 static struct i40e_veb *
2382 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2383 {
2384         struct i40e_veb *veb;
2385         int ret;
2386         struct i40e_hw *hw;
2387
2388         if (NULL == pf || vsi == NULL) {
2389                 PMD_DRV_LOG(ERR, "veb setup failed, "
2390                             "associated VSI shouldn't null");
2391                 return NULL;
2392         }
2393         hw = I40E_PF_TO_HW(pf);
2394
2395         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2396         if (!veb) {
2397                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2398                 goto fail;
2399         }
2400
2401         veb->associate_vsi = vsi;
2402         TAILQ_INIT(&veb->head);
2403         veb->uplink_seid = vsi->uplink_seid;
2404
2405         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2406                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2407
2408         if (ret != I40E_SUCCESS) {
2409                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2410                             hw->aq.asq_last_status);
2411                 goto fail;
2412         }
2413
2414         /* get statistics index */
2415         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2416                                 &veb->stats_idx, NULL, NULL, NULL);
2417         if (ret != I40E_SUCCESS) {
2418                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2419                             hw->aq.asq_last_status);
2420                 goto fail;
2421         }
2422
2423         /* Get VEB bandwidth, to be implemented */
2424         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2425         vsi->uplink_seid = veb->seid;
2426
2427         return veb;
2428 fail:
2429         rte_free(veb);
2430         return NULL;
2431 }
2432
2433 int
2434 i40e_vsi_release(struct i40e_vsi *vsi)
2435 {
2436         struct i40e_pf *pf;
2437         struct i40e_hw *hw;
2438         struct i40e_vsi_list *vsi_list;
2439         int ret;
2440         struct i40e_mac_filter *f;
2441
2442         if (!vsi)
2443                 return I40E_SUCCESS;
2444
2445         pf = I40E_VSI_TO_PF(vsi);
2446         hw = I40E_VSI_TO_HW(vsi);
2447
2448         /* VSI has child to attach, release child first */
2449         if (vsi->veb) {
2450                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2451                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2452                                 return -1;
2453                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2454                 }
2455                 i40e_veb_release(vsi->veb);
2456         }
2457
2458         /* Remove all macvlan filters of the VSI */
2459         i40e_vsi_remove_all_macvlan_filter(vsi);
2460         TAILQ_FOREACH(f, &vsi->mac_list, next)
2461                 rte_free(f);
2462
2463         if (vsi->type != I40E_VSI_MAIN) {
2464                 /* Remove vsi from parent's sibling list */
2465                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2466                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2467                         return I40E_ERR_PARAM;
2468                 }
2469                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2470                                 &vsi->sib_vsi_list, list);
2471
2472                 /* Remove all switch element of the VSI */
2473                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2474                 if (ret != I40E_SUCCESS)
2475                         PMD_DRV_LOG(ERR, "Failed to delete element");
2476         }
2477         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2478
2479         if (vsi->type != I40E_VSI_SRIOV)
2480                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2481         rte_free(vsi);
2482
2483         return I40E_SUCCESS;
2484 }
2485
2486 static int
2487 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2488 {
2489         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2490         struct i40e_aqc_remove_macvlan_element_data def_filter;
2491         struct i40e_mac_filter_info filter;
2492         int ret;
2493
2494         if (vsi->type != I40E_VSI_MAIN)
2495                 return I40E_ERR_CONFIG;
2496         memset(&def_filter, 0, sizeof(def_filter));
2497         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2498                                         ETH_ADDR_LEN);
2499         def_filter.vlan_tag = 0;
2500         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2501                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2502         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2503         if (ret != I40E_SUCCESS) {
2504                 struct i40e_mac_filter *f;
2505                 struct ether_addr *mac;
2506
2507                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2508                             "macvlan filter");
2509                 /* It needs to add the permanent mac into mac list */
2510                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2511                 if (f == NULL) {
2512                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2513                         return I40E_ERR_NO_MEMORY;
2514                 }
2515                 mac = &f->mac_info.mac_addr;
2516                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2517                                 ETH_ADDR_LEN);
2518                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2519                 vsi->mac_num++;
2520
2521                 return ret;
2522         }
2523         (void)rte_memcpy(&filter.mac_addr,
2524                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2525         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2526         return i40e_vsi_add_mac(vsi, &filter);
2527 }
2528
2529 static int
2530 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2531 {
2532         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2533         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2534         struct i40e_hw *hw = &vsi->adapter->hw;
2535         i40e_status ret;
2536         int i;
2537
2538         memset(&bw_config, 0, sizeof(bw_config));
2539         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2540         if (ret != I40E_SUCCESS) {
2541                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2542                             hw->aq.asq_last_status);
2543                 return ret;
2544         }
2545
2546         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2547         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2548                                         &ets_sla_config, NULL);
2549         if (ret != I40E_SUCCESS) {
2550                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2551                             "configuration %u", hw->aq.asq_last_status);
2552                 return ret;
2553         }
2554
2555         /* Not store the info yet, just print out */
2556         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2557         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2558         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2559                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2560                             ets_sla_config.share_credits[i]);
2561                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2562                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2563                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2564                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2565                             (i * 4));
2566         }
2567
2568         return 0;
2569 }
2570
2571 /* Setup a VSI */
2572 struct i40e_vsi *
2573 i40e_vsi_setup(struct i40e_pf *pf,
2574                enum i40e_vsi_type type,
2575                struct i40e_vsi *uplink_vsi,
2576                uint16_t user_param)
2577 {
2578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2579         struct i40e_vsi *vsi;
2580         struct i40e_mac_filter_info filter;
2581         int ret;
2582         struct i40e_vsi_context ctxt;
2583         struct ether_addr broadcast =
2584                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2585
2586         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2587                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2588                             "VSI link shouldn't be NULL");
2589                 return NULL;
2590         }
2591
2592         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2593                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2594                             "uplink VSI should be NULL");
2595                 return NULL;
2596         }
2597
2598         /* If uplink vsi didn't setup VEB, create one first */
2599         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2600                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2601
2602                 if (NULL == uplink_vsi->veb) {
2603                         PMD_DRV_LOG(ERR, "VEB setup failed");
2604                         return NULL;
2605                 }
2606         }
2607
2608         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2609         if (!vsi) {
2610                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2611                 return NULL;
2612         }
2613         TAILQ_INIT(&vsi->mac_list);
2614         vsi->type = type;
2615         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2616         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2617         vsi->parent_vsi = uplink_vsi;
2618         vsi->user_param = user_param;
2619         /* Allocate queues */
2620         switch (vsi->type) {
2621         case I40E_VSI_MAIN  :
2622                 vsi->nb_qps = pf->lan_nb_qps;
2623                 break;
2624         case I40E_VSI_SRIOV :
2625                 vsi->nb_qps = pf->vf_nb_qps;
2626                 break;
2627         default:
2628                 goto fail_mem;
2629         }
2630         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2631         if (ret < 0) {
2632                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2633                                 vsi->seid, ret);
2634                 goto fail_mem;
2635         }
2636         vsi->base_queue = ret;
2637
2638         /* VF has MSIX interrupt in VF range, don't allocate here */
2639         if (type != I40E_VSI_SRIOV) {
2640                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2641                 if (ret < 0) {
2642                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2643                         goto fail_queue_alloc;
2644                 }
2645                 vsi->msix_intr = ret;
2646         } else
2647                 vsi->msix_intr = 0;
2648         /* Add VSI */
2649         if (type == I40E_VSI_MAIN) {
2650                 /* For main VSI, no need to add since it's default one */
2651                 vsi->uplink_seid = pf->mac_seid;
2652                 vsi->seid = pf->main_vsi_seid;
2653                 /* Bind queues with specific MSIX interrupt */
2654                 /**
2655                  * Needs 2 interrupt at least, one for misc cause which will
2656                  * enabled from OS side, Another for queues binding the
2657                  * interrupt from device side only.
2658                  */
2659
2660                 /* Get default VSI parameters from hardware */
2661                 memset(&ctxt, 0, sizeof(ctxt));
2662                 ctxt.seid = vsi->seid;
2663                 ctxt.pf_num = hw->pf_id;
2664                 ctxt.uplink_seid = vsi->uplink_seid;
2665                 ctxt.vf_num = 0;
2666                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2667                 if (ret != I40E_SUCCESS) {
2668                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2669                         goto fail_msix_alloc;
2670                 }
2671                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2672                         sizeof(struct i40e_aqc_vsi_properties_data));
2673                 vsi->vsi_id = ctxt.vsi_number;
2674                 vsi->info.valid_sections = 0;
2675
2676                 /* Configure tc, enabled TC0 only */
2677                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2678                         I40E_SUCCESS) {
2679                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2680                         goto fail_msix_alloc;
2681                 }
2682
2683                 /* TC, queue mapping */
2684                 memset(&ctxt, 0, sizeof(ctxt));
2685                 vsi->info.valid_sections |=
2686                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2687                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2688                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2689                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2690                         sizeof(struct i40e_aqc_vsi_properties_data));
2691                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2692                                                 I40E_DEFAULT_TCMAP);
2693                 if (ret != I40E_SUCCESS) {
2694                         PMD_DRV_LOG(ERR, "Failed to configure "
2695                                     "TC queue mapping");
2696                         goto fail_msix_alloc;
2697                 }
2698                 ctxt.seid = vsi->seid;
2699                 ctxt.pf_num = hw->pf_id;
2700                 ctxt.uplink_seid = vsi->uplink_seid;
2701                 ctxt.vf_num = 0;
2702
2703                 /* Update VSI parameters */
2704                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2705                 if (ret != I40E_SUCCESS) {
2706                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2707                         goto fail_msix_alloc;
2708                 }
2709
2710                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2711                                                 sizeof(vsi->info.tc_mapping));
2712                 (void)rte_memcpy(&vsi->info.queue_mapping,
2713                                 &ctxt.info.queue_mapping,
2714                         sizeof(vsi->info.queue_mapping));
2715                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2716                 vsi->info.valid_sections = 0;
2717
2718                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2719                                 ETH_ADDR_LEN);
2720
2721                 /**
2722                  * Updating default filter settings are necessary to prevent
2723                  * reception of tagged packets.
2724                  * Some old firmware configurations load a default macvlan
2725                  * filter which accepts both tagged and untagged packets.
2726                  * The updating is to use a normal filter instead if needed.
2727                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2728                  * The firmware with correct configurations load the default
2729                  * macvlan filter which is expected and cannot be removed.
2730                  */
2731                 i40e_update_default_filter_setting(vsi);
2732         } else if (type == I40E_VSI_SRIOV) {
2733                 memset(&ctxt, 0, sizeof(ctxt));
2734                 /**
2735                  * For other VSI, the uplink_seid equals to uplink VSI's
2736                  * uplink_seid since they share same VEB
2737                  */
2738                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2739                 ctxt.pf_num = hw->pf_id;
2740                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2741                 ctxt.uplink_seid = vsi->uplink_seid;
2742                 ctxt.connection_type = 0x1;
2743                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2744
2745                 /* Configure switch ID */
2746                 ctxt.info.valid_sections |=
2747                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2748                 ctxt.info.switch_id =
2749                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2750                 /* Configure port/vlan */
2751                 ctxt.info.valid_sections |=
2752                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2753                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2754                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2755                                                 I40E_DEFAULT_TCMAP);
2756                 if (ret != I40E_SUCCESS) {
2757                         PMD_DRV_LOG(ERR, "Failed to configure "
2758                                     "TC queue mapping");
2759                         goto fail_msix_alloc;
2760                 }
2761                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2762                 ctxt.info.valid_sections |=
2763                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2764                 /**
2765                  * Since VSI is not created yet, only configure parameter,
2766                  * will add vsi below.
2767                  */
2768         }
2769         else {
2770                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2771                 goto fail_msix_alloc;
2772         }
2773
2774         if (vsi->type != I40E_VSI_MAIN) {
2775                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2776                 if (ret) {
2777                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2778                                     hw->aq.asq_last_status);
2779                         goto fail_msix_alloc;
2780                 }
2781                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2782                 vsi->info.valid_sections = 0;
2783                 vsi->seid = ctxt.seid;
2784                 vsi->vsi_id = ctxt.vsi_number;
2785                 vsi->sib_vsi_list.vsi = vsi;
2786                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2787                                 &vsi->sib_vsi_list, list);
2788         }
2789
2790         /* MAC/VLAN configuration */
2791         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
2792         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2793
2794         ret = i40e_vsi_add_mac(vsi, &filter);
2795         if (ret != I40E_SUCCESS) {
2796                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2797                 goto fail_msix_alloc;
2798         }
2799
2800         /* Get VSI BW information */
2801         i40e_vsi_dump_bw_config(vsi);
2802         return vsi;
2803 fail_msix_alloc:
2804         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2805 fail_queue_alloc:
2806         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2807 fail_mem:
2808         rte_free(vsi);
2809         return NULL;
2810 }
2811
2812 /* Configure vlan stripping on or off */
2813 int
2814 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2815 {
2816         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2817         struct i40e_vsi_context ctxt;
2818         uint8_t vlan_flags;
2819         int ret = I40E_SUCCESS;
2820
2821         /* Check if it has been already on or off */
2822         if (vsi->info.valid_sections &
2823                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2824                 if (on) {
2825                         if ((vsi->info.port_vlan_flags &
2826                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2827                                 return 0; /* already on */
2828                 } else {
2829                         if ((vsi->info.port_vlan_flags &
2830                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2831                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2832                                 return 0; /* already off */
2833                 }
2834         }
2835
2836         if (on)
2837                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2838         else
2839                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2840         vsi->info.valid_sections =
2841                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2842         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2843         vsi->info.port_vlan_flags |= vlan_flags;
2844         ctxt.seid = vsi->seid;
2845         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2846         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2847         if (ret)
2848                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2849                             on ? "enable" : "disable");
2850
2851         return ret;
2852 }
2853
2854 static int
2855 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2856 {
2857         struct rte_eth_dev_data *data = dev->data;
2858         int ret;
2859
2860         /* Apply vlan offload setting */
2861         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2862
2863         /* Apply double-vlan setting, not implemented yet */
2864
2865         /* Apply pvid setting */
2866         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2867                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2868         if (ret)
2869                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2870
2871         return ret;
2872 }
2873
2874 static int
2875 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2876 {
2877         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2878
2879         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2880 }
2881
2882 static int
2883 i40e_update_flow_control(struct i40e_hw *hw)
2884 {
2885 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2886         struct i40e_link_status link_status;
2887         uint32_t rxfc = 0, txfc = 0, reg;
2888         uint8_t an_info;
2889         int ret;
2890
2891         memset(&link_status, 0, sizeof(link_status));
2892         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2893         if (ret != I40E_SUCCESS) {
2894                 PMD_DRV_LOG(ERR, "Failed to get link status information");
2895                 goto write_reg; /* Disable flow control */
2896         }
2897
2898         an_info = hw->phy.link_info.an_info;
2899         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2900                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2901                 ret = I40E_ERR_NOT_READY;
2902                 goto write_reg; /* Disable flow control */
2903         }
2904         /**
2905          * If link auto negotiation is enabled, flow control needs to
2906          * be configured according to it
2907          */
2908         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2909         case I40E_LINK_PAUSE_RXTX:
2910                 rxfc = 1;
2911                 txfc = 1;
2912                 hw->fc.current_mode = I40E_FC_FULL;
2913                 break;
2914         case I40E_AQ_LINK_PAUSE_RX:
2915                 rxfc = 1;
2916                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2917                 break;
2918         case I40E_AQ_LINK_PAUSE_TX:
2919                 txfc = 1;
2920                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2921                 break;
2922         default:
2923                 hw->fc.current_mode = I40E_FC_NONE;
2924                 break;
2925         }
2926
2927 write_reg:
2928         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2929                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2930         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2931         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2932         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2933         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2934
2935         return ret;
2936 }
2937
2938 /* PF setup */
2939 static int
2940 i40e_pf_setup(struct i40e_pf *pf)
2941 {
2942         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2943         struct i40e_filter_control_settings settings;
2944         struct rte_eth_dev_data *dev_data = pf->dev_data;
2945         struct i40e_vsi *vsi;
2946         int ret;
2947
2948         /* Clear all stats counters */
2949         pf->offset_loaded = FALSE;
2950         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2951         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2952
2953         ret = i40e_pf_get_switch_config(pf);
2954         if (ret != I40E_SUCCESS) {
2955                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2956                 return ret;
2957         }
2958
2959         /* VSI setup */
2960         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2961         if (!vsi) {
2962                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2963                 return I40E_ERR_NOT_READY;
2964         }
2965         pf->main_vsi = vsi;
2966         dev_data->nb_rx_queues = vsi->nb_qps;
2967         dev_data->nb_tx_queues = vsi->nb_qps;
2968
2969         /* Configure filter control */
2970         memset(&settings, 0, sizeof(settings));
2971         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2972         /* Enable ethtype and macvlan filters */
2973         settings.enable_ethtype = TRUE;
2974         settings.enable_macvlan = TRUE;
2975         ret = i40e_set_filter_control(hw, &settings);
2976         if (ret)
2977                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2978                                                                 ret);
2979
2980         /* Update flow control according to the auto negotiation */
2981         i40e_update_flow_control(hw);
2982
2983         return I40E_SUCCESS;
2984 }
2985
2986 int
2987 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2988 {
2989         uint32_t reg;
2990         uint16_t j;
2991
2992         /**
2993          * Set or clear TX Queue Disable flags,
2994          * which is required by hardware.
2995          */
2996         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2997         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2998
2999         /* Wait until the request is finished */
3000         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3001                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3002                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3003                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3004                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3005                                                         & 0x1))) {
3006                         break;
3007                 }
3008         }
3009         if (on) {
3010                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3011                         return I40E_SUCCESS; /* already on, skip next steps */
3012
3013                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3014                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3015         } else {
3016                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3017                         return I40E_SUCCESS; /* already off, skip next steps */
3018                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3019         }
3020         /* Write the register */
3021         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3022         /* Check the result */
3023         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3024                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3025                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3026                 if (on) {
3027                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3028                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3029                                 break;
3030                 } else {
3031                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3032                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3033                                 break;
3034                 }
3035         }
3036         /* Check if it is timeout */
3037         if (j >= I40E_CHK_Q_ENA_COUNT) {
3038                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3039                             (on ? "enable" : "disable"), q_idx);
3040                 return I40E_ERR_TIMEOUT;
3041         }
3042
3043         return I40E_SUCCESS;
3044 }
3045
3046 /* Swith on or off the tx queues */
3047 static int
3048 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3049 {
3050         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3051         struct i40e_tx_queue *txq;
3052         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3053         uint16_t i;
3054         int ret;
3055
3056         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3057                 txq = dev_data->tx_queues[i];
3058                 /* Don't operate the queue if not configured or
3059                  * if starting only per queue */
3060                 if (!txq->q_set || (on && txq->tx_deferred_start))
3061                         continue;
3062                 if (on)
3063                         ret = i40e_dev_tx_queue_start(dev, i);
3064                 else
3065                         ret = i40e_dev_tx_queue_stop(dev, i);
3066                 if ( ret != I40E_SUCCESS)
3067                         return ret;
3068         }
3069
3070         return I40E_SUCCESS;
3071 }
3072
3073 int
3074 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3075 {
3076         uint32_t reg;
3077         uint16_t j;
3078
3079         /* Wait until the request is finished */
3080         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3081                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3082                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3083                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3084                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3085                         break;
3086         }
3087
3088         if (on) {
3089                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3090                         return I40E_SUCCESS; /* Already on, skip next steps */
3091                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3092         } else {
3093                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3094                         return I40E_SUCCESS; /* Already off, skip next steps */
3095                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3096         }
3097
3098         /* Write the register */
3099         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3100         /* Check the result */
3101         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3102                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3103                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3104                 if (on) {
3105                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3106                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3107                                 break;
3108                 } else {
3109                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3110                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3111                                 break;
3112                 }
3113         }
3114
3115         /* Check if it is timeout */
3116         if (j >= I40E_CHK_Q_ENA_COUNT) {
3117                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3118                             (on ? "enable" : "disable"), q_idx);
3119                 return I40E_ERR_TIMEOUT;
3120         }
3121
3122         return I40E_SUCCESS;
3123 }
3124 /* Switch on or off the rx queues */
3125 static int
3126 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3127 {
3128         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3129         struct i40e_rx_queue *rxq;
3130         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3131         uint16_t i;
3132         int ret;
3133
3134         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3135                 rxq = dev_data->rx_queues[i];
3136                 /* Don't operate the queue if not configured or
3137                  * if starting only per queue */
3138                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3139                         continue;
3140                 if (on)
3141                         ret = i40e_dev_rx_queue_start(dev, i);
3142                 else
3143                         ret = i40e_dev_rx_queue_stop(dev, i);
3144                 if (ret != I40E_SUCCESS)
3145                         return ret;
3146         }
3147
3148         return I40E_SUCCESS;
3149 }
3150
3151 /* Switch on or off all the rx/tx queues */
3152 int
3153 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3154 {
3155         int ret;
3156
3157         if (on) {
3158                 /* enable rx queues before enabling tx queues */
3159                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3160                 if (ret) {
3161                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3162                         return ret;
3163                 }
3164                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3165         } else {
3166                 /* Stop tx queues before stopping rx queues */
3167                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3168                 if (ret) {
3169                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3170                         return ret;
3171                 }
3172                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3173         }
3174
3175         return ret;
3176 }
3177
3178 /* Initialize VSI for TX */
3179 static int
3180 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3181 {
3182         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3183         struct rte_eth_dev_data *data = pf->dev_data;
3184         uint16_t i;
3185         uint32_t ret = I40E_SUCCESS;
3186
3187         for (i = 0; i < data->nb_tx_queues; i++) {
3188                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3189                 if (ret != I40E_SUCCESS)
3190                         break;
3191         }
3192
3193         return ret;
3194 }
3195
3196 /* Initialize VSI for RX */
3197 static int
3198 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3199 {
3200         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3201         struct rte_eth_dev_data *data = pf->dev_data;
3202         int ret = I40E_SUCCESS;
3203         uint16_t i;
3204
3205         i40e_pf_config_mq_rx(pf);
3206         for (i = 0; i < data->nb_rx_queues; i++) {
3207                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3208                 if (ret != I40E_SUCCESS) {
3209                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3210                                     "initialization");
3211                         break;
3212                 }
3213         }
3214
3215         return ret;
3216 }
3217
3218 /* Initialize VSI */
3219 static int
3220 i40e_vsi_init(struct i40e_vsi *vsi)
3221 {
3222         int err;
3223
3224         err = i40e_vsi_tx_init(vsi);
3225         if (err) {
3226                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3227                 return err;
3228         }
3229         err = i40e_vsi_rx_init(vsi);
3230         if (err) {
3231                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3232                 return err;
3233         }
3234
3235         return err;
3236 }
3237
3238 static void
3239 i40e_stat_update_32(struct i40e_hw *hw,
3240                    uint32_t reg,
3241                    bool offset_loaded,
3242                    uint64_t *offset,
3243                    uint64_t *stat)
3244 {
3245         uint64_t new_data;
3246
3247         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3248         if (!offset_loaded)
3249                 *offset = new_data;
3250
3251         if (new_data >= *offset)
3252                 *stat = (uint64_t)(new_data - *offset);
3253         else
3254                 *stat = (uint64_t)((new_data +
3255                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3256 }
3257
3258 static void
3259 i40e_stat_update_48(struct i40e_hw *hw,
3260                    uint32_t hireg,
3261                    uint32_t loreg,
3262                    bool offset_loaded,
3263                    uint64_t *offset,
3264                    uint64_t *stat)
3265 {
3266         uint64_t new_data;
3267
3268         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3269         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3270                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3271
3272         if (!offset_loaded)
3273                 *offset = new_data;
3274
3275         if (new_data >= *offset)
3276                 *stat = new_data - *offset;
3277         else
3278                 *stat = (uint64_t)((new_data +
3279                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3280
3281         *stat &= I40E_48_BIT_MASK;
3282 }
3283
3284 /* Disable IRQ0 */
3285 void
3286 i40e_pf_disable_irq0(struct i40e_hw *hw)
3287 {
3288         /* Disable all interrupt types */
3289         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3290         I40E_WRITE_FLUSH(hw);
3291 }
3292
3293 /* Enable IRQ0 */
3294 void
3295 i40e_pf_enable_irq0(struct i40e_hw *hw)
3296 {
3297         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3298                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3299                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3300                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3301         I40E_WRITE_FLUSH(hw);
3302 }
3303
3304 static void
3305 i40e_pf_config_irq0(struct i40e_hw *hw)
3306 {
3307         uint32_t enable;
3308
3309         /* read pending request and disable first */
3310         i40e_pf_disable_irq0(hw);
3311         /**
3312          * Enable all interrupt error options to detect possible errors,
3313          * other informative int are ignored
3314          */
3315         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3316                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3317                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3318                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3319                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3320                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3321                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3322                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3323
3324         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3325         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3326                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3327
3328         /* Link no queues with irq0 */
3329         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3330                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3331 }
3332
3333 static void
3334 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3335 {
3336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3338         int i;
3339         uint16_t abs_vf_id;
3340         uint32_t index, offset, val;
3341
3342         if (!pf->vfs)
3343                 return;
3344         /**
3345          * Try to find which VF trigger a reset, use absolute VF id to access
3346          * since the reg is global register.
3347          */
3348         for (i = 0; i < pf->vf_num; i++) {
3349                 abs_vf_id = hw->func_caps.vf_base_id + i;
3350                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3351                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3352                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3353                 /* VFR event occured */
3354                 if (val & (0x1 << offset)) {
3355                         int ret;
3356
3357                         /* Clear the event first */
3358                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3359                                                         (0x1 << offset));
3360                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3361                         /**
3362                          * Only notify a VF reset event occured,
3363                          * don't trigger another SW reset
3364                          */
3365                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3366                         if (ret != I40E_SUCCESS)
3367                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3368                 }
3369         }
3370 }
3371
3372 static void
3373 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3374 {
3375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376         struct i40e_arq_event_info info;
3377         uint16_t pending, opcode;
3378         int ret;
3379
3380         info.buf_len = I40E_AQ_BUF_SZ;
3381         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3382         if (!info.msg_buf) {
3383                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3384                 return;
3385         }
3386
3387         pending = 1;
3388         while (pending) {
3389                 ret = i40e_clean_arq_element(hw, &info, &pending);
3390
3391                 if (ret != I40E_SUCCESS) {
3392                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3393                                     "aq_err: %u", hw->aq.asq_last_status);
3394                         break;
3395                 }
3396                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3397
3398                 switch (opcode) {
3399                 case i40e_aqc_opc_send_msg_to_pf:
3400                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3401                         i40e_pf_host_handle_vf_msg(dev,
3402                                         rte_le_to_cpu_16(info.desc.retval),
3403                                         rte_le_to_cpu_32(info.desc.cookie_high),
3404                                         rte_le_to_cpu_32(info.desc.cookie_low),
3405                                         info.msg_buf,
3406                                         info.msg_len);
3407                         break;
3408                 default:
3409                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3410                                     opcode);
3411                         break;
3412                 }
3413         }
3414         rte_free(info.msg_buf);
3415 }
3416
3417 /**
3418  * Interrupt handler triggered by NIC  for handling
3419  * specific interrupt.
3420  *
3421  * @param handle
3422  *  Pointer to interrupt handle.
3423  * @param param
3424  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3425  *
3426  * @return
3427  *  void
3428  */
3429 static void
3430 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3431                            void *param)
3432 {
3433         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435         uint32_t cause, enable;
3436
3437         i40e_pf_disable_irq0(hw);
3438
3439         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3440         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3441
3442         /* Shared IRQ case, return */
3443         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3444                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3445                             "no INT event to process", hw->pf_id);
3446                 goto done;
3447         }
3448
3449         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3450                 PMD_DRV_LOG(INFO, "INT:Link status changed");
3451                 i40e_dev_link_update(dev, 0);
3452         }
3453
3454         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3455                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3456
3457         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3458                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3459
3460         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3461                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3462
3463         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3464                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3465
3466         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3467                 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3468
3469         /* Add processing func to deal with VF reset vent */
3470         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3471                 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3472                 i40e_dev_handle_vfr_event(dev);
3473         }
3474         /* Find admin queue event */
3475         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3476                 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3477                 i40e_dev_handle_aq_msg(dev);
3478         }
3479
3480 done:
3481         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3482         /* Re-enable interrupt from device side */
3483         i40e_pf_enable_irq0(hw);
3484         /* Re-enable interrupt from host side */
3485         rte_intr_enable(&(dev->pci_dev->intr_handle));
3486 }
3487
3488 static int
3489 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3490                          struct i40e_macvlan_filter *filter,
3491                          int total)
3492 {
3493         int ele_num, ele_buff_size;
3494         int num, actual_num, i;
3495         uint16_t flags;
3496         int ret = I40E_SUCCESS;
3497         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3498         struct i40e_aqc_add_macvlan_element_data *req_list;
3499
3500         if (filter == NULL  || total == 0)
3501                 return I40E_ERR_PARAM;
3502         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3503         ele_buff_size = hw->aq.asq_buf_size;
3504
3505         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3506         if (req_list == NULL) {
3507                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3508                 return I40E_ERR_NO_MEMORY;
3509         }
3510
3511         num = 0;
3512         do {
3513                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3514                 memset(req_list, 0, ele_buff_size);
3515
3516                 for (i = 0; i < actual_num; i++) {
3517                         (void)rte_memcpy(req_list[i].mac_addr,
3518                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3519                         req_list[i].vlan_tag =
3520                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3521
3522                         switch (filter[num + i].filter_type) {
3523                         case RTE_MAC_PERFECT_MATCH:
3524                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3525                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3526                                 break;
3527                         case RTE_MACVLAN_PERFECT_MATCH:
3528                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3529                                 break;
3530                         case RTE_MAC_HASH_MATCH:
3531                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3532                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3533                                 break;
3534                         case RTE_MACVLAN_HASH_MATCH:
3535                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
3536                                 break;
3537                         default:
3538                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
3539                                 ret = I40E_ERR_PARAM;
3540                                 goto DONE;
3541                         }
3542
3543                         req_list[i].queue_number = 0;
3544
3545                         req_list[i].flags = rte_cpu_to_le_16(flags);
3546                 }
3547
3548                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3549                                                 actual_num, NULL);
3550                 if (ret != I40E_SUCCESS) {
3551                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3552                         goto DONE;
3553                 }
3554                 num += actual_num;
3555         } while (num < total);
3556
3557 DONE:
3558         rte_free(req_list);
3559         return ret;
3560 }
3561
3562 static int
3563 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3564                             struct i40e_macvlan_filter *filter,
3565                             int total)
3566 {
3567         int ele_num, ele_buff_size;
3568         int num, actual_num, i;
3569         uint16_t flags;
3570         int ret = I40E_SUCCESS;
3571         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3572         struct i40e_aqc_remove_macvlan_element_data *req_list;
3573
3574         if (filter == NULL  || total == 0)
3575                 return I40E_ERR_PARAM;
3576
3577         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3578         ele_buff_size = hw->aq.asq_buf_size;
3579
3580         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3581         if (req_list == NULL) {
3582                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3583                 return I40E_ERR_NO_MEMORY;
3584         }
3585
3586         num = 0;
3587         do {
3588                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3589                 memset(req_list, 0, ele_buff_size);
3590
3591                 for (i = 0; i < actual_num; i++) {
3592                         (void)rte_memcpy(req_list[i].mac_addr,
3593                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3594                         req_list[i].vlan_tag =
3595                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3596
3597                         switch (filter[num + i].filter_type) {
3598                         case RTE_MAC_PERFECT_MATCH:
3599                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3600                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3601                                 break;
3602                         case RTE_MACVLAN_PERFECT_MATCH:
3603                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3604                                 break;
3605                         case RTE_MAC_HASH_MATCH:
3606                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
3607                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3608                                 break;
3609                         case RTE_MACVLAN_HASH_MATCH:
3610                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
3611                                 break;
3612                         default:
3613                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
3614                                 ret = I40E_ERR_PARAM;
3615                                 goto DONE;
3616                         }
3617                         req_list[i].flags = rte_cpu_to_le_16(flags);
3618                 }
3619
3620                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3621                                                 actual_num, NULL);
3622                 if (ret != I40E_SUCCESS) {
3623                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3624                         goto DONE;
3625                 }
3626                 num += actual_num;
3627         } while (num < total);
3628
3629 DONE:
3630         rte_free(req_list);
3631         return ret;
3632 }
3633
3634 /* Find out specific MAC filter */
3635 static struct i40e_mac_filter *
3636 i40e_find_mac_filter(struct i40e_vsi *vsi,
3637                          struct ether_addr *macaddr)
3638 {
3639         struct i40e_mac_filter *f;
3640
3641         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3642                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
3643                         return f;
3644         }
3645
3646         return NULL;
3647 }
3648
3649 static bool
3650 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3651                          uint16_t vlan_id)
3652 {
3653         uint32_t vid_idx, vid_bit;
3654
3655         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3656         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3657
3658         if (vsi->vfta[vid_idx] & vid_bit)
3659                 return 1;
3660         else
3661                 return 0;
3662 }
3663
3664 static void
3665 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3666                          uint16_t vlan_id, bool on)
3667 {
3668         uint32_t vid_idx, vid_bit;
3669
3670 #define UINT32_BIT_MASK      0x1F
3671 #define VALID_VLAN_BIT_MASK  0xFFF
3672         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3673          *  element first, then find the bits it belongs to
3674          */
3675         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3676                   sizeof(uint32_t));
3677         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3678
3679         if (on)
3680                 vsi->vfta[vid_idx] |= vid_bit;
3681         else
3682                 vsi->vfta[vid_idx] &= ~vid_bit;
3683 }
3684
3685 /**
3686  * Find all vlan options for specific mac addr,
3687  * return with actual vlan found.
3688  */
3689 static inline int
3690 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3691                            struct i40e_macvlan_filter *mv_f,
3692                            int num, struct ether_addr *addr)
3693 {
3694         int i;
3695         uint32_t j, k;
3696
3697         /**
3698          * Not to use i40e_find_vlan_filter to decrease the loop time,
3699          * although the code looks complex.
3700           */
3701         if (num < vsi->vlan_num)
3702                 return I40E_ERR_PARAM;
3703
3704         i = 0;
3705         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3706                 if (vsi->vfta[j]) {
3707                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3708                                 if (vsi->vfta[j] & (1 << k)) {
3709                                         if (i > num - 1) {
3710                                                 PMD_DRV_LOG(ERR, "vlan number "
3711                                                             "not match");
3712                                                 return I40E_ERR_PARAM;
3713                                         }
3714                                         (void)rte_memcpy(&mv_f[i].macaddr,
3715                                                         addr, ETH_ADDR_LEN);
3716                                         mv_f[i].vlan_id =
3717                                                 j * I40E_UINT32_BIT_SIZE + k;
3718                                         i++;
3719                                 }
3720                         }
3721                 }
3722         }
3723         return I40E_SUCCESS;
3724 }
3725
3726 static inline int
3727 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3728                            struct i40e_macvlan_filter *mv_f,
3729                            int num,
3730                            uint16_t vlan)
3731 {
3732         int i = 0;
3733         struct i40e_mac_filter *f;
3734
3735         if (num < vsi->mac_num)
3736                 return I40E_ERR_PARAM;
3737
3738         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3739                 if (i > num - 1) {
3740                         PMD_DRV_LOG(ERR, "buffer number not match");
3741                         return I40E_ERR_PARAM;
3742                 }
3743                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
3744                                 ETH_ADDR_LEN);
3745                 mv_f[i].vlan_id = vlan;
3746                 mv_f[i].filter_type = f->mac_info.filter_type;
3747                 i++;
3748         }
3749
3750         return I40E_SUCCESS;
3751 }
3752
3753 static int
3754 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3755 {
3756         int i, num;
3757         struct i40e_mac_filter *f;
3758         struct i40e_macvlan_filter *mv_f;
3759         int ret = I40E_SUCCESS;
3760
3761         if (vsi == NULL || vsi->mac_num == 0)
3762                 return I40E_ERR_PARAM;
3763
3764         /* Case that no vlan is set */
3765         if (vsi->vlan_num == 0)
3766                 num = vsi->mac_num;
3767         else
3768                 num = vsi->mac_num * vsi->vlan_num;
3769
3770         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3771         if (mv_f == NULL) {
3772                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3773                 return I40E_ERR_NO_MEMORY;
3774         }
3775
3776         i = 0;
3777         if (vsi->vlan_num == 0) {
3778                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3779                         (void)rte_memcpy(&mv_f[i].macaddr,
3780                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
3781                         mv_f[i].vlan_id = 0;
3782                         i++;
3783                 }
3784         } else {
3785                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3786                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3787                                         vsi->vlan_num, &f->mac_info.mac_addr);
3788                         if (ret != I40E_SUCCESS)
3789                                 goto DONE;
3790                         i += vsi->vlan_num;
3791                 }
3792         }
3793
3794         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3795 DONE:
3796         rte_free(mv_f);
3797
3798         return ret;
3799 }
3800
3801 int
3802 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3803 {
3804         struct i40e_macvlan_filter *mv_f;
3805         int mac_num;
3806         int ret = I40E_SUCCESS;
3807
3808         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3809                 return I40E_ERR_PARAM;
3810
3811         /* If it's already set, just return */
3812         if (i40e_find_vlan_filter(vsi,vlan))
3813                 return I40E_SUCCESS;
3814
3815         mac_num = vsi->mac_num;
3816
3817         if (mac_num == 0) {
3818                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3819                 return I40E_ERR_PARAM;
3820         }
3821
3822         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3823
3824         if (mv_f == NULL) {
3825                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3826                 return I40E_ERR_NO_MEMORY;
3827         }
3828
3829         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3830
3831         if (ret != I40E_SUCCESS)
3832                 goto DONE;
3833
3834         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3835
3836         if (ret != I40E_SUCCESS)
3837                 goto DONE;
3838
3839         i40e_set_vlan_filter(vsi, vlan, 1);
3840
3841         vsi->vlan_num++;
3842         ret = I40E_SUCCESS;
3843 DONE:
3844         rte_free(mv_f);
3845         return ret;
3846 }
3847
3848 int
3849 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3850 {
3851         struct i40e_macvlan_filter *mv_f;
3852         int mac_num;
3853         int ret = I40E_SUCCESS;
3854
3855         /**
3856          * Vlan 0 is the generic filter for untagged packets
3857          * and can't be removed.
3858          */
3859         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3860                 return I40E_ERR_PARAM;
3861
3862         /* If can't find it, just return */
3863         if (!i40e_find_vlan_filter(vsi, vlan))
3864                 return I40E_ERR_PARAM;
3865
3866         mac_num = vsi->mac_num;
3867
3868         if (mac_num == 0) {
3869                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3870                 return I40E_ERR_PARAM;
3871         }
3872
3873         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3874
3875         if (mv_f == NULL) {
3876                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3877                 return I40E_ERR_NO_MEMORY;
3878         }
3879
3880         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3881
3882         if (ret != I40E_SUCCESS)
3883                 goto DONE;
3884
3885         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3886
3887         if (ret != I40E_SUCCESS)
3888                 goto DONE;
3889
3890         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3891         if (vsi->vlan_num == 1) {
3892                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3893                 if (ret != I40E_SUCCESS)
3894                         goto DONE;
3895
3896                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3897                 if (ret != I40E_SUCCESS)
3898                         goto DONE;
3899         }
3900
3901         i40e_set_vlan_filter(vsi, vlan, 0);
3902
3903         vsi->vlan_num--;
3904         ret = I40E_SUCCESS;
3905 DONE:
3906         rte_free(mv_f);
3907         return ret;
3908 }
3909
3910 int
3911 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
3912 {
3913         struct i40e_mac_filter *f;
3914         struct i40e_macvlan_filter *mv_f;
3915         int i, vlan_num = 0;
3916         int ret = I40E_SUCCESS;
3917
3918         /* If it's add and we've config it, return */
3919         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
3920         if (f != NULL)
3921                 return I40E_SUCCESS;
3922         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
3923                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
3924
3925                 /**
3926                  * If vlan_num is 0, that's the first time to add mac,
3927                  * set mask for vlan_id 0.
3928                  */
3929                 if (vsi->vlan_num == 0) {
3930                         i40e_set_vlan_filter(vsi, 0, 1);
3931                         vsi->vlan_num = 1;
3932                 }
3933                 vlan_num = vsi->vlan_num;
3934         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
3935                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
3936                 vlan_num = 1;
3937
3938         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3939         if (mv_f == NULL) {
3940                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3941                 return I40E_ERR_NO_MEMORY;
3942         }
3943
3944         for (i = 0; i < vlan_num; i++) {
3945                 mv_f[i].filter_type = mac_filter->filter_type;
3946                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
3947                                 ETH_ADDR_LEN);
3948         }
3949
3950         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
3951                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
3952                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
3953                                         &mac_filter->mac_addr);
3954                 if (ret != I40E_SUCCESS)
3955                         goto DONE;
3956         }
3957
3958         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3959         if (ret != I40E_SUCCESS)
3960                 goto DONE;
3961
3962         /* Add the mac addr into mac list */
3963         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3964         if (f == NULL) {
3965                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3966                 ret = I40E_ERR_NO_MEMORY;
3967                 goto DONE;
3968         }
3969         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
3970                         ETH_ADDR_LEN);
3971         f->mac_info.filter_type = mac_filter->filter_type;
3972         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3973         vsi->mac_num++;
3974
3975         ret = I40E_SUCCESS;
3976 DONE:
3977         rte_free(mv_f);
3978
3979         return ret;
3980 }
3981
3982 int
3983 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3984 {
3985         struct i40e_mac_filter *f;
3986         struct i40e_macvlan_filter *mv_f;
3987         int i, vlan_num;
3988         enum rte_mac_filter_type filter_type;
3989         int ret = I40E_SUCCESS;
3990
3991         /* Can't find it, return an error */
3992         f = i40e_find_mac_filter(vsi, addr);
3993         if (f == NULL)
3994                 return I40E_ERR_PARAM;
3995
3996         vlan_num = vsi->vlan_num;
3997         filter_type = f->mac_info.filter_type;
3998         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
3999                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4000                 if (vlan_num == 0) {
4001                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4002                         return I40E_ERR_PARAM;
4003                 }
4004         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4005                         filter_type == RTE_MAC_HASH_MATCH)
4006                 vlan_num = 1;
4007
4008         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4009         if (mv_f == NULL) {
4010                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4011                 return I40E_ERR_NO_MEMORY;
4012         }
4013
4014         for (i = 0; i < vlan_num; i++) {
4015                 mv_f[i].filter_type = filter_type;
4016                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4017                                 ETH_ADDR_LEN);
4018         }
4019         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4020                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4021                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4022                 if (ret != I40E_SUCCESS)
4023                         goto DONE;
4024         }
4025
4026         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4027         if (ret != I40E_SUCCESS)
4028                 goto DONE;
4029
4030         /* Remove the mac addr into mac list */
4031         TAILQ_REMOVE(&vsi->mac_list, f, next);
4032         rte_free(f);
4033         vsi->mac_num--;
4034
4035         ret = I40E_SUCCESS;
4036 DONE:
4037         rte_free(mv_f);
4038         return ret;
4039 }
4040
4041 /* Configure hash enable flags for RSS */
4042 uint64_t
4043 i40e_config_hena(uint64_t flags)
4044 {
4045         uint64_t hena = 0;
4046
4047         if (!flags)
4048                 return hena;
4049
4050         if (flags & ETH_RSS_NONF_IPV4_UDP)
4051                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4052         if (flags & ETH_RSS_NONF_IPV4_TCP)
4053                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4054         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4055                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4056         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4057                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4058         if (flags & ETH_RSS_FRAG_IPV4)
4059                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4060         if (flags & ETH_RSS_NONF_IPV6_UDP)
4061                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4062         if (flags & ETH_RSS_NONF_IPV6_TCP)
4063                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4064         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4065                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4066         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4067                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4068         if (flags & ETH_RSS_FRAG_IPV6)
4069                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4070         if (flags & ETH_RSS_L2_PAYLOAD)
4071                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4072
4073         return hena;
4074 }
4075
4076 /* Parse the hash enable flags */
4077 uint64_t
4078 i40e_parse_hena(uint64_t flags)
4079 {
4080         uint64_t rss_hf = 0;
4081
4082         if (!flags)
4083                 return rss_hf;
4084
4085         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4086                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4087         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4088                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4089         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4090                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4091         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4092                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4093         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4094                 rss_hf |= ETH_RSS_FRAG_IPV4;
4095         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4096                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4097         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4098                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4099         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4100                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4101         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4102                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4103         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4104                 rss_hf |= ETH_RSS_FRAG_IPV6;
4105         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4106                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4107
4108         return rss_hf;
4109 }
4110
4111 /* Disable RSS */
4112 static void
4113 i40e_pf_disable_rss(struct i40e_pf *pf)
4114 {
4115         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4116         uint64_t hena;
4117
4118         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4119         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4120         hena &= ~I40E_RSS_HENA_ALL;
4121         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4122         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4123         I40E_WRITE_FLUSH(hw);
4124 }
4125
4126 static int
4127 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4128 {
4129         uint32_t *hash_key;
4130         uint8_t hash_key_len;
4131         uint64_t rss_hf;
4132         uint16_t i;
4133         uint64_t hena;
4134
4135         hash_key = (uint32_t *)(rss_conf->rss_key);
4136         hash_key_len = rss_conf->rss_key_len;
4137         if (hash_key != NULL && hash_key_len >=
4138                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4139                 /* Fill in RSS hash key */
4140                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4141                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4142         }
4143
4144         rss_hf = rss_conf->rss_hf;
4145         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4146         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4147         hena &= ~I40E_RSS_HENA_ALL;
4148         hena |= i40e_config_hena(rss_hf);
4149         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4150         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4151         I40E_WRITE_FLUSH(hw);
4152
4153         return 0;
4154 }
4155
4156 static int
4157 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4158                          struct rte_eth_rss_conf *rss_conf)
4159 {
4160         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4161         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4162         uint64_t hena;
4163
4164         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4165         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4166         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4167                 if (rss_hf != 0) /* Enable RSS */
4168                         return -EINVAL;
4169                 return 0; /* Nothing to do */
4170         }
4171         /* RSS enabled */
4172         if (rss_hf == 0) /* Disable RSS */
4173                 return -EINVAL;
4174
4175         return i40e_hw_rss_hash_set(hw, rss_conf);
4176 }
4177
4178 static int
4179 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4180                            struct rte_eth_rss_conf *rss_conf)
4181 {
4182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4183         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4184         uint64_t hena;
4185         uint16_t i;
4186
4187         if (hash_key != NULL) {
4188                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4189                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4190                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4191         }
4192         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4193         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4194         rss_conf->rss_hf = i40e_parse_hena(hena);
4195
4196         return 0;
4197 }
4198
4199 static int
4200 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4201 {
4202         switch (filter_type) {
4203         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4204                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4205                 break;
4206         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4207                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4208                 break;
4209         case RTE_TUNNEL_FILTER_IMAC_TENID:
4210                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4211                 break;
4212         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4213                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4214                 break;
4215         case ETH_TUNNEL_FILTER_IMAC:
4216                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4217                 break;
4218         default:
4219                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4220                 return -EINVAL;
4221         }
4222
4223         return 0;
4224 }
4225
4226 static int
4227 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4228                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4229                         uint8_t add)
4230 {
4231         uint16_t ip_type;
4232         uint8_t tun_type = 0;
4233         int val, ret = 0;
4234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4235         struct i40e_vsi *vsi = pf->main_vsi;
4236         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4237         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4238
4239         cld_filter = rte_zmalloc("tunnel_filter",
4240                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4241                 0);
4242
4243         if (NULL == cld_filter) {
4244                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4245                 return -EINVAL;
4246         }
4247         pfilter = cld_filter;
4248
4249         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4250                         sizeof(struct ether_addr));
4251         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4252                         sizeof(struct ether_addr));
4253
4254         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4255         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4256                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4257                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4258                                 &tunnel_filter->ip_addr,
4259                                 sizeof(pfilter->ipaddr.v4.data));
4260         } else {
4261                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4262                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4263                                 &tunnel_filter->ip_addr,
4264                                 sizeof(pfilter->ipaddr.v6.data));
4265         }
4266
4267         /* check tunneled type */
4268         switch (tunnel_filter->tunnel_type) {
4269         case RTE_TUNNEL_TYPE_VXLAN:
4270                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4271                 break;
4272         default:
4273                 /* Other tunnel types is not supported. */
4274                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4275                 rte_free(cld_filter);
4276                 return -EINVAL;
4277         }
4278
4279         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4280                                                 &pfilter->flags);
4281         if (val < 0) {
4282                 rte_free(cld_filter);
4283                 return -EINVAL;
4284         }
4285
4286         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4287                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4288         pfilter->tenant_id = tunnel_filter->tenant_id;
4289         pfilter->queue_number = tunnel_filter->queue_id;
4290
4291         if (add)
4292                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4293         else
4294                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4295                                                 cld_filter, 1);
4296
4297         rte_free(cld_filter);
4298         return ret;
4299 }
4300
4301 static int
4302 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4303 {
4304         uint8_t i;
4305
4306         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4307                 if (pf->vxlan_ports[i] == port)
4308                         return i;
4309         }
4310
4311         return -1;
4312 }
4313
4314 static int
4315 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4316 {
4317         int  idx, ret;
4318         uint8_t filter_idx;
4319         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4320
4321         idx = i40e_get_vxlan_port_idx(pf, port);
4322
4323         /* Check if port already exists */
4324         if (idx >= 0) {
4325                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4326                 return -EINVAL;
4327         }
4328
4329         /* Now check if there is space to add the new port */
4330         idx = i40e_get_vxlan_port_idx(pf, 0);
4331         if (idx < 0) {
4332                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4333                         "not adding port %d", port);
4334                 return -ENOSPC;
4335         }
4336
4337         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4338                                         &filter_idx, NULL);
4339         if (ret < 0) {
4340                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4341                 return -1;
4342         }
4343
4344         PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4345                          port,  filter_index);
4346
4347         /* New port: add it and mark its index in the bitmap */
4348         pf->vxlan_ports[idx] = port;
4349         pf->vxlan_bitmap |= (1 << idx);
4350
4351         if (!(pf->flags & I40E_FLAG_VXLAN))
4352                 pf->flags |= I40E_FLAG_VXLAN;
4353
4354         return 0;
4355 }
4356
4357 static int
4358 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4359 {
4360         int idx;
4361         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4362
4363         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4364                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4365                 return -EINVAL;
4366         }
4367
4368         idx = i40e_get_vxlan_port_idx(pf, port);
4369
4370         if (idx < 0) {
4371                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4372                 return -EINVAL;
4373         }
4374
4375         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4376                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4377                 return -1;
4378         }
4379
4380         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4381                         port, idx);
4382
4383         pf->vxlan_ports[idx] = 0;
4384         pf->vxlan_bitmap &= ~(1 << idx);
4385
4386         if (!pf->vxlan_bitmap)
4387                 pf->flags &= ~I40E_FLAG_VXLAN;
4388
4389         return 0;
4390 }
4391
4392 /* Add UDP tunneling port */
4393 static int
4394 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4395                         struct rte_eth_udp_tunnel *udp_tunnel)
4396 {
4397         int ret = 0;
4398         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4399
4400         if (udp_tunnel == NULL)
4401                 return -EINVAL;
4402
4403         switch (udp_tunnel->prot_type) {
4404         case RTE_TUNNEL_TYPE_VXLAN:
4405                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4406                 break;
4407
4408         case RTE_TUNNEL_TYPE_GENEVE:
4409         case RTE_TUNNEL_TYPE_TEREDO:
4410                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4411                 ret = -1;
4412                 break;
4413
4414         default:
4415                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4416                 ret = -1;
4417                 break;
4418         }
4419
4420         return ret;
4421 }
4422
4423 /* Remove UDP tunneling port */
4424 static int
4425 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4426                         struct rte_eth_udp_tunnel *udp_tunnel)
4427 {
4428         int ret = 0;
4429         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4430
4431         if (udp_tunnel == NULL)
4432                 return -EINVAL;
4433
4434         switch (udp_tunnel->prot_type) {
4435         case RTE_TUNNEL_TYPE_VXLAN:
4436                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4437                 break;
4438         case RTE_TUNNEL_TYPE_GENEVE:
4439         case RTE_TUNNEL_TYPE_TEREDO:
4440                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4441                 ret = -1;
4442                 break;
4443         default:
4444                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4445                 ret = -1;
4446                 break;
4447         }
4448
4449         return ret;
4450 }
4451
4452 /* Configure RSS */
4453 static int
4454 i40e_pf_config_rss(struct i40e_pf *pf)
4455 {
4456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4457         struct rte_eth_rss_conf rss_conf;
4458         uint32_t i, lut = 0;
4459         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4460
4461         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4462                 if (j == num)
4463                         j = 0;
4464                 lut = (lut << 8) | (j & ((0x1 <<
4465                         hw->func_caps.rss_table_entry_width) - 1));
4466                 if ((i & 3) == 3)
4467                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4468         }
4469
4470         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4471         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4472                 i40e_pf_disable_rss(pf);
4473                 return 0;
4474         }
4475         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4476                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4477                 /* Calculate the default hash key */
4478                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4479                         rss_key_default[i] = (uint32_t)rte_rand();
4480                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4481                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4482                                                         sizeof(uint32_t);
4483         }
4484
4485         return i40e_hw_rss_hash_set(hw, &rss_conf);
4486 }
4487
4488 static int
4489 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4490                         struct rte_eth_tunnel_filter_conf *filter)
4491 {
4492         if (pf == NULL || filter == NULL) {
4493                 PMD_DRV_LOG(ERR, "Invalid parameter");
4494                 return -EINVAL;
4495         }
4496
4497         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4498                 PMD_DRV_LOG(ERR, "Invalid queue ID");
4499                 return -EINVAL;
4500         }
4501
4502         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4503                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4504                 return -EINVAL;
4505         }
4506
4507         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4508                 (is_zero_ether_addr(filter->outer_mac))) {
4509                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4510                 return -EINVAL;
4511         }
4512
4513         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4514                 (is_zero_ether_addr(filter->inner_mac))) {
4515                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4516                 return -EINVAL;
4517         }
4518
4519         return 0;
4520 }
4521
4522 static int
4523 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4524                         void *arg)
4525 {
4526         struct rte_eth_tunnel_filter_conf *filter;
4527         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4528         int ret = I40E_SUCCESS;
4529
4530         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4531
4532         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4533                 return I40E_ERR_PARAM;
4534
4535         switch (filter_op) {
4536         case RTE_ETH_FILTER_NOP:
4537                 if (!(pf->flags & I40E_FLAG_VXLAN))
4538                         ret = I40E_NOT_SUPPORTED;
4539         case RTE_ETH_FILTER_ADD:
4540                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4541                 break;
4542         case RTE_ETH_FILTER_DELETE:
4543                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4544                 break;
4545         default:
4546                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4547                 ret = I40E_ERR_PARAM;
4548                 break;
4549         }
4550
4551         return ret;
4552 }
4553
4554 static int
4555 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4556 {
4557         if (!pf->dev_data->sriov.active) {
4558                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4559                 case ETH_MQ_RX_RSS:
4560                         i40e_pf_config_rss(pf);
4561                         break;
4562                 default:
4563                         i40e_pf_disable_rss(pf);
4564                         break;
4565                 }
4566         }
4567
4568         return 0;
4569 }
4570
4571 static int
4572 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4573                      enum rte_filter_type filter_type,
4574                      enum rte_filter_op filter_op,
4575                      void *arg)
4576 {
4577         int ret = 0;
4578
4579         if (dev == NULL)
4580                 return -EINVAL;
4581
4582         switch (filter_type) {
4583         case RTE_ETH_FILTER_TUNNEL:
4584                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
4585                 break;
4586         default:
4587                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4588                                                         filter_type);
4589                 ret = -EINVAL;
4590                 break;
4591         }
4592
4593         return ret;
4594 }