lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(\
 110                         __attribute__((unused)) struct eth_driver *eth_drv,
 111                         struct rte_eth_dev *eth_dev);
 112 static int i40e_dev_configure(struct rte_eth_dev *dev);
 113 static int i40e_dev_start(struct rte_eth_dev *dev);
 114 static void i40e_dev_stop(struct rte_eth_dev *dev);
 115 static void i40e_dev_close(struct rte_eth_dev *dev);
 116 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 118 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 119 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 120 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 121 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 122 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 123                                struct rte_eth_stats *stats);
 124 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 125 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 126                                             uint16_t queue_id,
 127                                             uint8_t stat_idx,
 128                                             uint8_t is_rx);
 129 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 130                               struct rte_eth_dev_info *dev_info);
 131 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 132                                 uint16_t vlan_id,
 133                                 int on);
 134 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 135 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 136 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 137                                       uint16_t queue,
 138                                       int on);
 139 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 140 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 141 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 142 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 143                               struct rte_eth_fc_conf *fc_conf);
 144 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                                        struct rte_eth_pfc_conf *pfc_conf);
 146 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 147                           struct ether_addr *mac_addr,
 148                           uint32_t index,
 149                           uint32_t pool);
 150 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 151 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 152                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 153                                     uint16_t reta_size);
 154 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 155                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 156                                    uint16_t reta_size);
 157
 158 static int i40e_get_cap(struct i40e_hw *hw);
 159 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 160 static int i40e_pf_setup(struct i40e_pf *pf);
 161 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 162 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 163 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 164                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 165 static void i40e_stat_update_48(struct i40e_hw *hw,
 166                                uint32_t hireg,
 167                                uint32_t loreg,
 168                                bool offset_loaded,
 169                                uint64_t *offset,
 170                                uint64_t *stat);
 171 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 172 static void i40e_dev_interrupt_handler(
 173                 __rte_unused struct rte_intr_handle *handle, void *param);
 174 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 175                                 uint32_t base, uint32_t num);
 176 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 177 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 178                         uint32_t base);
 179 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 180                         uint16_t num);
 181 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 182 static int i40e_veb_release(struct i40e_veb *veb);
 183 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 184                                                 struct i40e_vsi *vsi);
 185 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 186 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 187 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 188                                              struct i40e_macvlan_filter *mv_f,
 189                                              int num,
 190                                              struct ether_addr *addr);
 191 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 192                                              struct i40e_macvlan_filter *mv_f,
 193                                              int num,
 194                                              uint16_t vlan);
 195 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 196 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 197                                     struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 199                                       struct rte_eth_rss_conf *rss_conf);
 200 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 203                                 struct rte_eth_udp_tunnel *udp_tunnel);
 204 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 205                         struct rte_eth_ethertype_filter *filter,
 206                         bool add);
 207 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 211                                 enum rte_filter_type filter_type,
 212                                 enum rte_filter_op filter_op,
 213                                 void *arg);
 214 static void i40e_configure_registers(struct i40e_hw *hw);
 215 static void i40e_hw_init(struct i40e_hw *hw);
 216
 217 static struct rte_pci_id pci_id_i40e_map[] = {
 218 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 219 #include "rte_pci_dev_ids.h"
 220 { .vendor_id = 0, /* sentinel */ },
 221 };
 222
 223 static struct eth_dev_ops i40e_eth_dev_ops = {
 224         .dev_configure                = i40e_dev_configure,
 225         .dev_start                    = i40e_dev_start,
 226         .dev_stop                     = i40e_dev_stop,
 227         .dev_close                    = i40e_dev_close,
 228         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 229         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 230         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 231         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 232         .dev_set_link_up              = i40e_dev_set_link_up,
 233         .dev_set_link_down            = i40e_dev_set_link_down,
 234         .link_update                  = i40e_dev_link_update,
 235         .stats_get                    = i40e_dev_stats_get,
 236         .stats_reset                  = i40e_dev_stats_reset,
 237         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 238         .dev_infos_get                = i40e_dev_info_get,
 239         .vlan_filter_set              = i40e_vlan_filter_set,
 240         .vlan_tpid_set                = i40e_vlan_tpid_set,
 241         .vlan_offload_set             = i40e_vlan_offload_set,
 242         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 243         .vlan_pvid_set                = i40e_vlan_pvid_set,
 244         .rx_queue_start               = i40e_dev_rx_queue_start,
 245         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 246         .tx_queue_start               = i40e_dev_tx_queue_start,
 247         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 248         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 249         .rx_queue_release             = i40e_dev_rx_queue_release,
 250         .rx_queue_count               = i40e_dev_rx_queue_count,
 251         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 252         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 253         .tx_queue_release             = i40e_dev_tx_queue_release,
 254         .dev_led_on                   = i40e_dev_led_on,
 255         .dev_led_off                  = i40e_dev_led_off,
 256         .flow_ctrl_set                = i40e_flow_ctrl_set,
 257         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 258         .mac_addr_add                 = i40e_macaddr_add,
 259         .mac_addr_remove              = i40e_macaddr_remove,
 260         .reta_update                  = i40e_dev_rss_reta_update,
 261         .reta_query                   = i40e_dev_rss_reta_query,
 262         .rss_hash_update              = i40e_dev_rss_hash_update,
 263         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 264         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 265         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 266         .filter_ctrl                  = i40e_dev_filter_ctrl,
 267 };
 268
 269 static struct eth_driver rte_i40e_pmd = {
 270         {
 271                 .name = "rte_i40e_pmd",
 272                 .id_table = pci_id_i40e_map,
 273                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 274         },
 275         .eth_dev_init = eth_i40e_dev_init,
 276         .dev_private_size = sizeof(struct i40e_adapter),
 277 };
 278
 279 static inline int
 280 i40e_align_floor(int n)
 281 {
 282         if (n == 0)
 283                 return 0;
 284         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 285 }
 286
 287 static inline int
 288 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 289                                      struct rte_eth_link *link)
 290 {
 291         struct rte_eth_link *dst = link;
 292         struct rte_eth_link *src = &(dev->data->dev_link);
 293
 294         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 295                                         *(uint64_t *)src) == 0)
 296                 return -1;
 297
 298         return 0;
 299 }
 300
 301 static inline int
 302 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 303                                       struct rte_eth_link *link)
 304 {
 305         struct rte_eth_link *dst = &(dev->data->dev_link);
 306         struct rte_eth_link *src = link;
 307
 308         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 309                                         *(uint64_t *)src) == 0)
 310                 return -1;
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Driver initialization routine.
 317  * Invoked once at EAL init time.
 318  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 319  */
 320 static int
 321 rte_i40e_pmd_init(const char *name __rte_unused,
 322                   const char *params __rte_unused)
 323 {
 324         PMD_INIT_FUNC_TRACE();
 325         rte_eth_driver_register(&rte_i40e_pmd);
 326
 327         return 0;
 328 }
 329
 330 static struct rte_driver rte_i40e_driver = {
 331         .type = PMD_PDEV,
 332         .init = rte_i40e_pmd_init,
 333 };
 334
 335 PMD_REGISTER_DRIVER(rte_i40e_driver);
 336
 337 /*
 338  * Initialize registers for flexible payload, which should be set by NVM.
 339  * This should be removed from code once it is fixed in NVM.
 340  */
 341 #ifndef I40E_GLQF_ORT
 342 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 343 #endif
 344 #ifndef I40E_GLQF_PIT
 345 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 346 #endif
 347
 348 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 349 {
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 359         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 360
 361         /* GLQF_PIT Registers */
 362         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 363         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 364 }
 365
 366 static int
 367 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 368                   struct rte_eth_dev *dev)
 369 {
 370         struct rte_pci_device *pci_dev;
 371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373         struct i40e_vsi *vsi;
 374         int ret;
 375         uint32_t len;
 376         uint8_t aq_fail = 0;
 377
 378         PMD_INIT_FUNC_TRACE();
 379
 380         dev->dev_ops = &i40e_eth_dev_ops;
 381         dev->rx_pkt_burst = i40e_recv_pkts;
 382         dev->tx_pkt_burst = i40e_xmit_pkts;
 383
 384         /* for secondary processes, we don't initialise any further as primary
 385          * has already done this work. Only check we don't need a different
 386          * RX function */
 387         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 388                 if (dev->data->scattered_rx)
 389                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 390                 return 0;
 391         }
 392         pci_dev = dev->pci_dev;
 393         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 394         pf->adapter->eth_dev = dev;
 395         pf->dev_data = dev->data;
 396
 397         hw->back = I40E_PF_TO_ADAPTER(pf);
 398         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 399         if (!hw->hw_addr) {
 400                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 401                              "as address is NULL");
 402                 return -ENODEV;
 403         }
 404
 405         hw->vendor_id = pci_dev->id.vendor_id;
 406         hw->device_id = pci_dev->id.device_id;
 407         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 408         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 409         hw->bus.device = pci_dev->addr.devid;
 410         hw->bus.func = pci_dev->addr.function;
 411
 412         /* Make sure all is clean before doing PF reset */
 413         i40e_clear_hw(hw);
 414
 415         /* Initialize the hardware */
 416         i40e_hw_init(hw);
 417
 418         /* Reset here to make sure all is clean for each PF */
 419         ret = i40e_pf_reset(hw);
 420         if (ret) {
 421                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 422                 return ret;
 423         }
 424
 425         /* Initialize the shared code (base driver) */
 426         ret = i40e_init_shared_code(hw);
 427         if (ret) {
 428                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 429                 return ret;
 430         }
 431
 432         /*
 433          * To work around the NVM issue,initialize registers
 434          * for flexible payload by software.
 435          * It should be removed once issues are fixed in NVM.
 436          */
 437         i40e_flex_payload_reg_init(hw);
 438
 439         /* Initialize the parameters for adminq */
 440         i40e_init_adminq_parameter(hw);
 441         ret = i40e_init_adminq(hw);
 442         if (ret != I40E_SUCCESS) {
 443                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 444                 return -EIO;
 445         }
 446         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 447                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 448                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 449                      ((hw->nvm.version >> 12) & 0xf),
 450                      ((hw->nvm.version >> 4) & 0xff),
 451                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 452
 453         /* Disable LLDP */
 454         ret = i40e_aq_stop_lldp(hw, true, NULL);
 455         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 456                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 457
 458         /* Clear PXE mode */
 459         i40e_clear_pxe_mode(hw);
 460
 461         /*
 462          * On X710, performance number is far from the expectation on recent
 463          * firmware versions. The fix for this issue may not be integrated in
 464          * the following firmware version. So the workaround in software driver
 465          * is needed. It needs to modify the initial values of 3 internal only
 466          * registers. Note that the workaround can be removed when it is fixed
 467          * in firmware in the future.
 468          */
 469         i40e_configure_registers(hw);
 470
 471         /* Get hw capabilities */
 472         ret = i40e_get_cap(hw);
 473         if (ret != I40E_SUCCESS) {
 474                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 475                 goto err_get_capabilities;
 476         }
 477
 478         /* Initialize parameters for PF */
 479         ret = i40e_pf_parameter_init(dev);
 480         if (ret != 0) {
 481                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 482                 goto err_parameter_init;
 483         }
 484
 485         /* Initialize the queue management */
 486         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 487         if (ret < 0) {
 488                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 489                 goto err_qp_pool_init;
 490         }
 491         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 492                                 hw->func_caps.num_msix_vectors - 1);
 493         if (ret < 0) {
 494                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 495                 goto err_msix_pool_init;
 496         }
 497
 498         /* Initialize lan hmc */
 499         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 500                                 hw->func_caps.num_rx_qp, 0, 0);
 501         if (ret != I40E_SUCCESS) {
 502                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 503                 goto err_init_lan_hmc;
 504         }
 505
 506         /* Configure lan hmc */
 507         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 508         if (ret != I40E_SUCCESS) {
 509                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 510                 goto err_configure_lan_hmc;
 511         }
 512
 513         /* Get and check the mac address */
 514         i40e_get_mac_addr(hw, hw->mac.addr);
 515         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 516                 PMD_INIT_LOG(ERR, "mac address is not valid");
 517                 ret = -EIO;
 518                 goto err_get_mac_addr;
 519         }
 520         /* Copy the permanent MAC address */
 521         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 522                         (struct ether_addr *) hw->mac.perm_addr);
 523
 524         /* Disable flow control */
 525         hw->fc.requested_mode = I40E_FC_NONE;
 526         i40e_set_fc(hw, &aq_fail, TRUE);
 527
 528         /* PF setup, which includes VSI setup */
 529         ret = i40e_pf_setup(pf);
 530         if (ret) {
 531                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 532                 goto err_setup_pf_switch;
 533         }
 534
 535         vsi = pf->main_vsi;
 536
 537         /* Disable double vlan by default */
 538         i40e_vsi_config_double_vlan(vsi, FALSE);
 539
 540         if (!vsi->max_macaddrs)
 541                 len = ETHER_ADDR_LEN;
 542         else
 543                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 544
 545         /* Should be after VSI initialized */
 546         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 547         if (!dev->data->mac_addrs) {
 548                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 549                                         "for storing mac address");
 550                 goto err_mac_alloc;
 551         }
 552         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 553                                         &dev->data->mac_addrs[0]);
 554
 555         /* initialize pf host driver to setup SRIOV resource if applicable */
 556         i40e_pf_host_init(dev);
 557
 558         /* register callback func to eal lib */
 559         rte_intr_callback_register(&(pci_dev->intr_handle),
 560                 i40e_dev_interrupt_handler, (void *)dev);
 561
 562         /* configure and enable device interrupt */
 563         i40e_pf_config_irq0(hw);
 564         i40e_pf_enable_irq0(hw);
 565
 566         /* enable uio intr after callback register */
 567         rte_intr_enable(&(pci_dev->intr_handle));
 568
 569         return 0;
 570
 571 err_mac_alloc:
 572         i40e_vsi_release(pf->main_vsi);
 573 err_setup_pf_switch:
 574 err_get_mac_addr:
 575 err_configure_lan_hmc:
 576         (void)i40e_shutdown_lan_hmc(hw);
 577 err_init_lan_hmc:
 578         i40e_res_pool_destroy(&pf->msix_pool);
 579 err_msix_pool_init:
 580         i40e_res_pool_destroy(&pf->qp_pool);
 581 err_qp_pool_init:
 582 err_parameter_init:
 583 err_get_capabilities:
 584         (void)i40e_shutdown_adminq(hw);
 585
 586         return ret;
 587 }
 588
 589 static int
 590 i40e_dev_configure(struct rte_eth_dev *dev)
 591 {
 592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 593         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 594         int ret;
 595
 596         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 597                 ret = i40e_fdir_setup(pf);
 598                 if (ret != I40E_SUCCESS) {
 599                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 600                         return -ENOTSUP;
 601                 }
 602                 ret = i40e_fdir_configure(dev);
 603                 if (ret < 0) {
 604                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 605                         goto err;
 606                 }
 607         } else
 608                 i40e_fdir_teardown(pf);
 609
 610         ret = i40e_dev_init_vlan(dev);
 611         if (ret < 0)
 612                 goto err;
 613
 614         /* VMDQ setup.
 615          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 616          *  RSS setting have different requirements.
 617          *  General PMD driver call sequence are NIC init, configure,
 618          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 619          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 620          *  applicable. So, VMDQ setting has to be done before
 621          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 622          *  For RSS setting, it will try to calculate actual configured RX queue
 623          *  number, which will be available after rx_queue_setup(). dev_start()
 624          *  function is good to place RSS setup.
 625          */
 626         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 627                 ret = i40e_vmdq_setup(dev);
 628                 if (ret)
 629                         goto err;
 630         }
 631         return 0;
 632 err:
 633         i40e_fdir_teardown(pf);
 634         return ret;
 635 }
 636
 637 void
 638 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 639 {
 640         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 641         uint16_t msix_vect = vsi->msix_intr;
 642         uint16_t i;
 643
 644         for (i = 0; i < vsi->nb_qps; i++) {
 645                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 646                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 647                 rte_wmb();
 648         }
 649
 650         if (vsi->type != I40E_VSI_SRIOV) {
 651                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 652                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 653                                 msix_vect - 1), 0);
 654         } else {
 655                 uint32_t reg;
 656                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 657                         vsi->user_param + (msix_vect - 1);
 658
 659                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 660         }
 661         I40E_WRITE_FLUSH(hw);
 662 }
 663
 664 static inline uint16_t
 665 i40e_calc_itr_interval(int16_t interval)
 666 {
 667         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 668                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 669
 670         /* Convert to hardware count, as writing each 1 represents 2 us */
 671         return (interval/2);
 672 }
 673
 674 void
 675 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 676 {
 677         uint32_t val;
 678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 679         uint16_t msix_vect = vsi->msix_intr;
 680         int i;
 681
 682         for (i = 0; i < vsi->nb_qps; i++)
 683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 684
 685         /* Bind all RX queues to allocated MSIX interrupt */
 686         for (i = 0; i < vsi->nb_qps; i++) {
 687                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 688                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 689                         ((vsi->base_queue + i + 1) <<
 690                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 691                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 692                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 693
 694                 if (i == vsi->nb_qps - 1)
 695                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 696                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 697         }
 698
 699         /* Write first RX queue to Link list register as the head element */
 700         if (vsi->type != I40E_VSI_SRIOV) {
 701                 uint16_t interval =
 702                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 703
 704                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 705                                                 (vsi->base_queue <<
 706                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 707                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 708
 709                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 710                                                 msix_vect - 1), interval);
 711
 712 #ifndef I40E_GLINT_CTL
 713 #define I40E_GLINT_CTL                     0x0003F800
 714 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 715 #endif
 716                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 717                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 718                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 719         } else {
 720                 uint32_t reg;
 721
 722                 /* num_msix_vectors_vf needs to minus irq0 */
 723                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 724                         vsi->user_param + (msix_vect - 1);
 725
 726                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 727                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 728                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 729         }
 730
 731         I40E_WRITE_FLUSH(hw);
 732 }
 733
 734 static void
 735 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 736 {
 737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 738         uint16_t interval = i40e_calc_itr_interval(\
 739                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 740
 741         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 742                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 743                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 744                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 745                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 746 }
 747
 748 static void
 749 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 750 {
 751         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 752
 753         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 754 }
 755
 756 static inline uint8_t
 757 i40e_parse_link_speed(uint16_t eth_link_speed)
 758 {
 759         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 760
 761         switch (eth_link_speed) {
 762         case ETH_LINK_SPEED_40G:
 763                 link_speed = I40E_LINK_SPEED_40GB;
 764                 break;
 765         case ETH_LINK_SPEED_20G:
 766                 link_speed = I40E_LINK_SPEED_20GB;
 767                 break;
 768         case ETH_LINK_SPEED_10G:
 769                 link_speed = I40E_LINK_SPEED_10GB;
 770                 break;
 771         case ETH_LINK_SPEED_1000:
 772                 link_speed = I40E_LINK_SPEED_1GB;
 773                 break;
 774         case ETH_LINK_SPEED_100:
 775                 link_speed = I40E_LINK_SPEED_100MB;
 776                 break;
 777         }
 778
 779         return link_speed;
 780 }
 781
 782 static int
 783 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 784 {
 785         enum i40e_status_code status;
 786         struct i40e_aq_get_phy_abilities_resp phy_ab;
 787         struct i40e_aq_set_phy_config phy_conf;
 788         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 789                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 790                         I40E_AQ_PHY_FLAG_LOW_POWER;
 791         const uint8_t advt = I40E_LINK_SPEED_40GB |
 792                         I40E_LINK_SPEED_10GB |
 793                         I40E_LINK_SPEED_1GB |
 794                         I40E_LINK_SPEED_100MB;
 795         int ret = -ENOTSUP;
 796
 797         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 798                                               NULL);
 799         if (status)
 800                 return ret;
 801
 802         memset(&phy_conf, 0, sizeof(phy_conf));
 803
 804         /* bits 0-2 use the values from get_phy_abilities_resp */
 805         abilities &= ~mask;
 806         abilities |= phy_ab.abilities & mask;
 807
 808         /* update ablities and speed */
 809         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 810                 phy_conf.link_speed = advt;
 811         else
 812                 phy_conf.link_speed = force_speed;
 813
 814         phy_conf.abilities = abilities;
 815
 816         /* use get_phy_abilities_resp value for the rest */
 817         phy_conf.phy_type = phy_ab.phy_type;
 818         phy_conf.eee_capability = phy_ab.eee_capability;
 819         phy_conf.eeer = phy_ab.eeer_val;
 820         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 821
 822         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 823                     phy_ab.abilities, phy_ab.link_speed);
 824         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 825                     phy_conf.abilities, phy_conf.link_speed);
 826
 827         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 828         if (status)
 829                 return ret;
 830
 831         return I40E_SUCCESS;
 832 }
 833
 834 static int
 835 i40e_apply_link_speed(struct rte_eth_dev *dev)
 836 {
 837         uint8_t speed;
 838         uint8_t abilities = 0;
 839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 840         struct rte_eth_conf *conf = &dev->data->dev_conf;
 841
 842         speed = i40e_parse_link_speed(conf->link_speed);
 843         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 844         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 845                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 846         else
 847                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 848
 849         return i40e_phy_conf_link(hw, abilities, speed);
 850 }
 851
 852 static int
 853 i40e_dev_start(struct rte_eth_dev *dev)
 854 {
 855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 857         struct i40e_vsi *main_vsi = pf->main_vsi;
 858         int ret, i;
 859
 860         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 861                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 862                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 863                              dev->data->dev_conf.link_duplex,
 864                              dev->data->port_id);
 865                 return -EINVAL;
 866         }
 867
 868         /* Initialize VSI */
 869         ret = i40e_dev_rxtx_init(pf);
 870         if (ret != I40E_SUCCESS) {
 871                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 872                 goto err_up;
 873         }
 874
 875         /* Map queues with MSIX interrupt */
 876         i40e_vsi_queues_bind_intr(main_vsi);
 877         i40e_vsi_enable_queues_intr(main_vsi);
 878
 879         /* Map VMDQ VSI queues with MSIX interrupt */
 880         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 881                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 882                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 883         }
 884
 885         /* enable FDIR MSIX interrupt */
 886         if (pf->fdir.fdir_vsi) {
 887                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 888                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 889         }
 890
 891         /* Enable all queues which have been configured */
 892         ret = i40e_dev_switch_queues(pf, TRUE);
 893         if (ret != I40E_SUCCESS) {
 894                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 895                 goto err_up;
 896         }
 897
 898         /* Enable receiving broadcast packets */
 899         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 900         if (ret != I40E_SUCCESS)
 901                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 902
 903         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 904                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 905                                                 true, NULL);
 906                 if (ret != I40E_SUCCESS)
 907                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 908         }
 909
 910         /* Apply link configure */
 911         ret = i40e_apply_link_speed(dev);
 912         if (I40E_SUCCESS != ret) {
 913                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 914                 goto err_up;
 915         }
 916
 917         return I40E_SUCCESS;
 918
 919 err_up:
 920         i40e_dev_switch_queues(pf, FALSE);
 921         i40e_dev_clear_queues(dev);
 922
 923         return ret;
 924 }
 925
 926 static void
 927 i40e_dev_stop(struct rte_eth_dev *dev)
 928 {
 929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 930         struct i40e_vsi *main_vsi = pf->main_vsi;
 931         int i;
 932
 933         /* Disable all queues */
 934         i40e_dev_switch_queues(pf, FALSE);
 935
 936         /* un-map queues with interrupt registers */
 937         i40e_vsi_disable_queues_intr(main_vsi);
 938         i40e_vsi_queues_unbind_intr(main_vsi);
 939
 940         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 941                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 942                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 943         }
 944
 945         if (pf->fdir.fdir_vsi) {
 946                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 947                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 948         }
 949         /* Clear all queues and release memory */
 950         i40e_dev_clear_queues(dev);
 951
 952         /* Set link down */
 953         i40e_dev_set_link_down(dev);
 954
 955 }
 956
 957 static void
 958 i40e_dev_close(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         uint32_t reg;
 963
 964         PMD_INIT_FUNC_TRACE();
 965
 966         i40e_dev_stop(dev);
 967
 968         /* Disable interrupt */
 969         i40e_pf_disable_irq0(hw);
 970         rte_intr_disable(&(dev->pci_dev->intr_handle));
 971
 972         /* shutdown and destroy the HMC */
 973         i40e_shutdown_lan_hmc(hw);
 974
 975         /* release all the existing VSIs and VEBs */
 976         i40e_fdir_teardown(pf);
 977         i40e_vsi_release(pf->main_vsi);
 978
 979         /* shutdown the adminq */
 980         i40e_aq_queue_shutdown(hw, true);
 981         i40e_shutdown_adminq(hw);
 982
 983         i40e_res_pool_destroy(&pf->qp_pool);
 984         i40e_res_pool_destroy(&pf->msix_pool);
 985
 986         /* force a PF reset to clean anything leftover */
 987         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 988         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 989                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 990         I40E_WRITE_FLUSH(hw);
 991 }
 992
 993 static void
 994 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998         struct i40e_vsi *vsi = pf->main_vsi;
 999         int status;
1000
1001         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1002                                                         true, NULL);
1003         if (status != I40E_SUCCESS)
1004                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1005
1006         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1007                                                         TRUE, NULL);
1008         if (status != I40E_SUCCESS)
1009                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1010
1011 }
1012
1013 static void
1014 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1015 {
1016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018         struct i40e_vsi *vsi = pf->main_vsi;
1019         int status;
1020
1021         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1022                                                         false, NULL);
1023         if (status != I40E_SUCCESS)
1024                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1025
1026         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1027                                                         false, NULL);
1028         if (status != I40E_SUCCESS)
1029                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1030 }
1031
1032 static void
1033 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1034 {
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *vsi = pf->main_vsi;
1038         int ret;
1039
1040         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1041         if (ret != I40E_SUCCESS)
1042                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1043 }
1044
1045 static void
1046 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050         struct i40e_vsi *vsi = pf->main_vsi;
1051         int ret;
1052
1053         if (dev->data->promiscuous == 1)
1054                 return; /* must remain in all_multicast mode */
1055
1056         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1057                                 vsi->seid, FALSE, NULL);
1058         if (ret != I40E_SUCCESS)
1059                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1060 }
1061
1062 /*
1063  * Set device link up.
1064  */
1065 static int
1066 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1067 {
1068         /* re-apply link speed setting */
1069         return i40e_apply_link_speed(dev);
1070 }
1071
1072 /*
1073  * Set device link down.
1074  */
1075 static int
1076 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1077 {
1078         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1079         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081
1082         return i40e_phy_conf_link(hw, abilities, speed);
1083 }
1084
1085 int
1086 i40e_dev_link_update(struct rte_eth_dev *dev,
1087                      __rte_unused int wait_to_complete)
1088 {
1089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         struct i40e_link_status link_status;
1091         struct rte_eth_link link, old;
1092         int status;
1093
1094         memset(&link, 0, sizeof(link));
1095         memset(&old, 0, sizeof(old));
1096         memset(&link_status, 0, sizeof(link_status));
1097         rte_i40e_dev_atomic_read_link_status(dev, &old);
1098
1099         /* Get link status information from hardware */
1100         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1101         if (status != I40E_SUCCESS) {
1102                 link.link_speed = ETH_LINK_SPEED_100;
1103                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1104                 PMD_DRV_LOG(ERR, "Failed to get link info");
1105                 goto out;
1106         }
1107
1108         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1109
1110         if (!link.link_status)
1111                 goto out;
1112
1113         /* i40e uses full duplex only */
1114         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1115
1116         /* Parse the link status */
1117         switch (link_status.link_speed) {
1118         case I40E_LINK_SPEED_100MB:
1119                 link.link_speed = ETH_LINK_SPEED_100;
1120                 break;
1121         case I40E_LINK_SPEED_1GB:
1122                 link.link_speed = ETH_LINK_SPEED_1000;
1123                 break;
1124         case I40E_LINK_SPEED_10GB:
1125                 link.link_speed = ETH_LINK_SPEED_10G;
1126                 break;
1127         case I40E_LINK_SPEED_20GB:
1128                 link.link_speed = ETH_LINK_SPEED_20G;
1129                 break;
1130         case I40E_LINK_SPEED_40GB:
1131                 link.link_speed = ETH_LINK_SPEED_40G;
1132                 break;
1133         default:
1134                 link.link_speed = ETH_LINK_SPEED_100;
1135                 break;
1136         }
1137
1138 out:
1139         rte_i40e_dev_atomic_write_link_status(dev, &link);
1140         if (link.link_status == old.link_status)
1141                 return -1;
1142
1143         return 0;
1144 }
1145
1146 /* Get all the statistics of a VSI */
1147 void
1148 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1149 {
1150         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1151         struct i40e_eth_stats *nes = &vsi->eth_stats;
1152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1153         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1154
1155         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1156                             vsi->offset_loaded, &oes->rx_bytes,
1157                             &nes->rx_bytes);
1158         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1159                             vsi->offset_loaded, &oes->rx_unicast,
1160                             &nes->rx_unicast);
1161         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1162                             vsi->offset_loaded, &oes->rx_multicast,
1163                             &nes->rx_multicast);
1164         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1165                             vsi->offset_loaded, &oes->rx_broadcast,
1166                             &nes->rx_broadcast);
1167         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1168                             &oes->rx_discards, &nes->rx_discards);
1169         /* GLV_REPC not supported */
1170         /* GLV_RMPC not supported */
1171         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1172                             &oes->rx_unknown_protocol,
1173                             &nes->rx_unknown_protocol);
1174         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1175                             vsi->offset_loaded, &oes->tx_bytes,
1176                             &nes->tx_bytes);
1177         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1178                             vsi->offset_loaded, &oes->tx_unicast,
1179                             &nes->tx_unicast);
1180         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1181                             vsi->offset_loaded, &oes->tx_multicast,
1182                             &nes->tx_multicast);
1183         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1184                             vsi->offset_loaded,  &oes->tx_broadcast,
1185                             &nes->tx_broadcast);
1186         /* GLV_TDPC not supported */
1187         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1188                             &oes->tx_errors, &nes->tx_errors);
1189         vsi->offset_loaded = true;
1190
1191         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1192                     vsi->vsi_id);
1193         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1194         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1195         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1196         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1197         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1198         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1199                     nes->rx_unknown_protocol);
1200         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1201         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1202         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1203         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1204         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1205         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1206         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1207                     vsi->vsi_id);
1208 }
1209
1210 /* Get all statistics of a port */
1211 static void
1212 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1213 {
1214         uint32_t i;
1215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1218         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1219
1220         /* Get statistics of struct i40e_eth_stats */
1221         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1222                             I40E_GLPRT_GORCL(hw->port),
1223                             pf->offset_loaded, &os->eth.rx_bytes,
1224                             &ns->eth.rx_bytes);
1225         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1226                             I40E_GLPRT_UPRCL(hw->port),
1227                             pf->offset_loaded, &os->eth.rx_unicast,
1228                             &ns->eth.rx_unicast);
1229         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1230                             I40E_GLPRT_MPRCL(hw->port),
1231                             pf->offset_loaded, &os->eth.rx_multicast,
1232                             &ns->eth.rx_multicast);
1233         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1234                             I40E_GLPRT_BPRCL(hw->port),
1235                             pf->offset_loaded, &os->eth.rx_broadcast,
1236                             &ns->eth.rx_broadcast);
1237         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1238                             pf->offset_loaded, &os->eth.rx_discards,
1239                             &ns->eth.rx_discards);
1240         /* GLPRT_REPC not supported */
1241         /* GLPRT_RMPC not supported */
1242         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1243                             pf->offset_loaded,
1244                             &os->eth.rx_unknown_protocol,
1245                             &ns->eth.rx_unknown_protocol);
1246         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1247                             I40E_GLPRT_GOTCL(hw->port),
1248                             pf->offset_loaded, &os->eth.tx_bytes,
1249                             &ns->eth.tx_bytes);
1250         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1251                             I40E_GLPRT_UPTCL(hw->port),
1252                             pf->offset_loaded, &os->eth.tx_unicast,
1253                             &ns->eth.tx_unicast);
1254         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1255                             I40E_GLPRT_MPTCL(hw->port),
1256                             pf->offset_loaded, &os->eth.tx_multicast,
1257                             &ns->eth.tx_multicast);
1258         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1259                             I40E_GLPRT_BPTCL(hw->port),
1260                             pf->offset_loaded, &os->eth.tx_broadcast,
1261                             &ns->eth.tx_broadcast);
1262         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1263                             pf->offset_loaded, &os->eth.tx_discards,
1264                             &ns->eth.tx_discards);
1265         /* GLPRT_TEPC not supported */
1266
1267         /* additional port specific stats */
1268         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1269                             pf->offset_loaded, &os->tx_dropped_link_down,
1270                             &ns->tx_dropped_link_down);
1271         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1272                             pf->offset_loaded, &os->crc_errors,
1273                             &ns->crc_errors);
1274         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1275                             pf->offset_loaded, &os->illegal_bytes,
1276                             &ns->illegal_bytes);
1277         /* GLPRT_ERRBC not supported */
1278         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1279                             pf->offset_loaded, &os->mac_local_faults,
1280                             &ns->mac_local_faults);
1281         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1282                             pf->offset_loaded, &os->mac_remote_faults,
1283                             &ns->mac_remote_faults);
1284         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1285                             pf->offset_loaded, &os->rx_length_errors,
1286                             &ns->rx_length_errors);
1287         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1288                             pf->offset_loaded, &os->link_xon_rx,
1289                             &ns->link_xon_rx);
1290         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1291                             pf->offset_loaded, &os->link_xoff_rx,
1292                             &ns->link_xoff_rx);
1293         for (i = 0; i < 8; i++) {
1294                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1295                                     pf->offset_loaded,
1296                                     &os->priority_xon_rx[i],
1297                                     &ns->priority_xon_rx[i]);
1298                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1299                                     pf->offset_loaded,
1300                                     &os->priority_xoff_rx[i],
1301                                     &ns->priority_xoff_rx[i]);
1302         }
1303         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1304                             pf->offset_loaded, &os->link_xon_tx,
1305                             &ns->link_xon_tx);
1306         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1307                             pf->offset_loaded, &os->link_xoff_tx,
1308                             &ns->link_xoff_tx);
1309         for (i = 0; i < 8; i++) {
1310                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1311                                     pf->offset_loaded,
1312                                     &os->priority_xon_tx[i],
1313                                     &ns->priority_xon_tx[i]);
1314                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1315                                     pf->offset_loaded,
1316                                     &os->priority_xoff_tx[i],
1317                                     &ns->priority_xoff_tx[i]);
1318                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1319                                     pf->offset_loaded,
1320                                     &os->priority_xon_2_xoff[i],
1321                                     &ns->priority_xon_2_xoff[i]);
1322         }
1323         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1324                             I40E_GLPRT_PRC64L(hw->port),
1325                             pf->offset_loaded, &os->rx_size_64,
1326                             &ns->rx_size_64);
1327         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1328                             I40E_GLPRT_PRC127L(hw->port),
1329                             pf->offset_loaded, &os->rx_size_127,
1330                             &ns->rx_size_127);
1331         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1332                             I40E_GLPRT_PRC255L(hw->port),
1333                             pf->offset_loaded, &os->rx_size_255,
1334                             &ns->rx_size_255);
1335         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1336                             I40E_GLPRT_PRC511L(hw->port),
1337                             pf->offset_loaded, &os->rx_size_511,
1338                             &ns->rx_size_511);
1339         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1340                             I40E_GLPRT_PRC1023L(hw->port),
1341                             pf->offset_loaded, &os->rx_size_1023,
1342                             &ns->rx_size_1023);
1343         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1344                             I40E_GLPRT_PRC1522L(hw->port),
1345                             pf->offset_loaded, &os->rx_size_1522,
1346                             &ns->rx_size_1522);
1347         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1348                             I40E_GLPRT_PRC9522L(hw->port),
1349                             pf->offset_loaded, &os->rx_size_big,
1350                             &ns->rx_size_big);
1351         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1352                             pf->offset_loaded, &os->rx_undersize,
1353                             &ns->rx_undersize);
1354         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1355                             pf->offset_loaded, &os->rx_fragments,
1356                             &ns->rx_fragments);
1357         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1358                             pf->offset_loaded, &os->rx_oversize,
1359                             &ns->rx_oversize);
1360         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1361                             pf->offset_loaded, &os->rx_jabber,
1362                             &ns->rx_jabber);
1363         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1364                             I40E_GLPRT_PTC64L(hw->port),
1365                             pf->offset_loaded, &os->tx_size_64,
1366                             &ns->tx_size_64);
1367         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1368                             I40E_GLPRT_PTC127L(hw->port),
1369                             pf->offset_loaded, &os->tx_size_127,
1370                             &ns->tx_size_127);
1371         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1372                             I40E_GLPRT_PTC255L(hw->port),
1373                             pf->offset_loaded, &os->tx_size_255,
1374                             &ns->tx_size_255);
1375         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1376                             I40E_GLPRT_PTC511L(hw->port),
1377                             pf->offset_loaded, &os->tx_size_511,
1378                             &ns->tx_size_511);
1379         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1380                             I40E_GLPRT_PTC1023L(hw->port),
1381                             pf->offset_loaded, &os->tx_size_1023,
1382                             &ns->tx_size_1023);
1383         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1384                             I40E_GLPRT_PTC1522L(hw->port),
1385                             pf->offset_loaded, &os->tx_size_1522,
1386                             &ns->tx_size_1522);
1387         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1388                             I40E_GLPRT_PTC9522L(hw->port),
1389                             pf->offset_loaded, &os->tx_size_big,
1390                             &ns->tx_size_big);
1391         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1392                            pf->offset_loaded,
1393                            &os->fd_sb_match, &ns->fd_sb_match);
1394         /* GLPRT_MSPDC not supported */
1395         /* GLPRT_XEC not supported */
1396
1397         pf->offset_loaded = true;
1398
1399         if (pf->main_vsi)
1400                 i40e_update_vsi_stats(pf->main_vsi);
1401
1402         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1403                                                 ns->eth.rx_broadcast;
1404         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1405                                                 ns->eth.tx_broadcast;
1406         stats->ibytes   = ns->eth.rx_bytes;
1407         stats->obytes   = ns->eth.tx_bytes;
1408         stats->oerrors  = ns->eth.tx_errors;
1409         stats->imcasts  = ns->eth.rx_multicast;
1410         stats->fdirmatch = ns->fd_sb_match;
1411
1412         /* Rx Errors */
1413         stats->ibadcrc  = ns->crc_errors;
1414         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1415                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1416         stats->imissed  = ns->eth.rx_discards;
1417         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1418
1419         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1420         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1421         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1422         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1423         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1424         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1425         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1426                     ns->eth.rx_unknown_protocol);
1427         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1428         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1429         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1430         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1431         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1432         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1433
1434         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1435                     ns->tx_dropped_link_down);
1436         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1437         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1438                     ns->illegal_bytes);
1439         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1440         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1441                     ns->mac_local_faults);
1442         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1443                     ns->mac_remote_faults);
1444         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1445                     ns->rx_length_errors);
1446         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1447         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1448         for (i = 0; i < 8; i++) {
1449                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1450                                 i, ns->priority_xon_rx[i]);
1451                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1452                                 i, ns->priority_xoff_rx[i]);
1453         }
1454         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1455         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1456         for (i = 0; i < 8; i++) {
1457                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1458                                 i, ns->priority_xon_tx[i]);
1459                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1460                                 i, ns->priority_xoff_tx[i]);
1461                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1462                                 i, ns->priority_xon_2_xoff[i]);
1463         }
1464         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1465         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1466         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1467         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1468         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1469         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1470         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1471         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1472         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1473         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1474         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1475         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1476         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1477         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1478         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1479         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1480         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1481         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1482         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1483                         ns->mac_short_packet_dropped);
1484         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1485                     ns->checksum_error);
1486         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1487         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1488 }
1489
1490 /* Reset the statistics */
1491 static void
1492 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1493 {
1494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495
1496         /* It results in reloading the start point of each counter */
1497         pf->offset_loaded = false;
1498 }
1499
1500 static int
1501 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1502                                  __rte_unused uint16_t queue_id,
1503                                  __rte_unused uint8_t stat_idx,
1504                                  __rte_unused uint8_t is_rx)
1505 {
1506         PMD_INIT_FUNC_TRACE();
1507
1508         return -ENOSYS;
1509 }
1510
1511 static void
1512 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1513 {
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_vsi *vsi = pf->main_vsi;
1516
1517         dev_info->max_rx_queues = vsi->nb_qps;
1518         dev_info->max_tx_queues = vsi->nb_qps;
1519         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1520         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1521         dev_info->max_mac_addrs = vsi->max_macaddrs;
1522         dev_info->max_vfs = dev->pci_dev->max_vfs;
1523         dev_info->rx_offload_capa =
1524                 DEV_RX_OFFLOAD_VLAN_STRIP |
1525                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1526                 DEV_RX_OFFLOAD_UDP_CKSUM |
1527                 DEV_RX_OFFLOAD_TCP_CKSUM;
1528         dev_info->tx_offload_capa =
1529                 DEV_TX_OFFLOAD_VLAN_INSERT |
1530                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1531                 DEV_TX_OFFLOAD_UDP_CKSUM |
1532                 DEV_TX_OFFLOAD_TCP_CKSUM |
1533                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1534                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1535         dev_info->reta_size = pf->hash_lut_size;
1536         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1537
1538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1539                 .rx_thresh = {
1540                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1541                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1542                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1543                 },
1544                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1545                 .rx_drop_en = 0,
1546         };
1547
1548         dev_info->default_txconf = (struct rte_eth_txconf) {
1549                 .tx_thresh = {
1550                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1551                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1552                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1553                 },
1554                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1555                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1556                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1557                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1558         };
1559
1560         if (pf->flags | I40E_FLAG_VMDQ) {
1561                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1562                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1563                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1564                                                 pf->max_nb_vmdq_vsi;
1565                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1566                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1567                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1568         }
1569 }
1570
1571 static int
1572 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1573 {
1574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1575         struct i40e_vsi *vsi = pf->main_vsi;
1576         PMD_INIT_FUNC_TRACE();
1577
1578         if (on)
1579                 return i40e_vsi_add_vlan(vsi, vlan_id);
1580         else
1581                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1582 }
1583
1584 static void
1585 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1586                    __rte_unused uint16_t tpid)
1587 {
1588         PMD_INIT_FUNC_TRACE();
1589 }
1590
1591 static void
1592 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1593 {
1594         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1595         struct i40e_vsi *vsi = pf->main_vsi;
1596
1597         if (mask & ETH_VLAN_STRIP_MASK) {
1598                 /* Enable or disable VLAN stripping */
1599                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1600                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1601                 else
1602                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1603         }
1604
1605         if (mask & ETH_VLAN_EXTEND_MASK) {
1606                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1607                         i40e_vsi_config_double_vlan(vsi, TRUE);
1608                 else
1609                         i40e_vsi_config_double_vlan(vsi, FALSE);
1610         }
1611 }
1612
1613 static void
1614 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1615                           __rte_unused uint16_t queue,
1616                           __rte_unused int on)
1617 {
1618         PMD_INIT_FUNC_TRACE();
1619 }
1620
1621 static int
1622 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1623 {
1624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625         struct i40e_vsi *vsi = pf->main_vsi;
1626         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1627         struct i40e_vsi_vlan_pvid_info info;
1628
1629         memset(&info, 0, sizeof(info));
1630         info.on = on;
1631         if (info.on)
1632                 info.config.pvid = pvid;
1633         else {
1634                 info.config.reject.tagged =
1635                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1636                 info.config.reject.untagged =
1637                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1638         }
1639
1640         return i40e_vsi_vlan_pvid_set(vsi, &info);
1641 }
1642
1643 static int
1644 i40e_dev_led_on(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         uint32_t mode = i40e_led_get(hw);
1648
1649         if (mode == 0)
1650                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1651
1652         return 0;
1653 }
1654
1655 static int
1656 i40e_dev_led_off(struct rte_eth_dev *dev)
1657 {
1658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         uint32_t mode = i40e_led_get(hw);
1660
1661         if (mode != 0)
1662                 i40e_led_set(hw, 0, false);
1663
1664         return 0;
1665 }
1666
1667 static int
1668 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1669                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1670 {
1671         PMD_INIT_FUNC_TRACE();
1672
1673         return -ENOSYS;
1674 }
1675
1676 static int
1677 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1678                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1679 {
1680         PMD_INIT_FUNC_TRACE();
1681
1682         return -ENOSYS;
1683 }
1684
1685 /* Add a MAC address, and update filters */
1686 static void
1687 i40e_macaddr_add(struct rte_eth_dev *dev,
1688                  struct ether_addr *mac_addr,
1689                  __rte_unused uint32_t index,
1690                  uint32_t pool)
1691 {
1692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1693         struct i40e_mac_filter_info mac_filter;
1694         struct i40e_vsi *vsi;
1695         int ret;
1696
1697         /* If VMDQ not enabled or configured, return */
1698         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1699                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1700                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1701                         pool);
1702                 return;
1703         }
1704
1705         if (pool > pf->nb_cfg_vmdq_vsi) {
1706                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1707                                 pool, pf->nb_cfg_vmdq_vsi);
1708                 return;
1709         }
1710
1711         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1712         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1713
1714         if (pool == 0)
1715                 vsi = pf->main_vsi;
1716         else
1717                 vsi = pf->vmdq[pool - 1].vsi;
1718
1719         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1720         if (ret != I40E_SUCCESS) {
1721                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1722                 return;
1723         }
1724 }
1725
1726 /* Remove a MAC address, and update filters */
1727 static void
1728 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1729 {
1730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1731         struct i40e_vsi *vsi;
1732         struct rte_eth_dev_data *data = dev->data;
1733         struct ether_addr *macaddr;
1734         int ret;
1735         uint32_t i;
1736         uint64_t pool_sel;
1737
1738         macaddr = &(data->mac_addrs[index]);
1739
1740         pool_sel = dev->data->mac_pool_sel[index];
1741
1742         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1743                 if (pool_sel & (1ULL << i)) {
1744                         if (i == 0)
1745                                 vsi = pf->main_vsi;
1746                         else {
1747                                 /* No VMDQ pool enabled or configured */
1748                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1749                                         (i > pf->nb_cfg_vmdq_vsi)) {
1750                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1751                                                         "/configured");
1752                                         return;
1753                                 }
1754                                 vsi = pf->vmdq[i - 1].vsi;
1755                         }
1756                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1757
1758                         if (ret) {
1759                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1760                                 return;
1761                         }
1762                 }
1763         }
1764 }
1765
1766 /* Set perfect match or hash match of MAC and VLAN for a VF */
1767 static int
1768 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1769                  struct rte_eth_mac_filter *filter,
1770                  bool add)
1771 {
1772         struct i40e_hw *hw;
1773         struct i40e_mac_filter_info mac_filter;
1774         struct ether_addr old_mac;
1775         struct ether_addr *new_mac;
1776         struct i40e_pf_vf *vf = NULL;
1777         uint16_t vf_id;
1778         int ret;
1779
1780         if (pf == NULL) {
1781                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1782                 return -EINVAL;
1783         }
1784         hw = I40E_PF_TO_HW(pf);
1785
1786         if (filter == NULL) {
1787                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1788                 return -EINVAL;
1789         }
1790
1791         new_mac = &filter->mac_addr;
1792
1793         if (is_zero_ether_addr(new_mac)) {
1794                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1795                 return -EINVAL;
1796         }
1797
1798         vf_id = filter->dst_id;
1799
1800         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1801                 PMD_DRV_LOG(ERR, "Invalid argument.");
1802                 return -EINVAL;
1803         }
1804         vf = &pf->vfs[vf_id];
1805
1806         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1807                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1808                 return -EINVAL;
1809         }
1810
1811         if (add) {
1812                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1813                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1814                                 ETHER_ADDR_LEN);
1815                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1816                                  ETHER_ADDR_LEN);
1817
1818                 mac_filter.filter_type = filter->filter_type;
1819                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1820                 if (ret != I40E_SUCCESS) {
1821                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1822                         return -1;
1823                 }
1824                 ether_addr_copy(new_mac, &pf->dev_addr);
1825         } else {
1826                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1827                                 ETHER_ADDR_LEN);
1828                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1829                 if (ret != I40E_SUCCESS) {
1830                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1831                         return -1;
1832                 }
1833
1834                 /* Clear device address as it has been removed */
1835                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1836                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1837         }
1838
1839         return 0;
1840 }
1841
1842 /* MAC filter handle */
1843 static int
1844 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1845                 void *arg)
1846 {
1847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1848         struct rte_eth_mac_filter *filter;
1849         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1850         int ret = I40E_NOT_SUPPORTED;
1851
1852         filter = (struct rte_eth_mac_filter *)(arg);
1853
1854         switch (filter_op) {
1855         case RTE_ETH_FILTER_NOP:
1856                 ret = I40E_SUCCESS;
1857                 break;
1858         case RTE_ETH_FILTER_ADD:
1859                 i40e_pf_disable_irq0(hw);
1860                 if (filter->is_vf)
1861                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1862                 i40e_pf_enable_irq0(hw);
1863                 break;
1864         case RTE_ETH_FILTER_DELETE:
1865                 i40e_pf_disable_irq0(hw);
1866                 if (filter->is_vf)
1867                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1868                 i40e_pf_enable_irq0(hw);
1869                 break;
1870         default:
1871                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1872                 ret = I40E_ERR_PARAM;
1873                 break;
1874         }
1875
1876         return ret;
1877 }
1878
1879 static int
1880 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1881                          struct rte_eth_rss_reta_entry64 *reta_conf,
1882                          uint16_t reta_size)
1883 {
1884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         uint32_t lut, l;
1887         uint16_t i, j, lut_size = pf->hash_lut_size;
1888         uint16_t idx, shift;
1889         uint8_t mask;
1890
1891         if (reta_size != lut_size ||
1892                 reta_size > ETH_RSS_RETA_SIZE_512) {
1893                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1894                         "(%d) doesn't match the number hardware can supported "
1895                                         "(%d)\n", reta_size, lut_size);
1896                 return -EINVAL;
1897         }
1898
1899         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1900                 idx = i / RTE_RETA_GROUP_SIZE;
1901                 shift = i % RTE_RETA_GROUP_SIZE;
1902                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1903                                                 I40E_4_BIT_MASK);
1904                 if (!mask)
1905                         continue;
1906                 if (mask == I40E_4_BIT_MASK)
1907                         l = 0;
1908                 else
1909                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1910                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1911                         if (mask & (0x1 << j))
1912                                 lut |= reta_conf[idx].reta[shift + j] <<
1913                                                         (CHAR_BIT * j);
1914                         else
1915                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1916                 }
1917                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1918         }
1919
1920         return 0;
1921 }
1922
1923 static int
1924 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1925                         struct rte_eth_rss_reta_entry64 *reta_conf,
1926                         uint16_t reta_size)
1927 {
1928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1929         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         uint32_t lut;
1931         uint16_t i, j, lut_size = pf->hash_lut_size;
1932         uint16_t idx, shift;
1933         uint8_t mask;
1934
1935         if (reta_size != lut_size ||
1936                 reta_size > ETH_RSS_RETA_SIZE_512) {
1937                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1938                         "(%d) doesn't match the number hardware can supported "
1939                                         "(%d)\n", reta_size, lut_size);
1940                 return -EINVAL;
1941         }
1942
1943         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1944                 idx = i / RTE_RETA_GROUP_SIZE;
1945                 shift = i % RTE_RETA_GROUP_SIZE;
1946                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1947                                                 I40E_4_BIT_MASK);
1948                 if (!mask)
1949                         continue;
1950
1951                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1952                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1953                         if (mask & (0x1 << j))
1954                                 reta_conf[idx].reta[shift + j] = ((lut >>
1955                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1956                 }
1957         }
1958
1959         return 0;
1960 }
1961
1962 /**
1963  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1964  * @hw:   pointer to the HW structure
1965  * @mem:  pointer to mem struct to fill out
1966  * @size: size of memory requested
1967  * @alignment: what to align the allocation to
1968  **/
1969 enum i40e_status_code
1970 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1971                         struct i40e_dma_mem *mem,
1972                         u64 size,
1973                         u32 alignment)
1974 {
1975         static uint64_t id = 0;
1976         const struct rte_memzone *mz = NULL;
1977         char z_name[RTE_MEMZONE_NAMESIZE];
1978
1979         if (!mem)
1980                 return I40E_ERR_PARAM;
1981
1982         id++;
1983         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1984 #ifdef RTE_LIBRTE_XEN_DOM0
1985         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1986                                                         RTE_PGSIZE_2M);
1987 #else
1988         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1989 #endif
1990         if (!mz)
1991                 return I40E_ERR_NO_MEMORY;
1992
1993         mem->id = id;
1994         mem->size = size;
1995         mem->va = mz->addr;
1996 #ifdef RTE_LIBRTE_XEN_DOM0
1997         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1998 #else
1999         mem->pa = mz->phys_addr;
2000 #endif
2001
2002         return I40E_SUCCESS;
2003 }
2004
2005 /**
2006  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2007  * @hw:   pointer to the HW structure
2008  * @mem:  ptr to mem struct to free
2009  **/
2010 enum i40e_status_code
2011 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2012                     struct i40e_dma_mem *mem)
2013 {
2014         if (!mem || !mem->va)
2015                 return I40E_ERR_PARAM;
2016
2017         mem->va = NULL;
2018         mem->pa = (u64)0;
2019
2020         return I40E_SUCCESS;
2021 }
2022
2023 /**
2024  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2025  * @hw:   pointer to the HW structure
2026  * @mem:  pointer to mem struct to fill out
2027  * @size: size of memory requested
2028  **/
2029 enum i40e_status_code
2030 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2031                          struct i40e_virt_mem *mem,
2032                          u32 size)
2033 {
2034         if (!mem)
2035                 return I40E_ERR_PARAM;
2036
2037         mem->size = size;
2038         mem->va = rte_zmalloc("i40e", size, 0);
2039
2040         if (mem->va)
2041                 return I40E_SUCCESS;
2042         else
2043                 return I40E_ERR_NO_MEMORY;
2044 }
2045
2046 /**
2047  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2048  * @hw:   pointer to the HW structure
2049  * @mem:  pointer to mem struct to free
2050  **/
2051 enum i40e_status_code
2052 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2053                      struct i40e_virt_mem *mem)
2054 {
2055         if (!mem)
2056                 return I40E_ERR_PARAM;
2057
2058         rte_free(mem->va);
2059         mem->va = NULL;
2060
2061         return I40E_SUCCESS;
2062 }
2063
2064 void
2065 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2066 {
2067         rte_spinlock_init(&sp->spinlock);
2068 }
2069
2070 void
2071 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2072 {
2073         rte_spinlock_lock(&sp->spinlock);
2074 }
2075
2076 void
2077 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2078 {
2079         rte_spinlock_unlock(&sp->spinlock);
2080 }
2081
2082 void
2083 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2084 {
2085         return;
2086 }
2087
2088 /**
2089  * Get the hardware capabilities, which will be parsed
2090  * and saved into struct i40e_hw.
2091  */
2092 static int
2093 i40e_get_cap(struct i40e_hw *hw)
2094 {
2095         struct i40e_aqc_list_capabilities_element_resp *buf;
2096         uint16_t len, size = 0;
2097         int ret;
2098
2099         /* Calculate a huge enough buff for saving response data temporarily */
2100         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2101                                                 I40E_MAX_CAP_ELE_NUM;
2102         buf = rte_zmalloc("i40e", len, 0);
2103         if (!buf) {
2104                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2105                 return I40E_ERR_NO_MEMORY;
2106         }
2107
2108         /* Get, parse the capabilities and save it to hw */
2109         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2110                         i40e_aqc_opc_list_func_capabilities, NULL);
2111         if (ret != I40E_SUCCESS)
2112                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2113
2114         /* Free the temporary buffer after being used */
2115         rte_free(buf);
2116
2117         return ret;
2118 }
2119
2120 static int
2121 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2122 {
2123         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2125         uint16_t sum_queues = 0, sum_vsis, left_queues;
2126
2127         /* First check if FW support SRIOV */
2128         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2129                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2130                 return -EINVAL;
2131         }
2132
2133         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2134         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2135         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2136         /* Allocate queues for pf */
2137         if (hw->func_caps.rss) {
2138                 pf->flags |= I40E_FLAG_RSS;
2139                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2140                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2141                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2142         } else
2143                 pf->lan_nb_qps = 1;
2144         sum_queues = pf->lan_nb_qps;
2145         /* Default VSI is not counted in */
2146         sum_vsis = 0;
2147         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2148
2149         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2150                 pf->flags |= I40E_FLAG_SRIOV;
2151                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2152                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2153                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2154                                      "max supported %u.",
2155                                      dev->pci_dev->max_vfs,
2156                                      hw->func_caps.num_vfs);
2157                         return -EINVAL;
2158                 }
2159                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2160                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2161                                      "max support %u queues.",
2162                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2163                         return -EINVAL;
2164                 }
2165                 pf->vf_num = dev->pci_dev->max_vfs;
2166                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2167                 sum_vsis   += pf->vf_num;
2168                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2169                              pf->vf_num, pf->vf_nb_qps);
2170         } else
2171                 pf->vf_num = 0;
2172
2173         if (hw->func_caps.vmdq) {
2174                 pf->flags |= I40E_FLAG_VMDQ;
2175                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2176                 pf->max_nb_vmdq_vsi = 1;
2177                 /*
2178                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2179                  * later.
2180                  */
2181                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2182                 sum_vsis += pf->max_nb_vmdq_vsi;
2183         } else {
2184                 pf->vmdq_nb_qps = 0;
2185                 pf->max_nb_vmdq_vsi = 0;
2186         }
2187         pf->nb_cfg_vmdq_vsi = 0;
2188
2189         if (hw->func_caps.fd) {
2190                 pf->flags |= I40E_FLAG_FDIR;
2191                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2192                 /**
2193                  * Each flow director consumes one VSI and one queue,
2194                  * but can't calculate out predictably here.
2195                  */
2196         }
2197
2198         if (sum_vsis > pf->max_num_vsi ||
2199                 sum_queues > hw->func_caps.num_rx_qp) {
2200                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2201                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2202                              pf->max_num_vsi, sum_vsis);
2203                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2204                              hw->func_caps.num_rx_qp, sum_queues);
2205                 return -EINVAL;
2206         }
2207
2208         /* Adjust VMDQ setting to support as many VMs as possible */
2209         if (pf->flags & I40E_FLAG_VMDQ) {
2210                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2211
2212                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2213                                         pf->max_num_vsi - sum_vsis);
2214
2215                 /* Limit the max VMDQ number that rte_ether that can support  */
2216                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2217                                         ETH_64_POOLS - 1);
2218
2219                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2220                                 pf->max_nb_vmdq_vsi);
2221                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2222         }
2223
2224         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2225          * cause */
2226         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2227                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2228                              sum_vsis, hw->func_caps.num_msix_vectors);
2229                 return -EINVAL;
2230         }
2231         return I40E_SUCCESS;
2232 }
2233
2234 static int
2235 i40e_pf_get_switch_config(struct i40e_pf *pf)
2236 {
2237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2238         struct i40e_aqc_get_switch_config_resp *switch_config;
2239         struct i40e_aqc_switch_config_element_resp *element;
2240         uint16_t start_seid = 0, num_reported;
2241         int ret;
2242
2243         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2244                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2245         if (!switch_config) {
2246                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2247                 return -ENOMEM;
2248         }
2249
2250         /* Get the switch configurations */
2251         ret = i40e_aq_get_switch_config(hw, switch_config,
2252                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2253         if (ret != I40E_SUCCESS) {
2254                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2255                 goto fail;
2256         }
2257         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2258         if (num_reported != 1) { /* The number should be 1 */
2259                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2260                 goto fail;
2261         }
2262
2263         /* Parse the switch configuration elements */
2264         element = &(switch_config->element[0]);
2265         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2266                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2267                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2268         } else
2269                 PMD_DRV_LOG(INFO, "Unknown element type");
2270
2271 fail:
2272         rte_free(switch_config);
2273
2274         return ret;
2275 }
2276
2277 static int
2278 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2279                         uint32_t num)
2280 {
2281         struct pool_entry *entry;
2282
2283         if (pool == NULL || num == 0)
2284                 return -EINVAL;
2285
2286         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2287         if (entry == NULL) {
2288                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2289                 return -ENOMEM;
2290         }
2291
2292         /* queue heap initialize */
2293         pool->num_free = num;
2294         pool->num_alloc = 0;
2295         pool->base = base;
2296         LIST_INIT(&pool->alloc_list);
2297         LIST_INIT(&pool->free_list);
2298
2299         /* Initialize element  */
2300         entry->base = 0;
2301         entry->len = num;
2302
2303         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2304         return 0;
2305 }
2306
2307 static void
2308 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2309 {
2310         struct pool_entry *entry;
2311
2312         if (pool == NULL)
2313                 return;
2314
2315         LIST_FOREACH(entry, &pool->alloc_list, next) {
2316                 LIST_REMOVE(entry, next);
2317                 rte_free(entry);
2318         }
2319
2320         LIST_FOREACH(entry, &pool->free_list, next) {
2321                 LIST_REMOVE(entry, next);
2322                 rte_free(entry);
2323         }
2324
2325         pool->num_free = 0;
2326         pool->num_alloc = 0;
2327         pool->base = 0;
2328         LIST_INIT(&pool->alloc_list);
2329         LIST_INIT(&pool->free_list);
2330 }
2331
2332 static int
2333 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2334                        uint32_t base)
2335 {
2336         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2337         uint32_t pool_offset;
2338         int insert;
2339
2340         if (pool == NULL) {
2341                 PMD_DRV_LOG(ERR, "Invalid parameter");
2342                 return -EINVAL;
2343         }
2344
2345         pool_offset = base - pool->base;
2346         /* Lookup in alloc list */
2347         LIST_FOREACH(entry, &pool->alloc_list, next) {
2348                 if (entry->base == pool_offset) {
2349                         valid_entry = entry;
2350                         LIST_REMOVE(entry, next);
2351                         break;
2352                 }
2353         }
2354
2355         /* Not find, return */
2356         if (valid_entry == NULL) {
2357                 PMD_DRV_LOG(ERR, "Failed to find entry");
2358                 return -EINVAL;
2359         }
2360
2361         /**
2362          * Found it, move it to free list  and try to merge.
2363          * In order to make merge easier, always sort it by qbase.
2364          * Find adjacent prev and last entries.
2365          */
2366         prev = next = NULL;
2367         LIST_FOREACH(entry, &pool->free_list, next) {
2368                 if (entry->base > valid_entry->base) {
2369                         next = entry;
2370                         break;
2371                 }
2372                 prev = entry;
2373         }
2374
2375         insert = 0;
2376         /* Try to merge with next one*/
2377         if (next != NULL) {
2378                 /* Merge with next one */
2379                 if (valid_entry->base + valid_entry->len == next->base) {
2380                         next->base = valid_entry->base;
2381                         next->len += valid_entry->len;
2382                         rte_free(valid_entry);
2383                         valid_entry = next;
2384                         insert = 1;
2385                 }
2386         }
2387
2388         if (prev != NULL) {
2389                 /* Merge with previous one */
2390                 if (prev->base + prev->len == valid_entry->base) {
2391                         prev->len += valid_entry->len;
2392                         /* If it merge with next one, remove next node */
2393                         if (insert == 1) {
2394                                 LIST_REMOVE(valid_entry, next);
2395                                 rte_free(valid_entry);
2396                         } else {
2397                                 rte_free(valid_entry);
2398                                 insert = 1;
2399                         }
2400                 }
2401         }
2402
2403         /* Not find any entry to merge, insert */
2404         if (insert == 0) {
2405                 if (prev != NULL)
2406                         LIST_INSERT_AFTER(prev, valid_entry, next);
2407                 else if (next != NULL)
2408                         LIST_INSERT_BEFORE(next, valid_entry, next);
2409                 else /* It's empty list, insert to head */
2410                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2411         }
2412
2413         pool->num_free += valid_entry->len;
2414         pool->num_alloc -= valid_entry->len;
2415
2416         return 0;
2417 }
2418
2419 static int
2420 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2421                        uint16_t num)
2422 {
2423         struct pool_entry *entry, *valid_entry;
2424
2425         if (pool == NULL || num == 0) {
2426                 PMD_DRV_LOG(ERR, "Invalid parameter");
2427                 return -EINVAL;
2428         }
2429
2430         if (pool->num_free < num) {
2431                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2432                             num, pool->num_free);
2433                 return -ENOMEM;
2434         }
2435
2436         valid_entry = NULL;
2437         /* Lookup  in free list and find most fit one */
2438         LIST_FOREACH(entry, &pool->free_list, next) {
2439                 if (entry->len >= num) {
2440                         /* Find best one */
2441                         if (entry->len == num) {
2442                                 valid_entry = entry;
2443                                 break;
2444                         }
2445                         if (valid_entry == NULL || valid_entry->len > entry->len)
2446                                 valid_entry = entry;
2447                 }
2448         }
2449
2450         /* Not find one to satisfy the request, return */
2451         if (valid_entry == NULL) {
2452                 PMD_DRV_LOG(ERR, "No valid entry found");
2453                 return -ENOMEM;
2454         }
2455         /**
2456          * The entry have equal queue number as requested,
2457          * remove it from alloc_list.
2458          */
2459         if (valid_entry->len == num) {
2460                 LIST_REMOVE(valid_entry, next);
2461         } else {
2462                 /**
2463                  * The entry have more numbers than requested,
2464                  * create a new entry for alloc_list and minus its
2465                  * queue base and number in free_list.
2466                  */
2467                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2468                 if (entry == NULL) {
2469                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2470                                     "resource pool");
2471                         return -ENOMEM;
2472                 }
2473                 entry->base = valid_entry->base;
2474                 entry->len = num;
2475                 valid_entry->base += num;
2476                 valid_entry->len -= num;
2477                 valid_entry = entry;
2478         }
2479
2480         /* Insert it into alloc list, not sorted */
2481         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2482
2483         pool->num_free -= valid_entry->len;
2484         pool->num_alloc += valid_entry->len;
2485
2486         return (valid_entry->base + pool->base);
2487 }
2488
2489 /**
2490  * bitmap_is_subset - Check whether src2 is subset of src1
2491  **/
2492 static inline int
2493 bitmap_is_subset(uint8_t src1, uint8_t src2)
2494 {
2495         return !((src1 ^ src2) & src2);
2496 }
2497
2498 static int
2499 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2500 {
2501         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2502
2503         /* If DCB is not supported, only default TC is supported */
2504         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2505                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2506                 return -EINVAL;
2507         }
2508
2509         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2510                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2511                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2512                             enabled_tcmap);
2513                 return -EINVAL;
2514         }
2515         return I40E_SUCCESS;
2516 }
2517
2518 int
2519 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2520                                 struct i40e_vsi_vlan_pvid_info *info)
2521 {
2522         struct i40e_hw *hw;
2523         struct i40e_vsi_context ctxt;
2524         uint8_t vlan_flags = 0;
2525         int ret;
2526
2527         if (vsi == NULL || info == NULL) {
2528                 PMD_DRV_LOG(ERR, "invalid parameters");
2529                 return I40E_ERR_PARAM;
2530         }
2531
2532         if (info->on) {
2533                 vsi->info.pvid = info->config.pvid;
2534                 /**
2535                  * If insert pvid is enabled, only tagged pkts are
2536                  * allowed to be sent out.
2537                  */
2538                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2539                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2540         } else {
2541                 vsi->info.pvid = 0;
2542                 if (info->config.reject.tagged == 0)
2543                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2544
2545                 if (info->config.reject.untagged == 0)
2546                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2547         }
2548         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2549                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2550         vsi->info.port_vlan_flags |= vlan_flags;
2551         vsi->info.valid_sections =
2552                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2553         memset(&ctxt, 0, sizeof(ctxt));
2554         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2555         ctxt.seid = vsi->seid;
2556
2557         hw = I40E_VSI_TO_HW(vsi);
2558         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2559         if (ret != I40E_SUCCESS)
2560                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2561
2562         return ret;
2563 }
2564
2565 static int
2566 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2567 {
2568         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2569         int i, ret;
2570         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2571
2572         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2573         if (ret != I40E_SUCCESS)
2574                 return ret;
2575
2576         if (!vsi->seid) {
2577                 PMD_DRV_LOG(ERR, "seid not valid");
2578                 return -EINVAL;
2579         }
2580
2581         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2582         tc_bw_data.tc_valid_bits = enabled_tcmap;
2583         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2584                 tc_bw_data.tc_bw_credits[i] =
2585                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2586
2587         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2588         if (ret != I40E_SUCCESS) {
2589                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2590                 return ret;
2591         }
2592
2593         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2594                                         sizeof(vsi->info.qs_handle));
2595         return I40E_SUCCESS;
2596 }
2597
2598 static int
2599 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2600                                  struct i40e_aqc_vsi_properties_data *info,
2601                                  uint8_t enabled_tcmap)
2602 {
2603         int ret, total_tc = 0, i;
2604         uint16_t qpnum_per_tc, bsf, qp_idx;
2605
2606         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2607         if (ret != I40E_SUCCESS)
2608                 return ret;
2609
2610         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2611                 if (enabled_tcmap & (1 << i))
2612                         total_tc++;
2613         vsi->enabled_tc = enabled_tcmap;
2614
2615         /* Number of queues per enabled TC */
2616         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2617         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2618         bsf = rte_bsf32(qpnum_per_tc);
2619
2620         /* Adjust the queue number to actual queues that can be applied */
2621         vsi->nb_qps = qpnum_per_tc * total_tc;
2622
2623         /**
2624          * Configure TC and queue mapping parameters, for enabled TC,
2625          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2626          * default queue will serve it.
2627          */
2628         qp_idx = 0;
2629         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2630                 if (vsi->enabled_tc & (1 << i)) {
2631                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2632                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2633                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2634                         qp_idx += qpnum_per_tc;
2635                 } else
2636                         info->tc_mapping[i] = 0;
2637         }
2638
2639         /* Associate queue number with VSI */
2640         if (vsi->type == I40E_VSI_SRIOV) {
2641                 info->mapping_flags |=
2642                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2643                 for (i = 0; i < vsi->nb_qps; i++)
2644                         info->queue_mapping[i] =
2645                                 rte_cpu_to_le_16(vsi->base_queue + i);
2646         } else {
2647                 info->mapping_flags |=
2648                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2649                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2650         }
2651         info->valid_sections =
2652                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2653
2654         return I40E_SUCCESS;
2655 }
2656
2657 static int
2658 i40e_veb_release(struct i40e_veb *veb)
2659 {
2660         struct i40e_vsi *vsi;
2661         struct i40e_hw *hw;
2662
2663         if (veb == NULL || veb->associate_vsi == NULL)
2664                 return -EINVAL;
2665
2666         if (!TAILQ_EMPTY(&veb->head)) {
2667                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2668                 return -EACCES;
2669         }
2670
2671         vsi = veb->associate_vsi;
2672         hw = I40E_VSI_TO_HW(vsi);
2673
2674         vsi->uplink_seid = veb->uplink_seid;
2675         i40e_aq_delete_element(hw, veb->seid, NULL);
2676         rte_free(veb);
2677         vsi->veb = NULL;
2678         return I40E_SUCCESS;
2679 }
2680
2681 /* Setup a veb */
2682 static struct i40e_veb *
2683 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2684 {
2685         struct i40e_veb *veb;
2686         int ret;
2687         struct i40e_hw *hw;
2688
2689         if (NULL == pf || vsi == NULL) {
2690                 PMD_DRV_LOG(ERR, "veb setup failed, "
2691                             "associated VSI shouldn't null");
2692                 return NULL;
2693         }
2694         hw = I40E_PF_TO_HW(pf);
2695
2696         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2697         if (!veb) {
2698                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2699                 goto fail;
2700         }
2701
2702         veb->associate_vsi = vsi;
2703         TAILQ_INIT(&veb->head);
2704         veb->uplink_seid = vsi->uplink_seid;
2705
2706         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2707                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2708
2709         if (ret != I40E_SUCCESS) {
2710                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2711                             hw->aq.asq_last_status);
2712                 goto fail;
2713         }
2714
2715         /* get statistics index */
2716         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2717                                 &veb->stats_idx, NULL, NULL, NULL);
2718         if (ret != I40E_SUCCESS) {
2719                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2720                             hw->aq.asq_last_status);
2721                 goto fail;
2722         }
2723
2724         /* Get VEB bandwidth, to be implemented */
2725         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2726         vsi->uplink_seid = veb->seid;
2727
2728         return veb;
2729 fail:
2730         rte_free(veb);
2731         return NULL;
2732 }
2733
2734 int
2735 i40e_vsi_release(struct i40e_vsi *vsi)
2736 {
2737         struct i40e_pf *pf;
2738         struct i40e_hw *hw;
2739         struct i40e_vsi_list *vsi_list;
2740         int ret;
2741         struct i40e_mac_filter *f;
2742
2743         if (!vsi)
2744                 return I40E_SUCCESS;
2745
2746         pf = I40E_VSI_TO_PF(vsi);
2747         hw = I40E_VSI_TO_HW(vsi);
2748
2749         /* VSI has child to attach, release child first */
2750         if (vsi->veb) {
2751                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2752                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2753                                 return -1;
2754                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2755                 }
2756                 i40e_veb_release(vsi->veb);
2757         }
2758
2759         /* Remove all macvlan filters of the VSI */
2760         i40e_vsi_remove_all_macvlan_filter(vsi);
2761         TAILQ_FOREACH(f, &vsi->mac_list, next)
2762                 rte_free(f);
2763
2764         if (vsi->type != I40E_VSI_MAIN) {
2765                 /* Remove vsi from parent's sibling list */
2766                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2767                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2768                         return I40E_ERR_PARAM;
2769                 }
2770                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2771                                 &vsi->sib_vsi_list, list);
2772
2773                 /* Remove all switch element of the VSI */
2774                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2775                 if (ret != I40E_SUCCESS)
2776                         PMD_DRV_LOG(ERR, "Failed to delete element");
2777         }
2778         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2779
2780         if (vsi->type != I40E_VSI_SRIOV)
2781                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2782         rte_free(vsi);
2783
2784         return I40E_SUCCESS;
2785 }
2786
2787 static int
2788 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2789 {
2790         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2791         struct i40e_aqc_remove_macvlan_element_data def_filter;
2792         struct i40e_mac_filter_info filter;
2793         int ret;
2794
2795         if (vsi->type != I40E_VSI_MAIN)
2796                 return I40E_ERR_CONFIG;
2797         memset(&def_filter, 0, sizeof(def_filter));
2798         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2799                                         ETH_ADDR_LEN);
2800         def_filter.vlan_tag = 0;
2801         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2802                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2803         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2804         if (ret != I40E_SUCCESS) {
2805                 struct i40e_mac_filter *f;
2806                 struct ether_addr *mac;
2807
2808                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2809                             "macvlan filter");
2810                 /* It needs to add the permanent mac into mac list */
2811                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2812                 if (f == NULL) {
2813                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2814                         return I40E_ERR_NO_MEMORY;
2815                 }
2816                 mac = &f->mac_info.mac_addr;
2817                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2818                                 ETH_ADDR_LEN);
2819                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2820                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2821                 vsi->mac_num++;
2822
2823                 return ret;
2824         }
2825         (void)rte_memcpy(&filter.mac_addr,
2826                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2827         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2828         return i40e_vsi_add_mac(vsi, &filter);
2829 }
2830
2831 static int
2832 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2833 {
2834         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2835         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2836         struct i40e_hw *hw = &vsi->adapter->hw;
2837         i40e_status ret;
2838         int i;
2839
2840         memset(&bw_config, 0, sizeof(bw_config));
2841         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2842         if (ret != I40E_SUCCESS) {
2843                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2844                             hw->aq.asq_last_status);
2845                 return ret;
2846         }
2847
2848         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2849         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2850                                         &ets_sla_config, NULL);
2851         if (ret != I40E_SUCCESS) {
2852                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2853                             "configuration %u", hw->aq.asq_last_status);
2854                 return ret;
2855         }
2856
2857         /* Not store the info yet, just print out */
2858         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2859         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2860         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2861                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2862                             ets_sla_config.share_credits[i]);
2863                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2864                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2865                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2866                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2867                             (i * 4));
2868         }
2869
2870         return 0;
2871 }
2872
2873 /* Setup a VSI */
2874 struct i40e_vsi *
2875 i40e_vsi_setup(struct i40e_pf *pf,
2876                enum i40e_vsi_type type,
2877                struct i40e_vsi *uplink_vsi,
2878                uint16_t user_param)
2879 {
2880         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2881         struct i40e_vsi *vsi;
2882         struct i40e_mac_filter_info filter;
2883         int ret;
2884         struct i40e_vsi_context ctxt;
2885         struct ether_addr broadcast =
2886                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2887
2888         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2889                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2890                             "VSI link shouldn't be NULL");
2891                 return NULL;
2892         }
2893
2894         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2895                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2896                             "uplink VSI should be NULL");
2897                 return NULL;
2898         }
2899
2900         /* If uplink vsi didn't setup VEB, create one first */
2901         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2902                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2903
2904                 if (NULL == uplink_vsi->veb) {
2905                         PMD_DRV_LOG(ERR, "VEB setup failed");
2906                         return NULL;
2907                 }
2908         }
2909
2910         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2911         if (!vsi) {
2912                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2913                 return NULL;
2914         }
2915         TAILQ_INIT(&vsi->mac_list);
2916         vsi->type = type;
2917         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2918         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2919         vsi->parent_vsi = uplink_vsi;
2920         vsi->user_param = user_param;
2921         /* Allocate queues */
2922         switch (vsi->type) {
2923         case I40E_VSI_MAIN  :
2924                 vsi->nb_qps = pf->lan_nb_qps;
2925                 break;
2926         case I40E_VSI_SRIOV :
2927                 vsi->nb_qps = pf->vf_nb_qps;
2928                 break;
2929         case I40E_VSI_VMDQ2:
2930                 vsi->nb_qps = pf->vmdq_nb_qps;
2931                 break;
2932         case I40E_VSI_FDIR:
2933                 vsi->nb_qps = pf->fdir_nb_qps;
2934                 break;
2935         default:
2936                 goto fail_mem;
2937         }
2938         /*
2939          * The filter status descriptor is reported in rx queue 0,
2940          * while the tx queue for fdir filter programming has no
2941          * such constraints, can be non-zero queues.
2942          * To simplify it, choose FDIR vsi use queue 0 pair.
2943          * To make sure it will use queue 0 pair, queue allocation
2944          * need be done before this function is called
2945          */
2946         if (type != I40E_VSI_FDIR) {
2947                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2948                         if (ret < 0) {
2949                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2950                                                 vsi->seid, ret);
2951                                 goto fail_mem;
2952                         }
2953                         vsi->base_queue = ret;
2954         } else
2955                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2956
2957         /* VF has MSIX interrupt in VF range, don't allocate here */
2958         if (type != I40E_VSI_SRIOV) {
2959                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2960                 if (ret < 0) {
2961                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2962                         goto fail_queue_alloc;
2963                 }
2964                 vsi->msix_intr = ret;
2965         } else
2966                 vsi->msix_intr = 0;
2967         /* Add VSI */
2968         if (type == I40E_VSI_MAIN) {
2969                 /* For main VSI, no need to add since it's default one */
2970                 vsi->uplink_seid = pf->mac_seid;
2971                 vsi->seid = pf->main_vsi_seid;
2972                 /* Bind queues with specific MSIX interrupt */
2973                 /**
2974                  * Needs 2 interrupt at least, one for misc cause which will
2975                  * enabled from OS side, Another for queues binding the
2976                  * interrupt from device side only.
2977                  */
2978
2979                 /* Get default VSI parameters from hardware */
2980                 memset(&ctxt, 0, sizeof(ctxt));
2981                 ctxt.seid = vsi->seid;
2982                 ctxt.pf_num = hw->pf_id;
2983                 ctxt.uplink_seid = vsi->uplink_seid;
2984                 ctxt.vf_num = 0;
2985                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2986                 if (ret != I40E_SUCCESS) {
2987                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2988                         goto fail_msix_alloc;
2989                 }
2990                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2991                         sizeof(struct i40e_aqc_vsi_properties_data));
2992                 vsi->vsi_id = ctxt.vsi_number;
2993                 vsi->info.valid_sections = 0;
2994
2995                 /* Configure tc, enabled TC0 only */
2996                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2997                         I40E_SUCCESS) {
2998                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2999                         goto fail_msix_alloc;
3000                 }
3001
3002                 /* TC, queue mapping */
3003                 memset(&ctxt, 0, sizeof(ctxt));
3004                 vsi->info.valid_sections |=
3005                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3006                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3007                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3008                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3009                         sizeof(struct i40e_aqc_vsi_properties_data));
3010                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3011                                                 I40E_DEFAULT_TCMAP);
3012                 if (ret != I40E_SUCCESS) {
3013                         PMD_DRV_LOG(ERR, "Failed to configure "
3014                                     "TC queue mapping");
3015                         goto fail_msix_alloc;
3016                 }
3017                 ctxt.seid = vsi->seid;
3018                 ctxt.pf_num = hw->pf_id;
3019                 ctxt.uplink_seid = vsi->uplink_seid;
3020                 ctxt.vf_num = 0;
3021
3022                 /* Update VSI parameters */
3023                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3024                 if (ret != I40E_SUCCESS) {
3025                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3026                         goto fail_msix_alloc;
3027                 }
3028
3029                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3030                                                 sizeof(vsi->info.tc_mapping));
3031                 (void)rte_memcpy(&vsi->info.queue_mapping,
3032                                 &ctxt.info.queue_mapping,
3033                         sizeof(vsi->info.queue_mapping));
3034                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3035                 vsi->info.valid_sections = 0;
3036
3037                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3038                                 ETH_ADDR_LEN);
3039
3040                 /**
3041                  * Updating default filter settings are necessary to prevent
3042                  * reception of tagged packets.
3043                  * Some old firmware configurations load a default macvlan
3044                  * filter which accepts both tagged and untagged packets.
3045                  * The updating is to use a normal filter instead if needed.
3046                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3047                  * The firmware with correct configurations load the default
3048                  * macvlan filter which is expected and cannot be removed.
3049                  */
3050                 i40e_update_default_filter_setting(vsi);
3051         } else if (type == I40E_VSI_SRIOV) {
3052                 memset(&ctxt, 0, sizeof(ctxt));
3053                 /**
3054                  * For other VSI, the uplink_seid equals to uplink VSI's
3055                  * uplink_seid since they share same VEB
3056                  */
3057                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3058                 ctxt.pf_num = hw->pf_id;
3059                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3060                 ctxt.uplink_seid = vsi->uplink_seid;
3061                 ctxt.connection_type = 0x1;
3062                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3063
3064                 /* Configure switch ID */
3065                 ctxt.info.valid_sections |=
3066                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3067                 ctxt.info.switch_id =
3068                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3069                 /* Configure port/vlan */
3070                 ctxt.info.valid_sections |=
3071                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3072                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3073                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3074                                                 I40E_DEFAULT_TCMAP);
3075                 if (ret != I40E_SUCCESS) {
3076                         PMD_DRV_LOG(ERR, "Failed to configure "
3077                                     "TC queue mapping");
3078                         goto fail_msix_alloc;
3079                 }
3080                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3081                 ctxt.info.valid_sections |=
3082                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3083                 /**
3084                  * Since VSI is not created yet, only configure parameter,
3085                  * will add vsi below.
3086                  */
3087         } else if (type == I40E_VSI_VMDQ2) {
3088                 memset(&ctxt, 0, sizeof(ctxt));
3089                 /*
3090                  * For other VSI, the uplink_seid equals to uplink VSI's
3091                  * uplink_seid since they share same VEB
3092                  */
3093                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3094                 ctxt.pf_num = hw->pf_id;
3095                 ctxt.vf_num = 0;
3096                 ctxt.uplink_seid = vsi->uplink_seid;
3097                 ctxt.connection_type = 0x1;
3098                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3099
3100                 ctxt.info.valid_sections |=
3101                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3102                 /* user_param carries flag to enable loop back */
3103                 if (user_param) {
3104                         ctxt.info.switch_id =
3105                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3106                         ctxt.info.switch_id |=
3107                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3108                 }
3109
3110                 /* Configure port/vlan */
3111                 ctxt.info.valid_sections |=
3112                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3113                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3114                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3115                                                 I40E_DEFAULT_TCMAP);
3116                 if (ret != I40E_SUCCESS) {
3117                         PMD_DRV_LOG(ERR, "Failed to configure "
3118                                         "TC queue mapping");
3119                         goto fail_msix_alloc;
3120                 }
3121                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3122                 ctxt.info.valid_sections |=
3123                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3124         } else if (type == I40E_VSI_FDIR) {
3125                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3126                 ctxt.pf_num = hw->pf_id;
3127                 ctxt.vf_num = 0;
3128                 ctxt.uplink_seid = vsi->uplink_seid;
3129                 ctxt.connection_type = 0x1;     /* regular data port */
3130                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3131                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3132                                                 I40E_DEFAULT_TCMAP);
3133                 if (ret != I40E_SUCCESS) {
3134                         PMD_DRV_LOG(ERR, "Failed to configure "
3135                                         "TC queue mapping.");
3136                         goto fail_msix_alloc;
3137                 }
3138                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3139                 ctxt.info.valid_sections |=
3140                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3141         } else {
3142                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3143                 goto fail_msix_alloc;
3144         }
3145
3146         if (vsi->type != I40E_VSI_MAIN) {
3147                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3148                 if (ret) {
3149                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3150                                     hw->aq.asq_last_status);
3151                         goto fail_msix_alloc;
3152                 }
3153                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3154                 vsi->info.valid_sections = 0;
3155                 vsi->seid = ctxt.seid;
3156                 vsi->vsi_id = ctxt.vsi_number;
3157                 vsi->sib_vsi_list.vsi = vsi;
3158                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3159                                 &vsi->sib_vsi_list, list);
3160         }
3161
3162         /* MAC/VLAN configuration */
3163         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3164         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3165
3166         ret = i40e_vsi_add_mac(vsi, &filter);
3167         if (ret != I40E_SUCCESS) {
3168                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3169                 goto fail_msix_alloc;
3170         }
3171
3172         /* Get VSI BW information */
3173         i40e_vsi_dump_bw_config(vsi);
3174         return vsi;
3175 fail_msix_alloc:
3176         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3177 fail_queue_alloc:
3178         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3179 fail_mem:
3180         rte_free(vsi);
3181         return NULL;
3182 }
3183
3184 /* Configure vlan stripping on or off */
3185 int
3186 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3187 {
3188         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3189         struct i40e_vsi_context ctxt;
3190         uint8_t vlan_flags;
3191         int ret = I40E_SUCCESS;
3192
3193         /* Check if it has been already on or off */
3194         if (vsi->info.valid_sections &
3195                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3196                 if (on) {
3197                         if ((vsi->info.port_vlan_flags &
3198                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3199                                 return 0; /* already on */
3200                 } else {
3201                         if ((vsi->info.port_vlan_flags &
3202                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3203                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3204                                 return 0; /* already off */
3205                 }
3206         }
3207
3208         if (on)
3209                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3210         else
3211                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3212         vsi->info.valid_sections =
3213                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3214         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3215         vsi->info.port_vlan_flags |= vlan_flags;
3216         ctxt.seid = vsi->seid;
3217         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3218         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3219         if (ret)
3220                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3221                             on ? "enable" : "disable");
3222
3223         return ret;
3224 }
3225
3226 static int
3227 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3228 {
3229         struct rte_eth_dev_data *data = dev->data;
3230         int ret;
3231
3232         /* Apply vlan offload setting */
3233         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3234
3235         /* Apply double-vlan setting, not implemented yet */
3236
3237         /* Apply pvid setting */
3238         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3239                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3240         if (ret)
3241                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3242
3243         return ret;
3244 }
3245
3246 static int
3247 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3248 {
3249         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3250
3251         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3252 }
3253
3254 static int
3255 i40e_update_flow_control(struct i40e_hw *hw)
3256 {
3257 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3258         struct i40e_link_status link_status;
3259         uint32_t rxfc = 0, txfc = 0, reg;
3260         uint8_t an_info;
3261         int ret;
3262
3263         memset(&link_status, 0, sizeof(link_status));
3264         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3265         if (ret != I40E_SUCCESS) {
3266                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3267                 goto write_reg; /* Disable flow control */
3268         }
3269
3270         an_info = hw->phy.link_info.an_info;
3271         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3272                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3273                 ret = I40E_ERR_NOT_READY;
3274                 goto write_reg; /* Disable flow control */
3275         }
3276         /**
3277          * If link auto negotiation is enabled, flow control needs to
3278          * be configured according to it
3279          */
3280         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3281         case I40E_LINK_PAUSE_RXTX:
3282                 rxfc = 1;
3283                 txfc = 1;
3284                 hw->fc.current_mode = I40E_FC_FULL;
3285                 break;
3286         case I40E_AQ_LINK_PAUSE_RX:
3287                 rxfc = 1;
3288                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3289                 break;
3290         case I40E_AQ_LINK_PAUSE_TX:
3291                 txfc = 1;
3292                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3293                 break;
3294         default:
3295                 hw->fc.current_mode = I40E_FC_NONE;
3296                 break;
3297         }
3298
3299 write_reg:
3300         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3301                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3302         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3303         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3304         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3305         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3306
3307         return ret;
3308 }
3309
3310 /* PF setup */
3311 static int
3312 i40e_pf_setup(struct i40e_pf *pf)
3313 {
3314         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3315         struct i40e_filter_control_settings settings;
3316         struct i40e_vsi *vsi;
3317         int ret;
3318
3319         /* Clear all stats counters */
3320         pf->offset_loaded = FALSE;
3321         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3322         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3323
3324         ret = i40e_pf_get_switch_config(pf);
3325         if (ret != I40E_SUCCESS) {
3326                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3327                 return ret;
3328         }
3329         if (pf->flags & I40E_FLAG_FDIR) {
3330                 /* make queue allocated first, let FDIR use queue pair 0*/
3331                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3332                 if (ret != I40E_FDIR_QUEUE_ID) {
3333                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3334                                     " ret =%d", ret);
3335                         pf->flags &= ~I40E_FLAG_FDIR;
3336                 }
3337         }
3338         /*  main VSI setup */
3339         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3340         if (!vsi) {
3341                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3342                 return I40E_ERR_NOT_READY;
3343         }
3344         pf->main_vsi = vsi;
3345
3346         /* Configure filter control */
3347         memset(&settings, 0, sizeof(settings));
3348         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3349                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3350         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3351                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3352         else {
3353                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3354                                                 hw->func_caps.rss_table_size);
3355                 return I40E_ERR_PARAM;
3356         }
3357         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3358                         "size: %u\n", hw->func_caps.rss_table_size);
3359         pf->hash_lut_size = hw->func_caps.rss_table_size;
3360
3361         /* Enable ethtype and macvlan filters */
3362         settings.enable_ethtype = TRUE;
3363         settings.enable_macvlan = TRUE;
3364         ret = i40e_set_filter_control(hw, &settings);
3365         if (ret)
3366                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3367                                                                 ret);
3368
3369         /* Update flow control according to the auto negotiation */
3370         i40e_update_flow_control(hw);
3371
3372         return I40E_SUCCESS;
3373 }
3374
3375 int
3376 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3377 {
3378         uint32_t reg;
3379         uint16_t j;
3380
3381         /**
3382          * Set or clear TX Queue Disable flags,
3383          * which is required by hardware.
3384          */
3385         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3386         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3387
3388         /* Wait until the request is finished */
3389         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3390                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3391                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3392                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3393                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3394                                                         & 0x1))) {
3395                         break;
3396                 }
3397         }
3398         if (on) {
3399                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3400                         return I40E_SUCCESS; /* already on, skip next steps */
3401
3402                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3403                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3404         } else {
3405                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3406                         return I40E_SUCCESS; /* already off, skip next steps */
3407                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3408         }
3409         /* Write the register */
3410         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3411         /* Check the result */
3412         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3413                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3414                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3415                 if (on) {
3416                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3417                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3418                                 break;
3419                 } else {
3420                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3421                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3422                                 break;
3423                 }
3424         }
3425         /* Check if it is timeout */
3426         if (j >= I40E_CHK_Q_ENA_COUNT) {
3427                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3428                             (on ? "enable" : "disable"), q_idx);
3429                 return I40E_ERR_TIMEOUT;
3430         }
3431
3432         return I40E_SUCCESS;
3433 }
3434
3435 /* Swith on or off the tx queues */
3436 static int
3437 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3438 {
3439         struct rte_eth_dev_data *dev_data = pf->dev_data;
3440         struct i40e_tx_queue *txq;
3441         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3442         uint16_t i;
3443         int ret;
3444
3445         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3446                 txq = dev_data->tx_queues[i];
3447                 /* Don't operate the queue if not configured or
3448                  * if starting only per queue */
3449                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3450                         continue;
3451                 if (on)
3452                         ret = i40e_dev_tx_queue_start(dev, i);
3453                 else
3454                         ret = i40e_dev_tx_queue_stop(dev, i);
3455                 if ( ret != I40E_SUCCESS)
3456                         return ret;
3457         }
3458
3459         return I40E_SUCCESS;
3460 }
3461
3462 int
3463 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3464 {
3465         uint32_t reg;
3466         uint16_t j;
3467
3468         /* Wait until the request is finished */
3469         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3470                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3471                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3472                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3473                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3474                         break;
3475         }
3476
3477         if (on) {
3478                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3479                         return I40E_SUCCESS; /* Already on, skip next steps */
3480                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3481         } else {
3482                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3483                         return I40E_SUCCESS; /* Already off, skip next steps */
3484                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3485         }
3486
3487         /* Write the register */
3488         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3489         /* Check the result */
3490         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3491                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3492                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3493                 if (on) {
3494                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3495                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3496                                 break;
3497                 } else {
3498                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3499                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3500                                 break;
3501                 }
3502         }
3503
3504         /* Check if it is timeout */
3505         if (j >= I40E_CHK_Q_ENA_COUNT) {
3506                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3507                             (on ? "enable" : "disable"), q_idx);
3508                 return I40E_ERR_TIMEOUT;
3509         }
3510
3511         return I40E_SUCCESS;
3512 }
3513 /* Switch on or off the rx queues */
3514 static int
3515 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3516 {
3517         struct rte_eth_dev_data *dev_data = pf->dev_data;
3518         struct i40e_rx_queue *rxq;
3519         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3520         uint16_t i;
3521         int ret;
3522
3523         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3524                 rxq = dev_data->rx_queues[i];
3525                 /* Don't operate the queue if not configured or
3526                  * if starting only per queue */
3527                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3528                         continue;
3529                 if (on)
3530                         ret = i40e_dev_rx_queue_start(dev, i);
3531                 else
3532                         ret = i40e_dev_rx_queue_stop(dev, i);
3533                 if (ret != I40E_SUCCESS)
3534                         return ret;
3535         }
3536
3537         return I40E_SUCCESS;
3538 }
3539
3540 /* Switch on or off all the rx/tx queues */
3541 int
3542 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3543 {
3544         int ret;
3545
3546         if (on) {
3547                 /* enable rx queues before enabling tx queues */
3548                 ret = i40e_dev_switch_rx_queues(pf, on);
3549                 if (ret) {
3550                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3551                         return ret;
3552                 }
3553                 ret = i40e_dev_switch_tx_queues(pf, on);
3554         } else {
3555                 /* Stop tx queues before stopping rx queues */
3556                 ret = i40e_dev_switch_tx_queues(pf, on);
3557                 if (ret) {
3558                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3559                         return ret;
3560                 }
3561                 ret = i40e_dev_switch_rx_queues(pf, on);
3562         }
3563
3564         return ret;
3565 }
3566
3567 /* Initialize VSI for TX */
3568 static int
3569 i40e_dev_tx_init(struct i40e_pf *pf)
3570 {
3571         struct rte_eth_dev_data *data = pf->dev_data;
3572         uint16_t i;
3573         uint32_t ret = I40E_SUCCESS;
3574         struct i40e_tx_queue *txq;
3575
3576         for (i = 0; i < data->nb_tx_queues; i++) {
3577                 txq = data->tx_queues[i];
3578                 if (!txq || !txq->q_set)
3579                         continue;
3580                 ret = i40e_tx_queue_init(txq);
3581                 if (ret != I40E_SUCCESS)
3582                         break;
3583         }
3584
3585         return ret;
3586 }
3587
3588 /* Initialize VSI for RX */
3589 static int
3590 i40e_dev_rx_init(struct i40e_pf *pf)
3591 {
3592         struct rte_eth_dev_data *data = pf->dev_data;
3593         int ret = I40E_SUCCESS;
3594         uint16_t i;
3595         struct i40e_rx_queue *rxq;
3596
3597         i40e_pf_config_mq_rx(pf);
3598         for (i = 0; i < data->nb_rx_queues; i++) {
3599                 rxq = data->rx_queues[i];
3600                 if (!rxq || !rxq->q_set)
3601                         continue;
3602
3603                 ret = i40e_rx_queue_init(rxq);
3604                 if (ret != I40E_SUCCESS) {
3605                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3606                                     "initialization");
3607                         break;
3608                 }
3609         }
3610
3611         return ret;
3612 }
3613
3614 static int
3615 i40e_dev_rxtx_init(struct i40e_pf *pf)
3616 {
3617         int err;
3618
3619         err = i40e_dev_tx_init(pf);
3620         if (err) {
3621                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3622                 return err;
3623         }
3624         err = i40e_dev_rx_init(pf);
3625         if (err) {
3626                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3627                 return err;
3628         }
3629
3630         return err;
3631 }
3632
3633 static int
3634 i40e_vmdq_setup(struct rte_eth_dev *dev)
3635 {
3636         struct rte_eth_conf *conf = &dev->data->dev_conf;
3637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638         int i, err, conf_vsis, j, loop;
3639         struct i40e_vsi *vsi;
3640         struct i40e_vmdq_info *vmdq_info;
3641         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3642         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3643
3644         /*
3645          * Disable interrupt to avoid message from VF. Furthermore, it will
3646          * avoid race condition in VSI creation/destroy.
3647          */
3648         i40e_pf_disable_irq0(hw);
3649
3650         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3651                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3652                 return -ENOTSUP;
3653         }
3654
3655         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3656         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3657                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3658                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3659                         pf->max_nb_vmdq_vsi);
3660                 return -ENOTSUP;
3661         }
3662
3663         if (pf->vmdq != NULL) {
3664                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3665                 return 0;
3666         }
3667
3668         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3669                                 sizeof(*vmdq_info) * conf_vsis, 0);
3670
3671         if (pf->vmdq == NULL) {
3672                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3673                 return -ENOMEM;
3674         }
3675
3676         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3677
3678         /* Create VMDQ VSI */
3679         for (i = 0; i < conf_vsis; i++) {
3680                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3681                                 vmdq_conf->enable_loop_back);
3682                 if (vsi == NULL) {
3683                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3684                         err = -1;
3685                         goto err_vsi_setup;
3686                 }
3687                 vmdq_info = &pf->vmdq[i];
3688                 vmdq_info->pf = pf;
3689                 vmdq_info->vsi = vsi;
3690         }
3691         pf->nb_cfg_vmdq_vsi = conf_vsis;
3692
3693         /* Configure Vlan */
3694         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3695         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3696                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3697                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3698                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3699                                         vmdq_conf->pool_map[i].vlan_id, j);
3700
3701                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3702                                                 vmdq_conf->pool_map[i].vlan_id);
3703                                 if (err) {
3704                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3705                                         err = -1;
3706                                         goto err_vsi_setup;
3707                                 }
3708                         }
3709                 }
3710         }
3711
3712         i40e_pf_enable_irq0(hw);
3713
3714         return 0;
3715
3716 err_vsi_setup:
3717         for (i = 0; i < conf_vsis; i++)
3718                 if (pf->vmdq[i].vsi == NULL)
3719                         break;
3720                 else
3721                         i40e_vsi_release(pf->vmdq[i].vsi);
3722
3723         rte_free(pf->vmdq);
3724         pf->vmdq = NULL;
3725         i40e_pf_enable_irq0(hw);
3726         return err;
3727 }
3728
3729 static void
3730 i40e_stat_update_32(struct i40e_hw *hw,
3731                    uint32_t reg,
3732                    bool offset_loaded,
3733                    uint64_t *offset,
3734                    uint64_t *stat)
3735 {
3736         uint64_t new_data;
3737
3738         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3739         if (!offset_loaded)
3740                 *offset = new_data;
3741
3742         if (new_data >= *offset)
3743                 *stat = (uint64_t)(new_data - *offset);
3744         else
3745                 *stat = (uint64_t)((new_data +
3746                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3747 }
3748
3749 static void
3750 i40e_stat_update_48(struct i40e_hw *hw,
3751                    uint32_t hireg,
3752                    uint32_t loreg,
3753                    bool offset_loaded,
3754                    uint64_t *offset,
3755                    uint64_t *stat)
3756 {
3757         uint64_t new_data;
3758
3759         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3760         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3761                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3762
3763         if (!offset_loaded)
3764                 *offset = new_data;
3765
3766         if (new_data >= *offset)
3767                 *stat = new_data - *offset;
3768         else
3769                 *stat = (uint64_t)((new_data +
3770                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3771
3772         *stat &= I40E_48_BIT_MASK;
3773 }
3774
3775 /* Disable IRQ0 */
3776 void
3777 i40e_pf_disable_irq0(struct i40e_hw *hw)
3778 {
3779         /* Disable all interrupt types */
3780         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3781         I40E_WRITE_FLUSH(hw);
3782 }
3783
3784 /* Enable IRQ0 */
3785 void
3786 i40e_pf_enable_irq0(struct i40e_hw *hw)
3787 {
3788         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3789                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3790                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3791                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3792         I40E_WRITE_FLUSH(hw);
3793 }
3794
3795 static void
3796 i40e_pf_config_irq0(struct i40e_hw *hw)
3797 {
3798         /* read pending request and disable first */
3799         i40e_pf_disable_irq0(hw);
3800         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3801         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3802                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3803
3804         /* Link no queues with irq0 */
3805         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3806                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3807 }
3808
3809 static void
3810 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3811 {
3812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3814         int i;
3815         uint16_t abs_vf_id;
3816         uint32_t index, offset, val;
3817
3818         if (!pf->vfs)
3819                 return;
3820         /**
3821          * Try to find which VF trigger a reset, use absolute VF id to access
3822          * since the reg is global register.
3823          */
3824         for (i = 0; i < pf->vf_num; i++) {
3825                 abs_vf_id = hw->func_caps.vf_base_id + i;
3826                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3827                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3828                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3829                 /* VFR event occured */
3830                 if (val & (0x1 << offset)) {
3831                         int ret;
3832
3833                         /* Clear the event first */
3834                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3835                                                         (0x1 << offset));
3836                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3837                         /**
3838                          * Only notify a VF reset event occured,
3839                          * don't trigger another SW reset
3840                          */
3841                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3842                         if (ret != I40E_SUCCESS)
3843                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3844                 }
3845         }
3846 }
3847
3848 static void
3849 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3850 {
3851         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852         struct i40e_arq_event_info info;
3853         uint16_t pending, opcode;
3854         int ret;
3855
3856         info.buf_len = I40E_AQ_BUF_SZ;
3857         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3858         if (!info.msg_buf) {
3859                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3860                 return;
3861         }
3862
3863         pending = 1;
3864         while (pending) {
3865                 ret = i40e_clean_arq_element(hw, &info, &pending);
3866
3867                 if (ret != I40E_SUCCESS) {
3868                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3869                                     "aq_err: %u", hw->aq.asq_last_status);
3870                         break;
3871                 }
3872                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3873
3874                 switch (opcode) {
3875                 case i40e_aqc_opc_send_msg_to_pf:
3876                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3877                         i40e_pf_host_handle_vf_msg(dev,
3878                                         rte_le_to_cpu_16(info.desc.retval),
3879                                         rte_le_to_cpu_32(info.desc.cookie_high),
3880                                         rte_le_to_cpu_32(info.desc.cookie_low),
3881                                         info.msg_buf,
3882                                         info.msg_len);
3883                         break;
3884                 default:
3885                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3886                                     opcode);
3887                         break;
3888                 }
3889         }
3890         rte_free(info.msg_buf);
3891 }
3892
3893 /*
3894  * Interrupt handler is registered as the alarm callback for handling LSC
3895  * interrupt in a definite of time, in order to wait the NIC into a stable
3896  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3897  * no need for link down interrupt.
3898  */
3899 static void
3900 i40e_dev_interrupt_delayed_handler(void *param)
3901 {
3902         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         uint32_t icr0;
3905
3906         /* read interrupt causes again */
3907         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3908
3909 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3910         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3911                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3912         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3913                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3914         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3915                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3916         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3917                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3918         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3919                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3920                                                                 "state\n");
3921         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3922                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3923         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3924                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3925 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3926
3927         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3928                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3929                 i40e_dev_handle_vfr_event(dev);
3930         }
3931         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3932                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3933                 i40e_dev_handle_aq_msg(dev);
3934         }
3935
3936         /* handle the link up interrupt in an alarm callback */
3937         i40e_dev_link_update(dev, 0);
3938         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3939
3940         i40e_pf_enable_irq0(hw);
3941         rte_intr_enable(&(dev->pci_dev->intr_handle));
3942 }
3943
3944 /**
3945  * Interrupt handler triggered by NIC  for handling
3946  * specific interrupt.
3947  *
3948  * @param handle
3949  *  Pointer to interrupt handle.
3950  * @param param
3951  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3952  *
3953  * @return
3954  *  void
3955  */
3956 static void
3957 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3958                            void *param)
3959 {
3960         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3962         uint32_t icr0;
3963
3964         /* Disable interrupt */
3965         i40e_pf_disable_irq0(hw);
3966
3967         /* read out interrupt causes */
3968         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3969
3970         /* No interrupt event indicated */
3971         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3972                 PMD_DRV_LOG(INFO, "No interrupt event");
3973                 goto done;
3974         }
3975 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3976         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3977                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3978         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3979                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3980         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3981                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3982         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3983                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3984         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3985                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3986         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3987                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3988         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3989                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3990 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3991
3992         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3993                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3994                 i40e_dev_handle_vfr_event(dev);
3995         }
3996         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3997                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3998                 i40e_dev_handle_aq_msg(dev);
3999         }
4000
4001         /* Link Status Change interrupt */
4002         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4003 #define I40E_US_PER_SECOND 1000000
4004                 struct rte_eth_link link;
4005
4006                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4007                 memset(&link, 0, sizeof(link));
4008                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4009                 i40e_dev_link_update(dev, 0);
4010
4011                 /*
4012                  * For link up interrupt, it needs to wait 1 second to let the
4013                  * hardware be a stable state. Otherwise several consecutive
4014                  * interrupts can be observed.
4015                  * For link down interrupt, no need to wait.
4016                  */
4017                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4018                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4019                         return;
4020                 else
4021                         _rte_eth_dev_callback_process(dev,
4022                                 RTE_ETH_EVENT_INTR_LSC);
4023         }
4024
4025 done:
4026         /* Enable interrupt */
4027         i40e_pf_enable_irq0(hw);
4028         rte_intr_enable(&(dev->pci_dev->intr_handle));
4029 }
4030
4031 static int
4032 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4033                          struct i40e_macvlan_filter *filter,
4034                          int total)
4035 {
4036         int ele_num, ele_buff_size;
4037         int num, actual_num, i;
4038         uint16_t flags;
4039         int ret = I40E_SUCCESS;
4040         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4041         struct i40e_aqc_add_macvlan_element_data *req_list;
4042
4043         if (filter == NULL  || total == 0)
4044                 return I40E_ERR_PARAM;
4045         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4046         ele_buff_size = hw->aq.asq_buf_size;
4047
4048         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4049         if (req_list == NULL) {
4050                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4051                 return I40E_ERR_NO_MEMORY;
4052         }
4053
4054         num = 0;
4055         do {
4056                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4057                 memset(req_list, 0, ele_buff_size);
4058
4059                 for (i = 0; i < actual_num; i++) {
4060                         (void)rte_memcpy(req_list[i].mac_addr,
4061                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4062                         req_list[i].vlan_tag =
4063                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4064
4065                         switch (filter[num + i].filter_type) {
4066                         case RTE_MAC_PERFECT_MATCH:
4067                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4068                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4069                                 break;
4070                         case RTE_MACVLAN_PERFECT_MATCH:
4071                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4072                                 break;
4073                         case RTE_MAC_HASH_MATCH:
4074                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4075                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4076                                 break;
4077                         case RTE_MACVLAN_HASH_MATCH:
4078                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4079                                 break;
4080                         default:
4081                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4082                                 ret = I40E_ERR_PARAM;
4083                                 goto DONE;
4084                         }
4085
4086                         req_list[i].queue_number = 0;
4087
4088                         req_list[i].flags = rte_cpu_to_le_16(flags);
4089                 }
4090
4091                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4092                                                 actual_num, NULL);
4093                 if (ret != I40E_SUCCESS) {
4094                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4095                         goto DONE;
4096                 }
4097                 num += actual_num;
4098         } while (num < total);
4099
4100 DONE:
4101         rte_free(req_list);
4102         return ret;
4103 }
4104
4105 static int
4106 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4107                             struct i40e_macvlan_filter *filter,
4108                             int total)
4109 {
4110         int ele_num, ele_buff_size;
4111         int num, actual_num, i;
4112         uint16_t flags;
4113         int ret = I40E_SUCCESS;
4114         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4115         struct i40e_aqc_remove_macvlan_element_data *req_list;
4116
4117         if (filter == NULL  || total == 0)
4118                 return I40E_ERR_PARAM;
4119
4120         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4121         ele_buff_size = hw->aq.asq_buf_size;
4122
4123         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4124         if (req_list == NULL) {
4125                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4126                 return I40E_ERR_NO_MEMORY;
4127         }
4128
4129         num = 0;
4130         do {
4131                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4132                 memset(req_list, 0, ele_buff_size);
4133
4134                 for (i = 0; i < actual_num; i++) {
4135                         (void)rte_memcpy(req_list[i].mac_addr,
4136                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4137                         req_list[i].vlan_tag =
4138                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4139
4140                         switch (filter[num + i].filter_type) {
4141                         case RTE_MAC_PERFECT_MATCH:
4142                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4143                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4144                                 break;
4145                         case RTE_MACVLAN_PERFECT_MATCH:
4146                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4147                                 break;
4148                         case RTE_MAC_HASH_MATCH:
4149                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4150                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4151                                 break;
4152                         case RTE_MACVLAN_HASH_MATCH:
4153                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4154                                 break;
4155                         default:
4156                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4157                                 ret = I40E_ERR_PARAM;
4158                                 goto DONE;
4159                         }
4160                         req_list[i].flags = rte_cpu_to_le_16(flags);
4161                 }
4162
4163                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4164                                                 actual_num, NULL);
4165                 if (ret != I40E_SUCCESS) {
4166                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4167                         goto DONE;
4168                 }
4169                 num += actual_num;
4170         } while (num < total);
4171
4172 DONE:
4173         rte_free(req_list);
4174         return ret;
4175 }
4176
4177 /* Find out specific MAC filter */
4178 static struct i40e_mac_filter *
4179 i40e_find_mac_filter(struct i40e_vsi *vsi,
4180                          struct ether_addr *macaddr)
4181 {
4182         struct i40e_mac_filter *f;
4183
4184         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4185                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4186                         return f;
4187         }
4188
4189         return NULL;
4190 }
4191
4192 static bool
4193 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4194                          uint16_t vlan_id)
4195 {
4196         uint32_t vid_idx, vid_bit;
4197
4198         if (vlan_id > ETH_VLAN_ID_MAX)
4199                 return 0;
4200
4201         vid_idx = I40E_VFTA_IDX(vlan_id);
4202         vid_bit = I40E_VFTA_BIT(vlan_id);
4203
4204         if (vsi->vfta[vid_idx] & vid_bit)
4205                 return 1;
4206         else
4207                 return 0;
4208 }
4209
4210 static void
4211 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4212                          uint16_t vlan_id, bool on)
4213 {
4214         uint32_t vid_idx, vid_bit;
4215
4216         if (vlan_id > ETH_VLAN_ID_MAX)
4217                 return;
4218
4219         vid_idx = I40E_VFTA_IDX(vlan_id);
4220         vid_bit = I40E_VFTA_BIT(vlan_id);
4221
4222         if (on)
4223                 vsi->vfta[vid_idx] |= vid_bit;
4224         else
4225                 vsi->vfta[vid_idx] &= ~vid_bit;
4226 }
4227
4228 /**
4229  * Find all vlan options for specific mac addr,
4230  * return with actual vlan found.
4231  */
4232 static inline int
4233 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4234                            struct i40e_macvlan_filter *mv_f,
4235                            int num, struct ether_addr *addr)
4236 {
4237         int i;
4238         uint32_t j, k;
4239
4240         /**
4241          * Not to use i40e_find_vlan_filter to decrease the loop time,
4242          * although the code looks complex.
4243           */
4244         if (num < vsi->vlan_num)
4245                 return I40E_ERR_PARAM;
4246
4247         i = 0;
4248         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4249                 if (vsi->vfta[j]) {
4250                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4251                                 if (vsi->vfta[j] & (1 << k)) {
4252                                         if (i > num - 1) {
4253                                                 PMD_DRV_LOG(ERR, "vlan number "
4254                                                             "not match");
4255                                                 return I40E_ERR_PARAM;
4256                                         }
4257                                         (void)rte_memcpy(&mv_f[i].macaddr,
4258                                                         addr, ETH_ADDR_LEN);
4259                                         mv_f[i].vlan_id =
4260                                                 j * I40E_UINT32_BIT_SIZE + k;
4261                                         i++;
4262                                 }
4263                         }
4264                 }
4265         }
4266         return I40E_SUCCESS;
4267 }
4268
4269 static inline int
4270 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4271                            struct i40e_macvlan_filter *mv_f,
4272                            int num,
4273                            uint16_t vlan)
4274 {
4275         int i = 0;
4276         struct i40e_mac_filter *f;
4277
4278         if (num < vsi->mac_num)
4279                 return I40E_ERR_PARAM;
4280
4281         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4282                 if (i > num - 1) {
4283                         PMD_DRV_LOG(ERR, "buffer number not match");
4284                         return I40E_ERR_PARAM;
4285                 }
4286                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4287                                 ETH_ADDR_LEN);
4288                 mv_f[i].vlan_id = vlan;
4289                 mv_f[i].filter_type = f->mac_info.filter_type;
4290                 i++;
4291         }
4292
4293         return I40E_SUCCESS;
4294 }
4295
4296 static int
4297 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4298 {
4299         int i, num;
4300         struct i40e_mac_filter *f;
4301         struct i40e_macvlan_filter *mv_f;
4302         int ret = I40E_SUCCESS;
4303
4304         if (vsi == NULL || vsi->mac_num == 0)
4305                 return I40E_ERR_PARAM;
4306
4307         /* Case that no vlan is set */
4308         if (vsi->vlan_num == 0)
4309                 num = vsi->mac_num;
4310         else
4311                 num = vsi->mac_num * vsi->vlan_num;
4312
4313         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4314         if (mv_f == NULL) {
4315                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4316                 return I40E_ERR_NO_MEMORY;
4317         }
4318
4319         i = 0;
4320         if (vsi->vlan_num == 0) {
4321                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4322                         (void)rte_memcpy(&mv_f[i].macaddr,
4323                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4324                         mv_f[i].vlan_id = 0;
4325                         i++;
4326                 }
4327         } else {
4328                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4329                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4330                                         vsi->vlan_num, &f->mac_info.mac_addr);
4331                         if (ret != I40E_SUCCESS)
4332                                 goto DONE;
4333                         i += vsi->vlan_num;
4334                 }
4335         }
4336
4337         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4338 DONE:
4339         rte_free(mv_f);
4340
4341         return ret;
4342 }
4343
4344 int
4345 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4346 {
4347         struct i40e_macvlan_filter *mv_f;
4348         int mac_num;
4349         int ret = I40E_SUCCESS;
4350
4351         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4352                 return I40E_ERR_PARAM;
4353
4354         /* If it's already set, just return */
4355         if (i40e_find_vlan_filter(vsi,vlan))
4356                 return I40E_SUCCESS;
4357
4358         mac_num = vsi->mac_num;
4359
4360         if (mac_num == 0) {
4361                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4362                 return I40E_ERR_PARAM;
4363         }
4364
4365         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4366
4367         if (mv_f == NULL) {
4368                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4369                 return I40E_ERR_NO_MEMORY;
4370         }
4371
4372         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4373
4374         if (ret != I40E_SUCCESS)
4375                 goto DONE;
4376
4377         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4378
4379         if (ret != I40E_SUCCESS)
4380                 goto DONE;
4381
4382         i40e_set_vlan_filter(vsi, vlan, 1);
4383
4384         vsi->vlan_num++;
4385         ret = I40E_SUCCESS;
4386 DONE:
4387         rte_free(mv_f);
4388         return ret;
4389 }
4390
4391 int
4392 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4393 {
4394         struct i40e_macvlan_filter *mv_f;
4395         int mac_num;
4396         int ret = I40E_SUCCESS;
4397
4398         /**
4399          * Vlan 0 is the generic filter for untagged packets
4400          * and can't be removed.
4401          */
4402         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4403                 return I40E_ERR_PARAM;
4404
4405         /* If can't find it, just return */
4406         if (!i40e_find_vlan_filter(vsi, vlan))
4407                 return I40E_ERR_PARAM;
4408
4409         mac_num = vsi->mac_num;
4410
4411         if (mac_num == 0) {
4412                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4413                 return I40E_ERR_PARAM;
4414         }
4415
4416         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4417
4418         if (mv_f == NULL) {
4419                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4420                 return I40E_ERR_NO_MEMORY;
4421         }
4422
4423         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4424
4425         if (ret != I40E_SUCCESS)
4426                 goto DONE;
4427
4428         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4429
4430         if (ret != I40E_SUCCESS)
4431                 goto DONE;
4432
4433         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4434         if (vsi->vlan_num == 1) {
4435                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4436                 if (ret != I40E_SUCCESS)
4437                         goto DONE;
4438
4439                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4440                 if (ret != I40E_SUCCESS)
4441                         goto DONE;
4442         }
4443
4444         i40e_set_vlan_filter(vsi, vlan, 0);
4445
4446         vsi->vlan_num--;
4447         ret = I40E_SUCCESS;
4448 DONE:
4449         rte_free(mv_f);
4450         return ret;
4451 }
4452
4453 int
4454 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4455 {
4456         struct i40e_mac_filter *f;
4457         struct i40e_macvlan_filter *mv_f;
4458         int i, vlan_num = 0;
4459         int ret = I40E_SUCCESS;
4460
4461         /* If it's add and we've config it, return */
4462         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4463         if (f != NULL)
4464                 return I40E_SUCCESS;
4465         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4466                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4467
4468                 /**
4469                  * If vlan_num is 0, that's the first time to add mac,
4470                  * set mask for vlan_id 0.
4471                  */
4472                 if (vsi->vlan_num == 0) {
4473                         i40e_set_vlan_filter(vsi, 0, 1);
4474                         vsi->vlan_num = 1;
4475                 }
4476                 vlan_num = vsi->vlan_num;
4477         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4478                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4479                 vlan_num = 1;
4480
4481         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4482         if (mv_f == NULL) {
4483                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4484                 return I40E_ERR_NO_MEMORY;
4485         }
4486
4487         for (i = 0; i < vlan_num; i++) {
4488                 mv_f[i].filter_type = mac_filter->filter_type;
4489                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4490                                 ETH_ADDR_LEN);
4491         }
4492
4493         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4494                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4495                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4496                                         &mac_filter->mac_addr);
4497                 if (ret != I40E_SUCCESS)
4498                         goto DONE;
4499         }
4500
4501         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4502         if (ret != I40E_SUCCESS)
4503                 goto DONE;
4504
4505         /* Add the mac addr into mac list */
4506         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4507         if (f == NULL) {
4508                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4509                 ret = I40E_ERR_NO_MEMORY;
4510                 goto DONE;
4511         }
4512         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4513                         ETH_ADDR_LEN);
4514         f->mac_info.filter_type = mac_filter->filter_type;
4515         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4516         vsi->mac_num++;
4517
4518         ret = I40E_SUCCESS;
4519 DONE:
4520         rte_free(mv_f);
4521
4522         return ret;
4523 }
4524
4525 int
4526 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4527 {
4528         struct i40e_mac_filter *f;
4529         struct i40e_macvlan_filter *mv_f;
4530         int i, vlan_num;
4531         enum rte_mac_filter_type filter_type;
4532         int ret = I40E_SUCCESS;
4533
4534         /* Can't find it, return an error */
4535         f = i40e_find_mac_filter(vsi, addr);
4536         if (f == NULL)
4537                 return I40E_ERR_PARAM;
4538
4539         vlan_num = vsi->vlan_num;
4540         filter_type = f->mac_info.filter_type;
4541         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4542                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4543                 if (vlan_num == 0) {
4544                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4545                         return I40E_ERR_PARAM;
4546                 }
4547         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4548                         filter_type == RTE_MAC_HASH_MATCH)
4549                 vlan_num = 1;
4550
4551         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4552         if (mv_f == NULL) {
4553                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4554                 return I40E_ERR_NO_MEMORY;
4555         }
4556
4557         for (i = 0; i < vlan_num; i++) {
4558                 mv_f[i].filter_type = filter_type;
4559                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4560                                 ETH_ADDR_LEN);
4561         }
4562         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4563                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4564                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4565                 if (ret != I40E_SUCCESS)
4566                         goto DONE;
4567         }
4568
4569         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4570         if (ret != I40E_SUCCESS)
4571                 goto DONE;
4572
4573         /* Remove the mac addr into mac list */
4574         TAILQ_REMOVE(&vsi->mac_list, f, next);
4575         rte_free(f);
4576         vsi->mac_num--;
4577
4578         ret = I40E_SUCCESS;
4579 DONE:
4580         rte_free(mv_f);
4581         return ret;
4582 }
4583
4584 /* Configure hash enable flags for RSS */
4585 uint64_t
4586 i40e_config_hena(uint64_t flags)
4587 {
4588         uint64_t hena = 0;
4589
4590         if (!flags)
4591                 return hena;
4592
4593         if (flags & ETH_RSS_FRAG_IPV4)
4594                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4595         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4596                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4597         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4598                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4599         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4600                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4601         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4602                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4603         if (flags & ETH_RSS_FRAG_IPV6)
4604                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4605         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4606                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4607         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4608                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4609         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4610                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4611         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4612                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4613         if (flags & ETH_RSS_L2_PAYLOAD)
4614                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4615
4616         return hena;
4617 }
4618
4619 /* Parse the hash enable flags */
4620 uint64_t
4621 i40e_parse_hena(uint64_t flags)
4622 {
4623         uint64_t rss_hf = 0;
4624
4625         if (!flags)
4626                 return rss_hf;
4627         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4628                 rss_hf |= ETH_RSS_FRAG_IPV4;
4629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4630                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4631         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4632                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4633         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4634                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4635         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4636                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4637         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4638                 rss_hf |= ETH_RSS_FRAG_IPV6;
4639         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4640                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4641         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4642                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4643         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4644                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4645         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4646                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4647         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4648                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4649
4650         return rss_hf;
4651 }
4652
4653 /* Disable RSS */
4654 static void
4655 i40e_pf_disable_rss(struct i40e_pf *pf)
4656 {
4657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4658         uint64_t hena;
4659
4660         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4661         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4662         hena &= ~I40E_RSS_HENA_ALL;
4663         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4664         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4665         I40E_WRITE_FLUSH(hw);
4666 }
4667
4668 static int
4669 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4670 {
4671         uint32_t *hash_key;
4672         uint8_t hash_key_len;
4673         uint64_t rss_hf;
4674         uint16_t i;
4675         uint64_t hena;
4676
4677         hash_key = (uint32_t *)(rss_conf->rss_key);
4678         hash_key_len = rss_conf->rss_key_len;
4679         if (hash_key != NULL && hash_key_len >=
4680                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4681                 /* Fill in RSS hash key */
4682                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4683                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4684         }
4685
4686         rss_hf = rss_conf->rss_hf;
4687         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4688         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4689         hena &= ~I40E_RSS_HENA_ALL;
4690         hena |= i40e_config_hena(rss_hf);
4691         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4692         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4693         I40E_WRITE_FLUSH(hw);
4694
4695         return 0;
4696 }
4697
4698 static int
4699 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4700                          struct rte_eth_rss_conf *rss_conf)
4701 {
4702         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4704         uint64_t hena;
4705
4706         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4707         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4708         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4709                 if (rss_hf != 0) /* Enable RSS */
4710                         return -EINVAL;
4711                 return 0; /* Nothing to do */
4712         }
4713         /* RSS enabled */
4714         if (rss_hf == 0) /* Disable RSS */
4715                 return -EINVAL;
4716
4717         return i40e_hw_rss_hash_set(hw, rss_conf);
4718 }
4719
4720 static int
4721 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4722                            struct rte_eth_rss_conf *rss_conf)
4723 {
4724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4726         uint64_t hena;
4727         uint16_t i;
4728
4729         if (hash_key != NULL) {
4730                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4731                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4732                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4733         }
4734         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4735         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4736         rss_conf->rss_hf = i40e_parse_hena(hena);
4737
4738         return 0;
4739 }
4740
4741 static int
4742 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4743 {
4744         switch (filter_type) {
4745         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4746                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4747                 break;
4748         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4749                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4750                 break;
4751         case RTE_TUNNEL_FILTER_IMAC_TENID:
4752                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4753                 break;
4754         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4755                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4756                 break;
4757         case ETH_TUNNEL_FILTER_IMAC:
4758                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4759                 break;
4760         default:
4761                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4762                 return -EINVAL;
4763         }
4764
4765         return 0;
4766 }
4767
4768 static int
4769 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4770                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4771                         uint8_t add)
4772 {
4773         uint16_t ip_type;
4774         uint8_t tun_type = 0;
4775         int val, ret = 0;
4776         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4777         struct i40e_vsi *vsi = pf->main_vsi;
4778         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4779         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4780
4781         cld_filter = rte_zmalloc("tunnel_filter",
4782                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4783                 0);
4784
4785         if (NULL == cld_filter) {
4786                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4787                 return -EINVAL;
4788         }
4789         pfilter = cld_filter;
4790
4791         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4792                         sizeof(struct ether_addr));
4793         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4794                         sizeof(struct ether_addr));
4795
4796         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4797         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4798                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4799                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4800                                 &tunnel_filter->ip_addr,
4801                                 sizeof(pfilter->ipaddr.v4.data));
4802         } else {
4803                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4804                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4805                                 &tunnel_filter->ip_addr,
4806                                 sizeof(pfilter->ipaddr.v6.data));
4807         }
4808
4809         /* check tunneled type */
4810         switch (tunnel_filter->tunnel_type) {
4811         case RTE_TUNNEL_TYPE_VXLAN:
4812                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4813                 break;
4814         case RTE_TUNNEL_TYPE_NVGRE:
4815                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4816                 break;
4817         default:
4818                 /* Other tunnel types is not supported. */
4819                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4820                 rte_free(cld_filter);
4821                 return -EINVAL;
4822         }
4823
4824         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4825                                                 &pfilter->flags);
4826         if (val < 0) {
4827                 rte_free(cld_filter);
4828                 return -EINVAL;
4829         }
4830
4831         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4832                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4833         pfilter->tenant_id = tunnel_filter->tenant_id;
4834         pfilter->queue_number = tunnel_filter->queue_id;
4835
4836         if (add)
4837                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4838         else
4839                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4840                                                 cld_filter, 1);
4841
4842         rte_free(cld_filter);
4843         return ret;
4844 }
4845
4846 static int
4847 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4848 {
4849         uint8_t i;
4850
4851         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4852                 if (pf->vxlan_ports[i] == port)
4853                         return i;
4854         }
4855
4856         return -1;
4857 }
4858
4859 static int
4860 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4861 {
4862         int  idx, ret;
4863         uint8_t filter_idx;
4864         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4865
4866         idx = i40e_get_vxlan_port_idx(pf, port);
4867
4868         /* Check if port already exists */
4869         if (idx >= 0) {
4870                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4871                 return -EINVAL;
4872         }
4873
4874         /* Now check if there is space to add the new port */
4875         idx = i40e_get_vxlan_port_idx(pf, 0);
4876         if (idx < 0) {
4877                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4878                         "not adding port %d", port);
4879                 return -ENOSPC;
4880         }
4881
4882         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4883                                         &filter_idx, NULL);
4884         if (ret < 0) {
4885                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4886                 return -1;
4887         }
4888
4889         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4890                          port,  filter_idx);
4891
4892         /* New port: add it and mark its index in the bitmap */
4893         pf->vxlan_ports[idx] = port;
4894         pf->vxlan_bitmap |= (1 << idx);
4895
4896         if (!(pf->flags & I40E_FLAG_VXLAN))
4897                 pf->flags |= I40E_FLAG_VXLAN;
4898
4899         return 0;
4900 }
4901
4902 static int
4903 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4904 {
4905         int idx;
4906         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4907
4908         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4909                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4910                 return -EINVAL;
4911         }
4912
4913         idx = i40e_get_vxlan_port_idx(pf, port);
4914
4915         if (idx < 0) {
4916                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4917                 return -EINVAL;
4918         }
4919
4920         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4921                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4922                 return -1;
4923         }
4924
4925         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4926                         port, idx);
4927
4928         pf->vxlan_ports[idx] = 0;
4929         pf->vxlan_bitmap &= ~(1 << idx);
4930
4931         if (!pf->vxlan_bitmap)
4932                 pf->flags &= ~I40E_FLAG_VXLAN;
4933
4934         return 0;
4935 }
4936
4937 /* Add UDP tunneling port */
4938 static int
4939 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4940                         struct rte_eth_udp_tunnel *udp_tunnel)
4941 {
4942         int ret = 0;
4943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4944
4945         if (udp_tunnel == NULL)
4946                 return -EINVAL;
4947
4948         switch (udp_tunnel->prot_type) {
4949         case RTE_TUNNEL_TYPE_VXLAN:
4950                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4951                 break;
4952
4953         case RTE_TUNNEL_TYPE_GENEVE:
4954         case RTE_TUNNEL_TYPE_TEREDO:
4955                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4956                 ret = -1;
4957                 break;
4958
4959         default:
4960                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4961                 ret = -1;
4962                 break;
4963         }
4964
4965         return ret;
4966 }
4967
4968 /* Remove UDP tunneling port */
4969 static int
4970 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4971                         struct rte_eth_udp_tunnel *udp_tunnel)
4972 {
4973         int ret = 0;
4974         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4975
4976         if (udp_tunnel == NULL)
4977                 return -EINVAL;
4978
4979         switch (udp_tunnel->prot_type) {
4980         case RTE_TUNNEL_TYPE_VXLAN:
4981                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4982                 break;
4983         case RTE_TUNNEL_TYPE_GENEVE:
4984         case RTE_TUNNEL_TYPE_TEREDO:
4985                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4986                 ret = -1;
4987                 break;
4988         default:
4989                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4990                 ret = -1;
4991                 break;
4992         }
4993
4994         return ret;
4995 }
4996
4997 /* Calculate the maximum number of contiguous PF queues that are configured */
4998 static int
4999 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5000 {
5001         struct rte_eth_dev_data *data = pf->dev_data;
5002         int i, num;
5003         struct i40e_rx_queue *rxq;
5004
5005         num = 0;
5006         for (i = 0; i < pf->lan_nb_qps; i++) {
5007                 rxq = data->rx_queues[i];
5008                 if (rxq && rxq->q_set)
5009                         num++;
5010                 else
5011                         break;
5012         }
5013
5014         return num;
5015 }
5016
5017 /* Configure RSS */
5018 static int
5019 i40e_pf_config_rss(struct i40e_pf *pf)
5020 {
5021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5022         struct rte_eth_rss_conf rss_conf;
5023         uint32_t i, lut = 0;
5024         uint16_t j, num;
5025
5026         /*
5027          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5028          * It's necessary to calulate the actual PF queues that are configured.
5029          */
5030         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5031                 num = i40e_pf_calc_configured_queues_num(pf);
5032                 num = i40e_align_floor(num);
5033         } else
5034                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5035
5036         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5037                         num);
5038
5039         if (num == 0) {
5040                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5041                 return -ENOTSUP;
5042         }
5043
5044         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5045                 if (j == num)
5046                         j = 0;
5047                 lut = (lut << 8) | (j & ((0x1 <<
5048                         hw->func_caps.rss_table_entry_width) - 1));
5049                 if ((i & 3) == 3)
5050                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5051         }
5052
5053         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5054         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5055                 i40e_pf_disable_rss(pf);
5056                 return 0;
5057         }
5058         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5059                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5060                 /* Random default keys */
5061                 static uint32_t rss_key_default[] = {0x6b793944,
5062                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5063                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5064                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5065
5066                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5067                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5068                                                         sizeof(uint32_t);
5069         }
5070
5071         return i40e_hw_rss_hash_set(hw, &rss_conf);
5072 }
5073
5074 static int
5075 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5076                         struct rte_eth_tunnel_filter_conf *filter)
5077 {
5078         if (pf == NULL || filter == NULL) {
5079                 PMD_DRV_LOG(ERR, "Invalid parameter");
5080                 return -EINVAL;
5081         }
5082
5083         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5084                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5085                 return -EINVAL;
5086         }
5087
5088         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5089                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5090                 return -EINVAL;
5091         }
5092
5093         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5094                 (is_zero_ether_addr(filter->outer_mac))) {
5095                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5096                 return -EINVAL;
5097         }
5098
5099         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5100                 (is_zero_ether_addr(filter->inner_mac))) {
5101                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5102                 return -EINVAL;
5103         }
5104
5105         return 0;
5106 }
5107
5108 static int
5109 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5110                         void *arg)
5111 {
5112         struct rte_eth_tunnel_filter_conf *filter;
5113         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5114         int ret = I40E_SUCCESS;
5115
5116         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5117
5118         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5119                 return I40E_ERR_PARAM;
5120
5121         switch (filter_op) {
5122         case RTE_ETH_FILTER_NOP:
5123                 if (!(pf->flags & I40E_FLAG_VXLAN))
5124                         ret = I40E_NOT_SUPPORTED;
5125         case RTE_ETH_FILTER_ADD:
5126                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5127                 break;
5128         case RTE_ETH_FILTER_DELETE:
5129                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5130                 break;
5131         default:
5132                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5133                 ret = I40E_ERR_PARAM;
5134                 break;
5135         }
5136
5137         return ret;
5138 }
5139
5140 static int
5141 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5142 {
5143         int ret = 0;
5144         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5145
5146         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5147                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5148                 return -ENOTSUP;
5149         }
5150
5151         /* RSS setup */
5152         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5153                 ret = i40e_pf_config_rss(pf);
5154         else
5155                 i40e_pf_disable_rss(pf);
5156
5157         return ret;
5158 }
5159
5160 /* Get the symmetric hash enable configurations per port */
5161 static void
5162 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5163 {
5164         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5165
5166         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5167 }
5168
5169 /* Set the symmetric hash enable configurations per port */
5170 static void
5171 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5172 {
5173         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5174
5175         if (enable > 0) {
5176                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5177                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5178                                                         "been enabled");
5179                         return;
5180                 }
5181                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5182         } else {
5183                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5184                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5185                                                         "been disabled");
5186                         return;
5187                 }
5188                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5189         }
5190         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5191         I40E_WRITE_FLUSH(hw);
5192 }
5193
5194 /*
5195  * Get global configurations of hash function type and symmetric hash enable
5196  * per flow type (pctype). Note that global configuration means it affects all
5197  * the ports on the same NIC.
5198  */
5199 static int
5200 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5201                                    struct rte_eth_hash_global_conf *g_cfg)
5202 {
5203         uint32_t reg, mask = I40E_FLOW_TYPES;
5204         uint16_t i;
5205         enum i40e_filter_pctype pctype;
5206
5207         memset(g_cfg, 0, sizeof(*g_cfg));
5208         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5209         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5210                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5211         else
5212                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5213         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5214                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5215
5216         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5217                 if (!(mask & (1UL << i)))
5218                         continue;
5219                 mask &= ~(1UL << i);
5220                 /* Bit set indicats the coresponding flow type is supported */
5221                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5222                 pctype = i40e_flowtype_to_pctype(i);
5223                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5224                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5225                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5226         }
5227
5228         return 0;
5229 }
5230
5231 static int
5232 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5233 {
5234         uint32_t i;
5235         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5236
5237         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5238                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5239                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5240                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5241                                                 g_cfg->hash_func);
5242                 return -EINVAL;
5243         }
5244
5245         /*
5246          * As i40e supports less than 32 flow types, only first 32 bits need to
5247          * be checked.
5248          */
5249         mask0 = g_cfg->valid_bit_mask[0];
5250         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5251                 if (i == 0) {
5252                         /* Check if any unsupported flow type configured */
5253                         if ((mask0 | i40e_mask) ^ i40e_mask)
5254                                 goto mask_err;
5255                 } else {
5256                         if (g_cfg->valid_bit_mask[i])
5257                                 goto mask_err;
5258                 }
5259         }
5260
5261         return 0;
5262
5263 mask_err:
5264         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5265
5266         return -EINVAL;
5267 }
5268
5269 /*
5270  * Set global configurations of hash function type and symmetric hash enable
5271  * per flow type (pctype). Note any modifying global configuration will affect
5272  * all the ports on the same NIC.
5273  */
5274 static int
5275 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5276                                    struct rte_eth_hash_global_conf *g_cfg)
5277 {
5278         int ret;
5279         uint16_t i;
5280         uint32_t reg;
5281         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5282         enum i40e_filter_pctype pctype;
5283
5284         /* Check the input parameters */
5285         ret = i40e_hash_global_config_check(g_cfg);
5286         if (ret < 0)
5287                 return ret;
5288
5289         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5290                 if (!(mask0 & (1UL << i)))
5291                         continue;
5292                 mask0 &= ~(1UL << i);
5293                 pctype = i40e_flowtype_to_pctype(i);
5294                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5295                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5296                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5297         }
5298
5299         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5300         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5301                 /* Toeplitz */
5302                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5303                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5304                                                                 "Toeplitz");
5305                         goto out;
5306                 }
5307                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5308         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5309                 /* Simple XOR */
5310                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5311                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5312                                                         "Simple XOR");
5313                         goto out;
5314                 }
5315                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5316         } else
5317                 /* Use the default, and keep it as it is */
5318                 goto out;
5319
5320         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5321
5322 out:
5323         I40E_WRITE_FLUSH(hw);
5324
5325         return 0;
5326 }
5327
5328 static int
5329 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5330 {
5331         int ret = 0;
5332
5333         if (!hw || !info) {
5334                 PMD_DRV_LOG(ERR, "Invalid pointer");
5335                 return -EFAULT;
5336         }
5337
5338         switch (info->info_type) {
5339         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5340                 i40e_get_symmetric_hash_enable_per_port(hw,
5341                                         &(info->info.enable));
5342                 break;
5343         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5344                 ret = i40e_get_hash_filter_global_config(hw,
5345                                 &(info->info.global_conf));
5346                 break;
5347         default:
5348                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5349                                                         info->info_type);
5350                 ret = -EINVAL;
5351                 break;
5352         }
5353
5354         return ret;
5355 }
5356
5357 static int
5358 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5359 {
5360         int ret = 0;
5361
5362         if (!hw || !info) {
5363                 PMD_DRV_LOG(ERR, "Invalid pointer");
5364                 return -EFAULT;
5365         }
5366
5367         switch (info->info_type) {
5368         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5369                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5370                 break;
5371         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5372                 ret = i40e_set_hash_filter_global_config(hw,
5373                                 &(info->info.global_conf));
5374                 break;
5375         default:
5376                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5377                                                         info->info_type);
5378                 ret = -EINVAL;
5379                 break;
5380         }
5381
5382         return ret;
5383 }
5384
5385 /* Operations for hash function */
5386 static int
5387 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5388                       enum rte_filter_op filter_op,
5389                       void *arg)
5390 {
5391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5392         int ret = 0;
5393
5394         switch (filter_op) {
5395         case RTE_ETH_FILTER_NOP:
5396                 break;
5397         case RTE_ETH_FILTER_GET:
5398                 ret = i40e_hash_filter_get(hw,
5399                         (struct rte_eth_hash_filter_info *)arg);
5400                 break;
5401         case RTE_ETH_FILTER_SET:
5402                 ret = i40e_hash_filter_set(hw,
5403                         (struct rte_eth_hash_filter_info *)arg);
5404                 break;
5405         default:
5406                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5407                                                                 filter_op);
5408                 ret = -ENOTSUP;
5409                 break;
5410         }
5411
5412         return ret;
5413 }
5414
5415 /*
5416  * Configure ethertype filter, which can director packet by filtering
5417  * with mac address and ether_type or only ether_type
5418  */
5419 static int
5420 i40e_ethertype_filter_set(struct i40e_pf *pf,
5421                         struct rte_eth_ethertype_filter *filter,
5422                         bool add)
5423 {
5424         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5425         struct i40e_control_filter_stats stats;
5426         uint16_t flags = 0;
5427         int ret;
5428
5429         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5430                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5431                 return -EINVAL;
5432         }
5433         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5434                 filter->ether_type == ETHER_TYPE_IPv6) {
5435                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5436                         " control packet filter.", filter->ether_type);
5437                 return -EINVAL;
5438         }
5439         if (filter->ether_type == ETHER_TYPE_VLAN)
5440                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5441                         " not supported.");
5442
5443         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5444                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5445         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5446                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5447         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5448
5449         memset(&stats, 0, sizeof(stats));
5450         ret = i40e_aq_add_rem_control_packet_filter(hw,
5451                         filter->mac_addr.addr_bytes,
5452                         filter->ether_type, flags,
5453                         pf->main_vsi->seid,
5454                         filter->queue, add, &stats, NULL);
5455
5456         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5457                          " mac_etype_used = %u, etype_used = %u,"
5458                          " mac_etype_free = %u, etype_free = %u\n",
5459                          ret, stats.mac_etype_used, stats.etype_used,
5460                          stats.mac_etype_free, stats.etype_free);
5461         if (ret < 0)
5462                 return -ENOSYS;
5463         return 0;
5464 }
5465
5466 /*
5467  * Handle operations for ethertype filter.
5468  */
5469 static int
5470 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5471                                 enum rte_filter_op filter_op,
5472                                 void *arg)
5473 {
5474         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5475         int ret = 0;
5476
5477         if (filter_op == RTE_ETH_FILTER_NOP)
5478                 return ret;
5479
5480         if (arg == NULL) {
5481                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5482                             filter_op);
5483                 return -EINVAL;
5484         }
5485
5486         switch (filter_op) {
5487         case RTE_ETH_FILTER_ADD:
5488                 ret = i40e_ethertype_filter_set(pf,
5489                         (struct rte_eth_ethertype_filter *)arg,
5490                         TRUE);
5491                 break;
5492         case RTE_ETH_FILTER_DELETE:
5493                 ret = i40e_ethertype_filter_set(pf,
5494                         (struct rte_eth_ethertype_filter *)arg,
5495                         FALSE);
5496                 break;
5497         default:
5498                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5499                 ret = -ENOSYS;
5500                 break;
5501         }
5502         return ret;
5503 }
5504
5505 static int
5506 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5507                      enum rte_filter_type filter_type,
5508                      enum rte_filter_op filter_op,
5509                      void *arg)
5510 {
5511         int ret = 0;
5512
5513         if (dev == NULL)
5514                 return -EINVAL;
5515
5516         switch (filter_type) {
5517         case RTE_ETH_FILTER_HASH:
5518                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5519                 break;
5520         case RTE_ETH_FILTER_MACVLAN:
5521                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5522                 break;
5523         case RTE_ETH_FILTER_ETHERTYPE:
5524                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5525                 break;
5526         case RTE_ETH_FILTER_TUNNEL:
5527                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5528                 break;
5529         case RTE_ETH_FILTER_FDIR:
5530                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5531                 break;
5532         default:
5533                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5534                                                         filter_type);
5535                 ret = -EINVAL;
5536                 break;
5537         }
5538
5539         return ret;
5540 }
5541
5542 /*
5543  * As some registers wouldn't be reset unless a global hardware reset,
5544  * hardware initialization is needed to put those registers into an
5545  * expected initial state.
5546  */
5547 static void
5548 i40e_hw_init(struct i40e_hw *hw)
5549 {
5550         /* clear the PF Queue Filter control register */
5551         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5552
5553         /* Disable symmetric hash per port */
5554         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5555 }
5556
5557 enum i40e_filter_pctype
5558 i40e_flowtype_to_pctype(uint16_t flow_type)
5559 {
5560         static const enum i40e_filter_pctype pctype_table[] = {
5561                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5562                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5563                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5564                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5565                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5566                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5567                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5568                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5569                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5570                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5571                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5572                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5573                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5574                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5575                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5576                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5577                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5578                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5579                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5580         };
5581
5582         return pctype_table[flow_type];
5583 }
5584
5585 uint16_t
5586 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5587 {
5588         static const uint16_t flowtype_table[] = {
5589                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5590                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5591                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5592                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5593                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5594                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5595                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5596                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5597                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5598                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5599                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5600                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5601                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5602                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5603                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5604                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5605                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5606                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5607                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5608         };
5609
5610         return flowtype_table[pctype];
5611 }
5612
5613 static int
5614 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5615 {
5616         struct i40e_aq_desc desc;
5617         enum i40e_status_code status;
5618
5619         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5620         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5621         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5622         if (status < 0)
5623                 return status;
5624
5625         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5626                                         (CHAR_BIT * sizeof(uint32_t))) +
5627                                 rte_le_to_cpu_32(desc.params.internal.param3);
5628
5629         return status;
5630 }
5631
5632 /*
5633  * On X710, performance number is far from the expectation on recent firmware
5634  * versions. The fix for this issue may not be integrated in the following
5635  * firmware version. So the workaround in software driver is needed. It needs
5636  * to modify the initial values of 3 internal only registers. Note that the
5637  * workaround can be removed when it is fixed in firmware in the future.
5638  */
5639 static void
5640 i40e_configure_registers(struct i40e_hw *hw)
5641 {
5642 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5643 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5644 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5645 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5646 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5647 #define I40E_GL_SWR_PM_UP_THR_VALUE      0x03030303
5648
5649         static const struct {
5650                 uint32_t addr;
5651                 uint64_t val;
5652         } reg_table[] = {
5653                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5654                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5655                 {I40E_GL_SWR_PM_UP_THR, I40E_GL_SWR_PM_UP_THR_VALUE},
5656         };
5657         uint64_t reg;
5658         uint32_t i;
5659         int ret;
5660
5661         /* Below fix is for X710 only */
5662         if (i40e_is_40G_device(hw->device_id))
5663                 return;
5664
5665         for (i = 0; i < RTE_DIM(reg_table); i++) {
5666                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5667                 if (ret < 0) {
5668                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5669                                                         reg_table[i].addr);
5670                         break;
5671                 }
5672                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5673                                                 reg_table[i].addr, reg);
5674                 if (reg == reg_table[i].val)
5675                         continue;
5676
5677                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5678                                                 reg_table[i].val, NULL);
5679                 if (ret < 0) {
5680                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5681                                 "address of 0x%"PRIx32, reg_table[i].val,
5682                                                         reg_table[i].addr);
5683                         break;
5684                 }
5685                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5686                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5687         }
5688 }