lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 110 static int i40e_dev_configure(struct rte_eth_dev *dev);
 111 static int i40e_dev_start(struct rte_eth_dev *dev);
 112 static void i40e_dev_stop(struct rte_eth_dev *dev);
 113 static void i40e_dev_close(struct rte_eth_dev *dev);
 114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 121                                struct rte_eth_stats *stats);
 122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 124                                             uint16_t queue_id,
 125                                             uint8_t stat_idx,
 126                                             uint8_t is_rx);
 127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 128                               struct rte_eth_dev_info *dev_info);
 129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 130                                 uint16_t vlan_id,
 131                                 int on);
 132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 135                                       uint16_t queue,
 136                                       int on);
 137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 141                               struct rte_eth_fc_conf *fc_conf);
 142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                        struct rte_eth_pfc_conf *pfc_conf);
 144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 145                           struct ether_addr *mac_addr,
 146                           uint32_t index,
 147                           uint32_t pool);
 148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 150                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                     uint16_t reta_size);
 152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 153                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 154                                    uint16_t reta_size);
 155
 156 static int i40e_get_cap(struct i40e_hw *hw);
 157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 158 static int i40e_pf_setup(struct i40e_pf *pf);
 159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 162                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 163 static void i40e_stat_update_48(struct i40e_hw *hw,
 164                                uint32_t hireg,
 165                                uint32_t loreg,
 166                                bool offset_loaded,
 167                                uint64_t *offset,
 168                                uint64_t *stat);
 169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 170 static void i40e_dev_interrupt_handler(
 171                 __rte_unused struct rte_intr_handle *handle, void *param);
 172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 173                                 uint32_t base, uint32_t num);
 174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 176                         uint32_t base);
 177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 178                         uint16_t num);
 179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 180 static int i40e_veb_release(struct i40e_veb *veb);
 181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 182                                                 struct i40e_vsi *vsi);
 183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 186                                              struct i40e_macvlan_filter *mv_f,
 187                                              int num,
 188                                              struct ether_addr *addr);
 189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 190                                              struct i40e_macvlan_filter *mv_f,
 191                                              int num,
 192                                              uint16_t vlan);
 193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 195                                     struct rte_eth_rss_conf *rss_conf);
 196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 197                                       struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 199                                 struct rte_eth_udp_tunnel *udp_tunnel);
 200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 203                         struct rte_eth_ethertype_filter *filter,
 204                         bool add);
 205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 206                                 enum rte_filter_op filter_op,
 207                                 void *arg);
 208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 209                                 enum rte_filter_type filter_type,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static void i40e_configure_registers(struct i40e_hw *hw);
 213 static void i40e_hw_init(struct i40e_hw *hw);
 214
 215 static const struct rte_pci_id pci_id_i40e_map[] = {
 216 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 217 #include "rte_pci_dev_ids.h"
 218 { .vendor_id = 0, /* sentinel */ },
 219 };
 220
 221 static const struct eth_dev_ops i40e_eth_dev_ops = {
 222         .dev_configure                = i40e_dev_configure,
 223         .dev_start                    = i40e_dev_start,
 224         .dev_stop                     = i40e_dev_stop,
 225         .dev_close                    = i40e_dev_close,
 226         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 227         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 228         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 229         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 230         .dev_set_link_up              = i40e_dev_set_link_up,
 231         .dev_set_link_down            = i40e_dev_set_link_down,
 232         .link_update                  = i40e_dev_link_update,
 233         .stats_get                    = i40e_dev_stats_get,
 234         .stats_reset                  = i40e_dev_stats_reset,
 235         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 236         .dev_infos_get                = i40e_dev_info_get,
 237         .vlan_filter_set              = i40e_vlan_filter_set,
 238         .vlan_tpid_set                = i40e_vlan_tpid_set,
 239         .vlan_offload_set             = i40e_vlan_offload_set,
 240         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 241         .vlan_pvid_set                = i40e_vlan_pvid_set,
 242         .rx_queue_start               = i40e_dev_rx_queue_start,
 243         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 244         .tx_queue_start               = i40e_dev_tx_queue_start,
 245         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 246         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 247         .rx_queue_release             = i40e_dev_rx_queue_release,
 248         .rx_queue_count               = i40e_dev_rx_queue_count,
 249         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 250         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 251         .tx_queue_release             = i40e_dev_tx_queue_release,
 252         .dev_led_on                   = i40e_dev_led_on,
 253         .dev_led_off                  = i40e_dev_led_off,
 254         .flow_ctrl_set                = i40e_flow_ctrl_set,
 255         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 256         .mac_addr_add                 = i40e_macaddr_add,
 257         .mac_addr_remove              = i40e_macaddr_remove,
 258         .reta_update                  = i40e_dev_rss_reta_update,
 259         .reta_query                   = i40e_dev_rss_reta_query,
 260         .rss_hash_update              = i40e_dev_rss_hash_update,
 261         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 262         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 263         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 264         .filter_ctrl                  = i40e_dev_filter_ctrl,
 265 };
 266
 267 static struct eth_driver rte_i40e_pmd = {
 268         {
 269                 .name = "rte_i40e_pmd",
 270                 .id_table = pci_id_i40e_map,
 271                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 272         },
 273         .eth_dev_init = eth_i40e_dev_init,
 274         .dev_private_size = sizeof(struct i40e_adapter),
 275 };
 276
 277 static inline int
 278 i40e_align_floor(int n)
 279 {
 280         if (n == 0)
 281                 return 0;
 282         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 283 }
 284
 285 static inline int
 286 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 287                                      struct rte_eth_link *link)
 288 {
 289         struct rte_eth_link *dst = link;
 290         struct rte_eth_link *src = &(dev->data->dev_link);
 291
 292         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 293                                         *(uint64_t *)src) == 0)
 294                 return -1;
 295
 296         return 0;
 297 }
 298
 299 static inline int
 300 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 301                                       struct rte_eth_link *link)
 302 {
 303         struct rte_eth_link *dst = &(dev->data->dev_link);
 304         struct rte_eth_link *src = link;
 305
 306         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 307                                         *(uint64_t *)src) == 0)
 308                 return -1;
 309
 310         return 0;
 311 }
 312
 313 /*
 314  * Driver initialization routine.
 315  * Invoked once at EAL init time.
 316  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 317  */
 318 static int
 319 rte_i40e_pmd_init(const char *name __rte_unused,
 320                   const char *params __rte_unused)
 321 {
 322         PMD_INIT_FUNC_TRACE();
 323         rte_eth_driver_register(&rte_i40e_pmd);
 324
 325         return 0;
 326 }
 327
 328 static struct rte_driver rte_i40e_driver = {
 329         .type = PMD_PDEV,
 330         .init = rte_i40e_pmd_init,
 331 };
 332
 333 PMD_REGISTER_DRIVER(rte_i40e_driver);
 334
 335 /*
 336  * Initialize registers for flexible payload, which should be set by NVM.
 337  * This should be removed from code once it is fixed in NVM.
 338  */
 339 #ifndef I40E_GLQF_ORT
 340 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 341 #endif
 342 #ifndef I40E_GLQF_PIT
 343 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 344 #endif
 345
 346 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 347 {
 348         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 349         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 358
 359         /* GLQF_PIT Registers */
 360         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 361         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 362 }
 363
 364 static int
 365 eth_i40e_dev_init(struct rte_eth_dev *dev)
 366 {
 367         struct rte_pci_device *pci_dev;
 368         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 370         struct i40e_vsi *vsi;
 371         int ret;
 372         uint32_t len;
 373         uint8_t aq_fail = 0;
 374
 375         PMD_INIT_FUNC_TRACE();
 376
 377         dev->dev_ops = &i40e_eth_dev_ops;
 378         dev->rx_pkt_burst = i40e_recv_pkts;
 379         dev->tx_pkt_burst = i40e_xmit_pkts;
 380
 381         /* for secondary processes, we don't initialise any further as primary
 382          * has already done this work. Only check we don't need a different
 383          * RX function */
 384         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 385                 if (dev->data->scattered_rx)
 386                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 387                 return 0;
 388         }
 389         pci_dev = dev->pci_dev;
 390         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 391         pf->adapter->eth_dev = dev;
 392         pf->dev_data = dev->data;
 393
 394         hw->back = I40E_PF_TO_ADAPTER(pf);
 395         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 396         if (!hw->hw_addr) {
 397                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 398                              "as address is NULL");
 399                 return -ENODEV;
 400         }
 401
 402         hw->vendor_id = pci_dev->id.vendor_id;
 403         hw->device_id = pci_dev->id.device_id;
 404         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 405         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 406         hw->bus.device = pci_dev->addr.devid;
 407         hw->bus.func = pci_dev->addr.function;
 408
 409         /* Make sure all is clean before doing PF reset */
 410         i40e_clear_hw(hw);
 411
 412         /* Initialize the hardware */
 413         i40e_hw_init(hw);
 414
 415         /* Reset here to make sure all is clean for each PF */
 416         ret = i40e_pf_reset(hw);
 417         if (ret) {
 418                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 419                 return ret;
 420         }
 421
 422         /* Initialize the shared code (base driver) */
 423         ret = i40e_init_shared_code(hw);
 424         if (ret) {
 425                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 426                 return ret;
 427         }
 428
 429         /*
 430          * To work around the NVM issue,initialize registers
 431          * for flexible payload by software.
 432          * It should be removed once issues are fixed in NVM.
 433          */
 434         i40e_flex_payload_reg_init(hw);
 435
 436         /* Initialize the parameters for adminq */
 437         i40e_init_adminq_parameter(hw);
 438         ret = i40e_init_adminq(hw);
 439         if (ret != I40E_SUCCESS) {
 440                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 441                 return -EIO;
 442         }
 443         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 444                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 445                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 446                      ((hw->nvm.version >> 12) & 0xf),
 447                      ((hw->nvm.version >> 4) & 0xff),
 448                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 449
 450         /* Disable LLDP */
 451         ret = i40e_aq_stop_lldp(hw, true, NULL);
 452         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 453                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 454
 455         /* Clear PXE mode */
 456         i40e_clear_pxe_mode(hw);
 457
 458         /*
 459          * On X710, performance number is far from the expectation on recent
 460          * firmware versions. The fix for this issue may not be integrated in
 461          * the following firmware version. So the workaround in software driver
 462          * is needed. It needs to modify the initial values of 3 internal only
 463          * registers. Note that the workaround can be removed when it is fixed
 464          * in firmware in the future.
 465          */
 466         i40e_configure_registers(hw);
 467
 468         /* Get hw capabilities */
 469         ret = i40e_get_cap(hw);
 470         if (ret != I40E_SUCCESS) {
 471                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 472                 goto err_get_capabilities;
 473         }
 474
 475         /* Initialize parameters for PF */
 476         ret = i40e_pf_parameter_init(dev);
 477         if (ret != 0) {
 478                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 479                 goto err_parameter_init;
 480         }
 481
 482         /* Initialize the queue management */
 483         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 484         if (ret < 0) {
 485                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 486                 goto err_qp_pool_init;
 487         }
 488         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 489                                 hw->func_caps.num_msix_vectors - 1);
 490         if (ret < 0) {
 491                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 492                 goto err_msix_pool_init;
 493         }
 494
 495         /* Initialize lan hmc */
 496         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 497                                 hw->func_caps.num_rx_qp, 0, 0);
 498         if (ret != I40E_SUCCESS) {
 499                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 500                 goto err_init_lan_hmc;
 501         }
 502
 503         /* Configure lan hmc */
 504         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 505         if (ret != I40E_SUCCESS) {
 506                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 507                 goto err_configure_lan_hmc;
 508         }
 509
 510         /* Get and check the mac address */
 511         i40e_get_mac_addr(hw, hw->mac.addr);
 512         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 513                 PMD_INIT_LOG(ERR, "mac address is not valid");
 514                 ret = -EIO;
 515                 goto err_get_mac_addr;
 516         }
 517         /* Copy the permanent MAC address */
 518         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 519                         (struct ether_addr *) hw->mac.perm_addr);
 520
 521         /* Disable flow control */
 522         hw->fc.requested_mode = I40E_FC_NONE;
 523         i40e_set_fc(hw, &aq_fail, TRUE);
 524
 525         /* PF setup, which includes VSI setup */
 526         ret = i40e_pf_setup(pf);
 527         if (ret) {
 528                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 529                 goto err_setup_pf_switch;
 530         }
 531
 532         vsi = pf->main_vsi;
 533
 534         /* Disable double vlan by default */
 535         i40e_vsi_config_double_vlan(vsi, FALSE);
 536
 537         if (!vsi->max_macaddrs)
 538                 len = ETHER_ADDR_LEN;
 539         else
 540                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 541
 542         /* Should be after VSI initialized */
 543         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 544         if (!dev->data->mac_addrs) {
 545                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 546                                         "for storing mac address");
 547                 goto err_mac_alloc;
 548         }
 549         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 550                                         &dev->data->mac_addrs[0]);
 551
 552         /* initialize pf host driver to setup SRIOV resource if applicable */
 553         i40e_pf_host_init(dev);
 554
 555         /* register callback func to eal lib */
 556         rte_intr_callback_register(&(pci_dev->intr_handle),
 557                 i40e_dev_interrupt_handler, (void *)dev);
 558
 559         /* configure and enable device interrupt */
 560         i40e_pf_config_irq0(hw);
 561         i40e_pf_enable_irq0(hw);
 562
 563         /* enable uio intr after callback register */
 564         rte_intr_enable(&(pci_dev->intr_handle));
 565
 566         return 0;
 567
 568 err_mac_alloc:
 569         i40e_vsi_release(pf->main_vsi);
 570 err_setup_pf_switch:
 571 err_get_mac_addr:
 572 err_configure_lan_hmc:
 573         (void)i40e_shutdown_lan_hmc(hw);
 574 err_init_lan_hmc:
 575         i40e_res_pool_destroy(&pf->msix_pool);
 576 err_msix_pool_init:
 577         i40e_res_pool_destroy(&pf->qp_pool);
 578 err_qp_pool_init:
 579 err_parameter_init:
 580 err_get_capabilities:
 581         (void)i40e_shutdown_adminq(hw);
 582
 583         return ret;
 584 }
 585
 586 static int
 587 i40e_dev_configure(struct rte_eth_dev *dev)
 588 {
 589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 590         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 591         int ret;
 592
 593         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 594                 ret = i40e_fdir_setup(pf);
 595                 if (ret != I40E_SUCCESS) {
 596                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 597                         return -ENOTSUP;
 598                 }
 599                 ret = i40e_fdir_configure(dev);
 600                 if (ret < 0) {
 601                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 602                         goto err;
 603                 }
 604         } else
 605                 i40e_fdir_teardown(pf);
 606
 607         ret = i40e_dev_init_vlan(dev);
 608         if (ret < 0)
 609                 goto err;
 610
 611         /* VMDQ setup.
 612          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 613          *  RSS setting have different requirements.
 614          *  General PMD driver call sequence are NIC init, configure,
 615          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 616          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 617          *  applicable. So, VMDQ setting has to be done before
 618          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 619          *  For RSS setting, it will try to calculate actual configured RX queue
 620          *  number, which will be available after rx_queue_setup(). dev_start()
 621          *  function is good to place RSS setup.
 622          */
 623         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 624                 ret = i40e_vmdq_setup(dev);
 625                 if (ret)
 626                         goto err;
 627         }
 628         return 0;
 629 err:
 630         i40e_fdir_teardown(pf);
 631         return ret;
 632 }
 633
 634 void
 635 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 636 {
 637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 638         uint16_t msix_vect = vsi->msix_intr;
 639         uint16_t i;
 640
 641         for (i = 0; i < vsi->nb_qps; i++) {
 642                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 643                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 644                 rte_wmb();
 645         }
 646
 647         if (vsi->type != I40E_VSI_SRIOV) {
 648                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 649                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 650                                 msix_vect - 1), 0);
 651         } else {
 652                 uint32_t reg;
 653                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 654                         vsi->user_param + (msix_vect - 1);
 655
 656                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 657         }
 658         I40E_WRITE_FLUSH(hw);
 659 }
 660
 661 static inline uint16_t
 662 i40e_calc_itr_interval(int16_t interval)
 663 {
 664         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 665                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 666
 667         /* Convert to hardware count, as writing each 1 represents 2 us */
 668         return (interval/2);
 669 }
 670
 671 void
 672 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 673 {
 674         uint32_t val;
 675         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 676         uint16_t msix_vect = vsi->msix_intr;
 677         int i;
 678
 679         for (i = 0; i < vsi->nb_qps; i++)
 680                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 681
 682         /* Bind all RX queues to allocated MSIX interrupt */
 683         for (i = 0; i < vsi->nb_qps; i++) {
 684                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 685                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 686                         ((vsi->base_queue + i + 1) <<
 687                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 688                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 689                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 690
 691                 if (i == vsi->nb_qps - 1)
 692                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 693                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 694         }
 695
 696         /* Write first RX queue to Link list register as the head element */
 697         if (vsi->type != I40E_VSI_SRIOV) {
 698                 uint16_t interval =
 699                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 700
 701                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 702                                                 (vsi->base_queue <<
 703                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 704                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 705
 706                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 707                                                 msix_vect - 1), interval);
 708
 709 #ifndef I40E_GLINT_CTL
 710 #define I40E_GLINT_CTL                     0x0003F800
 711 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 712 #endif
 713                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 714                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 715                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 716         } else {
 717                 uint32_t reg;
 718
 719                 /* num_msix_vectors_vf needs to minus irq0 */
 720                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 721                         vsi->user_param + (msix_vect - 1);
 722
 723                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 724                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 725                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 726         }
 727
 728         I40E_WRITE_FLUSH(hw);
 729 }
 730
 731 static void
 732 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 733 {
 734         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 735         uint16_t interval = i40e_calc_itr_interval(\
 736                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 737
 738         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 739                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 740                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 741                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 742                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 743 }
 744
 745 static void
 746 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 747 {
 748         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 749
 750         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 751 }
 752
 753 static inline uint8_t
 754 i40e_parse_link_speed(uint16_t eth_link_speed)
 755 {
 756         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 757
 758         switch (eth_link_speed) {
 759         case ETH_LINK_SPEED_40G:
 760                 link_speed = I40E_LINK_SPEED_40GB;
 761                 break;
 762         case ETH_LINK_SPEED_20G:
 763                 link_speed = I40E_LINK_SPEED_20GB;
 764                 break;
 765         case ETH_LINK_SPEED_10G:
 766                 link_speed = I40E_LINK_SPEED_10GB;
 767                 break;
 768         case ETH_LINK_SPEED_1000:
 769                 link_speed = I40E_LINK_SPEED_1GB;
 770                 break;
 771         case ETH_LINK_SPEED_100:
 772                 link_speed = I40E_LINK_SPEED_100MB;
 773                 break;
 774         }
 775
 776         return link_speed;
 777 }
 778
 779 static int
 780 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 781 {
 782         enum i40e_status_code status;
 783         struct i40e_aq_get_phy_abilities_resp phy_ab;
 784         struct i40e_aq_set_phy_config phy_conf;
 785         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 786                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 787                         I40E_AQ_PHY_FLAG_LOW_POWER;
 788         const uint8_t advt = I40E_LINK_SPEED_40GB |
 789                         I40E_LINK_SPEED_10GB |
 790                         I40E_LINK_SPEED_1GB |
 791                         I40E_LINK_SPEED_100MB;
 792         int ret = -ENOTSUP;
 793
 794         /* Skip it on 40G interfaces, as a workaround for the link issue */
 795         if (i40e_is_40G_device(hw->device_id))
 796                 return I40E_SUCCESS;
 797
 798         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 799                                               NULL);
 800         if (status)
 801                 return ret;
 802
 803         memset(&phy_conf, 0, sizeof(phy_conf));
 804
 805         /* bits 0-2 use the values from get_phy_abilities_resp */
 806         abilities &= ~mask;
 807         abilities |= phy_ab.abilities & mask;
 808
 809         /* update ablities and speed */
 810         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 811                 phy_conf.link_speed = advt;
 812         else
 813                 phy_conf.link_speed = force_speed;
 814
 815         phy_conf.abilities = abilities;
 816
 817         /* use get_phy_abilities_resp value for the rest */
 818         phy_conf.phy_type = phy_ab.phy_type;
 819         phy_conf.eee_capability = phy_ab.eee_capability;
 820         phy_conf.eeer = phy_ab.eeer_val;
 821         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 822
 823         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 824                     phy_ab.abilities, phy_ab.link_speed);
 825         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 826                     phy_conf.abilities, phy_conf.link_speed);
 827
 828         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 829         if (status)
 830                 return ret;
 831
 832         return I40E_SUCCESS;
 833 }
 834
 835 static int
 836 i40e_apply_link_speed(struct rte_eth_dev *dev)
 837 {
 838         uint8_t speed;
 839         uint8_t abilities = 0;
 840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 841         struct rte_eth_conf *conf = &dev->data->dev_conf;
 842
 843         speed = i40e_parse_link_speed(conf->link_speed);
 844         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 845         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 846                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 847         else
 848                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 849
 850         return i40e_phy_conf_link(hw, abilities, speed);
 851 }
 852
 853 static int
 854 i40e_dev_start(struct rte_eth_dev *dev)
 855 {
 856         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 858         struct i40e_vsi *main_vsi = pf->main_vsi;
 859         int ret, i;
 860
 861         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 862                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 863                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 864                              dev->data->dev_conf.link_duplex,
 865                              dev->data->port_id);
 866                 return -EINVAL;
 867         }
 868
 869         /* Initialize VSI */
 870         ret = i40e_dev_rxtx_init(pf);
 871         if (ret != I40E_SUCCESS) {
 872                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 873                 goto err_up;
 874         }
 875
 876         /* Map queues with MSIX interrupt */
 877         i40e_vsi_queues_bind_intr(main_vsi);
 878         i40e_vsi_enable_queues_intr(main_vsi);
 879
 880         /* Map VMDQ VSI queues with MSIX interrupt */
 881         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 882                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 883                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 884         }
 885
 886         /* enable FDIR MSIX interrupt */
 887         if (pf->fdir.fdir_vsi) {
 888                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 889                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 890         }
 891
 892         /* Enable all queues which have been configured */
 893         ret = i40e_dev_switch_queues(pf, TRUE);
 894         if (ret != I40E_SUCCESS) {
 895                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 896                 goto err_up;
 897         }
 898
 899         /* Enable receiving broadcast packets */
 900         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 901         if (ret != I40E_SUCCESS)
 902                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 903
 904         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 905                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 906                                                 true, NULL);
 907                 if (ret != I40E_SUCCESS)
 908                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 909         }
 910
 911         /* Apply link configure */
 912         ret = i40e_apply_link_speed(dev);
 913         if (I40E_SUCCESS != ret) {
 914                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 915                 goto err_up;
 916         }
 917
 918         return I40E_SUCCESS;
 919
 920 err_up:
 921         i40e_dev_switch_queues(pf, FALSE);
 922         i40e_dev_clear_queues(dev);
 923
 924         return ret;
 925 }
 926
 927 static void
 928 i40e_dev_stop(struct rte_eth_dev *dev)
 929 {
 930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 931         struct i40e_vsi *main_vsi = pf->main_vsi;
 932         int i;
 933
 934         /* Disable all queues */
 935         i40e_dev_switch_queues(pf, FALSE);
 936
 937         /* un-map queues with interrupt registers */
 938         i40e_vsi_disable_queues_intr(main_vsi);
 939         i40e_vsi_queues_unbind_intr(main_vsi);
 940
 941         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 942                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 943                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 944         }
 945
 946         if (pf->fdir.fdir_vsi) {
 947                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 948                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 949         }
 950         /* Clear all queues and release memory */
 951         i40e_dev_clear_queues(dev);
 952
 953         /* Set link down */
 954         i40e_dev_set_link_down(dev);
 955
 956 }
 957
 958 static void
 959 i40e_dev_close(struct rte_eth_dev *dev)
 960 {
 961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 962         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 963         uint32_t reg;
 964
 965         PMD_INIT_FUNC_TRACE();
 966
 967         i40e_dev_stop(dev);
 968
 969         /* Disable interrupt */
 970         i40e_pf_disable_irq0(hw);
 971         rte_intr_disable(&(dev->pci_dev->intr_handle));
 972
 973         /* shutdown and destroy the HMC */
 974         i40e_shutdown_lan_hmc(hw);
 975
 976         /* release all the existing VSIs and VEBs */
 977         i40e_fdir_teardown(pf);
 978         i40e_vsi_release(pf->main_vsi);
 979
 980         /* shutdown the adminq */
 981         i40e_aq_queue_shutdown(hw, true);
 982         i40e_shutdown_adminq(hw);
 983
 984         i40e_res_pool_destroy(&pf->qp_pool);
 985         i40e_res_pool_destroy(&pf->msix_pool);
 986
 987         /* force a PF reset to clean anything leftover */
 988         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 989         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 990                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 991         I40E_WRITE_FLUSH(hw);
 992 }
 993
 994 static void
 995 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 996 {
 997         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 999         struct i40e_vsi *vsi = pf->main_vsi;
1000         int status;
1001
1002         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1003                                                         true, NULL);
1004         if (status != I40E_SUCCESS)
1005                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1006
1007         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1008                                                         TRUE, NULL);
1009         if (status != I40E_SUCCESS)
1010                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1011
1012 }
1013
1014 static void
1015 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1016 {
1017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1018         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019         struct i40e_vsi *vsi = pf->main_vsi;
1020         int status;
1021
1022         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1023                                                         false, NULL);
1024         if (status != I40E_SUCCESS)
1025                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1026
1027         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1028                                                         false, NULL);
1029         if (status != I40E_SUCCESS)
1030                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1031 }
1032
1033 static void
1034 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1035 {
1036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         struct i40e_vsi *vsi = pf->main_vsi;
1039         int ret;
1040
1041         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1042         if (ret != I40E_SUCCESS)
1043                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1044 }
1045
1046 static void
1047 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1048 {
1049         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1050         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051         struct i40e_vsi *vsi = pf->main_vsi;
1052         int ret;
1053
1054         if (dev->data->promiscuous == 1)
1055                 return; /* must remain in all_multicast mode */
1056
1057         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1058                                 vsi->seid, FALSE, NULL);
1059         if (ret != I40E_SUCCESS)
1060                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1061 }
1062
1063 /*
1064  * Set device link up.
1065  */
1066 static int
1067 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1068 {
1069         /* re-apply link speed setting */
1070         return i40e_apply_link_speed(dev);
1071 }
1072
1073 /*
1074  * Set device link down.
1075  */
1076 static int
1077 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1078 {
1079         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1080         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1082
1083         return i40e_phy_conf_link(hw, abilities, speed);
1084 }
1085
1086 int
1087 i40e_dev_link_update(struct rte_eth_dev *dev,
1088                      int wait_to_complete)
1089 {
1090 #define CHECK_INTERVAL 100  /* 100ms */
1091 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093         struct i40e_link_status link_status;
1094         struct rte_eth_link link, old;
1095         int status;
1096         unsigned rep_cnt = MAX_REPEAT_TIME;
1097
1098         memset(&link, 0, sizeof(link));
1099         memset(&old, 0, sizeof(old));
1100         memset(&link_status, 0, sizeof(link_status));
1101         rte_i40e_dev_atomic_read_link_status(dev, &old);
1102
1103         do {
1104                 /* Get link status information from hardware */
1105                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1106                 if (status != I40E_SUCCESS) {
1107                         link.link_speed = ETH_LINK_SPEED_100;
1108                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1109                         PMD_DRV_LOG(ERR, "Failed to get link info");
1110                         goto out;
1111                 }
1112
1113                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1114                 if (!wait_to_complete)
1115                         break;
1116
1117                 rte_delay_ms(CHECK_INTERVAL);
1118         } while (!link.link_status && rep_cnt--);
1119
1120         if (!link.link_status)
1121                 goto out;
1122
1123         /* i40e uses full duplex only */
1124         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1125
1126         /* Parse the link status */
1127         switch (link_status.link_speed) {
1128         case I40E_LINK_SPEED_100MB:
1129                 link.link_speed = ETH_LINK_SPEED_100;
1130                 break;
1131         case I40E_LINK_SPEED_1GB:
1132                 link.link_speed = ETH_LINK_SPEED_1000;
1133                 break;
1134         case I40E_LINK_SPEED_10GB:
1135                 link.link_speed = ETH_LINK_SPEED_10G;
1136                 break;
1137         case I40E_LINK_SPEED_20GB:
1138                 link.link_speed = ETH_LINK_SPEED_20G;
1139                 break;
1140         case I40E_LINK_SPEED_40GB:
1141                 link.link_speed = ETH_LINK_SPEED_40G;
1142                 break;
1143         default:
1144                 link.link_speed = ETH_LINK_SPEED_100;
1145                 break;
1146         }
1147
1148 out:
1149         rte_i40e_dev_atomic_write_link_status(dev, &link);
1150         if (link.link_status == old.link_status)
1151                 return -1;
1152
1153         return 0;
1154 }
1155
1156 /* Get all the statistics of a VSI */
1157 void
1158 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1159 {
1160         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1161         struct i40e_eth_stats *nes = &vsi->eth_stats;
1162         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1163         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1164
1165         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1166                             vsi->offset_loaded, &oes->rx_bytes,
1167                             &nes->rx_bytes);
1168         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1169                             vsi->offset_loaded, &oes->rx_unicast,
1170                             &nes->rx_unicast);
1171         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1172                             vsi->offset_loaded, &oes->rx_multicast,
1173                             &nes->rx_multicast);
1174         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1175                             vsi->offset_loaded, &oes->rx_broadcast,
1176                             &nes->rx_broadcast);
1177         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1178                             &oes->rx_discards, &nes->rx_discards);
1179         /* GLV_REPC not supported */
1180         /* GLV_RMPC not supported */
1181         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1182                             &oes->rx_unknown_protocol,
1183                             &nes->rx_unknown_protocol);
1184         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1185                             vsi->offset_loaded, &oes->tx_bytes,
1186                             &nes->tx_bytes);
1187         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1188                             vsi->offset_loaded, &oes->tx_unicast,
1189                             &nes->tx_unicast);
1190         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1191                             vsi->offset_loaded, &oes->tx_multicast,
1192                             &nes->tx_multicast);
1193         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1194                             vsi->offset_loaded,  &oes->tx_broadcast,
1195                             &nes->tx_broadcast);
1196         /* GLV_TDPC not supported */
1197         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1198                             &oes->tx_errors, &nes->tx_errors);
1199         vsi->offset_loaded = true;
1200
1201         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1202                     vsi->vsi_id);
1203         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1204         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1205         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1206         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1207         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1208         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1209                     nes->rx_unknown_protocol);
1210         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1211         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1212         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1213         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1214         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1215         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1216         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1217                     vsi->vsi_id);
1218 }
1219
1220 /* Get all statistics of a port */
1221 static void
1222 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1223 {
1224         uint32_t i;
1225         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1228         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1229
1230         /* Get statistics of struct i40e_eth_stats */
1231         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1232                             I40E_GLPRT_GORCL(hw->port),
1233                             pf->offset_loaded, &os->eth.rx_bytes,
1234                             &ns->eth.rx_bytes);
1235         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1236                             I40E_GLPRT_UPRCL(hw->port),
1237                             pf->offset_loaded, &os->eth.rx_unicast,
1238                             &ns->eth.rx_unicast);
1239         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1240                             I40E_GLPRT_MPRCL(hw->port),
1241                             pf->offset_loaded, &os->eth.rx_multicast,
1242                             &ns->eth.rx_multicast);
1243         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1244                             I40E_GLPRT_BPRCL(hw->port),
1245                             pf->offset_loaded, &os->eth.rx_broadcast,
1246                             &ns->eth.rx_broadcast);
1247         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1248                             pf->offset_loaded, &os->eth.rx_discards,
1249                             &ns->eth.rx_discards);
1250         /* GLPRT_REPC not supported */
1251         /* GLPRT_RMPC not supported */
1252         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1253                             pf->offset_loaded,
1254                             &os->eth.rx_unknown_protocol,
1255                             &ns->eth.rx_unknown_protocol);
1256         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1257                             I40E_GLPRT_GOTCL(hw->port),
1258                             pf->offset_loaded, &os->eth.tx_bytes,
1259                             &ns->eth.tx_bytes);
1260         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1261                             I40E_GLPRT_UPTCL(hw->port),
1262                             pf->offset_loaded, &os->eth.tx_unicast,
1263                             &ns->eth.tx_unicast);
1264         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1265                             I40E_GLPRT_MPTCL(hw->port),
1266                             pf->offset_loaded, &os->eth.tx_multicast,
1267                             &ns->eth.tx_multicast);
1268         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1269                             I40E_GLPRT_BPTCL(hw->port),
1270                             pf->offset_loaded, &os->eth.tx_broadcast,
1271                             &ns->eth.tx_broadcast);
1272         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1273                             pf->offset_loaded, &os->eth.tx_discards,
1274                             &ns->eth.tx_discards);
1275         /* GLPRT_TEPC not supported */
1276
1277         /* additional port specific stats */
1278         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1279                             pf->offset_loaded, &os->tx_dropped_link_down,
1280                             &ns->tx_dropped_link_down);
1281         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1282                             pf->offset_loaded, &os->crc_errors,
1283                             &ns->crc_errors);
1284         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1285                             pf->offset_loaded, &os->illegal_bytes,
1286                             &ns->illegal_bytes);
1287         /* GLPRT_ERRBC not supported */
1288         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1289                             pf->offset_loaded, &os->mac_local_faults,
1290                             &ns->mac_local_faults);
1291         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1292                             pf->offset_loaded, &os->mac_remote_faults,
1293                             &ns->mac_remote_faults);
1294         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1295                             pf->offset_loaded, &os->rx_length_errors,
1296                             &ns->rx_length_errors);
1297         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1298                             pf->offset_loaded, &os->link_xon_rx,
1299                             &ns->link_xon_rx);
1300         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1301                             pf->offset_loaded, &os->link_xoff_rx,
1302                             &ns->link_xoff_rx);
1303         for (i = 0; i < 8; i++) {
1304                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1305                                     pf->offset_loaded,
1306                                     &os->priority_xon_rx[i],
1307                                     &ns->priority_xon_rx[i]);
1308                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1309                                     pf->offset_loaded,
1310                                     &os->priority_xoff_rx[i],
1311                                     &ns->priority_xoff_rx[i]);
1312         }
1313         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1314                             pf->offset_loaded, &os->link_xon_tx,
1315                             &ns->link_xon_tx);
1316         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1317                             pf->offset_loaded, &os->link_xoff_tx,
1318                             &ns->link_xoff_tx);
1319         for (i = 0; i < 8; i++) {
1320                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1321                                     pf->offset_loaded,
1322                                     &os->priority_xon_tx[i],
1323                                     &ns->priority_xon_tx[i]);
1324                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1325                                     pf->offset_loaded,
1326                                     &os->priority_xoff_tx[i],
1327                                     &ns->priority_xoff_tx[i]);
1328                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1329                                     pf->offset_loaded,
1330                                     &os->priority_xon_2_xoff[i],
1331                                     &ns->priority_xon_2_xoff[i]);
1332         }
1333         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1334                             I40E_GLPRT_PRC64L(hw->port),
1335                             pf->offset_loaded, &os->rx_size_64,
1336                             &ns->rx_size_64);
1337         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1338                             I40E_GLPRT_PRC127L(hw->port),
1339                             pf->offset_loaded, &os->rx_size_127,
1340                             &ns->rx_size_127);
1341         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1342                             I40E_GLPRT_PRC255L(hw->port),
1343                             pf->offset_loaded, &os->rx_size_255,
1344                             &ns->rx_size_255);
1345         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1346                             I40E_GLPRT_PRC511L(hw->port),
1347                             pf->offset_loaded, &os->rx_size_511,
1348                             &ns->rx_size_511);
1349         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1350                             I40E_GLPRT_PRC1023L(hw->port),
1351                             pf->offset_loaded, &os->rx_size_1023,
1352                             &ns->rx_size_1023);
1353         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1354                             I40E_GLPRT_PRC1522L(hw->port),
1355                             pf->offset_loaded, &os->rx_size_1522,
1356                             &ns->rx_size_1522);
1357         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1358                             I40E_GLPRT_PRC9522L(hw->port),
1359                             pf->offset_loaded, &os->rx_size_big,
1360                             &ns->rx_size_big);
1361         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1362                             pf->offset_loaded, &os->rx_undersize,
1363                             &ns->rx_undersize);
1364         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1365                             pf->offset_loaded, &os->rx_fragments,
1366                             &ns->rx_fragments);
1367         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1368                             pf->offset_loaded, &os->rx_oversize,
1369                             &ns->rx_oversize);
1370         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1371                             pf->offset_loaded, &os->rx_jabber,
1372                             &ns->rx_jabber);
1373         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1374                             I40E_GLPRT_PTC64L(hw->port),
1375                             pf->offset_loaded, &os->tx_size_64,
1376                             &ns->tx_size_64);
1377         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1378                             I40E_GLPRT_PTC127L(hw->port),
1379                             pf->offset_loaded, &os->tx_size_127,
1380                             &ns->tx_size_127);
1381         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1382                             I40E_GLPRT_PTC255L(hw->port),
1383                             pf->offset_loaded, &os->tx_size_255,
1384                             &ns->tx_size_255);
1385         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1386                             I40E_GLPRT_PTC511L(hw->port),
1387                             pf->offset_loaded, &os->tx_size_511,
1388                             &ns->tx_size_511);
1389         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1390                             I40E_GLPRT_PTC1023L(hw->port),
1391                             pf->offset_loaded, &os->tx_size_1023,
1392                             &ns->tx_size_1023);
1393         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1394                             I40E_GLPRT_PTC1522L(hw->port),
1395                             pf->offset_loaded, &os->tx_size_1522,
1396                             &ns->tx_size_1522);
1397         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1398                             I40E_GLPRT_PTC9522L(hw->port),
1399                             pf->offset_loaded, &os->tx_size_big,
1400                             &ns->tx_size_big);
1401         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1402                            pf->offset_loaded,
1403                            &os->fd_sb_match, &ns->fd_sb_match);
1404         /* GLPRT_MSPDC not supported */
1405         /* GLPRT_XEC not supported */
1406
1407         pf->offset_loaded = true;
1408
1409         if (pf->main_vsi)
1410                 i40e_update_vsi_stats(pf->main_vsi);
1411
1412         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1413                                                 ns->eth.rx_broadcast;
1414         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1415                                                 ns->eth.tx_broadcast;
1416         stats->ibytes   = ns->eth.rx_bytes;
1417         stats->obytes   = ns->eth.tx_bytes;
1418         stats->oerrors  = ns->eth.tx_errors;
1419         stats->imcasts  = ns->eth.rx_multicast;
1420         stats->fdirmatch = ns->fd_sb_match;
1421
1422         /* Rx Errors */
1423         stats->ibadcrc  = ns->crc_errors;
1424         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1425                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1426         stats->imissed  = ns->eth.rx_discards;
1427         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1428
1429         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1430         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1431         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1432         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1433         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1434         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1435         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1436                     ns->eth.rx_unknown_protocol);
1437         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1438         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1439         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1440         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1441         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1442         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1443
1444         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1445                     ns->tx_dropped_link_down);
1446         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1447         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1448                     ns->illegal_bytes);
1449         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1450         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1451                     ns->mac_local_faults);
1452         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1453                     ns->mac_remote_faults);
1454         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1455                     ns->rx_length_errors);
1456         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1457         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1458         for (i = 0; i < 8; i++) {
1459                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1460                                 i, ns->priority_xon_rx[i]);
1461                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1462                                 i, ns->priority_xoff_rx[i]);
1463         }
1464         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1465         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1466         for (i = 0; i < 8; i++) {
1467                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1468                                 i, ns->priority_xon_tx[i]);
1469                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1470                                 i, ns->priority_xoff_tx[i]);
1471                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1472                                 i, ns->priority_xon_2_xoff[i]);
1473         }
1474         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1475         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1476         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1477         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1478         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1479         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1480         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1481         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1482         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1483         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1484         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1485         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1486         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1487         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1488         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1489         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1490         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1491         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1492         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1493                         ns->mac_short_packet_dropped);
1494         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1495                     ns->checksum_error);
1496         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1497         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1498 }
1499
1500 /* Reset the statistics */
1501 static void
1502 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1503 {
1504         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1505
1506         /* It results in reloading the start point of each counter */
1507         pf->offset_loaded = false;
1508 }
1509
1510 static int
1511 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1512                                  __rte_unused uint16_t queue_id,
1513                                  __rte_unused uint8_t stat_idx,
1514                                  __rte_unused uint8_t is_rx)
1515 {
1516         PMD_INIT_FUNC_TRACE();
1517
1518         return -ENOSYS;
1519 }
1520
1521 static void
1522 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1523 {
1524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1525         struct i40e_vsi *vsi = pf->main_vsi;
1526
1527         dev_info->max_rx_queues = vsi->nb_qps;
1528         dev_info->max_tx_queues = vsi->nb_qps;
1529         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1530         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1531         dev_info->max_mac_addrs = vsi->max_macaddrs;
1532         dev_info->max_vfs = dev->pci_dev->max_vfs;
1533         dev_info->rx_offload_capa =
1534                 DEV_RX_OFFLOAD_VLAN_STRIP |
1535                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1536                 DEV_RX_OFFLOAD_UDP_CKSUM |
1537                 DEV_RX_OFFLOAD_TCP_CKSUM;
1538         dev_info->tx_offload_capa =
1539                 DEV_TX_OFFLOAD_VLAN_INSERT |
1540                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1541                 DEV_TX_OFFLOAD_UDP_CKSUM |
1542                 DEV_TX_OFFLOAD_TCP_CKSUM |
1543                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1544                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1545                 DEV_TX_OFFLOAD_TCP_TSO;
1546         dev_info->reta_size = pf->hash_lut_size;
1547         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1548
1549         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1550                 .rx_thresh = {
1551                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1552                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1553                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1554                 },
1555                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1556                 .rx_drop_en = 0,
1557         };
1558
1559         dev_info->default_txconf = (struct rte_eth_txconf) {
1560                 .tx_thresh = {
1561                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1562                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1563                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1564                 },
1565                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1566                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1567                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1568                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1569         };
1570
1571         if (pf->flags | I40E_FLAG_VMDQ) {
1572                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1573                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1574                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1575                                                 pf->max_nb_vmdq_vsi;
1576                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1577                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1578                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1579         }
1580 }
1581
1582 static int
1583 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1584 {
1585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1586         struct i40e_vsi *vsi = pf->main_vsi;
1587         PMD_INIT_FUNC_TRACE();
1588
1589         if (on)
1590                 return i40e_vsi_add_vlan(vsi, vlan_id);
1591         else
1592                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1593 }
1594
1595 static void
1596 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1597                    __rte_unused uint16_t tpid)
1598 {
1599         PMD_INIT_FUNC_TRACE();
1600 }
1601
1602 static void
1603 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1604 {
1605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1606         struct i40e_vsi *vsi = pf->main_vsi;
1607
1608         if (mask & ETH_VLAN_STRIP_MASK) {
1609                 /* Enable or disable VLAN stripping */
1610                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1611                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1612                 else
1613                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1614         }
1615
1616         if (mask & ETH_VLAN_EXTEND_MASK) {
1617                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1618                         i40e_vsi_config_double_vlan(vsi, TRUE);
1619                 else
1620                         i40e_vsi_config_double_vlan(vsi, FALSE);
1621         }
1622 }
1623
1624 static void
1625 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1626                           __rte_unused uint16_t queue,
1627                           __rte_unused int on)
1628 {
1629         PMD_INIT_FUNC_TRACE();
1630 }
1631
1632 static int
1633 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1634 {
1635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1636         struct i40e_vsi *vsi = pf->main_vsi;
1637         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1638         struct i40e_vsi_vlan_pvid_info info;
1639
1640         memset(&info, 0, sizeof(info));
1641         info.on = on;
1642         if (info.on)
1643                 info.config.pvid = pvid;
1644         else {
1645                 info.config.reject.tagged =
1646                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1647                 info.config.reject.untagged =
1648                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1649         }
1650
1651         return i40e_vsi_vlan_pvid_set(vsi, &info);
1652 }
1653
1654 static int
1655 i40e_dev_led_on(struct rte_eth_dev *dev)
1656 {
1657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658         uint32_t mode = i40e_led_get(hw);
1659
1660         if (mode == 0)
1661                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1662
1663         return 0;
1664 }
1665
1666 static int
1667 i40e_dev_led_off(struct rte_eth_dev *dev)
1668 {
1669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         uint32_t mode = i40e_led_get(hw);
1671
1672         if (mode != 0)
1673                 i40e_led_set(hw, 0, false);
1674
1675         return 0;
1676 }
1677
1678 static int
1679 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1680                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1681 {
1682         PMD_INIT_FUNC_TRACE();
1683
1684         return -ENOSYS;
1685 }
1686
1687 static int
1688 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1689                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1690 {
1691         PMD_INIT_FUNC_TRACE();
1692
1693         return -ENOSYS;
1694 }
1695
1696 /* Add a MAC address, and update filters */
1697 static void
1698 i40e_macaddr_add(struct rte_eth_dev *dev,
1699                  struct ether_addr *mac_addr,
1700                  __rte_unused uint32_t index,
1701                  uint32_t pool)
1702 {
1703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1704         struct i40e_mac_filter_info mac_filter;
1705         struct i40e_vsi *vsi;
1706         int ret;
1707
1708         /* If VMDQ not enabled or configured, return */
1709         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1710                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1711                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1712                         pool);
1713                 return;
1714         }
1715
1716         if (pool > pf->nb_cfg_vmdq_vsi) {
1717                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1718                                 pool, pf->nb_cfg_vmdq_vsi);
1719                 return;
1720         }
1721
1722         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1723         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1724
1725         if (pool == 0)
1726                 vsi = pf->main_vsi;
1727         else
1728                 vsi = pf->vmdq[pool - 1].vsi;
1729
1730         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1731         if (ret != I40E_SUCCESS) {
1732                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1733                 return;
1734         }
1735 }
1736
1737 /* Remove a MAC address, and update filters */
1738 static void
1739 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1740 {
1741         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1742         struct i40e_vsi *vsi;
1743         struct rte_eth_dev_data *data = dev->data;
1744         struct ether_addr *macaddr;
1745         int ret;
1746         uint32_t i;
1747         uint64_t pool_sel;
1748
1749         macaddr = &(data->mac_addrs[index]);
1750
1751         pool_sel = dev->data->mac_pool_sel[index];
1752
1753         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1754                 if (pool_sel & (1ULL << i)) {
1755                         if (i == 0)
1756                                 vsi = pf->main_vsi;
1757                         else {
1758                                 /* No VMDQ pool enabled or configured */
1759                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1760                                         (i > pf->nb_cfg_vmdq_vsi)) {
1761                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1762                                                         "/configured");
1763                                         return;
1764                                 }
1765                                 vsi = pf->vmdq[i - 1].vsi;
1766                         }
1767                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1768
1769                         if (ret) {
1770                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1771                                 return;
1772                         }
1773                 }
1774         }
1775 }
1776
1777 /* Set perfect match or hash match of MAC and VLAN for a VF */
1778 static int
1779 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1780                  struct rte_eth_mac_filter *filter,
1781                  bool add)
1782 {
1783         struct i40e_hw *hw;
1784         struct i40e_mac_filter_info mac_filter;
1785         struct ether_addr old_mac;
1786         struct ether_addr *new_mac;
1787         struct i40e_pf_vf *vf = NULL;
1788         uint16_t vf_id;
1789         int ret;
1790
1791         if (pf == NULL) {
1792                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1793                 return -EINVAL;
1794         }
1795         hw = I40E_PF_TO_HW(pf);
1796
1797         if (filter == NULL) {
1798                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1799                 return -EINVAL;
1800         }
1801
1802         new_mac = &filter->mac_addr;
1803
1804         if (is_zero_ether_addr(new_mac)) {
1805                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1806                 return -EINVAL;
1807         }
1808
1809         vf_id = filter->dst_id;
1810
1811         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1812                 PMD_DRV_LOG(ERR, "Invalid argument.");
1813                 return -EINVAL;
1814         }
1815         vf = &pf->vfs[vf_id];
1816
1817         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1818                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1819                 return -EINVAL;
1820         }
1821
1822         if (add) {
1823                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1824                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1825                                 ETHER_ADDR_LEN);
1826                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1827                                  ETHER_ADDR_LEN);
1828
1829                 mac_filter.filter_type = filter->filter_type;
1830                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1831                 if (ret != I40E_SUCCESS) {
1832                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1833                         return -1;
1834                 }
1835                 ether_addr_copy(new_mac, &pf->dev_addr);
1836         } else {
1837                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1838                                 ETHER_ADDR_LEN);
1839                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1840                 if (ret != I40E_SUCCESS) {
1841                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1842                         return -1;
1843                 }
1844
1845                 /* Clear device address as it has been removed */
1846                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1847                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1848         }
1849
1850         return 0;
1851 }
1852
1853 /* MAC filter handle */
1854 static int
1855 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1856                 void *arg)
1857 {
1858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1859         struct rte_eth_mac_filter *filter;
1860         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1861         int ret = I40E_NOT_SUPPORTED;
1862
1863         filter = (struct rte_eth_mac_filter *)(arg);
1864
1865         switch (filter_op) {
1866         case RTE_ETH_FILTER_NOP:
1867                 ret = I40E_SUCCESS;
1868                 break;
1869         case RTE_ETH_FILTER_ADD:
1870                 i40e_pf_disable_irq0(hw);
1871                 if (filter->is_vf)
1872                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1873                 i40e_pf_enable_irq0(hw);
1874                 break;
1875         case RTE_ETH_FILTER_DELETE:
1876                 i40e_pf_disable_irq0(hw);
1877                 if (filter->is_vf)
1878                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1879                 i40e_pf_enable_irq0(hw);
1880                 break;
1881         default:
1882                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1883                 ret = I40E_ERR_PARAM;
1884                 break;
1885         }
1886
1887         return ret;
1888 }
1889
1890 static int
1891 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1892                          struct rte_eth_rss_reta_entry64 *reta_conf,
1893                          uint16_t reta_size)
1894 {
1895         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897         uint32_t lut, l;
1898         uint16_t i, j, lut_size = pf->hash_lut_size;
1899         uint16_t idx, shift;
1900         uint8_t mask;
1901
1902         if (reta_size != lut_size ||
1903                 reta_size > ETH_RSS_RETA_SIZE_512) {
1904                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1905                         "(%d) doesn't match the number hardware can supported "
1906                                         "(%d)\n", reta_size, lut_size);
1907                 return -EINVAL;
1908         }
1909
1910         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1911                 idx = i / RTE_RETA_GROUP_SIZE;
1912                 shift = i % RTE_RETA_GROUP_SIZE;
1913                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1914                                                 I40E_4_BIT_MASK);
1915                 if (!mask)
1916                         continue;
1917                 if (mask == I40E_4_BIT_MASK)
1918                         l = 0;
1919                 else
1920                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1921                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1922                         if (mask & (0x1 << j))
1923                                 lut |= reta_conf[idx].reta[shift + j] <<
1924                                                         (CHAR_BIT * j);
1925                         else
1926                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1927                 }
1928                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1929         }
1930
1931         return 0;
1932 }
1933
1934 static int
1935 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1936                         struct rte_eth_rss_reta_entry64 *reta_conf,
1937                         uint16_t reta_size)
1938 {
1939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         uint32_t lut;
1942         uint16_t i, j, lut_size = pf->hash_lut_size;
1943         uint16_t idx, shift;
1944         uint8_t mask;
1945
1946         if (reta_size != lut_size ||
1947                 reta_size > ETH_RSS_RETA_SIZE_512) {
1948                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1949                         "(%d) doesn't match the number hardware can supported "
1950                                         "(%d)\n", reta_size, lut_size);
1951                 return -EINVAL;
1952         }
1953
1954         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1955                 idx = i / RTE_RETA_GROUP_SIZE;
1956                 shift = i % RTE_RETA_GROUP_SIZE;
1957                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1958                                                 I40E_4_BIT_MASK);
1959                 if (!mask)
1960                         continue;
1961
1962                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1963                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1964                         if (mask & (0x1 << j))
1965                                 reta_conf[idx].reta[shift + j] = ((lut >>
1966                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1967                 }
1968         }
1969
1970         return 0;
1971 }
1972
1973 /**
1974  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1975  * @hw:   pointer to the HW structure
1976  * @mem:  pointer to mem struct to fill out
1977  * @size: size of memory requested
1978  * @alignment: what to align the allocation to
1979  **/
1980 enum i40e_status_code
1981 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1982                         struct i40e_dma_mem *mem,
1983                         u64 size,
1984                         u32 alignment)
1985 {
1986         static uint64_t id = 0;
1987         const struct rte_memzone *mz = NULL;
1988         char z_name[RTE_MEMZONE_NAMESIZE];
1989
1990         if (!mem)
1991                 return I40E_ERR_PARAM;
1992
1993         id++;
1994         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1995 #ifdef RTE_LIBRTE_XEN_DOM0
1996         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1997                                                         RTE_PGSIZE_2M);
1998 #else
1999         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2000 #endif
2001         if (!mz)
2002                 return I40E_ERR_NO_MEMORY;
2003
2004         mem->id = id;
2005         mem->size = size;
2006         mem->va = mz->addr;
2007 #ifdef RTE_LIBRTE_XEN_DOM0
2008         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2009 #else
2010         mem->pa = mz->phys_addr;
2011 #endif
2012
2013         return I40E_SUCCESS;
2014 }
2015
2016 /**
2017  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2018  * @hw:   pointer to the HW structure
2019  * @mem:  ptr to mem struct to free
2020  **/
2021 enum i40e_status_code
2022 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2023                     struct i40e_dma_mem *mem)
2024 {
2025         if (!mem || !mem->va)
2026                 return I40E_ERR_PARAM;
2027
2028         mem->va = NULL;
2029         mem->pa = (u64)0;
2030
2031         return I40E_SUCCESS;
2032 }
2033
2034 /**
2035  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2036  * @hw:   pointer to the HW structure
2037  * @mem:  pointer to mem struct to fill out
2038  * @size: size of memory requested
2039  **/
2040 enum i40e_status_code
2041 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2042                          struct i40e_virt_mem *mem,
2043                          u32 size)
2044 {
2045         if (!mem)
2046                 return I40E_ERR_PARAM;
2047
2048         mem->size = size;
2049         mem->va = rte_zmalloc("i40e", size, 0);
2050
2051         if (mem->va)
2052                 return I40E_SUCCESS;
2053         else
2054                 return I40E_ERR_NO_MEMORY;
2055 }
2056
2057 /**
2058  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2059  * @hw:   pointer to the HW structure
2060  * @mem:  pointer to mem struct to free
2061  **/
2062 enum i40e_status_code
2063 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2064                      struct i40e_virt_mem *mem)
2065 {
2066         if (!mem)
2067                 return I40E_ERR_PARAM;
2068
2069         rte_free(mem->va);
2070         mem->va = NULL;
2071
2072         return I40E_SUCCESS;
2073 }
2074
2075 void
2076 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2077 {
2078         rte_spinlock_init(&sp->spinlock);
2079 }
2080
2081 void
2082 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2083 {
2084         rte_spinlock_lock(&sp->spinlock);
2085 }
2086
2087 void
2088 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2089 {
2090         rte_spinlock_unlock(&sp->spinlock);
2091 }
2092
2093 void
2094 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2095 {
2096         return;
2097 }
2098
2099 /**
2100  * Get the hardware capabilities, which will be parsed
2101  * and saved into struct i40e_hw.
2102  */
2103 static int
2104 i40e_get_cap(struct i40e_hw *hw)
2105 {
2106         struct i40e_aqc_list_capabilities_element_resp *buf;
2107         uint16_t len, size = 0;
2108         int ret;
2109
2110         /* Calculate a huge enough buff for saving response data temporarily */
2111         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2112                                                 I40E_MAX_CAP_ELE_NUM;
2113         buf = rte_zmalloc("i40e", len, 0);
2114         if (!buf) {
2115                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2116                 return I40E_ERR_NO_MEMORY;
2117         }
2118
2119         /* Get, parse the capabilities and save it to hw */
2120         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2121                         i40e_aqc_opc_list_func_capabilities, NULL);
2122         if (ret != I40E_SUCCESS)
2123                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2124
2125         /* Free the temporary buffer after being used */
2126         rte_free(buf);
2127
2128         return ret;
2129 }
2130
2131 static int
2132 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2133 {
2134         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2135         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2136         uint16_t sum_queues = 0, sum_vsis, left_queues;
2137
2138         /* First check if FW support SRIOV */
2139         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2140                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2141                 return -EINVAL;
2142         }
2143
2144         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2145         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2146         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2147         /* Allocate queues for pf */
2148         if (hw->func_caps.rss) {
2149                 pf->flags |= I40E_FLAG_RSS;
2150                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2151                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2152                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2153         } else
2154                 pf->lan_nb_qps = 1;
2155         sum_queues = pf->lan_nb_qps;
2156         /* Default VSI is not counted in */
2157         sum_vsis = 0;
2158         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2159
2160         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2161                 pf->flags |= I40E_FLAG_SRIOV;
2162                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2163                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2164                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2165                                      "max supported %u.",
2166                                      dev->pci_dev->max_vfs,
2167                                      hw->func_caps.num_vfs);
2168                         return -EINVAL;
2169                 }
2170                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2171                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2172                                      "max support %u queues.",
2173                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2174                         return -EINVAL;
2175                 }
2176                 pf->vf_num = dev->pci_dev->max_vfs;
2177                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2178                 sum_vsis   += pf->vf_num;
2179                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2180                              pf->vf_num, pf->vf_nb_qps);
2181         } else
2182                 pf->vf_num = 0;
2183
2184         if (hw->func_caps.vmdq) {
2185                 pf->flags |= I40E_FLAG_VMDQ;
2186                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2187                 pf->max_nb_vmdq_vsi = 1;
2188                 /*
2189                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2190                  * later.
2191                  */
2192                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2193                 sum_vsis += pf->max_nb_vmdq_vsi;
2194         } else {
2195                 pf->vmdq_nb_qps = 0;
2196                 pf->max_nb_vmdq_vsi = 0;
2197         }
2198         pf->nb_cfg_vmdq_vsi = 0;
2199
2200         if (hw->func_caps.fd) {
2201                 pf->flags |= I40E_FLAG_FDIR;
2202                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2203                 /**
2204                  * Each flow director consumes one VSI and one queue,
2205                  * but can't calculate out predictably here.
2206                  */
2207         }
2208
2209         if (sum_vsis > pf->max_num_vsi ||
2210                 sum_queues > hw->func_caps.num_rx_qp) {
2211                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2212                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2213                              pf->max_num_vsi, sum_vsis);
2214                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2215                              hw->func_caps.num_rx_qp, sum_queues);
2216                 return -EINVAL;
2217         }
2218
2219         /* Adjust VMDQ setting to support as many VMs as possible */
2220         if (pf->flags & I40E_FLAG_VMDQ) {
2221                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2222
2223                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2224                                         pf->max_num_vsi - sum_vsis);
2225
2226                 /* Limit the max VMDQ number that rte_ether that can support  */
2227                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2228                                         ETH_64_POOLS - 1);
2229
2230                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2231                                 pf->max_nb_vmdq_vsi);
2232                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2233         }
2234
2235         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2236          * cause */
2237         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2238                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2239                              sum_vsis, hw->func_caps.num_msix_vectors);
2240                 return -EINVAL;
2241         }
2242         return I40E_SUCCESS;
2243 }
2244
2245 static int
2246 i40e_pf_get_switch_config(struct i40e_pf *pf)
2247 {
2248         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2249         struct i40e_aqc_get_switch_config_resp *switch_config;
2250         struct i40e_aqc_switch_config_element_resp *element;
2251         uint16_t start_seid = 0, num_reported;
2252         int ret;
2253
2254         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2255                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2256         if (!switch_config) {
2257                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2258                 return -ENOMEM;
2259         }
2260
2261         /* Get the switch configurations */
2262         ret = i40e_aq_get_switch_config(hw, switch_config,
2263                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2264         if (ret != I40E_SUCCESS) {
2265                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2266                 goto fail;
2267         }
2268         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2269         if (num_reported != 1) { /* The number should be 1 */
2270                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2271                 goto fail;
2272         }
2273
2274         /* Parse the switch configuration elements */
2275         element = &(switch_config->element[0]);
2276         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2277                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2278                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2279         } else
2280                 PMD_DRV_LOG(INFO, "Unknown element type");
2281
2282 fail:
2283         rte_free(switch_config);
2284
2285         return ret;
2286 }
2287
2288 static int
2289 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2290                         uint32_t num)
2291 {
2292         struct pool_entry *entry;
2293
2294         if (pool == NULL || num == 0)
2295                 return -EINVAL;
2296
2297         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2298         if (entry == NULL) {
2299                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2300                 return -ENOMEM;
2301         }
2302
2303         /* queue heap initialize */
2304         pool->num_free = num;
2305         pool->num_alloc = 0;
2306         pool->base = base;
2307         LIST_INIT(&pool->alloc_list);
2308         LIST_INIT(&pool->free_list);
2309
2310         /* Initialize element  */
2311         entry->base = 0;
2312         entry->len = num;
2313
2314         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2315         return 0;
2316 }
2317
2318 static void
2319 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2320 {
2321         struct pool_entry *entry;
2322
2323         if (pool == NULL)
2324                 return;
2325
2326         LIST_FOREACH(entry, &pool->alloc_list, next) {
2327                 LIST_REMOVE(entry, next);
2328                 rte_free(entry);
2329         }
2330
2331         LIST_FOREACH(entry, &pool->free_list, next) {
2332                 LIST_REMOVE(entry, next);
2333                 rte_free(entry);
2334         }
2335
2336         pool->num_free = 0;
2337         pool->num_alloc = 0;
2338         pool->base = 0;
2339         LIST_INIT(&pool->alloc_list);
2340         LIST_INIT(&pool->free_list);
2341 }
2342
2343 static int
2344 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2345                        uint32_t base)
2346 {
2347         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2348         uint32_t pool_offset;
2349         int insert;
2350
2351         if (pool == NULL) {
2352                 PMD_DRV_LOG(ERR, "Invalid parameter");
2353                 return -EINVAL;
2354         }
2355
2356         pool_offset = base - pool->base;
2357         /* Lookup in alloc list */
2358         LIST_FOREACH(entry, &pool->alloc_list, next) {
2359                 if (entry->base == pool_offset) {
2360                         valid_entry = entry;
2361                         LIST_REMOVE(entry, next);
2362                         break;
2363                 }
2364         }
2365
2366         /* Not find, return */
2367         if (valid_entry == NULL) {
2368                 PMD_DRV_LOG(ERR, "Failed to find entry");
2369                 return -EINVAL;
2370         }
2371
2372         /**
2373          * Found it, move it to free list  and try to merge.
2374          * In order to make merge easier, always sort it by qbase.
2375          * Find adjacent prev and last entries.
2376          */
2377         prev = next = NULL;
2378         LIST_FOREACH(entry, &pool->free_list, next) {
2379                 if (entry->base > valid_entry->base) {
2380                         next = entry;
2381                         break;
2382                 }
2383                 prev = entry;
2384         }
2385
2386         insert = 0;
2387         /* Try to merge with next one*/
2388         if (next != NULL) {
2389                 /* Merge with next one */
2390                 if (valid_entry->base + valid_entry->len == next->base) {
2391                         next->base = valid_entry->base;
2392                         next->len += valid_entry->len;
2393                         rte_free(valid_entry);
2394                         valid_entry = next;
2395                         insert = 1;
2396                 }
2397         }
2398
2399         if (prev != NULL) {
2400                 /* Merge with previous one */
2401                 if (prev->base + prev->len == valid_entry->base) {
2402                         prev->len += valid_entry->len;
2403                         /* If it merge with next one, remove next node */
2404                         if (insert == 1) {
2405                                 LIST_REMOVE(valid_entry, next);
2406                                 rte_free(valid_entry);
2407                         } else {
2408                                 rte_free(valid_entry);
2409                                 insert = 1;
2410                         }
2411                 }
2412         }
2413
2414         /* Not find any entry to merge, insert */
2415         if (insert == 0) {
2416                 if (prev != NULL)
2417                         LIST_INSERT_AFTER(prev, valid_entry, next);
2418                 else if (next != NULL)
2419                         LIST_INSERT_BEFORE(next, valid_entry, next);
2420                 else /* It's empty list, insert to head */
2421                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2422         }
2423
2424         pool->num_free += valid_entry->len;
2425         pool->num_alloc -= valid_entry->len;
2426
2427         return 0;
2428 }
2429
2430 static int
2431 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2432                        uint16_t num)
2433 {
2434         struct pool_entry *entry, *valid_entry;
2435
2436         if (pool == NULL || num == 0) {
2437                 PMD_DRV_LOG(ERR, "Invalid parameter");
2438                 return -EINVAL;
2439         }
2440
2441         if (pool->num_free < num) {
2442                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2443                             num, pool->num_free);
2444                 return -ENOMEM;
2445         }
2446
2447         valid_entry = NULL;
2448         /* Lookup  in free list and find most fit one */
2449         LIST_FOREACH(entry, &pool->free_list, next) {
2450                 if (entry->len >= num) {
2451                         /* Find best one */
2452                         if (entry->len == num) {
2453                                 valid_entry = entry;
2454                                 break;
2455                         }
2456                         if (valid_entry == NULL || valid_entry->len > entry->len)
2457                                 valid_entry = entry;
2458                 }
2459         }
2460
2461         /* Not find one to satisfy the request, return */
2462         if (valid_entry == NULL) {
2463                 PMD_DRV_LOG(ERR, "No valid entry found");
2464                 return -ENOMEM;
2465         }
2466         /**
2467          * The entry have equal queue number as requested,
2468          * remove it from alloc_list.
2469          */
2470         if (valid_entry->len == num) {
2471                 LIST_REMOVE(valid_entry, next);
2472         } else {
2473                 /**
2474                  * The entry have more numbers than requested,
2475                  * create a new entry for alloc_list and minus its
2476                  * queue base and number in free_list.
2477                  */
2478                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2479                 if (entry == NULL) {
2480                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2481                                     "resource pool");
2482                         return -ENOMEM;
2483                 }
2484                 entry->base = valid_entry->base;
2485                 entry->len = num;
2486                 valid_entry->base += num;
2487                 valid_entry->len -= num;
2488                 valid_entry = entry;
2489         }
2490
2491         /* Insert it into alloc list, not sorted */
2492         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2493
2494         pool->num_free -= valid_entry->len;
2495         pool->num_alloc += valid_entry->len;
2496
2497         return (valid_entry->base + pool->base);
2498 }
2499
2500 /**
2501  * bitmap_is_subset - Check whether src2 is subset of src1
2502  **/
2503 static inline int
2504 bitmap_is_subset(uint8_t src1, uint8_t src2)
2505 {
2506         return !((src1 ^ src2) & src2);
2507 }
2508
2509 static int
2510 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2511 {
2512         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2513
2514         /* If DCB is not supported, only default TC is supported */
2515         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2516                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2517                 return -EINVAL;
2518         }
2519
2520         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2521                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2522                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2523                             enabled_tcmap);
2524                 return -EINVAL;
2525         }
2526         return I40E_SUCCESS;
2527 }
2528
2529 int
2530 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2531                                 struct i40e_vsi_vlan_pvid_info *info)
2532 {
2533         struct i40e_hw *hw;
2534         struct i40e_vsi_context ctxt;
2535         uint8_t vlan_flags = 0;
2536         int ret;
2537
2538         if (vsi == NULL || info == NULL) {
2539                 PMD_DRV_LOG(ERR, "invalid parameters");
2540                 return I40E_ERR_PARAM;
2541         }
2542
2543         if (info->on) {
2544                 vsi->info.pvid = info->config.pvid;
2545                 /**
2546                  * If insert pvid is enabled, only tagged pkts are
2547                  * allowed to be sent out.
2548                  */
2549                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2550                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2551         } else {
2552                 vsi->info.pvid = 0;
2553                 if (info->config.reject.tagged == 0)
2554                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2555
2556                 if (info->config.reject.untagged == 0)
2557                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2558         }
2559         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2560                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2561         vsi->info.port_vlan_flags |= vlan_flags;
2562         vsi->info.valid_sections =
2563                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2564         memset(&ctxt, 0, sizeof(ctxt));
2565         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2566         ctxt.seid = vsi->seid;
2567
2568         hw = I40E_VSI_TO_HW(vsi);
2569         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2570         if (ret != I40E_SUCCESS)
2571                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2572
2573         return ret;
2574 }
2575
2576 static int
2577 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2578 {
2579         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2580         int i, ret;
2581         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2582
2583         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2584         if (ret != I40E_SUCCESS)
2585                 return ret;
2586
2587         if (!vsi->seid) {
2588                 PMD_DRV_LOG(ERR, "seid not valid");
2589                 return -EINVAL;
2590         }
2591
2592         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2593         tc_bw_data.tc_valid_bits = enabled_tcmap;
2594         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2595                 tc_bw_data.tc_bw_credits[i] =
2596                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2597
2598         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2599         if (ret != I40E_SUCCESS) {
2600                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2601                 return ret;
2602         }
2603
2604         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2605                                         sizeof(vsi->info.qs_handle));
2606         return I40E_SUCCESS;
2607 }
2608
2609 static int
2610 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2611                                  struct i40e_aqc_vsi_properties_data *info,
2612                                  uint8_t enabled_tcmap)
2613 {
2614         int ret, total_tc = 0, i;
2615         uint16_t qpnum_per_tc, bsf, qp_idx;
2616
2617         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2618         if (ret != I40E_SUCCESS)
2619                 return ret;
2620
2621         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2622                 if (enabled_tcmap & (1 << i))
2623                         total_tc++;
2624         vsi->enabled_tc = enabled_tcmap;
2625
2626         /* Number of queues per enabled TC */
2627         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2628         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2629         bsf = rte_bsf32(qpnum_per_tc);
2630
2631         /* Adjust the queue number to actual queues that can be applied */
2632         vsi->nb_qps = qpnum_per_tc * total_tc;
2633
2634         /**
2635          * Configure TC and queue mapping parameters, for enabled TC,
2636          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2637          * default queue will serve it.
2638          */
2639         qp_idx = 0;
2640         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2641                 if (vsi->enabled_tc & (1 << i)) {
2642                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2643                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2644                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2645                         qp_idx += qpnum_per_tc;
2646                 } else
2647                         info->tc_mapping[i] = 0;
2648         }
2649
2650         /* Associate queue number with VSI */
2651         if (vsi->type == I40E_VSI_SRIOV) {
2652                 info->mapping_flags |=
2653                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2654                 for (i = 0; i < vsi->nb_qps; i++)
2655                         info->queue_mapping[i] =
2656                                 rte_cpu_to_le_16(vsi->base_queue + i);
2657         } else {
2658                 info->mapping_flags |=
2659                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2660                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2661         }
2662         info->valid_sections |=
2663                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2664
2665         return I40E_SUCCESS;
2666 }
2667
2668 static int
2669 i40e_veb_release(struct i40e_veb *veb)
2670 {
2671         struct i40e_vsi *vsi;
2672         struct i40e_hw *hw;
2673
2674         if (veb == NULL || veb->associate_vsi == NULL)
2675                 return -EINVAL;
2676
2677         if (!TAILQ_EMPTY(&veb->head)) {
2678                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2679                 return -EACCES;
2680         }
2681
2682         vsi = veb->associate_vsi;
2683         hw = I40E_VSI_TO_HW(vsi);
2684
2685         vsi->uplink_seid = veb->uplink_seid;
2686         i40e_aq_delete_element(hw, veb->seid, NULL);
2687         rte_free(veb);
2688         vsi->veb = NULL;
2689         return I40E_SUCCESS;
2690 }
2691
2692 /* Setup a veb */
2693 static struct i40e_veb *
2694 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2695 {
2696         struct i40e_veb *veb;
2697         int ret;
2698         struct i40e_hw *hw;
2699
2700         if (NULL == pf || vsi == NULL) {
2701                 PMD_DRV_LOG(ERR, "veb setup failed, "
2702                             "associated VSI shouldn't null");
2703                 return NULL;
2704         }
2705         hw = I40E_PF_TO_HW(pf);
2706
2707         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2708         if (!veb) {
2709                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2710                 goto fail;
2711         }
2712
2713         veb->associate_vsi = vsi;
2714         TAILQ_INIT(&veb->head);
2715         veb->uplink_seid = vsi->uplink_seid;
2716
2717         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2718                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2719
2720         if (ret != I40E_SUCCESS) {
2721                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2722                             hw->aq.asq_last_status);
2723                 goto fail;
2724         }
2725
2726         /* get statistics index */
2727         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2728                                 &veb->stats_idx, NULL, NULL, NULL);
2729         if (ret != I40E_SUCCESS) {
2730                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2731                             hw->aq.asq_last_status);
2732                 goto fail;
2733         }
2734
2735         /* Get VEB bandwidth, to be implemented */
2736         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2737         vsi->uplink_seid = veb->seid;
2738
2739         return veb;
2740 fail:
2741         rte_free(veb);
2742         return NULL;
2743 }
2744
2745 int
2746 i40e_vsi_release(struct i40e_vsi *vsi)
2747 {
2748         struct i40e_pf *pf;
2749         struct i40e_hw *hw;
2750         struct i40e_vsi_list *vsi_list;
2751         int ret;
2752         struct i40e_mac_filter *f;
2753
2754         if (!vsi)
2755                 return I40E_SUCCESS;
2756
2757         pf = I40E_VSI_TO_PF(vsi);
2758         hw = I40E_VSI_TO_HW(vsi);
2759
2760         /* VSI has child to attach, release child first */
2761         if (vsi->veb) {
2762                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2763                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2764                                 return -1;
2765                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2766                 }
2767                 i40e_veb_release(vsi->veb);
2768         }
2769
2770         /* Remove all macvlan filters of the VSI */
2771         i40e_vsi_remove_all_macvlan_filter(vsi);
2772         TAILQ_FOREACH(f, &vsi->mac_list, next)
2773                 rte_free(f);
2774
2775         if (vsi->type != I40E_VSI_MAIN) {
2776                 /* Remove vsi from parent's sibling list */
2777                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2778                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2779                         return I40E_ERR_PARAM;
2780                 }
2781                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2782                                 &vsi->sib_vsi_list, list);
2783
2784                 /* Remove all switch element of the VSI */
2785                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2786                 if (ret != I40E_SUCCESS)
2787                         PMD_DRV_LOG(ERR, "Failed to delete element");
2788         }
2789         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2790
2791         if (vsi->type != I40E_VSI_SRIOV)
2792                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2793         rte_free(vsi);
2794
2795         return I40E_SUCCESS;
2796 }
2797
2798 static int
2799 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2800 {
2801         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2802         struct i40e_aqc_remove_macvlan_element_data def_filter;
2803         struct i40e_mac_filter_info filter;
2804         int ret;
2805
2806         if (vsi->type != I40E_VSI_MAIN)
2807                 return I40E_ERR_CONFIG;
2808         memset(&def_filter, 0, sizeof(def_filter));
2809         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2810                                         ETH_ADDR_LEN);
2811         def_filter.vlan_tag = 0;
2812         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2813                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2814         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2815         if (ret != I40E_SUCCESS) {
2816                 struct i40e_mac_filter *f;
2817                 struct ether_addr *mac;
2818
2819                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2820                             "macvlan filter");
2821                 /* It needs to add the permanent mac into mac list */
2822                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2823                 if (f == NULL) {
2824                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2825                         return I40E_ERR_NO_MEMORY;
2826                 }
2827                 mac = &f->mac_info.mac_addr;
2828                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2829                                 ETH_ADDR_LEN);
2830                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2831                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2832                 vsi->mac_num++;
2833
2834                 return ret;
2835         }
2836         (void)rte_memcpy(&filter.mac_addr,
2837                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2838         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2839         return i40e_vsi_add_mac(vsi, &filter);
2840 }
2841
2842 static int
2843 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2844 {
2845         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2846         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2847         struct i40e_hw *hw = &vsi->adapter->hw;
2848         i40e_status ret;
2849         int i;
2850
2851         memset(&bw_config, 0, sizeof(bw_config));
2852         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2853         if (ret != I40E_SUCCESS) {
2854                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2855                             hw->aq.asq_last_status);
2856                 return ret;
2857         }
2858
2859         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2860         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2861                                         &ets_sla_config, NULL);
2862         if (ret != I40E_SUCCESS) {
2863                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2864                             "configuration %u", hw->aq.asq_last_status);
2865                 return ret;
2866         }
2867
2868         /* Not store the info yet, just print out */
2869         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2870         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2871         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2872                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2873                             ets_sla_config.share_credits[i]);
2874                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2875                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2876                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2877                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2878                             (i * 4));
2879         }
2880
2881         return 0;
2882 }
2883
2884 /* Setup a VSI */
2885 struct i40e_vsi *
2886 i40e_vsi_setup(struct i40e_pf *pf,
2887                enum i40e_vsi_type type,
2888                struct i40e_vsi *uplink_vsi,
2889                uint16_t user_param)
2890 {
2891         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2892         struct i40e_vsi *vsi;
2893         struct i40e_mac_filter_info filter;
2894         int ret;
2895         struct i40e_vsi_context ctxt;
2896         struct ether_addr broadcast =
2897                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2898
2899         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2900                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2901                             "VSI link shouldn't be NULL");
2902                 return NULL;
2903         }
2904
2905         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2906                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2907                             "uplink VSI should be NULL");
2908                 return NULL;
2909         }
2910
2911         /* If uplink vsi didn't setup VEB, create one first */
2912         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2913                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2914
2915                 if (NULL == uplink_vsi->veb) {
2916                         PMD_DRV_LOG(ERR, "VEB setup failed");
2917                         return NULL;
2918                 }
2919         }
2920
2921         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2922         if (!vsi) {
2923                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2924                 return NULL;
2925         }
2926         TAILQ_INIT(&vsi->mac_list);
2927         vsi->type = type;
2928         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2929         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2930         vsi->parent_vsi = uplink_vsi;
2931         vsi->user_param = user_param;
2932         /* Allocate queues */
2933         switch (vsi->type) {
2934         case I40E_VSI_MAIN  :
2935                 vsi->nb_qps = pf->lan_nb_qps;
2936                 break;
2937         case I40E_VSI_SRIOV :
2938                 vsi->nb_qps = pf->vf_nb_qps;
2939                 break;
2940         case I40E_VSI_VMDQ2:
2941                 vsi->nb_qps = pf->vmdq_nb_qps;
2942                 break;
2943         case I40E_VSI_FDIR:
2944                 vsi->nb_qps = pf->fdir_nb_qps;
2945                 break;
2946         default:
2947                 goto fail_mem;
2948         }
2949         /*
2950          * The filter status descriptor is reported in rx queue 0,
2951          * while the tx queue for fdir filter programming has no
2952          * such constraints, can be non-zero queues.
2953          * To simplify it, choose FDIR vsi use queue 0 pair.
2954          * To make sure it will use queue 0 pair, queue allocation
2955          * need be done before this function is called
2956          */
2957         if (type != I40E_VSI_FDIR) {
2958                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2959                         if (ret < 0) {
2960                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2961                                                 vsi->seid, ret);
2962                                 goto fail_mem;
2963                         }
2964                         vsi->base_queue = ret;
2965         } else
2966                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2967
2968         /* VF has MSIX interrupt in VF range, don't allocate here */
2969         if (type != I40E_VSI_SRIOV) {
2970                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2971                 if (ret < 0) {
2972                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2973                         goto fail_queue_alloc;
2974                 }
2975                 vsi->msix_intr = ret;
2976         } else
2977                 vsi->msix_intr = 0;
2978         /* Add VSI */
2979         if (type == I40E_VSI_MAIN) {
2980                 /* For main VSI, no need to add since it's default one */
2981                 vsi->uplink_seid = pf->mac_seid;
2982                 vsi->seid = pf->main_vsi_seid;
2983                 /* Bind queues with specific MSIX interrupt */
2984                 /**
2985                  * Needs 2 interrupt at least, one for misc cause which will
2986                  * enabled from OS side, Another for queues binding the
2987                  * interrupt from device side only.
2988                  */
2989
2990                 /* Get default VSI parameters from hardware */
2991                 memset(&ctxt, 0, sizeof(ctxt));
2992                 ctxt.seid = vsi->seid;
2993                 ctxt.pf_num = hw->pf_id;
2994                 ctxt.uplink_seid = vsi->uplink_seid;
2995                 ctxt.vf_num = 0;
2996                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2997                 if (ret != I40E_SUCCESS) {
2998                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2999                         goto fail_msix_alloc;
3000                 }
3001                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3002                         sizeof(struct i40e_aqc_vsi_properties_data));
3003                 vsi->vsi_id = ctxt.vsi_number;
3004                 vsi->info.valid_sections = 0;
3005
3006                 /* Configure tc, enabled TC0 only */
3007                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3008                         I40E_SUCCESS) {
3009                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3010                         goto fail_msix_alloc;
3011                 }
3012
3013                 /* TC, queue mapping */
3014                 memset(&ctxt, 0, sizeof(ctxt));
3015                 vsi->info.valid_sections |=
3016                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3017                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3018                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3019                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3020                         sizeof(struct i40e_aqc_vsi_properties_data));
3021                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3022                                                 I40E_DEFAULT_TCMAP);
3023                 if (ret != I40E_SUCCESS) {
3024                         PMD_DRV_LOG(ERR, "Failed to configure "
3025                                     "TC queue mapping");
3026                         goto fail_msix_alloc;
3027                 }
3028                 ctxt.seid = vsi->seid;
3029                 ctxt.pf_num = hw->pf_id;
3030                 ctxt.uplink_seid = vsi->uplink_seid;
3031                 ctxt.vf_num = 0;
3032
3033                 /* Update VSI parameters */
3034                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3035                 if (ret != I40E_SUCCESS) {
3036                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3037                         goto fail_msix_alloc;
3038                 }
3039
3040                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3041                                                 sizeof(vsi->info.tc_mapping));
3042                 (void)rte_memcpy(&vsi->info.queue_mapping,
3043                                 &ctxt.info.queue_mapping,
3044                         sizeof(vsi->info.queue_mapping));
3045                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3046                 vsi->info.valid_sections = 0;
3047
3048                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3049                                 ETH_ADDR_LEN);
3050
3051                 /**
3052                  * Updating default filter settings are necessary to prevent
3053                  * reception of tagged packets.
3054                  * Some old firmware configurations load a default macvlan
3055                  * filter which accepts both tagged and untagged packets.
3056                  * The updating is to use a normal filter instead if needed.
3057                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3058                  * The firmware with correct configurations load the default
3059                  * macvlan filter which is expected and cannot be removed.
3060                  */
3061                 i40e_update_default_filter_setting(vsi);
3062         } else if (type == I40E_VSI_SRIOV) {
3063                 memset(&ctxt, 0, sizeof(ctxt));
3064                 /**
3065                  * For other VSI, the uplink_seid equals to uplink VSI's
3066                  * uplink_seid since they share same VEB
3067                  */
3068                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3069                 ctxt.pf_num = hw->pf_id;
3070                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3071                 ctxt.uplink_seid = vsi->uplink_seid;
3072                 ctxt.connection_type = 0x1;
3073                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3074
3075                 /**
3076                  * Do not configure switch ID to enable VEB switch by
3077                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3078                  * if the source mac address of packet sent from VF is not
3079                  * listed in the VEB's mac table, the VEB will switch the
3080                  * packet back to the VF. Need to enable it when HW issue
3081                  * is fixed.
3082                  */
3083
3084                 /* Configure port/vlan */
3085                 ctxt.info.valid_sections |=
3086                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3087                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3088                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3089                                                 I40E_DEFAULT_TCMAP);
3090                 if (ret != I40E_SUCCESS) {
3091                         PMD_DRV_LOG(ERR, "Failed to configure "
3092                                     "TC queue mapping");
3093                         goto fail_msix_alloc;
3094                 }
3095                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3096                 ctxt.info.valid_sections |=
3097                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3098                 /**
3099                  * Since VSI is not created yet, only configure parameter,
3100                  * will add vsi below.
3101                  */
3102         } else if (type == I40E_VSI_VMDQ2) {
3103                 memset(&ctxt, 0, sizeof(ctxt));
3104                 /*
3105                  * For other VSI, the uplink_seid equals to uplink VSI's
3106                  * uplink_seid since they share same VEB
3107                  */
3108                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3109                 ctxt.pf_num = hw->pf_id;
3110                 ctxt.vf_num = 0;
3111                 ctxt.uplink_seid = vsi->uplink_seid;
3112                 ctxt.connection_type = 0x1;
3113                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3114
3115                 ctxt.info.valid_sections |=
3116                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3117                 /* user_param carries flag to enable loop back */
3118                 if (user_param) {
3119                         ctxt.info.switch_id =
3120                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3121                         ctxt.info.switch_id |=
3122                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3123                 }
3124
3125                 /* Configure port/vlan */
3126                 ctxt.info.valid_sections |=
3127                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3128                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3129                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3130                                                 I40E_DEFAULT_TCMAP);
3131                 if (ret != I40E_SUCCESS) {
3132                         PMD_DRV_LOG(ERR, "Failed to configure "
3133                                         "TC queue mapping");
3134                         goto fail_msix_alloc;
3135                 }
3136                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3137                 ctxt.info.valid_sections |=
3138                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3139         } else if (type == I40E_VSI_FDIR) {
3140                 memset(&ctxt, 0, sizeof(ctxt));
3141                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3142                 ctxt.pf_num = hw->pf_id;
3143                 ctxt.vf_num = 0;
3144                 ctxt.uplink_seid = vsi->uplink_seid;
3145                 ctxt.connection_type = 0x1;     /* regular data port */
3146                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3147                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3148                                                 I40E_DEFAULT_TCMAP);
3149                 if (ret != I40E_SUCCESS) {
3150                         PMD_DRV_LOG(ERR, "Failed to configure "
3151                                         "TC queue mapping.");
3152                         goto fail_msix_alloc;
3153                 }
3154                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3155                 ctxt.info.valid_sections |=
3156                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3157         } else {
3158                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3159                 goto fail_msix_alloc;
3160         }
3161
3162         if (vsi->type != I40E_VSI_MAIN) {
3163                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3164                 if (ret != I40E_SUCCESS) {
3165                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3166                                     hw->aq.asq_last_status);
3167                         goto fail_msix_alloc;
3168                 }
3169                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3170                 vsi->info.valid_sections = 0;
3171                 vsi->seid = ctxt.seid;
3172                 vsi->vsi_id = ctxt.vsi_number;
3173                 vsi->sib_vsi_list.vsi = vsi;
3174                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3175                                 &vsi->sib_vsi_list, list);
3176         }
3177
3178         /* MAC/VLAN configuration */
3179         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3180         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3181
3182         ret = i40e_vsi_add_mac(vsi, &filter);
3183         if (ret != I40E_SUCCESS) {
3184                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3185                 goto fail_msix_alloc;
3186         }
3187
3188         /* Get VSI BW information */
3189         i40e_vsi_dump_bw_config(vsi);
3190         return vsi;
3191 fail_msix_alloc:
3192         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3193 fail_queue_alloc:
3194         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3195 fail_mem:
3196         rte_free(vsi);
3197         return NULL;
3198 }
3199
3200 /* Configure vlan stripping on or off */
3201 int
3202 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3203 {
3204         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3205         struct i40e_vsi_context ctxt;
3206         uint8_t vlan_flags;
3207         int ret = I40E_SUCCESS;
3208
3209         /* Check if it has been already on or off */
3210         if (vsi->info.valid_sections &
3211                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3212                 if (on) {
3213                         if ((vsi->info.port_vlan_flags &
3214                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3215                                 return 0; /* already on */
3216                 } else {
3217                         if ((vsi->info.port_vlan_flags &
3218                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3219                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3220                                 return 0; /* already off */
3221                 }
3222         }
3223
3224         if (on)
3225                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3226         else
3227                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3228         vsi->info.valid_sections =
3229                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3230         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3231         vsi->info.port_vlan_flags |= vlan_flags;
3232         ctxt.seid = vsi->seid;
3233         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3234         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3235         if (ret)
3236                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3237                             on ? "enable" : "disable");
3238
3239         return ret;
3240 }
3241
3242 static int
3243 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3244 {
3245         struct rte_eth_dev_data *data = dev->data;
3246         int ret;
3247
3248         /* Apply vlan offload setting */
3249         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3250
3251         /* Apply double-vlan setting, not implemented yet */
3252
3253         /* Apply pvid setting */
3254         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3255                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3256         if (ret)
3257                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3258
3259         return ret;
3260 }
3261
3262 static int
3263 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3264 {
3265         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3266
3267         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3268 }
3269
3270 static int
3271 i40e_update_flow_control(struct i40e_hw *hw)
3272 {
3273 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3274         struct i40e_link_status link_status;
3275         uint32_t rxfc = 0, txfc = 0, reg;
3276         uint8_t an_info;
3277         int ret;
3278
3279         memset(&link_status, 0, sizeof(link_status));
3280         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3281         if (ret != I40E_SUCCESS) {
3282                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3283                 goto write_reg; /* Disable flow control */
3284         }
3285
3286         an_info = hw->phy.link_info.an_info;
3287         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3288                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3289                 ret = I40E_ERR_NOT_READY;
3290                 goto write_reg; /* Disable flow control */
3291         }
3292         /**
3293          * If link auto negotiation is enabled, flow control needs to
3294          * be configured according to it
3295          */
3296         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3297         case I40E_LINK_PAUSE_RXTX:
3298                 rxfc = 1;
3299                 txfc = 1;
3300                 hw->fc.current_mode = I40E_FC_FULL;
3301                 break;
3302         case I40E_AQ_LINK_PAUSE_RX:
3303                 rxfc = 1;
3304                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3305                 break;
3306         case I40E_AQ_LINK_PAUSE_TX:
3307                 txfc = 1;
3308                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3309                 break;
3310         default:
3311                 hw->fc.current_mode = I40E_FC_NONE;
3312                 break;
3313         }
3314
3315 write_reg:
3316         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3317                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3318         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3319         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3320         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3321         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3322
3323         return ret;
3324 }
3325
3326 /* PF setup */
3327 static int
3328 i40e_pf_setup(struct i40e_pf *pf)
3329 {
3330         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3331         struct i40e_filter_control_settings settings;
3332         struct i40e_vsi *vsi;
3333         int ret;
3334
3335         /* Clear all stats counters */
3336         pf->offset_loaded = FALSE;
3337         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3338         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3339
3340         ret = i40e_pf_get_switch_config(pf);
3341         if (ret != I40E_SUCCESS) {
3342                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3343                 return ret;
3344         }
3345         if (pf->flags & I40E_FLAG_FDIR) {
3346                 /* make queue allocated first, let FDIR use queue pair 0*/
3347                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3348                 if (ret != I40E_FDIR_QUEUE_ID) {
3349                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3350                                     " ret =%d", ret);
3351                         pf->flags &= ~I40E_FLAG_FDIR;
3352                 }
3353         }
3354         /*  main VSI setup */
3355         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3356         if (!vsi) {
3357                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3358                 return I40E_ERR_NOT_READY;
3359         }
3360         pf->main_vsi = vsi;
3361
3362         /* Configure filter control */
3363         memset(&settings, 0, sizeof(settings));
3364         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3365                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3366         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3367                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3368         else {
3369                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3370                                                 hw->func_caps.rss_table_size);
3371                 return I40E_ERR_PARAM;
3372         }
3373         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3374                         "size: %u\n", hw->func_caps.rss_table_size);
3375         pf->hash_lut_size = hw->func_caps.rss_table_size;
3376
3377         /* Enable ethtype and macvlan filters */
3378         settings.enable_ethtype = TRUE;
3379         settings.enable_macvlan = TRUE;
3380         ret = i40e_set_filter_control(hw, &settings);
3381         if (ret)
3382                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3383                                                                 ret);
3384
3385         /* Update flow control according to the auto negotiation */
3386         i40e_update_flow_control(hw);
3387
3388         return I40E_SUCCESS;
3389 }
3390
3391 int
3392 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3393 {
3394         uint32_t reg;
3395         uint16_t j;
3396
3397         /**
3398          * Set or clear TX Queue Disable flags,
3399          * which is required by hardware.
3400          */
3401         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3402         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3403
3404         /* Wait until the request is finished */
3405         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3406                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3407                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3408                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3409                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3410                                                         & 0x1))) {
3411                         break;
3412                 }
3413         }
3414         if (on) {
3415                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3416                         return I40E_SUCCESS; /* already on, skip next steps */
3417
3418                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3419                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3420         } else {
3421                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3422                         return I40E_SUCCESS; /* already off, skip next steps */
3423                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3424         }
3425         /* Write the register */
3426         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3427         /* Check the result */
3428         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3429                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3430                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3431                 if (on) {
3432                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3433                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3434                                 break;
3435                 } else {
3436                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3437                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3438                                 break;
3439                 }
3440         }
3441         /* Check if it is timeout */
3442         if (j >= I40E_CHK_Q_ENA_COUNT) {
3443                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3444                             (on ? "enable" : "disable"), q_idx);
3445                 return I40E_ERR_TIMEOUT;
3446         }
3447
3448         return I40E_SUCCESS;
3449 }
3450
3451 /* Swith on or off the tx queues */
3452 static int
3453 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3454 {
3455         struct rte_eth_dev_data *dev_data = pf->dev_data;
3456         struct i40e_tx_queue *txq;
3457         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3458         uint16_t i;
3459         int ret;
3460
3461         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3462                 txq = dev_data->tx_queues[i];
3463                 /* Don't operate the queue if not configured or
3464                  * if starting only per queue */
3465                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3466                         continue;
3467                 if (on)
3468                         ret = i40e_dev_tx_queue_start(dev, i);
3469                 else
3470                         ret = i40e_dev_tx_queue_stop(dev, i);
3471                 if ( ret != I40E_SUCCESS)
3472                         return ret;
3473         }
3474
3475         return I40E_SUCCESS;
3476 }
3477
3478 int
3479 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3480 {
3481         uint32_t reg;
3482         uint16_t j;
3483
3484         /* Wait until the request is finished */
3485         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3486                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3487                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3488                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3489                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3490                         break;
3491         }
3492
3493         if (on) {
3494                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3495                         return I40E_SUCCESS; /* Already on, skip next steps */
3496                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3497         } else {
3498                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3499                         return I40E_SUCCESS; /* Already off, skip next steps */
3500                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3501         }
3502
3503         /* Write the register */
3504         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3505         /* Check the result */
3506         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3507                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3508                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3509                 if (on) {
3510                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3511                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3512                                 break;
3513                 } else {
3514                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3515                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3516                                 break;
3517                 }
3518         }
3519
3520         /* Check if it is timeout */
3521         if (j >= I40E_CHK_Q_ENA_COUNT) {
3522                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3523                             (on ? "enable" : "disable"), q_idx);
3524                 return I40E_ERR_TIMEOUT;
3525         }
3526
3527         return I40E_SUCCESS;
3528 }
3529 /* Switch on or off the rx queues */
3530 static int
3531 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3532 {
3533         struct rte_eth_dev_data *dev_data = pf->dev_data;
3534         struct i40e_rx_queue *rxq;
3535         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3536         uint16_t i;
3537         int ret;
3538
3539         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3540                 rxq = dev_data->rx_queues[i];
3541                 /* Don't operate the queue if not configured or
3542                  * if starting only per queue */
3543                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3544                         continue;
3545                 if (on)
3546                         ret = i40e_dev_rx_queue_start(dev, i);
3547                 else
3548                         ret = i40e_dev_rx_queue_stop(dev, i);
3549                 if (ret != I40E_SUCCESS)
3550                         return ret;
3551         }
3552
3553         return I40E_SUCCESS;
3554 }
3555
3556 /* Switch on or off all the rx/tx queues */
3557 int
3558 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3559 {
3560         int ret;
3561
3562         if (on) {
3563                 /* enable rx queues before enabling tx queues */
3564                 ret = i40e_dev_switch_rx_queues(pf, on);
3565                 if (ret) {
3566                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3567                         return ret;
3568                 }
3569                 ret = i40e_dev_switch_tx_queues(pf, on);
3570         } else {
3571                 /* Stop tx queues before stopping rx queues */
3572                 ret = i40e_dev_switch_tx_queues(pf, on);
3573                 if (ret) {
3574                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3575                         return ret;
3576                 }
3577                 ret = i40e_dev_switch_rx_queues(pf, on);
3578         }
3579
3580         return ret;
3581 }
3582
3583 /* Initialize VSI for TX */
3584 static int
3585 i40e_dev_tx_init(struct i40e_pf *pf)
3586 {
3587         struct rte_eth_dev_data *data = pf->dev_data;
3588         uint16_t i;
3589         uint32_t ret = I40E_SUCCESS;
3590         struct i40e_tx_queue *txq;
3591
3592         for (i = 0; i < data->nb_tx_queues; i++) {
3593                 txq = data->tx_queues[i];
3594                 if (!txq || !txq->q_set)
3595                         continue;
3596                 ret = i40e_tx_queue_init(txq);
3597                 if (ret != I40E_SUCCESS)
3598                         break;
3599         }
3600
3601         return ret;
3602 }
3603
3604 /* Initialize VSI for RX */
3605 static int
3606 i40e_dev_rx_init(struct i40e_pf *pf)
3607 {
3608         struct rte_eth_dev_data *data = pf->dev_data;
3609         int ret = I40E_SUCCESS;
3610         uint16_t i;
3611         struct i40e_rx_queue *rxq;
3612
3613         i40e_pf_config_mq_rx(pf);
3614         for (i = 0; i < data->nb_rx_queues; i++) {
3615                 rxq = data->rx_queues[i];
3616                 if (!rxq || !rxq->q_set)
3617                         continue;
3618
3619                 ret = i40e_rx_queue_init(rxq);
3620                 if (ret != I40E_SUCCESS) {
3621                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3622                                     "initialization");
3623                         break;
3624                 }
3625         }
3626
3627         return ret;
3628 }
3629
3630 static int
3631 i40e_dev_rxtx_init(struct i40e_pf *pf)
3632 {
3633         int err;
3634
3635         err = i40e_dev_tx_init(pf);
3636         if (err) {
3637                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3638                 return err;
3639         }
3640         err = i40e_dev_rx_init(pf);
3641         if (err) {
3642                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3643                 return err;
3644         }
3645
3646         return err;
3647 }
3648
3649 static int
3650 i40e_vmdq_setup(struct rte_eth_dev *dev)
3651 {
3652         struct rte_eth_conf *conf = &dev->data->dev_conf;
3653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3654         int i, err, conf_vsis, j, loop;
3655         struct i40e_vsi *vsi;
3656         struct i40e_vmdq_info *vmdq_info;
3657         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3658         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3659
3660         /*
3661          * Disable interrupt to avoid message from VF. Furthermore, it will
3662          * avoid race condition in VSI creation/destroy.
3663          */
3664         i40e_pf_disable_irq0(hw);
3665
3666         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3667                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3668                 return -ENOTSUP;
3669         }
3670
3671         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3672         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3673                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3674                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3675                         pf->max_nb_vmdq_vsi);
3676                 return -ENOTSUP;
3677         }
3678
3679         if (pf->vmdq != NULL) {
3680                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3681                 return 0;
3682         }
3683
3684         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3685                                 sizeof(*vmdq_info) * conf_vsis, 0);
3686
3687         if (pf->vmdq == NULL) {
3688                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3689                 return -ENOMEM;
3690         }
3691
3692         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3693
3694         /* Create VMDQ VSI */
3695         for (i = 0; i < conf_vsis; i++) {
3696                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3697                                 vmdq_conf->enable_loop_back);
3698                 if (vsi == NULL) {
3699                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3700                         err = -1;
3701                         goto err_vsi_setup;
3702                 }
3703                 vmdq_info = &pf->vmdq[i];
3704                 vmdq_info->pf = pf;
3705                 vmdq_info->vsi = vsi;
3706         }
3707         pf->nb_cfg_vmdq_vsi = conf_vsis;
3708
3709         /* Configure Vlan */
3710         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3711         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3712                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3713                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3714                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3715                                         vmdq_conf->pool_map[i].vlan_id, j);
3716
3717                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3718                                                 vmdq_conf->pool_map[i].vlan_id);
3719                                 if (err) {
3720                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3721                                         err = -1;
3722                                         goto err_vsi_setup;
3723                                 }
3724                         }
3725                 }
3726         }
3727
3728         i40e_pf_enable_irq0(hw);
3729
3730         return 0;
3731
3732 err_vsi_setup:
3733         for (i = 0; i < conf_vsis; i++)
3734                 if (pf->vmdq[i].vsi == NULL)
3735                         break;
3736                 else
3737                         i40e_vsi_release(pf->vmdq[i].vsi);
3738
3739         rte_free(pf->vmdq);
3740         pf->vmdq = NULL;
3741         i40e_pf_enable_irq0(hw);
3742         return err;
3743 }
3744
3745 static void
3746 i40e_stat_update_32(struct i40e_hw *hw,
3747                    uint32_t reg,
3748                    bool offset_loaded,
3749                    uint64_t *offset,
3750                    uint64_t *stat)
3751 {
3752         uint64_t new_data;
3753
3754         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3755         if (!offset_loaded)
3756                 *offset = new_data;
3757
3758         if (new_data >= *offset)
3759                 *stat = (uint64_t)(new_data - *offset);
3760         else
3761                 *stat = (uint64_t)((new_data +
3762                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3763 }
3764
3765 static void
3766 i40e_stat_update_48(struct i40e_hw *hw,
3767                    uint32_t hireg,
3768                    uint32_t loreg,
3769                    bool offset_loaded,
3770                    uint64_t *offset,
3771                    uint64_t *stat)
3772 {
3773         uint64_t new_data;
3774
3775         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3776         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3777                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3778
3779         if (!offset_loaded)
3780                 *offset = new_data;
3781
3782         if (new_data >= *offset)
3783                 *stat = new_data - *offset;
3784         else
3785                 *stat = (uint64_t)((new_data +
3786                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3787
3788         *stat &= I40E_48_BIT_MASK;
3789 }
3790
3791 /* Disable IRQ0 */
3792 void
3793 i40e_pf_disable_irq0(struct i40e_hw *hw)
3794 {
3795         /* Disable all interrupt types */
3796         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3797         I40E_WRITE_FLUSH(hw);
3798 }
3799
3800 /* Enable IRQ0 */
3801 void
3802 i40e_pf_enable_irq0(struct i40e_hw *hw)
3803 {
3804         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3805                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3806                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3807                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3808         I40E_WRITE_FLUSH(hw);
3809 }
3810
3811 static void
3812 i40e_pf_config_irq0(struct i40e_hw *hw)
3813 {
3814         /* read pending request and disable first */
3815         i40e_pf_disable_irq0(hw);
3816         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3817         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3818                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3819
3820         /* Link no queues with irq0 */
3821         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3822                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3823 }
3824
3825 static void
3826 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3827 {
3828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3829         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3830         int i;
3831         uint16_t abs_vf_id;
3832         uint32_t index, offset, val;
3833
3834         if (!pf->vfs)
3835                 return;
3836         /**
3837          * Try to find which VF trigger a reset, use absolute VF id to access
3838          * since the reg is global register.
3839          */
3840         for (i = 0; i < pf->vf_num; i++) {
3841                 abs_vf_id = hw->func_caps.vf_base_id + i;
3842                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3843                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3844                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3845                 /* VFR event occured */
3846                 if (val & (0x1 << offset)) {
3847                         int ret;
3848
3849                         /* Clear the event first */
3850                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3851                                                         (0x1 << offset));
3852                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3853                         /**
3854                          * Only notify a VF reset event occured,
3855                          * don't trigger another SW reset
3856                          */
3857                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3858                         if (ret != I40E_SUCCESS)
3859                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3860                 }
3861         }
3862 }
3863
3864 static void
3865 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3866 {
3867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868         struct i40e_arq_event_info info;
3869         uint16_t pending, opcode;
3870         int ret;
3871
3872         info.buf_len = I40E_AQ_BUF_SZ;
3873         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3874         if (!info.msg_buf) {
3875                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3876                 return;
3877         }
3878
3879         pending = 1;
3880         while (pending) {
3881                 ret = i40e_clean_arq_element(hw, &info, &pending);
3882
3883                 if (ret != I40E_SUCCESS) {
3884                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3885                                     "aq_err: %u", hw->aq.asq_last_status);
3886                         break;
3887                 }
3888                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3889
3890                 switch (opcode) {
3891                 case i40e_aqc_opc_send_msg_to_pf:
3892                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3893                         i40e_pf_host_handle_vf_msg(dev,
3894                                         rte_le_to_cpu_16(info.desc.retval),
3895                                         rte_le_to_cpu_32(info.desc.cookie_high),
3896                                         rte_le_to_cpu_32(info.desc.cookie_low),
3897                                         info.msg_buf,
3898                                         info.msg_len);
3899                         break;
3900                 default:
3901                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3902                                     opcode);
3903                         break;
3904                 }
3905         }
3906         rte_free(info.msg_buf);
3907 }
3908
3909 /*
3910  * Interrupt handler is registered as the alarm callback for handling LSC
3911  * interrupt in a definite of time, in order to wait the NIC into a stable
3912  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3913  * no need for link down interrupt.
3914  */
3915 static void
3916 i40e_dev_interrupt_delayed_handler(void *param)
3917 {
3918         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3920         uint32_t icr0;
3921
3922         /* read interrupt causes again */
3923         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3924
3925 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3926         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3927                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3928         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3929                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3930         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3931                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3932         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3933                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3934         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3935                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3936                                                                 "state\n");
3937         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3938                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3939         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3940                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3941 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3942
3943         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3944                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3945                 i40e_dev_handle_vfr_event(dev);
3946         }
3947         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3948                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3949                 i40e_dev_handle_aq_msg(dev);
3950         }
3951
3952         /* handle the link up interrupt in an alarm callback */
3953         i40e_dev_link_update(dev, 0);
3954         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3955
3956         i40e_pf_enable_irq0(hw);
3957         rte_intr_enable(&(dev->pci_dev->intr_handle));
3958 }
3959
3960 /**
3961  * Interrupt handler triggered by NIC  for handling
3962  * specific interrupt.
3963  *
3964  * @param handle
3965  *  Pointer to interrupt handle.
3966  * @param param
3967  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3968  *
3969  * @return
3970  *  void
3971  */
3972 static void
3973 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3974                            void *param)
3975 {
3976         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978         uint32_t icr0;
3979
3980         /* Disable interrupt */
3981         i40e_pf_disable_irq0(hw);
3982
3983         /* read out interrupt causes */
3984         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3985
3986         /* No interrupt event indicated */
3987         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3988                 PMD_DRV_LOG(INFO, "No interrupt event");
3989                 goto done;
3990         }
3991 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3992         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3993                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3994         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3995                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3996         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3997                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3998         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3999                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4000         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4001                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4002         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4003                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4004         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4005                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4006 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4007
4008         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4009                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4010                 i40e_dev_handle_vfr_event(dev);
4011         }
4012         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4013                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4014                 i40e_dev_handle_aq_msg(dev);
4015         }
4016
4017         /* Link Status Change interrupt */
4018         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4019 #define I40E_US_PER_SECOND 1000000
4020                 struct rte_eth_link link;
4021
4022                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4023                 memset(&link, 0, sizeof(link));
4024                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4025                 i40e_dev_link_update(dev, 0);
4026
4027                 /*
4028                  * For link up interrupt, it needs to wait 1 second to let the
4029                  * hardware be a stable state. Otherwise several consecutive
4030                  * interrupts can be observed.
4031                  * For link down interrupt, no need to wait.
4032                  */
4033                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4034                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4035                         return;
4036                 else
4037                         _rte_eth_dev_callback_process(dev,
4038                                 RTE_ETH_EVENT_INTR_LSC);
4039         }
4040
4041 done:
4042         /* Enable interrupt */
4043         i40e_pf_enable_irq0(hw);
4044         rte_intr_enable(&(dev->pci_dev->intr_handle));
4045 }
4046
4047 static int
4048 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4049                          struct i40e_macvlan_filter *filter,
4050                          int total)
4051 {
4052         int ele_num, ele_buff_size;
4053         int num, actual_num, i;
4054         uint16_t flags;
4055         int ret = I40E_SUCCESS;
4056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4057         struct i40e_aqc_add_macvlan_element_data *req_list;
4058
4059         if (filter == NULL  || total == 0)
4060                 return I40E_ERR_PARAM;
4061         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4062         ele_buff_size = hw->aq.asq_buf_size;
4063
4064         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4065         if (req_list == NULL) {
4066                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4067                 return I40E_ERR_NO_MEMORY;
4068         }
4069
4070         num = 0;
4071         do {
4072                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4073                 memset(req_list, 0, ele_buff_size);
4074
4075                 for (i = 0; i < actual_num; i++) {
4076                         (void)rte_memcpy(req_list[i].mac_addr,
4077                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4078                         req_list[i].vlan_tag =
4079                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4080
4081                         switch (filter[num + i].filter_type) {
4082                         case RTE_MAC_PERFECT_MATCH:
4083                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4084                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4085                                 break;
4086                         case RTE_MACVLAN_PERFECT_MATCH:
4087                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4088                                 break;
4089                         case RTE_MAC_HASH_MATCH:
4090                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4091                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4092                                 break;
4093                         case RTE_MACVLAN_HASH_MATCH:
4094                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4095                                 break;
4096                         default:
4097                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4098                                 ret = I40E_ERR_PARAM;
4099                                 goto DONE;
4100                         }
4101
4102                         req_list[i].queue_number = 0;
4103
4104                         req_list[i].flags = rte_cpu_to_le_16(flags);
4105                 }
4106
4107                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4108                                                 actual_num, NULL);
4109                 if (ret != I40E_SUCCESS) {
4110                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4111                         goto DONE;
4112                 }
4113                 num += actual_num;
4114         } while (num < total);
4115
4116 DONE:
4117         rte_free(req_list);
4118         return ret;
4119 }
4120
4121 static int
4122 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4123                             struct i40e_macvlan_filter *filter,
4124                             int total)
4125 {
4126         int ele_num, ele_buff_size;
4127         int num, actual_num, i;
4128         uint16_t flags;
4129         int ret = I40E_SUCCESS;
4130         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4131         struct i40e_aqc_remove_macvlan_element_data *req_list;
4132
4133         if (filter == NULL  || total == 0)
4134                 return I40E_ERR_PARAM;
4135
4136         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4137         ele_buff_size = hw->aq.asq_buf_size;
4138
4139         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4140         if (req_list == NULL) {
4141                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4142                 return I40E_ERR_NO_MEMORY;
4143         }
4144
4145         num = 0;
4146         do {
4147                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4148                 memset(req_list, 0, ele_buff_size);
4149
4150                 for (i = 0; i < actual_num; i++) {
4151                         (void)rte_memcpy(req_list[i].mac_addr,
4152                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4153                         req_list[i].vlan_tag =
4154                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4155
4156                         switch (filter[num + i].filter_type) {
4157                         case RTE_MAC_PERFECT_MATCH:
4158                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4159                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4160                                 break;
4161                         case RTE_MACVLAN_PERFECT_MATCH:
4162                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4163                                 break;
4164                         case RTE_MAC_HASH_MATCH:
4165                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4166                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4167                                 break;
4168                         case RTE_MACVLAN_HASH_MATCH:
4169                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4170                                 break;
4171                         default:
4172                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4173                                 ret = I40E_ERR_PARAM;
4174                                 goto DONE;
4175                         }
4176                         req_list[i].flags = rte_cpu_to_le_16(flags);
4177                 }
4178
4179                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4180                                                 actual_num, NULL);
4181                 if (ret != I40E_SUCCESS) {
4182                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4183                         goto DONE;
4184                 }
4185                 num += actual_num;
4186         } while (num < total);
4187
4188 DONE:
4189         rte_free(req_list);
4190         return ret;
4191 }
4192
4193 /* Find out specific MAC filter */
4194 static struct i40e_mac_filter *
4195 i40e_find_mac_filter(struct i40e_vsi *vsi,
4196                          struct ether_addr *macaddr)
4197 {
4198         struct i40e_mac_filter *f;
4199
4200         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4201                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4202                         return f;
4203         }
4204
4205         return NULL;
4206 }
4207
4208 static bool
4209 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4210                          uint16_t vlan_id)
4211 {
4212         uint32_t vid_idx, vid_bit;
4213
4214         if (vlan_id > ETH_VLAN_ID_MAX)
4215                 return 0;
4216
4217         vid_idx = I40E_VFTA_IDX(vlan_id);
4218         vid_bit = I40E_VFTA_BIT(vlan_id);
4219
4220         if (vsi->vfta[vid_idx] & vid_bit)
4221                 return 1;
4222         else
4223                 return 0;
4224 }
4225
4226 static void
4227 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4228                          uint16_t vlan_id, bool on)
4229 {
4230         uint32_t vid_idx, vid_bit;
4231
4232         if (vlan_id > ETH_VLAN_ID_MAX)
4233                 return;
4234
4235         vid_idx = I40E_VFTA_IDX(vlan_id);
4236         vid_bit = I40E_VFTA_BIT(vlan_id);
4237
4238         if (on)
4239                 vsi->vfta[vid_idx] |= vid_bit;
4240         else
4241                 vsi->vfta[vid_idx] &= ~vid_bit;
4242 }
4243
4244 /**
4245  * Find all vlan options for specific mac addr,
4246  * return with actual vlan found.
4247  */
4248 static inline int
4249 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4250                            struct i40e_macvlan_filter *mv_f,
4251                            int num, struct ether_addr *addr)
4252 {
4253         int i;
4254         uint32_t j, k;
4255
4256         /**
4257          * Not to use i40e_find_vlan_filter to decrease the loop time,
4258          * although the code looks complex.
4259           */
4260         if (num < vsi->vlan_num)
4261                 return I40E_ERR_PARAM;
4262
4263         i = 0;
4264         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4265                 if (vsi->vfta[j]) {
4266                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4267                                 if (vsi->vfta[j] & (1 << k)) {
4268                                         if (i > num - 1) {
4269                                                 PMD_DRV_LOG(ERR, "vlan number "
4270                                                             "not match");
4271                                                 return I40E_ERR_PARAM;
4272                                         }
4273                                         (void)rte_memcpy(&mv_f[i].macaddr,
4274                                                         addr, ETH_ADDR_LEN);
4275                                         mv_f[i].vlan_id =
4276                                                 j * I40E_UINT32_BIT_SIZE + k;
4277                                         i++;
4278                                 }
4279                         }
4280                 }
4281         }
4282         return I40E_SUCCESS;
4283 }
4284
4285 static inline int
4286 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4287                            struct i40e_macvlan_filter *mv_f,
4288                            int num,
4289                            uint16_t vlan)
4290 {
4291         int i = 0;
4292         struct i40e_mac_filter *f;
4293
4294         if (num < vsi->mac_num)
4295                 return I40E_ERR_PARAM;
4296
4297         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4298                 if (i > num - 1) {
4299                         PMD_DRV_LOG(ERR, "buffer number not match");
4300                         return I40E_ERR_PARAM;
4301                 }
4302                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4303                                 ETH_ADDR_LEN);
4304                 mv_f[i].vlan_id = vlan;
4305                 mv_f[i].filter_type = f->mac_info.filter_type;
4306                 i++;
4307         }
4308
4309         return I40E_SUCCESS;
4310 }
4311
4312 static int
4313 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4314 {
4315         int i, num;
4316         struct i40e_mac_filter *f;
4317         struct i40e_macvlan_filter *mv_f;
4318         int ret = I40E_SUCCESS;
4319
4320         if (vsi == NULL || vsi->mac_num == 0)
4321                 return I40E_ERR_PARAM;
4322
4323         /* Case that no vlan is set */
4324         if (vsi->vlan_num == 0)
4325                 num = vsi->mac_num;
4326         else
4327                 num = vsi->mac_num * vsi->vlan_num;
4328
4329         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4330         if (mv_f == NULL) {
4331                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4332                 return I40E_ERR_NO_MEMORY;
4333         }
4334
4335         i = 0;
4336         if (vsi->vlan_num == 0) {
4337                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4338                         (void)rte_memcpy(&mv_f[i].macaddr,
4339                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4340                         mv_f[i].vlan_id = 0;
4341                         i++;
4342                 }
4343         } else {
4344                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4345                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4346                                         vsi->vlan_num, &f->mac_info.mac_addr);
4347                         if (ret != I40E_SUCCESS)
4348                                 goto DONE;
4349                         i += vsi->vlan_num;
4350                 }
4351         }
4352
4353         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4354 DONE:
4355         rte_free(mv_f);
4356
4357         return ret;
4358 }
4359
4360 int
4361 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4362 {
4363         struct i40e_macvlan_filter *mv_f;
4364         int mac_num;
4365         int ret = I40E_SUCCESS;
4366
4367         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4368                 return I40E_ERR_PARAM;
4369
4370         /* If it's already set, just return */
4371         if (i40e_find_vlan_filter(vsi,vlan))
4372                 return I40E_SUCCESS;
4373
4374         mac_num = vsi->mac_num;
4375
4376         if (mac_num == 0) {
4377                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4378                 return I40E_ERR_PARAM;
4379         }
4380
4381         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4382
4383         if (mv_f == NULL) {
4384                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4385                 return I40E_ERR_NO_MEMORY;
4386         }
4387
4388         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4389
4390         if (ret != I40E_SUCCESS)
4391                 goto DONE;
4392
4393         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4394
4395         if (ret != I40E_SUCCESS)
4396                 goto DONE;
4397
4398         i40e_set_vlan_filter(vsi, vlan, 1);
4399
4400         vsi->vlan_num++;
4401         ret = I40E_SUCCESS;
4402 DONE:
4403         rte_free(mv_f);
4404         return ret;
4405 }
4406
4407 int
4408 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4409 {
4410         struct i40e_macvlan_filter *mv_f;
4411         int mac_num;
4412         int ret = I40E_SUCCESS;
4413
4414         /**
4415          * Vlan 0 is the generic filter for untagged packets
4416          * and can't be removed.
4417          */
4418         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4419                 return I40E_ERR_PARAM;
4420
4421         /* If can't find it, just return */
4422         if (!i40e_find_vlan_filter(vsi, vlan))
4423                 return I40E_ERR_PARAM;
4424
4425         mac_num = vsi->mac_num;
4426
4427         if (mac_num == 0) {
4428                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4429                 return I40E_ERR_PARAM;
4430         }
4431
4432         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4433
4434         if (mv_f == NULL) {
4435                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4436                 return I40E_ERR_NO_MEMORY;
4437         }
4438
4439         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4440
4441         if (ret != I40E_SUCCESS)
4442                 goto DONE;
4443
4444         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4445
4446         if (ret != I40E_SUCCESS)
4447                 goto DONE;
4448
4449         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4450         if (vsi->vlan_num == 1) {
4451                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4452                 if (ret != I40E_SUCCESS)
4453                         goto DONE;
4454
4455                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4456                 if (ret != I40E_SUCCESS)
4457                         goto DONE;
4458         }
4459
4460         i40e_set_vlan_filter(vsi, vlan, 0);
4461
4462         vsi->vlan_num--;
4463         ret = I40E_SUCCESS;
4464 DONE:
4465         rte_free(mv_f);
4466         return ret;
4467 }
4468
4469 int
4470 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4471 {
4472         struct i40e_mac_filter *f;
4473         struct i40e_macvlan_filter *mv_f;
4474         int i, vlan_num = 0;
4475         int ret = I40E_SUCCESS;
4476
4477         /* If it's add and we've config it, return */
4478         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4479         if (f != NULL)
4480                 return I40E_SUCCESS;
4481         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4482                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4483
4484                 /**
4485                  * If vlan_num is 0, that's the first time to add mac,
4486                  * set mask for vlan_id 0.
4487                  */
4488                 if (vsi->vlan_num == 0) {
4489                         i40e_set_vlan_filter(vsi, 0, 1);
4490                         vsi->vlan_num = 1;
4491                 }
4492                 vlan_num = vsi->vlan_num;
4493         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4494                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4495                 vlan_num = 1;
4496
4497         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4498         if (mv_f == NULL) {
4499                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4500                 return I40E_ERR_NO_MEMORY;
4501         }
4502
4503         for (i = 0; i < vlan_num; i++) {
4504                 mv_f[i].filter_type = mac_filter->filter_type;
4505                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4506                                 ETH_ADDR_LEN);
4507         }
4508
4509         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4510                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4511                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4512                                         &mac_filter->mac_addr);
4513                 if (ret != I40E_SUCCESS)
4514                         goto DONE;
4515         }
4516
4517         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4518         if (ret != I40E_SUCCESS)
4519                 goto DONE;
4520
4521         /* Add the mac addr into mac list */
4522         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4523         if (f == NULL) {
4524                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4525                 ret = I40E_ERR_NO_MEMORY;
4526                 goto DONE;
4527         }
4528         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4529                         ETH_ADDR_LEN);
4530         f->mac_info.filter_type = mac_filter->filter_type;
4531         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4532         vsi->mac_num++;
4533
4534         ret = I40E_SUCCESS;
4535 DONE:
4536         rte_free(mv_f);
4537
4538         return ret;
4539 }
4540
4541 int
4542 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4543 {
4544         struct i40e_mac_filter *f;
4545         struct i40e_macvlan_filter *mv_f;
4546         int i, vlan_num;
4547         enum rte_mac_filter_type filter_type;
4548         int ret = I40E_SUCCESS;
4549
4550         /* Can't find it, return an error */
4551         f = i40e_find_mac_filter(vsi, addr);
4552         if (f == NULL)
4553                 return I40E_ERR_PARAM;
4554
4555         vlan_num = vsi->vlan_num;
4556         filter_type = f->mac_info.filter_type;
4557         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4558                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4559                 if (vlan_num == 0) {
4560                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4561                         return I40E_ERR_PARAM;
4562                 }
4563         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4564                         filter_type == RTE_MAC_HASH_MATCH)
4565                 vlan_num = 1;
4566
4567         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4568         if (mv_f == NULL) {
4569                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4570                 return I40E_ERR_NO_MEMORY;
4571         }
4572
4573         for (i = 0; i < vlan_num; i++) {
4574                 mv_f[i].filter_type = filter_type;
4575                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4576                                 ETH_ADDR_LEN);
4577         }
4578         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4579                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4580                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4581                 if (ret != I40E_SUCCESS)
4582                         goto DONE;
4583         }
4584
4585         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4586         if (ret != I40E_SUCCESS)
4587                 goto DONE;
4588
4589         /* Remove the mac addr into mac list */
4590         TAILQ_REMOVE(&vsi->mac_list, f, next);
4591         rte_free(f);
4592         vsi->mac_num--;
4593
4594         ret = I40E_SUCCESS;
4595 DONE:
4596         rte_free(mv_f);
4597         return ret;
4598 }
4599
4600 /* Configure hash enable flags for RSS */
4601 uint64_t
4602 i40e_config_hena(uint64_t flags)
4603 {
4604         uint64_t hena = 0;
4605
4606         if (!flags)
4607                 return hena;
4608
4609         if (flags & ETH_RSS_FRAG_IPV4)
4610                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4611         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4612                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4613         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4614                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4615         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4616                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4617         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4618                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4619         if (flags & ETH_RSS_FRAG_IPV6)
4620                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4621         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4622                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4623         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4624                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4625         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4626                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4627         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4628                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4629         if (flags & ETH_RSS_L2_PAYLOAD)
4630                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4631
4632         return hena;
4633 }
4634
4635 /* Parse the hash enable flags */
4636 uint64_t
4637 i40e_parse_hena(uint64_t flags)
4638 {
4639         uint64_t rss_hf = 0;
4640
4641         if (!flags)
4642                 return rss_hf;
4643         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4644                 rss_hf |= ETH_RSS_FRAG_IPV4;
4645         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4646                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4647         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4648                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4649         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4650                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4651         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4652                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4653         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4654                 rss_hf |= ETH_RSS_FRAG_IPV6;
4655         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4656                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4657         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4658                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4659         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4660                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4661         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4662                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4663         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4664                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4665
4666         return rss_hf;
4667 }
4668
4669 /* Disable RSS */
4670 static void
4671 i40e_pf_disable_rss(struct i40e_pf *pf)
4672 {
4673         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4674         uint64_t hena;
4675
4676         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4677         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4678         hena &= ~I40E_RSS_HENA_ALL;
4679         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4680         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4681         I40E_WRITE_FLUSH(hw);
4682 }
4683
4684 static int
4685 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4686 {
4687         uint32_t *hash_key;
4688         uint8_t hash_key_len;
4689         uint64_t rss_hf;
4690         uint16_t i;
4691         uint64_t hena;
4692
4693         hash_key = (uint32_t *)(rss_conf->rss_key);
4694         hash_key_len = rss_conf->rss_key_len;
4695         if (hash_key != NULL && hash_key_len >=
4696                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4697                 /* Fill in RSS hash key */
4698                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4699                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4700         }
4701
4702         rss_hf = rss_conf->rss_hf;
4703         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4704         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4705         hena &= ~I40E_RSS_HENA_ALL;
4706         hena |= i40e_config_hena(rss_hf);
4707         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4708         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4709         I40E_WRITE_FLUSH(hw);
4710
4711         return 0;
4712 }
4713
4714 static int
4715 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4716                          struct rte_eth_rss_conf *rss_conf)
4717 {
4718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4719         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4720         uint64_t hena;
4721
4722         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4723         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4724         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4725                 if (rss_hf != 0) /* Enable RSS */
4726                         return -EINVAL;
4727                 return 0; /* Nothing to do */
4728         }
4729         /* RSS enabled */
4730         if (rss_hf == 0) /* Disable RSS */
4731                 return -EINVAL;
4732
4733         return i40e_hw_rss_hash_set(hw, rss_conf);
4734 }
4735
4736 static int
4737 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4738                            struct rte_eth_rss_conf *rss_conf)
4739 {
4740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4742         uint64_t hena;
4743         uint16_t i;
4744
4745         if (hash_key != NULL) {
4746                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4747                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4748                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4749         }
4750         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4751         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4752         rss_conf->rss_hf = i40e_parse_hena(hena);
4753
4754         return 0;
4755 }
4756
4757 static int
4758 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4759 {
4760         switch (filter_type) {
4761         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4762                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4763                 break;
4764         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4765                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4766                 break;
4767         case RTE_TUNNEL_FILTER_IMAC_TENID:
4768                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4769                 break;
4770         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4771                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4772                 break;
4773         case ETH_TUNNEL_FILTER_IMAC:
4774                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4775                 break;
4776         default:
4777                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4778                 return -EINVAL;
4779         }
4780
4781         return 0;
4782 }
4783
4784 static int
4785 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4786                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4787                         uint8_t add)
4788 {
4789         uint16_t ip_type;
4790         uint8_t tun_type = 0;
4791         int val, ret = 0;
4792         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4793         struct i40e_vsi *vsi = pf->main_vsi;
4794         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4795         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4796
4797         cld_filter = rte_zmalloc("tunnel_filter",
4798                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4799                 0);
4800
4801         if (NULL == cld_filter) {
4802                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4803                 return -EINVAL;
4804         }
4805         pfilter = cld_filter;
4806
4807         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4808                         sizeof(struct ether_addr));
4809         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4810                         sizeof(struct ether_addr));
4811
4812         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4813         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4814                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4815                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4816                                 &tunnel_filter->ip_addr,
4817                                 sizeof(pfilter->ipaddr.v4.data));
4818         } else {
4819                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4820                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4821                                 &tunnel_filter->ip_addr,
4822                                 sizeof(pfilter->ipaddr.v6.data));
4823         }
4824
4825         /* check tunneled type */
4826         switch (tunnel_filter->tunnel_type) {
4827         case RTE_TUNNEL_TYPE_VXLAN:
4828                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4829                 break;
4830         case RTE_TUNNEL_TYPE_NVGRE:
4831                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4832                 break;
4833         default:
4834                 /* Other tunnel types is not supported. */
4835                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4836                 rte_free(cld_filter);
4837                 return -EINVAL;
4838         }
4839
4840         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4841                                                 &pfilter->flags);
4842         if (val < 0) {
4843                 rte_free(cld_filter);
4844                 return -EINVAL;
4845         }
4846
4847         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4848                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4849         pfilter->tenant_id = tunnel_filter->tenant_id;
4850         pfilter->queue_number = tunnel_filter->queue_id;
4851
4852         if (add)
4853                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4854         else
4855                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4856                                                 cld_filter, 1);
4857
4858         rte_free(cld_filter);
4859         return ret;
4860 }
4861
4862 static int
4863 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4864 {
4865         uint8_t i;
4866
4867         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4868                 if (pf->vxlan_ports[i] == port)
4869                         return i;
4870         }
4871
4872         return -1;
4873 }
4874
4875 static int
4876 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4877 {
4878         int  idx, ret;
4879         uint8_t filter_idx;
4880         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4881
4882         idx = i40e_get_vxlan_port_idx(pf, port);
4883
4884         /* Check if port already exists */
4885         if (idx >= 0) {
4886                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4887                 return -EINVAL;
4888         }
4889
4890         /* Now check if there is space to add the new port */
4891         idx = i40e_get_vxlan_port_idx(pf, 0);
4892         if (idx < 0) {
4893                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4894                         "not adding port %d", port);
4895                 return -ENOSPC;
4896         }
4897
4898         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4899                                         &filter_idx, NULL);
4900         if (ret < 0) {
4901                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4902                 return -1;
4903         }
4904
4905         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4906                          port,  filter_idx);
4907
4908         /* New port: add it and mark its index in the bitmap */
4909         pf->vxlan_ports[idx] = port;
4910         pf->vxlan_bitmap |= (1 << idx);
4911
4912         if (!(pf->flags & I40E_FLAG_VXLAN))
4913                 pf->flags |= I40E_FLAG_VXLAN;
4914
4915         return 0;
4916 }
4917
4918 static int
4919 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4920 {
4921         int idx;
4922         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4923
4924         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4925                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4926                 return -EINVAL;
4927         }
4928
4929         idx = i40e_get_vxlan_port_idx(pf, port);
4930
4931         if (idx < 0) {
4932                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4933                 return -EINVAL;
4934         }
4935
4936         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4937                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4938                 return -1;
4939         }
4940
4941         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4942                         port, idx);
4943
4944         pf->vxlan_ports[idx] = 0;
4945         pf->vxlan_bitmap &= ~(1 << idx);
4946
4947         if (!pf->vxlan_bitmap)
4948                 pf->flags &= ~I40E_FLAG_VXLAN;
4949
4950         return 0;
4951 }
4952
4953 /* Add UDP tunneling port */
4954 static int
4955 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4956                         struct rte_eth_udp_tunnel *udp_tunnel)
4957 {
4958         int ret = 0;
4959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4960
4961         if (udp_tunnel == NULL)
4962                 return -EINVAL;
4963
4964         switch (udp_tunnel->prot_type) {
4965         case RTE_TUNNEL_TYPE_VXLAN:
4966                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4967                 break;
4968
4969         case RTE_TUNNEL_TYPE_GENEVE:
4970         case RTE_TUNNEL_TYPE_TEREDO:
4971                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4972                 ret = -1;
4973                 break;
4974
4975         default:
4976                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4977                 ret = -1;
4978                 break;
4979         }
4980
4981         return ret;
4982 }
4983
4984 /* Remove UDP tunneling port */
4985 static int
4986 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4987                         struct rte_eth_udp_tunnel *udp_tunnel)
4988 {
4989         int ret = 0;
4990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4991
4992         if (udp_tunnel == NULL)
4993                 return -EINVAL;
4994
4995         switch (udp_tunnel->prot_type) {
4996         case RTE_TUNNEL_TYPE_VXLAN:
4997                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4998                 break;
4999         case RTE_TUNNEL_TYPE_GENEVE:
5000         case RTE_TUNNEL_TYPE_TEREDO:
5001                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5002                 ret = -1;
5003                 break;
5004         default:
5005                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5006                 ret = -1;
5007                 break;
5008         }
5009
5010         return ret;
5011 }
5012
5013 /* Calculate the maximum number of contiguous PF queues that are configured */
5014 static int
5015 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5016 {
5017         struct rte_eth_dev_data *data = pf->dev_data;
5018         int i, num;
5019         struct i40e_rx_queue *rxq;
5020
5021         num = 0;
5022         for (i = 0; i < pf->lan_nb_qps; i++) {
5023                 rxq = data->rx_queues[i];
5024                 if (rxq && rxq->q_set)
5025                         num++;
5026                 else
5027                         break;
5028         }
5029
5030         return num;
5031 }
5032
5033 /* Configure RSS */
5034 static int
5035 i40e_pf_config_rss(struct i40e_pf *pf)
5036 {
5037         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5038         struct rte_eth_rss_conf rss_conf;
5039         uint32_t i, lut = 0;
5040         uint16_t j, num;
5041
5042         /*
5043          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5044          * It's necessary to calulate the actual PF queues that are configured.
5045          */
5046         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5047                 num = i40e_pf_calc_configured_queues_num(pf);
5048                 num = i40e_align_floor(num);
5049         } else
5050                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5051
5052         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5053                         num);
5054
5055         if (num == 0) {
5056                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5057                 return -ENOTSUP;
5058         }
5059
5060         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5061                 if (j == num)
5062                         j = 0;
5063                 lut = (lut << 8) | (j & ((0x1 <<
5064                         hw->func_caps.rss_table_entry_width) - 1));
5065                 if ((i & 3) == 3)
5066                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5067         }
5068
5069         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5070         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5071                 i40e_pf_disable_rss(pf);
5072                 return 0;
5073         }
5074         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5075                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5076                 /* Random default keys */
5077                 static uint32_t rss_key_default[] = {0x6b793944,
5078                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5079                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5080                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5081
5082                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5083                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5084                                                         sizeof(uint32_t);
5085         }
5086
5087         return i40e_hw_rss_hash_set(hw, &rss_conf);
5088 }
5089
5090 static int
5091 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5092                         struct rte_eth_tunnel_filter_conf *filter)
5093 {
5094         if (pf == NULL || filter == NULL) {
5095                 PMD_DRV_LOG(ERR, "Invalid parameter");
5096                 return -EINVAL;
5097         }
5098
5099         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5100                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5101                 return -EINVAL;
5102         }
5103
5104         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5105                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5106                 return -EINVAL;
5107         }
5108
5109         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5110                 (is_zero_ether_addr(filter->outer_mac))) {
5111                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5112                 return -EINVAL;
5113         }
5114
5115         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5116                 (is_zero_ether_addr(filter->inner_mac))) {
5117                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5118                 return -EINVAL;
5119         }
5120
5121         return 0;
5122 }
5123
5124 static int
5125 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5126                         void *arg)
5127 {
5128         struct rte_eth_tunnel_filter_conf *filter;
5129         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5130         int ret = I40E_SUCCESS;
5131
5132         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5133
5134         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5135                 return I40E_ERR_PARAM;
5136
5137         switch (filter_op) {
5138         case RTE_ETH_FILTER_NOP:
5139                 if (!(pf->flags & I40E_FLAG_VXLAN))
5140                         ret = I40E_NOT_SUPPORTED;
5141         case RTE_ETH_FILTER_ADD:
5142                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5143                 break;
5144         case RTE_ETH_FILTER_DELETE:
5145                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5146                 break;
5147         default:
5148                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5149                 ret = I40E_ERR_PARAM;
5150                 break;
5151         }
5152
5153         return ret;
5154 }
5155
5156 static int
5157 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5158 {
5159         int ret = 0;
5160         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5161
5162         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5163                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5164                 return -ENOTSUP;
5165         }
5166
5167         /* RSS setup */
5168         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5169                 ret = i40e_pf_config_rss(pf);
5170         else
5171                 i40e_pf_disable_rss(pf);
5172
5173         return ret;
5174 }
5175
5176 /* Get the symmetric hash enable configurations per port */
5177 static void
5178 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5179 {
5180         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5181
5182         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5183 }
5184
5185 /* Set the symmetric hash enable configurations per port */
5186 static void
5187 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5188 {
5189         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5190
5191         if (enable > 0) {
5192                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5193                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5194                                                         "been enabled");
5195                         return;
5196                 }
5197                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5198         } else {
5199                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5200                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5201                                                         "been disabled");
5202                         return;
5203                 }
5204                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5205         }
5206         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5207         I40E_WRITE_FLUSH(hw);
5208 }
5209
5210 /*
5211  * Get global configurations of hash function type and symmetric hash enable
5212  * per flow type (pctype). Note that global configuration means it affects all
5213  * the ports on the same NIC.
5214  */
5215 static int
5216 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5217                                    struct rte_eth_hash_global_conf *g_cfg)
5218 {
5219         uint32_t reg, mask = I40E_FLOW_TYPES;
5220         uint16_t i;
5221         enum i40e_filter_pctype pctype;
5222
5223         memset(g_cfg, 0, sizeof(*g_cfg));
5224         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5225         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5226                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5227         else
5228                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5229         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5230                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5231
5232         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5233                 if (!(mask & (1UL << i)))
5234                         continue;
5235                 mask &= ~(1UL << i);
5236                 /* Bit set indicats the coresponding flow type is supported */
5237                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5238                 pctype = i40e_flowtype_to_pctype(i);
5239                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5240                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5241                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5242         }
5243
5244         return 0;
5245 }
5246
5247 static int
5248 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5249 {
5250         uint32_t i;
5251         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5252
5253         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5254                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5255                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5256                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5257                                                 g_cfg->hash_func);
5258                 return -EINVAL;
5259         }
5260
5261         /*
5262          * As i40e supports less than 32 flow types, only first 32 bits need to
5263          * be checked.
5264          */
5265         mask0 = g_cfg->valid_bit_mask[0];
5266         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5267                 if (i == 0) {
5268                         /* Check if any unsupported flow type configured */
5269                         if ((mask0 | i40e_mask) ^ i40e_mask)
5270                                 goto mask_err;
5271                 } else {
5272                         if (g_cfg->valid_bit_mask[i])
5273                                 goto mask_err;
5274                 }
5275         }
5276
5277         return 0;
5278
5279 mask_err:
5280         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5281
5282         return -EINVAL;
5283 }
5284
5285 /*
5286  * Set global configurations of hash function type and symmetric hash enable
5287  * per flow type (pctype). Note any modifying global configuration will affect
5288  * all the ports on the same NIC.
5289  */
5290 static int
5291 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5292                                    struct rte_eth_hash_global_conf *g_cfg)
5293 {
5294         int ret;
5295         uint16_t i;
5296         uint32_t reg;
5297         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5298         enum i40e_filter_pctype pctype;
5299
5300         /* Check the input parameters */
5301         ret = i40e_hash_global_config_check(g_cfg);
5302         if (ret < 0)
5303                 return ret;
5304
5305         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5306                 if (!(mask0 & (1UL << i)))
5307                         continue;
5308                 mask0 &= ~(1UL << i);
5309                 pctype = i40e_flowtype_to_pctype(i);
5310                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5311                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5312                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5313         }
5314
5315         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5316         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5317                 /* Toeplitz */
5318                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5319                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5320                                                                 "Toeplitz");
5321                         goto out;
5322                 }
5323                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5324         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5325                 /* Simple XOR */
5326                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5327                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5328                                                         "Simple XOR");
5329                         goto out;
5330                 }
5331                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5332         } else
5333                 /* Use the default, and keep it as it is */
5334                 goto out;
5335
5336         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5337
5338 out:
5339         I40E_WRITE_FLUSH(hw);
5340
5341         return 0;
5342 }
5343
5344 static int
5345 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5346 {
5347         int ret = 0;
5348
5349         if (!hw || !info) {
5350                 PMD_DRV_LOG(ERR, "Invalid pointer");
5351                 return -EFAULT;
5352         }
5353
5354         switch (info->info_type) {
5355         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5356                 i40e_get_symmetric_hash_enable_per_port(hw,
5357                                         &(info->info.enable));
5358                 break;
5359         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5360                 ret = i40e_get_hash_filter_global_config(hw,
5361                                 &(info->info.global_conf));
5362                 break;
5363         default:
5364                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5365                                                         info->info_type);
5366                 ret = -EINVAL;
5367                 break;
5368         }
5369
5370         return ret;
5371 }
5372
5373 static int
5374 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5375 {
5376         int ret = 0;
5377
5378         if (!hw || !info) {
5379                 PMD_DRV_LOG(ERR, "Invalid pointer");
5380                 return -EFAULT;
5381         }
5382
5383         switch (info->info_type) {
5384         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5385                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5386                 break;
5387         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5388                 ret = i40e_set_hash_filter_global_config(hw,
5389                                 &(info->info.global_conf));
5390                 break;
5391         default:
5392                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5393                                                         info->info_type);
5394                 ret = -EINVAL;
5395                 break;
5396         }
5397
5398         return ret;
5399 }
5400
5401 /* Operations for hash function */
5402 static int
5403 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5404                       enum rte_filter_op filter_op,
5405                       void *arg)
5406 {
5407         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5408         int ret = 0;
5409
5410         switch (filter_op) {
5411         case RTE_ETH_FILTER_NOP:
5412                 break;
5413         case RTE_ETH_FILTER_GET:
5414                 ret = i40e_hash_filter_get(hw,
5415                         (struct rte_eth_hash_filter_info *)arg);
5416                 break;
5417         case RTE_ETH_FILTER_SET:
5418                 ret = i40e_hash_filter_set(hw,
5419                         (struct rte_eth_hash_filter_info *)arg);
5420                 break;
5421         default:
5422                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5423                                                                 filter_op);
5424                 ret = -ENOTSUP;
5425                 break;
5426         }
5427
5428         return ret;
5429 }
5430
5431 /*
5432  * Configure ethertype filter, which can director packet by filtering
5433  * with mac address and ether_type or only ether_type
5434  */
5435 static int
5436 i40e_ethertype_filter_set(struct i40e_pf *pf,
5437                         struct rte_eth_ethertype_filter *filter,
5438                         bool add)
5439 {
5440         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5441         struct i40e_control_filter_stats stats;
5442         uint16_t flags = 0;
5443         int ret;
5444
5445         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5446                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5447                 return -EINVAL;
5448         }
5449         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5450                 filter->ether_type == ETHER_TYPE_IPv6) {
5451                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5452                         " control packet filter.", filter->ether_type);
5453                 return -EINVAL;
5454         }
5455         if (filter->ether_type == ETHER_TYPE_VLAN)
5456                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5457                         " not supported.");
5458
5459         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5460                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5461         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5462                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5463         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5464
5465         memset(&stats, 0, sizeof(stats));
5466         ret = i40e_aq_add_rem_control_packet_filter(hw,
5467                         filter->mac_addr.addr_bytes,
5468                         filter->ether_type, flags,
5469                         pf->main_vsi->seid,
5470                         filter->queue, add, &stats, NULL);
5471
5472         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5473                          " mac_etype_used = %u, etype_used = %u,"
5474                          " mac_etype_free = %u, etype_free = %u\n",
5475                          ret, stats.mac_etype_used, stats.etype_used,
5476                          stats.mac_etype_free, stats.etype_free);
5477         if (ret < 0)
5478                 return -ENOSYS;
5479         return 0;
5480 }
5481
5482 /*
5483  * Handle operations for ethertype filter.
5484  */
5485 static int
5486 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5487                                 enum rte_filter_op filter_op,
5488                                 void *arg)
5489 {
5490         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5491         int ret = 0;
5492
5493         if (filter_op == RTE_ETH_FILTER_NOP)
5494                 return ret;
5495
5496         if (arg == NULL) {
5497                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5498                             filter_op);
5499                 return -EINVAL;
5500         }
5501
5502         switch (filter_op) {
5503         case RTE_ETH_FILTER_ADD:
5504                 ret = i40e_ethertype_filter_set(pf,
5505                         (struct rte_eth_ethertype_filter *)arg,
5506                         TRUE);
5507                 break;
5508         case RTE_ETH_FILTER_DELETE:
5509                 ret = i40e_ethertype_filter_set(pf,
5510                         (struct rte_eth_ethertype_filter *)arg,
5511                         FALSE);
5512                 break;
5513         default:
5514                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5515                 ret = -ENOSYS;
5516                 break;
5517         }
5518         return ret;
5519 }
5520
5521 static int
5522 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5523                      enum rte_filter_type filter_type,
5524                      enum rte_filter_op filter_op,
5525                      void *arg)
5526 {
5527         int ret = 0;
5528
5529         if (dev == NULL)
5530                 return -EINVAL;
5531
5532         switch (filter_type) {
5533         case RTE_ETH_FILTER_HASH:
5534                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5535                 break;
5536         case RTE_ETH_FILTER_MACVLAN:
5537                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5538                 break;
5539         case RTE_ETH_FILTER_ETHERTYPE:
5540                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5541                 break;
5542         case RTE_ETH_FILTER_TUNNEL:
5543                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5544                 break;
5545         case RTE_ETH_FILTER_FDIR:
5546                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5547                 break;
5548         default:
5549                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5550                                                         filter_type);
5551                 ret = -EINVAL;
5552                 break;
5553         }
5554
5555         return ret;
5556 }
5557
5558 /*
5559  * As some registers wouldn't be reset unless a global hardware reset,
5560  * hardware initialization is needed to put those registers into an
5561  * expected initial state.
5562  */
5563 static void
5564 i40e_hw_init(struct i40e_hw *hw)
5565 {
5566         /* clear the PF Queue Filter control register */
5567         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5568
5569         /* Disable symmetric hash per port */
5570         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5571 }
5572
5573 enum i40e_filter_pctype
5574 i40e_flowtype_to_pctype(uint16_t flow_type)
5575 {
5576         static const enum i40e_filter_pctype pctype_table[] = {
5577                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5578                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5579                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5580                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5581                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5582                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5583                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5584                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5585                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5586                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5587                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5588                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5589                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5590                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5591                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5592                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5593                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5594                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5595                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5596         };
5597
5598         return pctype_table[flow_type];
5599 }
5600
5601 uint16_t
5602 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5603 {
5604         static const uint16_t flowtype_table[] = {
5605                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5606                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5607                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5608                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5609                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5610                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5611                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5612                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5613                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5614                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5615                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5616                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5617                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5618                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5619                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5620                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5621                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5622                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5623                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5624         };
5625
5626         return flowtype_table[pctype];
5627 }
5628
5629 static int
5630 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5631 {
5632         struct i40e_aq_desc desc;
5633         enum i40e_status_code status;
5634
5635         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5636         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5637         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5638         if (status < 0)
5639                 return status;
5640
5641         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5642                                         (CHAR_BIT * sizeof(uint32_t))) +
5643                                 rte_le_to_cpu_32(desc.params.internal.param3);
5644
5645         return status;
5646 }
5647
5648 /*
5649  * On X710, performance number is far from the expectation on recent firmware
5650  * versions; on XL710, performance number is also far from the expectation on
5651  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5652  * mode is enabled and port MAC address is equal to the packet destination MAC
5653  * address. The fix for this issue may not be integrated in the following
5654  * firmware version. So the workaround in software driver is needed. It needs
5655  * to modify the initial values of 3 internal only registers for both X710 and
5656  * XL710. Note that the values for X710 or XL710 could be different, and the
5657  * workaround can be removed when it is fixed in firmware in the future.
5658  */
5659
5660 /* For both X710 and XL710 */
5661 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5662 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5663
5664 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5665 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5666
5667 /* For X710 */
5668 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5669 /* For XL710 */
5670 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5671 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5672
5673 static void
5674 i40e_configure_registers(struct i40e_hw *hw)
5675 {
5676         static struct {
5677                 uint32_t addr;
5678                 uint64_t val;
5679         } reg_table[] = {
5680                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5681                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5682                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5683         };
5684         uint64_t reg;
5685         uint32_t i;
5686         int ret;
5687
5688         for (i = 0; i < RTE_DIM(reg_table); i++) {
5689                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5690                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5691                                 reg_table[i].val =
5692                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5693                         else /* For X710 */
5694                                 reg_table[i].val =
5695                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5696                 }
5697
5698                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5699                 if (ret < 0) {
5700                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5701                                                         reg_table[i].addr);
5702                         break;
5703                 }
5704                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5705                                                 reg_table[i].addr, reg);
5706                 if (reg == reg_table[i].val)
5707                         continue;
5708
5709                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5710                                                 reg_table[i].val, NULL);
5711                 if (ret < 0) {
5712                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5713                                 "address of 0x%"PRIx32, reg_table[i].val,
5714                                                         reg_table[i].addr);
5715                         break;
5716                 }
5717                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5718                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5719         }
5720 }