lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds*/
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 static int eth_i40e_dev_init(\
  97                         __attribute__((unused)) struct eth_driver *eth_drv,
  98                         struct rte_eth_dev *eth_dev);
  99 static int i40e_dev_configure(struct rte_eth_dev *dev);
 100 static int i40e_dev_start(struct rte_eth_dev *dev);
 101 static void i40e_dev_stop(struct rte_eth_dev *dev);
 102 static void i40e_dev_close(struct rte_eth_dev *dev);
 103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 110                                struct rte_eth_stats *stats);
 111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 113                                             uint16_t queue_id,
 114                                             uint8_t stat_idx,
 115                                             uint8_t is_rx);
 116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_dev_info *dev_info);
 118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 119                                 uint16_t vlan_id,
 120                                 int on);
 121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 124                                       uint16_t queue,
 125                                       int on);
 126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 130                               struct rte_eth_fc_conf *fc_conf);
 131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 132                                        struct rte_eth_pfc_conf *pfc_conf);
 133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 134                           struct ether_addr *mac_addr,
 135                           uint32_t index,
 136                           uint32_t pool);
 137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 139                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 140                                     uint16_t reta_size);
 141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 142                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 143                                    uint16_t reta_size);
 144
 145 static int i40e_get_cap(struct i40e_hw *hw);
 146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 147 static int i40e_pf_setup(struct i40e_pf *pf);
 148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 151                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 152 static void i40e_stat_update_48(struct i40e_hw *hw,
 153                                uint32_t hireg,
 154                                uint32_t loreg,
 155                                bool offset_loaded,
 156                                uint64_t *offset,
 157                                uint64_t *stat);
 158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 159 static void i40e_dev_interrupt_handler(
 160                 __rte_unused struct rte_intr_handle *handle, void *param);
 161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 162                                 uint32_t base, uint32_t num);
 163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 165                         uint32_t base);
 166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 167                         uint16_t num);
 168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 169 static int i40e_veb_release(struct i40e_veb *veb);
 170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 171                                                 struct i40e_vsi *vsi);
 172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 175                                              struct i40e_macvlan_filter *mv_f,
 176                                              int num,
 177                                              struct ether_addr *addr);
 178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 179                                              struct i40e_macvlan_filter *mv_f,
 180                                              int num,
 181                                              uint16_t vlan);
 182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 184                                     struct rte_eth_rss_conf *rss_conf);
 185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 186                                       struct rte_eth_rss_conf *rss_conf);
 187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 188                                 struct rte_eth_udp_tunnel *udp_tunnel);
 189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 190                                 struct rte_eth_udp_tunnel *udp_tunnel);
 191 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 192                                 enum rte_filter_type filter_type,
 193                                 enum rte_filter_op filter_op,
 194                                 void *arg);
 195
 196 /* Default hash key buffer for RSS */
 197 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 198
 199 static struct rte_pci_id pci_id_i40e_map[] = {
 200 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 201 #include "rte_pci_dev_ids.h"
 202 { .vendor_id = 0, /* sentinel */ },
 203 };
 204
 205 static struct eth_dev_ops i40e_eth_dev_ops = {
 206         .dev_configure                = i40e_dev_configure,
 207         .dev_start                    = i40e_dev_start,
 208         .dev_stop                     = i40e_dev_stop,
 209         .dev_close                    = i40e_dev_close,
 210         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 211         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 212         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 213         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 214         .dev_set_link_up              = i40e_dev_set_link_up,
 215         .dev_set_link_down            = i40e_dev_set_link_down,
 216         .link_update                  = i40e_dev_link_update,
 217         .stats_get                    = i40e_dev_stats_get,
 218         .stats_reset                  = i40e_dev_stats_reset,
 219         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 220         .dev_infos_get                = i40e_dev_info_get,
 221         .vlan_filter_set              = i40e_vlan_filter_set,
 222         .vlan_tpid_set                = i40e_vlan_tpid_set,
 223         .vlan_offload_set             = i40e_vlan_offload_set,
 224         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 225         .vlan_pvid_set                = i40e_vlan_pvid_set,
 226         .rx_queue_start               = i40e_dev_rx_queue_start,
 227         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 228         .tx_queue_start               = i40e_dev_tx_queue_start,
 229         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 230         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 231         .rx_queue_release             = i40e_dev_rx_queue_release,
 232         .rx_queue_count               = i40e_dev_rx_queue_count,
 233         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 234         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 235         .tx_queue_release             = i40e_dev_tx_queue_release,
 236         .dev_led_on                   = i40e_dev_led_on,
 237         .dev_led_off                  = i40e_dev_led_off,
 238         .flow_ctrl_set                = i40e_flow_ctrl_set,
 239         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 240         .mac_addr_add                 = i40e_macaddr_add,
 241         .mac_addr_remove              = i40e_macaddr_remove,
 242         .reta_update                  = i40e_dev_rss_reta_update,
 243         .reta_query                   = i40e_dev_rss_reta_query,
 244         .rss_hash_update              = i40e_dev_rss_hash_update,
 245         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 246         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 247         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 248         .filter_ctrl                  = i40e_dev_filter_ctrl,
 249 };
 250
 251 static struct eth_driver rte_i40e_pmd = {
 252         {
 253                 .name = "rte_i40e_pmd",
 254                 .id_table = pci_id_i40e_map,
 255                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 256         },
 257         .eth_dev_init = eth_i40e_dev_init,
 258         .dev_private_size = sizeof(struct i40e_adapter),
 259 };
 260
 261 static inline int
 262 i40e_align_floor(int n)
 263 {
 264         if (n == 0)
 265                 return 0;
 266         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 267 }
 268
 269 static inline int
 270 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 271                                      struct rte_eth_link *link)
 272 {
 273         struct rte_eth_link *dst = link;
 274         struct rte_eth_link *src = &(dev->data->dev_link);
 275
 276         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 277                                         *(uint64_t *)src) == 0)
 278                 return -1;
 279
 280         return 0;
 281 }
 282
 283 static inline int
 284 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 285                                       struct rte_eth_link *link)
 286 {
 287         struct rte_eth_link *dst = &(dev->data->dev_link);
 288         struct rte_eth_link *src = link;
 289
 290         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 291                                         *(uint64_t *)src) == 0)
 292                 return -1;
 293
 294         return 0;
 295 }
 296
 297 /*
 298  * Driver initialization routine.
 299  * Invoked once at EAL init time.
 300  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 301  */
 302 static int
 303 rte_i40e_pmd_init(const char *name __rte_unused,
 304                   const char *params __rte_unused)
 305 {
 306         PMD_INIT_FUNC_TRACE();
 307         rte_eth_driver_register(&rte_i40e_pmd);
 308
 309         return 0;
 310 }
 311
 312 static struct rte_driver rte_i40e_driver = {
 313         .type = PMD_PDEV,
 314         .init = rte_i40e_pmd_init,
 315 };
 316
 317 PMD_REGISTER_DRIVER(rte_i40e_driver);
 318
 319 /*
 320  * Initialize registers for flexible payload, which should be set by NVM.
 321  * This should be removed from code once it is fixed in NVM.
 322  */
 323 #ifndef I40E_GLQF_ORT
 324 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 325 #endif
 326 #ifndef I40E_GLQF_PIT
 327 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 328 #endif
 329
 330 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 331 {
 332         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 333         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 334         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 335         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 336         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 337         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 338         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 339         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 340         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 341         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 342
 343         /* GLQF_PIT Registers */
 344         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 345         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 346 }
 347
 348 static int
 349 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 350                   struct rte_eth_dev *dev)
 351 {
 352         struct rte_pci_device *pci_dev;
 353         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 355         struct i40e_vsi *vsi;
 356         int ret;
 357         uint32_t len;
 358         uint8_t aq_fail = 0;
 359
 360         PMD_INIT_FUNC_TRACE();
 361
 362         dev->dev_ops = &i40e_eth_dev_ops;
 363         dev->rx_pkt_burst = i40e_recv_pkts;
 364         dev->tx_pkt_burst = i40e_xmit_pkts;
 365
 366         /* for secondary processes, we don't initialise any further as primary
 367          * has already done this work. Only check we don't need a different
 368          * RX function */
 369         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 370                 if (dev->data->scattered_rx)
 371                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 372                 return 0;
 373         }
 374         pci_dev = dev->pci_dev;
 375         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 376         pf->adapter->eth_dev = dev;
 377         pf->dev_data = dev->data;
 378
 379         hw->back = I40E_PF_TO_ADAPTER(pf);
 380         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 381         if (!hw->hw_addr) {
 382                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 383                              "as address is NULL");
 384                 return -ENODEV;
 385         }
 386
 387         hw->vendor_id = pci_dev->id.vendor_id;
 388         hw->device_id = pci_dev->id.device_id;
 389         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 390         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 391         hw->bus.device = pci_dev->addr.devid;
 392         hw->bus.func = pci_dev->addr.function;
 393
 394         /* Make sure all is clean before doing PF reset */
 395         i40e_clear_hw(hw);
 396
 397         /* Reset here to make sure all is clean for each PF */
 398         ret = i40e_pf_reset(hw);
 399         if (ret) {
 400                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 401                 return ret;
 402         }
 403
 404         /* Initialize the shared code (base driver) */
 405         ret = i40e_init_shared_code(hw);
 406         if (ret) {
 407                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 408                 return ret;
 409         }
 410
 411         /*
 412          * To work around the NVM issue,initialize registers
 413          * for flexible payload by software.
 414          * It should be removed once issues are fixed in NVM.
 415          */
 416         i40e_flex_payload_reg_init(hw);
 417
 418         /* Initialize the parameters for adminq */
 419         i40e_init_adminq_parameter(hw);
 420         ret = i40e_init_adminq(hw);
 421         if (ret != I40E_SUCCESS) {
 422                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 423                 return -EIO;
 424         }
 425         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 426                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 427                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 428                      ((hw->nvm.version >> 12) & 0xf),
 429                      ((hw->nvm.version >> 4) & 0xff),
 430                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 431
 432         /* Disable LLDP */
 433         ret = i40e_aq_stop_lldp(hw, true, NULL);
 434         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 435                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 436
 437         /* Clear PXE mode */
 438         i40e_clear_pxe_mode(hw);
 439
 440         /* Get hw capabilities */
 441         ret = i40e_get_cap(hw);
 442         if (ret != I40E_SUCCESS) {
 443                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 444                 goto err_get_capabilities;
 445         }
 446
 447         /* Initialize parameters for PF */
 448         ret = i40e_pf_parameter_init(dev);
 449         if (ret != 0) {
 450                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 451                 goto err_parameter_init;
 452         }
 453
 454         /* Initialize the queue management */
 455         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 456         if (ret < 0) {
 457                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 458                 goto err_qp_pool_init;
 459         }
 460         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 461                                 hw->func_caps.num_msix_vectors - 1);
 462         if (ret < 0) {
 463                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 464                 goto err_msix_pool_init;
 465         }
 466
 467         /* Initialize lan hmc */
 468         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 469                                 hw->func_caps.num_rx_qp, 0, 0);
 470         if (ret != I40E_SUCCESS) {
 471                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 472                 goto err_init_lan_hmc;
 473         }
 474
 475         /* Configure lan hmc */
 476         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 477         if (ret != I40E_SUCCESS) {
 478                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 479                 goto err_configure_lan_hmc;
 480         }
 481
 482         /* Get and check the mac address */
 483         i40e_get_mac_addr(hw, hw->mac.addr);
 484         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 485                 PMD_INIT_LOG(ERR, "mac address is not valid");
 486                 ret = -EIO;
 487                 goto err_get_mac_addr;
 488         }
 489         /* Copy the permanent MAC address */
 490         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 491                         (struct ether_addr *) hw->mac.perm_addr);
 492
 493         /* Disable flow control */
 494         hw->fc.requested_mode = I40E_FC_NONE;
 495         i40e_set_fc(hw, &aq_fail, TRUE);
 496
 497         /* PF setup, which includes VSI setup */
 498         ret = i40e_pf_setup(pf);
 499         if (ret) {
 500                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 501                 goto err_setup_pf_switch;
 502         }
 503
 504         vsi = pf->main_vsi;
 505
 506         /* Disable double vlan by default */
 507         i40e_vsi_config_double_vlan(vsi, FALSE);
 508
 509         if (!vsi->max_macaddrs)
 510                 len = ETHER_ADDR_LEN;
 511         else
 512                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 513
 514         /* Should be after VSI initialized */
 515         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 516         if (!dev->data->mac_addrs) {
 517                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 518                                         "for storing mac address");
 519                 goto err_mac_alloc;
 520         }
 521         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 522                                         &dev->data->mac_addrs[0]);
 523
 524         /* initialize pf host driver to setup SRIOV resource if applicable */
 525         i40e_pf_host_init(dev);
 526
 527         /* register callback func to eal lib */
 528         rte_intr_callback_register(&(pci_dev->intr_handle),
 529                 i40e_dev_interrupt_handler, (void *)dev);
 530
 531         /* configure and enable device interrupt */
 532         i40e_pf_config_irq0(hw);
 533         i40e_pf_enable_irq0(hw);
 534
 535         /* enable uio intr after callback register */
 536         rte_intr_enable(&(pci_dev->intr_handle));
 537
 538         return 0;
 539
 540 err_mac_alloc:
 541         i40e_vsi_release(pf->main_vsi);
 542 err_setup_pf_switch:
 543         i40e_fdir_teardown(pf);
 544 err_get_mac_addr:
 545 err_configure_lan_hmc:
 546         (void)i40e_shutdown_lan_hmc(hw);
 547 err_init_lan_hmc:
 548         i40e_res_pool_destroy(&pf->msix_pool);
 549 err_msix_pool_init:
 550         i40e_res_pool_destroy(&pf->qp_pool);
 551 err_qp_pool_init:
 552 err_parameter_init:
 553 err_get_capabilities:
 554         (void)i40e_shutdown_adminq(hw);
 555
 556         return ret;
 557 }
 558
 559 static int
 560 i40e_dev_configure(struct rte_eth_dev *dev)
 561 {
 562         int ret;
 563         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 564
 565         /* VMDQ setup.
 566          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 567          *  RSS setting have different requirements.
 568          *  General PMD driver call sequence are NIC init, configure,
 569          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 570          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 571          *  applicable. So, VMDQ setting has to be done before
 572          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 573          *  For RSS setting, it will try to calculate actual configured RX queue
 574          *  number, which will be available after rx_queue_setup(). dev_start()
 575          *  function is good to place RSS setup.
 576          */
 577         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 578                 ret = i40e_vmdq_setup(dev);
 579                 if (ret)
 580                         return ret;
 581         }
 582
 583         return i40e_dev_init_vlan(dev);
 584 }
 585
 586 void
 587 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 588 {
 589         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 590         uint16_t msix_vect = vsi->msix_intr;
 591         uint16_t i;
 592
 593         for (i = 0; i < vsi->nb_qps; i++) {
 594                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 595                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 596                 rte_wmb();
 597         }
 598
 599         if (vsi->type != I40E_VSI_SRIOV) {
 600                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 601                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 602                                 msix_vect - 1), 0);
 603         } else {
 604                 uint32_t reg;
 605                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 606                         vsi->user_param + (msix_vect - 1);
 607
 608                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 609         }
 610         I40E_WRITE_FLUSH(hw);
 611 }
 612
 613 static inline uint16_t
 614 i40e_calc_itr_interval(int16_t interval)
 615 {
 616         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 617                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 618
 619         /* Convert to hardware count, as writing each 1 represents 2 us */
 620         return (interval/2);
 621 }
 622
 623 void
 624 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 625 {
 626         uint32_t val;
 627         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 628         uint16_t msix_vect = vsi->msix_intr;
 629         int i;
 630
 631         for (i = 0; i < vsi->nb_qps; i++)
 632                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 633
 634         /* Bind all RX queues to allocated MSIX interrupt */
 635         for (i = 0; i < vsi->nb_qps; i++) {
 636                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 637                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 638                         ((vsi->base_queue + i + 1) <<
 639                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 640                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 641                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 642
 643                 if (i == vsi->nb_qps - 1)
 644                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 645                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 646         }
 647
 648         /* Write first RX queue to Link list register as the head element */
 649         if (vsi->type != I40E_VSI_SRIOV) {
 650                 uint16_t interval =
 651                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 652
 653                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 654                                                 (vsi->base_queue <<
 655                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 656                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 657
 658                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 659                                                 msix_vect - 1), interval);
 660
 661 #ifndef I40E_GLINT_CTL
 662 #define I40E_GLINT_CTL                     0x0003F800
 663 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 664 #endif
 665                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 666                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 667                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 668         } else {
 669                 uint32_t reg;
 670
 671                 /* num_msix_vectors_vf needs to minus irq0 */
 672                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 673                         vsi->user_param + (msix_vect - 1);
 674
 675                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 676                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 677                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 678         }
 679
 680         I40E_WRITE_FLUSH(hw);
 681 }
 682
 683 static void
 684 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 685 {
 686         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 687         uint16_t interval = i40e_calc_itr_interval(\
 688                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 689
 690         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 691                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 692                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 693                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 694                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 695 }
 696
 697 static void
 698 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 699 {
 700         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 701
 702         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 703 }
 704
 705 static inline uint8_t
 706 i40e_parse_link_speed(uint16_t eth_link_speed)
 707 {
 708         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 709
 710         switch (eth_link_speed) {
 711         case ETH_LINK_SPEED_40G:
 712                 link_speed = I40E_LINK_SPEED_40GB;
 713                 break;
 714         case ETH_LINK_SPEED_20G:
 715                 link_speed = I40E_LINK_SPEED_20GB;
 716                 break;
 717         case ETH_LINK_SPEED_10G:
 718                 link_speed = I40E_LINK_SPEED_10GB;
 719                 break;
 720         case ETH_LINK_SPEED_1000:
 721                 link_speed = I40E_LINK_SPEED_1GB;
 722                 break;
 723         case ETH_LINK_SPEED_100:
 724                 link_speed = I40E_LINK_SPEED_100MB;
 725                 break;
 726         }
 727
 728         return link_speed;
 729 }
 730
 731 static int
 732 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 733 {
 734         enum i40e_status_code status;
 735         struct i40e_aq_get_phy_abilities_resp phy_ab;
 736         struct i40e_aq_set_phy_config phy_conf;
 737         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 738                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 739                         I40E_AQ_PHY_FLAG_LOW_POWER;
 740         const uint8_t advt = I40E_LINK_SPEED_40GB |
 741                         I40E_LINK_SPEED_10GB |
 742                         I40E_LINK_SPEED_1GB |
 743                         I40E_LINK_SPEED_100MB;
 744         int ret = -ENOTSUP;
 745
 746         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 747                                               NULL);
 748         if (status)
 749                 return ret;
 750
 751         memset(&phy_conf, 0, sizeof(phy_conf));
 752
 753         /* bits 0-2 use the values from get_phy_abilities_resp */
 754         abilities &= ~mask;
 755         abilities |= phy_ab.abilities & mask;
 756
 757         /* update ablities and speed */
 758         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 759                 phy_conf.link_speed = advt;
 760         else
 761                 phy_conf.link_speed = force_speed;
 762
 763         phy_conf.abilities = abilities;
 764
 765         /* use get_phy_abilities_resp value for the rest */
 766         phy_conf.phy_type = phy_ab.phy_type;
 767         phy_conf.eee_capability = phy_ab.eee_capability;
 768         phy_conf.eeer = phy_ab.eeer_val;
 769         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 770
 771         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 772                     phy_ab.abilities, phy_ab.link_speed);
 773         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 774                     phy_conf.abilities, phy_conf.link_speed);
 775
 776         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 777         if (status)
 778                 return ret;
 779
 780         return I40E_SUCCESS;
 781 }
 782
 783 static int
 784 i40e_apply_link_speed(struct rte_eth_dev *dev)
 785 {
 786         uint8_t speed;
 787         uint8_t abilities = 0;
 788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 789         struct rte_eth_conf *conf = &dev->data->dev_conf;
 790
 791         speed = i40e_parse_link_speed(conf->link_speed);
 792         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 793         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 794                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 795         else
 796                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 797
 798         return i40e_phy_conf_link(hw, abilities, speed);
 799 }
 800
 801 static int
 802 i40e_dev_start(struct rte_eth_dev *dev)
 803 {
 804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 806         struct i40e_vsi *main_vsi = pf->main_vsi;
 807         int ret, i;
 808
 809         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 810                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 811                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 812                              dev->data->dev_conf.link_duplex,
 813                              dev->data->port_id);
 814                 return -EINVAL;
 815         }
 816
 817         /* Initialize VSI */
 818         ret = i40e_dev_rxtx_init(pf);
 819         if (ret != I40E_SUCCESS) {
 820                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 821                 goto err_up;
 822         }
 823
 824         /* Map queues with MSIX interrupt */
 825         i40e_vsi_queues_bind_intr(main_vsi);
 826         i40e_vsi_enable_queues_intr(main_vsi);
 827
 828         /* Map VMDQ VSI queues with MSIX interrupt */
 829         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 830                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 831                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 832         }
 833
 834         ret = i40e_fdir_configure(dev);
 835         if (ret < 0) {
 836                 PMD_DRV_LOG(ERR, "failed to configure fdir.");
 837                 goto err_up;
 838         }
 839
 840         /* enable FDIR MSIX interrupt */
 841         if (pf->flags & I40E_FLAG_FDIR) {
 842                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 843                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 844         }
 845
 846         /* Enable all queues which have been configured */
 847         ret = i40e_dev_switch_queues(pf, TRUE);
 848         if (ret != I40E_SUCCESS) {
 849                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 850                 goto err_up;
 851         }
 852
 853         /* Enable receiving broadcast packets */
 854         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 855         if (ret != I40E_SUCCESS)
 856                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 857
 858         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 859                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 860                                                 true, NULL);
 861                 if (ret != I40E_SUCCESS)
 862                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 863         }
 864
 865         /* Apply link configure */
 866         ret = i40e_apply_link_speed(dev);
 867         if (I40E_SUCCESS != ret) {
 868                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 869                 goto err_up;
 870         }
 871
 872         return I40E_SUCCESS;
 873
 874 err_up:
 875         i40e_dev_switch_queues(pf, FALSE);
 876         i40e_dev_clear_queues(dev);
 877
 878         return ret;
 879 }
 880
 881 static void
 882 i40e_dev_stop(struct rte_eth_dev *dev)
 883 {
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_vsi *main_vsi = pf->main_vsi;
 886         int i;
 887
 888         /* Disable all queues */
 889         i40e_dev_switch_queues(pf, FALSE);
 890
 891         /* un-map queues with interrupt registers */
 892         i40e_vsi_disable_queues_intr(main_vsi);
 893         i40e_vsi_queues_unbind_intr(main_vsi);
 894
 895         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 896                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 897                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 898         }
 899
 900         if (pf->flags & I40E_FLAG_FDIR) {
 901                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 902                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 903         }
 904         /* Clear all queues and release memory */
 905         i40e_dev_clear_queues(dev);
 906
 907         /* Set link down */
 908         i40e_dev_set_link_down(dev);
 909
 910 }
 911
 912 static void
 913 i40e_dev_close(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 917         uint32_t reg;
 918
 919         PMD_INIT_FUNC_TRACE();
 920
 921         i40e_dev_stop(dev);
 922
 923         /* Disable interrupt */
 924         i40e_pf_disable_irq0(hw);
 925         rte_intr_disable(&(dev->pci_dev->intr_handle));
 926
 927         /* shutdown and destroy the HMC */
 928         i40e_shutdown_lan_hmc(hw);
 929
 930         /* release all the existing VSIs and VEBs */
 931         i40e_fdir_teardown(pf);
 932         i40e_vsi_release(pf->main_vsi);
 933
 934         /* shutdown the adminq */
 935         i40e_aq_queue_shutdown(hw, true);
 936         i40e_shutdown_adminq(hw);
 937
 938         i40e_res_pool_destroy(&pf->qp_pool);
 939         i40e_res_pool_destroy(&pf->msix_pool);
 940
 941         /* force a PF reset to clean anything leftover */
 942         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 943         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 944                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 945         I40E_WRITE_FLUSH(hw);
 946 }
 947
 948 static void
 949 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         struct i40e_vsi *vsi = pf->main_vsi;
 954         int status;
 955
 956         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 957                                                         true, NULL);
 958         if (status != I40E_SUCCESS)
 959                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 960
 961         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 962                                                         TRUE, NULL);
 963         if (status != I40E_SUCCESS)
 964                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 965
 966 }
 967
 968 static void
 969 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 970 {
 971         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 973         struct i40e_vsi *vsi = pf->main_vsi;
 974         int status;
 975
 976         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 977                                                         false, NULL);
 978         if (status != I40E_SUCCESS)
 979                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 980
 981         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 982                                                         false, NULL);
 983         if (status != I40E_SUCCESS)
 984                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 985 }
 986
 987 static void
 988 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 989 {
 990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 991         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 992         struct i40e_vsi *vsi = pf->main_vsi;
 993         int ret;
 994
 995         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 996         if (ret != I40E_SUCCESS)
 997                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 998 }
 999
1000 static void
1001 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1002 {
1003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005         struct i40e_vsi *vsi = pf->main_vsi;
1006         int ret;
1007
1008         if (dev->data->promiscuous == 1)
1009                 return; /* must remain in all_multicast mode */
1010
1011         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1012                                 vsi->seid, FALSE, NULL);
1013         if (ret != I40E_SUCCESS)
1014                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1015 }
1016
1017 /*
1018  * Set device link up.
1019  */
1020 static int
1021 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1022 {
1023         /* re-apply link speed setting */
1024         return i40e_apply_link_speed(dev);
1025 }
1026
1027 /*
1028  * Set device link down.
1029  */
1030 static int
1031 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1032 {
1033         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1034         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036
1037         return i40e_phy_conf_link(hw, abilities, speed);
1038 }
1039
1040 int
1041 i40e_dev_link_update(struct rte_eth_dev *dev,
1042                      __rte_unused int wait_to_complete)
1043 {
1044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045         struct i40e_link_status link_status;
1046         struct rte_eth_link link, old;
1047         int status;
1048
1049         memset(&link, 0, sizeof(link));
1050         memset(&old, 0, sizeof(old));
1051         memset(&link_status, 0, sizeof(link_status));
1052         rte_i40e_dev_atomic_read_link_status(dev, &old);
1053
1054         /* Get link status information from hardware */
1055         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1056         if (status != I40E_SUCCESS) {
1057                 link.link_speed = ETH_LINK_SPEED_100;
1058                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1059                 PMD_DRV_LOG(ERR, "Failed to get link info");
1060                 goto out;
1061         }
1062
1063         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1064
1065         if (!link.link_status)
1066                 goto out;
1067
1068         /* i40e uses full duplex only */
1069         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1070
1071         /* Parse the link status */
1072         switch (link_status.link_speed) {
1073         case I40E_LINK_SPEED_100MB:
1074                 link.link_speed = ETH_LINK_SPEED_100;
1075                 break;
1076         case I40E_LINK_SPEED_1GB:
1077                 link.link_speed = ETH_LINK_SPEED_1000;
1078                 break;
1079         case I40E_LINK_SPEED_10GB:
1080                 link.link_speed = ETH_LINK_SPEED_10G;
1081                 break;
1082         case I40E_LINK_SPEED_20GB:
1083                 link.link_speed = ETH_LINK_SPEED_20G;
1084                 break;
1085         case I40E_LINK_SPEED_40GB:
1086                 link.link_speed = ETH_LINK_SPEED_40G;
1087                 break;
1088         default:
1089                 link.link_speed = ETH_LINK_SPEED_100;
1090                 break;
1091         }
1092
1093 out:
1094         rte_i40e_dev_atomic_write_link_status(dev, &link);
1095         if (link.link_status == old.link_status)
1096                 return -1;
1097
1098         return 0;
1099 }
1100
1101 /* Get all the statistics of a VSI */
1102 void
1103 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1104 {
1105         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1106         struct i40e_eth_stats *nes = &vsi->eth_stats;
1107         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1108         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1109
1110         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1111                             vsi->offset_loaded, &oes->rx_bytes,
1112                             &nes->rx_bytes);
1113         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1114                             vsi->offset_loaded, &oes->rx_unicast,
1115                             &nes->rx_unicast);
1116         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1117                             vsi->offset_loaded, &oes->rx_multicast,
1118                             &nes->rx_multicast);
1119         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1120                             vsi->offset_loaded, &oes->rx_broadcast,
1121                             &nes->rx_broadcast);
1122         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1123                             &oes->rx_discards, &nes->rx_discards);
1124         /* GLV_REPC not supported */
1125         /* GLV_RMPC not supported */
1126         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1127                             &oes->rx_unknown_protocol,
1128                             &nes->rx_unknown_protocol);
1129         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1130                             vsi->offset_loaded, &oes->tx_bytes,
1131                             &nes->tx_bytes);
1132         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1133                             vsi->offset_loaded, &oes->tx_unicast,
1134                             &nes->tx_unicast);
1135         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1136                             vsi->offset_loaded, &oes->tx_multicast,
1137                             &nes->tx_multicast);
1138         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1139                             vsi->offset_loaded,  &oes->tx_broadcast,
1140                             &nes->tx_broadcast);
1141         /* GLV_TDPC not supported */
1142         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1143                             &oes->tx_errors, &nes->tx_errors);
1144         vsi->offset_loaded = true;
1145
1146         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1147                     vsi->vsi_id);
1148         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1149         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1150         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1151         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1152         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1153         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1154                     nes->rx_unknown_protocol);
1155         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1156         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1157         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1158         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1159         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1160         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1161         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1162                     vsi->vsi_id);
1163 }
1164
1165 /* Get all statistics of a port */
1166 static void
1167 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1168 {
1169         uint32_t i;
1170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1171         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1172         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1173         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1174
1175         /* Get statistics of struct i40e_eth_stats */
1176         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1177                             I40E_GLPRT_GORCL(hw->port),
1178                             pf->offset_loaded, &os->eth.rx_bytes,
1179                             &ns->eth.rx_bytes);
1180         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1181                             I40E_GLPRT_UPRCL(hw->port),
1182                             pf->offset_loaded, &os->eth.rx_unicast,
1183                             &ns->eth.rx_unicast);
1184         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1185                             I40E_GLPRT_MPRCL(hw->port),
1186                             pf->offset_loaded, &os->eth.rx_multicast,
1187                             &ns->eth.rx_multicast);
1188         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1189                             I40E_GLPRT_BPRCL(hw->port),
1190                             pf->offset_loaded, &os->eth.rx_broadcast,
1191                             &ns->eth.rx_broadcast);
1192         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1193                             pf->offset_loaded, &os->eth.rx_discards,
1194                             &ns->eth.rx_discards);
1195         /* GLPRT_REPC not supported */
1196         /* GLPRT_RMPC not supported */
1197         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1198                             pf->offset_loaded,
1199                             &os->eth.rx_unknown_protocol,
1200                             &ns->eth.rx_unknown_protocol);
1201         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1202                             I40E_GLPRT_GOTCL(hw->port),
1203                             pf->offset_loaded, &os->eth.tx_bytes,
1204                             &ns->eth.tx_bytes);
1205         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1206                             I40E_GLPRT_UPTCL(hw->port),
1207                             pf->offset_loaded, &os->eth.tx_unicast,
1208                             &ns->eth.tx_unicast);
1209         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1210                             I40E_GLPRT_MPTCL(hw->port),
1211                             pf->offset_loaded, &os->eth.tx_multicast,
1212                             &ns->eth.tx_multicast);
1213         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1214                             I40E_GLPRT_BPTCL(hw->port),
1215                             pf->offset_loaded, &os->eth.tx_broadcast,
1216                             &ns->eth.tx_broadcast);
1217         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1218                             pf->offset_loaded, &os->eth.tx_discards,
1219                             &ns->eth.tx_discards);
1220         /* GLPRT_TEPC not supported */
1221
1222         /* additional port specific stats */
1223         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1224                             pf->offset_loaded, &os->tx_dropped_link_down,
1225                             &ns->tx_dropped_link_down);
1226         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1227                             pf->offset_loaded, &os->crc_errors,
1228                             &ns->crc_errors);
1229         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1230                             pf->offset_loaded, &os->illegal_bytes,
1231                             &ns->illegal_bytes);
1232         /* GLPRT_ERRBC not supported */
1233         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1234                             pf->offset_loaded, &os->mac_local_faults,
1235                             &ns->mac_local_faults);
1236         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1237                             pf->offset_loaded, &os->mac_remote_faults,
1238                             &ns->mac_remote_faults);
1239         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1240                             pf->offset_loaded, &os->rx_length_errors,
1241                             &ns->rx_length_errors);
1242         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1243                             pf->offset_loaded, &os->link_xon_rx,
1244                             &ns->link_xon_rx);
1245         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1246                             pf->offset_loaded, &os->link_xoff_rx,
1247                             &ns->link_xoff_rx);
1248         for (i = 0; i < 8; i++) {
1249                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1250                                     pf->offset_loaded,
1251                                     &os->priority_xon_rx[i],
1252                                     &ns->priority_xon_rx[i]);
1253                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1254                                     pf->offset_loaded,
1255                                     &os->priority_xoff_rx[i],
1256                                     &ns->priority_xoff_rx[i]);
1257         }
1258         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1259                             pf->offset_loaded, &os->link_xon_tx,
1260                             &ns->link_xon_tx);
1261         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1262                             pf->offset_loaded, &os->link_xoff_tx,
1263                             &ns->link_xoff_tx);
1264         for (i = 0; i < 8; i++) {
1265                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1266                                     pf->offset_loaded,
1267                                     &os->priority_xon_tx[i],
1268                                     &ns->priority_xon_tx[i]);
1269                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1270                                     pf->offset_loaded,
1271                                     &os->priority_xoff_tx[i],
1272                                     &ns->priority_xoff_tx[i]);
1273                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1274                                     pf->offset_loaded,
1275                                     &os->priority_xon_2_xoff[i],
1276                                     &ns->priority_xon_2_xoff[i]);
1277         }
1278         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1279                             I40E_GLPRT_PRC64L(hw->port),
1280                             pf->offset_loaded, &os->rx_size_64,
1281                             &ns->rx_size_64);
1282         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1283                             I40E_GLPRT_PRC127L(hw->port),
1284                             pf->offset_loaded, &os->rx_size_127,
1285                             &ns->rx_size_127);
1286         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1287                             I40E_GLPRT_PRC255L(hw->port),
1288                             pf->offset_loaded, &os->rx_size_255,
1289                             &ns->rx_size_255);
1290         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1291                             I40E_GLPRT_PRC511L(hw->port),
1292                             pf->offset_loaded, &os->rx_size_511,
1293                             &ns->rx_size_511);
1294         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1295                             I40E_GLPRT_PRC1023L(hw->port),
1296                             pf->offset_loaded, &os->rx_size_1023,
1297                             &ns->rx_size_1023);
1298         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1299                             I40E_GLPRT_PRC1522L(hw->port),
1300                             pf->offset_loaded, &os->rx_size_1522,
1301                             &ns->rx_size_1522);
1302         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1303                             I40E_GLPRT_PRC9522L(hw->port),
1304                             pf->offset_loaded, &os->rx_size_big,
1305                             &ns->rx_size_big);
1306         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1307                             pf->offset_loaded, &os->rx_undersize,
1308                             &ns->rx_undersize);
1309         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1310                             pf->offset_loaded, &os->rx_fragments,
1311                             &ns->rx_fragments);
1312         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1313                             pf->offset_loaded, &os->rx_oversize,
1314                             &ns->rx_oversize);
1315         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1316                             pf->offset_loaded, &os->rx_jabber,
1317                             &ns->rx_jabber);
1318         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1319                             I40E_GLPRT_PTC64L(hw->port),
1320                             pf->offset_loaded, &os->tx_size_64,
1321                             &ns->tx_size_64);
1322         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1323                             I40E_GLPRT_PTC127L(hw->port),
1324                             pf->offset_loaded, &os->tx_size_127,
1325                             &ns->tx_size_127);
1326         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1327                             I40E_GLPRT_PTC255L(hw->port),
1328                             pf->offset_loaded, &os->tx_size_255,
1329                             &ns->tx_size_255);
1330         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1331                             I40E_GLPRT_PTC511L(hw->port),
1332                             pf->offset_loaded, &os->tx_size_511,
1333                             &ns->tx_size_511);
1334         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1335                             I40E_GLPRT_PTC1023L(hw->port),
1336                             pf->offset_loaded, &os->tx_size_1023,
1337                             &ns->tx_size_1023);
1338         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1339                             I40E_GLPRT_PTC1522L(hw->port),
1340                             pf->offset_loaded, &os->tx_size_1522,
1341                             &ns->tx_size_1522);
1342         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1343                             I40E_GLPRT_PTC9522L(hw->port),
1344                             pf->offset_loaded, &os->tx_size_big,
1345                             &ns->tx_size_big);
1346         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1347                            pf->offset_loaded,
1348                            &os->fd_sb_match, &ns->fd_sb_match);
1349         /* GLPRT_MSPDC not supported */
1350         /* GLPRT_XEC not supported */
1351
1352         pf->offset_loaded = true;
1353
1354         if (pf->main_vsi)
1355                 i40e_update_vsi_stats(pf->main_vsi);
1356
1357         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1358                                                 ns->eth.rx_broadcast;
1359         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1360                                                 ns->eth.tx_broadcast;
1361         stats->ibytes   = ns->eth.rx_bytes;
1362         stats->obytes   = ns->eth.tx_bytes;
1363         stats->oerrors  = ns->eth.tx_errors;
1364         stats->imcasts  = ns->eth.rx_multicast;
1365         stats->fdirmatch = ns->fd_sb_match;
1366
1367         /* Rx Errors */
1368         stats->ibadcrc  = ns->crc_errors;
1369         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1370                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1371         stats->imissed  = ns->eth.rx_discards;
1372         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1373
1374         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1375         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1376         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1377         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1378         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1379         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1380         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1381                     ns->eth.rx_unknown_protocol);
1382         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1383         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1384         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1385         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1386         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1387         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1388
1389         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1390                     ns->tx_dropped_link_down);
1391         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1392         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1393                     ns->illegal_bytes);
1394         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1395         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1396                     ns->mac_local_faults);
1397         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1398                     ns->mac_remote_faults);
1399         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1400                     ns->rx_length_errors);
1401         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1402         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1403         for (i = 0; i < 8; i++) {
1404                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1405                                 i, ns->priority_xon_rx[i]);
1406                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1407                                 i, ns->priority_xoff_rx[i]);
1408         }
1409         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1410         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1411         for (i = 0; i < 8; i++) {
1412                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1413                                 i, ns->priority_xon_tx[i]);
1414                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1415                                 i, ns->priority_xoff_tx[i]);
1416                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1417                                 i, ns->priority_xon_2_xoff[i]);
1418         }
1419         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1420         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1421         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1422         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1423         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1424         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1425         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1426         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1427         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1428         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1429         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1430         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1431         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1432         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1433         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1434         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1435         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1436         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1437         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1438                         ns->mac_short_packet_dropped);
1439         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1440                     ns->checksum_error);
1441         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1442         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1443 }
1444
1445 /* Reset the statistics */
1446 static void
1447 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1448 {
1449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1450
1451         /* It results in reloading the start point of each counter */
1452         pf->offset_loaded = false;
1453 }
1454
1455 static int
1456 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1457                                  __rte_unused uint16_t queue_id,
1458                                  __rte_unused uint8_t stat_idx,
1459                                  __rte_unused uint8_t is_rx)
1460 {
1461         PMD_INIT_FUNC_TRACE();
1462
1463         return -ENOSYS;
1464 }
1465
1466 static void
1467 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1468 {
1469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1470         struct i40e_vsi *vsi = pf->main_vsi;
1471
1472         dev_info->max_rx_queues = vsi->nb_qps;
1473         dev_info->max_tx_queues = vsi->nb_qps;
1474         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1475         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1476         dev_info->max_mac_addrs = vsi->max_macaddrs;
1477         dev_info->max_vfs = dev->pci_dev->max_vfs;
1478         dev_info->rx_offload_capa =
1479                 DEV_RX_OFFLOAD_VLAN_STRIP |
1480                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1481                 DEV_RX_OFFLOAD_UDP_CKSUM |
1482                 DEV_RX_OFFLOAD_TCP_CKSUM;
1483         dev_info->tx_offload_capa =
1484                 DEV_TX_OFFLOAD_VLAN_INSERT |
1485                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1486                 DEV_TX_OFFLOAD_UDP_CKSUM |
1487                 DEV_TX_OFFLOAD_TCP_CKSUM |
1488                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1489         dev_info->reta_size = pf->hash_lut_size;
1490
1491         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1492                 .rx_thresh = {
1493                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1494                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1495                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1496                 },
1497                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1498                 .rx_drop_en = 0,
1499         };
1500
1501         dev_info->default_txconf = (struct rte_eth_txconf) {
1502                 .tx_thresh = {
1503                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1504                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1505                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1506                 },
1507                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1508                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1509                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1510                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1511         };
1512
1513         if (pf->flags | I40E_FLAG_VMDQ) {
1514                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1515                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1516                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1517                                                 pf->max_nb_vmdq_vsi;
1518                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1519                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1520                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1521         }
1522 }
1523
1524 static int
1525 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1526 {
1527         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1528         struct i40e_vsi *vsi = pf->main_vsi;
1529         PMD_INIT_FUNC_TRACE();
1530
1531         if (on)
1532                 return i40e_vsi_add_vlan(vsi, vlan_id);
1533         else
1534                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1535 }
1536
1537 static void
1538 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1539                    __rte_unused uint16_t tpid)
1540 {
1541         PMD_INIT_FUNC_TRACE();
1542 }
1543
1544 static void
1545 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1546 {
1547         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1548         struct i40e_vsi *vsi = pf->main_vsi;
1549
1550         if (mask & ETH_VLAN_STRIP_MASK) {
1551                 /* Enable or disable VLAN stripping */
1552                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1553                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1554                 else
1555                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1556         }
1557
1558         if (mask & ETH_VLAN_EXTEND_MASK) {
1559                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1560                         i40e_vsi_config_double_vlan(vsi, TRUE);
1561                 else
1562                         i40e_vsi_config_double_vlan(vsi, FALSE);
1563         }
1564 }
1565
1566 static void
1567 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1568                           __rte_unused uint16_t queue,
1569                           __rte_unused int on)
1570 {
1571         PMD_INIT_FUNC_TRACE();
1572 }
1573
1574 static int
1575 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1576 {
1577         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1578         struct i40e_vsi *vsi = pf->main_vsi;
1579         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1580         struct i40e_vsi_vlan_pvid_info info;
1581
1582         memset(&info, 0, sizeof(info));
1583         info.on = on;
1584         if (info.on)
1585                 info.config.pvid = pvid;
1586         else {
1587                 info.config.reject.tagged =
1588                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1589                 info.config.reject.untagged =
1590                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1591         }
1592
1593         return i40e_vsi_vlan_pvid_set(vsi, &info);
1594 }
1595
1596 static int
1597 i40e_dev_led_on(struct rte_eth_dev *dev)
1598 {
1599         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600         uint32_t mode = i40e_led_get(hw);
1601
1602         if (mode == 0)
1603                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1604
1605         return 0;
1606 }
1607
1608 static int
1609 i40e_dev_led_off(struct rte_eth_dev *dev)
1610 {
1611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612         uint32_t mode = i40e_led_get(hw);
1613
1614         if (mode != 0)
1615                 i40e_led_set(hw, 0, false);
1616
1617         return 0;
1618 }
1619
1620 static int
1621 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1622                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1623 {
1624         PMD_INIT_FUNC_TRACE();
1625
1626         return -ENOSYS;
1627 }
1628
1629 static int
1630 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1631                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1632 {
1633         PMD_INIT_FUNC_TRACE();
1634
1635         return -ENOSYS;
1636 }
1637
1638 /* Add a MAC address, and update filters */
1639 static void
1640 i40e_macaddr_add(struct rte_eth_dev *dev,
1641                  struct ether_addr *mac_addr,
1642                  __rte_unused uint32_t index,
1643                  uint32_t pool)
1644 {
1645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1646         struct i40e_mac_filter_info mac_filter;
1647         struct i40e_vsi *vsi;
1648         int ret;
1649
1650         /* If VMDQ not enabled or configured, return */
1651         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1652                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1653                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1654                         pool);
1655                 return;
1656         }
1657
1658         if (pool > pf->nb_cfg_vmdq_vsi) {
1659                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1660                                 pool, pf->nb_cfg_vmdq_vsi);
1661                 return;
1662         }
1663
1664         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1665         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1666
1667         if (pool == 0)
1668                 vsi = pf->main_vsi;
1669         else
1670                 vsi = pf->vmdq[pool - 1].vsi;
1671
1672         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1673         if (ret != I40E_SUCCESS) {
1674                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1675                 return;
1676         }
1677 }
1678
1679 /* Remove a MAC address, and update filters */
1680 static void
1681 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_vsi *vsi;
1685         struct rte_eth_dev_data *data = dev->data;
1686         struct ether_addr *macaddr;
1687         int ret;
1688         uint32_t i;
1689         uint64_t pool_sel;
1690
1691         macaddr = &(data->mac_addrs[index]);
1692
1693         pool_sel = dev->data->mac_pool_sel[index];
1694
1695         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1696                 if (pool_sel & (1ULL << i)) {
1697                         if (i == 0)
1698                                 vsi = pf->main_vsi;
1699                         else {
1700                                 /* No VMDQ pool enabled or configured */
1701                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1702                                         (i > pf->nb_cfg_vmdq_vsi)) {
1703                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1704                                                         "/configured");
1705                                         return;
1706                                 }
1707                                 vsi = pf->vmdq[i - 1].vsi;
1708                         }
1709                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1710
1711                         if (ret) {
1712                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1713                                 return;
1714                         }
1715                 }
1716         }
1717 }
1718
1719 /* Set perfect match or hash match of MAC and VLAN for a VF */
1720 static int
1721 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1722                  struct rte_eth_mac_filter *filter,
1723                  bool add)
1724 {
1725         struct i40e_hw *hw;
1726         struct i40e_mac_filter_info mac_filter;
1727         struct ether_addr old_mac;
1728         struct ether_addr *new_mac;
1729         struct i40e_pf_vf *vf = NULL;
1730         uint16_t vf_id;
1731         int ret;
1732
1733         if (pf == NULL) {
1734                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1735                 return -EINVAL;
1736         }
1737         hw = I40E_PF_TO_HW(pf);
1738
1739         if (filter == NULL) {
1740                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1741                 return -EINVAL;
1742         }
1743
1744         new_mac = &filter->mac_addr;
1745
1746         if (is_zero_ether_addr(new_mac)) {
1747                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1748                 return -EINVAL;
1749         }
1750
1751         vf_id = filter->dst_id;
1752
1753         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1754                 PMD_DRV_LOG(ERR, "Invalid argument.");
1755                 return -EINVAL;
1756         }
1757         vf = &pf->vfs[vf_id];
1758
1759         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1760                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1761                 return -EINVAL;
1762         }
1763
1764         if (add) {
1765                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1766                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1767                                 ETHER_ADDR_LEN);
1768                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1769                                  ETHER_ADDR_LEN);
1770
1771                 mac_filter.filter_type = filter->filter_type;
1772                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1773                 if (ret != I40E_SUCCESS) {
1774                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1775                         return -1;
1776                 }
1777                 ether_addr_copy(new_mac, &pf->dev_addr);
1778         } else {
1779                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1780                                 ETHER_ADDR_LEN);
1781                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1782                 if (ret != I40E_SUCCESS) {
1783                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1784                         return -1;
1785                 }
1786
1787                 /* Clear device address as it has been removed */
1788                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1789                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1790         }
1791
1792         return 0;
1793 }
1794
1795 /* MAC filter handle */
1796 static int
1797 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1798                 void *arg)
1799 {
1800         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1801         struct rte_eth_mac_filter *filter;
1802         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1803         int ret = I40E_NOT_SUPPORTED;
1804
1805         filter = (struct rte_eth_mac_filter *)(arg);
1806
1807         switch (filter_op) {
1808         case RTE_ETH_FILTER_NOP:
1809                 ret = I40E_SUCCESS;
1810                 break;
1811         case RTE_ETH_FILTER_ADD:
1812                 i40e_pf_disable_irq0(hw);
1813                 if (filter->is_vf)
1814                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1815                 i40e_pf_enable_irq0(hw);
1816                 break;
1817         case RTE_ETH_FILTER_DELETE:
1818                 i40e_pf_disable_irq0(hw);
1819                 if (filter->is_vf)
1820                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1821                 i40e_pf_enable_irq0(hw);
1822                 break;
1823         default:
1824                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1825                 ret = I40E_ERR_PARAM;
1826                 break;
1827         }
1828
1829         return ret;
1830 }
1831
1832 static int
1833 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1834                          struct rte_eth_rss_reta_entry64 *reta_conf,
1835                          uint16_t reta_size)
1836 {
1837         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         uint32_t lut, l;
1840         uint16_t i, j, lut_size = pf->hash_lut_size;
1841         uint16_t idx, shift;
1842         uint8_t mask;
1843
1844         if (reta_size != lut_size ||
1845                 reta_size > ETH_RSS_RETA_SIZE_512) {
1846                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1847                         "(%d) doesn't match the number hardware can supported "
1848                                         "(%d)\n", reta_size, lut_size);
1849                 return -EINVAL;
1850         }
1851
1852         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1853                 idx = i / RTE_RETA_GROUP_SIZE;
1854                 shift = i % RTE_RETA_GROUP_SIZE;
1855                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1856                                                 I40E_4_BIT_MASK);
1857                 if (!mask)
1858                         continue;
1859                 if (mask == I40E_4_BIT_MASK)
1860                         l = 0;
1861                 else
1862                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1863                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1864                         if (mask & (0x1 << j))
1865                                 lut |= reta_conf[idx].reta[shift + j] <<
1866                                                         (CHAR_BIT * j);
1867                         else
1868                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1869                 }
1870                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1871         }
1872
1873         return 0;
1874 }
1875
1876 static int
1877 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1878                         struct rte_eth_rss_reta_entry64 *reta_conf,
1879                         uint16_t reta_size)
1880 {
1881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         uint32_t lut;
1884         uint16_t i, j, lut_size = pf->hash_lut_size;
1885         uint16_t idx, shift;
1886         uint8_t mask;
1887
1888         if (reta_size != lut_size ||
1889                 reta_size > ETH_RSS_RETA_SIZE_512) {
1890                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1891                         "(%d) doesn't match the number hardware can supported "
1892                                         "(%d)\n", reta_size, lut_size);
1893                 return -EINVAL;
1894         }
1895
1896         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1897                 idx = i / RTE_RETA_GROUP_SIZE;
1898                 shift = i % RTE_RETA_GROUP_SIZE;
1899                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1900                                                 I40E_4_BIT_MASK);
1901                 if (!mask)
1902                         continue;
1903
1904                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1905                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1906                         if (mask & (0x1 << j))
1907                                 reta_conf[idx].reta[shift] = ((lut >>
1908                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1909                 }
1910         }
1911
1912         return 0;
1913 }
1914
1915 /**
1916  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1917  * @hw:   pointer to the HW structure
1918  * @mem:  pointer to mem struct to fill out
1919  * @size: size of memory requested
1920  * @alignment: what to align the allocation to
1921  **/
1922 enum i40e_status_code
1923 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1924                         struct i40e_dma_mem *mem,
1925                         u64 size,
1926                         u32 alignment)
1927 {
1928         static uint64_t id = 0;
1929         const struct rte_memzone *mz = NULL;
1930         char z_name[RTE_MEMZONE_NAMESIZE];
1931
1932         if (!mem)
1933                 return I40E_ERR_PARAM;
1934
1935         id++;
1936         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1937 #ifdef RTE_LIBRTE_XEN_DOM0
1938         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1939                                                         RTE_PGSIZE_2M);
1940 #else
1941         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1942 #endif
1943         if (!mz)
1944                 return I40E_ERR_NO_MEMORY;
1945
1946         mem->id = id;
1947         mem->size = size;
1948         mem->va = mz->addr;
1949 #ifdef RTE_LIBRTE_XEN_DOM0
1950         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1951 #else
1952         mem->pa = mz->phys_addr;
1953 #endif
1954
1955         return I40E_SUCCESS;
1956 }
1957
1958 /**
1959  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1960  * @hw:   pointer to the HW structure
1961  * @mem:  ptr to mem struct to free
1962  **/
1963 enum i40e_status_code
1964 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1965                     struct i40e_dma_mem *mem)
1966 {
1967         if (!mem || !mem->va)
1968                 return I40E_ERR_PARAM;
1969
1970         mem->va = NULL;
1971         mem->pa = (u64)0;
1972
1973         return I40E_SUCCESS;
1974 }
1975
1976 /**
1977  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1978  * @hw:   pointer to the HW structure
1979  * @mem:  pointer to mem struct to fill out
1980  * @size: size of memory requested
1981  **/
1982 enum i40e_status_code
1983 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1984                          struct i40e_virt_mem *mem,
1985                          u32 size)
1986 {
1987         if (!mem)
1988                 return I40E_ERR_PARAM;
1989
1990         mem->size = size;
1991         mem->va = rte_zmalloc("i40e", size, 0);
1992
1993         if (mem->va)
1994                 return I40E_SUCCESS;
1995         else
1996                 return I40E_ERR_NO_MEMORY;
1997 }
1998
1999 /**
2000  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2001  * @hw:   pointer to the HW structure
2002  * @mem:  pointer to mem struct to free
2003  **/
2004 enum i40e_status_code
2005 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2006                      struct i40e_virt_mem *mem)
2007 {
2008         if (!mem)
2009                 return I40E_ERR_PARAM;
2010
2011         rte_free(mem->va);
2012         mem->va = NULL;
2013
2014         return I40E_SUCCESS;
2015 }
2016
2017 void
2018 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2019 {
2020         rte_spinlock_init(&sp->spinlock);
2021 }
2022
2023 void
2024 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2025 {
2026         rte_spinlock_lock(&sp->spinlock);
2027 }
2028
2029 void
2030 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2031 {
2032         rte_spinlock_unlock(&sp->spinlock);
2033 }
2034
2035 void
2036 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2037 {
2038         return;
2039 }
2040
2041 /**
2042  * Get the hardware capabilities, which will be parsed
2043  * and saved into struct i40e_hw.
2044  */
2045 static int
2046 i40e_get_cap(struct i40e_hw *hw)
2047 {
2048         struct i40e_aqc_list_capabilities_element_resp *buf;
2049         uint16_t len, size = 0;
2050         int ret;
2051
2052         /* Calculate a huge enough buff for saving response data temporarily */
2053         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2054                                                 I40E_MAX_CAP_ELE_NUM;
2055         buf = rte_zmalloc("i40e", len, 0);
2056         if (!buf) {
2057                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2058                 return I40E_ERR_NO_MEMORY;
2059         }
2060
2061         /* Get, parse the capabilities and save it to hw */
2062         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2063                         i40e_aqc_opc_list_func_capabilities, NULL);
2064         if (ret != I40E_SUCCESS)
2065                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2066
2067         /* Free the temporary buffer after being used */
2068         rte_free(buf);
2069
2070         return ret;
2071 }
2072
2073 static int
2074 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2075 {
2076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2078         uint16_t sum_queues = 0, sum_vsis, left_queues;
2079
2080         /* First check if FW support SRIOV */
2081         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2082                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2083                 return -EINVAL;
2084         }
2085
2086         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2087         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2088         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2089         /* Allocate queues for pf */
2090         if (hw->func_caps.rss) {
2091                 pf->flags |= I40E_FLAG_RSS;
2092                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2093                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2094                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2095         } else
2096                 pf->lan_nb_qps = 1;
2097         sum_queues = pf->lan_nb_qps;
2098         /* Default VSI is not counted in */
2099         sum_vsis = 0;
2100         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2101
2102         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2103                 pf->flags |= I40E_FLAG_SRIOV;
2104                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2105                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2106                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2107                                      "max supported %u.",
2108                                      dev->pci_dev->max_vfs,
2109                                      hw->func_caps.num_vfs);
2110                         return -EINVAL;
2111                 }
2112                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2113                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2114                                      "max support %u queues.",
2115                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2116                         return -EINVAL;
2117                 }
2118                 pf->vf_num = dev->pci_dev->max_vfs;
2119                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2120                 sum_vsis   += pf->vf_num;
2121                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2122                              pf->vf_num, pf->vf_nb_qps);
2123         } else
2124                 pf->vf_num = 0;
2125
2126         if (hw->func_caps.vmdq) {
2127                 pf->flags |= I40E_FLAG_VMDQ;
2128                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2129                 pf->max_nb_vmdq_vsi = 1;
2130                 /*
2131                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2132                  * later.
2133                  */
2134                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2135                 sum_vsis += pf->max_nb_vmdq_vsi;
2136         } else {
2137                 pf->vmdq_nb_qps = 0;
2138                 pf->max_nb_vmdq_vsi = 0;
2139         }
2140         pf->nb_cfg_vmdq_vsi = 0;
2141
2142         if (hw->func_caps.fd) {
2143                 pf->flags |= I40E_FLAG_FDIR;
2144                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2145                 /**
2146                  * Each flow director consumes one VSI and one queue,
2147                  * but can't calculate out predictably here.
2148                  */
2149         }
2150
2151         if (sum_vsis > pf->max_num_vsi ||
2152                 sum_queues > hw->func_caps.num_rx_qp) {
2153                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2154                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2155                              pf->max_num_vsi, sum_vsis);
2156                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2157                              hw->func_caps.num_rx_qp, sum_queues);
2158                 return -EINVAL;
2159         }
2160
2161         /* Adjust VMDQ setting to support as many VMs as possible */
2162         if (pf->flags & I40E_FLAG_VMDQ) {
2163                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2164
2165                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2166                                         pf->max_num_vsi - sum_vsis);
2167
2168                 /* Limit the max VMDQ number that rte_ether that can support  */
2169                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2170                                         ETH_64_POOLS - 1);
2171
2172                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2173                                 pf->max_nb_vmdq_vsi);
2174                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2175         }
2176
2177         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2178          * cause */
2179         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2180                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2181                              sum_vsis, hw->func_caps.num_msix_vectors);
2182                 return -EINVAL;
2183         }
2184         return I40E_SUCCESS;
2185 }
2186
2187 static int
2188 i40e_pf_get_switch_config(struct i40e_pf *pf)
2189 {
2190         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2191         struct i40e_aqc_get_switch_config_resp *switch_config;
2192         struct i40e_aqc_switch_config_element_resp *element;
2193         uint16_t start_seid = 0, num_reported;
2194         int ret;
2195
2196         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2197                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2198         if (!switch_config) {
2199                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2200                 return -ENOMEM;
2201         }
2202
2203         /* Get the switch configurations */
2204         ret = i40e_aq_get_switch_config(hw, switch_config,
2205                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2206         if (ret != I40E_SUCCESS) {
2207                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2208                 goto fail;
2209         }
2210         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2211         if (num_reported != 1) { /* The number should be 1 */
2212                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2213                 goto fail;
2214         }
2215
2216         /* Parse the switch configuration elements */
2217         element = &(switch_config->element[0]);
2218         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2219                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2220                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2221         } else
2222                 PMD_DRV_LOG(INFO, "Unknown element type");
2223
2224 fail:
2225         rte_free(switch_config);
2226
2227         return ret;
2228 }
2229
2230 static int
2231 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2232                         uint32_t num)
2233 {
2234         struct pool_entry *entry;
2235
2236         if (pool == NULL || num == 0)
2237                 return -EINVAL;
2238
2239         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2240         if (entry == NULL) {
2241                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2242                 return -ENOMEM;
2243         }
2244
2245         /* queue heap initialize */
2246         pool->num_free = num;
2247         pool->num_alloc = 0;
2248         pool->base = base;
2249         LIST_INIT(&pool->alloc_list);
2250         LIST_INIT(&pool->free_list);
2251
2252         /* Initialize element  */
2253         entry->base = 0;
2254         entry->len = num;
2255
2256         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2257         return 0;
2258 }
2259
2260 static void
2261 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2262 {
2263         struct pool_entry *entry;
2264
2265         if (pool == NULL)
2266                 return;
2267
2268         LIST_FOREACH(entry, &pool->alloc_list, next) {
2269                 LIST_REMOVE(entry, next);
2270                 rte_free(entry);
2271         }
2272
2273         LIST_FOREACH(entry, &pool->free_list, next) {
2274                 LIST_REMOVE(entry, next);
2275                 rte_free(entry);
2276         }
2277
2278         pool->num_free = 0;
2279         pool->num_alloc = 0;
2280         pool->base = 0;
2281         LIST_INIT(&pool->alloc_list);
2282         LIST_INIT(&pool->free_list);
2283 }
2284
2285 static int
2286 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2287                        uint32_t base)
2288 {
2289         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2290         uint32_t pool_offset;
2291         int insert;
2292
2293         if (pool == NULL) {
2294                 PMD_DRV_LOG(ERR, "Invalid parameter");
2295                 return -EINVAL;
2296         }
2297
2298         pool_offset = base - pool->base;
2299         /* Lookup in alloc list */
2300         LIST_FOREACH(entry, &pool->alloc_list, next) {
2301                 if (entry->base == pool_offset) {
2302                         valid_entry = entry;
2303                         LIST_REMOVE(entry, next);
2304                         break;
2305                 }
2306         }
2307
2308         /* Not find, return */
2309         if (valid_entry == NULL) {
2310                 PMD_DRV_LOG(ERR, "Failed to find entry");
2311                 return -EINVAL;
2312         }
2313
2314         /**
2315          * Found it, move it to free list  and try to merge.
2316          * In order to make merge easier, always sort it by qbase.
2317          * Find adjacent prev and last entries.
2318          */
2319         prev = next = NULL;
2320         LIST_FOREACH(entry, &pool->free_list, next) {
2321                 if (entry->base > valid_entry->base) {
2322                         next = entry;
2323                         break;
2324                 }
2325                 prev = entry;
2326         }
2327
2328         insert = 0;
2329         /* Try to merge with next one*/
2330         if (next != NULL) {
2331                 /* Merge with next one */
2332                 if (valid_entry->base + valid_entry->len == next->base) {
2333                         next->base = valid_entry->base;
2334                         next->len += valid_entry->len;
2335                         rte_free(valid_entry);
2336                         valid_entry = next;
2337                         insert = 1;
2338                 }
2339         }
2340
2341         if (prev != NULL) {
2342                 /* Merge with previous one */
2343                 if (prev->base + prev->len == valid_entry->base) {
2344                         prev->len += valid_entry->len;
2345                         /* If it merge with next one, remove next node */
2346                         if (insert == 1) {
2347                                 LIST_REMOVE(valid_entry, next);
2348                                 rte_free(valid_entry);
2349                         } else {
2350                                 rte_free(valid_entry);
2351                                 insert = 1;
2352                         }
2353                 }
2354         }
2355
2356         /* Not find any entry to merge, insert */
2357         if (insert == 0) {
2358                 if (prev != NULL)
2359                         LIST_INSERT_AFTER(prev, valid_entry, next);
2360                 else if (next != NULL)
2361                         LIST_INSERT_BEFORE(next, valid_entry, next);
2362                 else /* It's empty list, insert to head */
2363                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2364         }
2365
2366         pool->num_free += valid_entry->len;
2367         pool->num_alloc -= valid_entry->len;
2368
2369         return 0;
2370 }
2371
2372 static int
2373 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2374                        uint16_t num)
2375 {
2376         struct pool_entry *entry, *valid_entry;
2377
2378         if (pool == NULL || num == 0) {
2379                 PMD_DRV_LOG(ERR, "Invalid parameter");
2380                 return -EINVAL;
2381         }
2382
2383         if (pool->num_free < num) {
2384                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2385                             num, pool->num_free);
2386                 return -ENOMEM;
2387         }
2388
2389         valid_entry = NULL;
2390         /* Lookup  in free list and find most fit one */
2391         LIST_FOREACH(entry, &pool->free_list, next) {
2392                 if (entry->len >= num) {
2393                         /* Find best one */
2394                         if (entry->len == num) {
2395                                 valid_entry = entry;
2396                                 break;
2397                         }
2398                         if (valid_entry == NULL || valid_entry->len > entry->len)
2399                                 valid_entry = entry;
2400                 }
2401         }
2402
2403         /* Not find one to satisfy the request, return */
2404         if (valid_entry == NULL) {
2405                 PMD_DRV_LOG(ERR, "No valid entry found");
2406                 return -ENOMEM;
2407         }
2408         /**
2409          * The entry have equal queue number as requested,
2410          * remove it from alloc_list.
2411          */
2412         if (valid_entry->len == num) {
2413                 LIST_REMOVE(valid_entry, next);
2414         } else {
2415                 /**
2416                  * The entry have more numbers than requested,
2417                  * create a new entry for alloc_list and minus its
2418                  * queue base and number in free_list.
2419                  */
2420                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2421                 if (entry == NULL) {
2422                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2423                                     "resource pool");
2424                         return -ENOMEM;
2425                 }
2426                 entry->base = valid_entry->base;
2427                 entry->len = num;
2428                 valid_entry->base += num;
2429                 valid_entry->len -= num;
2430                 valid_entry = entry;
2431         }
2432
2433         /* Insert it into alloc list, not sorted */
2434         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2435
2436         pool->num_free -= valid_entry->len;
2437         pool->num_alloc += valid_entry->len;
2438
2439         return (valid_entry->base + pool->base);
2440 }
2441
2442 /**
2443  * bitmap_is_subset - Check whether src2 is subset of src1
2444  **/
2445 static inline int
2446 bitmap_is_subset(uint8_t src1, uint8_t src2)
2447 {
2448         return !((src1 ^ src2) & src2);
2449 }
2450
2451 static int
2452 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2453 {
2454         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2455
2456         /* If DCB is not supported, only default TC is supported */
2457         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2458                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2459                 return -EINVAL;
2460         }
2461
2462         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2463                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2464                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2465                             enabled_tcmap);
2466                 return -EINVAL;
2467         }
2468         return I40E_SUCCESS;
2469 }
2470
2471 int
2472 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2473                                 struct i40e_vsi_vlan_pvid_info *info)
2474 {
2475         struct i40e_hw *hw;
2476         struct i40e_vsi_context ctxt;
2477         uint8_t vlan_flags = 0;
2478         int ret;
2479
2480         if (vsi == NULL || info == NULL) {
2481                 PMD_DRV_LOG(ERR, "invalid parameters");
2482                 return I40E_ERR_PARAM;
2483         }
2484
2485         if (info->on) {
2486                 vsi->info.pvid = info->config.pvid;
2487                 /**
2488                  * If insert pvid is enabled, only tagged pkts are
2489                  * allowed to be sent out.
2490                  */
2491                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2492                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2493         } else {
2494                 vsi->info.pvid = 0;
2495                 if (info->config.reject.tagged == 0)
2496                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2497
2498                 if (info->config.reject.untagged == 0)
2499                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2500         }
2501         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2502                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2503         vsi->info.port_vlan_flags |= vlan_flags;
2504         vsi->info.valid_sections =
2505                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2506         memset(&ctxt, 0, sizeof(ctxt));
2507         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2508         ctxt.seid = vsi->seid;
2509
2510         hw = I40E_VSI_TO_HW(vsi);
2511         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2512         if (ret != I40E_SUCCESS)
2513                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2514
2515         return ret;
2516 }
2517
2518 static int
2519 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2520 {
2521         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2522         int i, ret;
2523         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2524
2525         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2526         if (ret != I40E_SUCCESS)
2527                 return ret;
2528
2529         if (!vsi->seid) {
2530                 PMD_DRV_LOG(ERR, "seid not valid");
2531                 return -EINVAL;
2532         }
2533
2534         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2535         tc_bw_data.tc_valid_bits = enabled_tcmap;
2536         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2537                 tc_bw_data.tc_bw_credits[i] =
2538                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2539
2540         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2541         if (ret != I40E_SUCCESS) {
2542                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2543                 return ret;
2544         }
2545
2546         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2547                                         sizeof(vsi->info.qs_handle));
2548         return I40E_SUCCESS;
2549 }
2550
2551 static int
2552 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2553                                  struct i40e_aqc_vsi_properties_data *info,
2554                                  uint8_t enabled_tcmap)
2555 {
2556         int ret, total_tc = 0, i;
2557         uint16_t qpnum_per_tc, bsf, qp_idx;
2558
2559         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2560         if (ret != I40E_SUCCESS)
2561                 return ret;
2562
2563         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2564                 if (enabled_tcmap & (1 << i))
2565                         total_tc++;
2566         vsi->enabled_tc = enabled_tcmap;
2567
2568         /* Number of queues per enabled TC */
2569         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2570         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2571         bsf = rte_bsf32(qpnum_per_tc);
2572
2573         /* Adjust the queue number to actual queues that can be applied */
2574         vsi->nb_qps = qpnum_per_tc * total_tc;
2575
2576         /**
2577          * Configure TC and queue mapping parameters, for enabled TC,
2578          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2579          * default queue will serve it.
2580          */
2581         qp_idx = 0;
2582         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2583                 if (vsi->enabled_tc & (1 << i)) {
2584                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2585                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2586                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2587                         qp_idx += qpnum_per_tc;
2588                 } else
2589                         info->tc_mapping[i] = 0;
2590         }
2591
2592         /* Associate queue number with VSI */
2593         if (vsi->type == I40E_VSI_SRIOV) {
2594                 info->mapping_flags |=
2595                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2596                 for (i = 0; i < vsi->nb_qps; i++)
2597                         info->queue_mapping[i] =
2598                                 rte_cpu_to_le_16(vsi->base_queue + i);
2599         } else {
2600                 info->mapping_flags |=
2601                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2602                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2603         }
2604         info->valid_sections =
2605                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2606
2607         return I40E_SUCCESS;
2608 }
2609
2610 static int
2611 i40e_veb_release(struct i40e_veb *veb)
2612 {
2613         struct i40e_vsi *vsi;
2614         struct i40e_hw *hw;
2615
2616         if (veb == NULL || veb->associate_vsi == NULL)
2617                 return -EINVAL;
2618
2619         if (!TAILQ_EMPTY(&veb->head)) {
2620                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2621                 return -EACCES;
2622         }
2623
2624         vsi = veb->associate_vsi;
2625         hw = I40E_VSI_TO_HW(vsi);
2626
2627         vsi->uplink_seid = veb->uplink_seid;
2628         i40e_aq_delete_element(hw, veb->seid, NULL);
2629         rte_free(veb);
2630         vsi->veb = NULL;
2631         return I40E_SUCCESS;
2632 }
2633
2634 /* Setup a veb */
2635 static struct i40e_veb *
2636 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2637 {
2638         struct i40e_veb *veb;
2639         int ret;
2640         struct i40e_hw *hw;
2641
2642         if (NULL == pf || vsi == NULL) {
2643                 PMD_DRV_LOG(ERR, "veb setup failed, "
2644                             "associated VSI shouldn't null");
2645                 return NULL;
2646         }
2647         hw = I40E_PF_TO_HW(pf);
2648
2649         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2650         if (!veb) {
2651                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2652                 goto fail;
2653         }
2654
2655         veb->associate_vsi = vsi;
2656         TAILQ_INIT(&veb->head);
2657         veb->uplink_seid = vsi->uplink_seid;
2658
2659         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2660                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2661
2662         if (ret != I40E_SUCCESS) {
2663                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2664                             hw->aq.asq_last_status);
2665                 goto fail;
2666         }
2667
2668         /* get statistics index */
2669         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2670                                 &veb->stats_idx, NULL, NULL, NULL);
2671         if (ret != I40E_SUCCESS) {
2672                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2673                             hw->aq.asq_last_status);
2674                 goto fail;
2675         }
2676
2677         /* Get VEB bandwidth, to be implemented */
2678         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2679         vsi->uplink_seid = veb->seid;
2680
2681         return veb;
2682 fail:
2683         rte_free(veb);
2684         return NULL;
2685 }
2686
2687 int
2688 i40e_vsi_release(struct i40e_vsi *vsi)
2689 {
2690         struct i40e_pf *pf;
2691         struct i40e_hw *hw;
2692         struct i40e_vsi_list *vsi_list;
2693         int ret;
2694         struct i40e_mac_filter *f;
2695
2696         if (!vsi)
2697                 return I40E_SUCCESS;
2698
2699         pf = I40E_VSI_TO_PF(vsi);
2700         hw = I40E_VSI_TO_HW(vsi);
2701
2702         /* VSI has child to attach, release child first */
2703         if (vsi->veb) {
2704                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2705                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2706                                 return -1;
2707                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2708                 }
2709                 i40e_veb_release(vsi->veb);
2710         }
2711
2712         /* Remove all macvlan filters of the VSI */
2713         i40e_vsi_remove_all_macvlan_filter(vsi);
2714         TAILQ_FOREACH(f, &vsi->mac_list, next)
2715                 rte_free(f);
2716
2717         if (vsi->type != I40E_VSI_MAIN) {
2718                 /* Remove vsi from parent's sibling list */
2719                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2720                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2721                         return I40E_ERR_PARAM;
2722                 }
2723                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2724                                 &vsi->sib_vsi_list, list);
2725
2726                 /* Remove all switch element of the VSI */
2727                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2728                 if (ret != I40E_SUCCESS)
2729                         PMD_DRV_LOG(ERR, "Failed to delete element");
2730         }
2731         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2732
2733         if (vsi->type != I40E_VSI_SRIOV)
2734                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2735         rte_free(vsi);
2736
2737         return I40E_SUCCESS;
2738 }
2739
2740 static int
2741 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2742 {
2743         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2744         struct i40e_aqc_remove_macvlan_element_data def_filter;
2745         struct i40e_mac_filter_info filter;
2746         int ret;
2747
2748         if (vsi->type != I40E_VSI_MAIN)
2749                 return I40E_ERR_CONFIG;
2750         memset(&def_filter, 0, sizeof(def_filter));
2751         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2752                                         ETH_ADDR_LEN);
2753         def_filter.vlan_tag = 0;
2754         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2755                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2756         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2757         if (ret != I40E_SUCCESS) {
2758                 struct i40e_mac_filter *f;
2759                 struct ether_addr *mac;
2760
2761                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2762                             "macvlan filter");
2763                 /* It needs to add the permanent mac into mac list */
2764                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2765                 if (f == NULL) {
2766                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2767                         return I40E_ERR_NO_MEMORY;
2768                 }
2769                 mac = &f->mac_info.mac_addr;
2770                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2771                                 ETH_ADDR_LEN);
2772                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2773                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2774                 vsi->mac_num++;
2775
2776                 return ret;
2777         }
2778         (void)rte_memcpy(&filter.mac_addr,
2779                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2780         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2781         return i40e_vsi_add_mac(vsi, &filter);
2782 }
2783
2784 static int
2785 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2786 {
2787         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2788         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2789         struct i40e_hw *hw = &vsi->adapter->hw;
2790         i40e_status ret;
2791         int i;
2792
2793         memset(&bw_config, 0, sizeof(bw_config));
2794         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2795         if (ret != I40E_SUCCESS) {
2796                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2797                             hw->aq.asq_last_status);
2798                 return ret;
2799         }
2800
2801         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2802         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2803                                         &ets_sla_config, NULL);
2804         if (ret != I40E_SUCCESS) {
2805                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2806                             "configuration %u", hw->aq.asq_last_status);
2807                 return ret;
2808         }
2809
2810         /* Not store the info yet, just print out */
2811         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2812         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2813         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2814                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2815                             ets_sla_config.share_credits[i]);
2816                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2817                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2818                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2819                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2820                             (i * 4));
2821         }
2822
2823         return 0;
2824 }
2825
2826 /* Setup a VSI */
2827 struct i40e_vsi *
2828 i40e_vsi_setup(struct i40e_pf *pf,
2829                enum i40e_vsi_type type,
2830                struct i40e_vsi *uplink_vsi,
2831                uint16_t user_param)
2832 {
2833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2834         struct i40e_vsi *vsi;
2835         struct i40e_mac_filter_info filter;
2836         int ret;
2837         struct i40e_vsi_context ctxt;
2838         struct ether_addr broadcast =
2839                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2840
2841         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2842                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2843                             "VSI link shouldn't be NULL");
2844                 return NULL;
2845         }
2846
2847         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2848                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2849                             "uplink VSI should be NULL");
2850                 return NULL;
2851         }
2852
2853         /* If uplink vsi didn't setup VEB, create one first */
2854         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2855                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2856
2857                 if (NULL == uplink_vsi->veb) {
2858                         PMD_DRV_LOG(ERR, "VEB setup failed");
2859                         return NULL;
2860                 }
2861         }
2862
2863         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2864         if (!vsi) {
2865                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2866                 return NULL;
2867         }
2868         TAILQ_INIT(&vsi->mac_list);
2869         vsi->type = type;
2870         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2871         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2872         vsi->parent_vsi = uplink_vsi;
2873         vsi->user_param = user_param;
2874         /* Allocate queues */
2875         switch (vsi->type) {
2876         case I40E_VSI_MAIN  :
2877                 vsi->nb_qps = pf->lan_nb_qps;
2878                 break;
2879         case I40E_VSI_SRIOV :
2880                 vsi->nb_qps = pf->vf_nb_qps;
2881                 break;
2882         case I40E_VSI_VMDQ2:
2883                 vsi->nb_qps = pf->vmdq_nb_qps;
2884                 break;
2885         case I40E_VSI_FDIR:
2886                 vsi->nb_qps = pf->fdir_nb_qps;
2887                 break;
2888         default:
2889                 goto fail_mem;
2890         }
2891         /*
2892          * The filter status descriptor is reported in rx queue 0,
2893          * while the tx queue for fdir filter programming has no
2894          * such constraints, can be non-zero queues.
2895          * To simplify it, choose FDIR vsi use queue 0 pair.
2896          * To make sure it will use queue 0 pair, queue allocation
2897          * need be done before this function is called
2898          */
2899         if (type != I40E_VSI_FDIR) {
2900                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2901                         if (ret < 0) {
2902                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2903                                                 vsi->seid, ret);
2904                                 goto fail_mem;
2905                         }
2906                         vsi->base_queue = ret;
2907         } else
2908                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2909
2910         /* VF has MSIX interrupt in VF range, don't allocate here */
2911         if (type != I40E_VSI_SRIOV) {
2912                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2913                 if (ret < 0) {
2914                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2915                         goto fail_queue_alloc;
2916                 }
2917                 vsi->msix_intr = ret;
2918         } else
2919                 vsi->msix_intr = 0;
2920         /* Add VSI */
2921         if (type == I40E_VSI_MAIN) {
2922                 /* For main VSI, no need to add since it's default one */
2923                 vsi->uplink_seid = pf->mac_seid;
2924                 vsi->seid = pf->main_vsi_seid;
2925                 /* Bind queues with specific MSIX interrupt */
2926                 /**
2927                  * Needs 2 interrupt at least, one for misc cause which will
2928                  * enabled from OS side, Another for queues binding the
2929                  * interrupt from device side only.
2930                  */
2931
2932                 /* Get default VSI parameters from hardware */
2933                 memset(&ctxt, 0, sizeof(ctxt));
2934                 ctxt.seid = vsi->seid;
2935                 ctxt.pf_num = hw->pf_id;
2936                 ctxt.uplink_seid = vsi->uplink_seid;
2937                 ctxt.vf_num = 0;
2938                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2939                 if (ret != I40E_SUCCESS) {
2940                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2941                         goto fail_msix_alloc;
2942                 }
2943                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2944                         sizeof(struct i40e_aqc_vsi_properties_data));
2945                 vsi->vsi_id = ctxt.vsi_number;
2946                 vsi->info.valid_sections = 0;
2947
2948                 /* Configure tc, enabled TC0 only */
2949                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2950                         I40E_SUCCESS) {
2951                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2952                         goto fail_msix_alloc;
2953                 }
2954
2955                 /* TC, queue mapping */
2956                 memset(&ctxt, 0, sizeof(ctxt));
2957                 vsi->info.valid_sections |=
2958                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2959                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2960                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2961                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2962                         sizeof(struct i40e_aqc_vsi_properties_data));
2963                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2964                                                 I40E_DEFAULT_TCMAP);
2965                 if (ret != I40E_SUCCESS) {
2966                         PMD_DRV_LOG(ERR, "Failed to configure "
2967                                     "TC queue mapping");
2968                         goto fail_msix_alloc;
2969                 }
2970                 ctxt.seid = vsi->seid;
2971                 ctxt.pf_num = hw->pf_id;
2972                 ctxt.uplink_seid = vsi->uplink_seid;
2973                 ctxt.vf_num = 0;
2974
2975                 /* Update VSI parameters */
2976                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2977                 if (ret != I40E_SUCCESS) {
2978                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2979                         goto fail_msix_alloc;
2980                 }
2981
2982                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2983                                                 sizeof(vsi->info.tc_mapping));
2984                 (void)rte_memcpy(&vsi->info.queue_mapping,
2985                                 &ctxt.info.queue_mapping,
2986                         sizeof(vsi->info.queue_mapping));
2987                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2988                 vsi->info.valid_sections = 0;
2989
2990                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2991                                 ETH_ADDR_LEN);
2992
2993                 /**
2994                  * Updating default filter settings are necessary to prevent
2995                  * reception of tagged packets.
2996                  * Some old firmware configurations load a default macvlan
2997                  * filter which accepts both tagged and untagged packets.
2998                  * The updating is to use a normal filter instead if needed.
2999                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3000                  * The firmware with correct configurations load the default
3001                  * macvlan filter which is expected and cannot be removed.
3002                  */
3003                 i40e_update_default_filter_setting(vsi);
3004         } else if (type == I40E_VSI_SRIOV) {
3005                 memset(&ctxt, 0, sizeof(ctxt));
3006                 /**
3007                  * For other VSI, the uplink_seid equals to uplink VSI's
3008                  * uplink_seid since they share same VEB
3009                  */
3010                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3011                 ctxt.pf_num = hw->pf_id;
3012                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3013                 ctxt.uplink_seid = vsi->uplink_seid;
3014                 ctxt.connection_type = 0x1;
3015                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3016
3017                 /* Configure switch ID */
3018                 ctxt.info.valid_sections |=
3019                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3020                 ctxt.info.switch_id =
3021                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3022                 /* Configure port/vlan */
3023                 ctxt.info.valid_sections |=
3024                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3025                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3026                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3027                                                 I40E_DEFAULT_TCMAP);
3028                 if (ret != I40E_SUCCESS) {
3029                         PMD_DRV_LOG(ERR, "Failed to configure "
3030                                     "TC queue mapping");
3031                         goto fail_msix_alloc;
3032                 }
3033                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3034                 ctxt.info.valid_sections |=
3035                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3036                 /**
3037                  * Since VSI is not created yet, only configure parameter,
3038                  * will add vsi below.
3039                  */
3040         } else if (type == I40E_VSI_VMDQ2) {
3041                 memset(&ctxt, 0, sizeof(ctxt));
3042                 /*
3043                  * For other VSI, the uplink_seid equals to uplink VSI's
3044                  * uplink_seid since they share same VEB
3045                  */
3046                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3047                 ctxt.pf_num = hw->pf_id;
3048                 ctxt.vf_num = 0;
3049                 ctxt.uplink_seid = vsi->uplink_seid;
3050                 ctxt.connection_type = 0x1;
3051                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3052
3053                 ctxt.info.valid_sections |=
3054                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3055                 /* user_param carries flag to enable loop back */
3056                 if (user_param) {
3057                         ctxt.info.switch_id =
3058                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3059                         ctxt.info.switch_id |=
3060                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3061                 }
3062
3063                 /* Configure port/vlan */
3064                 ctxt.info.valid_sections |=
3065                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3066                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3067                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3068                                                 I40E_DEFAULT_TCMAP);
3069                 if (ret != I40E_SUCCESS) {
3070                         PMD_DRV_LOG(ERR, "Failed to configure "
3071                                         "TC queue mapping");
3072                         goto fail_msix_alloc;
3073                 }
3074                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3075                 ctxt.info.valid_sections |=
3076                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3077         } else if (type == I40E_VSI_FDIR) {
3078                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3079                 ctxt.pf_num = hw->pf_id;
3080                 ctxt.vf_num = 0;
3081                 ctxt.uplink_seid = vsi->uplink_seid;
3082                 ctxt.connection_type = 0x1;     /* regular data port */
3083                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3084                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3085                                                 I40E_DEFAULT_TCMAP);
3086                 if (ret != I40E_SUCCESS) {
3087                         PMD_DRV_LOG(ERR, "Failed to configure "
3088                                         "TC queue mapping.");
3089                         goto fail_msix_alloc;
3090                 }
3091                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3092                 ctxt.info.valid_sections |=
3093                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3094         } else {
3095                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3096                 goto fail_msix_alloc;
3097         }
3098
3099         if (vsi->type != I40E_VSI_MAIN) {
3100                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3101                 if (ret) {
3102                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3103                                     hw->aq.asq_last_status);
3104                         goto fail_msix_alloc;
3105                 }
3106                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3107                 vsi->info.valid_sections = 0;
3108                 vsi->seid = ctxt.seid;
3109                 vsi->vsi_id = ctxt.vsi_number;
3110                 vsi->sib_vsi_list.vsi = vsi;
3111                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3112                                 &vsi->sib_vsi_list, list);
3113         }
3114
3115         /* MAC/VLAN configuration */
3116         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3117         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3118
3119         ret = i40e_vsi_add_mac(vsi, &filter);
3120         if (ret != I40E_SUCCESS) {
3121                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3122                 goto fail_msix_alloc;
3123         }
3124
3125         /* Get VSI BW information */
3126         i40e_vsi_dump_bw_config(vsi);
3127         return vsi;
3128 fail_msix_alloc:
3129         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3130 fail_queue_alloc:
3131         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3132 fail_mem:
3133         rte_free(vsi);
3134         return NULL;
3135 }
3136
3137 /* Configure vlan stripping on or off */
3138 int
3139 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3140 {
3141         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3142         struct i40e_vsi_context ctxt;
3143         uint8_t vlan_flags;
3144         int ret = I40E_SUCCESS;
3145
3146         /* Check if it has been already on or off */
3147         if (vsi->info.valid_sections &
3148                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3149                 if (on) {
3150                         if ((vsi->info.port_vlan_flags &
3151                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3152                                 return 0; /* already on */
3153                 } else {
3154                         if ((vsi->info.port_vlan_flags &
3155                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3156                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3157                                 return 0; /* already off */
3158                 }
3159         }
3160
3161         if (on)
3162                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3163         else
3164                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3165         vsi->info.valid_sections =
3166                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3167         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3168         vsi->info.port_vlan_flags |= vlan_flags;
3169         ctxt.seid = vsi->seid;
3170         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3171         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3172         if (ret)
3173                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3174                             on ? "enable" : "disable");
3175
3176         return ret;
3177 }
3178
3179 static int
3180 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3181 {
3182         struct rte_eth_dev_data *data = dev->data;
3183         int ret;
3184
3185         /* Apply vlan offload setting */
3186         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3187
3188         /* Apply double-vlan setting, not implemented yet */
3189
3190         /* Apply pvid setting */
3191         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3192                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3193         if (ret)
3194                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3195
3196         return ret;
3197 }
3198
3199 static int
3200 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3201 {
3202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3203
3204         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3205 }
3206
3207 static int
3208 i40e_update_flow_control(struct i40e_hw *hw)
3209 {
3210 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3211         struct i40e_link_status link_status;
3212         uint32_t rxfc = 0, txfc = 0, reg;
3213         uint8_t an_info;
3214         int ret;
3215
3216         memset(&link_status, 0, sizeof(link_status));
3217         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3218         if (ret != I40E_SUCCESS) {
3219                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3220                 goto write_reg; /* Disable flow control */
3221         }
3222
3223         an_info = hw->phy.link_info.an_info;
3224         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3225                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3226                 ret = I40E_ERR_NOT_READY;
3227                 goto write_reg; /* Disable flow control */
3228         }
3229         /**
3230          * If link auto negotiation is enabled, flow control needs to
3231          * be configured according to it
3232          */
3233         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3234         case I40E_LINK_PAUSE_RXTX:
3235                 rxfc = 1;
3236                 txfc = 1;
3237                 hw->fc.current_mode = I40E_FC_FULL;
3238                 break;
3239         case I40E_AQ_LINK_PAUSE_RX:
3240                 rxfc = 1;
3241                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3242                 break;
3243         case I40E_AQ_LINK_PAUSE_TX:
3244                 txfc = 1;
3245                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3246                 break;
3247         default:
3248                 hw->fc.current_mode = I40E_FC_NONE;
3249                 break;
3250         }
3251
3252 write_reg:
3253         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3254                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3255         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3256         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3257         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3258         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3259
3260         return ret;
3261 }
3262
3263 /* PF setup */
3264 static int
3265 i40e_pf_setup(struct i40e_pf *pf)
3266 {
3267         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3268         struct i40e_filter_control_settings settings;
3269         struct i40e_vsi *vsi;
3270         int ret;
3271
3272         /* Clear all stats counters */
3273         pf->offset_loaded = FALSE;
3274         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3275         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3276
3277         ret = i40e_pf_get_switch_config(pf);
3278         if (ret != I40E_SUCCESS) {
3279                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3280                 return ret;
3281         }
3282         if (pf->flags & I40E_FLAG_FDIR) {
3283                 /* make queue allocated first, let FDIR use queue pair 0*/
3284                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3285                 if (ret != I40E_FDIR_QUEUE_ID) {
3286                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3287                                     " ret =%d", ret);
3288                         pf->flags &= ~I40E_FLAG_FDIR;
3289                 }
3290         }
3291         /*  main VSI setup */
3292         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3293         if (!vsi) {
3294                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3295                 return I40E_ERR_NOT_READY;
3296         }
3297         pf->main_vsi = vsi;
3298
3299         /* setup FDIR after main vsi created.*/
3300         if (pf->flags & I40E_FLAG_FDIR) {
3301                 ret = i40e_fdir_setup(pf);
3302                 if (ret != I40E_SUCCESS) {
3303                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
3304                         pf->flags &= ~I40E_FLAG_FDIR;
3305                 }
3306         }
3307
3308         /* Configure filter control */
3309         memset(&settings, 0, sizeof(settings));
3310         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3311                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3312         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3313                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3314         else {
3315                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3316                                                 hw->func_caps.rss_table_size);
3317                 return I40E_ERR_PARAM;
3318         }
3319         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3320                         "size: %u\n", hw->func_caps.rss_table_size);
3321         pf->hash_lut_size = hw->func_caps.rss_table_size;
3322
3323         /* Enable ethtype and macvlan filters */
3324         settings.enable_ethtype = TRUE;
3325         settings.enable_macvlan = TRUE;
3326         ret = i40e_set_filter_control(hw, &settings);
3327         if (ret)
3328                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3329                                                                 ret);
3330
3331         /* Update flow control according to the auto negotiation */
3332         i40e_update_flow_control(hw);
3333
3334         return I40E_SUCCESS;
3335 }
3336
3337 int
3338 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3339 {
3340         uint32_t reg;
3341         uint16_t j;
3342
3343         /**
3344          * Set or clear TX Queue Disable flags,
3345          * which is required by hardware.
3346          */
3347         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3348         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3349
3350         /* Wait until the request is finished */
3351         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3352                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3353                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3354                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3355                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3356                                                         & 0x1))) {
3357                         break;
3358                 }
3359         }
3360         if (on) {
3361                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3362                         return I40E_SUCCESS; /* already on, skip next steps */
3363
3364                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3365                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3366         } else {
3367                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3368                         return I40E_SUCCESS; /* already off, skip next steps */
3369                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3370         }
3371         /* Write the register */
3372         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3373         /* Check the result */
3374         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3375                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3376                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3377                 if (on) {
3378                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3379                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3380                                 break;
3381                 } else {
3382                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3383                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3384                                 break;
3385                 }
3386         }
3387         /* Check if it is timeout */
3388         if (j >= I40E_CHK_Q_ENA_COUNT) {
3389                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3390                             (on ? "enable" : "disable"), q_idx);
3391                 return I40E_ERR_TIMEOUT;
3392         }
3393
3394         return I40E_SUCCESS;
3395 }
3396
3397 /* Swith on or off the tx queues */
3398 static int
3399 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3400 {
3401         struct rte_eth_dev_data *dev_data = pf->dev_data;
3402         struct i40e_tx_queue *txq;
3403         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3404         uint16_t i;
3405         int ret;
3406
3407         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3408                 txq = dev_data->tx_queues[i];
3409                 /* Don't operate the queue if not configured or
3410                  * if starting only per queue */
3411                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3412                         continue;
3413                 if (on)
3414                         ret = i40e_dev_tx_queue_start(dev, i);
3415                 else
3416                         ret = i40e_dev_tx_queue_stop(dev, i);
3417                 if ( ret != I40E_SUCCESS)
3418                         return ret;
3419         }
3420
3421         return I40E_SUCCESS;
3422 }
3423
3424 int
3425 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3426 {
3427         uint32_t reg;
3428         uint16_t j;
3429
3430         /* Wait until the request is finished */
3431         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3432                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3433                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3434                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3435                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3436                         break;
3437         }
3438
3439         if (on) {
3440                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3441                         return I40E_SUCCESS; /* Already on, skip next steps */
3442                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3443         } else {
3444                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3445                         return I40E_SUCCESS; /* Already off, skip next steps */
3446                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3447         }
3448
3449         /* Write the register */
3450         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3451         /* Check the result */
3452         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3453                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3454                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3455                 if (on) {
3456                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3457                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3458                                 break;
3459                 } else {
3460                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3461                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3462                                 break;
3463                 }
3464         }
3465
3466         /* Check if it is timeout */
3467         if (j >= I40E_CHK_Q_ENA_COUNT) {
3468                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3469                             (on ? "enable" : "disable"), q_idx);
3470                 return I40E_ERR_TIMEOUT;
3471         }
3472
3473         return I40E_SUCCESS;
3474 }
3475 /* Switch on or off the rx queues */
3476 static int
3477 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3478 {
3479         struct rte_eth_dev_data *dev_data = pf->dev_data;
3480         struct i40e_rx_queue *rxq;
3481         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3482         uint16_t i;
3483         int ret;
3484
3485         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3486                 rxq = dev_data->rx_queues[i];
3487                 /* Don't operate the queue if not configured or
3488                  * if starting only per queue */
3489                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3490                         continue;
3491                 if (on)
3492                         ret = i40e_dev_rx_queue_start(dev, i);
3493                 else
3494                         ret = i40e_dev_rx_queue_stop(dev, i);
3495                 if (ret != I40E_SUCCESS)
3496                         return ret;
3497         }
3498
3499         return I40E_SUCCESS;
3500 }
3501
3502 /* Switch on or off all the rx/tx queues */
3503 int
3504 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3505 {
3506         int ret;
3507
3508         if (on) {
3509                 /* enable rx queues before enabling tx queues */
3510                 ret = i40e_dev_switch_rx_queues(pf, on);
3511                 if (ret) {
3512                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3513                         return ret;
3514                 }
3515                 ret = i40e_dev_switch_tx_queues(pf, on);
3516         } else {
3517                 /* Stop tx queues before stopping rx queues */
3518                 ret = i40e_dev_switch_tx_queues(pf, on);
3519                 if (ret) {
3520                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3521                         return ret;
3522                 }
3523                 ret = i40e_dev_switch_rx_queues(pf, on);
3524         }
3525
3526         return ret;
3527 }
3528
3529 /* Initialize VSI for TX */
3530 static int
3531 i40e_dev_tx_init(struct i40e_pf *pf)
3532 {
3533         struct rte_eth_dev_data *data = pf->dev_data;
3534         uint16_t i;
3535         uint32_t ret = I40E_SUCCESS;
3536         struct i40e_tx_queue *txq;
3537
3538         for (i = 0; i < data->nb_tx_queues; i++) {
3539                 txq = data->tx_queues[i];
3540                 if (!txq || !txq->q_set)
3541                         continue;
3542                 ret = i40e_tx_queue_init(txq);
3543                 if (ret != I40E_SUCCESS)
3544                         break;
3545         }
3546
3547         return ret;
3548 }
3549
3550 /* Initialize VSI for RX */
3551 static int
3552 i40e_dev_rx_init(struct i40e_pf *pf)
3553 {
3554         struct rte_eth_dev_data *data = pf->dev_data;
3555         int ret = I40E_SUCCESS;
3556         uint16_t i;
3557         struct i40e_rx_queue *rxq;
3558
3559         i40e_pf_config_mq_rx(pf);
3560         for (i = 0; i < data->nb_rx_queues; i++) {
3561                 rxq = data->rx_queues[i];
3562                 if (!rxq || !rxq->q_set)
3563                         continue;
3564
3565                 ret = i40e_rx_queue_init(rxq);
3566                 if (ret != I40E_SUCCESS) {
3567                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3568                                     "initialization");
3569                         break;
3570                 }
3571         }
3572
3573         return ret;
3574 }
3575
3576 static int
3577 i40e_dev_rxtx_init(struct i40e_pf *pf)
3578 {
3579         int err;
3580
3581         err = i40e_dev_tx_init(pf);
3582         if (err) {
3583                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3584                 return err;
3585         }
3586         err = i40e_dev_rx_init(pf);
3587         if (err) {
3588                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3589                 return err;
3590         }
3591
3592         return err;
3593 }
3594
3595 static int
3596 i40e_vmdq_setup(struct rte_eth_dev *dev)
3597 {
3598         struct rte_eth_conf *conf = &dev->data->dev_conf;
3599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3600         int i, err, conf_vsis, j, loop;
3601         struct i40e_vsi *vsi;
3602         struct i40e_vmdq_info *vmdq_info;
3603         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3604         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3605
3606         /*
3607          * Disable interrupt to avoid message from VF. Furthermore, it will
3608          * avoid race condition in VSI creation/destroy.
3609          */
3610         i40e_pf_disable_irq0(hw);
3611
3612         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3613                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3614                 return -ENOTSUP;
3615         }
3616
3617         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3618         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3619                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3620                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3621                         pf->max_nb_vmdq_vsi);
3622                 return -ENOTSUP;
3623         }
3624
3625         if (pf->vmdq != NULL) {
3626                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3627                 return 0;
3628         }
3629
3630         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3631                                 sizeof(*vmdq_info) * conf_vsis, 0);
3632
3633         if (pf->vmdq == NULL) {
3634                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3635                 return -ENOMEM;
3636         }
3637
3638         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3639
3640         /* Create VMDQ VSI */
3641         for (i = 0; i < conf_vsis; i++) {
3642                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3643                                 vmdq_conf->enable_loop_back);
3644                 if (vsi == NULL) {
3645                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3646                         err = -1;
3647                         goto err_vsi_setup;
3648                 }
3649                 vmdq_info = &pf->vmdq[i];
3650                 vmdq_info->pf = pf;
3651                 vmdq_info->vsi = vsi;
3652         }
3653         pf->nb_cfg_vmdq_vsi = conf_vsis;
3654
3655         /* Configure Vlan */
3656         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3657         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3658                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3659                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3660                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3661                                         vmdq_conf->pool_map[i].vlan_id, j);
3662
3663                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3664                                                 vmdq_conf->pool_map[i].vlan_id);
3665                                 if (err) {
3666                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3667                                         err = -1;
3668                                         goto err_vsi_setup;
3669                                 }
3670                         }
3671                 }
3672         }
3673
3674         i40e_pf_enable_irq0(hw);
3675
3676         return 0;
3677
3678 err_vsi_setup:
3679         for (i = 0; i < conf_vsis; i++)
3680                 if (pf->vmdq[i].vsi == NULL)
3681                         break;
3682                 else
3683                         i40e_vsi_release(pf->vmdq[i].vsi);
3684
3685         rte_free(pf->vmdq);
3686         pf->vmdq = NULL;
3687         i40e_pf_enable_irq0(hw);
3688         return err;
3689 }
3690
3691 static void
3692 i40e_stat_update_32(struct i40e_hw *hw,
3693                    uint32_t reg,
3694                    bool offset_loaded,
3695                    uint64_t *offset,
3696                    uint64_t *stat)
3697 {
3698         uint64_t new_data;
3699
3700         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3701         if (!offset_loaded)
3702                 *offset = new_data;
3703
3704         if (new_data >= *offset)
3705                 *stat = (uint64_t)(new_data - *offset);
3706         else
3707                 *stat = (uint64_t)((new_data +
3708                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3709 }
3710
3711 static void
3712 i40e_stat_update_48(struct i40e_hw *hw,
3713                    uint32_t hireg,
3714                    uint32_t loreg,
3715                    bool offset_loaded,
3716                    uint64_t *offset,
3717                    uint64_t *stat)
3718 {
3719         uint64_t new_data;
3720
3721         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3722         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3723                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3724
3725         if (!offset_loaded)
3726                 *offset = new_data;
3727
3728         if (new_data >= *offset)
3729                 *stat = new_data - *offset;
3730         else
3731                 *stat = (uint64_t)((new_data +
3732                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3733
3734         *stat &= I40E_48_BIT_MASK;
3735 }
3736
3737 /* Disable IRQ0 */
3738 void
3739 i40e_pf_disable_irq0(struct i40e_hw *hw)
3740 {
3741         /* Disable all interrupt types */
3742         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3743         I40E_WRITE_FLUSH(hw);
3744 }
3745
3746 /* Enable IRQ0 */
3747 void
3748 i40e_pf_enable_irq0(struct i40e_hw *hw)
3749 {
3750         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3751                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3752                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3753                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3754         I40E_WRITE_FLUSH(hw);
3755 }
3756
3757 static void
3758 i40e_pf_config_irq0(struct i40e_hw *hw)
3759 {
3760         /* read pending request and disable first */
3761         i40e_pf_disable_irq0(hw);
3762         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3763         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3764                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3765
3766         /* Link no queues with irq0 */
3767         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3768                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3769 }
3770
3771 static void
3772 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3773 {
3774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3776         int i;
3777         uint16_t abs_vf_id;
3778         uint32_t index, offset, val;
3779
3780         if (!pf->vfs)
3781                 return;
3782         /**
3783          * Try to find which VF trigger a reset, use absolute VF id to access
3784          * since the reg is global register.
3785          */
3786         for (i = 0; i < pf->vf_num; i++) {
3787                 abs_vf_id = hw->func_caps.vf_base_id + i;
3788                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3789                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3790                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3791                 /* VFR event occured */
3792                 if (val & (0x1 << offset)) {
3793                         int ret;
3794
3795                         /* Clear the event first */
3796                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3797                                                         (0x1 << offset));
3798                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3799                         /**
3800                          * Only notify a VF reset event occured,
3801                          * don't trigger another SW reset
3802                          */
3803                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3804                         if (ret != I40E_SUCCESS)
3805                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3806                 }
3807         }
3808 }
3809
3810 static void
3811 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3812 {
3813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814         struct i40e_arq_event_info info;
3815         uint16_t pending, opcode;
3816         int ret;
3817
3818         info.buf_len = I40E_AQ_BUF_SZ;
3819         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3820         if (!info.msg_buf) {
3821                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3822                 return;
3823         }
3824
3825         pending = 1;
3826         while (pending) {
3827                 ret = i40e_clean_arq_element(hw, &info, &pending);
3828
3829                 if (ret != I40E_SUCCESS) {
3830                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3831                                     "aq_err: %u", hw->aq.asq_last_status);
3832                         break;
3833                 }
3834                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3835
3836                 switch (opcode) {
3837                 case i40e_aqc_opc_send_msg_to_pf:
3838                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3839                         i40e_pf_host_handle_vf_msg(dev,
3840                                         rte_le_to_cpu_16(info.desc.retval),
3841                                         rte_le_to_cpu_32(info.desc.cookie_high),
3842                                         rte_le_to_cpu_32(info.desc.cookie_low),
3843                                         info.msg_buf,
3844                                         info.msg_len);
3845                         break;
3846                 default:
3847                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3848                                     opcode);
3849                         break;
3850                 }
3851         }
3852         rte_free(info.msg_buf);
3853 }
3854
3855 /*
3856  * Interrupt handler is registered as the alarm callback for handling LSC
3857  * interrupt in a definite of time, in order to wait the NIC into a stable
3858  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3859  * no need for link down interrupt.
3860  */
3861 static void
3862 i40e_dev_interrupt_delayed_handler(void *param)
3863 {
3864         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3865         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         uint32_t icr0;
3867
3868         /* read interrupt causes again */
3869         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3870
3871 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3872         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3873                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3874         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3875                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3876         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3877                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3878         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3879                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3880         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3881                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3882                                                                 "state\n");
3883         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3884                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3885         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3886                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3887 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3888
3889         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3890                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3891                 i40e_dev_handle_vfr_event(dev);
3892         }
3893         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3894                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3895                 i40e_dev_handle_aq_msg(dev);
3896         }
3897
3898         /* handle the link up interrupt in an alarm callback */
3899         i40e_dev_link_update(dev, 0);
3900         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3901
3902         i40e_pf_enable_irq0(hw);
3903         rte_intr_enable(&(dev->pci_dev->intr_handle));
3904 }
3905
3906 /**
3907  * Interrupt handler triggered by NIC  for handling
3908  * specific interrupt.
3909  *
3910  * @param handle
3911  *  Pointer to interrupt handle.
3912  * @param param
3913  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3914  *
3915  * @return
3916  *  void
3917  */
3918 static void
3919 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3920                            void *param)
3921 {
3922         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3924         uint32_t icr0;
3925
3926         /* Disable interrupt */
3927         i40e_pf_disable_irq0(hw);
3928
3929         /* read out interrupt causes */
3930         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3931
3932         /* No interrupt event indicated */
3933         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3934                 PMD_DRV_LOG(INFO, "No interrupt event");
3935                 goto done;
3936         }
3937 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3938         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3939                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3940         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3941                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3942         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3943                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3944         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3945                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3946         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3947                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3948         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3949                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3950         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3951                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3952 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3953
3954         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3955                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3956                 i40e_dev_handle_vfr_event(dev);
3957         }
3958         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3959                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3960                 i40e_dev_handle_aq_msg(dev);
3961         }
3962
3963         /* Link Status Change interrupt */
3964         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3965 #define I40E_US_PER_SECOND 1000000
3966                 struct rte_eth_link link;
3967
3968                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3969                 memset(&link, 0, sizeof(link));
3970                 rte_i40e_dev_atomic_read_link_status(dev, &link);
3971                 i40e_dev_link_update(dev, 0);
3972
3973                 /*
3974                  * For link up interrupt, it needs to wait 1 second to let the
3975                  * hardware be a stable state. Otherwise several consecutive
3976                  * interrupts can be observed.
3977                  * For link down interrupt, no need to wait.
3978                  */
3979                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3980                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3981                         return;
3982                 else
3983                         _rte_eth_dev_callback_process(dev,
3984                                 RTE_ETH_EVENT_INTR_LSC);
3985         }
3986
3987 done:
3988         /* Enable interrupt */
3989         i40e_pf_enable_irq0(hw);
3990         rte_intr_enable(&(dev->pci_dev->intr_handle));
3991 }
3992
3993 static int
3994 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3995                          struct i40e_macvlan_filter *filter,
3996                          int total)
3997 {
3998         int ele_num, ele_buff_size;
3999         int num, actual_num, i;
4000         uint16_t flags;
4001         int ret = I40E_SUCCESS;
4002         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4003         struct i40e_aqc_add_macvlan_element_data *req_list;
4004
4005         if (filter == NULL  || total == 0)
4006                 return I40E_ERR_PARAM;
4007         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4008         ele_buff_size = hw->aq.asq_buf_size;
4009
4010         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4011         if (req_list == NULL) {
4012                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4013                 return I40E_ERR_NO_MEMORY;
4014         }
4015
4016         num = 0;
4017         do {
4018                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4019                 memset(req_list, 0, ele_buff_size);
4020
4021                 for (i = 0; i < actual_num; i++) {
4022                         (void)rte_memcpy(req_list[i].mac_addr,
4023                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4024                         req_list[i].vlan_tag =
4025                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4026
4027                         switch (filter[num + i].filter_type) {
4028                         case RTE_MAC_PERFECT_MATCH:
4029                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4030                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4031                                 break;
4032                         case RTE_MACVLAN_PERFECT_MATCH:
4033                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4034                                 break;
4035                         case RTE_MAC_HASH_MATCH:
4036                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4037                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4038                                 break;
4039                         case RTE_MACVLAN_HASH_MATCH:
4040                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4041                                 break;
4042                         default:
4043                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4044                                 ret = I40E_ERR_PARAM;
4045                                 goto DONE;
4046                         }
4047
4048                         req_list[i].queue_number = 0;
4049
4050                         req_list[i].flags = rte_cpu_to_le_16(flags);
4051                 }
4052
4053                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4054                                                 actual_num, NULL);
4055                 if (ret != I40E_SUCCESS) {
4056                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4057                         goto DONE;
4058                 }
4059                 num += actual_num;
4060         } while (num < total);
4061
4062 DONE:
4063         rte_free(req_list);
4064         return ret;
4065 }
4066
4067 static int
4068 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4069                             struct i40e_macvlan_filter *filter,
4070                             int total)
4071 {
4072         int ele_num, ele_buff_size;
4073         int num, actual_num, i;
4074         uint16_t flags;
4075         int ret = I40E_SUCCESS;
4076         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4077         struct i40e_aqc_remove_macvlan_element_data *req_list;
4078
4079         if (filter == NULL  || total == 0)
4080                 return I40E_ERR_PARAM;
4081
4082         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4083         ele_buff_size = hw->aq.asq_buf_size;
4084
4085         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4086         if (req_list == NULL) {
4087                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4088                 return I40E_ERR_NO_MEMORY;
4089         }
4090
4091         num = 0;
4092         do {
4093                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4094                 memset(req_list, 0, ele_buff_size);
4095
4096                 for (i = 0; i < actual_num; i++) {
4097                         (void)rte_memcpy(req_list[i].mac_addr,
4098                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4099                         req_list[i].vlan_tag =
4100                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4101
4102                         switch (filter[num + i].filter_type) {
4103                         case RTE_MAC_PERFECT_MATCH:
4104                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4105                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4106                                 break;
4107                         case RTE_MACVLAN_PERFECT_MATCH:
4108                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4109                                 break;
4110                         case RTE_MAC_HASH_MATCH:
4111                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4112                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4113                                 break;
4114                         case RTE_MACVLAN_HASH_MATCH:
4115                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4116                                 break;
4117                         default:
4118                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4119                                 ret = I40E_ERR_PARAM;
4120                                 goto DONE;
4121                         }
4122                         req_list[i].flags = rte_cpu_to_le_16(flags);
4123                 }
4124
4125                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4126                                                 actual_num, NULL);
4127                 if (ret != I40E_SUCCESS) {
4128                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4129                         goto DONE;
4130                 }
4131                 num += actual_num;
4132         } while (num < total);
4133
4134 DONE:
4135         rte_free(req_list);
4136         return ret;
4137 }
4138
4139 /* Find out specific MAC filter */
4140 static struct i40e_mac_filter *
4141 i40e_find_mac_filter(struct i40e_vsi *vsi,
4142                          struct ether_addr *macaddr)
4143 {
4144         struct i40e_mac_filter *f;
4145
4146         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4147                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4148                         return f;
4149         }
4150
4151         return NULL;
4152 }
4153
4154 static bool
4155 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4156                          uint16_t vlan_id)
4157 {
4158         uint32_t vid_idx, vid_bit;
4159
4160         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4161         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4162
4163         if (vsi->vfta[vid_idx] & vid_bit)
4164                 return 1;
4165         else
4166                 return 0;
4167 }
4168
4169 static void
4170 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4171                          uint16_t vlan_id, bool on)
4172 {
4173         uint32_t vid_idx, vid_bit;
4174
4175 #define UINT32_BIT_MASK      0x1F
4176 #define VALID_VLAN_BIT_MASK  0xFFF
4177         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4178          *  element first, then find the bits it belongs to
4179          */
4180         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4181                   sizeof(uint32_t));
4182         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4183
4184         if (on)
4185                 vsi->vfta[vid_idx] |= vid_bit;
4186         else
4187                 vsi->vfta[vid_idx] &= ~vid_bit;
4188 }
4189
4190 /**
4191  * Find all vlan options for specific mac addr,
4192  * return with actual vlan found.
4193  */
4194 static inline int
4195 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4196                            struct i40e_macvlan_filter *mv_f,
4197                            int num, struct ether_addr *addr)
4198 {
4199         int i;
4200         uint32_t j, k;
4201
4202         /**
4203          * Not to use i40e_find_vlan_filter to decrease the loop time,
4204          * although the code looks complex.
4205           */
4206         if (num < vsi->vlan_num)
4207                 return I40E_ERR_PARAM;
4208
4209         i = 0;
4210         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4211                 if (vsi->vfta[j]) {
4212                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4213                                 if (vsi->vfta[j] & (1 << k)) {
4214                                         if (i > num - 1) {
4215                                                 PMD_DRV_LOG(ERR, "vlan number "
4216                                                             "not match");
4217                                                 return I40E_ERR_PARAM;
4218                                         }
4219                                         (void)rte_memcpy(&mv_f[i].macaddr,
4220                                                         addr, ETH_ADDR_LEN);
4221                                         mv_f[i].vlan_id =
4222                                                 j * I40E_UINT32_BIT_SIZE + k;
4223                                         i++;
4224                                 }
4225                         }
4226                 }
4227         }
4228         return I40E_SUCCESS;
4229 }
4230
4231 static inline int
4232 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4233                            struct i40e_macvlan_filter *mv_f,
4234                            int num,
4235                            uint16_t vlan)
4236 {
4237         int i = 0;
4238         struct i40e_mac_filter *f;
4239
4240         if (num < vsi->mac_num)
4241                 return I40E_ERR_PARAM;
4242
4243         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4244                 if (i > num - 1) {
4245                         PMD_DRV_LOG(ERR, "buffer number not match");
4246                         return I40E_ERR_PARAM;
4247                 }
4248                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4249                                 ETH_ADDR_LEN);
4250                 mv_f[i].vlan_id = vlan;
4251                 mv_f[i].filter_type = f->mac_info.filter_type;
4252                 i++;
4253         }
4254
4255         return I40E_SUCCESS;
4256 }
4257
4258 static int
4259 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4260 {
4261         int i, num;
4262         struct i40e_mac_filter *f;
4263         struct i40e_macvlan_filter *mv_f;
4264         int ret = I40E_SUCCESS;
4265
4266         if (vsi == NULL || vsi->mac_num == 0)
4267                 return I40E_ERR_PARAM;
4268
4269         /* Case that no vlan is set */
4270         if (vsi->vlan_num == 0)
4271                 num = vsi->mac_num;
4272         else
4273                 num = vsi->mac_num * vsi->vlan_num;
4274
4275         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4276         if (mv_f == NULL) {
4277                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4278                 return I40E_ERR_NO_MEMORY;
4279         }
4280
4281         i = 0;
4282         if (vsi->vlan_num == 0) {
4283                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4284                         (void)rte_memcpy(&mv_f[i].macaddr,
4285                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4286                         mv_f[i].vlan_id = 0;
4287                         i++;
4288                 }
4289         } else {
4290                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4291                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4292                                         vsi->vlan_num, &f->mac_info.mac_addr);
4293                         if (ret != I40E_SUCCESS)
4294                                 goto DONE;
4295                         i += vsi->vlan_num;
4296                 }
4297         }
4298
4299         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4300 DONE:
4301         rte_free(mv_f);
4302
4303         return ret;
4304 }
4305
4306 int
4307 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4308 {
4309         struct i40e_macvlan_filter *mv_f;
4310         int mac_num;
4311         int ret = I40E_SUCCESS;
4312
4313         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4314                 return I40E_ERR_PARAM;
4315
4316         /* If it's already set, just return */
4317         if (i40e_find_vlan_filter(vsi,vlan))
4318                 return I40E_SUCCESS;
4319
4320         mac_num = vsi->mac_num;
4321
4322         if (mac_num == 0) {
4323                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4324                 return I40E_ERR_PARAM;
4325         }
4326
4327         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4328
4329         if (mv_f == NULL) {
4330                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4331                 return I40E_ERR_NO_MEMORY;
4332         }
4333
4334         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4335
4336         if (ret != I40E_SUCCESS)
4337                 goto DONE;
4338
4339         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4340
4341         if (ret != I40E_SUCCESS)
4342                 goto DONE;
4343
4344         i40e_set_vlan_filter(vsi, vlan, 1);
4345
4346         vsi->vlan_num++;
4347         ret = I40E_SUCCESS;
4348 DONE:
4349         rte_free(mv_f);
4350         return ret;
4351 }
4352
4353 int
4354 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4355 {
4356         struct i40e_macvlan_filter *mv_f;
4357         int mac_num;
4358         int ret = I40E_SUCCESS;
4359
4360         /**
4361          * Vlan 0 is the generic filter for untagged packets
4362          * and can't be removed.
4363          */
4364         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4365                 return I40E_ERR_PARAM;
4366
4367         /* If can't find it, just return */
4368         if (!i40e_find_vlan_filter(vsi, vlan))
4369                 return I40E_ERR_PARAM;
4370
4371         mac_num = vsi->mac_num;
4372
4373         if (mac_num == 0) {
4374                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4375                 return I40E_ERR_PARAM;
4376         }
4377
4378         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4379
4380         if (mv_f == NULL) {
4381                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4382                 return I40E_ERR_NO_MEMORY;
4383         }
4384
4385         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4386
4387         if (ret != I40E_SUCCESS)
4388                 goto DONE;
4389
4390         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4391
4392         if (ret != I40E_SUCCESS)
4393                 goto DONE;
4394
4395         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4396         if (vsi->vlan_num == 1) {
4397                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4398                 if (ret != I40E_SUCCESS)
4399                         goto DONE;
4400
4401                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4402                 if (ret != I40E_SUCCESS)
4403                         goto DONE;
4404         }
4405
4406         i40e_set_vlan_filter(vsi, vlan, 0);
4407
4408         vsi->vlan_num--;
4409         ret = I40E_SUCCESS;
4410 DONE:
4411         rte_free(mv_f);
4412         return ret;
4413 }
4414
4415 int
4416 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4417 {
4418         struct i40e_mac_filter *f;
4419         struct i40e_macvlan_filter *mv_f;
4420         int i, vlan_num = 0;
4421         int ret = I40E_SUCCESS;
4422
4423         /* If it's add and we've config it, return */
4424         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4425         if (f != NULL)
4426                 return I40E_SUCCESS;
4427         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4428                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4429
4430                 /**
4431                  * If vlan_num is 0, that's the first time to add mac,
4432                  * set mask for vlan_id 0.
4433                  */
4434                 if (vsi->vlan_num == 0) {
4435                         i40e_set_vlan_filter(vsi, 0, 1);
4436                         vsi->vlan_num = 1;
4437                 }
4438                 vlan_num = vsi->vlan_num;
4439         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4440                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4441                 vlan_num = 1;
4442
4443         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4444         if (mv_f == NULL) {
4445                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4446                 return I40E_ERR_NO_MEMORY;
4447         }
4448
4449         for (i = 0; i < vlan_num; i++) {
4450                 mv_f[i].filter_type = mac_filter->filter_type;
4451                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4452                                 ETH_ADDR_LEN);
4453         }
4454
4455         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4456                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4457                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4458                                         &mac_filter->mac_addr);
4459                 if (ret != I40E_SUCCESS)
4460                         goto DONE;
4461         }
4462
4463         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4464         if (ret != I40E_SUCCESS)
4465                 goto DONE;
4466
4467         /* Add the mac addr into mac list */
4468         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4469         if (f == NULL) {
4470                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4471                 ret = I40E_ERR_NO_MEMORY;
4472                 goto DONE;
4473         }
4474         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4475                         ETH_ADDR_LEN);
4476         f->mac_info.filter_type = mac_filter->filter_type;
4477         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4478         vsi->mac_num++;
4479
4480         ret = I40E_SUCCESS;
4481 DONE:
4482         rte_free(mv_f);
4483
4484         return ret;
4485 }
4486
4487 int
4488 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4489 {
4490         struct i40e_mac_filter *f;
4491         struct i40e_macvlan_filter *mv_f;
4492         int i, vlan_num;
4493         enum rte_mac_filter_type filter_type;
4494         int ret = I40E_SUCCESS;
4495
4496         /* Can't find it, return an error */
4497         f = i40e_find_mac_filter(vsi, addr);
4498         if (f == NULL)
4499                 return I40E_ERR_PARAM;
4500
4501         vlan_num = vsi->vlan_num;
4502         filter_type = f->mac_info.filter_type;
4503         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4504                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4505                 if (vlan_num == 0) {
4506                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4507                         return I40E_ERR_PARAM;
4508                 }
4509         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4510                         filter_type == RTE_MAC_HASH_MATCH)
4511                 vlan_num = 1;
4512
4513         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4514         if (mv_f == NULL) {
4515                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4516                 return I40E_ERR_NO_MEMORY;
4517         }
4518
4519         for (i = 0; i < vlan_num; i++) {
4520                 mv_f[i].filter_type = filter_type;
4521                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4522                                 ETH_ADDR_LEN);
4523         }
4524         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4525                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4526                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4527                 if (ret != I40E_SUCCESS)
4528                         goto DONE;
4529         }
4530
4531         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4532         if (ret != I40E_SUCCESS)
4533                 goto DONE;
4534
4535         /* Remove the mac addr into mac list */
4536         TAILQ_REMOVE(&vsi->mac_list, f, next);
4537         rte_free(f);
4538         vsi->mac_num--;
4539
4540         ret = I40E_SUCCESS;
4541 DONE:
4542         rte_free(mv_f);
4543         return ret;
4544 }
4545
4546 /* Configure hash enable flags for RSS */
4547 uint64_t
4548 i40e_config_hena(uint64_t flags)
4549 {
4550         uint64_t hena = 0;
4551
4552         if (!flags)
4553                 return hena;
4554
4555         if (flags & ETH_RSS_NONF_IPV4_UDP)
4556                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4557         if (flags & ETH_RSS_NONF_IPV4_TCP)
4558                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4559         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4560                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4561         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4562                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4563         if (flags & ETH_RSS_FRAG_IPV4)
4564                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4565         if (flags & ETH_RSS_NONF_IPV6_UDP)
4566                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4567         if (flags & ETH_RSS_NONF_IPV6_TCP)
4568                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4569         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4570                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4571         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4572                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4573         if (flags & ETH_RSS_FRAG_IPV6)
4574                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4575         if (flags & ETH_RSS_L2_PAYLOAD)
4576                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4577
4578         return hena;
4579 }
4580
4581 /* Parse the hash enable flags */
4582 uint64_t
4583 i40e_parse_hena(uint64_t flags)
4584 {
4585         uint64_t rss_hf = 0;
4586
4587         if (!flags)
4588                 return rss_hf;
4589
4590         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4591                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4592         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4593                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4594         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4595                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4596         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4597                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4598         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4599                 rss_hf |= ETH_RSS_FRAG_IPV4;
4600         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4601                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4602         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4603                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4604         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4605                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4606         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4607                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4608         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4609                 rss_hf |= ETH_RSS_FRAG_IPV6;
4610         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4611                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4612
4613         return rss_hf;
4614 }
4615
4616 /* Disable RSS */
4617 static void
4618 i40e_pf_disable_rss(struct i40e_pf *pf)
4619 {
4620         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4621         uint64_t hena;
4622
4623         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4624         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4625         hena &= ~I40E_RSS_HENA_ALL;
4626         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4627         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4628         I40E_WRITE_FLUSH(hw);
4629 }
4630
4631 static int
4632 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4633 {
4634         uint32_t *hash_key;
4635         uint8_t hash_key_len;
4636         uint64_t rss_hf;
4637         uint16_t i;
4638         uint64_t hena;
4639
4640         hash_key = (uint32_t *)(rss_conf->rss_key);
4641         hash_key_len = rss_conf->rss_key_len;
4642         if (hash_key != NULL && hash_key_len >=
4643                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4644                 /* Fill in RSS hash key */
4645                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4646                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4647         }
4648
4649         rss_hf = rss_conf->rss_hf;
4650         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4651         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4652         hena &= ~I40E_RSS_HENA_ALL;
4653         hena |= i40e_config_hena(rss_hf);
4654         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4655         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4656         I40E_WRITE_FLUSH(hw);
4657
4658         return 0;
4659 }
4660
4661 static int
4662 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4663                          struct rte_eth_rss_conf *rss_conf)
4664 {
4665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4667         uint64_t hena;
4668
4669         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4670         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4671         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4672                 if (rss_hf != 0) /* Enable RSS */
4673                         return -EINVAL;
4674                 return 0; /* Nothing to do */
4675         }
4676         /* RSS enabled */
4677         if (rss_hf == 0) /* Disable RSS */
4678                 return -EINVAL;
4679
4680         return i40e_hw_rss_hash_set(hw, rss_conf);
4681 }
4682
4683 static int
4684 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4685                            struct rte_eth_rss_conf *rss_conf)
4686 {
4687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4689         uint64_t hena;
4690         uint16_t i;
4691
4692         if (hash_key != NULL) {
4693                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4694                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4695                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4696         }
4697         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4698         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4699         rss_conf->rss_hf = i40e_parse_hena(hena);
4700
4701         return 0;
4702 }
4703
4704 static int
4705 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4706 {
4707         switch (filter_type) {
4708         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4709                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4710                 break;
4711         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4712                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4713                 break;
4714         case RTE_TUNNEL_FILTER_IMAC_TENID:
4715                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4716                 break;
4717         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4718                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4719                 break;
4720         case ETH_TUNNEL_FILTER_IMAC:
4721                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4722                 break;
4723         default:
4724                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4725                 return -EINVAL;
4726         }
4727
4728         return 0;
4729 }
4730
4731 static int
4732 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4733                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4734                         uint8_t add)
4735 {
4736         uint16_t ip_type;
4737         uint8_t tun_type = 0;
4738         int val, ret = 0;
4739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4740         struct i40e_vsi *vsi = pf->main_vsi;
4741         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4742         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4743
4744         cld_filter = rte_zmalloc("tunnel_filter",
4745                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4746                 0);
4747
4748         if (NULL == cld_filter) {
4749                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4750                 return -EINVAL;
4751         }
4752         pfilter = cld_filter;
4753
4754         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4755                         sizeof(struct ether_addr));
4756         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4757                         sizeof(struct ether_addr));
4758
4759         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4760         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4761                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4762                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4763                                 &tunnel_filter->ip_addr,
4764                                 sizeof(pfilter->ipaddr.v4.data));
4765         } else {
4766                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4767                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4768                                 &tunnel_filter->ip_addr,
4769                                 sizeof(pfilter->ipaddr.v6.data));
4770         }
4771
4772         /* check tunneled type */
4773         switch (tunnel_filter->tunnel_type) {
4774         case RTE_TUNNEL_TYPE_VXLAN:
4775                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4776                 break;
4777         default:
4778                 /* Other tunnel types is not supported. */
4779                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4780                 rte_free(cld_filter);
4781                 return -EINVAL;
4782         }
4783
4784         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4785                                                 &pfilter->flags);
4786         if (val < 0) {
4787                 rte_free(cld_filter);
4788                 return -EINVAL;
4789         }
4790
4791         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4792                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4793         pfilter->tenant_id = tunnel_filter->tenant_id;
4794         pfilter->queue_number = tunnel_filter->queue_id;
4795
4796         if (add)
4797                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4798         else
4799                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4800                                                 cld_filter, 1);
4801
4802         rte_free(cld_filter);
4803         return ret;
4804 }
4805
4806 static int
4807 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4808 {
4809         uint8_t i;
4810
4811         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4812                 if (pf->vxlan_ports[i] == port)
4813                         return i;
4814         }
4815
4816         return -1;
4817 }
4818
4819 static int
4820 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4821 {
4822         int  idx, ret;
4823         uint8_t filter_idx;
4824         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4825
4826         idx = i40e_get_vxlan_port_idx(pf, port);
4827
4828         /* Check if port already exists */
4829         if (idx >= 0) {
4830                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4831                 return -EINVAL;
4832         }
4833
4834         /* Now check if there is space to add the new port */
4835         idx = i40e_get_vxlan_port_idx(pf, 0);
4836         if (idx < 0) {
4837                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4838                         "not adding port %d", port);
4839                 return -ENOSPC;
4840         }
4841
4842         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4843                                         &filter_idx, NULL);
4844         if (ret < 0) {
4845                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4846                 return -1;
4847         }
4848
4849         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4850                          port,  filter_idx);
4851
4852         /* New port: add it and mark its index in the bitmap */
4853         pf->vxlan_ports[idx] = port;
4854         pf->vxlan_bitmap |= (1 << idx);
4855
4856         if (!(pf->flags & I40E_FLAG_VXLAN))
4857                 pf->flags |= I40E_FLAG_VXLAN;
4858
4859         return 0;
4860 }
4861
4862 static int
4863 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4864 {
4865         int idx;
4866         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4867
4868         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4869                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4870                 return -EINVAL;
4871         }
4872
4873         idx = i40e_get_vxlan_port_idx(pf, port);
4874
4875         if (idx < 0) {
4876                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4877                 return -EINVAL;
4878         }
4879
4880         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4881                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4882                 return -1;
4883         }
4884
4885         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4886                         port, idx);
4887
4888         pf->vxlan_ports[idx] = 0;
4889         pf->vxlan_bitmap &= ~(1 << idx);
4890
4891         if (!pf->vxlan_bitmap)
4892                 pf->flags &= ~I40E_FLAG_VXLAN;
4893
4894         return 0;
4895 }
4896
4897 /* Add UDP tunneling port */
4898 static int
4899 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4900                         struct rte_eth_udp_tunnel *udp_tunnel)
4901 {
4902         int ret = 0;
4903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4904
4905         if (udp_tunnel == NULL)
4906                 return -EINVAL;
4907
4908         switch (udp_tunnel->prot_type) {
4909         case RTE_TUNNEL_TYPE_VXLAN:
4910                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4911                 break;
4912
4913         case RTE_TUNNEL_TYPE_GENEVE:
4914         case RTE_TUNNEL_TYPE_TEREDO:
4915                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4916                 ret = -1;
4917                 break;
4918
4919         default:
4920                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4921                 ret = -1;
4922                 break;
4923         }
4924
4925         return ret;
4926 }
4927
4928 /* Remove UDP tunneling port */
4929 static int
4930 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4931                         struct rte_eth_udp_tunnel *udp_tunnel)
4932 {
4933         int ret = 0;
4934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4935
4936         if (udp_tunnel == NULL)
4937                 return -EINVAL;
4938
4939         switch (udp_tunnel->prot_type) {
4940         case RTE_TUNNEL_TYPE_VXLAN:
4941                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4942                 break;
4943         case RTE_TUNNEL_TYPE_GENEVE:
4944         case RTE_TUNNEL_TYPE_TEREDO:
4945                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4946                 ret = -1;
4947                 break;
4948         default:
4949                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4950                 ret = -1;
4951                 break;
4952         }
4953
4954         return ret;
4955 }
4956
4957 /* Calculate the maximum number of contiguous PF queues that are configured */
4958 static int
4959 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4960 {
4961         struct rte_eth_dev_data *data = pf->dev_data;
4962         int i, num;
4963         struct i40e_rx_queue *rxq;
4964
4965         num = 0;
4966         for (i = 0; i < pf->lan_nb_qps; i++) {
4967                 rxq = data->rx_queues[i];
4968                 if (rxq && rxq->q_set)
4969                         num++;
4970                 else
4971                         break;
4972         }
4973
4974         return num;
4975 }
4976
4977 /* Configure RSS */
4978 static int
4979 i40e_pf_config_rss(struct i40e_pf *pf)
4980 {
4981         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4982         struct rte_eth_rss_conf rss_conf;
4983         uint32_t i, lut = 0;
4984         uint16_t j, num;
4985
4986         /*
4987          * If both VMDQ and RSS enabled, not all of PF queues are configured.
4988          * It's necessary to calulate the actual PF queues that are configured.
4989          */
4990         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4991                 num = i40e_pf_calc_configured_queues_num(pf);
4992                 num = i40e_align_floor(num);
4993         } else
4994                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4995
4996         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
4997                         num);
4998
4999         if (num == 0) {
5000                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5001                 return -ENOTSUP;
5002         }
5003
5004         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5005                 if (j == num)
5006                         j = 0;
5007                 lut = (lut << 8) | (j & ((0x1 <<
5008                         hw->func_caps.rss_table_entry_width) - 1));
5009                 if ((i & 3) == 3)
5010                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5011         }
5012
5013         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5014         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5015                 i40e_pf_disable_rss(pf);
5016                 return 0;
5017         }
5018         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5019                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5020                 /* Calculate the default hash key */
5021                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5022                         rss_key_default[i] = (uint32_t)rte_rand();
5023                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5024                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5025                                                         sizeof(uint32_t);
5026         }
5027
5028         return i40e_hw_rss_hash_set(hw, &rss_conf);
5029 }
5030
5031 static int
5032 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5033                         struct rte_eth_tunnel_filter_conf *filter)
5034 {
5035         if (pf == NULL || filter == NULL) {
5036                 PMD_DRV_LOG(ERR, "Invalid parameter");
5037                 return -EINVAL;
5038         }
5039
5040         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5041                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5042                 return -EINVAL;
5043         }
5044
5045         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5046                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5047                 return -EINVAL;
5048         }
5049
5050         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5051                 (is_zero_ether_addr(filter->outer_mac))) {
5052                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5053                 return -EINVAL;
5054         }
5055
5056         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5057                 (is_zero_ether_addr(filter->inner_mac))) {
5058                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5059                 return -EINVAL;
5060         }
5061
5062         return 0;
5063 }
5064
5065 static int
5066 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5067                         void *arg)
5068 {
5069         struct rte_eth_tunnel_filter_conf *filter;
5070         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5071         int ret = I40E_SUCCESS;
5072
5073         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5074
5075         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5076                 return I40E_ERR_PARAM;
5077
5078         switch (filter_op) {
5079         case RTE_ETH_FILTER_NOP:
5080                 if (!(pf->flags & I40E_FLAG_VXLAN))
5081                         ret = I40E_NOT_SUPPORTED;
5082         case RTE_ETH_FILTER_ADD:
5083                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5084                 break;
5085         case RTE_ETH_FILTER_DELETE:
5086                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5087                 break;
5088         default:
5089                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5090                 ret = I40E_ERR_PARAM;
5091                 break;
5092         }
5093
5094         return ret;
5095 }
5096
5097 static int
5098 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5099 {
5100         int ret = 0;
5101         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5102
5103         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5104                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5105                 return -ENOTSUP;
5106         }
5107
5108         /* RSS setup */
5109         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5110                 ret = i40e_pf_config_rss(pf);
5111         else
5112                 i40e_pf_disable_rss(pf);
5113
5114         return ret;
5115 }
5116
5117 static int
5118 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5119                      enum rte_filter_type filter_type,
5120                      enum rte_filter_op filter_op,
5121                      void *arg)
5122 {
5123         int ret = 0;
5124
5125         if (dev == NULL)
5126                 return -EINVAL;
5127
5128         switch (filter_type) {
5129         case RTE_ETH_FILTER_MACVLAN:
5130                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5131                 break;
5132         case RTE_ETH_FILTER_TUNNEL:
5133                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5134                 break;
5135         case RTE_ETH_FILTER_FDIR:
5136                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5137                 break;
5138         default:
5139                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5140                                                         filter_type);
5141                 ret = -EINVAL;
5142                 break;
5143         }
5144
5145         return ret;
5146 }
5147
5148 enum i40e_filter_pctype
5149 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5150 {
5151         static const enum i40e_filter_pctype pctype_table[] = {
5152                 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5153                 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5154                 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5155                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5156                                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5157                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5158                                         I40E_FILTER_PCTYPE_FRAG_IPV4,
5159                 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5160                 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5161                 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5162                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5163                                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5164                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5165                                         I40E_FILTER_PCTYPE_FRAG_IPV6,
5166         };
5167
5168         return pctype_table[flow_type];
5169 }
5170
5171 enum rte_eth_flow_type
5172 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5173 {
5174         static const enum rte_eth_flow_type flowtype_table[] = {
5175                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5176                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5177                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5178                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5179                                         RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5180                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5181                                         RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5182                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5183                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5184                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5185                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5186                                         RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5187                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5188                                         RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5189         };
5190
5191         return flowtype_table[pctype];
5192 }