lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 #define I40E_DEFAULT_RX_FREE_THRESH  32
  62 #define I40E_DEFAULT_RX_PTHRESH      8
  63 #define I40E_DEFAULT_RX_HTHRESH      8
  64 #define I40E_DEFAULT_RX_WTHRESH      0
  65
  66 #define I40E_DEFAULT_TX_FREE_THRESH  32
  67 #define I40E_DEFAULT_TX_PTHRESH      32
  68 #define I40E_DEFAULT_TX_HTHRESH      0
  69 #define I40E_DEFAULT_TX_WTHRESH      0
  70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  71
  72 /* Maximun number of MAC addresses */
  73 #define I40E_NUM_MACADDR_MAX       64
  74 #define I40E_CLEAR_PXE_WAIT_MS     200
  75
  76 /* Maximun number of capability elements */
  77 #define I40E_MAX_CAP_ELE_NUM       128
  78
  79 /* Wait count and inteval */
  80 #define I40E_CHK_Q_ENA_COUNT       1000
  81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  82
  83 /* Maximun number of VSI */
  84 #define I40E_MAX_NUM_VSIS          (384UL)
  85
  86 /* Bit shift and mask */
  87 #define I40E_16_BIT_SHIFT 16
  88 #define I40E_16_BIT_MASK  0xFFFF
  89 #define I40E_32_BIT_SHIFT 32
  90 #define I40E_32_BIT_MASK  0xFFFFFFFF
  91 #define I40E_48_BIT_SHIFT 48
  92 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  93
  94 /* Default queue interrupt throttling time in microseconds*/
  95 #define I40E_ITR_INDEX_DEFAULT          0
  96 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  97 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  98
  99 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 100
 101 #define I40E_RSS_OFFLOAD_ALL ( \
 102         ETH_RSS_NONF_IPV4_UDP | \
 103         ETH_RSS_NONF_IPV4_TCP | \
 104         ETH_RSS_NONF_IPV4_SCTP | \
 105         ETH_RSS_NONF_IPV4_OTHER | \
 106         ETH_RSS_FRAG_IPV4 | \
 107         ETH_RSS_NONF_IPV6_UDP | \
 108         ETH_RSS_NONF_IPV6_TCP | \
 109         ETH_RSS_NONF_IPV6_SCTP | \
 110         ETH_RSS_NONF_IPV6_OTHER | \
 111         ETH_RSS_FRAG_IPV6 | \
 112         ETH_RSS_L2_PAYLOAD)
 113
 114 /* All bits of RSS hash enable */
 115 #define I40E_RSS_HENA_ALL ( \
 116         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 117         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 118         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 119         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 120         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 121         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 122         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 123         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 124         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 125         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 126         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 127         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 128         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 129         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 130
 131 static int eth_i40e_dev_init(\
 132                         __attribute__((unused)) struct eth_driver *eth_drv,
 133                         struct rte_eth_dev *eth_dev);
 134 static int i40e_dev_configure(struct rte_eth_dev *dev);
 135 static int i40e_dev_start(struct rte_eth_dev *dev);
 136 static void i40e_dev_stop(struct rte_eth_dev *dev);
 137 static void i40e_dev_close(struct rte_eth_dev *dev);
 138 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 139 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 140 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 141 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 142 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 145                                struct rte_eth_stats *stats);
 146 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 147 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 148                                             uint16_t queue_id,
 149                                             uint8_t stat_idx,
 150                                             uint8_t is_rx);
 151 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 152                               struct rte_eth_dev_info *dev_info);
 153 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 154                                 uint16_t vlan_id,
 155                                 int on);
 156 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 157 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 158 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 159                                       uint16_t queue,
 160                                       int on);
 161 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 162 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 163 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 164 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 165                               struct rte_eth_fc_conf *fc_conf);
 166 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                                        struct rte_eth_pfc_conf *pfc_conf);
 168 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 169                           struct ether_addr *mac_addr,
 170                           uint32_t index,
 171                           uint32_t pool);
 172 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 173 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 174                                     struct rte_eth_rss_reta *reta_conf);
 175 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 176                                    struct rte_eth_rss_reta *reta_conf);
 177
 178 static int i40e_get_cap(struct i40e_hw *hw);
 179 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 180 static int i40e_pf_setup(struct i40e_pf *pf);
 181 static int i40e_vsi_init(struct i40e_vsi *vsi);
 182 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 183                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 184 static void i40e_stat_update_48(struct i40e_hw *hw,
 185                                uint32_t hireg,
 186                                uint32_t loreg,
 187                                bool offset_loaded,
 188                                uint64_t *offset,
 189                                uint64_t *stat);
 190 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 191 static void i40e_dev_interrupt_handler(
 192                 __rte_unused struct rte_intr_handle *handle, void *param);
 193 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 194                                 uint32_t base, uint32_t num);
 195 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 196 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 197                         uint32_t base);
 198 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 199                         uint16_t num);
 200 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 201 static int i40e_veb_release(struct i40e_veb *veb);
 202 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 203                                                 struct i40e_vsi *vsi);
 204 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 205 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 206 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 207                                              struct i40e_macvlan_filter *mv_f,
 208                                              int num,
 209                                              struct ether_addr *addr);
 210 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 211                                              struct i40e_macvlan_filter *mv_f,
 212                                              int num,
 213                                              uint16_t vlan);
 214 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 215 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 216                                     struct rte_eth_rss_conf *rss_conf);
 217 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 218                                       struct rte_eth_rss_conf *rss_conf);
 219
 220 /* Default hash key buffer for RSS */
 221 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 222
 223 static struct rte_pci_id pci_id_i40e_map[] = {
 224 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 225 #include "rte_pci_dev_ids.h"
 226 { .vendor_id = 0, /* sentinel */ },
 227 };
 228
 229 static struct eth_dev_ops i40e_eth_dev_ops = {
 230         .dev_configure                = i40e_dev_configure,
 231         .dev_start                    = i40e_dev_start,
 232         .dev_stop                     = i40e_dev_stop,
 233         .dev_close                    = i40e_dev_close,
 234         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 235         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 236         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 237         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 238         .dev_set_link_up              = i40e_dev_set_link_up,
 239         .dev_set_link_down            = i40e_dev_set_link_down,
 240         .link_update                  = i40e_dev_link_update,
 241         .stats_get                    = i40e_dev_stats_get,
 242         .stats_reset                  = i40e_dev_stats_reset,
 243         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 244         .dev_infos_get                = i40e_dev_info_get,
 245         .vlan_filter_set              = i40e_vlan_filter_set,
 246         .vlan_tpid_set                = i40e_vlan_tpid_set,
 247         .vlan_offload_set             = i40e_vlan_offload_set,
 248         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 249         .vlan_pvid_set                = i40e_vlan_pvid_set,
 250         .rx_queue_start               = i40e_dev_rx_queue_start,
 251         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 252         .tx_queue_start               = i40e_dev_tx_queue_start,
 253         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 254         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 255         .rx_queue_release             = i40e_dev_rx_queue_release,
 256         .rx_queue_count               = i40e_dev_rx_queue_count,
 257         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 258         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 259         .tx_queue_release             = i40e_dev_tx_queue_release,
 260         .dev_led_on                   = i40e_dev_led_on,
 261         .dev_led_off                  = i40e_dev_led_off,
 262         .flow_ctrl_set                = i40e_flow_ctrl_set,
 263         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 264         .mac_addr_add                 = i40e_macaddr_add,
 265         .mac_addr_remove              = i40e_macaddr_remove,
 266         .reta_update                  = i40e_dev_rss_reta_update,
 267         .reta_query                   = i40e_dev_rss_reta_query,
 268         .rss_hash_update              = i40e_dev_rss_hash_update,
 269         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 270 };
 271
 272 static struct eth_driver rte_i40e_pmd = {
 273         {
 274                 .name = "rte_i40e_pmd",
 275                 .id_table = pci_id_i40e_map,
 276                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 277         },
 278         .eth_dev_init = eth_i40e_dev_init,
 279         .dev_private_size = sizeof(struct i40e_adapter),
 280 };
 281
 282 static inline int
 283 i40e_prev_power_of_2(int n)
 284 {
 285        int p = n;
 286
 287        --p;
 288        p |= p >> 1;
 289        p |= p >> 2;
 290        p |= p >> 4;
 291        p |= p >> 8;
 292        p |= p >> 16;
 293        if (p == (n - 1))
 294                return n;
 295        p >>= 1;
 296
 297        return ++p;
 298 }
 299
 300 static inline int
 301 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 302                                      struct rte_eth_link *link)
 303 {
 304         struct rte_eth_link *dst = link;
 305         struct rte_eth_link *src = &(dev->data->dev_link);
 306
 307         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 308                                         *(uint64_t *)src) == 0)
 309                 return -1;
 310
 311         return 0;
 312 }
 313
 314 static inline int
 315 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 316                                       struct rte_eth_link *link)
 317 {
 318         struct rte_eth_link *dst = &(dev->data->dev_link);
 319         struct rte_eth_link *src = link;
 320
 321         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 322                                         *(uint64_t *)src) == 0)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 /*
 329  * Driver initialization routine.
 330  * Invoked once at EAL init time.
 331  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 332  */
 333 static int
 334 rte_i40e_pmd_init(const char *name __rte_unused,
 335                   const char *params __rte_unused)
 336 {
 337         PMD_INIT_FUNC_TRACE();
 338         rte_eth_driver_register(&rte_i40e_pmd);
 339
 340         return 0;
 341 }
 342
 343 static struct rte_driver rte_i40e_driver = {
 344         .type = PMD_PDEV,
 345         .init = rte_i40e_pmd_init,
 346 };
 347
 348 PMD_REGISTER_DRIVER(rte_i40e_driver);
 349
 350 static int
 351 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 352                   struct rte_eth_dev *dev)
 353 {
 354         struct rte_pci_device *pci_dev;
 355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 357         struct i40e_vsi *vsi;
 358         int ret;
 359         uint32_t len;
 360         uint8_t aq_fail = 0;
 361
 362         PMD_INIT_FUNC_TRACE();
 363
 364         dev->dev_ops = &i40e_eth_dev_ops;
 365         dev->rx_pkt_burst = i40e_recv_pkts;
 366         dev->tx_pkt_burst = i40e_xmit_pkts;
 367
 368         /* for secondary processes, we don't initialise any further as primary
 369          * has already done this work. Only check we don't need a different
 370          * RX function */
 371         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 372                 if (dev->data->scattered_rx)
 373                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 374                 return 0;
 375         }
 376         pci_dev = dev->pci_dev;
 377         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 378         pf->adapter->eth_dev = dev;
 379         pf->dev_data = dev->data;
 380
 381         hw->back = I40E_PF_TO_ADAPTER(pf);
 382         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 383         if (!hw->hw_addr) {
 384                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 385                              "as address is NULL");
 386                 return -ENODEV;
 387         }
 388
 389         hw->vendor_id = pci_dev->id.vendor_id;
 390         hw->device_id = pci_dev->id.device_id;
 391         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 392         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 393         hw->bus.device = pci_dev->addr.devid;
 394         hw->bus.func = pci_dev->addr.function;
 395
 396         /* Make sure all is clean before doing PF reset */
 397         i40e_clear_hw(hw);
 398
 399         /* Reset here to make sure all is clean for each PF */
 400         ret = i40e_pf_reset(hw);
 401         if (ret) {
 402                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 403                 return ret;
 404         }
 405
 406         /* Initialize the shared code (base driver) */
 407         ret = i40e_init_shared_code(hw);
 408         if (ret) {
 409                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 410                 return ret;
 411         }
 412
 413         /* Initialize the parameters for adminq */
 414         i40e_init_adminq_parameter(hw);
 415         ret = i40e_init_adminq(hw);
 416         if (ret != I40E_SUCCESS) {
 417                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 418                 return -EIO;
 419         }
 420         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 421                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 422                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 423                      ((hw->nvm.version >> 12) & 0xf),
 424                      ((hw->nvm.version >> 4) & 0xff),
 425                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 426
 427         /* Disable LLDP */
 428         ret = i40e_aq_stop_lldp(hw, true, NULL);
 429         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 430                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 431
 432         /* Clear PXE mode */
 433         i40e_clear_pxe_mode(hw);
 434
 435         /* Get hw capabilities */
 436         ret = i40e_get_cap(hw);
 437         if (ret != I40E_SUCCESS) {
 438                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 439                 goto err_get_capabilities;
 440         }
 441
 442         /* Initialize parameters for PF */
 443         ret = i40e_pf_parameter_init(dev);
 444         if (ret != 0) {
 445                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 446                 goto err_parameter_init;
 447         }
 448
 449         /* Initialize the queue management */
 450         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 451         if (ret < 0) {
 452                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 453                 goto err_qp_pool_init;
 454         }
 455         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 456                                 hw->func_caps.num_msix_vectors - 1);
 457         if (ret < 0) {
 458                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 459                 goto err_msix_pool_init;
 460         }
 461
 462         /* Initialize lan hmc */
 463         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 464                                 hw->func_caps.num_rx_qp, 0, 0);
 465         if (ret != I40E_SUCCESS) {
 466                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 467                 goto err_init_lan_hmc;
 468         }
 469
 470         /* Configure lan hmc */
 471         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 472         if (ret != I40E_SUCCESS) {
 473                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 474                 goto err_configure_lan_hmc;
 475         }
 476
 477         /* Get and check the mac address */
 478         i40e_get_mac_addr(hw, hw->mac.addr);
 479         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 480                 PMD_INIT_LOG(ERR, "mac address is not valid");
 481                 ret = -EIO;
 482                 goto err_get_mac_addr;
 483         }
 484         /* Copy the permanent MAC address */
 485         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 486                         (struct ether_addr *) hw->mac.perm_addr);
 487
 488         /* Disable flow control */
 489         hw->fc.requested_mode = I40E_FC_NONE;
 490         i40e_set_fc(hw, &aq_fail, TRUE);
 491
 492         /* PF setup, which includes VSI setup */
 493         ret = i40e_pf_setup(pf);
 494         if (ret) {
 495                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 496                 goto err_setup_pf_switch;
 497         }
 498
 499         vsi = pf->main_vsi;
 500
 501         /* Disable double vlan by default */
 502         i40e_vsi_config_double_vlan(vsi, FALSE);
 503
 504         if (!vsi->max_macaddrs)
 505                 len = ETHER_ADDR_LEN;
 506         else
 507                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 508
 509         /* Should be after VSI initialized */
 510         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 511         if (!dev->data->mac_addrs) {
 512                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 513                                         "for storing mac address");
 514                 goto err_get_mac_addr;
 515         }
 516         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 517                                         &dev->data->mac_addrs[0]);
 518
 519         /* initialize pf host driver to setup SRIOV resource if applicable */
 520         i40e_pf_host_init(dev);
 521
 522         /* register callback func to eal lib */
 523         rte_intr_callback_register(&(pci_dev->intr_handle),
 524                 i40e_dev_interrupt_handler, (void *)dev);
 525
 526         /* configure and enable device interrupt */
 527         i40e_pf_config_irq0(hw);
 528         i40e_pf_enable_irq0(hw);
 529
 530         /* enable uio intr after callback register */
 531         rte_intr_enable(&(pci_dev->intr_handle));
 532
 533         return 0;
 534
 535 err_setup_pf_switch:
 536         rte_free(pf->main_vsi);
 537 err_get_mac_addr:
 538 err_configure_lan_hmc:
 539         (void)i40e_shutdown_lan_hmc(hw);
 540 err_init_lan_hmc:
 541         i40e_res_pool_destroy(&pf->msix_pool);
 542 err_msix_pool_init:
 543         i40e_res_pool_destroy(&pf->qp_pool);
 544 err_qp_pool_init:
 545 err_parameter_init:
 546 err_get_capabilities:
 547         (void)i40e_shutdown_adminq(hw);
 548
 549         return ret;
 550 }
 551
 552 static int
 553 i40e_dev_configure(struct rte_eth_dev *dev)
 554 {
 555         return i40e_dev_init_vlan(dev);
 556 }
 557
 558 void
 559 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 560 {
 561         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 562         uint16_t msix_vect = vsi->msix_intr;
 563         uint16_t i;
 564
 565         for (i = 0; i < vsi->nb_qps; i++) {
 566                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 567                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 568                 rte_wmb();
 569         }
 570
 571         if (vsi->type != I40E_VSI_SRIOV) {
 572                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 573                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 574                                 msix_vect - 1), 0);
 575         } else {
 576                 uint32_t reg;
 577                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 578                         vsi->user_param + (msix_vect - 1);
 579
 580                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 581         }
 582         I40E_WRITE_FLUSH(hw);
 583 }
 584
 585 static inline uint16_t
 586 i40e_calc_itr_interval(int16_t interval)
 587 {
 588         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 589                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 590
 591         /* Convert to hardware count, as writing each 1 represents 2 us */
 592         return (interval/2);
 593 }
 594
 595 void
 596 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 597 {
 598         uint32_t val;
 599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 600         uint16_t msix_vect = vsi->msix_intr;
 601         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 602         int i;
 603
 604         for (i = 0; i < vsi->nb_qps; i++)
 605                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 606
 607         /* Bind all RX queues to allocated MSIX interrupt */
 608         for (i = 0; i < vsi->nb_qps; i++) {
 609                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 610                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 611                         ((vsi->base_queue + i + 1) <<
 612                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 613                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 614                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 615
 616                 if (i == vsi->nb_qps - 1)
 617                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 618                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 619         }
 620
 621         /* Write first RX queue to Link list register as the head element */
 622         if (vsi->type != I40E_VSI_SRIOV) {
 623                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 624                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 625                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 626
 627                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 628                                 msix_vect - 1), interval);
 629
 630                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 631                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 632                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 633         }
 634         else {
 635                 uint32_t reg;
 636                 /* num_msix_vectors_vf needs to minus irq0 */
 637                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 638                         vsi->user_param + (msix_vect - 1);
 639
 640                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 641                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 642                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 643         }
 644
 645         I40E_WRITE_FLUSH(hw);
 646 }
 647
 648 static void
 649 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 650 {
 651         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 652         uint16_t interval = i40e_calc_itr_interval(\
 653                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 654
 655         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 656                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 657                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 658                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 659                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 660 }
 661
 662 static void
 663 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 664 {
 665         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 666
 667         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 668 }
 669
 670 static inline uint8_t
 671 i40e_parse_link_speed(uint16_t eth_link_speed)
 672 {
 673         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 674
 675         switch (eth_link_speed) {
 676         case ETH_LINK_SPEED_40G:
 677                 link_speed = I40E_LINK_SPEED_40GB;
 678                 break;
 679         case ETH_LINK_SPEED_20G:
 680                 link_speed = I40E_LINK_SPEED_20GB;
 681                 break;
 682         case ETH_LINK_SPEED_10G:
 683                 link_speed = I40E_LINK_SPEED_10GB;
 684                 break;
 685         case ETH_LINK_SPEED_1000:
 686                 link_speed = I40E_LINK_SPEED_1GB;
 687                 break;
 688         case ETH_LINK_SPEED_100:
 689                 link_speed = I40E_LINK_SPEED_100MB;
 690                 break;
 691         }
 692
 693         return link_speed;
 694 }
 695
 696 static int
 697 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 698 {
 699         enum i40e_status_code status;
 700         struct i40e_aq_get_phy_abilities_resp phy_ab;
 701         struct i40e_aq_set_phy_config phy_conf;
 702         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 703                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 704                         I40E_AQ_PHY_FLAG_LOW_POWER;
 705         const uint8_t advt = I40E_LINK_SPEED_40GB |
 706                         I40E_LINK_SPEED_10GB |
 707                         I40E_LINK_SPEED_1GB |
 708                         I40E_LINK_SPEED_100MB;
 709         int ret = -ENOTSUP;
 710
 711         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 712                                               NULL);
 713         if (status)
 714                 return ret;
 715
 716         memset(&phy_conf, 0, sizeof(phy_conf));
 717
 718         /* bits 0-2 use the values from get_phy_abilities_resp */
 719         abilities &= ~mask;
 720         abilities |= phy_ab.abilities & mask;
 721
 722         /* update ablities and speed */
 723         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 724                 phy_conf.link_speed = advt;
 725         else
 726                 phy_conf.link_speed = force_speed;
 727
 728         phy_conf.abilities = abilities;
 729
 730         /* use get_phy_abilities_resp value for the rest */
 731         phy_conf.phy_type = phy_ab.phy_type;
 732         phy_conf.eee_capability = phy_ab.eee_capability;
 733         phy_conf.eeer = phy_ab.eeer_val;
 734         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 735
 736         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 737                     phy_ab.abilities, phy_ab.link_speed);
 738         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 739                     phy_conf.abilities, phy_conf.link_speed);
 740
 741         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 742         if (status)
 743                 return ret;
 744
 745         return I40E_SUCCESS;
 746 }
 747
 748 static int
 749 i40e_apply_link_speed(struct rte_eth_dev *dev)
 750 {
 751         uint8_t speed;
 752         uint8_t abilities = 0;
 753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755
 756         speed = i40e_parse_link_speed(conf->link_speed);
 757         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 758         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 759                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 760         else
 761                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 762
 763         return i40e_phy_conf_link(hw, abilities, speed);
 764 }
 765
 766 static int
 767 i40e_dev_start(struct rte_eth_dev *dev)
 768 {
 769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 771         struct i40e_vsi *vsi = pf->main_vsi;
 772         int ret;
 773
 774         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 775                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 776                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 777                              dev->data->dev_conf.link_duplex,
 778                              dev->data->port_id);
 779                 return -EINVAL;
 780         }
 781
 782         /* Initialize VSI */
 783         ret = i40e_vsi_init(vsi);
 784         if (ret != I40E_SUCCESS) {
 785                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 786                 goto err_up;
 787         }
 788
 789         /* Map queues with MSIX interrupt */
 790         i40e_vsi_queues_bind_intr(vsi);
 791         i40e_vsi_enable_queues_intr(vsi);
 792
 793         /* Enable all queues which have been configured */
 794         ret = i40e_vsi_switch_queues(vsi, TRUE);
 795         if (ret != I40E_SUCCESS) {
 796                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 797                 goto err_up;
 798         }
 799
 800         /* Enable receiving broadcast packets */
 801         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 802                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 803                 if (ret != I40E_SUCCESS)
 804                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 805         }
 806
 807         /* Apply link configure */
 808         ret = i40e_apply_link_speed(dev);
 809         if (I40E_SUCCESS != ret) {
 810                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 811                 goto err_up;
 812         }
 813
 814         return I40E_SUCCESS;
 815
 816 err_up:
 817         i40e_vsi_switch_queues(vsi, FALSE);
 818
 819         return ret;
 820 }
 821
 822 static void
 823 i40e_dev_stop(struct rte_eth_dev *dev)
 824 {
 825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 826         struct i40e_vsi *vsi = pf->main_vsi;
 827
 828         /* Disable all queues */
 829         i40e_vsi_switch_queues(vsi, FALSE);
 830
 831         /* Set link down */
 832         i40e_dev_set_link_down(dev);
 833
 834         /* un-map queues with interrupt registers */
 835         i40e_vsi_disable_queues_intr(vsi);
 836         i40e_vsi_queues_unbind_intr(vsi);
 837 }
 838
 839 static void
 840 i40e_dev_close(struct rte_eth_dev *dev)
 841 {
 842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844         uint32_t reg;
 845
 846         PMD_INIT_FUNC_TRACE();
 847
 848         i40e_dev_stop(dev);
 849
 850         /* Disable interrupt */
 851         i40e_pf_disable_irq0(hw);
 852         rte_intr_disable(&(dev->pci_dev->intr_handle));
 853
 854         /* shutdown and destroy the HMC */
 855         i40e_shutdown_lan_hmc(hw);
 856
 857         /* release all the existing VSIs and VEBs */
 858         i40e_vsi_release(pf->main_vsi);
 859
 860         /* shutdown the adminq */
 861         i40e_aq_queue_shutdown(hw, true);
 862         i40e_shutdown_adminq(hw);
 863
 864         i40e_res_pool_destroy(&pf->qp_pool);
 865         i40e_res_pool_destroy(&pf->msix_pool);
 866
 867         /* force a PF reset to clean anything leftover */
 868         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 869         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 870                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 871         I40E_WRITE_FLUSH(hw);
 872 }
 873
 874 static void
 875 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 876 {
 877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 879         struct i40e_vsi *vsi = pf->main_vsi;
 880         int status;
 881
 882         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 883                                                         true, NULL);
 884         if (status != I40E_SUCCESS)
 885                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 886
 887         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 888                                                         TRUE, NULL);
 889         if (status != I40E_SUCCESS)
 890                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 891
 892 }
 893
 894 static void
 895 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 896 {
 897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 899         struct i40e_vsi *vsi = pf->main_vsi;
 900         int status;
 901
 902         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 903                                                         false, NULL);
 904         if (status != I40E_SUCCESS)
 905                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 906
 907         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 908                                                         false, NULL);
 909         if (status != I40E_SUCCESS)
 910                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 911 }
 912
 913 static void
 914 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 915 {
 916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918         struct i40e_vsi *vsi = pf->main_vsi;
 919         int ret;
 920
 921         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 922         if (ret != I40E_SUCCESS)
 923                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 924 }
 925
 926 static void
 927 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 928 {
 929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 931         struct i40e_vsi *vsi = pf->main_vsi;
 932         int ret;
 933
 934         if (dev->data->promiscuous == 1)
 935                 return; /* must remain in all_multicast mode */
 936
 937         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 938                                 vsi->seid, FALSE, NULL);
 939         if (ret != I40E_SUCCESS)
 940                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 941 }
 942
 943 /*
 944  * Set device link up.
 945  */
 946 static int
 947 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 948 {
 949         /* re-apply link speed setting */
 950         return i40e_apply_link_speed(dev);
 951 }
 952
 953 /*
 954  * Set device link down.
 955  */
 956 static int
 957 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 958 {
 959         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 960         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962
 963         return i40e_phy_conf_link(hw, abilities, speed);
 964 }
 965
 966 int
 967 i40e_dev_link_update(struct rte_eth_dev *dev,
 968                      __rte_unused int wait_to_complete)
 969 {
 970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         struct i40e_link_status link_status;
 972         struct rte_eth_link link, old;
 973         int status;
 974
 975         memset(&link, 0, sizeof(link));
 976         memset(&old, 0, sizeof(old));
 977         memset(&link_status, 0, sizeof(link_status));
 978         rte_i40e_dev_atomic_read_link_status(dev, &old);
 979
 980         /* Get link status information from hardware */
 981         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 982         if (status != I40E_SUCCESS) {
 983                 link.link_speed = ETH_LINK_SPEED_100;
 984                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 985                 PMD_DRV_LOG(ERR, "Failed to get link info");
 986                 goto out;
 987         }
 988
 989         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 990
 991         if (!link.link_status)
 992                 goto out;
 993
 994         /* i40e uses full duplex only */
 995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 996
 997         /* Parse the link status */
 998         switch (link_status.link_speed) {
 999         case I40E_LINK_SPEED_100MB:
1000                 link.link_speed = ETH_LINK_SPEED_100;
1001                 break;
1002         case I40E_LINK_SPEED_1GB:
1003                 link.link_speed = ETH_LINK_SPEED_1000;
1004                 break;
1005         case I40E_LINK_SPEED_10GB:
1006                 link.link_speed = ETH_LINK_SPEED_10G;
1007                 break;
1008         case I40E_LINK_SPEED_20GB:
1009                 link.link_speed = ETH_LINK_SPEED_20G;
1010                 break;
1011         case I40E_LINK_SPEED_40GB:
1012                 link.link_speed = ETH_LINK_SPEED_40G;
1013                 break;
1014         default:
1015                 link.link_speed = ETH_LINK_SPEED_100;
1016                 break;
1017         }
1018
1019 out:
1020         rte_i40e_dev_atomic_write_link_status(dev, &link);
1021         if (link.link_status == old.link_status)
1022                 return -1;
1023
1024         return 0;
1025 }
1026
1027 /* Get all the statistics of a VSI */
1028 void
1029 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1030 {
1031         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1032         struct i40e_eth_stats *nes = &vsi->eth_stats;
1033         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1034         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1035
1036         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1037                             vsi->offset_loaded, &oes->rx_bytes,
1038                             &nes->rx_bytes);
1039         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1040                             vsi->offset_loaded, &oes->rx_unicast,
1041                             &nes->rx_unicast);
1042         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1043                             vsi->offset_loaded, &oes->rx_multicast,
1044                             &nes->rx_multicast);
1045         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1046                             vsi->offset_loaded, &oes->rx_broadcast,
1047                             &nes->rx_broadcast);
1048         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1049                             &oes->rx_discards, &nes->rx_discards);
1050         /* GLV_REPC not supported */
1051         /* GLV_RMPC not supported */
1052         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1053                             &oes->rx_unknown_protocol,
1054                             &nes->rx_unknown_protocol);
1055         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1056                             vsi->offset_loaded, &oes->tx_bytes,
1057                             &nes->tx_bytes);
1058         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1059                             vsi->offset_loaded, &oes->tx_unicast,
1060                             &nes->tx_unicast);
1061         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1062                             vsi->offset_loaded, &oes->tx_multicast,
1063                             &nes->tx_multicast);
1064         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1065                             vsi->offset_loaded,  &oes->tx_broadcast,
1066                             &nes->tx_broadcast);
1067         /* GLV_TDPC not supported */
1068         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1069                             &oes->tx_errors, &nes->tx_errors);
1070         vsi->offset_loaded = true;
1071
1072         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1073                     vsi->vsi_id);
1074         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1075         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1076         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1077         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1078         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1079         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1080                     nes->rx_unknown_protocol);
1081         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1082         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1083         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1084         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1085         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1086         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1087         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1088                     vsi->vsi_id);
1089 }
1090
1091 /* Get all statistics of a port */
1092 static void
1093 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1094 {
1095         uint32_t i;
1096         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1097         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1099         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1100
1101         /* Get statistics of struct i40e_eth_stats */
1102         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1103                             I40E_GLPRT_GORCL(hw->port),
1104                             pf->offset_loaded, &os->eth.rx_bytes,
1105                             &ns->eth.rx_bytes);
1106         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1107                             I40E_GLPRT_UPRCL(hw->port),
1108                             pf->offset_loaded, &os->eth.rx_unicast,
1109                             &ns->eth.rx_unicast);
1110         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1111                             I40E_GLPRT_MPRCL(hw->port),
1112                             pf->offset_loaded, &os->eth.rx_multicast,
1113                             &ns->eth.rx_multicast);
1114         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1115                             I40E_GLPRT_BPRCL(hw->port),
1116                             pf->offset_loaded, &os->eth.rx_broadcast,
1117                             &ns->eth.rx_broadcast);
1118         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1119                             pf->offset_loaded, &os->eth.rx_discards,
1120                             &ns->eth.rx_discards);
1121         /* GLPRT_REPC not supported */
1122         /* GLPRT_RMPC not supported */
1123         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1124                             pf->offset_loaded,
1125                             &os->eth.rx_unknown_protocol,
1126                             &ns->eth.rx_unknown_protocol);
1127         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1128                             I40E_GLPRT_GOTCL(hw->port),
1129                             pf->offset_loaded, &os->eth.tx_bytes,
1130                             &ns->eth.tx_bytes);
1131         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1132                             I40E_GLPRT_UPTCL(hw->port),
1133                             pf->offset_loaded, &os->eth.tx_unicast,
1134                             &ns->eth.tx_unicast);
1135         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1136                             I40E_GLPRT_MPTCL(hw->port),
1137                             pf->offset_loaded, &os->eth.tx_multicast,
1138                             &ns->eth.tx_multicast);
1139         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1140                             I40E_GLPRT_BPTCL(hw->port),
1141                             pf->offset_loaded, &os->eth.tx_broadcast,
1142                             &ns->eth.tx_broadcast);
1143         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1144                             pf->offset_loaded, &os->eth.tx_discards,
1145                             &ns->eth.tx_discards);
1146         /* GLPRT_TEPC not supported */
1147
1148         /* additional port specific stats */
1149         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1150                             pf->offset_loaded, &os->tx_dropped_link_down,
1151                             &ns->tx_dropped_link_down);
1152         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1153                             pf->offset_loaded, &os->crc_errors,
1154                             &ns->crc_errors);
1155         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1156                             pf->offset_loaded, &os->illegal_bytes,
1157                             &ns->illegal_bytes);
1158         /* GLPRT_ERRBC not supported */
1159         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1160                             pf->offset_loaded, &os->mac_local_faults,
1161                             &ns->mac_local_faults);
1162         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1163                             pf->offset_loaded, &os->mac_remote_faults,
1164                             &ns->mac_remote_faults);
1165         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1166                             pf->offset_loaded, &os->rx_length_errors,
1167                             &ns->rx_length_errors);
1168         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1169                             pf->offset_loaded, &os->link_xon_rx,
1170                             &ns->link_xon_rx);
1171         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1172                             pf->offset_loaded, &os->link_xoff_rx,
1173                             &ns->link_xoff_rx);
1174         for (i = 0; i < 8; i++) {
1175                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1176                                     pf->offset_loaded,
1177                                     &os->priority_xon_rx[i],
1178                                     &ns->priority_xon_rx[i]);
1179                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1180                                     pf->offset_loaded,
1181                                     &os->priority_xoff_rx[i],
1182                                     &ns->priority_xoff_rx[i]);
1183         }
1184         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1185                             pf->offset_loaded, &os->link_xon_tx,
1186                             &ns->link_xon_tx);
1187         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1188                             pf->offset_loaded, &os->link_xoff_tx,
1189                             &ns->link_xoff_tx);
1190         for (i = 0; i < 8; i++) {
1191                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1192                                     pf->offset_loaded,
1193                                     &os->priority_xon_tx[i],
1194                                     &ns->priority_xon_tx[i]);
1195                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1196                                     pf->offset_loaded,
1197                                     &os->priority_xoff_tx[i],
1198                                     &ns->priority_xoff_tx[i]);
1199                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1200                                     pf->offset_loaded,
1201                                     &os->priority_xon_2_xoff[i],
1202                                     &ns->priority_xon_2_xoff[i]);
1203         }
1204         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1205                             I40E_GLPRT_PRC64L(hw->port),
1206                             pf->offset_loaded, &os->rx_size_64,
1207                             &ns->rx_size_64);
1208         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1209                             I40E_GLPRT_PRC127L(hw->port),
1210                             pf->offset_loaded, &os->rx_size_127,
1211                             &ns->rx_size_127);
1212         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1213                             I40E_GLPRT_PRC255L(hw->port),
1214                             pf->offset_loaded, &os->rx_size_255,
1215                             &ns->rx_size_255);
1216         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1217                             I40E_GLPRT_PRC511L(hw->port),
1218                             pf->offset_loaded, &os->rx_size_511,
1219                             &ns->rx_size_511);
1220         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1221                             I40E_GLPRT_PRC1023L(hw->port),
1222                             pf->offset_loaded, &os->rx_size_1023,
1223                             &ns->rx_size_1023);
1224         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1225                             I40E_GLPRT_PRC1522L(hw->port),
1226                             pf->offset_loaded, &os->rx_size_1522,
1227                             &ns->rx_size_1522);
1228         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1229                             I40E_GLPRT_PRC9522L(hw->port),
1230                             pf->offset_loaded, &os->rx_size_big,
1231                             &ns->rx_size_big);
1232         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1233                             pf->offset_loaded, &os->rx_undersize,
1234                             &ns->rx_undersize);
1235         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1236                             pf->offset_loaded, &os->rx_fragments,
1237                             &ns->rx_fragments);
1238         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1239                             pf->offset_loaded, &os->rx_oversize,
1240                             &ns->rx_oversize);
1241         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1242                             pf->offset_loaded, &os->rx_jabber,
1243                             &ns->rx_jabber);
1244         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1245                             I40E_GLPRT_PTC64L(hw->port),
1246                             pf->offset_loaded, &os->tx_size_64,
1247                             &ns->tx_size_64);
1248         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1249                             I40E_GLPRT_PTC127L(hw->port),
1250                             pf->offset_loaded, &os->tx_size_127,
1251                             &ns->tx_size_127);
1252         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1253                             I40E_GLPRT_PTC255L(hw->port),
1254                             pf->offset_loaded, &os->tx_size_255,
1255                             &ns->tx_size_255);
1256         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1257                             I40E_GLPRT_PTC511L(hw->port),
1258                             pf->offset_loaded, &os->tx_size_511,
1259                             &ns->tx_size_511);
1260         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1261                             I40E_GLPRT_PTC1023L(hw->port),
1262                             pf->offset_loaded, &os->tx_size_1023,
1263                             &ns->tx_size_1023);
1264         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1265                             I40E_GLPRT_PTC1522L(hw->port),
1266                             pf->offset_loaded, &os->tx_size_1522,
1267                             &ns->tx_size_1522);
1268         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1269                             I40E_GLPRT_PTC9522L(hw->port),
1270                             pf->offset_loaded, &os->tx_size_big,
1271                             &ns->tx_size_big);
1272         /* GLPRT_MSPDC not supported */
1273         /* GLPRT_XEC not supported */
1274
1275         pf->offset_loaded = true;
1276
1277         if (pf->main_vsi)
1278                 i40e_update_vsi_stats(pf->main_vsi);
1279
1280         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1281                                                 ns->eth.rx_broadcast;
1282         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1283                                                 ns->eth.tx_broadcast;
1284         stats->ibytes   = ns->eth.rx_bytes;
1285         stats->obytes   = ns->eth.tx_bytes;
1286         stats->oerrors  = ns->eth.tx_errors;
1287         stats->imcasts  = ns->eth.rx_multicast;
1288
1289         /* Rx Errors */
1290         stats->ibadcrc  = ns->crc_errors;
1291         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1292                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1293         stats->imissed  = ns->eth.rx_discards;
1294         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1295
1296         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1297         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1298         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1299         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1300         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1301         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1302         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1303                     ns->eth.rx_unknown_protocol);
1304         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1305         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1306         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1307         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1308         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1309         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1310
1311         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1312                     ns->tx_dropped_link_down);
1313         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1314         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1315                     ns->illegal_bytes);
1316         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1317         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1318                     ns->mac_local_faults);
1319         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1320                     ns->mac_remote_faults);
1321         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1322                     ns->rx_length_errors);
1323         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1324         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1325         for (i = 0; i < 8; i++) {
1326                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1327                                 i, ns->priority_xon_rx[i]);
1328                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1329                                 i, ns->priority_xoff_rx[i]);
1330         }
1331         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1332         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1333         for (i = 0; i < 8; i++) {
1334                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1335                                 i, ns->priority_xon_tx[i]);
1336                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1337                                 i, ns->priority_xoff_tx[i]);
1338                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1339                                 i, ns->priority_xon_2_xoff[i]);
1340         }
1341         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1342         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1343         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1344         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1345         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1346         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1347         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1348         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1349         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1350         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1351         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1352         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1353         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1354         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1355         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1356         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1357         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1358         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1359         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1360                         ns->mac_short_packet_dropped);
1361         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1362                     ns->checksum_error);
1363         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1364 }
1365
1366 /* Reset the statistics */
1367 static void
1368 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1369 {
1370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1371
1372         /* It results in reloading the start point of each counter */
1373         pf->offset_loaded = false;
1374 }
1375
1376 static int
1377 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1378                                  __rte_unused uint16_t queue_id,
1379                                  __rte_unused uint8_t stat_idx,
1380                                  __rte_unused uint8_t is_rx)
1381 {
1382         PMD_INIT_FUNC_TRACE();
1383
1384         return -ENOSYS;
1385 }
1386
1387 static void
1388 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1389 {
1390         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1391         struct i40e_vsi *vsi = pf->main_vsi;
1392
1393         dev_info->max_rx_queues = vsi->nb_qps;
1394         dev_info->max_tx_queues = vsi->nb_qps;
1395         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1396         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1397         dev_info->max_mac_addrs = vsi->max_macaddrs;
1398         dev_info->max_vfs = dev->pci_dev->max_vfs;
1399         dev_info->rx_offload_capa =
1400                 DEV_RX_OFFLOAD_VLAN_STRIP |
1401                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1402                 DEV_RX_OFFLOAD_UDP_CKSUM |
1403                 DEV_RX_OFFLOAD_TCP_CKSUM;
1404         dev_info->tx_offload_capa =
1405                 DEV_TX_OFFLOAD_VLAN_INSERT |
1406                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1407                 DEV_TX_OFFLOAD_UDP_CKSUM |
1408                 DEV_TX_OFFLOAD_TCP_CKSUM |
1409                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1410
1411         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1412                 .rx_thresh = {
1413                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1414                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1415                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1416                 },
1417                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1418                 .rx_drop_en = 0,
1419         };
1420
1421         dev_info->default_txconf = (struct rte_eth_txconf) {
1422                 .tx_thresh = {
1423                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1424                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1425                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1426                 },
1427                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1428                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1429                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1430         };
1431
1432 }
1433
1434 static int
1435 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1436 {
1437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438         struct i40e_vsi *vsi = pf->main_vsi;
1439         PMD_INIT_FUNC_TRACE();
1440
1441         if (on)
1442                 return i40e_vsi_add_vlan(vsi, vlan_id);
1443         else
1444                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1445 }
1446
1447 static void
1448 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1449                    __rte_unused uint16_t tpid)
1450 {
1451         PMD_INIT_FUNC_TRACE();
1452 }
1453
1454 static void
1455 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1456 {
1457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1458         struct i40e_vsi *vsi = pf->main_vsi;
1459
1460         if (mask & ETH_VLAN_STRIP_MASK) {
1461                 /* Enable or disable VLAN stripping */
1462                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1463                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1464                 else
1465                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1466         }
1467
1468         if (mask & ETH_VLAN_EXTEND_MASK) {
1469                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1470                         i40e_vsi_config_double_vlan(vsi, TRUE);
1471                 else
1472                         i40e_vsi_config_double_vlan(vsi, FALSE);
1473         }
1474 }
1475
1476 static void
1477 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1478                           __rte_unused uint16_t queue,
1479                           __rte_unused int on)
1480 {
1481         PMD_INIT_FUNC_TRACE();
1482 }
1483
1484 static int
1485 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1486 {
1487         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1488         struct i40e_vsi *vsi = pf->main_vsi;
1489         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1490         struct i40e_vsi_vlan_pvid_info info;
1491
1492         memset(&info, 0, sizeof(info));
1493         info.on = on;
1494         if (info.on)
1495                 info.config.pvid = pvid;
1496         else {
1497                 info.config.reject.tagged =
1498                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1499                 info.config.reject.untagged =
1500                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1501         }
1502
1503         return i40e_vsi_vlan_pvid_set(vsi, &info);
1504 }
1505
1506 static int
1507 i40e_dev_led_on(struct rte_eth_dev *dev)
1508 {
1509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510         uint32_t mode = i40e_led_get(hw);
1511
1512         if (mode == 0)
1513                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1514
1515         return 0;
1516 }
1517
1518 static int
1519 i40e_dev_led_off(struct rte_eth_dev *dev)
1520 {
1521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1522         uint32_t mode = i40e_led_get(hw);
1523
1524         if (mode != 0)
1525                 i40e_led_set(hw, 0, false);
1526
1527         return 0;
1528 }
1529
1530 static int
1531 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1532                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1533 {
1534         PMD_INIT_FUNC_TRACE();
1535
1536         return -ENOSYS;
1537 }
1538
1539 static int
1540 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1541                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1542 {
1543         PMD_INIT_FUNC_TRACE();
1544
1545         return -ENOSYS;
1546 }
1547
1548 /* Add a MAC address, and update filters */
1549 static void
1550 i40e_macaddr_add(struct rte_eth_dev *dev,
1551                  struct ether_addr *mac_addr,
1552                  __attribute__((unused)) uint32_t index,
1553                  __attribute__((unused)) uint32_t pool)
1554 {
1555         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557         struct i40e_vsi *vsi = pf->main_vsi;
1558         struct ether_addr old_mac;
1559         int ret;
1560
1561         if (!is_valid_assigned_ether_addr(mac_addr)) {
1562                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1563                 return;
1564         }
1565
1566         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1567                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1568                 return;
1569         }
1570
1571         /* Write mac address */
1572         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1573                                         mac_addr->addr_bytes, NULL);
1574         if (ret != I40E_SUCCESS) {
1575                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1576                 return;
1577         }
1578
1579         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1580         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1581                         ETHER_ADDR_LEN);
1582
1583         ret = i40e_vsi_add_mac(vsi, mac_addr);
1584         if (ret != I40E_SUCCESS) {
1585                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1586                 return;
1587         }
1588
1589         ether_addr_copy(mac_addr, &pf->dev_addr);
1590         i40e_vsi_delete_mac(vsi, &old_mac);
1591 }
1592
1593 /* Remove a MAC address, and update filters */
1594 static void
1595 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1596 {
1597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1598         struct i40e_vsi *vsi = pf->main_vsi;
1599         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1600         struct ether_addr *macaddr;
1601         int ret;
1602         struct i40e_hw *hw =
1603                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604
1605         if (index >= vsi->max_macaddrs)
1606                 return;
1607
1608         macaddr = &(data->mac_addrs[index]);
1609         if (!is_valid_assigned_ether_addr(macaddr))
1610                 return;
1611
1612         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1613                                         hw->mac.perm_addr, NULL);
1614         if (ret != I40E_SUCCESS) {
1615                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1616                 return;
1617         }
1618
1619         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1620
1621         ret = i40e_vsi_delete_mac(vsi, macaddr);
1622         if (ret != I40E_SUCCESS)
1623                 return;
1624
1625         /* Clear device address as it has been removed */
1626         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1627                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1628 }
1629
1630 static int
1631 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1632                          struct rte_eth_rss_reta *reta_conf)
1633 {
1634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         uint32_t lut, l;
1636         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1637
1638         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1639                 if (i < max)
1640                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1641                 else
1642                         mask = (uint8_t)((reta_conf->mask_hi >>
1643                                                 (i - max)) & 0xF);
1644
1645                 if (!mask)
1646                         continue;
1647
1648                 if (mask == 0xF)
1649                         l = 0;
1650                 else
1651                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1652
1653                 for (j = 0, lut = 0; j < 4; j++) {
1654                         if (mask & (0x1 << j))
1655                                 lut |= reta_conf->reta[i + j] << (8 * j);
1656                         else
1657                                 lut |= l & (0xFF << (8 * j));
1658                 }
1659                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1660         }
1661
1662         return 0;
1663 }
1664
1665 static int
1666 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1667                         struct rte_eth_rss_reta *reta_conf)
1668 {
1669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         uint32_t lut;
1671         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1672
1673         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1674                 if (i < max)
1675                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1676                 else
1677                         mask = (uint8_t)((reta_conf->mask_hi >>
1678                                                 (i - max)) & 0xF);
1679
1680                 if (!mask)
1681                         continue;
1682
1683                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1684                 for (j = 0; j < 4; j++) {
1685                         if (mask & (0x1 << j))
1686                                 reta_conf->reta[i + j] =
1687                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1688                 }
1689         }
1690
1691         return 0;
1692 }
1693
1694 /**
1695  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1696  * @hw:   pointer to the HW structure
1697  * @mem:  pointer to mem struct to fill out
1698  * @size: size of memory requested
1699  * @alignment: what to align the allocation to
1700  **/
1701 enum i40e_status_code
1702 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1703                         struct i40e_dma_mem *mem,
1704                         u64 size,
1705                         u32 alignment)
1706 {
1707         static uint64_t id = 0;
1708         const struct rte_memzone *mz = NULL;
1709         char z_name[RTE_MEMZONE_NAMESIZE];
1710
1711         if (!mem)
1712                 return I40E_ERR_PARAM;
1713
1714         id++;
1715         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1716 #ifdef RTE_LIBRTE_XEN_DOM0
1717         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1718                                                         RTE_PGSIZE_2M);
1719 #else
1720         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1721 #endif
1722         if (!mz)
1723                 return I40E_ERR_NO_MEMORY;
1724
1725         mem->id = id;
1726         mem->size = size;
1727         mem->va = mz->addr;
1728 #ifdef RTE_LIBRTE_XEN_DOM0
1729         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1730 #else
1731         mem->pa = mz->phys_addr;
1732 #endif
1733
1734         return I40E_SUCCESS;
1735 }
1736
1737 /**
1738  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1739  * @hw:   pointer to the HW structure
1740  * @mem:  ptr to mem struct to free
1741  **/
1742 enum i40e_status_code
1743 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1744                     struct i40e_dma_mem *mem)
1745 {
1746         if (!mem || !mem->va)
1747                 return I40E_ERR_PARAM;
1748
1749         mem->va = NULL;
1750         mem->pa = (u64)0;
1751
1752         return I40E_SUCCESS;
1753 }
1754
1755 /**
1756  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1757  * @hw:   pointer to the HW structure
1758  * @mem:  pointer to mem struct to fill out
1759  * @size: size of memory requested
1760  **/
1761 enum i40e_status_code
1762 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1763                          struct i40e_virt_mem *mem,
1764                          u32 size)
1765 {
1766         if (!mem)
1767                 return I40E_ERR_PARAM;
1768
1769         mem->size = size;
1770         mem->va = rte_zmalloc("i40e", size, 0);
1771
1772         if (mem->va)
1773                 return I40E_SUCCESS;
1774         else
1775                 return I40E_ERR_NO_MEMORY;
1776 }
1777
1778 /**
1779  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1780  * @hw:   pointer to the HW structure
1781  * @mem:  pointer to mem struct to free
1782  **/
1783 enum i40e_status_code
1784 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1785                      struct i40e_virt_mem *mem)
1786 {
1787         if (!mem)
1788                 return I40E_ERR_PARAM;
1789
1790         rte_free(mem->va);
1791         mem->va = NULL;
1792
1793         return I40E_SUCCESS;
1794 }
1795
1796 void
1797 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1798 {
1799         rte_spinlock_init(&sp->spinlock);
1800 }
1801
1802 void
1803 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1804 {
1805         rte_spinlock_lock(&sp->spinlock);
1806 }
1807
1808 void
1809 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1810 {
1811         rte_spinlock_unlock(&sp->spinlock);
1812 }
1813
1814 void
1815 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1816 {
1817         return;
1818 }
1819
1820 /**
1821  * Get the hardware capabilities, which will be parsed
1822  * and saved into struct i40e_hw.
1823  */
1824 static int
1825 i40e_get_cap(struct i40e_hw *hw)
1826 {
1827         struct i40e_aqc_list_capabilities_element_resp *buf;
1828         uint16_t len, size = 0;
1829         int ret;
1830
1831         /* Calculate a huge enough buff for saving response data temporarily */
1832         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1833                                                 I40E_MAX_CAP_ELE_NUM;
1834         buf = rte_zmalloc("i40e", len, 0);
1835         if (!buf) {
1836                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1837                 return I40E_ERR_NO_MEMORY;
1838         }
1839
1840         /* Get, parse the capabilities and save it to hw */
1841         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1842                         i40e_aqc_opc_list_func_capabilities, NULL);
1843         if (ret != I40E_SUCCESS)
1844                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1845
1846         /* Free the temporary buffer after being used */
1847         rte_free(buf);
1848
1849         return ret;
1850 }
1851
1852 static int
1853 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1854 {
1855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1856         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1857         uint16_t sum_queues = 0, sum_vsis;
1858
1859         /* First check if FW support SRIOV */
1860         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1861                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1862                 return -EINVAL;
1863         }
1864
1865         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1866         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1867         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1868         /* Allocate queues for pf */
1869         if (hw->func_caps.rss) {
1870                 pf->flags |= I40E_FLAG_RSS;
1871                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1872                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1873                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1874         } else
1875                 pf->lan_nb_qps = 1;
1876         sum_queues = pf->lan_nb_qps;
1877         /* Default VSI is not counted in */
1878         sum_vsis = 0;
1879         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1880
1881         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1882                 pf->flags |= I40E_FLAG_SRIOV;
1883                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1884                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1885                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1886                                      "max supported %u.",
1887                                      dev->pci_dev->max_vfs,
1888                                      hw->func_caps.num_vfs);
1889                         return -EINVAL;
1890                 }
1891                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1892                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1893                                      "max support %u queues.",
1894                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1895                         return -EINVAL;
1896                 }
1897                 pf->vf_num = dev->pci_dev->max_vfs;
1898                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1899                 sum_vsis   += pf->vf_num;
1900                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1901                              pf->vf_num, pf->vf_nb_qps);
1902         } else
1903                 pf->vf_num = 0;
1904
1905         if (hw->func_caps.vmdq) {
1906                 pf->flags |= I40E_FLAG_VMDQ;
1907                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1908                 sum_queues += pf->vmdq_nb_qps;
1909                 sum_vsis += 1;
1910                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1911         }
1912
1913         if (hw->func_caps.fd) {
1914                 pf->flags |= I40E_FLAG_FDIR;
1915                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1916                 /**
1917                  * Each flow director consumes one VSI and one queue,
1918                  * but can't calculate out predictably here.
1919                  */
1920         }
1921
1922         if (sum_vsis > pf->max_num_vsi ||
1923                 sum_queues > hw->func_caps.num_rx_qp) {
1924                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1925                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1926                              pf->max_num_vsi, sum_vsis);
1927                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1928                              hw->func_caps.num_rx_qp, sum_queues);
1929                 return -EINVAL;
1930         }
1931
1932         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1933          * cause */
1934         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1935                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1936                              sum_vsis, hw->func_caps.num_msix_vectors);
1937                 return -EINVAL;
1938         }
1939         return I40E_SUCCESS;
1940 }
1941
1942 static int
1943 i40e_pf_get_switch_config(struct i40e_pf *pf)
1944 {
1945         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1946         struct i40e_aqc_get_switch_config_resp *switch_config;
1947         struct i40e_aqc_switch_config_element_resp *element;
1948         uint16_t start_seid = 0, num_reported;
1949         int ret;
1950
1951         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1952                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1953         if (!switch_config) {
1954                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1955                 return -ENOMEM;
1956         }
1957
1958         /* Get the switch configurations */
1959         ret = i40e_aq_get_switch_config(hw, switch_config,
1960                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1961         if (ret != I40E_SUCCESS) {
1962                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1963                 goto fail;
1964         }
1965         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1966         if (num_reported != 1) { /* The number should be 1 */
1967                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1968                 goto fail;
1969         }
1970
1971         /* Parse the switch configuration elements */
1972         element = &(switch_config->element[0]);
1973         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1974                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1975                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1976         } else
1977                 PMD_DRV_LOG(INFO, "Unknown element type");
1978
1979 fail:
1980         rte_free(switch_config);
1981
1982         return ret;
1983 }
1984
1985 static int
1986 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1987                         uint32_t num)
1988 {
1989         struct pool_entry *entry;
1990
1991         if (pool == NULL || num == 0)
1992                 return -EINVAL;
1993
1994         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1995         if (entry == NULL) {
1996                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1997                 return -ENOMEM;
1998         }
1999
2000         /* queue heap initialize */
2001         pool->num_free = num;
2002         pool->num_alloc = 0;
2003         pool->base = base;
2004         LIST_INIT(&pool->alloc_list);
2005         LIST_INIT(&pool->free_list);
2006
2007         /* Initialize element  */
2008         entry->base = 0;
2009         entry->len = num;
2010
2011         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2012         return 0;
2013 }
2014
2015 static void
2016 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2017 {
2018         struct pool_entry *entry;
2019
2020         if (pool == NULL)
2021                 return;
2022
2023         LIST_FOREACH(entry, &pool->alloc_list, next) {
2024                 LIST_REMOVE(entry, next);
2025                 rte_free(entry);
2026         }
2027
2028         LIST_FOREACH(entry, &pool->free_list, next) {
2029                 LIST_REMOVE(entry, next);
2030                 rte_free(entry);
2031         }
2032
2033         pool->num_free = 0;
2034         pool->num_alloc = 0;
2035         pool->base = 0;
2036         LIST_INIT(&pool->alloc_list);
2037         LIST_INIT(&pool->free_list);
2038 }
2039
2040 static int
2041 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2042                        uint32_t base)
2043 {
2044         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2045         uint32_t pool_offset;
2046         int insert;
2047
2048         if (pool == NULL) {
2049                 PMD_DRV_LOG(ERR, "Invalid parameter");
2050                 return -EINVAL;
2051         }
2052
2053         pool_offset = base - pool->base;
2054         /* Lookup in alloc list */
2055         LIST_FOREACH(entry, &pool->alloc_list, next) {
2056                 if (entry->base == pool_offset) {
2057                         valid_entry = entry;
2058                         LIST_REMOVE(entry, next);
2059                         break;
2060                 }
2061         }
2062
2063         /* Not find, return */
2064         if (valid_entry == NULL) {
2065                 PMD_DRV_LOG(ERR, "Failed to find entry");
2066                 return -EINVAL;
2067         }
2068
2069         /**
2070          * Found it, move it to free list  and try to merge.
2071          * In order to make merge easier, always sort it by qbase.
2072          * Find adjacent prev and last entries.
2073          */
2074         prev = next = NULL;
2075         LIST_FOREACH(entry, &pool->free_list, next) {
2076                 if (entry->base > valid_entry->base) {
2077                         next = entry;
2078                         break;
2079                 }
2080                 prev = entry;
2081         }
2082
2083         insert = 0;
2084         /* Try to merge with next one*/
2085         if (next != NULL) {
2086                 /* Merge with next one */
2087                 if (valid_entry->base + valid_entry->len == next->base) {
2088                         next->base = valid_entry->base;
2089                         next->len += valid_entry->len;
2090                         rte_free(valid_entry);
2091                         valid_entry = next;
2092                         insert = 1;
2093                 }
2094         }
2095
2096         if (prev != NULL) {
2097                 /* Merge with previous one */
2098                 if (prev->base + prev->len == valid_entry->base) {
2099                         prev->len += valid_entry->len;
2100                         /* If it merge with next one, remove next node */
2101                         if (insert == 1) {
2102                                 LIST_REMOVE(valid_entry, next);
2103                                 rte_free(valid_entry);
2104                         } else {
2105                                 rte_free(valid_entry);
2106                                 insert = 1;
2107                         }
2108                 }
2109         }
2110
2111         /* Not find any entry to merge, insert */
2112         if (insert == 0) {
2113                 if (prev != NULL)
2114                         LIST_INSERT_AFTER(prev, valid_entry, next);
2115                 else if (next != NULL)
2116                         LIST_INSERT_BEFORE(next, valid_entry, next);
2117                 else /* It's empty list, insert to head */
2118                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2119         }
2120
2121         pool->num_free += valid_entry->len;
2122         pool->num_alloc -= valid_entry->len;
2123
2124         return 0;
2125 }
2126
2127 static int
2128 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2129                        uint16_t num)
2130 {
2131         struct pool_entry *entry, *valid_entry;
2132
2133         if (pool == NULL || num == 0) {
2134                 PMD_DRV_LOG(ERR, "Invalid parameter");
2135                 return -EINVAL;
2136         }
2137
2138         if (pool->num_free < num) {
2139                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2140                             num, pool->num_free);
2141                 return -ENOMEM;
2142         }
2143
2144         valid_entry = NULL;
2145         /* Lookup  in free list and find most fit one */
2146         LIST_FOREACH(entry, &pool->free_list, next) {
2147                 if (entry->len >= num) {
2148                         /* Find best one */
2149                         if (entry->len == num) {
2150                                 valid_entry = entry;
2151                                 break;
2152                         }
2153                         if (valid_entry == NULL || valid_entry->len > entry->len)
2154                                 valid_entry = entry;
2155                 }
2156         }
2157
2158         /* Not find one to satisfy the request, return */
2159         if (valid_entry == NULL) {
2160                 PMD_DRV_LOG(ERR, "No valid entry found");
2161                 return -ENOMEM;
2162         }
2163         /**
2164          * The entry have equal queue number as requested,
2165          * remove it from alloc_list.
2166          */
2167         if (valid_entry->len == num) {
2168                 LIST_REMOVE(valid_entry, next);
2169         } else {
2170                 /**
2171                  * The entry have more numbers than requested,
2172                  * create a new entry for alloc_list and minus its
2173                  * queue base and number in free_list.
2174                  */
2175                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2176                 if (entry == NULL) {
2177                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2178                                     "resource pool");
2179                         return -ENOMEM;
2180                 }
2181                 entry->base = valid_entry->base;
2182                 entry->len = num;
2183                 valid_entry->base += num;
2184                 valid_entry->len -= num;
2185                 valid_entry = entry;
2186         }
2187
2188         /* Insert it into alloc list, not sorted */
2189         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2190
2191         pool->num_free -= valid_entry->len;
2192         pool->num_alloc += valid_entry->len;
2193
2194         return (valid_entry->base + pool->base);
2195 }
2196
2197 /**
2198  * bitmap_is_subset - Check whether src2 is subset of src1
2199  **/
2200 static inline int
2201 bitmap_is_subset(uint8_t src1, uint8_t src2)
2202 {
2203         return !((src1 ^ src2) & src2);
2204 }
2205
2206 static int
2207 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2208 {
2209         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2210
2211         /* If DCB is not supported, only default TC is supported */
2212         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2213                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2214                 return -EINVAL;
2215         }
2216
2217         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2218                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2219                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2220                             enabled_tcmap);
2221                 return -EINVAL;
2222         }
2223         return I40E_SUCCESS;
2224 }
2225
2226 int
2227 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2228                                 struct i40e_vsi_vlan_pvid_info *info)
2229 {
2230         struct i40e_hw *hw;
2231         struct i40e_vsi_context ctxt;
2232         uint8_t vlan_flags = 0;
2233         int ret;
2234
2235         if (vsi == NULL || info == NULL) {
2236                 PMD_DRV_LOG(ERR, "invalid parameters");
2237                 return I40E_ERR_PARAM;
2238         }
2239
2240         if (info->on) {
2241                 vsi->info.pvid = info->config.pvid;
2242                 /**
2243                  * If insert pvid is enabled, only tagged pkts are
2244                  * allowed to be sent out.
2245                  */
2246                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2247                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2248         } else {
2249                 vsi->info.pvid = 0;
2250                 if (info->config.reject.tagged == 0)
2251                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2252
2253                 if (info->config.reject.untagged == 0)
2254                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2255         }
2256         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2257                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2258         vsi->info.port_vlan_flags |= vlan_flags;
2259         vsi->info.valid_sections =
2260                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2261         memset(&ctxt, 0, sizeof(ctxt));
2262         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2263         ctxt.seid = vsi->seid;
2264
2265         hw = I40E_VSI_TO_HW(vsi);
2266         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2267         if (ret != I40E_SUCCESS)
2268                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2269
2270         return ret;
2271 }
2272
2273 static int
2274 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2275 {
2276         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2277         int i, ret;
2278         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2279
2280         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2281         if (ret != I40E_SUCCESS)
2282                 return ret;
2283
2284         if (!vsi->seid) {
2285                 PMD_DRV_LOG(ERR, "seid not valid");
2286                 return -EINVAL;
2287         }
2288
2289         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2290         tc_bw_data.tc_valid_bits = enabled_tcmap;
2291         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2292                 tc_bw_data.tc_bw_credits[i] =
2293                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2294
2295         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2296         if (ret != I40E_SUCCESS) {
2297                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2298                 return ret;
2299         }
2300
2301         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2302                                         sizeof(vsi->info.qs_handle));
2303         return I40E_SUCCESS;
2304 }
2305
2306 static int
2307 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2308                                  struct i40e_aqc_vsi_properties_data *info,
2309                                  uint8_t enabled_tcmap)
2310 {
2311         int ret, total_tc = 0, i;
2312         uint16_t qpnum_per_tc, bsf, qp_idx;
2313
2314         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2315         if (ret != I40E_SUCCESS)
2316                 return ret;
2317
2318         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2319                 if (enabled_tcmap & (1 << i))
2320                         total_tc++;
2321         vsi->enabled_tc = enabled_tcmap;
2322
2323         /* Number of queues per enabled TC */
2324         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2325         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2326         bsf = rte_bsf32(qpnum_per_tc);
2327
2328         /* Adjust the queue number to actual queues that can be applied */
2329         vsi->nb_qps = qpnum_per_tc * total_tc;
2330
2331         /**
2332          * Configure TC and queue mapping parameters, for enabled TC,
2333          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2334          * default queue will serve it.
2335          */
2336         qp_idx = 0;
2337         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2338                 if (vsi->enabled_tc & (1 << i)) {
2339                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2340                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2341                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2342                         qp_idx += qpnum_per_tc;
2343                 } else
2344                         info->tc_mapping[i] = 0;
2345         }
2346
2347         /* Associate queue number with VSI */
2348         if (vsi->type == I40E_VSI_SRIOV) {
2349                 info->mapping_flags |=
2350                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2351                 for (i = 0; i < vsi->nb_qps; i++)
2352                         info->queue_mapping[i] =
2353                                 rte_cpu_to_le_16(vsi->base_queue + i);
2354         } else {
2355                 info->mapping_flags |=
2356                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2357                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2358         }
2359         info->valid_sections =
2360                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2361
2362         return I40E_SUCCESS;
2363 }
2364
2365 static int
2366 i40e_veb_release(struct i40e_veb *veb)
2367 {
2368         struct i40e_vsi *vsi;
2369         struct i40e_hw *hw;
2370
2371         if (veb == NULL || veb->associate_vsi == NULL)
2372                 return -EINVAL;
2373
2374         if (!TAILQ_EMPTY(&veb->head)) {
2375                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2376                 return -EACCES;
2377         }
2378
2379         vsi = veb->associate_vsi;
2380         hw = I40E_VSI_TO_HW(vsi);
2381
2382         vsi->uplink_seid = veb->uplink_seid;
2383         i40e_aq_delete_element(hw, veb->seid, NULL);
2384         rte_free(veb);
2385         vsi->veb = NULL;
2386         return I40E_SUCCESS;
2387 }
2388
2389 /* Setup a veb */
2390 static struct i40e_veb *
2391 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2392 {
2393         struct i40e_veb *veb;
2394         int ret;
2395         struct i40e_hw *hw;
2396
2397         if (NULL == pf || vsi == NULL) {
2398                 PMD_DRV_LOG(ERR, "veb setup failed, "
2399                             "associated VSI shouldn't null");
2400                 return NULL;
2401         }
2402         hw = I40E_PF_TO_HW(pf);
2403
2404         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2405         if (!veb) {
2406                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2407                 goto fail;
2408         }
2409
2410         veb->associate_vsi = vsi;
2411         TAILQ_INIT(&veb->head);
2412         veb->uplink_seid = vsi->uplink_seid;
2413
2414         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2415                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2416
2417         if (ret != I40E_SUCCESS) {
2418                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2419                             hw->aq.asq_last_status);
2420                 goto fail;
2421         }
2422
2423         /* get statistics index */
2424         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2425                                 &veb->stats_idx, NULL, NULL, NULL);
2426         if (ret != I40E_SUCCESS) {
2427                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2428                             hw->aq.asq_last_status);
2429                 goto fail;
2430         }
2431
2432         /* Get VEB bandwidth, to be implemented */
2433         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2434         vsi->uplink_seid = veb->seid;
2435
2436         return veb;
2437 fail:
2438         rte_free(veb);
2439         return NULL;
2440 }
2441
2442 int
2443 i40e_vsi_release(struct i40e_vsi *vsi)
2444 {
2445         struct i40e_pf *pf;
2446         struct i40e_hw *hw;
2447         struct i40e_vsi_list *vsi_list;
2448         int ret;
2449         struct i40e_mac_filter *f;
2450
2451         if (!vsi)
2452                 return I40E_SUCCESS;
2453
2454         pf = I40E_VSI_TO_PF(vsi);
2455         hw = I40E_VSI_TO_HW(vsi);
2456
2457         /* VSI has child to attach, release child first */
2458         if (vsi->veb) {
2459                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2460                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2461                                 return -1;
2462                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2463                 }
2464                 i40e_veb_release(vsi->veb);
2465         }
2466
2467         /* Remove all macvlan filters of the VSI */
2468         i40e_vsi_remove_all_macvlan_filter(vsi);
2469         TAILQ_FOREACH(f, &vsi->mac_list, next)
2470                 rte_free(f);
2471
2472         if (vsi->type != I40E_VSI_MAIN) {
2473                 /* Remove vsi from parent's sibling list */
2474                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2475                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2476                         return I40E_ERR_PARAM;
2477                 }
2478                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2479                                 &vsi->sib_vsi_list, list);
2480
2481                 /* Remove all switch element of the VSI */
2482                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2483                 if (ret != I40E_SUCCESS)
2484                         PMD_DRV_LOG(ERR, "Failed to delete element");
2485         }
2486         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2487
2488         if (vsi->type != I40E_VSI_SRIOV)
2489                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2490         rte_free(vsi);
2491
2492         return I40E_SUCCESS;
2493 }
2494
2495 static int
2496 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2497 {
2498         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2499         struct i40e_aqc_remove_macvlan_element_data def_filter;
2500         int ret;
2501
2502         if (vsi->type != I40E_VSI_MAIN)
2503                 return I40E_ERR_CONFIG;
2504         memset(&def_filter, 0, sizeof(def_filter));
2505         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2506                                         ETH_ADDR_LEN);
2507         def_filter.vlan_tag = 0;
2508         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2509                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2510         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2511         if (ret != I40E_SUCCESS) {
2512                 struct i40e_mac_filter *f;
2513
2514                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2515                             "macvlan filter");
2516                 /* It needs to add the permanent mac into mac list */
2517                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2518                 if (f == NULL) {
2519                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2520                         return I40E_ERR_NO_MEMORY;
2521                 }
2522                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2523                                 ETH_ADDR_LEN);
2524                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2525                 vsi->mac_num++;
2526
2527                 return ret;
2528         }
2529
2530         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2531 }
2532
2533 static int
2534 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2535 {
2536         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2537         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2538         struct i40e_hw *hw = &vsi->adapter->hw;
2539         i40e_status ret;
2540         int i;
2541
2542         memset(&bw_config, 0, sizeof(bw_config));
2543         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2544         if (ret != I40E_SUCCESS) {
2545                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2546                             hw->aq.asq_last_status);
2547                 return ret;
2548         }
2549
2550         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2551         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2552                                         &ets_sla_config, NULL);
2553         if (ret != I40E_SUCCESS) {
2554                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2555                             "configuration %u", hw->aq.asq_last_status);
2556                 return ret;
2557         }
2558
2559         /* Not store the info yet, just print out */
2560         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2561         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2562         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2563                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2564                             ets_sla_config.share_credits[i]);
2565                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2566                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2567                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2568                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2569                             (i * 4));
2570         }
2571
2572         return 0;
2573 }
2574
2575 /* Setup a VSI */
2576 struct i40e_vsi *
2577 i40e_vsi_setup(struct i40e_pf *pf,
2578                enum i40e_vsi_type type,
2579                struct i40e_vsi *uplink_vsi,
2580                uint16_t user_param)
2581 {
2582         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2583         struct i40e_vsi *vsi;
2584         int ret;
2585         struct i40e_vsi_context ctxt;
2586         struct ether_addr broadcast =
2587                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2588
2589         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2590                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2591                             "VSI link shouldn't be NULL");
2592                 return NULL;
2593         }
2594
2595         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2596                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2597                             "uplink VSI should be NULL");
2598                 return NULL;
2599         }
2600
2601         /* If uplink vsi didn't setup VEB, create one first */
2602         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2603                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2604
2605                 if (NULL == uplink_vsi->veb) {
2606                         PMD_DRV_LOG(ERR, "VEB setup failed");
2607                         return NULL;
2608                 }
2609         }
2610
2611         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2612         if (!vsi) {
2613                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2614                 return NULL;
2615         }
2616         TAILQ_INIT(&vsi->mac_list);
2617         vsi->type = type;
2618         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2619         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2620         vsi->parent_vsi = uplink_vsi;
2621         vsi->user_param = user_param;
2622         /* Allocate queues */
2623         switch (vsi->type) {
2624         case I40E_VSI_MAIN  :
2625                 vsi->nb_qps = pf->lan_nb_qps;
2626                 break;
2627         case I40E_VSI_SRIOV :
2628                 vsi->nb_qps = pf->vf_nb_qps;
2629                 break;
2630         default:
2631                 goto fail_mem;
2632         }
2633         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2634         if (ret < 0) {
2635                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2636                                 vsi->seid, ret);
2637                 goto fail_mem;
2638         }
2639         vsi->base_queue = ret;
2640
2641         /* VF has MSIX interrupt in VF range, don't allocate here */
2642         if (type != I40E_VSI_SRIOV) {
2643                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2644                 if (ret < 0) {
2645                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2646                         goto fail_queue_alloc;
2647                 }
2648                 vsi->msix_intr = ret;
2649         } else
2650                 vsi->msix_intr = 0;
2651         /* Add VSI */
2652         if (type == I40E_VSI_MAIN) {
2653                 /* For main VSI, no need to add since it's default one */
2654                 vsi->uplink_seid = pf->mac_seid;
2655                 vsi->seid = pf->main_vsi_seid;
2656                 /* Bind queues with specific MSIX interrupt */
2657                 /**
2658                  * Needs 2 interrupt at least, one for misc cause which will
2659                  * enabled from OS side, Another for queues binding the
2660                  * interrupt from device side only.
2661                  */
2662
2663                 /* Get default VSI parameters from hardware */
2664                 memset(&ctxt, 0, sizeof(ctxt));
2665                 ctxt.seid = vsi->seid;
2666                 ctxt.pf_num = hw->pf_id;
2667                 ctxt.uplink_seid = vsi->uplink_seid;
2668                 ctxt.vf_num = 0;
2669                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2670                 if (ret != I40E_SUCCESS) {
2671                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2672                         goto fail_msix_alloc;
2673                 }
2674                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2675                         sizeof(struct i40e_aqc_vsi_properties_data));
2676                 vsi->vsi_id = ctxt.vsi_number;
2677                 vsi->info.valid_sections = 0;
2678
2679                 /* Configure tc, enabled TC0 only */
2680                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2681                         I40E_SUCCESS) {
2682                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2683                         goto fail_msix_alloc;
2684                 }
2685
2686                 /* TC, queue mapping */
2687                 memset(&ctxt, 0, sizeof(ctxt));
2688                 vsi->info.valid_sections |=
2689                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2690                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2691                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2692                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2693                         sizeof(struct i40e_aqc_vsi_properties_data));
2694                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2695                                                 I40E_DEFAULT_TCMAP);
2696                 if (ret != I40E_SUCCESS) {
2697                         PMD_DRV_LOG(ERR, "Failed to configure "
2698                                     "TC queue mapping");
2699                         goto fail_msix_alloc;
2700                 }
2701                 ctxt.seid = vsi->seid;
2702                 ctxt.pf_num = hw->pf_id;
2703                 ctxt.uplink_seid = vsi->uplink_seid;
2704                 ctxt.vf_num = 0;
2705
2706                 /* Update VSI parameters */
2707                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2708                 if (ret != I40E_SUCCESS) {
2709                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2710                         goto fail_msix_alloc;
2711                 }
2712
2713                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2714                                                 sizeof(vsi->info.tc_mapping));
2715                 (void)rte_memcpy(&vsi->info.queue_mapping,
2716                                 &ctxt.info.queue_mapping,
2717                         sizeof(vsi->info.queue_mapping));
2718                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2719                 vsi->info.valid_sections = 0;
2720
2721                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2722                                 ETH_ADDR_LEN);
2723
2724                 /**
2725                  * Updating default filter settings are necessary to prevent
2726                  * reception of tagged packets.
2727                  * Some old firmware configurations load a default macvlan
2728                  * filter which accepts both tagged and untagged packets.
2729                  * The updating is to use a normal filter instead if needed.
2730                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2731                  * The firmware with correct configurations load the default
2732                  * macvlan filter which is expected and cannot be removed.
2733                  */
2734                 i40e_update_default_filter_setting(vsi);
2735         } else if (type == I40E_VSI_SRIOV) {
2736                 memset(&ctxt, 0, sizeof(ctxt));
2737                 /**
2738                  * For other VSI, the uplink_seid equals to uplink VSI's
2739                  * uplink_seid since they share same VEB
2740                  */
2741                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2742                 ctxt.pf_num = hw->pf_id;
2743                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2744                 ctxt.uplink_seid = vsi->uplink_seid;
2745                 ctxt.connection_type = 0x1;
2746                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2747
2748                 /* Configure switch ID */
2749                 ctxt.info.valid_sections |=
2750                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2751                 ctxt.info.switch_id =
2752                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2753                 /* Configure port/vlan */
2754                 ctxt.info.valid_sections |=
2755                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2756                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2757                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2758                                                 I40E_DEFAULT_TCMAP);
2759                 if (ret != I40E_SUCCESS) {
2760                         PMD_DRV_LOG(ERR, "Failed to configure "
2761                                     "TC queue mapping");
2762                         goto fail_msix_alloc;
2763                 }
2764                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2765                 ctxt.info.valid_sections |=
2766                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2767                 /**
2768                  * Since VSI is not created yet, only configure parameter,
2769                  * will add vsi below.
2770                  */
2771         }
2772         else {
2773                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2774                 goto fail_msix_alloc;
2775         }
2776
2777         if (vsi->type != I40E_VSI_MAIN) {
2778                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2779                 if (ret) {
2780                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2781                                     hw->aq.asq_last_status);
2782                         goto fail_msix_alloc;
2783                 }
2784                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2785                 vsi->info.valid_sections = 0;
2786                 vsi->seid = ctxt.seid;
2787                 vsi->vsi_id = ctxt.vsi_number;
2788                 vsi->sib_vsi_list.vsi = vsi;
2789                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2790                                 &vsi->sib_vsi_list, list);
2791         }
2792
2793         /* MAC/VLAN configuration */
2794         ret = i40e_vsi_add_mac(vsi, &broadcast);
2795         if (ret != I40E_SUCCESS) {
2796                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2797                 goto fail_msix_alloc;
2798         }
2799
2800         /* Get VSI BW information */
2801         i40e_vsi_dump_bw_config(vsi);
2802         return vsi;
2803 fail_msix_alloc:
2804         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2805 fail_queue_alloc:
2806         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2807 fail_mem:
2808         rte_free(vsi);
2809         return NULL;
2810 }
2811
2812 /* Configure vlan stripping on or off */
2813 int
2814 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2815 {
2816         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2817         struct i40e_vsi_context ctxt;
2818         uint8_t vlan_flags;
2819         int ret = I40E_SUCCESS;
2820
2821         /* Check if it has been already on or off */
2822         if (vsi->info.valid_sections &
2823                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2824                 if (on) {
2825                         if ((vsi->info.port_vlan_flags &
2826                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2827                                 return 0; /* already on */
2828                 } else {
2829                         if ((vsi->info.port_vlan_flags &
2830                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2831                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2832                                 return 0; /* already off */
2833                 }
2834         }
2835
2836         if (on)
2837                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2838         else
2839                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2840         vsi->info.valid_sections =
2841                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2842         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2843         vsi->info.port_vlan_flags |= vlan_flags;
2844         ctxt.seid = vsi->seid;
2845         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2846         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2847         if (ret)
2848                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2849                             on ? "enable" : "disable");
2850
2851         return ret;
2852 }
2853
2854 static int
2855 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2856 {
2857         struct rte_eth_dev_data *data = dev->data;
2858         int ret;
2859
2860         /* Apply vlan offload setting */
2861         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2862
2863         /* Apply double-vlan setting, not implemented yet */
2864
2865         /* Apply pvid setting */
2866         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2867                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2868         if (ret)
2869                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2870
2871         return ret;
2872 }
2873
2874 static int
2875 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2876 {
2877         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2878
2879         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2880 }
2881
2882 static int
2883 i40e_update_flow_control(struct i40e_hw *hw)
2884 {
2885 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2886         struct i40e_link_status link_status;
2887         uint32_t rxfc = 0, txfc = 0, reg;
2888         uint8_t an_info;
2889         int ret;
2890
2891         memset(&link_status, 0, sizeof(link_status));
2892         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2893         if (ret != I40E_SUCCESS) {
2894                 PMD_DRV_LOG(ERR, "Failed to get link status information");
2895                 goto write_reg; /* Disable flow control */
2896         }
2897
2898         an_info = hw->phy.link_info.an_info;
2899         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2900                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2901                 ret = I40E_ERR_NOT_READY;
2902                 goto write_reg; /* Disable flow control */
2903         }
2904         /**
2905          * If link auto negotiation is enabled, flow control needs to
2906          * be configured according to it
2907          */
2908         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2909         case I40E_LINK_PAUSE_RXTX:
2910                 rxfc = 1;
2911                 txfc = 1;
2912                 hw->fc.current_mode = I40E_FC_FULL;
2913                 break;
2914         case I40E_AQ_LINK_PAUSE_RX:
2915                 rxfc = 1;
2916                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2917                 break;
2918         case I40E_AQ_LINK_PAUSE_TX:
2919                 txfc = 1;
2920                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2921                 break;
2922         default:
2923                 hw->fc.current_mode = I40E_FC_NONE;
2924                 break;
2925         }
2926
2927 write_reg:
2928         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2929                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2930         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2931         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2932         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2933         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2934
2935         return ret;
2936 }
2937
2938 /* PF setup */
2939 static int
2940 i40e_pf_setup(struct i40e_pf *pf)
2941 {
2942         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2943         struct i40e_filter_control_settings settings;
2944         struct rte_eth_dev_data *dev_data = pf->dev_data;
2945         struct i40e_vsi *vsi;
2946         int ret;
2947
2948         /* Clear all stats counters */
2949         pf->offset_loaded = FALSE;
2950         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2951         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2952
2953         ret = i40e_pf_get_switch_config(pf);
2954         if (ret != I40E_SUCCESS) {
2955                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2956                 return ret;
2957         }
2958
2959         /* VSI setup */
2960         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2961         if (!vsi) {
2962                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2963                 return I40E_ERR_NOT_READY;
2964         }
2965         pf->main_vsi = vsi;
2966         dev_data->nb_rx_queues = vsi->nb_qps;
2967         dev_data->nb_tx_queues = vsi->nb_qps;
2968
2969         /* Configure filter control */
2970         memset(&settings, 0, sizeof(settings));
2971         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2972         /* Enable ethtype and macvlan filters */
2973         settings.enable_ethtype = TRUE;
2974         settings.enable_macvlan = TRUE;
2975         ret = i40e_set_filter_control(hw, &settings);
2976         if (ret)
2977                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2978                                                                 ret);
2979
2980         /* Update flow control according to the auto negotiation */
2981         i40e_update_flow_control(hw);
2982
2983         return I40E_SUCCESS;
2984 }
2985
2986 int
2987 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2988 {
2989         uint32_t reg;
2990         uint16_t j;
2991
2992         /**
2993          * Set or clear TX Queue Disable flags,
2994          * which is required by hardware.
2995          */
2996         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2997         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2998
2999         /* Wait until the request is finished */
3000         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3001                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3002                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3003                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3004                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3005                                                         & 0x1))) {
3006                         break;
3007                 }
3008         }
3009         if (on) {
3010                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3011                         return I40E_SUCCESS; /* already on, skip next steps */
3012
3013                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3014                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3015         } else {
3016                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3017                         return I40E_SUCCESS; /* already off, skip next steps */
3018                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3019         }
3020         /* Write the register */
3021         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3022         /* Check the result */
3023         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3024                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3025                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3026                 if (on) {
3027                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3028                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3029                                 break;
3030                 } else {
3031                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3032                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3033                                 break;
3034                 }
3035         }
3036         /* Check if it is timeout */
3037         if (j >= I40E_CHK_Q_ENA_COUNT) {
3038                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3039                             (on ? "enable" : "disable"), q_idx);
3040                 return I40E_ERR_TIMEOUT;
3041         }
3042
3043         return I40E_SUCCESS;
3044 }
3045
3046 /* Swith on or off the tx queues */
3047 static int
3048 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3049 {
3050         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3051         struct i40e_tx_queue *txq;
3052         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3053         uint16_t i;
3054         int ret;
3055
3056         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3057                 txq = dev_data->tx_queues[i];
3058                 /* Don't operate the queue if not configured or
3059                  * if starting only per queue */
3060                 if (!txq->q_set || (on && txq->tx_deferred_start))
3061                         continue;
3062                 if (on)
3063                         ret = i40e_dev_tx_queue_start(dev, i);
3064                 else
3065                         ret = i40e_dev_tx_queue_stop(dev, i);
3066                 if ( ret != I40E_SUCCESS)
3067                         return ret;
3068         }
3069
3070         return I40E_SUCCESS;
3071 }
3072
3073 int
3074 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3075 {
3076         uint32_t reg;
3077         uint16_t j;
3078
3079         /* Wait until the request is finished */
3080         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3081                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3082                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3083                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3084                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3085                         break;
3086         }
3087
3088         if (on) {
3089                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3090                         return I40E_SUCCESS; /* Already on, skip next steps */
3091                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3092         } else {
3093                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3094                         return I40E_SUCCESS; /* Already off, skip next steps */
3095                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3096         }
3097
3098         /* Write the register */
3099         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3100         /* Check the result */
3101         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3102                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3103                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3104                 if (on) {
3105                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3106                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3107                                 break;
3108                 } else {
3109                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3110                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3111                                 break;
3112                 }
3113         }
3114
3115         /* Check if it is timeout */
3116         if (j >= I40E_CHK_Q_ENA_COUNT) {
3117                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3118                             (on ? "enable" : "disable"), q_idx);
3119                 return I40E_ERR_TIMEOUT;
3120         }
3121
3122         return I40E_SUCCESS;
3123 }
3124 /* Switch on or off the rx queues */
3125 static int
3126 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3127 {
3128         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3129         struct i40e_rx_queue *rxq;
3130         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3131         uint16_t i;
3132         int ret;
3133
3134         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3135                 rxq = dev_data->rx_queues[i];
3136                 /* Don't operate the queue if not configured or
3137                  * if starting only per queue */
3138                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3139                         continue;
3140                 if (on)
3141                         ret = i40e_dev_rx_queue_start(dev, i);
3142                 else
3143                         ret = i40e_dev_rx_queue_stop(dev, i);
3144                 if (ret != I40E_SUCCESS)
3145                         return ret;
3146         }
3147
3148         return I40E_SUCCESS;
3149 }
3150
3151 /* Switch on or off all the rx/tx queues */
3152 int
3153 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3154 {
3155         int ret;
3156
3157         if (on) {
3158                 /* enable rx queues before enabling tx queues */
3159                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3160                 if (ret) {
3161                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3162                         return ret;
3163                 }
3164                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3165         } else {
3166                 /* Stop tx queues before stopping rx queues */
3167                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3168                 if (ret) {
3169                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3170                         return ret;
3171                 }
3172                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3173         }
3174
3175         return ret;
3176 }
3177
3178 /* Initialize VSI for TX */
3179 static int
3180 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3181 {
3182         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3183         struct rte_eth_dev_data *data = pf->dev_data;
3184         uint16_t i;
3185         uint32_t ret = I40E_SUCCESS;
3186
3187         for (i = 0; i < data->nb_tx_queues; i++) {
3188                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3189                 if (ret != I40E_SUCCESS)
3190                         break;
3191         }
3192
3193         return ret;
3194 }
3195
3196 /* Initialize VSI for RX */
3197 static int
3198 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3199 {
3200         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3201         struct rte_eth_dev_data *data = pf->dev_data;
3202         int ret = I40E_SUCCESS;
3203         uint16_t i;
3204
3205         i40e_pf_config_mq_rx(pf);
3206         for (i = 0; i < data->nb_rx_queues; i++) {
3207                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3208                 if (ret != I40E_SUCCESS) {
3209                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3210                                     "initialization");
3211                         break;
3212                 }
3213         }
3214
3215         return ret;
3216 }
3217
3218 /* Initialize VSI */
3219 static int
3220 i40e_vsi_init(struct i40e_vsi *vsi)
3221 {
3222         int err;
3223
3224         err = i40e_vsi_tx_init(vsi);
3225         if (err) {
3226                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3227                 return err;
3228         }
3229         err = i40e_vsi_rx_init(vsi);
3230         if (err) {
3231                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3232                 return err;
3233         }
3234
3235         return err;
3236 }
3237
3238 static void
3239 i40e_stat_update_32(struct i40e_hw *hw,
3240                    uint32_t reg,
3241                    bool offset_loaded,
3242                    uint64_t *offset,
3243                    uint64_t *stat)
3244 {
3245         uint64_t new_data;
3246
3247         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3248         if (!offset_loaded)
3249                 *offset = new_data;
3250
3251         if (new_data >= *offset)
3252                 *stat = (uint64_t)(new_data - *offset);
3253         else
3254                 *stat = (uint64_t)((new_data +
3255                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3256 }
3257
3258 static void
3259 i40e_stat_update_48(struct i40e_hw *hw,
3260                    uint32_t hireg,
3261                    uint32_t loreg,
3262                    bool offset_loaded,
3263                    uint64_t *offset,
3264                    uint64_t *stat)
3265 {
3266         uint64_t new_data;
3267
3268         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3269         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3270                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3271
3272         if (!offset_loaded)
3273                 *offset = new_data;
3274
3275         if (new_data >= *offset)
3276                 *stat = new_data - *offset;
3277         else
3278                 *stat = (uint64_t)((new_data +
3279                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3280
3281         *stat &= I40E_48_BIT_MASK;
3282 }
3283
3284 /* Disable IRQ0 */
3285 void
3286 i40e_pf_disable_irq0(struct i40e_hw *hw)
3287 {
3288         /* Disable all interrupt types */
3289         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3290         I40E_WRITE_FLUSH(hw);
3291 }
3292
3293 /* Enable IRQ0 */
3294 void
3295 i40e_pf_enable_irq0(struct i40e_hw *hw)
3296 {
3297         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3298                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3299                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3300                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3301         I40E_WRITE_FLUSH(hw);
3302 }
3303
3304 static void
3305 i40e_pf_config_irq0(struct i40e_hw *hw)
3306 {
3307         uint32_t enable;
3308
3309         /* read pending request and disable first */
3310         i40e_pf_disable_irq0(hw);
3311         /**
3312          * Enable all interrupt error options to detect possible errors,
3313          * other informative int are ignored
3314          */
3315         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3316                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3317                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3318                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3319                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3320                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3321                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3322                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3323
3324         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3325         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3326                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3327
3328         /* Link no queues with irq0 */
3329         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3330                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3331 }
3332
3333 static void
3334 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3335 {
3336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3338         int i;
3339         uint16_t abs_vf_id;
3340         uint32_t index, offset, val;
3341
3342         if (!pf->vfs)
3343                 return;
3344         /**
3345          * Try to find which VF trigger a reset, use absolute VF id to access
3346          * since the reg is global register.
3347          */
3348         for (i = 0; i < pf->vf_num; i++) {
3349                 abs_vf_id = hw->func_caps.vf_base_id + i;
3350                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3351                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3352                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3353                 /* VFR event occured */
3354                 if (val & (0x1 << offset)) {
3355                         int ret;
3356
3357                         /* Clear the event first */
3358                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3359                                                         (0x1 << offset));
3360                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3361                         /**
3362                          * Only notify a VF reset event occured,
3363                          * don't trigger another SW reset
3364                          */
3365                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3366                         if (ret != I40E_SUCCESS)
3367                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3368                 }
3369         }
3370 }
3371
3372 static void
3373 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3374 {
3375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376         struct i40e_arq_event_info info;
3377         uint16_t pending, opcode;
3378         int ret;
3379
3380         info.buf_len = I40E_AQ_BUF_SZ;
3381         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3382         if (!info.msg_buf) {
3383                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3384                 return;
3385         }
3386
3387         pending = 1;
3388         while (pending) {
3389                 ret = i40e_clean_arq_element(hw, &info, &pending);
3390
3391                 if (ret != I40E_SUCCESS) {
3392                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3393                                     "aq_err: %u", hw->aq.asq_last_status);
3394                         break;
3395                 }
3396                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3397
3398                 switch (opcode) {
3399                 case i40e_aqc_opc_send_msg_to_pf:
3400                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3401                         i40e_pf_host_handle_vf_msg(dev,
3402                                         rte_le_to_cpu_16(info.desc.retval),
3403                                         rte_le_to_cpu_32(info.desc.cookie_high),
3404                                         rte_le_to_cpu_32(info.desc.cookie_low),
3405                                         info.msg_buf,
3406                                         info.msg_len);
3407                         break;
3408                 default:
3409                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3410                                     opcode);
3411                         break;
3412                 }
3413         }
3414         rte_free(info.msg_buf);
3415 }
3416
3417 /**
3418  * Interrupt handler triggered by NIC  for handling
3419  * specific interrupt.
3420  *
3421  * @param handle
3422  *  Pointer to interrupt handle.
3423  * @param param
3424  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3425  *
3426  * @return
3427  *  void
3428  */
3429 static void
3430 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3431                            void *param)
3432 {
3433         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435         uint32_t cause, enable;
3436
3437         i40e_pf_disable_irq0(hw);
3438
3439         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3440         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3441
3442         /* Shared IRQ case, return */
3443         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3444                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3445                             "no INT event to process", hw->pf_id);
3446                 goto done;
3447         }
3448
3449         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3450                 PMD_DRV_LOG(INFO, "INT:Link status changed");
3451                 i40e_dev_link_update(dev, 0);
3452         }
3453
3454         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3455                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3456
3457         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3458                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3459
3460         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3461                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3462
3463         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3464                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3465
3466         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3467                 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3468
3469         /* Add processing func to deal with VF reset vent */
3470         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3471                 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3472                 i40e_dev_handle_vfr_event(dev);
3473         }
3474         /* Find admin queue event */
3475         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3476                 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3477                 i40e_dev_handle_aq_msg(dev);
3478         }
3479
3480 done:
3481         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3482         /* Re-enable interrupt from device side */
3483         i40e_pf_enable_irq0(hw);
3484         /* Re-enable interrupt from host side */
3485         rte_intr_enable(&(dev->pci_dev->intr_handle));
3486 }
3487
3488 static int
3489 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3490                          struct i40e_macvlan_filter *filter,
3491                          int total)
3492 {
3493         int ele_num, ele_buff_size;
3494         int num, actual_num, i;
3495         int ret = I40E_SUCCESS;
3496         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3497         struct i40e_aqc_add_macvlan_element_data *req_list;
3498
3499         if (filter == NULL  || total == 0)
3500                 return I40E_ERR_PARAM;
3501         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3502         ele_buff_size = hw->aq.asq_buf_size;
3503
3504         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3505         if (req_list == NULL) {
3506                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3507                 return I40E_ERR_NO_MEMORY;
3508         }
3509
3510         num = 0;
3511         do {
3512                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3513                 memset(req_list, 0, ele_buff_size);
3514
3515                 for (i = 0; i < actual_num; i++) {
3516                         (void)rte_memcpy(req_list[i].mac_addr,
3517                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3518                         req_list[i].vlan_tag =
3519                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3520                         req_list[i].flags = rte_cpu_to_le_16(\
3521                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3522                         req_list[i].queue_number = 0;
3523                 }
3524
3525                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3526                                                 actual_num, NULL);
3527                 if (ret != I40E_SUCCESS) {
3528                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3529                         goto DONE;
3530                 }
3531                 num += actual_num;
3532         } while (num < total);
3533
3534 DONE:
3535         rte_free(req_list);
3536         return ret;
3537 }
3538
3539 static int
3540 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3541                             struct i40e_macvlan_filter *filter,
3542                             int total)
3543 {
3544         int ele_num, ele_buff_size;
3545         int num, actual_num, i;
3546         int ret = I40E_SUCCESS;
3547         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3548         struct i40e_aqc_remove_macvlan_element_data *req_list;
3549
3550         if (filter == NULL  || total == 0)
3551                 return I40E_ERR_PARAM;
3552
3553         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3554         ele_buff_size = hw->aq.asq_buf_size;
3555
3556         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3557         if (req_list == NULL) {
3558                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3559                 return I40E_ERR_NO_MEMORY;
3560         }
3561
3562         num = 0;
3563         do {
3564                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3565                 memset(req_list, 0, ele_buff_size);
3566
3567                 for (i = 0; i < actual_num; i++) {
3568                         (void)rte_memcpy(req_list[i].mac_addr,
3569                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3570                         req_list[i].vlan_tag =
3571                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3572                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3573                 }
3574
3575                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3576                                                 actual_num, NULL);
3577                 if (ret != I40E_SUCCESS) {
3578                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3579                         goto DONE;
3580                 }
3581                 num += actual_num;
3582         } while (num < total);
3583
3584 DONE:
3585         rte_free(req_list);
3586         return ret;
3587 }
3588
3589 /* Find out specific MAC filter */
3590 static struct i40e_mac_filter *
3591 i40e_find_mac_filter(struct i40e_vsi *vsi,
3592                          struct ether_addr *macaddr)
3593 {
3594         struct i40e_mac_filter *f;
3595
3596         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3597                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3598                         return f;
3599         }
3600
3601         return NULL;
3602 }
3603
3604 static bool
3605 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3606                          uint16_t vlan_id)
3607 {
3608         uint32_t vid_idx, vid_bit;
3609
3610         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3611         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3612
3613         if (vsi->vfta[vid_idx] & vid_bit)
3614                 return 1;
3615         else
3616                 return 0;
3617 }
3618
3619 static void
3620 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3621                          uint16_t vlan_id, bool on)
3622 {
3623         uint32_t vid_idx, vid_bit;
3624
3625 #define UINT32_BIT_MASK      0x1F
3626 #define VALID_VLAN_BIT_MASK  0xFFF
3627         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3628          *  element first, then find the bits it belongs to
3629          */
3630         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3631                   sizeof(uint32_t));
3632         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3633
3634         if (on)
3635                 vsi->vfta[vid_idx] |= vid_bit;
3636         else
3637                 vsi->vfta[vid_idx] &= ~vid_bit;
3638 }
3639
3640 /**
3641  * Find all vlan options for specific mac addr,
3642  * return with actual vlan found.
3643  */
3644 static inline int
3645 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3646                            struct i40e_macvlan_filter *mv_f,
3647                            int num, struct ether_addr *addr)
3648 {
3649         int i;
3650         uint32_t j, k;
3651
3652         /**
3653          * Not to use i40e_find_vlan_filter to decrease the loop time,
3654          * although the code looks complex.
3655           */
3656         if (num < vsi->vlan_num)
3657                 return I40E_ERR_PARAM;
3658
3659         i = 0;
3660         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3661                 if (vsi->vfta[j]) {
3662                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3663                                 if (vsi->vfta[j] & (1 << k)) {
3664                                         if (i > num - 1) {
3665                                                 PMD_DRV_LOG(ERR, "vlan number "
3666                                                             "not match");
3667                                                 return I40E_ERR_PARAM;
3668                                         }
3669                                         (void)rte_memcpy(&mv_f[i].macaddr,
3670                                                         addr, ETH_ADDR_LEN);
3671                                         mv_f[i].vlan_id =
3672                                                 j * I40E_UINT32_BIT_SIZE + k;
3673                                         i++;
3674                                 }
3675                         }
3676                 }
3677         }
3678         return I40E_SUCCESS;
3679 }
3680
3681 static inline int
3682 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3683                            struct i40e_macvlan_filter *mv_f,
3684                            int num,
3685                            uint16_t vlan)
3686 {
3687         int i = 0;
3688         struct i40e_mac_filter *f;
3689
3690         if (num < vsi->mac_num)
3691                 return I40E_ERR_PARAM;
3692
3693         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3694                 if (i > num - 1) {
3695                         PMD_DRV_LOG(ERR, "buffer number not match");
3696                         return I40E_ERR_PARAM;
3697                 }
3698                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3699                 mv_f[i].vlan_id = vlan;
3700                 i++;
3701         }
3702
3703         return I40E_SUCCESS;
3704 }
3705
3706 static int
3707 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3708 {
3709         int i, num;
3710         struct i40e_mac_filter *f;
3711         struct i40e_macvlan_filter *mv_f;
3712         int ret = I40E_SUCCESS;
3713
3714         if (vsi == NULL || vsi->mac_num == 0)
3715                 return I40E_ERR_PARAM;
3716
3717         /* Case that no vlan is set */
3718         if (vsi->vlan_num == 0)
3719                 num = vsi->mac_num;
3720         else
3721                 num = vsi->mac_num * vsi->vlan_num;
3722
3723         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3724         if (mv_f == NULL) {
3725                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3726                 return I40E_ERR_NO_MEMORY;
3727         }
3728
3729         i = 0;
3730         if (vsi->vlan_num == 0) {
3731                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3732                         (void)rte_memcpy(&mv_f[i].macaddr,
3733                                 &f->macaddr, ETH_ADDR_LEN);
3734                         mv_f[i].vlan_id = 0;
3735                         i++;
3736                 }
3737         } else {
3738                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3739                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3740                                         vsi->vlan_num, &f->macaddr);
3741                         if (ret != I40E_SUCCESS)
3742                                 goto DONE;
3743                         i += vsi->vlan_num;
3744                 }
3745         }
3746
3747         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3748 DONE:
3749         rte_free(mv_f);
3750
3751         return ret;
3752 }
3753
3754 int
3755 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3756 {
3757         struct i40e_macvlan_filter *mv_f;
3758         int mac_num;
3759         int ret = I40E_SUCCESS;
3760
3761         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3762                 return I40E_ERR_PARAM;
3763
3764         /* If it's already set, just return */
3765         if (i40e_find_vlan_filter(vsi,vlan))
3766                 return I40E_SUCCESS;
3767
3768         mac_num = vsi->mac_num;
3769
3770         if (mac_num == 0) {
3771                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3772                 return I40E_ERR_PARAM;
3773         }
3774
3775         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3776
3777         if (mv_f == NULL) {
3778                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3779                 return I40E_ERR_NO_MEMORY;
3780         }
3781
3782         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3783
3784         if (ret != I40E_SUCCESS)
3785                 goto DONE;
3786
3787         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3788
3789         if (ret != I40E_SUCCESS)
3790                 goto DONE;
3791
3792         i40e_set_vlan_filter(vsi, vlan, 1);
3793
3794         vsi->vlan_num++;
3795         ret = I40E_SUCCESS;
3796 DONE:
3797         rte_free(mv_f);
3798         return ret;
3799 }
3800
3801 int
3802 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3803 {
3804         struct i40e_macvlan_filter *mv_f;
3805         int mac_num;
3806         int ret = I40E_SUCCESS;
3807
3808         /**
3809          * Vlan 0 is the generic filter for untagged packets
3810          * and can't be removed.
3811          */
3812         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3813                 return I40E_ERR_PARAM;
3814
3815         /* If can't find it, just return */
3816         if (!i40e_find_vlan_filter(vsi, vlan))
3817                 return I40E_ERR_PARAM;
3818
3819         mac_num = vsi->mac_num;
3820
3821         if (mac_num == 0) {
3822                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3823                 return I40E_ERR_PARAM;
3824         }
3825
3826         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3827
3828         if (mv_f == NULL) {
3829                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3830                 return I40E_ERR_NO_MEMORY;
3831         }
3832
3833         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3834
3835         if (ret != I40E_SUCCESS)
3836                 goto DONE;
3837
3838         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3839
3840         if (ret != I40E_SUCCESS)
3841                 goto DONE;
3842
3843         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3844         if (vsi->vlan_num == 1) {
3845                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3846                 if (ret != I40E_SUCCESS)
3847                         goto DONE;
3848
3849                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3850                 if (ret != I40E_SUCCESS)
3851                         goto DONE;
3852         }
3853
3854         i40e_set_vlan_filter(vsi, vlan, 0);
3855
3856         vsi->vlan_num--;
3857         ret = I40E_SUCCESS;
3858 DONE:
3859         rte_free(mv_f);
3860         return ret;
3861 }
3862
3863 int
3864 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3865 {
3866         struct i40e_mac_filter *f;
3867         struct i40e_macvlan_filter *mv_f;
3868         int vlan_num;
3869         int ret = I40E_SUCCESS;
3870
3871         /* If it's add and we've config it, return */
3872         f = i40e_find_mac_filter(vsi, addr);
3873         if (f != NULL)
3874                 return I40E_SUCCESS;
3875
3876         /**
3877          * If vlan_num is 0, that's the first time to add mac,
3878          * set mask for vlan_id 0.
3879          */
3880         if (vsi->vlan_num == 0) {
3881                 i40e_set_vlan_filter(vsi, 0, 1);
3882                 vsi->vlan_num = 1;
3883         }
3884
3885         vlan_num = vsi->vlan_num;
3886
3887         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3888         if (mv_f == NULL) {
3889                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3890                 return I40E_ERR_NO_MEMORY;
3891         }
3892
3893         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3894         if (ret != I40E_SUCCESS)
3895                 goto DONE;
3896
3897         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3898         if (ret != I40E_SUCCESS)
3899                 goto DONE;
3900
3901         /* Add the mac addr into mac list */
3902         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3903         if (f == NULL) {
3904                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3905                 ret = I40E_ERR_NO_MEMORY;
3906                 goto DONE;
3907         }
3908         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3909         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3910         vsi->mac_num++;
3911
3912         ret = I40E_SUCCESS;
3913 DONE:
3914         rte_free(mv_f);
3915
3916         return ret;
3917 }
3918
3919 int
3920 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3921 {
3922         struct i40e_mac_filter *f;
3923         struct i40e_macvlan_filter *mv_f;
3924         int vlan_num;
3925         int ret = I40E_SUCCESS;
3926
3927         /* Can't find it, return an error */
3928         f = i40e_find_mac_filter(vsi, addr);
3929         if (f == NULL)
3930                 return I40E_ERR_PARAM;
3931
3932         vlan_num = vsi->vlan_num;
3933         if (vlan_num == 0) {
3934                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3935                 return I40E_ERR_PARAM;
3936         }
3937         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3938         if (mv_f == NULL) {
3939                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3940                 return I40E_ERR_NO_MEMORY;
3941         }
3942
3943         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3944         if (ret != I40E_SUCCESS)
3945                 goto DONE;
3946
3947         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3948         if (ret != I40E_SUCCESS)
3949                 goto DONE;
3950
3951         /* Remove the mac addr into mac list */
3952         TAILQ_REMOVE(&vsi->mac_list, f, next);
3953         rte_free(f);
3954         vsi->mac_num--;
3955
3956         ret = I40E_SUCCESS;
3957 DONE:
3958         rte_free(mv_f);
3959         return ret;
3960 }
3961
3962 /* Configure hash enable flags for RSS */
3963 static uint64_t
3964 i40e_config_hena(uint64_t flags)
3965 {
3966         uint64_t hena = 0;
3967
3968         if (!flags)
3969                 return hena;
3970
3971         if (flags & ETH_RSS_NONF_IPV4_UDP)
3972                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3973         if (flags & ETH_RSS_NONF_IPV4_TCP)
3974                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3975         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3976                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3977         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3978                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3979         if (flags & ETH_RSS_FRAG_IPV4)
3980                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3981         if (flags & ETH_RSS_NONF_IPV6_UDP)
3982                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3983         if (flags & ETH_RSS_NONF_IPV6_TCP)
3984                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3985         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3986                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3987         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3988                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3989         if (flags & ETH_RSS_FRAG_IPV6)
3990                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3991         if (flags & ETH_RSS_L2_PAYLOAD)
3992                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3993
3994         return hena;
3995 }
3996
3997 /* Parse the hash enable flags */
3998 static uint64_t
3999 i40e_parse_hena(uint64_t flags)
4000 {
4001         uint64_t rss_hf = 0;
4002
4003         if (!flags)
4004                 return rss_hf;
4005
4006         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4007                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4008         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4009                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4010         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4011                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4012         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4013                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4014         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4015                 rss_hf |= ETH_RSS_FRAG_IPV4;
4016         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4017                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4018         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4019                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4020         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4021                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4022         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4023                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4024         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4025                 rss_hf |= ETH_RSS_FRAG_IPV6;
4026         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4027                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4028
4029         return rss_hf;
4030 }
4031
4032 /* Disable RSS */
4033 static void
4034 i40e_pf_disable_rss(struct i40e_pf *pf)
4035 {
4036         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4037         uint64_t hena;
4038
4039         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4040         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4041         hena &= ~I40E_RSS_HENA_ALL;
4042         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4043         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4044         I40E_WRITE_FLUSH(hw);
4045 }
4046
4047 static int
4048 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4049 {
4050         uint32_t *hash_key;
4051         uint8_t hash_key_len;
4052         uint64_t rss_hf;
4053         uint16_t i;
4054         uint64_t hena;
4055
4056         hash_key = (uint32_t *)(rss_conf->rss_key);
4057         hash_key_len = rss_conf->rss_key_len;
4058         if (hash_key != NULL && hash_key_len >=
4059                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4060                 /* Fill in RSS hash key */
4061                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4062                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4063         }
4064
4065         rss_hf = rss_conf->rss_hf;
4066         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4067         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4068         hena &= ~I40E_RSS_HENA_ALL;
4069         hena |= i40e_config_hena(rss_hf);
4070         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4071         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4072         I40E_WRITE_FLUSH(hw);
4073
4074         return 0;
4075 }
4076
4077 static int
4078 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4079                          struct rte_eth_rss_conf *rss_conf)
4080 {
4081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4082         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4083         uint64_t hena;
4084
4085         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4086         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4087         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4088                 if (rss_hf != 0) /* Enable RSS */
4089                         return -EINVAL;
4090                 return 0; /* Nothing to do */
4091         }
4092         /* RSS enabled */
4093         if (rss_hf == 0) /* Disable RSS */
4094                 return -EINVAL;
4095
4096         return i40e_hw_rss_hash_set(hw, rss_conf);
4097 }
4098
4099 static int
4100 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4101                            struct rte_eth_rss_conf *rss_conf)
4102 {
4103         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4105         uint64_t hena;
4106         uint16_t i;
4107
4108         if (hash_key != NULL) {
4109                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4110                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4111                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4112         }
4113         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4114         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4115         rss_conf->rss_hf = i40e_parse_hena(hena);
4116
4117         return 0;
4118 }
4119
4120 /* Configure RSS */
4121 static int
4122 i40e_pf_config_rss(struct i40e_pf *pf)
4123 {
4124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4125         struct rte_eth_rss_conf rss_conf;
4126         uint32_t i, lut = 0;
4127         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4128
4129         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4130                 if (j == num)
4131                         j = 0;
4132                 lut = (lut << 8) | (j & ((0x1 <<
4133                         hw->func_caps.rss_table_entry_width) - 1));
4134                 if ((i & 3) == 3)
4135                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4136         }
4137
4138         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4139         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4140                 i40e_pf_disable_rss(pf);
4141                 return 0;
4142         }
4143         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4144                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4145                 /* Calculate the default hash key */
4146                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4147                         rss_key_default[i] = (uint32_t)rte_rand();
4148                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4149                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4150                                                         sizeof(uint32_t);
4151         }
4152
4153         return i40e_hw_rss_hash_set(hw, &rss_conf);
4154 }
4155
4156 static int
4157 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4158 {
4159         if (!pf->dev_data->sriov.active) {
4160                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4161                 case ETH_MQ_RX_RSS:
4162                         i40e_pf_config_rss(pf);
4163                         break;
4164                 default:
4165                         i40e_pf_disable_rss(pf);
4166                         break;
4167                 }
4168         }
4169
4170         return 0;
4171 }