lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(\
 110                         __attribute__((unused)) struct eth_driver *eth_drv,
 111                         struct rte_eth_dev *eth_dev);
 112 static int i40e_dev_configure(struct rte_eth_dev *dev);
 113 static int i40e_dev_start(struct rte_eth_dev *dev);
 114 static void i40e_dev_stop(struct rte_eth_dev *dev);
 115 static void i40e_dev_close(struct rte_eth_dev *dev);
 116 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 118 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 119 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 120 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 121 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 122 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 123                                struct rte_eth_stats *stats);
 124 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 125 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 126                                             uint16_t queue_id,
 127                                             uint8_t stat_idx,
 128                                             uint8_t is_rx);
 129 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 130                               struct rte_eth_dev_info *dev_info);
 131 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 132                                 uint16_t vlan_id,
 133                                 int on);
 134 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 135 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 136 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 137                                       uint16_t queue,
 138                                       int on);
 139 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 140 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 141 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 142 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 143                               struct rte_eth_fc_conf *fc_conf);
 144 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                                        struct rte_eth_pfc_conf *pfc_conf);
 146 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 147                           struct ether_addr *mac_addr,
 148                           uint32_t index,
 149                           uint32_t pool);
 150 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 151 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 152                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 153                                     uint16_t reta_size);
 154 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 155                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 156                                    uint16_t reta_size);
 157
 158 static int i40e_get_cap(struct i40e_hw *hw);
 159 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 160 static int i40e_pf_setup(struct i40e_pf *pf);
 161 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 162 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 163 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 164                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 165 static void i40e_stat_update_48(struct i40e_hw *hw,
 166                                uint32_t hireg,
 167                                uint32_t loreg,
 168                                bool offset_loaded,
 169                                uint64_t *offset,
 170                                uint64_t *stat);
 171 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 172 static void i40e_dev_interrupt_handler(
 173                 __rte_unused struct rte_intr_handle *handle, void *param);
 174 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 175                                 uint32_t base, uint32_t num);
 176 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 177 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 178                         uint32_t base);
 179 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 180                         uint16_t num);
 181 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 182 static int i40e_veb_release(struct i40e_veb *veb);
 183 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 184                                                 struct i40e_vsi *vsi);
 185 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 186 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 187 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 188                                              struct i40e_macvlan_filter *mv_f,
 189                                              int num,
 190                                              struct ether_addr *addr);
 191 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 192                                              struct i40e_macvlan_filter *mv_f,
 193                                              int num,
 194                                              uint16_t vlan);
 195 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 196 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 197                                     struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 199                                       struct rte_eth_rss_conf *rss_conf);
 200 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 203                                 struct rte_eth_udp_tunnel *udp_tunnel);
 204 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 205                         struct rte_eth_ethertype_filter *filter,
 206                         bool add);
 207 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 211                                 enum rte_filter_type filter_type,
 212                                 enum rte_filter_op filter_op,
 213                                 void *arg);
 214 static void i40e_configure_registers(struct i40e_hw *hw);
 215 static void i40e_hw_init(struct i40e_hw *hw);
 216
 217 static struct rte_pci_id pci_id_i40e_map[] = {
 218 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 219 #include "rte_pci_dev_ids.h"
 220 { .vendor_id = 0, /* sentinel */ },
 221 };
 222
 223 static struct eth_dev_ops i40e_eth_dev_ops = {
 224         .dev_configure                = i40e_dev_configure,
 225         .dev_start                    = i40e_dev_start,
 226         .dev_stop                     = i40e_dev_stop,
 227         .dev_close                    = i40e_dev_close,
 228         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 229         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 230         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 231         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 232         .dev_set_link_up              = i40e_dev_set_link_up,
 233         .dev_set_link_down            = i40e_dev_set_link_down,
 234         .link_update                  = i40e_dev_link_update,
 235         .stats_get                    = i40e_dev_stats_get,
 236         .stats_reset                  = i40e_dev_stats_reset,
 237         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 238         .dev_infos_get                = i40e_dev_info_get,
 239         .vlan_filter_set              = i40e_vlan_filter_set,
 240         .vlan_tpid_set                = i40e_vlan_tpid_set,
 241         .vlan_offload_set             = i40e_vlan_offload_set,
 242         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 243         .vlan_pvid_set                = i40e_vlan_pvid_set,
 244         .rx_queue_start               = i40e_dev_rx_queue_start,
 245         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 246         .tx_queue_start               = i40e_dev_tx_queue_start,
 247         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 248         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 249         .rx_queue_release             = i40e_dev_rx_queue_release,
 250         .rx_queue_count               = i40e_dev_rx_queue_count,
 251         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 252         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 253         .tx_queue_release             = i40e_dev_tx_queue_release,
 254         .dev_led_on                   = i40e_dev_led_on,
 255         .dev_led_off                  = i40e_dev_led_off,
 256         .flow_ctrl_set                = i40e_flow_ctrl_set,
 257         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 258         .mac_addr_add                 = i40e_macaddr_add,
 259         .mac_addr_remove              = i40e_macaddr_remove,
 260         .reta_update                  = i40e_dev_rss_reta_update,
 261         .reta_query                   = i40e_dev_rss_reta_query,
 262         .rss_hash_update              = i40e_dev_rss_hash_update,
 263         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 264         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 265         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 266         .filter_ctrl                  = i40e_dev_filter_ctrl,
 267 };
 268
 269 static struct eth_driver rte_i40e_pmd = {
 270         {
 271                 .name = "rte_i40e_pmd",
 272                 .id_table = pci_id_i40e_map,
 273                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 274         },
 275         .eth_dev_init = eth_i40e_dev_init,
 276         .dev_private_size = sizeof(struct i40e_adapter),
 277 };
 278
 279 static inline int
 280 i40e_align_floor(int n)
 281 {
 282         if (n == 0)
 283                 return 0;
 284         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 285 }
 286
 287 static inline int
 288 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 289                                      struct rte_eth_link *link)
 290 {
 291         struct rte_eth_link *dst = link;
 292         struct rte_eth_link *src = &(dev->data->dev_link);
 293
 294         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 295                                         *(uint64_t *)src) == 0)
 296                 return -1;
 297
 298         return 0;
 299 }
 300
 301 static inline int
 302 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 303                                       struct rte_eth_link *link)
 304 {
 305         struct rte_eth_link *dst = &(dev->data->dev_link);
 306         struct rte_eth_link *src = link;
 307
 308         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 309                                         *(uint64_t *)src) == 0)
 310                 return -1;
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Driver initialization routine.
 317  * Invoked once at EAL init time.
 318  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 319  */
 320 static int
 321 rte_i40e_pmd_init(const char *name __rte_unused,
 322                   const char *params __rte_unused)
 323 {
 324         PMD_INIT_FUNC_TRACE();
 325         rte_eth_driver_register(&rte_i40e_pmd);
 326
 327         return 0;
 328 }
 329
 330 static struct rte_driver rte_i40e_driver = {
 331         .type = PMD_PDEV,
 332         .init = rte_i40e_pmd_init,
 333 };
 334
 335 PMD_REGISTER_DRIVER(rte_i40e_driver);
 336
 337 /*
 338  * Initialize registers for flexible payload, which should be set by NVM.
 339  * This should be removed from code once it is fixed in NVM.
 340  */
 341 #ifndef I40E_GLQF_ORT
 342 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 343 #endif
 344 #ifndef I40E_GLQF_PIT
 345 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 346 #endif
 347
 348 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 349 {
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 359         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 360
 361         /* GLQF_PIT Registers */
 362         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 363         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 364 }
 365
 366 static int
 367 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 368                   struct rte_eth_dev *dev)
 369 {
 370         struct rte_pci_device *pci_dev;
 371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373         struct i40e_vsi *vsi;
 374         int ret;
 375         uint32_t len;
 376         uint8_t aq_fail = 0;
 377
 378         PMD_INIT_FUNC_TRACE();
 379
 380         dev->dev_ops = &i40e_eth_dev_ops;
 381         dev->rx_pkt_burst = i40e_recv_pkts;
 382         dev->tx_pkt_burst = i40e_xmit_pkts;
 383
 384         /* for secondary processes, we don't initialise any further as primary
 385          * has already done this work. Only check we don't need a different
 386          * RX function */
 387         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 388                 if (dev->data->scattered_rx)
 389                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 390                 return 0;
 391         }
 392         pci_dev = dev->pci_dev;
 393         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 394         pf->adapter->eth_dev = dev;
 395         pf->dev_data = dev->data;
 396
 397         hw->back = I40E_PF_TO_ADAPTER(pf);
 398         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 399         if (!hw->hw_addr) {
 400                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 401                              "as address is NULL");
 402                 return -ENODEV;
 403         }
 404
 405         hw->vendor_id = pci_dev->id.vendor_id;
 406         hw->device_id = pci_dev->id.device_id;
 407         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 408         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 409         hw->bus.device = pci_dev->addr.devid;
 410         hw->bus.func = pci_dev->addr.function;
 411
 412         /* Make sure all is clean before doing PF reset */
 413         i40e_clear_hw(hw);
 414
 415         /* Initialize the hardware */
 416         i40e_hw_init(hw);
 417
 418         /* Reset here to make sure all is clean for each PF */
 419         ret = i40e_pf_reset(hw);
 420         if (ret) {
 421                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 422                 return ret;
 423         }
 424
 425         /* Initialize the shared code (base driver) */
 426         ret = i40e_init_shared_code(hw);
 427         if (ret) {
 428                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 429                 return ret;
 430         }
 431
 432         /*
 433          * To work around the NVM issue,initialize registers
 434          * for flexible payload by software.
 435          * It should be removed once issues are fixed in NVM.
 436          */
 437         i40e_flex_payload_reg_init(hw);
 438
 439         /* Initialize the parameters for adminq */
 440         i40e_init_adminq_parameter(hw);
 441         ret = i40e_init_adminq(hw);
 442         if (ret != I40E_SUCCESS) {
 443                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 444                 return -EIO;
 445         }
 446         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 447                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 448                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 449                      ((hw->nvm.version >> 12) & 0xf),
 450                      ((hw->nvm.version >> 4) & 0xff),
 451                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 452
 453         /* Disable LLDP */
 454         ret = i40e_aq_stop_lldp(hw, true, NULL);
 455         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 456                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 457
 458         /* Clear PXE mode */
 459         i40e_clear_pxe_mode(hw);
 460
 461         /*
 462          * On X710, performance number is far from the expectation on recent
 463          * firmware versions. The fix for this issue may not be integrated in
 464          * the following firmware version. So the workaround in software driver
 465          * is needed. It needs to modify the initial values of 3 internal only
 466          * registers. Note that the workaround can be removed when it is fixed
 467          * in firmware in the future.
 468          */
 469         i40e_configure_registers(hw);
 470
 471         /* Get hw capabilities */
 472         ret = i40e_get_cap(hw);
 473         if (ret != I40E_SUCCESS) {
 474                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 475                 goto err_get_capabilities;
 476         }
 477
 478         /* Initialize parameters for PF */
 479         ret = i40e_pf_parameter_init(dev);
 480         if (ret != 0) {
 481                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 482                 goto err_parameter_init;
 483         }
 484
 485         /* Initialize the queue management */
 486         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 487         if (ret < 0) {
 488                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 489                 goto err_qp_pool_init;
 490         }
 491         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 492                                 hw->func_caps.num_msix_vectors - 1);
 493         if (ret < 0) {
 494                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 495                 goto err_msix_pool_init;
 496         }
 497
 498         /* Initialize lan hmc */
 499         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 500                                 hw->func_caps.num_rx_qp, 0, 0);
 501         if (ret != I40E_SUCCESS) {
 502                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 503                 goto err_init_lan_hmc;
 504         }
 505
 506         /* Configure lan hmc */
 507         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 508         if (ret != I40E_SUCCESS) {
 509                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 510                 goto err_configure_lan_hmc;
 511         }
 512
 513         /* Get and check the mac address */
 514         i40e_get_mac_addr(hw, hw->mac.addr);
 515         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 516                 PMD_INIT_LOG(ERR, "mac address is not valid");
 517                 ret = -EIO;
 518                 goto err_get_mac_addr;
 519         }
 520         /* Copy the permanent MAC address */
 521         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 522                         (struct ether_addr *) hw->mac.perm_addr);
 523
 524         /* Disable flow control */
 525         hw->fc.requested_mode = I40E_FC_NONE;
 526         i40e_set_fc(hw, &aq_fail, TRUE);
 527
 528         /* PF setup, which includes VSI setup */
 529         ret = i40e_pf_setup(pf);
 530         if (ret) {
 531                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 532                 goto err_setup_pf_switch;
 533         }
 534
 535         vsi = pf->main_vsi;
 536
 537         /* Disable double vlan by default */
 538         i40e_vsi_config_double_vlan(vsi, FALSE);
 539
 540         if (!vsi->max_macaddrs)
 541                 len = ETHER_ADDR_LEN;
 542         else
 543                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 544
 545         /* Should be after VSI initialized */
 546         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 547         if (!dev->data->mac_addrs) {
 548                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 549                                         "for storing mac address");
 550                 goto err_mac_alloc;
 551         }
 552         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 553                                         &dev->data->mac_addrs[0]);
 554
 555         /* initialize pf host driver to setup SRIOV resource if applicable */
 556         i40e_pf_host_init(dev);
 557
 558         /* register callback func to eal lib */
 559         rte_intr_callback_register(&(pci_dev->intr_handle),
 560                 i40e_dev_interrupt_handler, (void *)dev);
 561
 562         /* configure and enable device interrupt */
 563         i40e_pf_config_irq0(hw);
 564         i40e_pf_enable_irq0(hw);
 565
 566         /* enable uio intr after callback register */
 567         rte_intr_enable(&(pci_dev->intr_handle));
 568
 569         return 0;
 570
 571 err_mac_alloc:
 572         i40e_vsi_release(pf->main_vsi);
 573 err_setup_pf_switch:
 574 err_get_mac_addr:
 575 err_configure_lan_hmc:
 576         (void)i40e_shutdown_lan_hmc(hw);
 577 err_init_lan_hmc:
 578         i40e_res_pool_destroy(&pf->msix_pool);
 579 err_msix_pool_init:
 580         i40e_res_pool_destroy(&pf->qp_pool);
 581 err_qp_pool_init:
 582 err_parameter_init:
 583 err_get_capabilities:
 584         (void)i40e_shutdown_adminq(hw);
 585
 586         return ret;
 587 }
 588
 589 static int
 590 i40e_dev_configure(struct rte_eth_dev *dev)
 591 {
 592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 593         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 594         int ret;
 595
 596         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 597                 ret = i40e_fdir_setup(pf);
 598                 if (ret != I40E_SUCCESS) {
 599                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 600                         return -ENOTSUP;
 601                 }
 602                 ret = i40e_fdir_configure(dev);
 603                 if (ret < 0) {
 604                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 605                         goto err;
 606                 }
 607         } else
 608                 i40e_fdir_teardown(pf);
 609
 610         ret = i40e_dev_init_vlan(dev);
 611         if (ret < 0)
 612                 goto err;
 613
 614         /* VMDQ setup.
 615          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 616          *  RSS setting have different requirements.
 617          *  General PMD driver call sequence are NIC init, configure,
 618          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 619          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 620          *  applicable. So, VMDQ setting has to be done before
 621          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 622          *  For RSS setting, it will try to calculate actual configured RX queue
 623          *  number, which will be available after rx_queue_setup(). dev_start()
 624          *  function is good to place RSS setup.
 625          */
 626         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 627                 ret = i40e_vmdq_setup(dev);
 628                 if (ret)
 629                         goto err;
 630         }
 631         return 0;
 632 err:
 633         i40e_fdir_teardown(pf);
 634         return ret;
 635 }
 636
 637 void
 638 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 639 {
 640         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 641         uint16_t msix_vect = vsi->msix_intr;
 642         uint16_t i;
 643
 644         for (i = 0; i < vsi->nb_qps; i++) {
 645                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 646                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 647                 rte_wmb();
 648         }
 649
 650         if (vsi->type != I40E_VSI_SRIOV) {
 651                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 652                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 653                                 msix_vect - 1), 0);
 654         } else {
 655                 uint32_t reg;
 656                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 657                         vsi->user_param + (msix_vect - 1);
 658
 659                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 660         }
 661         I40E_WRITE_FLUSH(hw);
 662 }
 663
 664 static inline uint16_t
 665 i40e_calc_itr_interval(int16_t interval)
 666 {
 667         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 668                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 669
 670         /* Convert to hardware count, as writing each 1 represents 2 us */
 671         return (interval/2);
 672 }
 673
 674 void
 675 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 676 {
 677         uint32_t val;
 678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 679         uint16_t msix_vect = vsi->msix_intr;
 680         int i;
 681
 682         for (i = 0; i < vsi->nb_qps; i++)
 683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 684
 685         /* Bind all RX queues to allocated MSIX interrupt */
 686         for (i = 0; i < vsi->nb_qps; i++) {
 687                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 688                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 689                         ((vsi->base_queue + i + 1) <<
 690                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 691                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 692                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 693
 694                 if (i == vsi->nb_qps - 1)
 695                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 696                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 697         }
 698
 699         /* Write first RX queue to Link list register as the head element */
 700         if (vsi->type != I40E_VSI_SRIOV) {
 701                 uint16_t interval =
 702                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 703
 704                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 705                                                 (vsi->base_queue <<
 706                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 707                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 708
 709                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 710                                                 msix_vect - 1), interval);
 711
 712 #ifndef I40E_GLINT_CTL
 713 #define I40E_GLINT_CTL                     0x0003F800
 714 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 715 #endif
 716                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 717                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 718                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 719         } else {
 720                 uint32_t reg;
 721
 722                 /* num_msix_vectors_vf needs to minus irq0 */
 723                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 724                         vsi->user_param + (msix_vect - 1);
 725
 726                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 727                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 728                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 729         }
 730
 731         I40E_WRITE_FLUSH(hw);
 732 }
 733
 734 static void
 735 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 736 {
 737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 738         uint16_t interval = i40e_calc_itr_interval(\
 739                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 740
 741         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 742                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 743                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 744                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 745                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 746 }
 747
 748 static void
 749 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 750 {
 751         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 752
 753         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 754 }
 755
 756 static inline uint8_t
 757 i40e_parse_link_speed(uint16_t eth_link_speed)
 758 {
 759         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 760
 761         switch (eth_link_speed) {
 762         case ETH_LINK_SPEED_40G:
 763                 link_speed = I40E_LINK_SPEED_40GB;
 764                 break;
 765         case ETH_LINK_SPEED_20G:
 766                 link_speed = I40E_LINK_SPEED_20GB;
 767                 break;
 768         case ETH_LINK_SPEED_10G:
 769                 link_speed = I40E_LINK_SPEED_10GB;
 770                 break;
 771         case ETH_LINK_SPEED_1000:
 772                 link_speed = I40E_LINK_SPEED_1GB;
 773                 break;
 774         case ETH_LINK_SPEED_100:
 775                 link_speed = I40E_LINK_SPEED_100MB;
 776                 break;
 777         }
 778
 779         return link_speed;
 780 }
 781
 782 static int
 783 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 784 {
 785         enum i40e_status_code status;
 786         struct i40e_aq_get_phy_abilities_resp phy_ab;
 787         struct i40e_aq_set_phy_config phy_conf;
 788         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 789                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 790                         I40E_AQ_PHY_FLAG_LOW_POWER;
 791         const uint8_t advt = I40E_LINK_SPEED_40GB |
 792                         I40E_LINK_SPEED_10GB |
 793                         I40E_LINK_SPEED_1GB |
 794                         I40E_LINK_SPEED_100MB;
 795         int ret = -ENOTSUP;
 796
 797         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 798                                               NULL);
 799         if (status)
 800                 return ret;
 801
 802         memset(&phy_conf, 0, sizeof(phy_conf));
 803
 804         /* bits 0-2 use the values from get_phy_abilities_resp */
 805         abilities &= ~mask;
 806         abilities |= phy_ab.abilities & mask;
 807
 808         /* update ablities and speed */
 809         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 810                 phy_conf.link_speed = advt;
 811         else
 812                 phy_conf.link_speed = force_speed;
 813
 814         phy_conf.abilities = abilities;
 815
 816         /* use get_phy_abilities_resp value for the rest */
 817         phy_conf.phy_type = phy_ab.phy_type;
 818         phy_conf.eee_capability = phy_ab.eee_capability;
 819         phy_conf.eeer = phy_ab.eeer_val;
 820         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 821
 822         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 823                     phy_ab.abilities, phy_ab.link_speed);
 824         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 825                     phy_conf.abilities, phy_conf.link_speed);
 826
 827         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 828         if (status)
 829                 return ret;
 830
 831         return I40E_SUCCESS;
 832 }
 833
 834 static int
 835 i40e_apply_link_speed(struct rte_eth_dev *dev)
 836 {
 837         uint8_t speed;
 838         uint8_t abilities = 0;
 839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 840         struct rte_eth_conf *conf = &dev->data->dev_conf;
 841
 842         speed = i40e_parse_link_speed(conf->link_speed);
 843         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 844         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 845                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 846         else
 847                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 848
 849         return i40e_phy_conf_link(hw, abilities, speed);
 850 }
 851
 852 static int
 853 i40e_dev_start(struct rte_eth_dev *dev)
 854 {
 855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 857         struct i40e_vsi *main_vsi = pf->main_vsi;
 858         int ret, i;
 859
 860         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 861                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 862                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 863                              dev->data->dev_conf.link_duplex,
 864                              dev->data->port_id);
 865                 return -EINVAL;
 866         }
 867
 868         /* Initialize VSI */
 869         ret = i40e_dev_rxtx_init(pf);
 870         if (ret != I40E_SUCCESS) {
 871                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 872                 goto err_up;
 873         }
 874
 875         /* Map queues with MSIX interrupt */
 876         i40e_vsi_queues_bind_intr(main_vsi);
 877         i40e_vsi_enable_queues_intr(main_vsi);
 878
 879         /* Map VMDQ VSI queues with MSIX interrupt */
 880         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 881                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 882                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 883         }
 884
 885         /* enable FDIR MSIX interrupt */
 886         if (pf->fdir.fdir_vsi) {
 887                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 888                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 889         }
 890
 891         /* Enable all queues which have been configured */
 892         ret = i40e_dev_switch_queues(pf, TRUE);
 893         if (ret != I40E_SUCCESS) {
 894                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 895                 goto err_up;
 896         }
 897
 898         /* Enable receiving broadcast packets */
 899         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 900         if (ret != I40E_SUCCESS)
 901                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 902
 903         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 904                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 905                                                 true, NULL);
 906                 if (ret != I40E_SUCCESS)
 907                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 908         }
 909
 910         /* Apply link configure */
 911         ret = i40e_apply_link_speed(dev);
 912         if (I40E_SUCCESS != ret) {
 913                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 914                 goto err_up;
 915         }
 916
 917         return I40E_SUCCESS;
 918
 919 err_up:
 920         i40e_dev_switch_queues(pf, FALSE);
 921         i40e_dev_clear_queues(dev);
 922
 923         return ret;
 924 }
 925
 926 static void
 927 i40e_dev_stop(struct rte_eth_dev *dev)
 928 {
 929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 930         struct i40e_vsi *main_vsi = pf->main_vsi;
 931         int i;
 932
 933         /* Disable all queues */
 934         i40e_dev_switch_queues(pf, FALSE);
 935
 936         /* un-map queues with interrupt registers */
 937         i40e_vsi_disable_queues_intr(main_vsi);
 938         i40e_vsi_queues_unbind_intr(main_vsi);
 939
 940         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 941                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 942                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 943         }
 944
 945         if (pf->fdir.fdir_vsi) {
 946                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 947                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 948         }
 949         /* Clear all queues and release memory */
 950         i40e_dev_clear_queues(dev);
 951
 952         /* Set link down */
 953         i40e_dev_set_link_down(dev);
 954
 955 }
 956
 957 static void
 958 i40e_dev_close(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         uint32_t reg;
 963
 964         PMD_INIT_FUNC_TRACE();
 965
 966         i40e_dev_stop(dev);
 967
 968         /* Disable interrupt */
 969         i40e_pf_disable_irq0(hw);
 970         rte_intr_disable(&(dev->pci_dev->intr_handle));
 971
 972         /* shutdown and destroy the HMC */
 973         i40e_shutdown_lan_hmc(hw);
 974
 975         /* release all the existing VSIs and VEBs */
 976         i40e_fdir_teardown(pf);
 977         i40e_vsi_release(pf->main_vsi);
 978
 979         /* shutdown the adminq */
 980         i40e_aq_queue_shutdown(hw, true);
 981         i40e_shutdown_adminq(hw);
 982
 983         i40e_res_pool_destroy(&pf->qp_pool);
 984         i40e_res_pool_destroy(&pf->msix_pool);
 985
 986         /* force a PF reset to clean anything leftover */
 987         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 988         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 989                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 990         I40E_WRITE_FLUSH(hw);
 991 }
 992
 993 static void
 994 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998         struct i40e_vsi *vsi = pf->main_vsi;
 999         int status;
1000
1001         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1002                                                         true, NULL);
1003         if (status != I40E_SUCCESS)
1004                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1005
1006         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1007                                                         TRUE, NULL);
1008         if (status != I40E_SUCCESS)
1009                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1010
1011 }
1012
1013 static void
1014 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1015 {
1016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018         struct i40e_vsi *vsi = pf->main_vsi;
1019         int status;
1020
1021         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1022                                                         false, NULL);
1023         if (status != I40E_SUCCESS)
1024                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1025
1026         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1027                                                         false, NULL);
1028         if (status != I40E_SUCCESS)
1029                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1030 }
1031
1032 static void
1033 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1034 {
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *vsi = pf->main_vsi;
1038         int ret;
1039
1040         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1041         if (ret != I40E_SUCCESS)
1042                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1043 }
1044
1045 static void
1046 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050         struct i40e_vsi *vsi = pf->main_vsi;
1051         int ret;
1052
1053         if (dev->data->promiscuous == 1)
1054                 return; /* must remain in all_multicast mode */
1055
1056         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1057                                 vsi->seid, FALSE, NULL);
1058         if (ret != I40E_SUCCESS)
1059                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1060 }
1061
1062 /*
1063  * Set device link up.
1064  */
1065 static int
1066 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1067 {
1068         /* re-apply link speed setting */
1069         return i40e_apply_link_speed(dev);
1070 }
1071
1072 /*
1073  * Set device link down.
1074  */
1075 static int
1076 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1077 {
1078         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1079         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081
1082         return i40e_phy_conf_link(hw, abilities, speed);
1083 }
1084
1085 int
1086 i40e_dev_link_update(struct rte_eth_dev *dev,
1087                      __rte_unused int wait_to_complete)
1088 {
1089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         struct i40e_link_status link_status;
1091         struct rte_eth_link link, old;
1092         int status;
1093
1094         memset(&link, 0, sizeof(link));
1095         memset(&old, 0, sizeof(old));
1096         memset(&link_status, 0, sizeof(link_status));
1097         rte_i40e_dev_atomic_read_link_status(dev, &old);
1098
1099         /* Get link status information from hardware */
1100         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1101         if (status != I40E_SUCCESS) {
1102                 link.link_speed = ETH_LINK_SPEED_100;
1103                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1104                 PMD_DRV_LOG(ERR, "Failed to get link info");
1105                 goto out;
1106         }
1107
1108         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1109
1110         if (!link.link_status)
1111                 goto out;
1112
1113         /* i40e uses full duplex only */
1114         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1115
1116         /* Parse the link status */
1117         switch (link_status.link_speed) {
1118         case I40E_LINK_SPEED_100MB:
1119                 link.link_speed = ETH_LINK_SPEED_100;
1120                 break;
1121         case I40E_LINK_SPEED_1GB:
1122                 link.link_speed = ETH_LINK_SPEED_1000;
1123                 break;
1124         case I40E_LINK_SPEED_10GB:
1125                 link.link_speed = ETH_LINK_SPEED_10G;
1126                 break;
1127         case I40E_LINK_SPEED_20GB:
1128                 link.link_speed = ETH_LINK_SPEED_20G;
1129                 break;
1130         case I40E_LINK_SPEED_40GB:
1131                 link.link_speed = ETH_LINK_SPEED_40G;
1132                 break;
1133         default:
1134                 link.link_speed = ETH_LINK_SPEED_100;
1135                 break;
1136         }
1137
1138 out:
1139         rte_i40e_dev_atomic_write_link_status(dev, &link);
1140         if (link.link_status == old.link_status)
1141                 return -1;
1142
1143         return 0;
1144 }
1145
1146 /* Get all the statistics of a VSI */
1147 void
1148 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1149 {
1150         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1151         struct i40e_eth_stats *nes = &vsi->eth_stats;
1152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1153         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1154
1155         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1156                             vsi->offset_loaded, &oes->rx_bytes,
1157                             &nes->rx_bytes);
1158         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1159                             vsi->offset_loaded, &oes->rx_unicast,
1160                             &nes->rx_unicast);
1161         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1162                             vsi->offset_loaded, &oes->rx_multicast,
1163                             &nes->rx_multicast);
1164         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1165                             vsi->offset_loaded, &oes->rx_broadcast,
1166                             &nes->rx_broadcast);
1167         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1168                             &oes->rx_discards, &nes->rx_discards);
1169         /* GLV_REPC not supported */
1170         /* GLV_RMPC not supported */
1171         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1172                             &oes->rx_unknown_protocol,
1173                             &nes->rx_unknown_protocol);
1174         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1175                             vsi->offset_loaded, &oes->tx_bytes,
1176                             &nes->tx_bytes);
1177         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1178                             vsi->offset_loaded, &oes->tx_unicast,
1179                             &nes->tx_unicast);
1180         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1181                             vsi->offset_loaded, &oes->tx_multicast,
1182                             &nes->tx_multicast);
1183         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1184                             vsi->offset_loaded,  &oes->tx_broadcast,
1185                             &nes->tx_broadcast);
1186         /* GLV_TDPC not supported */
1187         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1188                             &oes->tx_errors, &nes->tx_errors);
1189         vsi->offset_loaded = true;
1190
1191         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1192                     vsi->vsi_id);
1193         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1194         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1195         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1196         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1197         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1198         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1199                     nes->rx_unknown_protocol);
1200         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1201         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1202         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1203         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1204         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1205         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1206         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1207                     vsi->vsi_id);
1208 }
1209
1210 /* Get all statistics of a port */
1211 static void
1212 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1213 {
1214         uint32_t i;
1215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1218         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1219
1220         /* Get statistics of struct i40e_eth_stats */
1221         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1222                             I40E_GLPRT_GORCL(hw->port),
1223                             pf->offset_loaded, &os->eth.rx_bytes,
1224                             &ns->eth.rx_bytes);
1225         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1226                             I40E_GLPRT_UPRCL(hw->port),
1227                             pf->offset_loaded, &os->eth.rx_unicast,
1228                             &ns->eth.rx_unicast);
1229         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1230                             I40E_GLPRT_MPRCL(hw->port),
1231                             pf->offset_loaded, &os->eth.rx_multicast,
1232                             &ns->eth.rx_multicast);
1233         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1234                             I40E_GLPRT_BPRCL(hw->port),
1235                             pf->offset_loaded, &os->eth.rx_broadcast,
1236                             &ns->eth.rx_broadcast);
1237         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1238                             pf->offset_loaded, &os->eth.rx_discards,
1239                             &ns->eth.rx_discards);
1240         /* GLPRT_REPC not supported */
1241         /* GLPRT_RMPC not supported */
1242         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1243                             pf->offset_loaded,
1244                             &os->eth.rx_unknown_protocol,
1245                             &ns->eth.rx_unknown_protocol);
1246         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1247                             I40E_GLPRT_GOTCL(hw->port),
1248                             pf->offset_loaded, &os->eth.tx_bytes,
1249                             &ns->eth.tx_bytes);
1250         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1251                             I40E_GLPRT_UPTCL(hw->port),
1252                             pf->offset_loaded, &os->eth.tx_unicast,
1253                             &ns->eth.tx_unicast);
1254         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1255                             I40E_GLPRT_MPTCL(hw->port),
1256                             pf->offset_loaded, &os->eth.tx_multicast,
1257                             &ns->eth.tx_multicast);
1258         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1259                             I40E_GLPRT_BPTCL(hw->port),
1260                             pf->offset_loaded, &os->eth.tx_broadcast,
1261                             &ns->eth.tx_broadcast);
1262         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1263                             pf->offset_loaded, &os->eth.tx_discards,
1264                             &ns->eth.tx_discards);
1265         /* GLPRT_TEPC not supported */
1266
1267         /* additional port specific stats */
1268         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1269                             pf->offset_loaded, &os->tx_dropped_link_down,
1270                             &ns->tx_dropped_link_down);
1271         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1272                             pf->offset_loaded, &os->crc_errors,
1273                             &ns->crc_errors);
1274         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1275                             pf->offset_loaded, &os->illegal_bytes,
1276                             &ns->illegal_bytes);
1277         /* GLPRT_ERRBC not supported */
1278         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1279                             pf->offset_loaded, &os->mac_local_faults,
1280                             &ns->mac_local_faults);
1281         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1282                             pf->offset_loaded, &os->mac_remote_faults,
1283                             &ns->mac_remote_faults);
1284         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1285                             pf->offset_loaded, &os->rx_length_errors,
1286                             &ns->rx_length_errors);
1287         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1288                             pf->offset_loaded, &os->link_xon_rx,
1289                             &ns->link_xon_rx);
1290         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1291                             pf->offset_loaded, &os->link_xoff_rx,
1292                             &ns->link_xoff_rx);
1293         for (i = 0; i < 8; i++) {
1294                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1295                                     pf->offset_loaded,
1296                                     &os->priority_xon_rx[i],
1297                                     &ns->priority_xon_rx[i]);
1298                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1299                                     pf->offset_loaded,
1300                                     &os->priority_xoff_rx[i],
1301                                     &ns->priority_xoff_rx[i]);
1302         }
1303         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1304                             pf->offset_loaded, &os->link_xon_tx,
1305                             &ns->link_xon_tx);
1306         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1307                             pf->offset_loaded, &os->link_xoff_tx,
1308                             &ns->link_xoff_tx);
1309         for (i = 0; i < 8; i++) {
1310                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1311                                     pf->offset_loaded,
1312                                     &os->priority_xon_tx[i],
1313                                     &ns->priority_xon_tx[i]);
1314                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1315                                     pf->offset_loaded,
1316                                     &os->priority_xoff_tx[i],
1317                                     &ns->priority_xoff_tx[i]);
1318                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1319                                     pf->offset_loaded,
1320                                     &os->priority_xon_2_xoff[i],
1321                                     &ns->priority_xon_2_xoff[i]);
1322         }
1323         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1324                             I40E_GLPRT_PRC64L(hw->port),
1325                             pf->offset_loaded, &os->rx_size_64,
1326                             &ns->rx_size_64);
1327         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1328                             I40E_GLPRT_PRC127L(hw->port),
1329                             pf->offset_loaded, &os->rx_size_127,
1330                             &ns->rx_size_127);
1331         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1332                             I40E_GLPRT_PRC255L(hw->port),
1333                             pf->offset_loaded, &os->rx_size_255,
1334                             &ns->rx_size_255);
1335         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1336                             I40E_GLPRT_PRC511L(hw->port),
1337                             pf->offset_loaded, &os->rx_size_511,
1338                             &ns->rx_size_511);
1339         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1340                             I40E_GLPRT_PRC1023L(hw->port),
1341                             pf->offset_loaded, &os->rx_size_1023,
1342                             &ns->rx_size_1023);
1343         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1344                             I40E_GLPRT_PRC1522L(hw->port),
1345                             pf->offset_loaded, &os->rx_size_1522,
1346                             &ns->rx_size_1522);
1347         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1348                             I40E_GLPRT_PRC9522L(hw->port),
1349                             pf->offset_loaded, &os->rx_size_big,
1350                             &ns->rx_size_big);
1351         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1352                             pf->offset_loaded, &os->rx_undersize,
1353                             &ns->rx_undersize);
1354         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1355                             pf->offset_loaded, &os->rx_fragments,
1356                             &ns->rx_fragments);
1357         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1358                             pf->offset_loaded, &os->rx_oversize,
1359                             &ns->rx_oversize);
1360         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1361                             pf->offset_loaded, &os->rx_jabber,
1362                             &ns->rx_jabber);
1363         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1364                             I40E_GLPRT_PTC64L(hw->port),
1365                             pf->offset_loaded, &os->tx_size_64,
1366                             &ns->tx_size_64);
1367         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1368                             I40E_GLPRT_PTC127L(hw->port),
1369                             pf->offset_loaded, &os->tx_size_127,
1370                             &ns->tx_size_127);
1371         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1372                             I40E_GLPRT_PTC255L(hw->port),
1373                             pf->offset_loaded, &os->tx_size_255,
1374                             &ns->tx_size_255);
1375         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1376                             I40E_GLPRT_PTC511L(hw->port),
1377                             pf->offset_loaded, &os->tx_size_511,
1378                             &ns->tx_size_511);
1379         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1380                             I40E_GLPRT_PTC1023L(hw->port),
1381                             pf->offset_loaded, &os->tx_size_1023,
1382                             &ns->tx_size_1023);
1383         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1384                             I40E_GLPRT_PTC1522L(hw->port),
1385                             pf->offset_loaded, &os->tx_size_1522,
1386                             &ns->tx_size_1522);
1387         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1388                             I40E_GLPRT_PTC9522L(hw->port),
1389                             pf->offset_loaded, &os->tx_size_big,
1390                             &ns->tx_size_big);
1391         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1392                            pf->offset_loaded,
1393                            &os->fd_sb_match, &ns->fd_sb_match);
1394         /* GLPRT_MSPDC not supported */
1395         /* GLPRT_XEC not supported */
1396
1397         pf->offset_loaded = true;
1398
1399         if (pf->main_vsi)
1400                 i40e_update_vsi_stats(pf->main_vsi);
1401
1402         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1403                                                 ns->eth.rx_broadcast;
1404         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1405                                                 ns->eth.tx_broadcast;
1406         stats->ibytes   = ns->eth.rx_bytes;
1407         stats->obytes   = ns->eth.tx_bytes;
1408         stats->oerrors  = ns->eth.tx_errors;
1409         stats->imcasts  = ns->eth.rx_multicast;
1410         stats->fdirmatch = ns->fd_sb_match;
1411
1412         /* Rx Errors */
1413         stats->ibadcrc  = ns->crc_errors;
1414         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1415                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1416         stats->imissed  = ns->eth.rx_discards;
1417         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1418
1419         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1420         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1421         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1422         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1423         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1424         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1425         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1426                     ns->eth.rx_unknown_protocol);
1427         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1428         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1429         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1430         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1431         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1432         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1433
1434         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1435                     ns->tx_dropped_link_down);
1436         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1437         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1438                     ns->illegal_bytes);
1439         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1440         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1441                     ns->mac_local_faults);
1442         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1443                     ns->mac_remote_faults);
1444         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1445                     ns->rx_length_errors);
1446         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1447         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1448         for (i = 0; i < 8; i++) {
1449                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1450                                 i, ns->priority_xon_rx[i]);
1451                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1452                                 i, ns->priority_xoff_rx[i]);
1453         }
1454         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1455         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1456         for (i = 0; i < 8; i++) {
1457                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1458                                 i, ns->priority_xon_tx[i]);
1459                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1460                                 i, ns->priority_xoff_tx[i]);
1461                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1462                                 i, ns->priority_xon_2_xoff[i]);
1463         }
1464         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1465         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1466         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1467         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1468         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1469         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1470         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1471         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1472         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1473         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1474         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1475         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1476         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1477         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1478         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1479         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1480         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1481         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1482         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1483                         ns->mac_short_packet_dropped);
1484         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1485                     ns->checksum_error);
1486         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1487         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1488 }
1489
1490 /* Reset the statistics */
1491 static void
1492 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1493 {
1494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495
1496         /* It results in reloading the start point of each counter */
1497         pf->offset_loaded = false;
1498 }
1499
1500 static int
1501 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1502                                  __rte_unused uint16_t queue_id,
1503                                  __rte_unused uint8_t stat_idx,
1504                                  __rte_unused uint8_t is_rx)
1505 {
1506         PMD_INIT_FUNC_TRACE();
1507
1508         return -ENOSYS;
1509 }
1510
1511 static void
1512 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1513 {
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_vsi *vsi = pf->main_vsi;
1516
1517         dev_info->max_rx_queues = vsi->nb_qps;
1518         dev_info->max_tx_queues = vsi->nb_qps;
1519         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1520         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1521         dev_info->max_mac_addrs = vsi->max_macaddrs;
1522         dev_info->max_vfs = dev->pci_dev->max_vfs;
1523         dev_info->rx_offload_capa =
1524                 DEV_RX_OFFLOAD_VLAN_STRIP |
1525                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1526                 DEV_RX_OFFLOAD_UDP_CKSUM |
1527                 DEV_RX_OFFLOAD_TCP_CKSUM;
1528         dev_info->tx_offload_capa =
1529                 DEV_TX_OFFLOAD_VLAN_INSERT |
1530                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1531                 DEV_TX_OFFLOAD_UDP_CKSUM |
1532                 DEV_TX_OFFLOAD_TCP_CKSUM |
1533                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1534                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1535         dev_info->reta_size = pf->hash_lut_size;
1536         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1537
1538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1539                 .rx_thresh = {
1540                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1541                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1542                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1543                 },
1544                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1545                 .rx_drop_en = 0,
1546         };
1547
1548         dev_info->default_txconf = (struct rte_eth_txconf) {
1549                 .tx_thresh = {
1550                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1551                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1552                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1553                 },
1554                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1555                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1556                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1557                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1558         };
1559
1560         if (pf->flags | I40E_FLAG_VMDQ) {
1561                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1562                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1563                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1564                                                 pf->max_nb_vmdq_vsi;
1565                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1566                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1567                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1568         }
1569 }
1570
1571 static int
1572 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1573 {
1574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1575         struct i40e_vsi *vsi = pf->main_vsi;
1576         PMD_INIT_FUNC_TRACE();
1577
1578         if (on)
1579                 return i40e_vsi_add_vlan(vsi, vlan_id);
1580         else
1581                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1582 }
1583
1584 static void
1585 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1586                    __rte_unused uint16_t tpid)
1587 {
1588         PMD_INIT_FUNC_TRACE();
1589 }
1590
1591 static void
1592 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1593 {
1594         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1595         struct i40e_vsi *vsi = pf->main_vsi;
1596
1597         if (mask & ETH_VLAN_STRIP_MASK) {
1598                 /* Enable or disable VLAN stripping */
1599                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1600                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1601                 else
1602                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1603         }
1604
1605         if (mask & ETH_VLAN_EXTEND_MASK) {
1606                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1607                         i40e_vsi_config_double_vlan(vsi, TRUE);
1608                 else
1609                         i40e_vsi_config_double_vlan(vsi, FALSE);
1610         }
1611 }
1612
1613 static void
1614 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1615                           __rte_unused uint16_t queue,
1616                           __rte_unused int on)
1617 {
1618         PMD_INIT_FUNC_TRACE();
1619 }
1620
1621 static int
1622 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1623 {
1624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625         struct i40e_vsi *vsi = pf->main_vsi;
1626         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1627         struct i40e_vsi_vlan_pvid_info info;
1628
1629         memset(&info, 0, sizeof(info));
1630         info.on = on;
1631         if (info.on)
1632                 info.config.pvid = pvid;
1633         else {
1634                 info.config.reject.tagged =
1635                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1636                 info.config.reject.untagged =
1637                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1638         }
1639
1640         return i40e_vsi_vlan_pvid_set(vsi, &info);
1641 }
1642
1643 static int
1644 i40e_dev_led_on(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         uint32_t mode = i40e_led_get(hw);
1648
1649         if (mode == 0)
1650                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1651
1652         return 0;
1653 }
1654
1655 static int
1656 i40e_dev_led_off(struct rte_eth_dev *dev)
1657 {
1658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         uint32_t mode = i40e_led_get(hw);
1660
1661         if (mode != 0)
1662                 i40e_led_set(hw, 0, false);
1663
1664         return 0;
1665 }
1666
1667 static int
1668 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1669                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1670 {
1671         PMD_INIT_FUNC_TRACE();
1672
1673         return -ENOSYS;
1674 }
1675
1676 static int
1677 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1678                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1679 {
1680         PMD_INIT_FUNC_TRACE();
1681
1682         return -ENOSYS;
1683 }
1684
1685 /* Add a MAC address, and update filters */
1686 static void
1687 i40e_macaddr_add(struct rte_eth_dev *dev,
1688                  struct ether_addr *mac_addr,
1689                  __rte_unused uint32_t index,
1690                  uint32_t pool)
1691 {
1692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1693         struct i40e_mac_filter_info mac_filter;
1694         struct i40e_vsi *vsi;
1695         int ret;
1696
1697         /* If VMDQ not enabled or configured, return */
1698         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1699                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1700                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1701                         pool);
1702                 return;
1703         }
1704
1705         if (pool > pf->nb_cfg_vmdq_vsi) {
1706                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1707                                 pool, pf->nb_cfg_vmdq_vsi);
1708                 return;
1709         }
1710
1711         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1712         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1713
1714         if (pool == 0)
1715                 vsi = pf->main_vsi;
1716         else
1717                 vsi = pf->vmdq[pool - 1].vsi;
1718
1719         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1720         if (ret != I40E_SUCCESS) {
1721                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1722                 return;
1723         }
1724 }
1725
1726 /* Remove a MAC address, and update filters */
1727 static void
1728 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1729 {
1730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1731         struct i40e_vsi *vsi;
1732         struct rte_eth_dev_data *data = dev->data;
1733         struct ether_addr *macaddr;
1734         int ret;
1735         uint32_t i;
1736         uint64_t pool_sel;
1737
1738         macaddr = &(data->mac_addrs[index]);
1739
1740         pool_sel = dev->data->mac_pool_sel[index];
1741
1742         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1743                 if (pool_sel & (1ULL << i)) {
1744                         if (i == 0)
1745                                 vsi = pf->main_vsi;
1746                         else {
1747                                 /* No VMDQ pool enabled or configured */
1748                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1749                                         (i > pf->nb_cfg_vmdq_vsi)) {
1750                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1751                                                         "/configured");
1752                                         return;
1753                                 }
1754                                 vsi = pf->vmdq[i - 1].vsi;
1755                         }
1756                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1757
1758                         if (ret) {
1759                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1760                                 return;
1761                         }
1762                 }
1763         }
1764 }
1765
1766 /* Set perfect match or hash match of MAC and VLAN for a VF */
1767 static int
1768 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1769                  struct rte_eth_mac_filter *filter,
1770                  bool add)
1771 {
1772         struct i40e_hw *hw;
1773         struct i40e_mac_filter_info mac_filter;
1774         struct ether_addr old_mac;
1775         struct ether_addr *new_mac;
1776         struct i40e_pf_vf *vf = NULL;
1777         uint16_t vf_id;
1778         int ret;
1779
1780         if (pf == NULL) {
1781                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1782                 return -EINVAL;
1783         }
1784         hw = I40E_PF_TO_HW(pf);
1785
1786         if (filter == NULL) {
1787                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1788                 return -EINVAL;
1789         }
1790
1791         new_mac = &filter->mac_addr;
1792
1793         if (is_zero_ether_addr(new_mac)) {
1794                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1795                 return -EINVAL;
1796         }
1797
1798         vf_id = filter->dst_id;
1799
1800         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1801                 PMD_DRV_LOG(ERR, "Invalid argument.");
1802                 return -EINVAL;
1803         }
1804         vf = &pf->vfs[vf_id];
1805
1806         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1807                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1808                 return -EINVAL;
1809         }
1810
1811         if (add) {
1812                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1813                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1814                                 ETHER_ADDR_LEN);
1815                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1816                                  ETHER_ADDR_LEN);
1817
1818                 mac_filter.filter_type = filter->filter_type;
1819                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1820                 if (ret != I40E_SUCCESS) {
1821                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1822                         return -1;
1823                 }
1824                 ether_addr_copy(new_mac, &pf->dev_addr);
1825         } else {
1826                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1827                                 ETHER_ADDR_LEN);
1828                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1829                 if (ret != I40E_SUCCESS) {
1830                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1831                         return -1;
1832                 }
1833
1834                 /* Clear device address as it has been removed */
1835                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1836                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1837         }
1838
1839         return 0;
1840 }
1841
1842 /* MAC filter handle */
1843 static int
1844 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1845                 void *arg)
1846 {
1847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1848         struct rte_eth_mac_filter *filter;
1849         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1850         int ret = I40E_NOT_SUPPORTED;
1851
1852         filter = (struct rte_eth_mac_filter *)(arg);
1853
1854         switch (filter_op) {
1855         case RTE_ETH_FILTER_NOP:
1856                 ret = I40E_SUCCESS;
1857                 break;
1858         case RTE_ETH_FILTER_ADD:
1859                 i40e_pf_disable_irq0(hw);
1860                 if (filter->is_vf)
1861                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1862                 i40e_pf_enable_irq0(hw);
1863                 break;
1864         case RTE_ETH_FILTER_DELETE:
1865                 i40e_pf_disable_irq0(hw);
1866                 if (filter->is_vf)
1867                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1868                 i40e_pf_enable_irq0(hw);
1869                 break;
1870         default:
1871                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1872                 ret = I40E_ERR_PARAM;
1873                 break;
1874         }
1875
1876         return ret;
1877 }
1878
1879 static int
1880 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1881                          struct rte_eth_rss_reta_entry64 *reta_conf,
1882                          uint16_t reta_size)
1883 {
1884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         uint32_t lut, l;
1887         uint16_t i, j, lut_size = pf->hash_lut_size;
1888         uint16_t idx, shift;
1889         uint8_t mask;
1890
1891         if (reta_size != lut_size ||
1892                 reta_size > ETH_RSS_RETA_SIZE_512) {
1893                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1894                         "(%d) doesn't match the number hardware can supported "
1895                                         "(%d)\n", reta_size, lut_size);
1896                 return -EINVAL;
1897         }
1898
1899         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1900                 idx = i / RTE_RETA_GROUP_SIZE;
1901                 shift = i % RTE_RETA_GROUP_SIZE;
1902                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1903                                                 I40E_4_BIT_MASK);
1904                 if (!mask)
1905                         continue;
1906                 if (mask == I40E_4_BIT_MASK)
1907                         l = 0;
1908                 else
1909                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1910                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1911                         if (mask & (0x1 << j))
1912                                 lut |= reta_conf[idx].reta[shift + j] <<
1913                                                         (CHAR_BIT * j);
1914                         else
1915                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1916                 }
1917                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1918         }
1919
1920         return 0;
1921 }
1922
1923 static int
1924 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1925                         struct rte_eth_rss_reta_entry64 *reta_conf,
1926                         uint16_t reta_size)
1927 {
1928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1929         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         uint32_t lut;
1931         uint16_t i, j, lut_size = pf->hash_lut_size;
1932         uint16_t idx, shift;
1933         uint8_t mask;
1934
1935         if (reta_size != lut_size ||
1936                 reta_size > ETH_RSS_RETA_SIZE_512) {
1937                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1938                         "(%d) doesn't match the number hardware can supported "
1939                                         "(%d)\n", reta_size, lut_size);
1940                 return -EINVAL;
1941         }
1942
1943         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1944                 idx = i / RTE_RETA_GROUP_SIZE;
1945                 shift = i % RTE_RETA_GROUP_SIZE;
1946                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1947                                                 I40E_4_BIT_MASK);
1948                 if (!mask)
1949                         continue;
1950
1951                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1952                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1953                         if (mask & (0x1 << j))
1954                                 reta_conf[idx].reta[shift + j] = ((lut >>
1955                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1956                 }
1957         }
1958
1959         return 0;
1960 }
1961
1962 /**
1963  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1964  * @hw:   pointer to the HW structure
1965  * @mem:  pointer to mem struct to fill out
1966  * @size: size of memory requested
1967  * @alignment: what to align the allocation to
1968  **/
1969 enum i40e_status_code
1970 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1971                         struct i40e_dma_mem *mem,
1972                         u64 size,
1973                         u32 alignment)
1974 {
1975         static uint64_t id = 0;
1976         const struct rte_memzone *mz = NULL;
1977         char z_name[RTE_MEMZONE_NAMESIZE];
1978
1979         if (!mem)
1980                 return I40E_ERR_PARAM;
1981
1982         id++;
1983         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1984 #ifdef RTE_LIBRTE_XEN_DOM0
1985         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1986                                                         RTE_PGSIZE_2M);
1987 #else
1988         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1989 #endif
1990         if (!mz)
1991                 return I40E_ERR_NO_MEMORY;
1992
1993         mem->id = id;
1994         mem->size = size;
1995         mem->va = mz->addr;
1996 #ifdef RTE_LIBRTE_XEN_DOM0
1997         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1998 #else
1999         mem->pa = mz->phys_addr;
2000 #endif
2001
2002         return I40E_SUCCESS;
2003 }
2004
2005 /**
2006  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2007  * @hw:   pointer to the HW structure
2008  * @mem:  ptr to mem struct to free
2009  **/
2010 enum i40e_status_code
2011 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2012                     struct i40e_dma_mem *mem)
2013 {
2014         if (!mem || !mem->va)
2015                 return I40E_ERR_PARAM;
2016
2017         mem->va = NULL;
2018         mem->pa = (u64)0;
2019
2020         return I40E_SUCCESS;
2021 }
2022
2023 /**
2024  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2025  * @hw:   pointer to the HW structure
2026  * @mem:  pointer to mem struct to fill out
2027  * @size: size of memory requested
2028  **/
2029 enum i40e_status_code
2030 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2031                          struct i40e_virt_mem *mem,
2032                          u32 size)
2033 {
2034         if (!mem)
2035                 return I40E_ERR_PARAM;
2036
2037         mem->size = size;
2038         mem->va = rte_zmalloc("i40e", size, 0);
2039
2040         if (mem->va)
2041                 return I40E_SUCCESS;
2042         else
2043                 return I40E_ERR_NO_MEMORY;
2044 }
2045
2046 /**
2047  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2048  * @hw:   pointer to the HW structure
2049  * @mem:  pointer to mem struct to free
2050  **/
2051 enum i40e_status_code
2052 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2053                      struct i40e_virt_mem *mem)
2054 {
2055         if (!mem)
2056                 return I40E_ERR_PARAM;
2057
2058         rte_free(mem->va);
2059         mem->va = NULL;
2060
2061         return I40E_SUCCESS;
2062 }
2063
2064 void
2065 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2066 {
2067         rte_spinlock_init(&sp->spinlock);
2068 }
2069
2070 void
2071 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2072 {
2073         rte_spinlock_lock(&sp->spinlock);
2074 }
2075
2076 void
2077 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2078 {
2079         rte_spinlock_unlock(&sp->spinlock);
2080 }
2081
2082 void
2083 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2084 {
2085         return;
2086 }
2087
2088 /**
2089  * Get the hardware capabilities, which will be parsed
2090  * and saved into struct i40e_hw.
2091  */
2092 static int
2093 i40e_get_cap(struct i40e_hw *hw)
2094 {
2095         struct i40e_aqc_list_capabilities_element_resp *buf;
2096         uint16_t len, size = 0;
2097         int ret;
2098
2099         /* Calculate a huge enough buff for saving response data temporarily */
2100         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2101                                                 I40E_MAX_CAP_ELE_NUM;
2102         buf = rte_zmalloc("i40e", len, 0);
2103         if (!buf) {
2104                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2105                 return I40E_ERR_NO_MEMORY;
2106         }
2107
2108         /* Get, parse the capabilities and save it to hw */
2109         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2110                         i40e_aqc_opc_list_func_capabilities, NULL);
2111         if (ret != I40E_SUCCESS)
2112                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2113
2114         /* Free the temporary buffer after being used */
2115         rte_free(buf);
2116
2117         return ret;
2118 }
2119
2120 static int
2121 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2122 {
2123         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2125         uint16_t sum_queues = 0, sum_vsis, left_queues;
2126
2127         /* First check if FW support SRIOV */
2128         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2129                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2130                 return -EINVAL;
2131         }
2132
2133         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2134         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2135         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2136         /* Allocate queues for pf */
2137         if (hw->func_caps.rss) {
2138                 pf->flags |= I40E_FLAG_RSS;
2139                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2140                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2141                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2142         } else
2143                 pf->lan_nb_qps = 1;
2144         sum_queues = pf->lan_nb_qps;
2145         /* Default VSI is not counted in */
2146         sum_vsis = 0;
2147         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2148
2149         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2150                 pf->flags |= I40E_FLAG_SRIOV;
2151                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2152                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2153                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2154                                      "max supported %u.",
2155                                      dev->pci_dev->max_vfs,
2156                                      hw->func_caps.num_vfs);
2157                         return -EINVAL;
2158                 }
2159                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2160                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2161                                      "max support %u queues.",
2162                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2163                         return -EINVAL;
2164                 }
2165                 pf->vf_num = dev->pci_dev->max_vfs;
2166                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2167                 sum_vsis   += pf->vf_num;
2168                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2169                              pf->vf_num, pf->vf_nb_qps);
2170         } else
2171                 pf->vf_num = 0;
2172
2173         if (hw->func_caps.vmdq) {
2174                 pf->flags |= I40E_FLAG_VMDQ;
2175                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2176                 pf->max_nb_vmdq_vsi = 1;
2177                 /*
2178                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2179                  * later.
2180                  */
2181                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2182                 sum_vsis += pf->max_nb_vmdq_vsi;
2183         } else {
2184                 pf->vmdq_nb_qps = 0;
2185                 pf->max_nb_vmdq_vsi = 0;
2186         }
2187         pf->nb_cfg_vmdq_vsi = 0;
2188
2189         if (hw->func_caps.fd) {
2190                 pf->flags |= I40E_FLAG_FDIR;
2191                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2192                 /**
2193                  * Each flow director consumes one VSI and one queue,
2194                  * but can't calculate out predictably here.
2195                  */
2196         }
2197
2198         if (sum_vsis > pf->max_num_vsi ||
2199                 sum_queues > hw->func_caps.num_rx_qp) {
2200                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2201                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2202                              pf->max_num_vsi, sum_vsis);
2203                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2204                              hw->func_caps.num_rx_qp, sum_queues);
2205                 return -EINVAL;
2206         }
2207
2208         /* Adjust VMDQ setting to support as many VMs as possible */
2209         if (pf->flags & I40E_FLAG_VMDQ) {
2210                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2211
2212                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2213                                         pf->max_num_vsi - sum_vsis);
2214
2215                 /* Limit the max VMDQ number that rte_ether that can support  */
2216                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2217                                         ETH_64_POOLS - 1);
2218
2219                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2220                                 pf->max_nb_vmdq_vsi);
2221                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2222         }
2223
2224         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2225          * cause */
2226         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2227                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2228                              sum_vsis, hw->func_caps.num_msix_vectors);
2229                 return -EINVAL;
2230         }
2231         return I40E_SUCCESS;
2232 }
2233
2234 static int
2235 i40e_pf_get_switch_config(struct i40e_pf *pf)
2236 {
2237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2238         struct i40e_aqc_get_switch_config_resp *switch_config;
2239         struct i40e_aqc_switch_config_element_resp *element;
2240         uint16_t start_seid = 0, num_reported;
2241         int ret;
2242
2243         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2244                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2245         if (!switch_config) {
2246                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2247                 return -ENOMEM;
2248         }
2249
2250         /* Get the switch configurations */
2251         ret = i40e_aq_get_switch_config(hw, switch_config,
2252                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2253         if (ret != I40E_SUCCESS) {
2254                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2255                 goto fail;
2256         }
2257         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2258         if (num_reported != 1) { /* The number should be 1 */
2259                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2260                 goto fail;
2261         }
2262
2263         /* Parse the switch configuration elements */
2264         element = &(switch_config->element[0]);
2265         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2266                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2267                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2268         } else
2269                 PMD_DRV_LOG(INFO, "Unknown element type");
2270
2271 fail:
2272         rte_free(switch_config);
2273
2274         return ret;
2275 }
2276
2277 static int
2278 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2279                         uint32_t num)
2280 {
2281         struct pool_entry *entry;
2282
2283         if (pool == NULL || num == 0)
2284                 return -EINVAL;
2285
2286         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2287         if (entry == NULL) {
2288                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2289                 return -ENOMEM;
2290         }
2291
2292         /* queue heap initialize */
2293         pool->num_free = num;
2294         pool->num_alloc = 0;
2295         pool->base = base;
2296         LIST_INIT(&pool->alloc_list);
2297         LIST_INIT(&pool->free_list);
2298
2299         /* Initialize element  */
2300         entry->base = 0;
2301         entry->len = num;
2302
2303         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2304         return 0;
2305 }
2306
2307 static void
2308 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2309 {
2310         struct pool_entry *entry;
2311
2312         if (pool == NULL)
2313                 return;
2314
2315         LIST_FOREACH(entry, &pool->alloc_list, next) {
2316                 LIST_REMOVE(entry, next);
2317                 rte_free(entry);
2318         }
2319
2320         LIST_FOREACH(entry, &pool->free_list, next) {
2321                 LIST_REMOVE(entry, next);
2322                 rte_free(entry);
2323         }
2324
2325         pool->num_free = 0;
2326         pool->num_alloc = 0;
2327         pool->base = 0;
2328         LIST_INIT(&pool->alloc_list);
2329         LIST_INIT(&pool->free_list);
2330 }
2331
2332 static int
2333 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2334                        uint32_t base)
2335 {
2336         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2337         uint32_t pool_offset;
2338         int insert;
2339
2340         if (pool == NULL) {
2341                 PMD_DRV_LOG(ERR, "Invalid parameter");
2342                 return -EINVAL;
2343         }
2344
2345         pool_offset = base - pool->base;
2346         /* Lookup in alloc list */
2347         LIST_FOREACH(entry, &pool->alloc_list, next) {
2348                 if (entry->base == pool_offset) {
2349                         valid_entry = entry;
2350                         LIST_REMOVE(entry, next);
2351                         break;
2352                 }
2353         }
2354
2355         /* Not find, return */
2356         if (valid_entry == NULL) {
2357                 PMD_DRV_LOG(ERR, "Failed to find entry");
2358                 return -EINVAL;
2359         }
2360
2361         /**
2362          * Found it, move it to free list  and try to merge.
2363          * In order to make merge easier, always sort it by qbase.
2364          * Find adjacent prev and last entries.
2365          */
2366         prev = next = NULL;
2367         LIST_FOREACH(entry, &pool->free_list, next) {
2368                 if (entry->base > valid_entry->base) {
2369                         next = entry;
2370                         break;
2371                 }
2372                 prev = entry;
2373         }
2374
2375         insert = 0;
2376         /* Try to merge with next one*/
2377         if (next != NULL) {
2378                 /* Merge with next one */
2379                 if (valid_entry->base + valid_entry->len == next->base) {
2380                         next->base = valid_entry->base;
2381                         next->len += valid_entry->len;
2382                         rte_free(valid_entry);
2383                         valid_entry = next;
2384                         insert = 1;
2385                 }
2386         }
2387
2388         if (prev != NULL) {
2389                 /* Merge with previous one */
2390                 if (prev->base + prev->len == valid_entry->base) {
2391                         prev->len += valid_entry->len;
2392                         /* If it merge with next one, remove next node */
2393                         if (insert == 1) {
2394                                 LIST_REMOVE(valid_entry, next);
2395                                 rte_free(valid_entry);
2396                         } else {
2397                                 rte_free(valid_entry);
2398                                 insert = 1;
2399                         }
2400                 }
2401         }
2402
2403         /* Not find any entry to merge, insert */
2404         if (insert == 0) {
2405                 if (prev != NULL)
2406                         LIST_INSERT_AFTER(prev, valid_entry, next);
2407                 else if (next != NULL)
2408                         LIST_INSERT_BEFORE(next, valid_entry, next);
2409                 else /* It's empty list, insert to head */
2410                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2411         }
2412
2413         pool->num_free += valid_entry->len;
2414         pool->num_alloc -= valid_entry->len;
2415
2416         return 0;
2417 }
2418
2419 static int
2420 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2421                        uint16_t num)
2422 {
2423         struct pool_entry *entry, *valid_entry;
2424
2425         if (pool == NULL || num == 0) {
2426                 PMD_DRV_LOG(ERR, "Invalid parameter");
2427                 return -EINVAL;
2428         }
2429
2430         if (pool->num_free < num) {
2431                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2432                             num, pool->num_free);
2433                 return -ENOMEM;
2434         }
2435
2436         valid_entry = NULL;
2437         /* Lookup  in free list and find most fit one */
2438         LIST_FOREACH(entry, &pool->free_list, next) {
2439                 if (entry->len >= num) {
2440                         /* Find best one */
2441                         if (entry->len == num) {
2442                                 valid_entry = entry;
2443                                 break;
2444                         }
2445                         if (valid_entry == NULL || valid_entry->len > entry->len)
2446                                 valid_entry = entry;
2447                 }
2448         }
2449
2450         /* Not find one to satisfy the request, return */
2451         if (valid_entry == NULL) {
2452                 PMD_DRV_LOG(ERR, "No valid entry found");
2453                 return -ENOMEM;
2454         }
2455         /**
2456          * The entry have equal queue number as requested,
2457          * remove it from alloc_list.
2458          */
2459         if (valid_entry->len == num) {
2460                 LIST_REMOVE(valid_entry, next);
2461         } else {
2462                 /**
2463                  * The entry have more numbers than requested,
2464                  * create a new entry for alloc_list and minus its
2465                  * queue base and number in free_list.
2466                  */
2467                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2468                 if (entry == NULL) {
2469                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2470                                     "resource pool");
2471                         return -ENOMEM;
2472                 }
2473                 entry->base = valid_entry->base;
2474                 entry->len = num;
2475                 valid_entry->base += num;
2476                 valid_entry->len -= num;
2477                 valid_entry = entry;
2478         }
2479
2480         /* Insert it into alloc list, not sorted */
2481         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2482
2483         pool->num_free -= valid_entry->len;
2484         pool->num_alloc += valid_entry->len;
2485
2486         return (valid_entry->base + pool->base);
2487 }
2488
2489 /**
2490  * bitmap_is_subset - Check whether src2 is subset of src1
2491  **/
2492 static inline int
2493 bitmap_is_subset(uint8_t src1, uint8_t src2)
2494 {
2495         return !((src1 ^ src2) & src2);
2496 }
2497
2498 static int
2499 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2500 {
2501         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2502
2503         /* If DCB is not supported, only default TC is supported */
2504         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2505                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2506                 return -EINVAL;
2507         }
2508
2509         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2510                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2511                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2512                             enabled_tcmap);
2513                 return -EINVAL;
2514         }
2515         return I40E_SUCCESS;
2516 }
2517
2518 int
2519 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2520                                 struct i40e_vsi_vlan_pvid_info *info)
2521 {
2522         struct i40e_hw *hw;
2523         struct i40e_vsi_context ctxt;
2524         uint8_t vlan_flags = 0;
2525         int ret;
2526
2527         if (vsi == NULL || info == NULL) {
2528                 PMD_DRV_LOG(ERR, "invalid parameters");
2529                 return I40E_ERR_PARAM;
2530         }
2531
2532         if (info->on) {
2533                 vsi->info.pvid = info->config.pvid;
2534                 /**
2535                  * If insert pvid is enabled, only tagged pkts are
2536                  * allowed to be sent out.
2537                  */
2538                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2539                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2540         } else {
2541                 vsi->info.pvid = 0;
2542                 if (info->config.reject.tagged == 0)
2543                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2544
2545                 if (info->config.reject.untagged == 0)
2546                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2547         }
2548         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2549                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2550         vsi->info.port_vlan_flags |= vlan_flags;
2551         vsi->info.valid_sections =
2552                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2553         memset(&ctxt, 0, sizeof(ctxt));
2554         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2555         ctxt.seid = vsi->seid;
2556
2557         hw = I40E_VSI_TO_HW(vsi);
2558         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2559         if (ret != I40E_SUCCESS)
2560                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2561
2562         return ret;
2563 }
2564
2565 static int
2566 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2567 {
2568         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2569         int i, ret;
2570         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2571
2572         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2573         if (ret != I40E_SUCCESS)
2574                 return ret;
2575
2576         if (!vsi->seid) {
2577                 PMD_DRV_LOG(ERR, "seid not valid");
2578                 return -EINVAL;
2579         }
2580
2581         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2582         tc_bw_data.tc_valid_bits = enabled_tcmap;
2583         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2584                 tc_bw_data.tc_bw_credits[i] =
2585                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2586
2587         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2588         if (ret != I40E_SUCCESS) {
2589                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2590                 return ret;
2591         }
2592
2593         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2594                                         sizeof(vsi->info.qs_handle));
2595         return I40E_SUCCESS;
2596 }
2597
2598 static int
2599 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2600                                  struct i40e_aqc_vsi_properties_data *info,
2601                                  uint8_t enabled_tcmap)
2602 {
2603         int ret, total_tc = 0, i;
2604         uint16_t qpnum_per_tc, bsf, qp_idx;
2605
2606         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2607         if (ret != I40E_SUCCESS)
2608                 return ret;
2609
2610         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2611                 if (enabled_tcmap & (1 << i))
2612                         total_tc++;
2613         vsi->enabled_tc = enabled_tcmap;
2614
2615         /* Number of queues per enabled TC */
2616         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2617         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2618         bsf = rte_bsf32(qpnum_per_tc);
2619
2620         /* Adjust the queue number to actual queues that can be applied */
2621         vsi->nb_qps = qpnum_per_tc * total_tc;
2622
2623         /**
2624          * Configure TC and queue mapping parameters, for enabled TC,
2625          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2626          * default queue will serve it.
2627          */
2628         qp_idx = 0;
2629         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2630                 if (vsi->enabled_tc & (1 << i)) {
2631                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2632                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2633                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2634                         qp_idx += qpnum_per_tc;
2635                 } else
2636                         info->tc_mapping[i] = 0;
2637         }
2638
2639         /* Associate queue number with VSI */
2640         if (vsi->type == I40E_VSI_SRIOV) {
2641                 info->mapping_flags |=
2642                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2643                 for (i = 0; i < vsi->nb_qps; i++)
2644                         info->queue_mapping[i] =
2645                                 rte_cpu_to_le_16(vsi->base_queue + i);
2646         } else {
2647                 info->mapping_flags |=
2648                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2649                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2650         }
2651         info->valid_sections |=
2652                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2653
2654         return I40E_SUCCESS;
2655 }
2656
2657 static int
2658 i40e_veb_release(struct i40e_veb *veb)
2659 {
2660         struct i40e_vsi *vsi;
2661         struct i40e_hw *hw;
2662
2663         if (veb == NULL || veb->associate_vsi == NULL)
2664                 return -EINVAL;
2665
2666         if (!TAILQ_EMPTY(&veb->head)) {
2667                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2668                 return -EACCES;
2669         }
2670
2671         vsi = veb->associate_vsi;
2672         hw = I40E_VSI_TO_HW(vsi);
2673
2674         vsi->uplink_seid = veb->uplink_seid;
2675         i40e_aq_delete_element(hw, veb->seid, NULL);
2676         rte_free(veb);
2677         vsi->veb = NULL;
2678         return I40E_SUCCESS;
2679 }
2680
2681 /* Setup a veb */
2682 static struct i40e_veb *
2683 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2684 {
2685         struct i40e_veb *veb;
2686         int ret;
2687         struct i40e_hw *hw;
2688
2689         if (NULL == pf || vsi == NULL) {
2690                 PMD_DRV_LOG(ERR, "veb setup failed, "
2691                             "associated VSI shouldn't null");
2692                 return NULL;
2693         }
2694         hw = I40E_PF_TO_HW(pf);
2695
2696         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2697         if (!veb) {
2698                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2699                 goto fail;
2700         }
2701
2702         veb->associate_vsi = vsi;
2703         TAILQ_INIT(&veb->head);
2704         veb->uplink_seid = vsi->uplink_seid;
2705
2706         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2707                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2708
2709         if (ret != I40E_SUCCESS) {
2710                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2711                             hw->aq.asq_last_status);
2712                 goto fail;
2713         }
2714
2715         /* get statistics index */
2716         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2717                                 &veb->stats_idx, NULL, NULL, NULL);
2718         if (ret != I40E_SUCCESS) {
2719                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2720                             hw->aq.asq_last_status);
2721                 goto fail;
2722         }
2723
2724         /* Get VEB bandwidth, to be implemented */
2725         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2726         vsi->uplink_seid = veb->seid;
2727
2728         return veb;
2729 fail:
2730         rte_free(veb);
2731         return NULL;
2732 }
2733
2734 int
2735 i40e_vsi_release(struct i40e_vsi *vsi)
2736 {
2737         struct i40e_pf *pf;
2738         struct i40e_hw *hw;
2739         struct i40e_vsi_list *vsi_list;
2740         int ret;
2741         struct i40e_mac_filter *f;
2742
2743         if (!vsi)
2744                 return I40E_SUCCESS;
2745
2746         pf = I40E_VSI_TO_PF(vsi);
2747         hw = I40E_VSI_TO_HW(vsi);
2748
2749         /* VSI has child to attach, release child first */
2750         if (vsi->veb) {
2751                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2752                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2753                                 return -1;
2754                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2755                 }
2756                 i40e_veb_release(vsi->veb);
2757         }
2758
2759         /* Remove all macvlan filters of the VSI */
2760         i40e_vsi_remove_all_macvlan_filter(vsi);
2761         TAILQ_FOREACH(f, &vsi->mac_list, next)
2762                 rte_free(f);
2763
2764         if (vsi->type != I40E_VSI_MAIN) {
2765                 /* Remove vsi from parent's sibling list */
2766                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2767                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2768                         return I40E_ERR_PARAM;
2769                 }
2770                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2771                                 &vsi->sib_vsi_list, list);
2772
2773                 /* Remove all switch element of the VSI */
2774                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2775                 if (ret != I40E_SUCCESS)
2776                         PMD_DRV_LOG(ERR, "Failed to delete element");
2777         }
2778         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2779
2780         if (vsi->type != I40E_VSI_SRIOV)
2781                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2782         rte_free(vsi);
2783
2784         return I40E_SUCCESS;
2785 }
2786
2787 static int
2788 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2789 {
2790         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2791         struct i40e_aqc_remove_macvlan_element_data def_filter;
2792         struct i40e_mac_filter_info filter;
2793         int ret;
2794
2795         if (vsi->type != I40E_VSI_MAIN)
2796                 return I40E_ERR_CONFIG;
2797         memset(&def_filter, 0, sizeof(def_filter));
2798         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2799                                         ETH_ADDR_LEN);
2800         def_filter.vlan_tag = 0;
2801         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2802                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2803         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2804         if (ret != I40E_SUCCESS) {
2805                 struct i40e_mac_filter *f;
2806                 struct ether_addr *mac;
2807
2808                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2809                             "macvlan filter");
2810                 /* It needs to add the permanent mac into mac list */
2811                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2812                 if (f == NULL) {
2813                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2814                         return I40E_ERR_NO_MEMORY;
2815                 }
2816                 mac = &f->mac_info.mac_addr;
2817                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2818                                 ETH_ADDR_LEN);
2819                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2820                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2821                 vsi->mac_num++;
2822
2823                 return ret;
2824         }
2825         (void)rte_memcpy(&filter.mac_addr,
2826                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2827         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2828         return i40e_vsi_add_mac(vsi, &filter);
2829 }
2830
2831 static int
2832 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2833 {
2834         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2835         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2836         struct i40e_hw *hw = &vsi->adapter->hw;
2837         i40e_status ret;
2838         int i;
2839
2840         memset(&bw_config, 0, sizeof(bw_config));
2841         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2842         if (ret != I40E_SUCCESS) {
2843                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2844                             hw->aq.asq_last_status);
2845                 return ret;
2846         }
2847
2848         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2849         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2850                                         &ets_sla_config, NULL);
2851         if (ret != I40E_SUCCESS) {
2852                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2853                             "configuration %u", hw->aq.asq_last_status);
2854                 return ret;
2855         }
2856
2857         /* Not store the info yet, just print out */
2858         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2859         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2860         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2861                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2862                             ets_sla_config.share_credits[i]);
2863                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2864                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2865                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2866                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2867                             (i * 4));
2868         }
2869
2870         return 0;
2871 }
2872
2873 /*
2874  * i40e_enable_pf_lb
2875  * @pf: pointer to the pf structure
2876  *
2877  * allow loopback on pf
2878  */
2879 static inline void
2880 i40e_enable_pf_lb(struct i40e_pf *pf)
2881 {
2882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2883         struct i40e_vsi_context ctxt;
2884         int ret;
2885
2886         memset(&ctxt, 0, sizeof(ctxt));
2887         ctxt.seid = pf->main_vsi_seid;
2888         ctxt.pf_num = hw->pf_id;
2889         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2890         if (ret) {
2891                 PMD_DRV_LOG(ERR, "couldn't get pf vsi config, err %d, aq_err %d",
2892                         ret, hw->aq.asq_last_status);
2893                 return;
2894         }
2895         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
2896         ctxt.info.valid_sections =
2897                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2898         ctxt.info.switch_id |=
2899                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2900
2901         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2902         if (ret)
2903                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
2904                         hw->aq.asq_last_status);
2905 }
2906
2907 /* Setup a VSI */
2908 struct i40e_vsi *
2909 i40e_vsi_setup(struct i40e_pf *pf,
2910                enum i40e_vsi_type type,
2911                struct i40e_vsi *uplink_vsi,
2912                uint16_t user_param)
2913 {
2914         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2915         struct i40e_vsi *vsi;
2916         struct i40e_mac_filter_info filter;
2917         int ret;
2918         struct i40e_vsi_context ctxt;
2919         struct ether_addr broadcast =
2920                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2921
2922         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2923                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2924                             "VSI link shouldn't be NULL");
2925                 return NULL;
2926         }
2927
2928         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2929                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2930                             "uplink VSI should be NULL");
2931                 return NULL;
2932         }
2933
2934         /* If uplink vsi didn't setup VEB, create one first */
2935         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2936                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2937
2938                 if (NULL == uplink_vsi->veb) {
2939                         PMD_DRV_LOG(ERR, "VEB setup failed");
2940                         return NULL;
2941                 }
2942                 /* set ALLOWLOOPBACk on pf, when veb is created */
2943                 i40e_enable_pf_lb(pf);
2944         }
2945
2946         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2947         if (!vsi) {
2948                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2949                 return NULL;
2950         }
2951         TAILQ_INIT(&vsi->mac_list);
2952         vsi->type = type;
2953         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2954         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2955         vsi->parent_vsi = uplink_vsi;
2956         vsi->user_param = user_param;
2957         /* Allocate queues */
2958         switch (vsi->type) {
2959         case I40E_VSI_MAIN  :
2960                 vsi->nb_qps = pf->lan_nb_qps;
2961                 break;
2962         case I40E_VSI_SRIOV :
2963                 vsi->nb_qps = pf->vf_nb_qps;
2964                 break;
2965         case I40E_VSI_VMDQ2:
2966                 vsi->nb_qps = pf->vmdq_nb_qps;
2967                 break;
2968         case I40E_VSI_FDIR:
2969                 vsi->nb_qps = pf->fdir_nb_qps;
2970                 break;
2971         default:
2972                 goto fail_mem;
2973         }
2974         /*
2975          * The filter status descriptor is reported in rx queue 0,
2976          * while the tx queue for fdir filter programming has no
2977          * such constraints, can be non-zero queues.
2978          * To simplify it, choose FDIR vsi use queue 0 pair.
2979          * To make sure it will use queue 0 pair, queue allocation
2980          * need be done before this function is called
2981          */
2982         if (type != I40E_VSI_FDIR) {
2983                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2984                         if (ret < 0) {
2985                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2986                                                 vsi->seid, ret);
2987                                 goto fail_mem;
2988                         }
2989                         vsi->base_queue = ret;
2990         } else
2991                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2992
2993         /* VF has MSIX interrupt in VF range, don't allocate here */
2994         if (type != I40E_VSI_SRIOV) {
2995                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2996                 if (ret < 0) {
2997                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2998                         goto fail_queue_alloc;
2999                 }
3000                 vsi->msix_intr = ret;
3001         } else
3002                 vsi->msix_intr = 0;
3003         /* Add VSI */
3004         if (type == I40E_VSI_MAIN) {
3005                 /* For main VSI, no need to add since it's default one */
3006                 vsi->uplink_seid = pf->mac_seid;
3007                 vsi->seid = pf->main_vsi_seid;
3008                 /* Bind queues with specific MSIX interrupt */
3009                 /**
3010                  * Needs 2 interrupt at least, one for misc cause which will
3011                  * enabled from OS side, Another for queues binding the
3012                  * interrupt from device side only.
3013                  */
3014
3015                 /* Get default VSI parameters from hardware */
3016                 memset(&ctxt, 0, sizeof(ctxt));
3017                 ctxt.seid = vsi->seid;
3018                 ctxt.pf_num = hw->pf_id;
3019                 ctxt.uplink_seid = vsi->uplink_seid;
3020                 ctxt.vf_num = 0;
3021                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3022                 if (ret != I40E_SUCCESS) {
3023                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3024                         goto fail_msix_alloc;
3025                 }
3026                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3027                         sizeof(struct i40e_aqc_vsi_properties_data));
3028                 vsi->vsi_id = ctxt.vsi_number;
3029                 vsi->info.valid_sections = 0;
3030
3031                 /* Configure tc, enabled TC0 only */
3032                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3033                         I40E_SUCCESS) {
3034                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3035                         goto fail_msix_alloc;
3036                 }
3037
3038                 /* TC, queue mapping */
3039                 memset(&ctxt, 0, sizeof(ctxt));
3040                 vsi->info.valid_sections |=
3041                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3042                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3043                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3044                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3045                         sizeof(struct i40e_aqc_vsi_properties_data));
3046                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3047                                                 I40E_DEFAULT_TCMAP);
3048                 if (ret != I40E_SUCCESS) {
3049                         PMD_DRV_LOG(ERR, "Failed to configure "
3050                                     "TC queue mapping");
3051                         goto fail_msix_alloc;
3052                 }
3053                 ctxt.seid = vsi->seid;
3054                 ctxt.pf_num = hw->pf_id;
3055                 ctxt.uplink_seid = vsi->uplink_seid;
3056                 ctxt.vf_num = 0;
3057
3058                 /* Update VSI parameters */
3059                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3060                 if (ret != I40E_SUCCESS) {
3061                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3062                         goto fail_msix_alloc;
3063                 }
3064
3065                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3066                                                 sizeof(vsi->info.tc_mapping));
3067                 (void)rte_memcpy(&vsi->info.queue_mapping,
3068                                 &ctxt.info.queue_mapping,
3069                         sizeof(vsi->info.queue_mapping));
3070                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3071                 vsi->info.valid_sections = 0;
3072
3073                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3074                                 ETH_ADDR_LEN);
3075
3076                 /**
3077                  * Updating default filter settings are necessary to prevent
3078                  * reception of tagged packets.
3079                  * Some old firmware configurations load a default macvlan
3080                  * filter which accepts both tagged and untagged packets.
3081                  * The updating is to use a normal filter instead if needed.
3082                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3083                  * The firmware with correct configurations load the default
3084                  * macvlan filter which is expected and cannot be removed.
3085                  */
3086                 i40e_update_default_filter_setting(vsi);
3087         } else if (type == I40E_VSI_SRIOV) {
3088                 memset(&ctxt, 0, sizeof(ctxt));
3089                 /**
3090                  * For other VSI, the uplink_seid equals to uplink VSI's
3091                  * uplink_seid since they share same VEB
3092                  */
3093                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3094                 ctxt.pf_num = hw->pf_id;
3095                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3096                 ctxt.uplink_seid = vsi->uplink_seid;
3097                 ctxt.connection_type = 0x1;
3098                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3099
3100                 /* Configure switch ID */
3101                 ctxt.info.valid_sections |=
3102                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3103                 ctxt.info.switch_id =
3104                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3105                 /* Configure port/vlan */
3106                 ctxt.info.valid_sections |=
3107                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3108                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3109                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3110                                                 I40E_DEFAULT_TCMAP);
3111                 if (ret != I40E_SUCCESS) {
3112                         PMD_DRV_LOG(ERR, "Failed to configure "
3113                                     "TC queue mapping");
3114                         goto fail_msix_alloc;
3115                 }
3116                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3117                 ctxt.info.valid_sections |=
3118                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3119                 /**
3120                  * Since VSI is not created yet, only configure parameter,
3121                  * will add vsi below.
3122                  */
3123         } else if (type == I40E_VSI_VMDQ2) {
3124                 memset(&ctxt, 0, sizeof(ctxt));
3125                 /*
3126                  * For other VSI, the uplink_seid equals to uplink VSI's
3127                  * uplink_seid since they share same VEB
3128                  */
3129                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3130                 ctxt.pf_num = hw->pf_id;
3131                 ctxt.vf_num = 0;
3132                 ctxt.uplink_seid = vsi->uplink_seid;
3133                 ctxt.connection_type = 0x1;
3134                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3135
3136                 ctxt.info.valid_sections |=
3137                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3138                 /* user_param carries flag to enable loop back */
3139                 if (user_param) {
3140                         ctxt.info.switch_id =
3141                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3142                         ctxt.info.switch_id |=
3143                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3144                 }
3145
3146                 /* Configure port/vlan */
3147                 ctxt.info.valid_sections |=
3148                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3149                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3150                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3151                                                 I40E_DEFAULT_TCMAP);
3152                 if (ret != I40E_SUCCESS) {
3153                         PMD_DRV_LOG(ERR, "Failed to configure "
3154                                         "TC queue mapping");
3155                         goto fail_msix_alloc;
3156                 }
3157                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3158                 ctxt.info.valid_sections |=
3159                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3160         } else if (type == I40E_VSI_FDIR) {
3161                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3162                 ctxt.pf_num = hw->pf_id;
3163                 ctxt.vf_num = 0;
3164                 ctxt.uplink_seid = vsi->uplink_seid;
3165                 ctxt.connection_type = 0x1;     /* regular data port */
3166                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3167                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3168                                                 I40E_DEFAULT_TCMAP);
3169                 if (ret != I40E_SUCCESS) {
3170                         PMD_DRV_LOG(ERR, "Failed to configure "
3171                                         "TC queue mapping.");
3172                         goto fail_msix_alloc;
3173                 }
3174                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3175                 ctxt.info.valid_sections |=
3176                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3177         } else {
3178                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3179                 goto fail_msix_alloc;
3180         }
3181
3182         if (vsi->type != I40E_VSI_MAIN) {
3183                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3184                 if (ret) {
3185                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3186                                     hw->aq.asq_last_status);
3187                         goto fail_msix_alloc;
3188                 }
3189                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3190                 vsi->info.valid_sections = 0;
3191                 vsi->seid = ctxt.seid;
3192                 vsi->vsi_id = ctxt.vsi_number;
3193                 vsi->sib_vsi_list.vsi = vsi;
3194                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3195                                 &vsi->sib_vsi_list, list);
3196         }
3197
3198         /* MAC/VLAN configuration */
3199         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3200         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3201
3202         ret = i40e_vsi_add_mac(vsi, &filter);
3203         if (ret != I40E_SUCCESS) {
3204                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3205                 goto fail_msix_alloc;
3206         }
3207
3208         /* Get VSI BW information */
3209         i40e_vsi_dump_bw_config(vsi);
3210         return vsi;
3211 fail_msix_alloc:
3212         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3213 fail_queue_alloc:
3214         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3215 fail_mem:
3216         rte_free(vsi);
3217         return NULL;
3218 }
3219
3220 /* Configure vlan stripping on or off */
3221 int
3222 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3223 {
3224         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3225         struct i40e_vsi_context ctxt;
3226         uint8_t vlan_flags;
3227         int ret = I40E_SUCCESS;
3228
3229         /* Check if it has been already on or off */
3230         if (vsi->info.valid_sections &
3231                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3232                 if (on) {
3233                         if ((vsi->info.port_vlan_flags &
3234                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3235                                 return 0; /* already on */
3236                 } else {
3237                         if ((vsi->info.port_vlan_flags &
3238                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3239                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3240                                 return 0; /* already off */
3241                 }
3242         }
3243
3244         if (on)
3245                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3246         else
3247                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3248         vsi->info.valid_sections =
3249                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3250         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3251         vsi->info.port_vlan_flags |= vlan_flags;
3252         ctxt.seid = vsi->seid;
3253         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3254         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3255         if (ret)
3256                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3257                             on ? "enable" : "disable");
3258
3259         return ret;
3260 }
3261
3262 static int
3263 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3264 {
3265         struct rte_eth_dev_data *data = dev->data;
3266         int ret;
3267
3268         /* Apply vlan offload setting */
3269         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3270
3271         /* Apply double-vlan setting, not implemented yet */
3272
3273         /* Apply pvid setting */
3274         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3275                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3276         if (ret)
3277                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3278
3279         return ret;
3280 }
3281
3282 static int
3283 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3284 {
3285         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3286
3287         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3288 }
3289
3290 static int
3291 i40e_update_flow_control(struct i40e_hw *hw)
3292 {
3293 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3294         struct i40e_link_status link_status;
3295         uint32_t rxfc = 0, txfc = 0, reg;
3296         uint8_t an_info;
3297         int ret;
3298
3299         memset(&link_status, 0, sizeof(link_status));
3300         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3301         if (ret != I40E_SUCCESS) {
3302                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3303                 goto write_reg; /* Disable flow control */
3304         }
3305
3306         an_info = hw->phy.link_info.an_info;
3307         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3308                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3309                 ret = I40E_ERR_NOT_READY;
3310                 goto write_reg; /* Disable flow control */
3311         }
3312         /**
3313          * If link auto negotiation is enabled, flow control needs to
3314          * be configured according to it
3315          */
3316         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3317         case I40E_LINK_PAUSE_RXTX:
3318                 rxfc = 1;
3319                 txfc = 1;
3320                 hw->fc.current_mode = I40E_FC_FULL;
3321                 break;
3322         case I40E_AQ_LINK_PAUSE_RX:
3323                 rxfc = 1;
3324                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3325                 break;
3326         case I40E_AQ_LINK_PAUSE_TX:
3327                 txfc = 1;
3328                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3329                 break;
3330         default:
3331                 hw->fc.current_mode = I40E_FC_NONE;
3332                 break;
3333         }
3334
3335 write_reg:
3336         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3337                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3338         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3339         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3340         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3341         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3342
3343         return ret;
3344 }
3345
3346 /* PF setup */
3347 static int
3348 i40e_pf_setup(struct i40e_pf *pf)
3349 {
3350         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3351         struct i40e_filter_control_settings settings;
3352         struct i40e_vsi *vsi;
3353         int ret;
3354
3355         /* Clear all stats counters */
3356         pf->offset_loaded = FALSE;
3357         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3358         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3359
3360         ret = i40e_pf_get_switch_config(pf);
3361         if (ret != I40E_SUCCESS) {
3362                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3363                 return ret;
3364         }
3365         if (pf->flags & I40E_FLAG_FDIR) {
3366                 /* make queue allocated first, let FDIR use queue pair 0*/
3367                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3368                 if (ret != I40E_FDIR_QUEUE_ID) {
3369                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3370                                     " ret =%d", ret);
3371                         pf->flags &= ~I40E_FLAG_FDIR;
3372                 }
3373         }
3374         /*  main VSI setup */
3375         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3376         if (!vsi) {
3377                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3378                 return I40E_ERR_NOT_READY;
3379         }
3380         pf->main_vsi = vsi;
3381
3382         /* Configure filter control */
3383         memset(&settings, 0, sizeof(settings));
3384         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3385                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3386         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3387                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3388         else {
3389                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3390                                                 hw->func_caps.rss_table_size);
3391                 return I40E_ERR_PARAM;
3392         }
3393         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3394                         "size: %u\n", hw->func_caps.rss_table_size);
3395         pf->hash_lut_size = hw->func_caps.rss_table_size;
3396
3397         /* Enable ethtype and macvlan filters */
3398         settings.enable_ethtype = TRUE;
3399         settings.enable_macvlan = TRUE;
3400         ret = i40e_set_filter_control(hw, &settings);
3401         if (ret)
3402                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3403                                                                 ret);
3404
3405         /* Update flow control according to the auto negotiation */
3406         i40e_update_flow_control(hw);
3407
3408         return I40E_SUCCESS;
3409 }
3410
3411 int
3412 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3413 {
3414         uint32_t reg;
3415         uint16_t j;
3416
3417         /**
3418          * Set or clear TX Queue Disable flags,
3419          * which is required by hardware.
3420          */
3421         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3422         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3423
3424         /* Wait until the request is finished */
3425         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3426                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3427                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3428                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3429                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3430                                                         & 0x1))) {
3431                         break;
3432                 }
3433         }
3434         if (on) {
3435                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3436                         return I40E_SUCCESS; /* already on, skip next steps */
3437
3438                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3439                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3440         } else {
3441                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3442                         return I40E_SUCCESS; /* already off, skip next steps */
3443                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3444         }
3445         /* Write the register */
3446         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3447         /* Check the result */
3448         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3449                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3450                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3451                 if (on) {
3452                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3453                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3454                                 break;
3455                 } else {
3456                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3457                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3458                                 break;
3459                 }
3460         }
3461         /* Check if it is timeout */
3462         if (j >= I40E_CHK_Q_ENA_COUNT) {
3463                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3464                             (on ? "enable" : "disable"), q_idx);
3465                 return I40E_ERR_TIMEOUT;
3466         }
3467
3468         return I40E_SUCCESS;
3469 }
3470
3471 /* Swith on or off the tx queues */
3472 static int
3473 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3474 {
3475         struct rte_eth_dev_data *dev_data = pf->dev_data;
3476         struct i40e_tx_queue *txq;
3477         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3478         uint16_t i;
3479         int ret;
3480
3481         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3482                 txq = dev_data->tx_queues[i];
3483                 /* Don't operate the queue if not configured or
3484                  * if starting only per queue */
3485                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3486                         continue;
3487                 if (on)
3488                         ret = i40e_dev_tx_queue_start(dev, i);
3489                 else
3490                         ret = i40e_dev_tx_queue_stop(dev, i);
3491                 if ( ret != I40E_SUCCESS)
3492                         return ret;
3493         }
3494
3495         return I40E_SUCCESS;
3496 }
3497
3498 int
3499 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3500 {
3501         uint32_t reg;
3502         uint16_t j;
3503
3504         /* Wait until the request is finished */
3505         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3506                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3507                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3508                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3509                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3510                         break;
3511         }
3512
3513         if (on) {
3514                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3515                         return I40E_SUCCESS; /* Already on, skip next steps */
3516                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3517         } else {
3518                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3519                         return I40E_SUCCESS; /* Already off, skip next steps */
3520                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3521         }
3522
3523         /* Write the register */
3524         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3525         /* Check the result */
3526         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3527                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3528                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3529                 if (on) {
3530                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3531                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3532                                 break;
3533                 } else {
3534                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3535                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3536                                 break;
3537                 }
3538         }
3539
3540         /* Check if it is timeout */
3541         if (j >= I40E_CHK_Q_ENA_COUNT) {
3542                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3543                             (on ? "enable" : "disable"), q_idx);
3544                 return I40E_ERR_TIMEOUT;
3545         }
3546
3547         return I40E_SUCCESS;
3548 }
3549 /* Switch on or off the rx queues */
3550 static int
3551 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3552 {
3553         struct rte_eth_dev_data *dev_data = pf->dev_data;
3554         struct i40e_rx_queue *rxq;
3555         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3556         uint16_t i;
3557         int ret;
3558
3559         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3560                 rxq = dev_data->rx_queues[i];
3561                 /* Don't operate the queue if not configured or
3562                  * if starting only per queue */
3563                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3564                         continue;
3565                 if (on)
3566                         ret = i40e_dev_rx_queue_start(dev, i);
3567                 else
3568                         ret = i40e_dev_rx_queue_stop(dev, i);
3569                 if (ret != I40E_SUCCESS)
3570                         return ret;
3571         }
3572
3573         return I40E_SUCCESS;
3574 }
3575
3576 /* Switch on or off all the rx/tx queues */
3577 int
3578 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3579 {
3580         int ret;
3581
3582         if (on) {
3583                 /* enable rx queues before enabling tx queues */
3584                 ret = i40e_dev_switch_rx_queues(pf, on);
3585                 if (ret) {
3586                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3587                         return ret;
3588                 }
3589                 ret = i40e_dev_switch_tx_queues(pf, on);
3590         } else {
3591                 /* Stop tx queues before stopping rx queues */
3592                 ret = i40e_dev_switch_tx_queues(pf, on);
3593                 if (ret) {
3594                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3595                         return ret;
3596                 }
3597                 ret = i40e_dev_switch_rx_queues(pf, on);
3598         }
3599
3600         return ret;
3601 }
3602
3603 /* Initialize VSI for TX */
3604 static int
3605 i40e_dev_tx_init(struct i40e_pf *pf)
3606 {
3607         struct rte_eth_dev_data *data = pf->dev_data;
3608         uint16_t i;
3609         uint32_t ret = I40E_SUCCESS;
3610         struct i40e_tx_queue *txq;
3611
3612         for (i = 0; i < data->nb_tx_queues; i++) {
3613                 txq = data->tx_queues[i];
3614                 if (!txq || !txq->q_set)
3615                         continue;
3616                 ret = i40e_tx_queue_init(txq);
3617                 if (ret != I40E_SUCCESS)
3618                         break;
3619         }
3620
3621         return ret;
3622 }
3623
3624 /* Initialize VSI for RX */
3625 static int
3626 i40e_dev_rx_init(struct i40e_pf *pf)
3627 {
3628         struct rte_eth_dev_data *data = pf->dev_data;
3629         int ret = I40E_SUCCESS;
3630         uint16_t i;
3631         struct i40e_rx_queue *rxq;
3632
3633         i40e_pf_config_mq_rx(pf);
3634         for (i = 0; i < data->nb_rx_queues; i++) {
3635                 rxq = data->rx_queues[i];
3636                 if (!rxq || !rxq->q_set)
3637                         continue;
3638
3639                 ret = i40e_rx_queue_init(rxq);
3640                 if (ret != I40E_SUCCESS) {
3641                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3642                                     "initialization");
3643                         break;
3644                 }
3645         }
3646
3647         return ret;
3648 }
3649
3650 static int
3651 i40e_dev_rxtx_init(struct i40e_pf *pf)
3652 {
3653         int err;
3654
3655         err = i40e_dev_tx_init(pf);
3656         if (err) {
3657                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3658                 return err;
3659         }
3660         err = i40e_dev_rx_init(pf);
3661         if (err) {
3662                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3663                 return err;
3664         }
3665
3666         return err;
3667 }
3668
3669 static int
3670 i40e_vmdq_setup(struct rte_eth_dev *dev)
3671 {
3672         struct rte_eth_conf *conf = &dev->data->dev_conf;
3673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3674         int i, err, conf_vsis, j, loop;
3675         struct i40e_vsi *vsi;
3676         struct i40e_vmdq_info *vmdq_info;
3677         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3678         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3679
3680         /*
3681          * Disable interrupt to avoid message from VF. Furthermore, it will
3682          * avoid race condition in VSI creation/destroy.
3683          */
3684         i40e_pf_disable_irq0(hw);
3685
3686         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3687                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3688                 return -ENOTSUP;
3689         }
3690
3691         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3692         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3693                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3694                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3695                         pf->max_nb_vmdq_vsi);
3696                 return -ENOTSUP;
3697         }
3698
3699         if (pf->vmdq != NULL) {
3700                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3701                 return 0;
3702         }
3703
3704         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3705                                 sizeof(*vmdq_info) * conf_vsis, 0);
3706
3707         if (pf->vmdq == NULL) {
3708                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3709                 return -ENOMEM;
3710         }
3711
3712         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3713
3714         /* Create VMDQ VSI */
3715         for (i = 0; i < conf_vsis; i++) {
3716                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3717                                 vmdq_conf->enable_loop_back);
3718                 if (vsi == NULL) {
3719                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3720                         err = -1;
3721                         goto err_vsi_setup;
3722                 }
3723                 vmdq_info = &pf->vmdq[i];
3724                 vmdq_info->pf = pf;
3725                 vmdq_info->vsi = vsi;
3726         }
3727         pf->nb_cfg_vmdq_vsi = conf_vsis;
3728
3729         /* Configure Vlan */
3730         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3731         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3732                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3733                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3734                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3735                                         vmdq_conf->pool_map[i].vlan_id, j);
3736
3737                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3738                                                 vmdq_conf->pool_map[i].vlan_id);
3739                                 if (err) {
3740                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3741                                         err = -1;
3742                                         goto err_vsi_setup;
3743                                 }
3744                         }
3745                 }
3746         }
3747
3748         i40e_pf_enable_irq0(hw);
3749
3750         return 0;
3751
3752 err_vsi_setup:
3753         for (i = 0; i < conf_vsis; i++)
3754                 if (pf->vmdq[i].vsi == NULL)
3755                         break;
3756                 else
3757                         i40e_vsi_release(pf->vmdq[i].vsi);
3758
3759         rte_free(pf->vmdq);
3760         pf->vmdq = NULL;
3761         i40e_pf_enable_irq0(hw);
3762         return err;
3763 }
3764
3765 static void
3766 i40e_stat_update_32(struct i40e_hw *hw,
3767                    uint32_t reg,
3768                    bool offset_loaded,
3769                    uint64_t *offset,
3770                    uint64_t *stat)
3771 {
3772         uint64_t new_data;
3773
3774         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3775         if (!offset_loaded)
3776                 *offset = new_data;
3777
3778         if (new_data >= *offset)
3779                 *stat = (uint64_t)(new_data - *offset);
3780         else
3781                 *stat = (uint64_t)((new_data +
3782                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3783 }
3784
3785 static void
3786 i40e_stat_update_48(struct i40e_hw *hw,
3787                    uint32_t hireg,
3788                    uint32_t loreg,
3789                    bool offset_loaded,
3790                    uint64_t *offset,
3791                    uint64_t *stat)
3792 {
3793         uint64_t new_data;
3794
3795         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3796         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3797                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3798
3799         if (!offset_loaded)
3800                 *offset = new_data;
3801
3802         if (new_data >= *offset)
3803                 *stat = new_data - *offset;
3804         else
3805                 *stat = (uint64_t)((new_data +
3806                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3807
3808         *stat &= I40E_48_BIT_MASK;
3809 }
3810
3811 /* Disable IRQ0 */
3812 void
3813 i40e_pf_disable_irq0(struct i40e_hw *hw)
3814 {
3815         /* Disable all interrupt types */
3816         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3817         I40E_WRITE_FLUSH(hw);
3818 }
3819
3820 /* Enable IRQ0 */
3821 void
3822 i40e_pf_enable_irq0(struct i40e_hw *hw)
3823 {
3824         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3825                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3826                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3827                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3828         I40E_WRITE_FLUSH(hw);
3829 }
3830
3831 static void
3832 i40e_pf_config_irq0(struct i40e_hw *hw)
3833 {
3834         /* read pending request and disable first */
3835         i40e_pf_disable_irq0(hw);
3836         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3837         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3838                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3839
3840         /* Link no queues with irq0 */
3841         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3842                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3843 }
3844
3845 static void
3846 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3847 {
3848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3850         int i;
3851         uint16_t abs_vf_id;
3852         uint32_t index, offset, val;
3853
3854         if (!pf->vfs)
3855                 return;
3856         /**
3857          * Try to find which VF trigger a reset, use absolute VF id to access
3858          * since the reg is global register.
3859          */
3860         for (i = 0; i < pf->vf_num; i++) {
3861                 abs_vf_id = hw->func_caps.vf_base_id + i;
3862                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3863                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3864                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3865                 /* VFR event occured */
3866                 if (val & (0x1 << offset)) {
3867                         int ret;
3868
3869                         /* Clear the event first */
3870                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3871                                                         (0x1 << offset));
3872                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3873                         /**
3874                          * Only notify a VF reset event occured,
3875                          * don't trigger another SW reset
3876                          */
3877                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3878                         if (ret != I40E_SUCCESS)
3879                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3880                 }
3881         }
3882 }
3883
3884 static void
3885 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3886 {
3887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888         struct i40e_arq_event_info info;
3889         uint16_t pending, opcode;
3890         int ret;
3891
3892         info.buf_len = I40E_AQ_BUF_SZ;
3893         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3894         if (!info.msg_buf) {
3895                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3896                 return;
3897         }
3898
3899         pending = 1;
3900         while (pending) {
3901                 ret = i40e_clean_arq_element(hw, &info, &pending);
3902
3903                 if (ret != I40E_SUCCESS) {
3904                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3905                                     "aq_err: %u", hw->aq.asq_last_status);
3906                         break;
3907                 }
3908                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3909
3910                 switch (opcode) {
3911                 case i40e_aqc_opc_send_msg_to_pf:
3912                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3913                         i40e_pf_host_handle_vf_msg(dev,
3914                                         rte_le_to_cpu_16(info.desc.retval),
3915                                         rte_le_to_cpu_32(info.desc.cookie_high),
3916                                         rte_le_to_cpu_32(info.desc.cookie_low),
3917                                         info.msg_buf,
3918                                         info.msg_len);
3919                         break;
3920                 default:
3921                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3922                                     opcode);
3923                         break;
3924                 }
3925         }
3926         rte_free(info.msg_buf);
3927 }
3928
3929 /*
3930  * Interrupt handler is registered as the alarm callback for handling LSC
3931  * interrupt in a definite of time, in order to wait the NIC into a stable
3932  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3933  * no need for link down interrupt.
3934  */
3935 static void
3936 i40e_dev_interrupt_delayed_handler(void *param)
3937 {
3938         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940         uint32_t icr0;
3941
3942         /* read interrupt causes again */
3943         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3944
3945 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3946         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3947                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3948         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3949                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3950         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3951                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3952         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3953                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3954         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3955                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3956                                                                 "state\n");
3957         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3958                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3959         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3960                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3961 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3962
3963         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3964                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3965                 i40e_dev_handle_vfr_event(dev);
3966         }
3967         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3968                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3969                 i40e_dev_handle_aq_msg(dev);
3970         }
3971
3972         /* handle the link up interrupt in an alarm callback */
3973         i40e_dev_link_update(dev, 0);
3974         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3975
3976         i40e_pf_enable_irq0(hw);
3977         rte_intr_enable(&(dev->pci_dev->intr_handle));
3978 }
3979
3980 /**
3981  * Interrupt handler triggered by NIC  for handling
3982  * specific interrupt.
3983  *
3984  * @param handle
3985  *  Pointer to interrupt handle.
3986  * @param param
3987  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3988  *
3989  * @return
3990  *  void
3991  */
3992 static void
3993 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3994                            void *param)
3995 {
3996         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998         uint32_t icr0;
3999
4000         /* Disable interrupt */
4001         i40e_pf_disable_irq0(hw);
4002
4003         /* read out interrupt causes */
4004         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4005
4006         /* No interrupt event indicated */
4007         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4008                 PMD_DRV_LOG(INFO, "No interrupt event");
4009                 goto done;
4010         }
4011 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4012         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4013                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4014         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4015                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4016         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4017                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4018         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4019                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4020         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4021                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4022         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4023                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4024         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4025                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4026 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4027
4028         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4029                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4030                 i40e_dev_handle_vfr_event(dev);
4031         }
4032         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4033                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4034                 i40e_dev_handle_aq_msg(dev);
4035         }
4036
4037         /* Link Status Change interrupt */
4038         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4039 #define I40E_US_PER_SECOND 1000000
4040                 struct rte_eth_link link;
4041
4042                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4043                 memset(&link, 0, sizeof(link));
4044                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4045                 i40e_dev_link_update(dev, 0);
4046
4047                 /*
4048                  * For link up interrupt, it needs to wait 1 second to let the
4049                  * hardware be a stable state. Otherwise several consecutive
4050                  * interrupts can be observed.
4051                  * For link down interrupt, no need to wait.
4052                  */
4053                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4054                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4055                         return;
4056                 else
4057                         _rte_eth_dev_callback_process(dev,
4058                                 RTE_ETH_EVENT_INTR_LSC);
4059         }
4060
4061 done:
4062         /* Enable interrupt */
4063         i40e_pf_enable_irq0(hw);
4064         rte_intr_enable(&(dev->pci_dev->intr_handle));
4065 }
4066
4067 static int
4068 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4069                          struct i40e_macvlan_filter *filter,
4070                          int total)
4071 {
4072         int ele_num, ele_buff_size;
4073         int num, actual_num, i;
4074         uint16_t flags;
4075         int ret = I40E_SUCCESS;
4076         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4077         struct i40e_aqc_add_macvlan_element_data *req_list;
4078
4079         if (filter == NULL  || total == 0)
4080                 return I40E_ERR_PARAM;
4081         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4082         ele_buff_size = hw->aq.asq_buf_size;
4083
4084         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4085         if (req_list == NULL) {
4086                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4087                 return I40E_ERR_NO_MEMORY;
4088         }
4089
4090         num = 0;
4091         do {
4092                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4093                 memset(req_list, 0, ele_buff_size);
4094
4095                 for (i = 0; i < actual_num; i++) {
4096                         (void)rte_memcpy(req_list[i].mac_addr,
4097                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4098                         req_list[i].vlan_tag =
4099                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4100
4101                         switch (filter[num + i].filter_type) {
4102                         case RTE_MAC_PERFECT_MATCH:
4103                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4104                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4105                                 break;
4106                         case RTE_MACVLAN_PERFECT_MATCH:
4107                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4108                                 break;
4109                         case RTE_MAC_HASH_MATCH:
4110                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4111                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4112                                 break;
4113                         case RTE_MACVLAN_HASH_MATCH:
4114                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4115                                 break;
4116                         default:
4117                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4118                                 ret = I40E_ERR_PARAM;
4119                                 goto DONE;
4120                         }
4121
4122                         req_list[i].queue_number = 0;
4123
4124                         req_list[i].flags = rte_cpu_to_le_16(flags);
4125                 }
4126
4127                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4128                                                 actual_num, NULL);
4129                 if (ret != I40E_SUCCESS) {
4130                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4131                         goto DONE;
4132                 }
4133                 num += actual_num;
4134         } while (num < total);
4135
4136 DONE:
4137         rte_free(req_list);
4138         return ret;
4139 }
4140
4141 static int
4142 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4143                             struct i40e_macvlan_filter *filter,
4144                             int total)
4145 {
4146         int ele_num, ele_buff_size;
4147         int num, actual_num, i;
4148         uint16_t flags;
4149         int ret = I40E_SUCCESS;
4150         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4151         struct i40e_aqc_remove_macvlan_element_data *req_list;
4152
4153         if (filter == NULL  || total == 0)
4154                 return I40E_ERR_PARAM;
4155
4156         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4157         ele_buff_size = hw->aq.asq_buf_size;
4158
4159         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4160         if (req_list == NULL) {
4161                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4162                 return I40E_ERR_NO_MEMORY;
4163         }
4164
4165         num = 0;
4166         do {
4167                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4168                 memset(req_list, 0, ele_buff_size);
4169
4170                 for (i = 0; i < actual_num; i++) {
4171                         (void)rte_memcpy(req_list[i].mac_addr,
4172                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4173                         req_list[i].vlan_tag =
4174                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4175
4176                         switch (filter[num + i].filter_type) {
4177                         case RTE_MAC_PERFECT_MATCH:
4178                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4179                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4180                                 break;
4181                         case RTE_MACVLAN_PERFECT_MATCH:
4182                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4183                                 break;
4184                         case RTE_MAC_HASH_MATCH:
4185                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4186                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4187                                 break;
4188                         case RTE_MACVLAN_HASH_MATCH:
4189                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4190                                 break;
4191                         default:
4192                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4193                                 ret = I40E_ERR_PARAM;
4194                                 goto DONE;
4195                         }
4196                         req_list[i].flags = rte_cpu_to_le_16(flags);
4197                 }
4198
4199                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4200                                                 actual_num, NULL);
4201                 if (ret != I40E_SUCCESS) {
4202                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4203                         goto DONE;
4204                 }
4205                 num += actual_num;
4206         } while (num < total);
4207
4208 DONE:
4209         rte_free(req_list);
4210         return ret;
4211 }
4212
4213 /* Find out specific MAC filter */
4214 static struct i40e_mac_filter *
4215 i40e_find_mac_filter(struct i40e_vsi *vsi,
4216                          struct ether_addr *macaddr)
4217 {
4218         struct i40e_mac_filter *f;
4219
4220         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4221                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4222                         return f;
4223         }
4224
4225         return NULL;
4226 }
4227
4228 static bool
4229 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4230                          uint16_t vlan_id)
4231 {
4232         uint32_t vid_idx, vid_bit;
4233
4234         if (vlan_id > ETH_VLAN_ID_MAX)
4235                 return 0;
4236
4237         vid_idx = I40E_VFTA_IDX(vlan_id);
4238         vid_bit = I40E_VFTA_BIT(vlan_id);
4239
4240         if (vsi->vfta[vid_idx] & vid_bit)
4241                 return 1;
4242         else
4243                 return 0;
4244 }
4245
4246 static void
4247 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4248                          uint16_t vlan_id, bool on)
4249 {
4250         uint32_t vid_idx, vid_bit;
4251
4252         if (vlan_id > ETH_VLAN_ID_MAX)
4253                 return;
4254
4255         vid_idx = I40E_VFTA_IDX(vlan_id);
4256         vid_bit = I40E_VFTA_BIT(vlan_id);
4257
4258         if (on)
4259                 vsi->vfta[vid_idx] |= vid_bit;
4260         else
4261                 vsi->vfta[vid_idx] &= ~vid_bit;
4262 }
4263
4264 /**
4265  * Find all vlan options for specific mac addr,
4266  * return with actual vlan found.
4267  */
4268 static inline int
4269 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4270                            struct i40e_macvlan_filter *mv_f,
4271                            int num, struct ether_addr *addr)
4272 {
4273         int i;
4274         uint32_t j, k;
4275
4276         /**
4277          * Not to use i40e_find_vlan_filter to decrease the loop time,
4278          * although the code looks complex.
4279           */
4280         if (num < vsi->vlan_num)
4281                 return I40E_ERR_PARAM;
4282
4283         i = 0;
4284         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4285                 if (vsi->vfta[j]) {
4286                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4287                                 if (vsi->vfta[j] & (1 << k)) {
4288                                         if (i > num - 1) {
4289                                                 PMD_DRV_LOG(ERR, "vlan number "
4290                                                             "not match");
4291                                                 return I40E_ERR_PARAM;
4292                                         }
4293                                         (void)rte_memcpy(&mv_f[i].macaddr,
4294                                                         addr, ETH_ADDR_LEN);
4295                                         mv_f[i].vlan_id =
4296                                                 j * I40E_UINT32_BIT_SIZE + k;
4297                                         i++;
4298                                 }
4299                         }
4300                 }
4301         }
4302         return I40E_SUCCESS;
4303 }
4304
4305 static inline int
4306 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4307                            struct i40e_macvlan_filter *mv_f,
4308                            int num,
4309                            uint16_t vlan)
4310 {
4311         int i = 0;
4312         struct i40e_mac_filter *f;
4313
4314         if (num < vsi->mac_num)
4315                 return I40E_ERR_PARAM;
4316
4317         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4318                 if (i > num - 1) {
4319                         PMD_DRV_LOG(ERR, "buffer number not match");
4320                         return I40E_ERR_PARAM;
4321                 }
4322                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4323                                 ETH_ADDR_LEN);
4324                 mv_f[i].vlan_id = vlan;
4325                 mv_f[i].filter_type = f->mac_info.filter_type;
4326                 i++;
4327         }
4328
4329         return I40E_SUCCESS;
4330 }
4331
4332 static int
4333 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4334 {
4335         int i, num;
4336         struct i40e_mac_filter *f;
4337         struct i40e_macvlan_filter *mv_f;
4338         int ret = I40E_SUCCESS;
4339
4340         if (vsi == NULL || vsi->mac_num == 0)
4341                 return I40E_ERR_PARAM;
4342
4343         /* Case that no vlan is set */
4344         if (vsi->vlan_num == 0)
4345                 num = vsi->mac_num;
4346         else
4347                 num = vsi->mac_num * vsi->vlan_num;
4348
4349         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4350         if (mv_f == NULL) {
4351                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4352                 return I40E_ERR_NO_MEMORY;
4353         }
4354
4355         i = 0;
4356         if (vsi->vlan_num == 0) {
4357                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4358                         (void)rte_memcpy(&mv_f[i].macaddr,
4359                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4360                         mv_f[i].vlan_id = 0;
4361                         i++;
4362                 }
4363         } else {
4364                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4365                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4366                                         vsi->vlan_num, &f->mac_info.mac_addr);
4367                         if (ret != I40E_SUCCESS)
4368                                 goto DONE;
4369                         i += vsi->vlan_num;
4370                 }
4371         }
4372
4373         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4374 DONE:
4375         rte_free(mv_f);
4376
4377         return ret;
4378 }
4379
4380 int
4381 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4382 {
4383         struct i40e_macvlan_filter *mv_f;
4384         int mac_num;
4385         int ret = I40E_SUCCESS;
4386
4387         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4388                 return I40E_ERR_PARAM;
4389
4390         /* If it's already set, just return */
4391         if (i40e_find_vlan_filter(vsi,vlan))
4392                 return I40E_SUCCESS;
4393
4394         mac_num = vsi->mac_num;
4395
4396         if (mac_num == 0) {
4397                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4398                 return I40E_ERR_PARAM;
4399         }
4400
4401         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4402
4403         if (mv_f == NULL) {
4404                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4405                 return I40E_ERR_NO_MEMORY;
4406         }
4407
4408         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4409
4410         if (ret != I40E_SUCCESS)
4411                 goto DONE;
4412
4413         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4414
4415         if (ret != I40E_SUCCESS)
4416                 goto DONE;
4417
4418         i40e_set_vlan_filter(vsi, vlan, 1);
4419
4420         vsi->vlan_num++;
4421         ret = I40E_SUCCESS;
4422 DONE:
4423         rte_free(mv_f);
4424         return ret;
4425 }
4426
4427 int
4428 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4429 {
4430         struct i40e_macvlan_filter *mv_f;
4431         int mac_num;
4432         int ret = I40E_SUCCESS;
4433
4434         /**
4435          * Vlan 0 is the generic filter for untagged packets
4436          * and can't be removed.
4437          */
4438         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4439                 return I40E_ERR_PARAM;
4440
4441         /* If can't find it, just return */
4442         if (!i40e_find_vlan_filter(vsi, vlan))
4443                 return I40E_ERR_PARAM;
4444
4445         mac_num = vsi->mac_num;
4446
4447         if (mac_num == 0) {
4448                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4449                 return I40E_ERR_PARAM;
4450         }
4451
4452         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4453
4454         if (mv_f == NULL) {
4455                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4456                 return I40E_ERR_NO_MEMORY;
4457         }
4458
4459         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4460
4461         if (ret != I40E_SUCCESS)
4462                 goto DONE;
4463
4464         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4465
4466         if (ret != I40E_SUCCESS)
4467                 goto DONE;
4468
4469         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4470         if (vsi->vlan_num == 1) {
4471                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4472                 if (ret != I40E_SUCCESS)
4473                         goto DONE;
4474
4475                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4476                 if (ret != I40E_SUCCESS)
4477                         goto DONE;
4478         }
4479
4480         i40e_set_vlan_filter(vsi, vlan, 0);
4481
4482         vsi->vlan_num--;
4483         ret = I40E_SUCCESS;
4484 DONE:
4485         rte_free(mv_f);
4486         return ret;
4487 }
4488
4489 int
4490 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4491 {
4492         struct i40e_mac_filter *f;
4493         struct i40e_macvlan_filter *mv_f;
4494         int i, vlan_num = 0;
4495         int ret = I40E_SUCCESS;
4496
4497         /* If it's add and we've config it, return */
4498         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4499         if (f != NULL)
4500                 return I40E_SUCCESS;
4501         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4502                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4503
4504                 /**
4505                  * If vlan_num is 0, that's the first time to add mac,
4506                  * set mask for vlan_id 0.
4507                  */
4508                 if (vsi->vlan_num == 0) {
4509                         i40e_set_vlan_filter(vsi, 0, 1);
4510                         vsi->vlan_num = 1;
4511                 }
4512                 vlan_num = vsi->vlan_num;
4513         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4514                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4515                 vlan_num = 1;
4516
4517         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4518         if (mv_f == NULL) {
4519                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4520                 return I40E_ERR_NO_MEMORY;
4521         }
4522
4523         for (i = 0; i < vlan_num; i++) {
4524                 mv_f[i].filter_type = mac_filter->filter_type;
4525                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4526                                 ETH_ADDR_LEN);
4527         }
4528
4529         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4530                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4531                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4532                                         &mac_filter->mac_addr);
4533                 if (ret != I40E_SUCCESS)
4534                         goto DONE;
4535         }
4536
4537         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4538         if (ret != I40E_SUCCESS)
4539                 goto DONE;
4540
4541         /* Add the mac addr into mac list */
4542         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4543         if (f == NULL) {
4544                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4545                 ret = I40E_ERR_NO_MEMORY;
4546                 goto DONE;
4547         }
4548         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4549                         ETH_ADDR_LEN);
4550         f->mac_info.filter_type = mac_filter->filter_type;
4551         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4552         vsi->mac_num++;
4553
4554         ret = I40E_SUCCESS;
4555 DONE:
4556         rte_free(mv_f);
4557
4558         return ret;
4559 }
4560
4561 int
4562 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4563 {
4564         struct i40e_mac_filter *f;
4565         struct i40e_macvlan_filter *mv_f;
4566         int i, vlan_num;
4567         enum rte_mac_filter_type filter_type;
4568         int ret = I40E_SUCCESS;
4569
4570         /* Can't find it, return an error */
4571         f = i40e_find_mac_filter(vsi, addr);
4572         if (f == NULL)
4573                 return I40E_ERR_PARAM;
4574
4575         vlan_num = vsi->vlan_num;
4576         filter_type = f->mac_info.filter_type;
4577         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4578                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4579                 if (vlan_num == 0) {
4580                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4581                         return I40E_ERR_PARAM;
4582                 }
4583         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4584                         filter_type == RTE_MAC_HASH_MATCH)
4585                 vlan_num = 1;
4586
4587         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4588         if (mv_f == NULL) {
4589                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4590                 return I40E_ERR_NO_MEMORY;
4591         }
4592
4593         for (i = 0; i < vlan_num; i++) {
4594                 mv_f[i].filter_type = filter_type;
4595                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4596                                 ETH_ADDR_LEN);
4597         }
4598         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4599                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4600                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4601                 if (ret != I40E_SUCCESS)
4602                         goto DONE;
4603         }
4604
4605         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4606         if (ret != I40E_SUCCESS)
4607                 goto DONE;
4608
4609         /* Remove the mac addr into mac list */
4610         TAILQ_REMOVE(&vsi->mac_list, f, next);
4611         rte_free(f);
4612         vsi->mac_num--;
4613
4614         ret = I40E_SUCCESS;
4615 DONE:
4616         rte_free(mv_f);
4617         return ret;
4618 }
4619
4620 /* Configure hash enable flags for RSS */
4621 uint64_t
4622 i40e_config_hena(uint64_t flags)
4623 {
4624         uint64_t hena = 0;
4625
4626         if (!flags)
4627                 return hena;
4628
4629         if (flags & ETH_RSS_FRAG_IPV4)
4630                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4631         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4632                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4633         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4634                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4635         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4636                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4637         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4638                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4639         if (flags & ETH_RSS_FRAG_IPV6)
4640                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4641         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4642                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4643         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4644                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4645         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4646                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4647         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4648                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4649         if (flags & ETH_RSS_L2_PAYLOAD)
4650                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4651
4652         return hena;
4653 }
4654
4655 /* Parse the hash enable flags */
4656 uint64_t
4657 i40e_parse_hena(uint64_t flags)
4658 {
4659         uint64_t rss_hf = 0;
4660
4661         if (!flags)
4662                 return rss_hf;
4663         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4664                 rss_hf |= ETH_RSS_FRAG_IPV4;
4665         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4666                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4667         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4668                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4669         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4670                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4671         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4672                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4673         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4674                 rss_hf |= ETH_RSS_FRAG_IPV6;
4675         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4676                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4677         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4678                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4679         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4680                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4681         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4682                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4683         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4684                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4685
4686         return rss_hf;
4687 }
4688
4689 /* Disable RSS */
4690 static void
4691 i40e_pf_disable_rss(struct i40e_pf *pf)
4692 {
4693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4694         uint64_t hena;
4695
4696         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4697         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4698         hena &= ~I40E_RSS_HENA_ALL;
4699         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4700         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4701         I40E_WRITE_FLUSH(hw);
4702 }
4703
4704 static int
4705 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4706 {
4707         uint32_t *hash_key;
4708         uint8_t hash_key_len;
4709         uint64_t rss_hf;
4710         uint16_t i;
4711         uint64_t hena;
4712
4713         hash_key = (uint32_t *)(rss_conf->rss_key);
4714         hash_key_len = rss_conf->rss_key_len;
4715         if (hash_key != NULL && hash_key_len >=
4716                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4717                 /* Fill in RSS hash key */
4718                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4719                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4720         }
4721
4722         rss_hf = rss_conf->rss_hf;
4723         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4724         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4725         hena &= ~I40E_RSS_HENA_ALL;
4726         hena |= i40e_config_hena(rss_hf);
4727         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4728         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4729         I40E_WRITE_FLUSH(hw);
4730
4731         return 0;
4732 }
4733
4734 static int
4735 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4736                          struct rte_eth_rss_conf *rss_conf)
4737 {
4738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4740         uint64_t hena;
4741
4742         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4743         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4744         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4745                 if (rss_hf != 0) /* Enable RSS */
4746                         return -EINVAL;
4747                 return 0; /* Nothing to do */
4748         }
4749         /* RSS enabled */
4750         if (rss_hf == 0) /* Disable RSS */
4751                 return -EINVAL;
4752
4753         return i40e_hw_rss_hash_set(hw, rss_conf);
4754 }
4755
4756 static int
4757 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4758                            struct rte_eth_rss_conf *rss_conf)
4759 {
4760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4762         uint64_t hena;
4763         uint16_t i;
4764
4765         if (hash_key != NULL) {
4766                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4767                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4768                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4769         }
4770         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4771         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4772         rss_conf->rss_hf = i40e_parse_hena(hena);
4773
4774         return 0;
4775 }
4776
4777 static int
4778 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4779 {
4780         switch (filter_type) {
4781         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4782                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4783                 break;
4784         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4785                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4786                 break;
4787         case RTE_TUNNEL_FILTER_IMAC_TENID:
4788                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4789                 break;
4790         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4791                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4792                 break;
4793         case ETH_TUNNEL_FILTER_IMAC:
4794                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4795                 break;
4796         default:
4797                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4798                 return -EINVAL;
4799         }
4800
4801         return 0;
4802 }
4803
4804 static int
4805 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4806                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4807                         uint8_t add)
4808 {
4809         uint16_t ip_type;
4810         uint8_t tun_type = 0;
4811         int val, ret = 0;
4812         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4813         struct i40e_vsi *vsi = pf->main_vsi;
4814         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4815         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4816
4817         cld_filter = rte_zmalloc("tunnel_filter",
4818                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4819                 0);
4820
4821         if (NULL == cld_filter) {
4822                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4823                 return -EINVAL;
4824         }
4825         pfilter = cld_filter;
4826
4827         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4828                         sizeof(struct ether_addr));
4829         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4830                         sizeof(struct ether_addr));
4831
4832         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4833         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4834                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4835                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4836                                 &tunnel_filter->ip_addr,
4837                                 sizeof(pfilter->ipaddr.v4.data));
4838         } else {
4839                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4840                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4841                                 &tunnel_filter->ip_addr,
4842                                 sizeof(pfilter->ipaddr.v6.data));
4843         }
4844
4845         /* check tunneled type */
4846         switch (tunnel_filter->tunnel_type) {
4847         case RTE_TUNNEL_TYPE_VXLAN:
4848                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4849                 break;
4850         case RTE_TUNNEL_TYPE_NVGRE:
4851                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4852                 break;
4853         default:
4854                 /* Other tunnel types is not supported. */
4855                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4856                 rte_free(cld_filter);
4857                 return -EINVAL;
4858         }
4859
4860         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4861                                                 &pfilter->flags);
4862         if (val < 0) {
4863                 rte_free(cld_filter);
4864                 return -EINVAL;
4865         }
4866
4867         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4868                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4869         pfilter->tenant_id = tunnel_filter->tenant_id;
4870         pfilter->queue_number = tunnel_filter->queue_id;
4871
4872         if (add)
4873                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4874         else
4875                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4876                                                 cld_filter, 1);
4877
4878         rte_free(cld_filter);
4879         return ret;
4880 }
4881
4882 static int
4883 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4884 {
4885         uint8_t i;
4886
4887         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4888                 if (pf->vxlan_ports[i] == port)
4889                         return i;
4890         }
4891
4892         return -1;
4893 }
4894
4895 static int
4896 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4897 {
4898         int  idx, ret;
4899         uint8_t filter_idx;
4900         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4901
4902         idx = i40e_get_vxlan_port_idx(pf, port);
4903
4904         /* Check if port already exists */
4905         if (idx >= 0) {
4906                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4907                 return -EINVAL;
4908         }
4909
4910         /* Now check if there is space to add the new port */
4911         idx = i40e_get_vxlan_port_idx(pf, 0);
4912         if (idx < 0) {
4913                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4914                         "not adding port %d", port);
4915                 return -ENOSPC;
4916         }
4917
4918         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4919                                         &filter_idx, NULL);
4920         if (ret < 0) {
4921                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4922                 return -1;
4923         }
4924
4925         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4926                          port,  filter_idx);
4927
4928         /* New port: add it and mark its index in the bitmap */
4929         pf->vxlan_ports[idx] = port;
4930         pf->vxlan_bitmap |= (1 << idx);
4931
4932         if (!(pf->flags & I40E_FLAG_VXLAN))
4933                 pf->flags |= I40E_FLAG_VXLAN;
4934
4935         return 0;
4936 }
4937
4938 static int
4939 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4940 {
4941         int idx;
4942         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4943
4944         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4945                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4946                 return -EINVAL;
4947         }
4948
4949         idx = i40e_get_vxlan_port_idx(pf, port);
4950
4951         if (idx < 0) {
4952                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4953                 return -EINVAL;
4954         }
4955
4956         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4957                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4958                 return -1;
4959         }
4960
4961         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4962                         port, idx);
4963
4964         pf->vxlan_ports[idx] = 0;
4965         pf->vxlan_bitmap &= ~(1 << idx);
4966
4967         if (!pf->vxlan_bitmap)
4968                 pf->flags &= ~I40E_FLAG_VXLAN;
4969
4970         return 0;
4971 }
4972
4973 /* Add UDP tunneling port */
4974 static int
4975 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4976                         struct rte_eth_udp_tunnel *udp_tunnel)
4977 {
4978         int ret = 0;
4979         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4980
4981         if (udp_tunnel == NULL)
4982                 return -EINVAL;
4983
4984         switch (udp_tunnel->prot_type) {
4985         case RTE_TUNNEL_TYPE_VXLAN:
4986                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4987                 break;
4988
4989         case RTE_TUNNEL_TYPE_GENEVE:
4990         case RTE_TUNNEL_TYPE_TEREDO:
4991                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4992                 ret = -1;
4993                 break;
4994
4995         default:
4996                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4997                 ret = -1;
4998                 break;
4999         }
5000
5001         return ret;
5002 }
5003
5004 /* Remove UDP tunneling port */
5005 static int
5006 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5007                         struct rte_eth_udp_tunnel *udp_tunnel)
5008 {
5009         int ret = 0;
5010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5011
5012         if (udp_tunnel == NULL)
5013                 return -EINVAL;
5014
5015         switch (udp_tunnel->prot_type) {
5016         case RTE_TUNNEL_TYPE_VXLAN:
5017                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5018                 break;
5019         case RTE_TUNNEL_TYPE_GENEVE:
5020         case RTE_TUNNEL_TYPE_TEREDO:
5021                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5022                 ret = -1;
5023                 break;
5024         default:
5025                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5026                 ret = -1;
5027                 break;
5028         }
5029
5030         return ret;
5031 }
5032
5033 /* Calculate the maximum number of contiguous PF queues that are configured */
5034 static int
5035 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5036 {
5037         struct rte_eth_dev_data *data = pf->dev_data;
5038         int i, num;
5039         struct i40e_rx_queue *rxq;
5040
5041         num = 0;
5042         for (i = 0; i < pf->lan_nb_qps; i++) {
5043                 rxq = data->rx_queues[i];
5044                 if (rxq && rxq->q_set)
5045                         num++;
5046                 else
5047                         break;
5048         }
5049
5050         return num;
5051 }
5052
5053 /* Configure RSS */
5054 static int
5055 i40e_pf_config_rss(struct i40e_pf *pf)
5056 {
5057         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5058         struct rte_eth_rss_conf rss_conf;
5059         uint32_t i, lut = 0;
5060         uint16_t j, num;
5061
5062         /*
5063          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5064          * It's necessary to calulate the actual PF queues that are configured.
5065          */
5066         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5067                 num = i40e_pf_calc_configured_queues_num(pf);
5068                 num = i40e_align_floor(num);
5069         } else
5070                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5071
5072         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5073                         num);
5074
5075         if (num == 0) {
5076                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5077                 return -ENOTSUP;
5078         }
5079
5080         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5081                 if (j == num)
5082                         j = 0;
5083                 lut = (lut << 8) | (j & ((0x1 <<
5084                         hw->func_caps.rss_table_entry_width) - 1));
5085                 if ((i & 3) == 3)
5086                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5087         }
5088
5089         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5090         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5091                 i40e_pf_disable_rss(pf);
5092                 return 0;
5093         }
5094         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5095                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5096                 /* Random default keys */
5097                 static uint32_t rss_key_default[] = {0x6b793944,
5098                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5099                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5100                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5101
5102                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5103                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5104                                                         sizeof(uint32_t);
5105         }
5106
5107         return i40e_hw_rss_hash_set(hw, &rss_conf);
5108 }
5109
5110 static int
5111 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5112                         struct rte_eth_tunnel_filter_conf *filter)
5113 {
5114         if (pf == NULL || filter == NULL) {
5115                 PMD_DRV_LOG(ERR, "Invalid parameter");
5116                 return -EINVAL;
5117         }
5118
5119         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5120                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5121                 return -EINVAL;
5122         }
5123
5124         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5125                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5126                 return -EINVAL;
5127         }
5128
5129         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5130                 (is_zero_ether_addr(filter->outer_mac))) {
5131                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5132                 return -EINVAL;
5133         }
5134
5135         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5136                 (is_zero_ether_addr(filter->inner_mac))) {
5137                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5138                 return -EINVAL;
5139         }
5140
5141         return 0;
5142 }
5143
5144 static int
5145 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5146                         void *arg)
5147 {
5148         struct rte_eth_tunnel_filter_conf *filter;
5149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5150         int ret = I40E_SUCCESS;
5151
5152         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5153
5154         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5155                 return I40E_ERR_PARAM;
5156
5157         switch (filter_op) {
5158         case RTE_ETH_FILTER_NOP:
5159                 if (!(pf->flags & I40E_FLAG_VXLAN))
5160                         ret = I40E_NOT_SUPPORTED;
5161         case RTE_ETH_FILTER_ADD:
5162                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5163                 break;
5164         case RTE_ETH_FILTER_DELETE:
5165                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5166                 break;
5167         default:
5168                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5169                 ret = I40E_ERR_PARAM;
5170                 break;
5171         }
5172
5173         return ret;
5174 }
5175
5176 static int
5177 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5178 {
5179         int ret = 0;
5180         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5181
5182         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5183                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5184                 return -ENOTSUP;
5185         }
5186
5187         /* RSS setup */
5188         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5189                 ret = i40e_pf_config_rss(pf);
5190         else
5191                 i40e_pf_disable_rss(pf);
5192
5193         return ret;
5194 }
5195
5196 /* Get the symmetric hash enable configurations per port */
5197 static void
5198 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5199 {
5200         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5201
5202         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5203 }
5204
5205 /* Set the symmetric hash enable configurations per port */
5206 static void
5207 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5208 {
5209         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5210
5211         if (enable > 0) {
5212                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5213                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5214                                                         "been enabled");
5215                         return;
5216                 }
5217                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5218         } else {
5219                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5220                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5221                                                         "been disabled");
5222                         return;
5223                 }
5224                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5225         }
5226         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5227         I40E_WRITE_FLUSH(hw);
5228 }
5229
5230 /*
5231  * Get global configurations of hash function type and symmetric hash enable
5232  * per flow type (pctype). Note that global configuration means it affects all
5233  * the ports on the same NIC.
5234  */
5235 static int
5236 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5237                                    struct rte_eth_hash_global_conf *g_cfg)
5238 {
5239         uint32_t reg, mask = I40E_FLOW_TYPES;
5240         uint16_t i;
5241         enum i40e_filter_pctype pctype;
5242
5243         memset(g_cfg, 0, sizeof(*g_cfg));
5244         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5245         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5246                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5247         else
5248                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5249         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5250                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5251
5252         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5253                 if (!(mask & (1UL << i)))
5254                         continue;
5255                 mask &= ~(1UL << i);
5256                 /* Bit set indicats the coresponding flow type is supported */
5257                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5258                 pctype = i40e_flowtype_to_pctype(i);
5259                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5260                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5261                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5262         }
5263
5264         return 0;
5265 }
5266
5267 static int
5268 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5269 {
5270         uint32_t i;
5271         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5272
5273         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5274                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5275                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5276                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5277                                                 g_cfg->hash_func);
5278                 return -EINVAL;
5279         }
5280
5281         /*
5282          * As i40e supports less than 32 flow types, only first 32 bits need to
5283          * be checked.
5284          */
5285         mask0 = g_cfg->valid_bit_mask[0];
5286         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5287                 if (i == 0) {
5288                         /* Check if any unsupported flow type configured */
5289                         if ((mask0 | i40e_mask) ^ i40e_mask)
5290                                 goto mask_err;
5291                 } else {
5292                         if (g_cfg->valid_bit_mask[i])
5293                                 goto mask_err;
5294                 }
5295         }
5296
5297         return 0;
5298
5299 mask_err:
5300         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5301
5302         return -EINVAL;
5303 }
5304
5305 /*
5306  * Set global configurations of hash function type and symmetric hash enable
5307  * per flow type (pctype). Note any modifying global configuration will affect
5308  * all the ports on the same NIC.
5309  */
5310 static int
5311 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5312                                    struct rte_eth_hash_global_conf *g_cfg)
5313 {
5314         int ret;
5315         uint16_t i;
5316         uint32_t reg;
5317         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5318         enum i40e_filter_pctype pctype;
5319
5320         /* Check the input parameters */
5321         ret = i40e_hash_global_config_check(g_cfg);
5322         if (ret < 0)
5323                 return ret;
5324
5325         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5326                 if (!(mask0 & (1UL << i)))
5327                         continue;
5328                 mask0 &= ~(1UL << i);
5329                 pctype = i40e_flowtype_to_pctype(i);
5330                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5331                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5332                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5333         }
5334
5335         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5336         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5337                 /* Toeplitz */
5338                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5339                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5340                                                                 "Toeplitz");
5341                         goto out;
5342                 }
5343                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5344         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5345                 /* Simple XOR */
5346                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5347                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5348                                                         "Simple XOR");
5349                         goto out;
5350                 }
5351                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5352         } else
5353                 /* Use the default, and keep it as it is */
5354                 goto out;
5355
5356         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5357
5358 out:
5359         I40E_WRITE_FLUSH(hw);
5360
5361         return 0;
5362 }
5363
5364 static int
5365 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5366 {
5367         int ret = 0;
5368
5369         if (!hw || !info) {
5370                 PMD_DRV_LOG(ERR, "Invalid pointer");
5371                 return -EFAULT;
5372         }
5373
5374         switch (info->info_type) {
5375         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5376                 i40e_get_symmetric_hash_enable_per_port(hw,
5377                                         &(info->info.enable));
5378                 break;
5379         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5380                 ret = i40e_get_hash_filter_global_config(hw,
5381                                 &(info->info.global_conf));
5382                 break;
5383         default:
5384                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5385                                                         info->info_type);
5386                 ret = -EINVAL;
5387                 break;
5388         }
5389
5390         return ret;
5391 }
5392
5393 static int
5394 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5395 {
5396         int ret = 0;
5397
5398         if (!hw || !info) {
5399                 PMD_DRV_LOG(ERR, "Invalid pointer");
5400                 return -EFAULT;
5401         }
5402
5403         switch (info->info_type) {
5404         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5405                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5406                 break;
5407         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5408                 ret = i40e_set_hash_filter_global_config(hw,
5409                                 &(info->info.global_conf));
5410                 break;
5411         default:
5412                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5413                                                         info->info_type);
5414                 ret = -EINVAL;
5415                 break;
5416         }
5417
5418         return ret;
5419 }
5420
5421 /* Operations for hash function */
5422 static int
5423 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5424                       enum rte_filter_op filter_op,
5425                       void *arg)
5426 {
5427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5428         int ret = 0;
5429
5430         switch (filter_op) {
5431         case RTE_ETH_FILTER_NOP:
5432                 break;
5433         case RTE_ETH_FILTER_GET:
5434                 ret = i40e_hash_filter_get(hw,
5435                         (struct rte_eth_hash_filter_info *)arg);
5436                 break;
5437         case RTE_ETH_FILTER_SET:
5438                 ret = i40e_hash_filter_set(hw,
5439                         (struct rte_eth_hash_filter_info *)arg);
5440                 break;
5441         default:
5442                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5443                                                                 filter_op);
5444                 ret = -ENOTSUP;
5445                 break;
5446         }
5447
5448         return ret;
5449 }
5450
5451 /*
5452  * Configure ethertype filter, which can director packet by filtering
5453  * with mac address and ether_type or only ether_type
5454  */
5455 static int
5456 i40e_ethertype_filter_set(struct i40e_pf *pf,
5457                         struct rte_eth_ethertype_filter *filter,
5458                         bool add)
5459 {
5460         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5461         struct i40e_control_filter_stats stats;
5462         uint16_t flags = 0;
5463         int ret;
5464
5465         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5466                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5467                 return -EINVAL;
5468         }
5469         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5470                 filter->ether_type == ETHER_TYPE_IPv6) {
5471                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5472                         " control packet filter.", filter->ether_type);
5473                 return -EINVAL;
5474         }
5475         if (filter->ether_type == ETHER_TYPE_VLAN)
5476                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5477                         " not supported.");
5478
5479         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5480                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5481         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5482                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5483         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5484
5485         memset(&stats, 0, sizeof(stats));
5486         ret = i40e_aq_add_rem_control_packet_filter(hw,
5487                         filter->mac_addr.addr_bytes,
5488                         filter->ether_type, flags,
5489                         pf->main_vsi->seid,
5490                         filter->queue, add, &stats, NULL);
5491
5492         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5493                          " mac_etype_used = %u, etype_used = %u,"
5494                          " mac_etype_free = %u, etype_free = %u\n",
5495                          ret, stats.mac_etype_used, stats.etype_used,
5496                          stats.mac_etype_free, stats.etype_free);
5497         if (ret < 0)
5498                 return -ENOSYS;
5499         return 0;
5500 }
5501
5502 /*
5503  * Handle operations for ethertype filter.
5504  */
5505 static int
5506 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5507                                 enum rte_filter_op filter_op,
5508                                 void *arg)
5509 {
5510         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5511         int ret = 0;
5512
5513         if (filter_op == RTE_ETH_FILTER_NOP)
5514                 return ret;
5515
5516         if (arg == NULL) {
5517                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5518                             filter_op);
5519                 return -EINVAL;
5520         }
5521
5522         switch (filter_op) {
5523         case RTE_ETH_FILTER_ADD:
5524                 ret = i40e_ethertype_filter_set(pf,
5525                         (struct rte_eth_ethertype_filter *)arg,
5526                         TRUE);
5527                 break;
5528         case RTE_ETH_FILTER_DELETE:
5529                 ret = i40e_ethertype_filter_set(pf,
5530                         (struct rte_eth_ethertype_filter *)arg,
5531                         FALSE);
5532                 break;
5533         default:
5534                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5535                 ret = -ENOSYS;
5536                 break;
5537         }
5538         return ret;
5539 }
5540
5541 static int
5542 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5543                      enum rte_filter_type filter_type,
5544                      enum rte_filter_op filter_op,
5545                      void *arg)
5546 {
5547         int ret = 0;
5548
5549         if (dev == NULL)
5550                 return -EINVAL;
5551
5552         switch (filter_type) {
5553         case RTE_ETH_FILTER_HASH:
5554                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5555                 break;
5556         case RTE_ETH_FILTER_MACVLAN:
5557                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5558                 break;
5559         case RTE_ETH_FILTER_ETHERTYPE:
5560                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5561                 break;
5562         case RTE_ETH_FILTER_TUNNEL:
5563                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5564                 break;
5565         case RTE_ETH_FILTER_FDIR:
5566                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5567                 break;
5568         default:
5569                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5570                                                         filter_type);
5571                 ret = -EINVAL;
5572                 break;
5573         }
5574
5575         return ret;
5576 }
5577
5578 /*
5579  * As some registers wouldn't be reset unless a global hardware reset,
5580  * hardware initialization is needed to put those registers into an
5581  * expected initial state.
5582  */
5583 static void
5584 i40e_hw_init(struct i40e_hw *hw)
5585 {
5586         /* clear the PF Queue Filter control register */
5587         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5588
5589         /* Disable symmetric hash per port */
5590         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5591 }
5592
5593 enum i40e_filter_pctype
5594 i40e_flowtype_to_pctype(uint16_t flow_type)
5595 {
5596         static const enum i40e_filter_pctype pctype_table[] = {
5597                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5598                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5599                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5600                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5601                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5602                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5603                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5604                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5605                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5606                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5607                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5608                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5609                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5610                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5611                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5612                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5613                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5614                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5615                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5616         };
5617
5618         return pctype_table[flow_type];
5619 }
5620
5621 uint16_t
5622 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5623 {
5624         static const uint16_t flowtype_table[] = {
5625                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5626                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5627                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5628                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5629                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5630                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5631                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5632                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5633                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5634                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5635                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5636                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5637                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5638                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5639                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5640                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5641                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5642                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5643                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5644         };
5645
5646         return flowtype_table[pctype];
5647 }
5648
5649 static int
5650 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5651 {
5652         struct i40e_aq_desc desc;
5653         enum i40e_status_code status;
5654
5655         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5656         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5657         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5658         if (status < 0)
5659                 return status;
5660
5661         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5662                                         (CHAR_BIT * sizeof(uint32_t))) +
5663                                 rte_le_to_cpu_32(desc.params.internal.param3);
5664
5665         return status;
5666 }
5667
5668 /*
5669  * On X710, performance number is far from the expectation on recent firmware
5670  * versions; on XL710, performance number is also far from the expectation on
5671  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5672  * mode is enabled and port MAC address is equal to the packet destination MAC
5673  * address. The fix for this issue may not be integrated in the following
5674  * firmware version. So the workaround in software driver is needed. It needs
5675  * to modify the initial values of 3 internal only registers for both X710 and
5676  * XL710. Note that the values for X710 or XL710 could be different, and the
5677  * workaround can be removed when it is fixed in firmware in the future.
5678  */
5679
5680 /* For both X710 and XL710 */
5681 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5682 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5683
5684 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5685 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5686
5687 /* For X710 */
5688 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5689 /* For XL710 */
5690 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5691 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5692
5693 static void
5694 i40e_configure_registers(struct i40e_hw *hw)
5695 {
5696         static struct {
5697                 uint32_t addr;
5698                 uint64_t val;
5699         } reg_table[] = {
5700                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5701                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5702                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5703         };
5704         uint64_t reg;
5705         uint32_t i;
5706         int ret;
5707
5708         for (i = 0; i < RTE_DIM(reg_table); i++) {
5709                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5710                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5711                                 reg_table[i].val =
5712                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5713                         else /* For X710 */
5714                                 reg_table[i].val =
5715                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5716                 }
5717
5718                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5719                 if (ret < 0) {
5720                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5721                                                         reg_table[i].addr);
5722                         break;
5723                 }
5724                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5725                                                 reg_table[i].addr, reg);
5726                 if (reg == reg_table[i].val)
5727                         continue;
5728
5729                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5730                                                 reg_table[i].val, NULL);
5731                 if (ret < 0) {
5732                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5733                                 "address of 0x%"PRIx32, reg_table[i].val,
5734                                                         reg_table[i].addr);
5735                         break;
5736                 }
5737                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5738                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5739         }
5740 }