4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 #define I40E_DEFAULT_RX_FREE_THRESH 32
63 #define I40E_DEFAULT_RX_PTHRESH 8
64 #define I40E_DEFAULT_RX_HTHRESH 8
65 #define I40E_DEFAULT_RX_WTHRESH 0
67 #define I40E_DEFAULT_TX_FREE_THRESH 32
68 #define I40E_DEFAULT_TX_PTHRESH 32
69 #define I40E_DEFAULT_TX_HTHRESH 0
70 #define I40E_DEFAULT_TX_WTHRESH 0
71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
73 /* Maximun number of MAC addresses */
74 #define I40E_NUM_MACADDR_MAX 64
75 #define I40E_CLEAR_PXE_WAIT_MS 200
77 /* Maximun number of capability elements */
78 #define I40E_MAX_CAP_ELE_NUM 128
80 /* Wait count and inteval */
81 #define I40E_CHK_Q_ENA_COUNT 1000
82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
84 /* Maximun number of VSI */
85 #define I40E_MAX_NUM_VSIS (384UL)
87 /* Bit shift and mask */
88 #define I40E_16_BIT_SHIFT 16
89 #define I40E_16_BIT_MASK 0xFFFF
90 #define I40E_32_BIT_SHIFT 32
91 #define I40E_32_BIT_MASK 0xFFFFFFFF
92 #define I40E_48_BIT_SHIFT 48
93 #define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL
95 /* Default queue interrupt throttling time in microseconds*/
96 #define I40E_ITR_INDEX_DEFAULT 0
97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
98 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
100 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
102 /* Mask of PF interrupt causes */
103 #define I40E_PFINT_ICR0_ENA_MASK ( \
104 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
105 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
106 I40E_PFINT_ICR0_ENA_GRST_MASK | \
107 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
108 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
109 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
110 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
112 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
113 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
115 static int eth_i40e_dev_init(\
116 __attribute__((unused)) struct eth_driver *eth_drv,
117 struct rte_eth_dev *eth_dev);
118 static int i40e_dev_configure(struct rte_eth_dev *dev);
119 static int i40e_dev_start(struct rte_eth_dev *dev);
120 static void i40e_dev_stop(struct rte_eth_dev *dev);
121 static void i40e_dev_close(struct rte_eth_dev *dev);
122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
129 struct rte_eth_stats *stats);
130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
149 struct rte_eth_fc_conf *fc_conf);
150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
151 struct rte_eth_pfc_conf *pfc_conf);
152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
153 struct ether_addr *mac_addr,
156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
158 struct rte_eth_rss_reta *reta_conf);
159 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
160 struct rte_eth_rss_reta *reta_conf);
162 static int i40e_get_cap(struct i40e_hw *hw);
163 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
164 static int i40e_pf_setup(struct i40e_pf *pf);
165 static int i40e_vsi_init(struct i40e_vsi *vsi);
166 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
167 bool offset_loaded, uint64_t *offset, uint64_t *stat);
168 static void i40e_stat_update_48(struct i40e_hw *hw,
174 static void i40e_pf_config_irq0(struct i40e_hw *hw);
175 static void i40e_dev_interrupt_handler(
176 __rte_unused struct rte_intr_handle *handle, void *param);
177 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
178 uint32_t base, uint32_t num);
179 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
180 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
182 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
184 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
185 static int i40e_veb_release(struct i40e_veb *veb);
186 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
187 struct i40e_vsi *vsi);
188 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
189 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
190 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
191 struct i40e_macvlan_filter *mv_f,
193 struct ether_addr *addr);
194 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
195 struct i40e_macvlan_filter *mv_f,
198 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
199 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
200 struct rte_eth_rss_conf *rss_conf);
201 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
202 struct rte_eth_rss_conf *rss_conf);
203 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
204 struct rte_eth_udp_tunnel *udp_tunnel);
205 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
206 struct rte_eth_udp_tunnel *udp_tunnel);
207 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
208 enum rte_filter_type filter_type,
209 enum rte_filter_op filter_op,
212 /* Default hash key buffer for RSS */
213 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
215 static struct rte_pci_id pci_id_i40e_map[] = {
216 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
217 #include "rte_pci_dev_ids.h"
218 { .vendor_id = 0, /* sentinel */ },
221 static struct eth_dev_ops i40e_eth_dev_ops = {
222 .dev_configure = i40e_dev_configure,
223 .dev_start = i40e_dev_start,
224 .dev_stop = i40e_dev_stop,
225 .dev_close = i40e_dev_close,
226 .promiscuous_enable = i40e_dev_promiscuous_enable,
227 .promiscuous_disable = i40e_dev_promiscuous_disable,
228 .allmulticast_enable = i40e_dev_allmulticast_enable,
229 .allmulticast_disable = i40e_dev_allmulticast_disable,
230 .dev_set_link_up = i40e_dev_set_link_up,
231 .dev_set_link_down = i40e_dev_set_link_down,
232 .link_update = i40e_dev_link_update,
233 .stats_get = i40e_dev_stats_get,
234 .stats_reset = i40e_dev_stats_reset,
235 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
236 .dev_infos_get = i40e_dev_info_get,
237 .vlan_filter_set = i40e_vlan_filter_set,
238 .vlan_tpid_set = i40e_vlan_tpid_set,
239 .vlan_offload_set = i40e_vlan_offload_set,
240 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
241 .vlan_pvid_set = i40e_vlan_pvid_set,
242 .rx_queue_start = i40e_dev_rx_queue_start,
243 .rx_queue_stop = i40e_dev_rx_queue_stop,
244 .tx_queue_start = i40e_dev_tx_queue_start,
245 .tx_queue_stop = i40e_dev_tx_queue_stop,
246 .rx_queue_setup = i40e_dev_rx_queue_setup,
247 .rx_queue_release = i40e_dev_rx_queue_release,
248 .rx_queue_count = i40e_dev_rx_queue_count,
249 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
250 .tx_queue_setup = i40e_dev_tx_queue_setup,
251 .tx_queue_release = i40e_dev_tx_queue_release,
252 .dev_led_on = i40e_dev_led_on,
253 .dev_led_off = i40e_dev_led_off,
254 .flow_ctrl_set = i40e_flow_ctrl_set,
255 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
256 .mac_addr_add = i40e_macaddr_add,
257 .mac_addr_remove = i40e_macaddr_remove,
258 .reta_update = i40e_dev_rss_reta_update,
259 .reta_query = i40e_dev_rss_reta_query,
260 .rss_hash_update = i40e_dev_rss_hash_update,
261 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
262 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
263 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
264 .filter_ctrl = i40e_dev_filter_ctrl,
267 static struct eth_driver rte_i40e_pmd = {
269 .name = "rte_i40e_pmd",
270 .id_table = pci_id_i40e_map,
271 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
273 .eth_dev_init = eth_i40e_dev_init,
274 .dev_private_size = sizeof(struct i40e_adapter),
278 i40e_prev_power_of_2(int n)
296 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
297 struct rte_eth_link *link)
299 struct rte_eth_link *dst = link;
300 struct rte_eth_link *src = &(dev->data->dev_link);
302 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
303 *(uint64_t *)src) == 0)
310 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
311 struct rte_eth_link *link)
313 struct rte_eth_link *dst = &(dev->data->dev_link);
314 struct rte_eth_link *src = link;
316 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
317 *(uint64_t *)src) == 0)
324 * Driver initialization routine.
325 * Invoked once at EAL init time.
326 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
329 rte_i40e_pmd_init(const char *name __rte_unused,
330 const char *params __rte_unused)
332 PMD_INIT_FUNC_TRACE();
333 rte_eth_driver_register(&rte_i40e_pmd);
338 static struct rte_driver rte_i40e_driver = {
340 .init = rte_i40e_pmd_init,
343 PMD_REGISTER_DRIVER(rte_i40e_driver);
346 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
347 struct rte_eth_dev *dev)
349 struct rte_pci_device *pci_dev;
350 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
351 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
352 struct i40e_vsi *vsi;
357 PMD_INIT_FUNC_TRACE();
359 dev->dev_ops = &i40e_eth_dev_ops;
360 dev->rx_pkt_burst = i40e_recv_pkts;
361 dev->tx_pkt_burst = i40e_xmit_pkts;
363 /* for secondary processes, we don't initialise any further as primary
364 * has already done this work. Only check we don't need a different
366 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
367 if (dev->data->scattered_rx)
368 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
371 pci_dev = dev->pci_dev;
372 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
373 pf->adapter->eth_dev = dev;
374 pf->dev_data = dev->data;
376 hw->back = I40E_PF_TO_ADAPTER(pf);
377 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
379 PMD_INIT_LOG(ERR, "Hardware is not available, "
380 "as address is NULL");
384 hw->vendor_id = pci_dev->id.vendor_id;
385 hw->device_id = pci_dev->id.device_id;
386 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
387 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
388 hw->bus.device = pci_dev->addr.devid;
389 hw->bus.func = pci_dev->addr.function;
391 /* Make sure all is clean before doing PF reset */
394 /* Reset here to make sure all is clean for each PF */
395 ret = i40e_pf_reset(hw);
397 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
401 /* Initialize the shared code (base driver) */
402 ret = i40e_init_shared_code(hw);
404 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
408 /* Initialize the parameters for adminq */
409 i40e_init_adminq_parameter(hw);
410 ret = i40e_init_adminq(hw);
411 if (ret != I40E_SUCCESS) {
412 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
415 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
416 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
417 hw->aq.api_maj_ver, hw->aq.api_min_ver,
418 ((hw->nvm.version >> 12) & 0xf),
419 ((hw->nvm.version >> 4) & 0xff),
420 (hw->nvm.version & 0xf), hw->nvm.eetrack);
423 ret = i40e_aq_stop_lldp(hw, true, NULL);
424 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
425 PMD_INIT_LOG(INFO, "Failed to stop lldp");
428 i40e_clear_pxe_mode(hw);
430 /* Get hw capabilities */
431 ret = i40e_get_cap(hw);
432 if (ret != I40E_SUCCESS) {
433 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
434 goto err_get_capabilities;
437 /* Initialize parameters for PF */
438 ret = i40e_pf_parameter_init(dev);
440 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
441 goto err_parameter_init;
444 /* Initialize the queue management */
445 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
447 PMD_INIT_LOG(ERR, "Failed to init queue pool");
448 goto err_qp_pool_init;
450 ret = i40e_res_pool_init(&pf->msix_pool, 1,
451 hw->func_caps.num_msix_vectors - 1);
453 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
454 goto err_msix_pool_init;
457 /* Initialize lan hmc */
458 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
459 hw->func_caps.num_rx_qp, 0, 0);
460 if (ret != I40E_SUCCESS) {
461 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
462 goto err_init_lan_hmc;
465 /* Configure lan hmc */
466 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
467 if (ret != I40E_SUCCESS) {
468 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
469 goto err_configure_lan_hmc;
472 /* Get and check the mac address */
473 i40e_get_mac_addr(hw, hw->mac.addr);
474 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
475 PMD_INIT_LOG(ERR, "mac address is not valid");
477 goto err_get_mac_addr;
479 /* Copy the permanent MAC address */
480 ether_addr_copy((struct ether_addr *) hw->mac.addr,
481 (struct ether_addr *) hw->mac.perm_addr);
483 /* Disable flow control */
484 hw->fc.requested_mode = I40E_FC_NONE;
485 i40e_set_fc(hw, &aq_fail, TRUE);
487 /* PF setup, which includes VSI setup */
488 ret = i40e_pf_setup(pf);
490 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
491 goto err_setup_pf_switch;
496 /* Disable double vlan by default */
497 i40e_vsi_config_double_vlan(vsi, FALSE);
499 if (!vsi->max_macaddrs)
500 len = ETHER_ADDR_LEN;
502 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
504 /* Should be after VSI initialized */
505 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
506 if (!dev->data->mac_addrs) {
507 PMD_INIT_LOG(ERR, "Failed to allocated memory "
508 "for storing mac address");
509 goto err_get_mac_addr;
511 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
512 &dev->data->mac_addrs[0]);
514 /* initialize pf host driver to setup SRIOV resource if applicable */
515 i40e_pf_host_init(dev);
517 /* register callback func to eal lib */
518 rte_intr_callback_register(&(pci_dev->intr_handle),
519 i40e_dev_interrupt_handler, (void *)dev);
521 /* configure and enable device interrupt */
522 i40e_pf_config_irq0(hw);
523 i40e_pf_enable_irq0(hw);
525 /* enable uio intr after callback register */
526 rte_intr_enable(&(pci_dev->intr_handle));
531 rte_free(pf->main_vsi);
533 err_configure_lan_hmc:
534 (void)i40e_shutdown_lan_hmc(hw);
536 i40e_res_pool_destroy(&pf->msix_pool);
538 i40e_res_pool_destroy(&pf->qp_pool);
541 err_get_capabilities:
542 (void)i40e_shutdown_adminq(hw);
548 i40e_dev_configure(struct rte_eth_dev *dev)
550 return i40e_dev_init_vlan(dev);
554 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
556 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
557 uint16_t msix_vect = vsi->msix_intr;
560 for (i = 0; i < vsi->nb_qps; i++) {
561 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
562 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
566 if (vsi->type != I40E_VSI_SRIOV) {
567 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
568 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
572 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
573 vsi->user_param + (msix_vect - 1);
575 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
577 I40E_WRITE_FLUSH(hw);
580 static inline uint16_t
581 i40e_calc_itr_interval(int16_t interval)
583 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
584 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
586 /* Convert to hardware count, as writing each 1 represents 2 us */
591 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
594 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
595 uint16_t msix_vect = vsi->msix_intr;
598 for (i = 0; i < vsi->nb_qps; i++)
599 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
601 /* Bind all RX queues to allocated MSIX interrupt */
602 for (i = 0; i < vsi->nb_qps; i++) {
603 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
604 I40E_QINT_RQCTL_ITR_INDX_MASK |
605 ((vsi->base_queue + i + 1) <<
606 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
607 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
608 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
610 if (i == vsi->nb_qps - 1)
611 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
612 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
615 /* Write first RX queue to Link list register as the head element */
616 if (vsi->type != I40E_VSI_SRIOV) {
618 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
620 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
622 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
623 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
625 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
626 msix_vect - 1), interval);
628 #ifndef I40E_GLINT_CTL
629 #define I40E_GLINT_CTL 0x0003F800
630 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
632 /* Disable auto-mask on enabling of all none-zero interrupt */
633 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
634 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
638 /* num_msix_vectors_vf needs to minus irq0 */
639 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
640 vsi->user_param + (msix_vect - 1);
642 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
643 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
644 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
647 I40E_WRITE_FLUSH(hw);
651 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
653 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
654 uint16_t interval = i40e_calc_itr_interval(\
655 RTE_LIBRTE_I40E_ITR_INTERVAL);
657 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
658 I40E_PFINT_DYN_CTLN_INTENA_MASK |
659 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
660 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
661 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
665 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
667 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
669 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
672 static inline uint8_t
673 i40e_parse_link_speed(uint16_t eth_link_speed)
675 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
677 switch (eth_link_speed) {
678 case ETH_LINK_SPEED_40G:
679 link_speed = I40E_LINK_SPEED_40GB;
681 case ETH_LINK_SPEED_20G:
682 link_speed = I40E_LINK_SPEED_20GB;
684 case ETH_LINK_SPEED_10G:
685 link_speed = I40E_LINK_SPEED_10GB;
687 case ETH_LINK_SPEED_1000:
688 link_speed = I40E_LINK_SPEED_1GB;
690 case ETH_LINK_SPEED_100:
691 link_speed = I40E_LINK_SPEED_100MB;
699 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
701 enum i40e_status_code status;
702 struct i40e_aq_get_phy_abilities_resp phy_ab;
703 struct i40e_aq_set_phy_config phy_conf;
704 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
705 I40E_AQ_PHY_FLAG_PAUSE_RX |
706 I40E_AQ_PHY_FLAG_LOW_POWER;
707 const uint8_t advt = I40E_LINK_SPEED_40GB |
708 I40E_LINK_SPEED_10GB |
709 I40E_LINK_SPEED_1GB |
710 I40E_LINK_SPEED_100MB;
713 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
718 memset(&phy_conf, 0, sizeof(phy_conf));
720 /* bits 0-2 use the values from get_phy_abilities_resp */
722 abilities |= phy_ab.abilities & mask;
724 /* update ablities and speed */
725 if (abilities & I40E_AQ_PHY_AN_ENABLED)
726 phy_conf.link_speed = advt;
728 phy_conf.link_speed = force_speed;
730 phy_conf.abilities = abilities;
732 /* use get_phy_abilities_resp value for the rest */
733 phy_conf.phy_type = phy_ab.phy_type;
734 phy_conf.eee_capability = phy_ab.eee_capability;
735 phy_conf.eeer = phy_ab.eeer_val;
736 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
738 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
739 phy_ab.abilities, phy_ab.link_speed);
740 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
741 phy_conf.abilities, phy_conf.link_speed);
743 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
751 i40e_apply_link_speed(struct rte_eth_dev *dev)
754 uint8_t abilities = 0;
755 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
756 struct rte_eth_conf *conf = &dev->data->dev_conf;
758 speed = i40e_parse_link_speed(conf->link_speed);
759 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
760 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
761 abilities |= I40E_AQ_PHY_AN_ENABLED;
763 abilities |= I40E_AQ_PHY_LINK_ENABLED;
765 return i40e_phy_conf_link(hw, abilities, speed);
769 i40e_dev_start(struct rte_eth_dev *dev)
771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
773 struct i40e_vsi *vsi = pf->main_vsi;
776 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
777 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
778 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
779 dev->data->dev_conf.link_duplex,
785 ret = i40e_vsi_init(vsi);
786 if (ret != I40E_SUCCESS) {
787 PMD_DRV_LOG(ERR, "Failed to init VSI");
791 /* Map queues with MSIX interrupt */
792 i40e_vsi_queues_bind_intr(vsi);
793 i40e_vsi_enable_queues_intr(vsi);
795 /* Enable all queues which have been configured */
796 ret = i40e_vsi_switch_queues(vsi, TRUE);
797 if (ret != I40E_SUCCESS) {
798 PMD_DRV_LOG(ERR, "Failed to enable VSI");
802 /* Enable receiving broadcast packets */
803 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
804 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
805 if (ret != I40E_SUCCESS)
806 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
809 /* Apply link configure */
810 ret = i40e_apply_link_speed(dev);
811 if (I40E_SUCCESS != ret) {
812 PMD_DRV_LOG(ERR, "Fail to apply link setting");
819 i40e_vsi_switch_queues(vsi, FALSE);
825 i40e_dev_stop(struct rte_eth_dev *dev)
827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
828 struct i40e_vsi *vsi = pf->main_vsi;
830 /* Disable all queues */
831 i40e_vsi_switch_queues(vsi, FALSE);
834 i40e_dev_set_link_down(dev);
836 /* un-map queues with interrupt registers */
837 i40e_vsi_disable_queues_intr(vsi);
838 i40e_vsi_queues_unbind_intr(vsi);
842 i40e_dev_close(struct rte_eth_dev *dev)
844 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
848 PMD_INIT_FUNC_TRACE();
852 /* Disable interrupt */
853 i40e_pf_disable_irq0(hw);
854 rte_intr_disable(&(dev->pci_dev->intr_handle));
856 /* shutdown and destroy the HMC */
857 i40e_shutdown_lan_hmc(hw);
859 /* release all the existing VSIs and VEBs */
860 i40e_vsi_release(pf->main_vsi);
862 /* shutdown the adminq */
863 i40e_aq_queue_shutdown(hw, true);
864 i40e_shutdown_adminq(hw);
866 i40e_res_pool_destroy(&pf->qp_pool);
867 i40e_res_pool_destroy(&pf->msix_pool);
869 /* force a PF reset to clean anything leftover */
870 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
871 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
872 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
873 I40E_WRITE_FLUSH(hw);
877 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
879 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
881 struct i40e_vsi *vsi = pf->main_vsi;
884 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
886 if (status != I40E_SUCCESS)
887 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
889 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
891 if (status != I40E_SUCCESS)
892 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
897 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
899 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
900 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
901 struct i40e_vsi *vsi = pf->main_vsi;
904 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
906 if (status != I40E_SUCCESS)
907 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
909 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
911 if (status != I40E_SUCCESS)
912 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
916 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
919 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
920 struct i40e_vsi *vsi = pf->main_vsi;
923 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
924 if (ret != I40E_SUCCESS)
925 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
929 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
931 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
932 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
933 struct i40e_vsi *vsi = pf->main_vsi;
936 if (dev->data->promiscuous == 1)
937 return; /* must remain in all_multicast mode */
939 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
940 vsi->seid, FALSE, NULL);
941 if (ret != I40E_SUCCESS)
942 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
946 * Set device link up.
949 i40e_dev_set_link_up(struct rte_eth_dev *dev)
951 /* re-apply link speed setting */
952 return i40e_apply_link_speed(dev);
956 * Set device link down.
959 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
961 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
962 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
965 return i40e_phy_conf_link(hw, abilities, speed);
969 i40e_dev_link_update(struct rte_eth_dev *dev,
970 __rte_unused int wait_to_complete)
972 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 struct i40e_link_status link_status;
974 struct rte_eth_link link, old;
977 memset(&link, 0, sizeof(link));
978 memset(&old, 0, sizeof(old));
979 memset(&link_status, 0, sizeof(link_status));
980 rte_i40e_dev_atomic_read_link_status(dev, &old);
982 /* Get link status information from hardware */
983 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
984 if (status != I40E_SUCCESS) {
985 link.link_speed = ETH_LINK_SPEED_100;
986 link.link_duplex = ETH_LINK_FULL_DUPLEX;
987 PMD_DRV_LOG(ERR, "Failed to get link info");
991 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
993 if (!link.link_status)
996 /* i40e uses full duplex only */
997 link.link_duplex = ETH_LINK_FULL_DUPLEX;
999 /* Parse the link status */
1000 switch (link_status.link_speed) {
1001 case I40E_LINK_SPEED_100MB:
1002 link.link_speed = ETH_LINK_SPEED_100;
1004 case I40E_LINK_SPEED_1GB:
1005 link.link_speed = ETH_LINK_SPEED_1000;
1007 case I40E_LINK_SPEED_10GB:
1008 link.link_speed = ETH_LINK_SPEED_10G;
1010 case I40E_LINK_SPEED_20GB:
1011 link.link_speed = ETH_LINK_SPEED_20G;
1013 case I40E_LINK_SPEED_40GB:
1014 link.link_speed = ETH_LINK_SPEED_40G;
1017 link.link_speed = ETH_LINK_SPEED_100;
1022 rte_i40e_dev_atomic_write_link_status(dev, &link);
1023 if (link.link_status == old.link_status)
1029 /* Get all the statistics of a VSI */
1031 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1033 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1034 struct i40e_eth_stats *nes = &vsi->eth_stats;
1035 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1036 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1038 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1039 vsi->offset_loaded, &oes->rx_bytes,
1041 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1042 vsi->offset_loaded, &oes->rx_unicast,
1044 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1045 vsi->offset_loaded, &oes->rx_multicast,
1046 &nes->rx_multicast);
1047 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1048 vsi->offset_loaded, &oes->rx_broadcast,
1049 &nes->rx_broadcast);
1050 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1051 &oes->rx_discards, &nes->rx_discards);
1052 /* GLV_REPC not supported */
1053 /* GLV_RMPC not supported */
1054 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1055 &oes->rx_unknown_protocol,
1056 &nes->rx_unknown_protocol);
1057 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1058 vsi->offset_loaded, &oes->tx_bytes,
1060 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1061 vsi->offset_loaded, &oes->tx_unicast,
1063 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1064 vsi->offset_loaded, &oes->tx_multicast,
1065 &nes->tx_multicast);
1066 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1067 vsi->offset_loaded, &oes->tx_broadcast,
1068 &nes->tx_broadcast);
1069 /* GLV_TDPC not supported */
1070 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1071 &oes->tx_errors, &nes->tx_errors);
1072 vsi->offset_loaded = true;
1074 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1076 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1077 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1078 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1079 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1080 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1081 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1082 nes->rx_unknown_protocol);
1083 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1084 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1085 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1086 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1087 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1088 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1089 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1093 /* Get all statistics of a port */
1095 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1101 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1103 /* Get statistics of struct i40e_eth_stats */
1104 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1105 I40E_GLPRT_GORCL(hw->port),
1106 pf->offset_loaded, &os->eth.rx_bytes,
1108 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1109 I40E_GLPRT_UPRCL(hw->port),
1110 pf->offset_loaded, &os->eth.rx_unicast,
1111 &ns->eth.rx_unicast);
1112 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1113 I40E_GLPRT_MPRCL(hw->port),
1114 pf->offset_loaded, &os->eth.rx_multicast,
1115 &ns->eth.rx_multicast);
1116 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1117 I40E_GLPRT_BPRCL(hw->port),
1118 pf->offset_loaded, &os->eth.rx_broadcast,
1119 &ns->eth.rx_broadcast);
1120 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1121 pf->offset_loaded, &os->eth.rx_discards,
1122 &ns->eth.rx_discards);
1123 /* GLPRT_REPC not supported */
1124 /* GLPRT_RMPC not supported */
1125 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1127 &os->eth.rx_unknown_protocol,
1128 &ns->eth.rx_unknown_protocol);
1129 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1130 I40E_GLPRT_GOTCL(hw->port),
1131 pf->offset_loaded, &os->eth.tx_bytes,
1133 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1134 I40E_GLPRT_UPTCL(hw->port),
1135 pf->offset_loaded, &os->eth.tx_unicast,
1136 &ns->eth.tx_unicast);
1137 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1138 I40E_GLPRT_MPTCL(hw->port),
1139 pf->offset_loaded, &os->eth.tx_multicast,
1140 &ns->eth.tx_multicast);
1141 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1142 I40E_GLPRT_BPTCL(hw->port),
1143 pf->offset_loaded, &os->eth.tx_broadcast,
1144 &ns->eth.tx_broadcast);
1145 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1146 pf->offset_loaded, &os->eth.tx_discards,
1147 &ns->eth.tx_discards);
1148 /* GLPRT_TEPC not supported */
1150 /* additional port specific stats */
1151 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1152 pf->offset_loaded, &os->tx_dropped_link_down,
1153 &ns->tx_dropped_link_down);
1154 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1155 pf->offset_loaded, &os->crc_errors,
1157 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1158 pf->offset_loaded, &os->illegal_bytes,
1159 &ns->illegal_bytes);
1160 /* GLPRT_ERRBC not supported */
1161 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1162 pf->offset_loaded, &os->mac_local_faults,
1163 &ns->mac_local_faults);
1164 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1165 pf->offset_loaded, &os->mac_remote_faults,
1166 &ns->mac_remote_faults);
1167 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1168 pf->offset_loaded, &os->rx_length_errors,
1169 &ns->rx_length_errors);
1170 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1171 pf->offset_loaded, &os->link_xon_rx,
1173 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1174 pf->offset_loaded, &os->link_xoff_rx,
1176 for (i = 0; i < 8; i++) {
1177 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1179 &os->priority_xon_rx[i],
1180 &ns->priority_xon_rx[i]);
1181 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1183 &os->priority_xoff_rx[i],
1184 &ns->priority_xoff_rx[i]);
1186 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1187 pf->offset_loaded, &os->link_xon_tx,
1189 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1190 pf->offset_loaded, &os->link_xoff_tx,
1192 for (i = 0; i < 8; i++) {
1193 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1195 &os->priority_xon_tx[i],
1196 &ns->priority_xon_tx[i]);
1197 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1199 &os->priority_xoff_tx[i],
1200 &ns->priority_xoff_tx[i]);
1201 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1203 &os->priority_xon_2_xoff[i],
1204 &ns->priority_xon_2_xoff[i]);
1206 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1207 I40E_GLPRT_PRC64L(hw->port),
1208 pf->offset_loaded, &os->rx_size_64,
1210 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1211 I40E_GLPRT_PRC127L(hw->port),
1212 pf->offset_loaded, &os->rx_size_127,
1214 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1215 I40E_GLPRT_PRC255L(hw->port),
1216 pf->offset_loaded, &os->rx_size_255,
1218 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1219 I40E_GLPRT_PRC511L(hw->port),
1220 pf->offset_loaded, &os->rx_size_511,
1222 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1223 I40E_GLPRT_PRC1023L(hw->port),
1224 pf->offset_loaded, &os->rx_size_1023,
1226 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1227 I40E_GLPRT_PRC1522L(hw->port),
1228 pf->offset_loaded, &os->rx_size_1522,
1230 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1231 I40E_GLPRT_PRC9522L(hw->port),
1232 pf->offset_loaded, &os->rx_size_big,
1234 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1235 pf->offset_loaded, &os->rx_undersize,
1237 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1238 pf->offset_loaded, &os->rx_fragments,
1240 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1241 pf->offset_loaded, &os->rx_oversize,
1243 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1244 pf->offset_loaded, &os->rx_jabber,
1246 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1247 I40E_GLPRT_PTC64L(hw->port),
1248 pf->offset_loaded, &os->tx_size_64,
1250 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1251 I40E_GLPRT_PTC127L(hw->port),
1252 pf->offset_loaded, &os->tx_size_127,
1254 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1255 I40E_GLPRT_PTC255L(hw->port),
1256 pf->offset_loaded, &os->tx_size_255,
1258 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1259 I40E_GLPRT_PTC511L(hw->port),
1260 pf->offset_loaded, &os->tx_size_511,
1262 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1263 I40E_GLPRT_PTC1023L(hw->port),
1264 pf->offset_loaded, &os->tx_size_1023,
1266 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1267 I40E_GLPRT_PTC1522L(hw->port),
1268 pf->offset_loaded, &os->tx_size_1522,
1270 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1271 I40E_GLPRT_PTC9522L(hw->port),
1272 pf->offset_loaded, &os->tx_size_big,
1274 /* GLPRT_MSPDC not supported */
1275 /* GLPRT_XEC not supported */
1277 pf->offset_loaded = true;
1280 i40e_update_vsi_stats(pf->main_vsi);
1282 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1283 ns->eth.rx_broadcast;
1284 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1285 ns->eth.tx_broadcast;
1286 stats->ibytes = ns->eth.rx_bytes;
1287 stats->obytes = ns->eth.tx_bytes;
1288 stats->oerrors = ns->eth.tx_errors;
1289 stats->imcasts = ns->eth.rx_multicast;
1292 stats->ibadcrc = ns->crc_errors;
1293 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1294 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1295 stats->imissed = ns->eth.rx_discards;
1296 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1298 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1299 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1300 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1301 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1302 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1303 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1304 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1305 ns->eth.rx_unknown_protocol);
1306 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1307 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1308 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1309 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1310 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1311 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1313 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1314 ns->tx_dropped_link_down);
1315 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1316 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1318 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1319 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1320 ns->mac_local_faults);
1321 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1322 ns->mac_remote_faults);
1323 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1324 ns->rx_length_errors);
1325 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1326 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1327 for (i = 0; i < 8; i++) {
1328 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1329 i, ns->priority_xon_rx[i]);
1330 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1331 i, ns->priority_xoff_rx[i]);
1333 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1334 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1335 for (i = 0; i < 8; i++) {
1336 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1337 i, ns->priority_xon_tx[i]);
1338 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1339 i, ns->priority_xoff_tx[i]);
1340 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1341 i, ns->priority_xon_2_xoff[i]);
1343 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1344 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1345 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1346 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1347 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1348 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1349 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1350 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1351 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1352 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1353 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1354 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1355 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1356 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1357 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1358 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1359 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1360 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1361 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1362 ns->mac_short_packet_dropped);
1363 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1364 ns->checksum_error);
1365 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1368 /* Reset the statistics */
1370 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1372 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1374 /* It results in reloading the start point of each counter */
1375 pf->offset_loaded = false;
1379 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1380 __rte_unused uint16_t queue_id,
1381 __rte_unused uint8_t stat_idx,
1382 __rte_unused uint8_t is_rx)
1384 PMD_INIT_FUNC_TRACE();
1390 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1392 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1393 struct i40e_vsi *vsi = pf->main_vsi;
1395 dev_info->max_rx_queues = vsi->nb_qps;
1396 dev_info->max_tx_queues = vsi->nb_qps;
1397 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1398 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1399 dev_info->max_mac_addrs = vsi->max_macaddrs;
1400 dev_info->max_vfs = dev->pci_dev->max_vfs;
1401 dev_info->rx_offload_capa =
1402 DEV_RX_OFFLOAD_VLAN_STRIP |
1403 DEV_RX_OFFLOAD_IPV4_CKSUM |
1404 DEV_RX_OFFLOAD_UDP_CKSUM |
1405 DEV_RX_OFFLOAD_TCP_CKSUM;
1406 dev_info->tx_offload_capa =
1407 DEV_TX_OFFLOAD_VLAN_INSERT |
1408 DEV_TX_OFFLOAD_IPV4_CKSUM |
1409 DEV_TX_OFFLOAD_UDP_CKSUM |
1410 DEV_TX_OFFLOAD_TCP_CKSUM |
1411 DEV_TX_OFFLOAD_SCTP_CKSUM;
1413 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1415 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1416 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1417 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1419 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1423 dev_info->default_txconf = (struct rte_eth_txconf) {
1425 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1426 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1427 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1429 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1430 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1431 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1437 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440 struct i40e_vsi *vsi = pf->main_vsi;
1441 PMD_INIT_FUNC_TRACE();
1444 return i40e_vsi_add_vlan(vsi, vlan_id);
1446 return i40e_vsi_delete_vlan(vsi, vlan_id);
1450 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1451 __rte_unused uint16_t tpid)
1453 PMD_INIT_FUNC_TRACE();
1457 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1459 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1460 struct i40e_vsi *vsi = pf->main_vsi;
1462 if (mask & ETH_VLAN_STRIP_MASK) {
1463 /* Enable or disable VLAN stripping */
1464 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1465 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1467 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1470 if (mask & ETH_VLAN_EXTEND_MASK) {
1471 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1472 i40e_vsi_config_double_vlan(vsi, TRUE);
1474 i40e_vsi_config_double_vlan(vsi, FALSE);
1479 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1480 __rte_unused uint16_t queue,
1481 __rte_unused int on)
1483 PMD_INIT_FUNC_TRACE();
1487 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1490 struct i40e_vsi *vsi = pf->main_vsi;
1491 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1492 struct i40e_vsi_vlan_pvid_info info;
1494 memset(&info, 0, sizeof(info));
1497 info.config.pvid = pvid;
1499 info.config.reject.tagged =
1500 data->dev_conf.txmode.hw_vlan_reject_tagged;
1501 info.config.reject.untagged =
1502 data->dev_conf.txmode.hw_vlan_reject_untagged;
1505 return i40e_vsi_vlan_pvid_set(vsi, &info);
1509 i40e_dev_led_on(struct rte_eth_dev *dev)
1511 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512 uint32_t mode = i40e_led_get(hw);
1515 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1521 i40e_dev_led_off(struct rte_eth_dev *dev)
1523 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 uint32_t mode = i40e_led_get(hw);
1527 i40e_led_set(hw, 0, false);
1533 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1534 __rte_unused struct rte_eth_fc_conf *fc_conf)
1536 PMD_INIT_FUNC_TRACE();
1542 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1543 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1545 PMD_INIT_FUNC_TRACE();
1550 /* Add a MAC address, and update filters */
1552 i40e_macaddr_add(struct rte_eth_dev *dev,
1553 struct ether_addr *mac_addr,
1554 __attribute__((unused)) uint32_t index,
1555 __attribute__((unused)) uint32_t pool)
1557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559 struct i40e_mac_filter_info mac_filter;
1560 struct i40e_vsi *vsi = pf->main_vsi;
1561 struct ether_addr old_mac;
1564 if (!is_valid_assigned_ether_addr(mac_addr)) {
1565 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1569 if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1570 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1574 /* Write mac address */
1575 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1576 mac_addr->addr_bytes, NULL);
1577 if (ret != I40E_SUCCESS) {
1578 PMD_DRV_LOG(ERR, "Failed to write mac address");
1582 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1583 (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1585 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1586 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1588 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1589 if (ret != I40E_SUCCESS) {
1590 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1594 ether_addr_copy(mac_addr, &pf->dev_addr);
1595 i40e_vsi_delete_mac(vsi, &old_mac);
1598 /* Remove a MAC address, and update filters */
1600 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1602 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1603 struct i40e_vsi *vsi = pf->main_vsi;
1604 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1605 struct ether_addr *macaddr;
1607 struct i40e_hw *hw =
1608 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610 if (index >= vsi->max_macaddrs)
1613 macaddr = &(data->mac_addrs[index]);
1614 if (!is_valid_assigned_ether_addr(macaddr))
1617 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1618 hw->mac.perm_addr, NULL);
1619 if (ret != I40E_SUCCESS) {
1620 PMD_DRV_LOG(ERR, "Failed to write mac address");
1624 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1626 ret = i40e_vsi_delete_mac(vsi, macaddr);
1627 if (ret != I40E_SUCCESS)
1630 /* Clear device address as it has been removed */
1631 if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1632 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1635 /* Set perfect match or hash match of MAC and VLAN for a VF */
1637 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1638 struct rte_eth_mac_filter *filter,
1642 struct i40e_mac_filter_info mac_filter;
1643 struct ether_addr old_mac;
1644 struct ether_addr *new_mac;
1645 struct i40e_pf_vf *vf = NULL;
1650 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1653 hw = I40E_PF_TO_HW(pf);
1655 if (filter == NULL) {
1656 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1660 new_mac = &filter->mac_addr;
1662 if (is_zero_ether_addr(new_mac)) {
1663 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1667 vf_id = filter->dst_id;
1669 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1670 PMD_DRV_LOG(ERR, "Invalid argument.");
1673 vf = &pf->vfs[vf_id];
1675 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1676 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1681 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1682 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1684 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1687 mac_filter.filter_type = filter->filter_type;
1688 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1689 if (ret != I40E_SUCCESS) {
1690 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1693 ether_addr_copy(new_mac, &pf->dev_addr);
1695 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1697 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1698 if (ret != I40E_SUCCESS) {
1699 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1703 /* Clear device address as it has been removed */
1704 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1705 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1711 /* MAC filter handle */
1713 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1716 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1717 struct rte_eth_mac_filter *filter;
1718 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1719 int ret = I40E_NOT_SUPPORTED;
1721 filter = (struct rte_eth_mac_filter *)(arg);
1723 switch (filter_op) {
1724 case RTE_ETH_FILTER_NONE:
1727 case RTE_ETH_FILTER_ADD:
1728 i40e_pf_disable_irq0(hw);
1730 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1731 i40e_pf_enable_irq0(hw);
1733 case RTE_ETH_FILTER_DELETE:
1734 i40e_pf_disable_irq0(hw);
1736 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1737 i40e_pf_enable_irq0(hw);
1740 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1741 ret = I40E_ERR_PARAM;
1749 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1750 struct rte_eth_rss_reta *reta_conf)
1752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1756 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1758 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1760 mask = (uint8_t)((reta_conf->mask_hi >>
1769 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1771 for (j = 0, lut = 0; j < 4; j++) {
1772 if (mask & (0x1 << j))
1773 lut |= reta_conf->reta[i + j] << (8 * j);
1775 lut |= l & (0xFF << (8 * j));
1777 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1784 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1785 struct rte_eth_rss_reta *reta_conf)
1787 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1791 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1793 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1795 mask = (uint8_t)((reta_conf->mask_hi >>
1801 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1802 for (j = 0; j < 4; j++) {
1803 if (mask & (0x1 << j))
1804 reta_conf->reta[i + j] =
1805 (uint8_t)((lut >> (8 * j)) & 0xFF);
1813 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1814 * @hw: pointer to the HW structure
1815 * @mem: pointer to mem struct to fill out
1816 * @size: size of memory requested
1817 * @alignment: what to align the allocation to
1819 enum i40e_status_code
1820 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1821 struct i40e_dma_mem *mem,
1825 static uint64_t id = 0;
1826 const struct rte_memzone *mz = NULL;
1827 char z_name[RTE_MEMZONE_NAMESIZE];
1830 return I40E_ERR_PARAM;
1833 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1834 #ifdef RTE_LIBRTE_XEN_DOM0
1835 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1838 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1841 return I40E_ERR_NO_MEMORY;
1846 #ifdef RTE_LIBRTE_XEN_DOM0
1847 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1849 mem->pa = mz->phys_addr;
1852 return I40E_SUCCESS;
1856 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1857 * @hw: pointer to the HW structure
1858 * @mem: ptr to mem struct to free
1860 enum i40e_status_code
1861 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1862 struct i40e_dma_mem *mem)
1864 if (!mem || !mem->va)
1865 return I40E_ERR_PARAM;
1870 return I40E_SUCCESS;
1874 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1875 * @hw: pointer to the HW structure
1876 * @mem: pointer to mem struct to fill out
1877 * @size: size of memory requested
1879 enum i40e_status_code
1880 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1881 struct i40e_virt_mem *mem,
1885 return I40E_ERR_PARAM;
1888 mem->va = rte_zmalloc("i40e", size, 0);
1891 return I40E_SUCCESS;
1893 return I40E_ERR_NO_MEMORY;
1897 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1898 * @hw: pointer to the HW structure
1899 * @mem: pointer to mem struct to free
1901 enum i40e_status_code
1902 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1903 struct i40e_virt_mem *mem)
1906 return I40E_ERR_PARAM;
1911 return I40E_SUCCESS;
1915 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1917 rte_spinlock_init(&sp->spinlock);
1921 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1923 rte_spinlock_lock(&sp->spinlock);
1927 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1929 rte_spinlock_unlock(&sp->spinlock);
1933 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1939 * Get the hardware capabilities, which will be parsed
1940 * and saved into struct i40e_hw.
1943 i40e_get_cap(struct i40e_hw *hw)
1945 struct i40e_aqc_list_capabilities_element_resp *buf;
1946 uint16_t len, size = 0;
1949 /* Calculate a huge enough buff for saving response data temporarily */
1950 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1951 I40E_MAX_CAP_ELE_NUM;
1952 buf = rte_zmalloc("i40e", len, 0);
1954 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1955 return I40E_ERR_NO_MEMORY;
1958 /* Get, parse the capabilities and save it to hw */
1959 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1960 i40e_aqc_opc_list_func_capabilities, NULL);
1961 if (ret != I40E_SUCCESS)
1962 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1964 /* Free the temporary buffer after being used */
1971 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1973 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1974 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1975 uint16_t sum_queues = 0, sum_vsis;
1977 /* First check if FW support SRIOV */
1978 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1979 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1983 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1984 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1985 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1986 /* Allocate queues for pf */
1987 if (hw->func_caps.rss) {
1988 pf->flags |= I40E_FLAG_RSS;
1989 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1990 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1991 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1994 sum_queues = pf->lan_nb_qps;
1995 /* Default VSI is not counted in */
1997 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1999 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2000 pf->flags |= I40E_FLAG_SRIOV;
2001 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2002 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2003 PMD_INIT_LOG(ERR, "Config VF number %u, "
2004 "max supported %u.",
2005 dev->pci_dev->max_vfs,
2006 hw->func_caps.num_vfs);
2009 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2010 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2011 "max support %u queues.",
2012 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2015 pf->vf_num = dev->pci_dev->max_vfs;
2016 sum_queues += pf->vf_nb_qps * pf->vf_num;
2017 sum_vsis += pf->vf_num;
2018 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2019 pf->vf_num, pf->vf_nb_qps);
2023 if (hw->func_caps.vmdq) {
2024 pf->flags |= I40E_FLAG_VMDQ;
2025 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
2026 sum_queues += pf->vmdq_nb_qps;
2028 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2031 if (hw->func_caps.fd) {
2032 pf->flags |= I40E_FLAG_FDIR;
2033 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2035 * Each flow director consumes one VSI and one queue,
2036 * but can't calculate out predictably here.
2040 if (sum_vsis > pf->max_num_vsi ||
2041 sum_queues > hw->func_caps.num_rx_qp) {
2042 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2043 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2044 pf->max_num_vsi, sum_vsis);
2045 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2046 hw->func_caps.num_rx_qp, sum_queues);
2050 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2052 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2053 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2054 sum_vsis, hw->func_caps.num_msix_vectors);
2057 return I40E_SUCCESS;
2061 i40e_pf_get_switch_config(struct i40e_pf *pf)
2063 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2064 struct i40e_aqc_get_switch_config_resp *switch_config;
2065 struct i40e_aqc_switch_config_element_resp *element;
2066 uint16_t start_seid = 0, num_reported;
2069 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2070 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2071 if (!switch_config) {
2072 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2076 /* Get the switch configurations */
2077 ret = i40e_aq_get_switch_config(hw, switch_config,
2078 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2079 if (ret != I40E_SUCCESS) {
2080 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2083 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2084 if (num_reported != 1) { /* The number should be 1 */
2085 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2089 /* Parse the switch configuration elements */
2090 element = &(switch_config->element[0]);
2091 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2092 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2093 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2095 PMD_DRV_LOG(INFO, "Unknown element type");
2098 rte_free(switch_config);
2104 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2107 struct pool_entry *entry;
2109 if (pool == NULL || num == 0)
2112 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2113 if (entry == NULL) {
2114 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2118 /* queue heap initialize */
2119 pool->num_free = num;
2120 pool->num_alloc = 0;
2122 LIST_INIT(&pool->alloc_list);
2123 LIST_INIT(&pool->free_list);
2125 /* Initialize element */
2129 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2134 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2136 struct pool_entry *entry;
2141 LIST_FOREACH(entry, &pool->alloc_list, next) {
2142 LIST_REMOVE(entry, next);
2146 LIST_FOREACH(entry, &pool->free_list, next) {
2147 LIST_REMOVE(entry, next);
2152 pool->num_alloc = 0;
2154 LIST_INIT(&pool->alloc_list);
2155 LIST_INIT(&pool->free_list);
2159 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2162 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2163 uint32_t pool_offset;
2167 PMD_DRV_LOG(ERR, "Invalid parameter");
2171 pool_offset = base - pool->base;
2172 /* Lookup in alloc list */
2173 LIST_FOREACH(entry, &pool->alloc_list, next) {
2174 if (entry->base == pool_offset) {
2175 valid_entry = entry;
2176 LIST_REMOVE(entry, next);
2181 /* Not find, return */
2182 if (valid_entry == NULL) {
2183 PMD_DRV_LOG(ERR, "Failed to find entry");
2188 * Found it, move it to free list and try to merge.
2189 * In order to make merge easier, always sort it by qbase.
2190 * Find adjacent prev and last entries.
2193 LIST_FOREACH(entry, &pool->free_list, next) {
2194 if (entry->base > valid_entry->base) {
2202 /* Try to merge with next one*/
2204 /* Merge with next one */
2205 if (valid_entry->base + valid_entry->len == next->base) {
2206 next->base = valid_entry->base;
2207 next->len += valid_entry->len;
2208 rte_free(valid_entry);
2215 /* Merge with previous one */
2216 if (prev->base + prev->len == valid_entry->base) {
2217 prev->len += valid_entry->len;
2218 /* If it merge with next one, remove next node */
2220 LIST_REMOVE(valid_entry, next);
2221 rte_free(valid_entry);
2223 rte_free(valid_entry);
2229 /* Not find any entry to merge, insert */
2232 LIST_INSERT_AFTER(prev, valid_entry, next);
2233 else if (next != NULL)
2234 LIST_INSERT_BEFORE(next, valid_entry, next);
2235 else /* It's empty list, insert to head */
2236 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2239 pool->num_free += valid_entry->len;
2240 pool->num_alloc -= valid_entry->len;
2246 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2249 struct pool_entry *entry, *valid_entry;
2251 if (pool == NULL || num == 0) {
2252 PMD_DRV_LOG(ERR, "Invalid parameter");
2256 if (pool->num_free < num) {
2257 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2258 num, pool->num_free);
2263 /* Lookup in free list and find most fit one */
2264 LIST_FOREACH(entry, &pool->free_list, next) {
2265 if (entry->len >= num) {
2267 if (entry->len == num) {
2268 valid_entry = entry;
2271 if (valid_entry == NULL || valid_entry->len > entry->len)
2272 valid_entry = entry;
2276 /* Not find one to satisfy the request, return */
2277 if (valid_entry == NULL) {
2278 PMD_DRV_LOG(ERR, "No valid entry found");
2282 * The entry have equal queue number as requested,
2283 * remove it from alloc_list.
2285 if (valid_entry->len == num) {
2286 LIST_REMOVE(valid_entry, next);
2289 * The entry have more numbers than requested,
2290 * create a new entry for alloc_list and minus its
2291 * queue base and number in free_list.
2293 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2294 if (entry == NULL) {
2295 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2299 entry->base = valid_entry->base;
2301 valid_entry->base += num;
2302 valid_entry->len -= num;
2303 valid_entry = entry;
2306 /* Insert it into alloc list, not sorted */
2307 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2309 pool->num_free -= valid_entry->len;
2310 pool->num_alloc += valid_entry->len;
2312 return (valid_entry->base + pool->base);
2316 * bitmap_is_subset - Check whether src2 is subset of src1
2319 bitmap_is_subset(uint8_t src1, uint8_t src2)
2321 return !((src1 ^ src2) & src2);
2325 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2327 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2329 /* If DCB is not supported, only default TC is supported */
2330 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2331 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2335 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2336 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2337 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2341 return I40E_SUCCESS;
2345 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2346 struct i40e_vsi_vlan_pvid_info *info)
2349 struct i40e_vsi_context ctxt;
2350 uint8_t vlan_flags = 0;
2353 if (vsi == NULL || info == NULL) {
2354 PMD_DRV_LOG(ERR, "invalid parameters");
2355 return I40E_ERR_PARAM;
2359 vsi->info.pvid = info->config.pvid;
2361 * If insert pvid is enabled, only tagged pkts are
2362 * allowed to be sent out.
2364 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2365 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2368 if (info->config.reject.tagged == 0)
2369 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2371 if (info->config.reject.untagged == 0)
2372 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2374 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2375 I40E_AQ_VSI_PVLAN_MODE_MASK);
2376 vsi->info.port_vlan_flags |= vlan_flags;
2377 vsi->info.valid_sections =
2378 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2379 memset(&ctxt, 0, sizeof(ctxt));
2380 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2381 ctxt.seid = vsi->seid;
2383 hw = I40E_VSI_TO_HW(vsi);
2384 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2385 if (ret != I40E_SUCCESS)
2386 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2392 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2394 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2396 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2398 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2399 if (ret != I40E_SUCCESS)
2403 PMD_DRV_LOG(ERR, "seid not valid");
2407 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2408 tc_bw_data.tc_valid_bits = enabled_tcmap;
2409 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2410 tc_bw_data.tc_bw_credits[i] =
2411 (enabled_tcmap & (1 << i)) ? 1 : 0;
2413 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2414 if (ret != I40E_SUCCESS) {
2415 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2419 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2420 sizeof(vsi->info.qs_handle));
2421 return I40E_SUCCESS;
2425 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2426 struct i40e_aqc_vsi_properties_data *info,
2427 uint8_t enabled_tcmap)
2429 int ret, total_tc = 0, i;
2430 uint16_t qpnum_per_tc, bsf, qp_idx;
2432 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2433 if (ret != I40E_SUCCESS)
2436 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2437 if (enabled_tcmap & (1 << i))
2439 vsi->enabled_tc = enabled_tcmap;
2441 /* Number of queues per enabled TC */
2442 qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2443 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2444 bsf = rte_bsf32(qpnum_per_tc);
2446 /* Adjust the queue number to actual queues that can be applied */
2447 vsi->nb_qps = qpnum_per_tc * total_tc;
2450 * Configure TC and queue mapping parameters, for enabled TC,
2451 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2452 * default queue will serve it.
2455 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2456 if (vsi->enabled_tc & (1 << i)) {
2457 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2458 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2459 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2460 qp_idx += qpnum_per_tc;
2462 info->tc_mapping[i] = 0;
2465 /* Associate queue number with VSI */
2466 if (vsi->type == I40E_VSI_SRIOV) {
2467 info->mapping_flags |=
2468 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2469 for (i = 0; i < vsi->nb_qps; i++)
2470 info->queue_mapping[i] =
2471 rte_cpu_to_le_16(vsi->base_queue + i);
2473 info->mapping_flags |=
2474 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2475 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2477 info->valid_sections =
2478 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2480 return I40E_SUCCESS;
2484 i40e_veb_release(struct i40e_veb *veb)
2486 struct i40e_vsi *vsi;
2489 if (veb == NULL || veb->associate_vsi == NULL)
2492 if (!TAILQ_EMPTY(&veb->head)) {
2493 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2497 vsi = veb->associate_vsi;
2498 hw = I40E_VSI_TO_HW(vsi);
2500 vsi->uplink_seid = veb->uplink_seid;
2501 i40e_aq_delete_element(hw, veb->seid, NULL);
2504 return I40E_SUCCESS;
2508 static struct i40e_veb *
2509 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2511 struct i40e_veb *veb;
2515 if (NULL == pf || vsi == NULL) {
2516 PMD_DRV_LOG(ERR, "veb setup failed, "
2517 "associated VSI shouldn't null");
2520 hw = I40E_PF_TO_HW(pf);
2522 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2524 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2528 veb->associate_vsi = vsi;
2529 TAILQ_INIT(&veb->head);
2530 veb->uplink_seid = vsi->uplink_seid;
2532 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2533 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2535 if (ret != I40E_SUCCESS) {
2536 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2537 hw->aq.asq_last_status);
2541 /* get statistics index */
2542 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2543 &veb->stats_idx, NULL, NULL, NULL);
2544 if (ret != I40E_SUCCESS) {
2545 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2546 hw->aq.asq_last_status);
2550 /* Get VEB bandwidth, to be implemented */
2551 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2552 vsi->uplink_seid = veb->seid;
2561 i40e_vsi_release(struct i40e_vsi *vsi)
2565 struct i40e_vsi_list *vsi_list;
2567 struct i40e_mac_filter *f;
2570 return I40E_SUCCESS;
2572 pf = I40E_VSI_TO_PF(vsi);
2573 hw = I40E_VSI_TO_HW(vsi);
2575 /* VSI has child to attach, release child first */
2577 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2578 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2580 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2582 i40e_veb_release(vsi->veb);
2585 /* Remove all macvlan filters of the VSI */
2586 i40e_vsi_remove_all_macvlan_filter(vsi);
2587 TAILQ_FOREACH(f, &vsi->mac_list, next)
2590 if (vsi->type != I40E_VSI_MAIN) {
2591 /* Remove vsi from parent's sibling list */
2592 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2593 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2594 return I40E_ERR_PARAM;
2596 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2597 &vsi->sib_vsi_list, list);
2599 /* Remove all switch element of the VSI */
2600 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2601 if (ret != I40E_SUCCESS)
2602 PMD_DRV_LOG(ERR, "Failed to delete element");
2604 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2606 if (vsi->type != I40E_VSI_SRIOV)
2607 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2610 return I40E_SUCCESS;
2614 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2616 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2617 struct i40e_aqc_remove_macvlan_element_data def_filter;
2618 struct i40e_mac_filter_info filter;
2621 if (vsi->type != I40E_VSI_MAIN)
2622 return I40E_ERR_CONFIG;
2623 memset(&def_filter, 0, sizeof(def_filter));
2624 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2626 def_filter.vlan_tag = 0;
2627 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2628 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2629 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2630 if (ret != I40E_SUCCESS) {
2631 struct i40e_mac_filter *f;
2632 struct ether_addr *mac;
2634 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2636 /* It needs to add the permanent mac into mac list */
2637 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2639 PMD_DRV_LOG(ERR, "failed to allocate memory");
2640 return I40E_ERR_NO_MEMORY;
2642 mac = &f->mac_info.mac_addr;
2643 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2645 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2646 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2651 (void)rte_memcpy(&filter.mac_addr,
2652 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2653 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2654 return i40e_vsi_add_mac(vsi, &filter);
2658 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2660 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2661 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2662 struct i40e_hw *hw = &vsi->adapter->hw;
2666 memset(&bw_config, 0, sizeof(bw_config));
2667 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2668 if (ret != I40E_SUCCESS) {
2669 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2670 hw->aq.asq_last_status);
2674 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2675 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2676 &ets_sla_config, NULL);
2677 if (ret != I40E_SUCCESS) {
2678 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2679 "configuration %u", hw->aq.asq_last_status);
2683 /* Not store the info yet, just print out */
2684 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2685 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2686 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2687 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2688 ets_sla_config.share_credits[i]);
2689 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2690 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2691 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2692 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2701 i40e_vsi_setup(struct i40e_pf *pf,
2702 enum i40e_vsi_type type,
2703 struct i40e_vsi *uplink_vsi,
2704 uint16_t user_param)
2706 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2707 struct i40e_vsi *vsi;
2708 struct i40e_mac_filter_info filter;
2710 struct i40e_vsi_context ctxt;
2711 struct ether_addr broadcast =
2712 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2714 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2715 PMD_DRV_LOG(ERR, "VSI setup failed, "
2716 "VSI link shouldn't be NULL");
2720 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2721 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2722 "uplink VSI should be NULL");
2726 /* If uplink vsi didn't setup VEB, create one first */
2727 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2728 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2730 if (NULL == uplink_vsi->veb) {
2731 PMD_DRV_LOG(ERR, "VEB setup failed");
2736 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2738 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2741 TAILQ_INIT(&vsi->mac_list);
2743 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2744 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2745 vsi->parent_vsi = uplink_vsi;
2746 vsi->user_param = user_param;
2747 /* Allocate queues */
2748 switch (vsi->type) {
2749 case I40E_VSI_MAIN :
2750 vsi->nb_qps = pf->lan_nb_qps;
2752 case I40E_VSI_SRIOV :
2753 vsi->nb_qps = pf->vf_nb_qps;
2758 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2760 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2764 vsi->base_queue = ret;
2766 /* VF has MSIX interrupt in VF range, don't allocate here */
2767 if (type != I40E_VSI_SRIOV) {
2768 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2770 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2771 goto fail_queue_alloc;
2773 vsi->msix_intr = ret;
2777 if (type == I40E_VSI_MAIN) {
2778 /* For main VSI, no need to add since it's default one */
2779 vsi->uplink_seid = pf->mac_seid;
2780 vsi->seid = pf->main_vsi_seid;
2781 /* Bind queues with specific MSIX interrupt */
2783 * Needs 2 interrupt at least, one for misc cause which will
2784 * enabled from OS side, Another for queues binding the
2785 * interrupt from device side only.
2788 /* Get default VSI parameters from hardware */
2789 memset(&ctxt, 0, sizeof(ctxt));
2790 ctxt.seid = vsi->seid;
2791 ctxt.pf_num = hw->pf_id;
2792 ctxt.uplink_seid = vsi->uplink_seid;
2794 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2795 if (ret != I40E_SUCCESS) {
2796 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2797 goto fail_msix_alloc;
2799 (void)rte_memcpy(&vsi->info, &ctxt.info,
2800 sizeof(struct i40e_aqc_vsi_properties_data));
2801 vsi->vsi_id = ctxt.vsi_number;
2802 vsi->info.valid_sections = 0;
2804 /* Configure tc, enabled TC0 only */
2805 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2807 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2808 goto fail_msix_alloc;
2811 /* TC, queue mapping */
2812 memset(&ctxt, 0, sizeof(ctxt));
2813 vsi->info.valid_sections |=
2814 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2815 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2816 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2817 (void)rte_memcpy(&ctxt.info, &vsi->info,
2818 sizeof(struct i40e_aqc_vsi_properties_data));
2819 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2820 I40E_DEFAULT_TCMAP);
2821 if (ret != I40E_SUCCESS) {
2822 PMD_DRV_LOG(ERR, "Failed to configure "
2823 "TC queue mapping");
2824 goto fail_msix_alloc;
2826 ctxt.seid = vsi->seid;
2827 ctxt.pf_num = hw->pf_id;
2828 ctxt.uplink_seid = vsi->uplink_seid;
2831 /* Update VSI parameters */
2832 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2833 if (ret != I40E_SUCCESS) {
2834 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2835 goto fail_msix_alloc;
2838 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2839 sizeof(vsi->info.tc_mapping));
2840 (void)rte_memcpy(&vsi->info.queue_mapping,
2841 &ctxt.info.queue_mapping,
2842 sizeof(vsi->info.queue_mapping));
2843 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2844 vsi->info.valid_sections = 0;
2846 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2850 * Updating default filter settings are necessary to prevent
2851 * reception of tagged packets.
2852 * Some old firmware configurations load a default macvlan
2853 * filter which accepts both tagged and untagged packets.
2854 * The updating is to use a normal filter instead if needed.
2855 * For NVM 4.2.2 or after, the updating is not needed anymore.
2856 * The firmware with correct configurations load the default
2857 * macvlan filter which is expected and cannot be removed.
2859 i40e_update_default_filter_setting(vsi);
2860 } else if (type == I40E_VSI_SRIOV) {
2861 memset(&ctxt, 0, sizeof(ctxt));
2863 * For other VSI, the uplink_seid equals to uplink VSI's
2864 * uplink_seid since they share same VEB
2866 vsi->uplink_seid = uplink_vsi->uplink_seid;
2867 ctxt.pf_num = hw->pf_id;
2868 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2869 ctxt.uplink_seid = vsi->uplink_seid;
2870 ctxt.connection_type = 0x1;
2871 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2873 /* Configure switch ID */
2874 ctxt.info.valid_sections |=
2875 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2876 ctxt.info.switch_id =
2877 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2878 /* Configure port/vlan */
2879 ctxt.info.valid_sections |=
2880 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2881 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2882 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2883 I40E_DEFAULT_TCMAP);
2884 if (ret != I40E_SUCCESS) {
2885 PMD_DRV_LOG(ERR, "Failed to configure "
2886 "TC queue mapping");
2887 goto fail_msix_alloc;
2889 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2890 ctxt.info.valid_sections |=
2891 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2893 * Since VSI is not created yet, only configure parameter,
2894 * will add vsi below.
2898 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2899 goto fail_msix_alloc;
2902 if (vsi->type != I40E_VSI_MAIN) {
2903 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2905 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2906 hw->aq.asq_last_status);
2907 goto fail_msix_alloc;
2909 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2910 vsi->info.valid_sections = 0;
2911 vsi->seid = ctxt.seid;
2912 vsi->vsi_id = ctxt.vsi_number;
2913 vsi->sib_vsi_list.vsi = vsi;
2914 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2915 &vsi->sib_vsi_list, list);
2918 /* MAC/VLAN configuration */
2919 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
2920 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2922 ret = i40e_vsi_add_mac(vsi, &filter);
2923 if (ret != I40E_SUCCESS) {
2924 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2925 goto fail_msix_alloc;
2928 /* Get VSI BW information */
2929 i40e_vsi_dump_bw_config(vsi);
2932 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2934 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2940 /* Configure vlan stripping on or off */
2942 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2944 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2945 struct i40e_vsi_context ctxt;
2947 int ret = I40E_SUCCESS;
2949 /* Check if it has been already on or off */
2950 if (vsi->info.valid_sections &
2951 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2953 if ((vsi->info.port_vlan_flags &
2954 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2955 return 0; /* already on */
2957 if ((vsi->info.port_vlan_flags &
2958 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2959 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2960 return 0; /* already off */
2965 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2967 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2968 vsi->info.valid_sections =
2969 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2970 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2971 vsi->info.port_vlan_flags |= vlan_flags;
2972 ctxt.seid = vsi->seid;
2973 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2974 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2976 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2977 on ? "enable" : "disable");
2983 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2985 struct rte_eth_dev_data *data = dev->data;
2988 /* Apply vlan offload setting */
2989 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2991 /* Apply double-vlan setting, not implemented yet */
2993 /* Apply pvid setting */
2994 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2995 data->dev_conf.txmode.hw_vlan_insert_pvid);
2997 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3003 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3005 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3007 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3011 i40e_update_flow_control(struct i40e_hw *hw)
3013 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3014 struct i40e_link_status link_status;
3015 uint32_t rxfc = 0, txfc = 0, reg;
3019 memset(&link_status, 0, sizeof(link_status));
3020 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3021 if (ret != I40E_SUCCESS) {
3022 PMD_DRV_LOG(ERR, "Failed to get link status information");
3023 goto write_reg; /* Disable flow control */
3026 an_info = hw->phy.link_info.an_info;
3027 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3028 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3029 ret = I40E_ERR_NOT_READY;
3030 goto write_reg; /* Disable flow control */
3033 * If link auto negotiation is enabled, flow control needs to
3034 * be configured according to it
3036 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3037 case I40E_LINK_PAUSE_RXTX:
3040 hw->fc.current_mode = I40E_FC_FULL;
3042 case I40E_AQ_LINK_PAUSE_RX:
3044 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3046 case I40E_AQ_LINK_PAUSE_TX:
3048 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3051 hw->fc.current_mode = I40E_FC_NONE;
3056 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3057 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3058 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3059 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3060 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3061 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3068 i40e_pf_setup(struct i40e_pf *pf)
3070 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3071 struct i40e_filter_control_settings settings;
3072 struct rte_eth_dev_data *dev_data = pf->dev_data;
3073 struct i40e_vsi *vsi;
3076 /* Clear all stats counters */
3077 pf->offset_loaded = FALSE;
3078 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3079 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3081 ret = i40e_pf_get_switch_config(pf);
3082 if (ret != I40E_SUCCESS) {
3083 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3088 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3090 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3091 return I40E_ERR_NOT_READY;
3094 dev_data->nb_rx_queues = vsi->nb_qps;
3095 dev_data->nb_tx_queues = vsi->nb_qps;
3097 /* Configure filter control */
3098 memset(&settings, 0, sizeof(settings));
3099 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3100 /* Enable ethtype and macvlan filters */
3101 settings.enable_ethtype = TRUE;
3102 settings.enable_macvlan = TRUE;
3103 ret = i40e_set_filter_control(hw, &settings);
3105 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3108 /* Update flow control according to the auto negotiation */
3109 i40e_update_flow_control(hw);
3111 return I40E_SUCCESS;
3115 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3121 * Set or clear TX Queue Disable flags,
3122 * which is required by hardware.
3124 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3125 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3127 /* Wait until the request is finished */
3128 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3129 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3130 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3131 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3132 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3138 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3139 return I40E_SUCCESS; /* already on, skip next steps */
3141 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3142 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3144 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3145 return I40E_SUCCESS; /* already off, skip next steps */
3146 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3148 /* Write the register */
3149 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3150 /* Check the result */
3151 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3152 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3153 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3155 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3156 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3159 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3160 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3164 /* Check if it is timeout */
3165 if (j >= I40E_CHK_Q_ENA_COUNT) {
3166 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3167 (on ? "enable" : "disable"), q_idx);
3168 return I40E_ERR_TIMEOUT;
3171 return I40E_SUCCESS;
3174 /* Swith on or off the tx queues */
3176 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3178 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3179 struct i40e_tx_queue *txq;
3180 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3184 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3185 txq = dev_data->tx_queues[i];
3186 /* Don't operate the queue if not configured or
3187 * if starting only per queue */
3188 if (!txq->q_set || (on && txq->tx_deferred_start))
3191 ret = i40e_dev_tx_queue_start(dev, i);
3193 ret = i40e_dev_tx_queue_stop(dev, i);
3194 if ( ret != I40E_SUCCESS)
3198 return I40E_SUCCESS;
3202 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3207 /* Wait until the request is finished */
3208 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3209 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3210 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3211 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3212 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3217 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3218 return I40E_SUCCESS; /* Already on, skip next steps */
3219 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3221 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3222 return I40E_SUCCESS; /* Already off, skip next steps */
3223 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3226 /* Write the register */
3227 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3228 /* Check the result */
3229 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3230 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3231 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3233 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3234 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3237 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3238 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3243 /* Check if it is timeout */
3244 if (j >= I40E_CHK_Q_ENA_COUNT) {
3245 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3246 (on ? "enable" : "disable"), q_idx);
3247 return I40E_ERR_TIMEOUT;
3250 return I40E_SUCCESS;
3252 /* Switch on or off the rx queues */
3254 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3256 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3257 struct i40e_rx_queue *rxq;
3258 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3262 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3263 rxq = dev_data->rx_queues[i];
3264 /* Don't operate the queue if not configured or
3265 * if starting only per queue */
3266 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3269 ret = i40e_dev_rx_queue_start(dev, i);
3271 ret = i40e_dev_rx_queue_stop(dev, i);
3272 if (ret != I40E_SUCCESS)
3276 return I40E_SUCCESS;
3279 /* Switch on or off all the rx/tx queues */
3281 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3286 /* enable rx queues before enabling tx queues */
3287 ret = i40e_vsi_switch_rx_queues(vsi, on);
3289 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3292 ret = i40e_vsi_switch_tx_queues(vsi, on);
3294 /* Stop tx queues before stopping rx queues */
3295 ret = i40e_vsi_switch_tx_queues(vsi, on);
3297 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3300 ret = i40e_vsi_switch_rx_queues(vsi, on);
3306 /* Initialize VSI for TX */
3308 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3310 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3311 struct rte_eth_dev_data *data = pf->dev_data;
3313 uint32_t ret = I40E_SUCCESS;
3315 for (i = 0; i < data->nb_tx_queues; i++) {
3316 ret = i40e_tx_queue_init(data->tx_queues[i]);
3317 if (ret != I40E_SUCCESS)
3324 /* Initialize VSI for RX */
3326 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3328 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3329 struct rte_eth_dev_data *data = pf->dev_data;
3330 int ret = I40E_SUCCESS;
3333 i40e_pf_config_mq_rx(pf);
3334 for (i = 0; i < data->nb_rx_queues; i++) {
3335 ret = i40e_rx_queue_init(data->rx_queues[i]);
3336 if (ret != I40E_SUCCESS) {
3337 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3346 /* Initialize VSI */
3348 i40e_vsi_init(struct i40e_vsi *vsi)
3352 err = i40e_vsi_tx_init(vsi);
3354 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3357 err = i40e_vsi_rx_init(vsi);
3359 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3367 i40e_stat_update_32(struct i40e_hw *hw,
3375 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3379 if (new_data >= *offset)
3380 *stat = (uint64_t)(new_data - *offset);
3382 *stat = (uint64_t)((new_data +
3383 ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3387 i40e_stat_update_48(struct i40e_hw *hw,
3396 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3397 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3398 I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3403 if (new_data >= *offset)
3404 *stat = new_data - *offset;
3406 *stat = (uint64_t)((new_data +
3407 ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3409 *stat &= I40E_48_BIT_MASK;
3414 i40e_pf_disable_irq0(struct i40e_hw *hw)
3416 /* Disable all interrupt types */
3417 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3418 I40E_WRITE_FLUSH(hw);
3423 i40e_pf_enable_irq0(struct i40e_hw *hw)
3425 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3426 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3427 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3428 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3429 I40E_WRITE_FLUSH(hw);
3433 i40e_pf_config_irq0(struct i40e_hw *hw)
3435 /* read pending request and disable first */
3436 i40e_pf_disable_irq0(hw);
3437 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3438 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3439 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3441 /* Link no queues with irq0 */
3442 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3443 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3447 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3449 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3453 uint32_t index, offset, val;
3458 * Try to find which VF trigger a reset, use absolute VF id to access
3459 * since the reg is global register.
3461 for (i = 0; i < pf->vf_num; i++) {
3462 abs_vf_id = hw->func_caps.vf_base_id + i;
3463 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3464 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3465 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3466 /* VFR event occured */
3467 if (val & (0x1 << offset)) {
3470 /* Clear the event first */
3471 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3473 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3475 * Only notify a VF reset event occured,
3476 * don't trigger another SW reset
3478 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3479 if (ret != I40E_SUCCESS)
3480 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3486 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3488 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489 struct i40e_arq_event_info info;
3490 uint16_t pending, opcode;
3493 info.buf_len = I40E_AQ_BUF_SZ;
3494 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3495 if (!info.msg_buf) {
3496 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3502 ret = i40e_clean_arq_element(hw, &info, &pending);
3504 if (ret != I40E_SUCCESS) {
3505 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3506 "aq_err: %u", hw->aq.asq_last_status);
3509 opcode = rte_le_to_cpu_16(info.desc.opcode);
3512 case i40e_aqc_opc_send_msg_to_pf:
3513 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3514 i40e_pf_host_handle_vf_msg(dev,
3515 rte_le_to_cpu_16(info.desc.retval),
3516 rte_le_to_cpu_32(info.desc.cookie_high),
3517 rte_le_to_cpu_32(info.desc.cookie_low),
3522 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3527 rte_free(info.msg_buf);
3531 * Interrupt handler is registered as the alarm callback for handling LSC
3532 * interrupt in a definite of time, in order to wait the NIC into a stable
3533 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3534 * no need for link down interrupt.
3537 i40e_dev_interrupt_delayed_handler(void *param)
3539 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3540 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543 /* read interrupt causes again */
3544 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3546 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3547 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3548 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3549 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3550 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3551 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3552 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3553 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3554 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3555 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3556 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3558 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3559 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3560 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3561 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3562 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3564 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3565 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3566 i40e_dev_handle_vfr_event(dev);
3568 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3569 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3570 i40e_dev_handle_aq_msg(dev);
3573 /* handle the link up interrupt in an alarm callback */
3574 i40e_dev_link_update(dev, 0);
3575 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3577 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3578 i40e_pf_enable_irq0(hw);
3579 rte_intr_enable(&(dev->pci_dev->intr_handle));
3583 * Interrupt handler triggered by NIC for handling
3584 * specific interrupt.
3587 * Pointer to interrupt handle.
3589 * The address of parameter (struct rte_eth_dev *) regsitered before.
3595 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3598 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3599 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 /* Disable interrupt */
3603 i40e_pf_disable_irq0(hw);
3604 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, 0);
3606 /* read out interrupt causes */
3607 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3609 /* No interrupt event indicated */
3610 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3611 PMD_DRV_LOG(INFO, "No interrupt event");
3614 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3615 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3616 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3617 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3618 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3619 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3620 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3621 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3622 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3623 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3624 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3625 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3626 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3627 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3628 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3629 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3631 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3632 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3633 i40e_dev_handle_vfr_event(dev);
3635 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3636 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3637 i40e_dev_handle_aq_msg(dev);
3640 /* Link Status Change interrupt */
3641 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3642 #define I40E_US_PER_SECOND 1000000
3643 struct rte_eth_link link;
3645 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3646 memset(&link, 0, sizeof(link));
3647 rte_i40e_dev_atomic_read_link_status(dev, &link);
3648 i40e_dev_link_update(dev, 0);
3651 * For link up interrupt, it needs to wait 1 second to let the
3652 * hardware be a stable state. Otherwise several consecutive
3653 * interrupts can be observed.
3654 * For link down interrupt, no need to wait.
3656 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3657 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3660 _rte_eth_dev_callback_process(dev,
3661 RTE_ETH_EVENT_INTR_LSC);
3665 /* Enable interrupt */
3666 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3667 i40e_pf_enable_irq0(hw);
3668 rte_intr_enable(&(dev->pci_dev->intr_handle));
3672 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3673 struct i40e_macvlan_filter *filter,
3676 int ele_num, ele_buff_size;
3677 int num, actual_num, i;
3679 int ret = I40E_SUCCESS;
3680 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3681 struct i40e_aqc_add_macvlan_element_data *req_list;
3683 if (filter == NULL || total == 0)
3684 return I40E_ERR_PARAM;
3685 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3686 ele_buff_size = hw->aq.asq_buf_size;
3688 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3689 if (req_list == NULL) {
3690 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3691 return I40E_ERR_NO_MEMORY;
3696 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3697 memset(req_list, 0, ele_buff_size);
3699 for (i = 0; i < actual_num; i++) {
3700 (void)rte_memcpy(req_list[i].mac_addr,
3701 &filter[num + i].macaddr, ETH_ADDR_LEN);
3702 req_list[i].vlan_tag =
3703 rte_cpu_to_le_16(filter[num + i].vlan_id);
3705 switch (filter[num + i].filter_type) {
3706 case RTE_MAC_PERFECT_MATCH:
3707 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3708 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3710 case RTE_MACVLAN_PERFECT_MATCH:
3711 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3713 case RTE_MAC_HASH_MATCH:
3714 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3715 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3717 case RTE_MACVLAN_HASH_MATCH:
3718 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
3721 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
3722 ret = I40E_ERR_PARAM;
3726 req_list[i].queue_number = 0;
3728 req_list[i].flags = rte_cpu_to_le_16(flags);
3731 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3733 if (ret != I40E_SUCCESS) {
3734 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3738 } while (num < total);
3746 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3747 struct i40e_macvlan_filter *filter,
3750 int ele_num, ele_buff_size;
3751 int num, actual_num, i;
3753 int ret = I40E_SUCCESS;
3754 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3755 struct i40e_aqc_remove_macvlan_element_data *req_list;
3757 if (filter == NULL || total == 0)
3758 return I40E_ERR_PARAM;
3760 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3761 ele_buff_size = hw->aq.asq_buf_size;
3763 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3764 if (req_list == NULL) {
3765 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3766 return I40E_ERR_NO_MEMORY;
3771 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3772 memset(req_list, 0, ele_buff_size);
3774 for (i = 0; i < actual_num; i++) {
3775 (void)rte_memcpy(req_list[i].mac_addr,
3776 &filter[num + i].macaddr, ETH_ADDR_LEN);
3777 req_list[i].vlan_tag =
3778 rte_cpu_to_le_16(filter[num + i].vlan_id);
3780 switch (filter[num + i].filter_type) {
3781 case RTE_MAC_PERFECT_MATCH:
3782 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3783 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3785 case RTE_MACVLAN_PERFECT_MATCH:
3786 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3788 case RTE_MAC_HASH_MATCH:
3789 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
3790 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3792 case RTE_MACVLAN_HASH_MATCH:
3793 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
3796 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
3797 ret = I40E_ERR_PARAM;
3800 req_list[i].flags = rte_cpu_to_le_16(flags);
3803 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3805 if (ret != I40E_SUCCESS) {
3806 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3810 } while (num < total);
3817 /* Find out specific MAC filter */
3818 static struct i40e_mac_filter *
3819 i40e_find_mac_filter(struct i40e_vsi *vsi,
3820 struct ether_addr *macaddr)
3822 struct i40e_mac_filter *f;
3824 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3825 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
3833 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3836 uint32_t vid_idx, vid_bit;
3838 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3839 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3841 if (vsi->vfta[vid_idx] & vid_bit)
3848 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3849 uint16_t vlan_id, bool on)
3851 uint32_t vid_idx, vid_bit;
3853 #define UINT32_BIT_MASK 0x1F
3854 #define VALID_VLAN_BIT_MASK 0xFFF
3855 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3856 * element first, then find the bits it belongs to
3858 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3860 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3863 vsi->vfta[vid_idx] |= vid_bit;
3865 vsi->vfta[vid_idx] &= ~vid_bit;
3869 * Find all vlan options for specific mac addr,
3870 * return with actual vlan found.
3873 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3874 struct i40e_macvlan_filter *mv_f,
3875 int num, struct ether_addr *addr)
3881 * Not to use i40e_find_vlan_filter to decrease the loop time,
3882 * although the code looks complex.
3884 if (num < vsi->vlan_num)
3885 return I40E_ERR_PARAM;
3888 for (j = 0; j < I40E_VFTA_SIZE; j++) {
3890 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3891 if (vsi->vfta[j] & (1 << k)) {
3893 PMD_DRV_LOG(ERR, "vlan number "
3895 return I40E_ERR_PARAM;
3897 (void)rte_memcpy(&mv_f[i].macaddr,
3898 addr, ETH_ADDR_LEN);
3900 j * I40E_UINT32_BIT_SIZE + k;
3906 return I40E_SUCCESS;
3910 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3911 struct i40e_macvlan_filter *mv_f,
3916 struct i40e_mac_filter *f;
3918 if (num < vsi->mac_num)
3919 return I40E_ERR_PARAM;
3921 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3923 PMD_DRV_LOG(ERR, "buffer number not match");
3924 return I40E_ERR_PARAM;
3926 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
3928 mv_f[i].vlan_id = vlan;
3929 mv_f[i].filter_type = f->mac_info.filter_type;
3933 return I40E_SUCCESS;
3937 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3940 struct i40e_mac_filter *f;
3941 struct i40e_macvlan_filter *mv_f;
3942 int ret = I40E_SUCCESS;
3944 if (vsi == NULL || vsi->mac_num == 0)
3945 return I40E_ERR_PARAM;
3947 /* Case that no vlan is set */
3948 if (vsi->vlan_num == 0)
3951 num = vsi->mac_num * vsi->vlan_num;
3953 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3955 PMD_DRV_LOG(ERR, "failed to allocate memory");
3956 return I40E_ERR_NO_MEMORY;
3960 if (vsi->vlan_num == 0) {
3961 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3962 (void)rte_memcpy(&mv_f[i].macaddr,
3963 &f->mac_info.mac_addr, ETH_ADDR_LEN);
3964 mv_f[i].vlan_id = 0;
3968 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3969 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3970 vsi->vlan_num, &f->mac_info.mac_addr);
3971 if (ret != I40E_SUCCESS)
3977 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3985 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3987 struct i40e_macvlan_filter *mv_f;
3989 int ret = I40E_SUCCESS;
3991 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3992 return I40E_ERR_PARAM;
3994 /* If it's already set, just return */
3995 if (i40e_find_vlan_filter(vsi,vlan))
3996 return I40E_SUCCESS;
3998 mac_num = vsi->mac_num;
4001 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4002 return I40E_ERR_PARAM;
4005 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4008 PMD_DRV_LOG(ERR, "failed to allocate memory");
4009 return I40E_ERR_NO_MEMORY;
4012 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4014 if (ret != I40E_SUCCESS)
4017 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4019 if (ret != I40E_SUCCESS)
4022 i40e_set_vlan_filter(vsi, vlan, 1);
4032 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4034 struct i40e_macvlan_filter *mv_f;
4036 int ret = I40E_SUCCESS;
4039 * Vlan 0 is the generic filter for untagged packets
4040 * and can't be removed.
4042 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4043 return I40E_ERR_PARAM;
4045 /* If can't find it, just return */
4046 if (!i40e_find_vlan_filter(vsi, vlan))
4047 return I40E_ERR_PARAM;
4049 mac_num = vsi->mac_num;
4052 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4053 return I40E_ERR_PARAM;
4056 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4059 PMD_DRV_LOG(ERR, "failed to allocate memory");
4060 return I40E_ERR_NO_MEMORY;
4063 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4065 if (ret != I40E_SUCCESS)
4068 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4070 if (ret != I40E_SUCCESS)
4073 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4074 if (vsi->vlan_num == 1) {
4075 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4076 if (ret != I40E_SUCCESS)
4079 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4080 if (ret != I40E_SUCCESS)
4084 i40e_set_vlan_filter(vsi, vlan, 0);
4094 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4096 struct i40e_mac_filter *f;
4097 struct i40e_macvlan_filter *mv_f;
4098 int i, vlan_num = 0;
4099 int ret = I40E_SUCCESS;
4101 /* If it's add and we've config it, return */
4102 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4104 return I40E_SUCCESS;
4105 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4106 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4109 * If vlan_num is 0, that's the first time to add mac,
4110 * set mask for vlan_id 0.
4112 if (vsi->vlan_num == 0) {
4113 i40e_set_vlan_filter(vsi, 0, 1);
4116 vlan_num = vsi->vlan_num;
4117 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4118 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4121 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4123 PMD_DRV_LOG(ERR, "failed to allocate memory");
4124 return I40E_ERR_NO_MEMORY;
4127 for (i = 0; i < vlan_num; i++) {
4128 mv_f[i].filter_type = mac_filter->filter_type;
4129 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4133 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4134 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4135 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4136 &mac_filter->mac_addr);
4137 if (ret != I40E_SUCCESS)
4141 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4142 if (ret != I40E_SUCCESS)
4145 /* Add the mac addr into mac list */
4146 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4148 PMD_DRV_LOG(ERR, "failed to allocate memory");
4149 ret = I40E_ERR_NO_MEMORY;
4152 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4154 f->mac_info.filter_type = mac_filter->filter_type;
4155 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4166 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4168 struct i40e_mac_filter *f;
4169 struct i40e_macvlan_filter *mv_f;
4171 enum rte_mac_filter_type filter_type;
4172 int ret = I40E_SUCCESS;
4174 /* Can't find it, return an error */
4175 f = i40e_find_mac_filter(vsi, addr);
4177 return I40E_ERR_PARAM;
4179 vlan_num = vsi->vlan_num;
4180 filter_type = f->mac_info.filter_type;
4181 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4182 filter_type == RTE_MACVLAN_HASH_MATCH) {
4183 if (vlan_num == 0) {
4184 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4185 return I40E_ERR_PARAM;
4187 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4188 filter_type == RTE_MAC_HASH_MATCH)
4191 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4193 PMD_DRV_LOG(ERR, "failed to allocate memory");
4194 return I40E_ERR_NO_MEMORY;
4197 for (i = 0; i < vlan_num; i++) {
4198 mv_f[i].filter_type = filter_type;
4199 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4202 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4203 filter_type == RTE_MACVLAN_HASH_MATCH) {
4204 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4205 if (ret != I40E_SUCCESS)
4209 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4210 if (ret != I40E_SUCCESS)
4213 /* Remove the mac addr into mac list */
4214 TAILQ_REMOVE(&vsi->mac_list, f, next);
4224 /* Configure hash enable flags for RSS */
4226 i40e_config_hena(uint64_t flags)
4233 if (flags & ETH_RSS_NONF_IPV4_UDP)
4234 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4235 if (flags & ETH_RSS_NONF_IPV4_TCP)
4236 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4237 if (flags & ETH_RSS_NONF_IPV4_SCTP)
4238 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4239 if (flags & ETH_RSS_NONF_IPV4_OTHER)
4240 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4241 if (flags & ETH_RSS_FRAG_IPV4)
4242 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4243 if (flags & ETH_RSS_NONF_IPV6_UDP)
4244 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4245 if (flags & ETH_RSS_NONF_IPV6_TCP)
4246 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4247 if (flags & ETH_RSS_NONF_IPV6_SCTP)
4248 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4249 if (flags & ETH_RSS_NONF_IPV6_OTHER)
4250 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4251 if (flags & ETH_RSS_FRAG_IPV6)
4252 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4253 if (flags & ETH_RSS_L2_PAYLOAD)
4254 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4259 /* Parse the hash enable flags */
4261 i40e_parse_hena(uint64_t flags)
4263 uint64_t rss_hf = 0;
4268 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4269 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4270 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4271 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4272 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4273 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4274 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4275 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4276 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4277 rss_hf |= ETH_RSS_FRAG_IPV4;
4278 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4279 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4280 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4281 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4282 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4283 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4284 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4285 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4286 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4287 rss_hf |= ETH_RSS_FRAG_IPV6;
4288 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4289 rss_hf |= ETH_RSS_L2_PAYLOAD;
4296 i40e_pf_disable_rss(struct i40e_pf *pf)
4298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4301 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4302 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4303 hena &= ~I40E_RSS_HENA_ALL;
4304 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4305 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4306 I40E_WRITE_FLUSH(hw);
4310 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4313 uint8_t hash_key_len;
4318 hash_key = (uint32_t *)(rss_conf->rss_key);
4319 hash_key_len = rss_conf->rss_key_len;
4320 if (hash_key != NULL && hash_key_len >=
4321 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4322 /* Fill in RSS hash key */
4323 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4324 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4327 rss_hf = rss_conf->rss_hf;
4328 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4329 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4330 hena &= ~I40E_RSS_HENA_ALL;
4331 hena |= i40e_config_hena(rss_hf);
4332 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4333 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4334 I40E_WRITE_FLUSH(hw);
4340 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4341 struct rte_eth_rss_conf *rss_conf)
4343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4347 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4348 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4349 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4350 if (rss_hf != 0) /* Enable RSS */
4352 return 0; /* Nothing to do */
4355 if (rss_hf == 0) /* Disable RSS */
4358 return i40e_hw_rss_hash_set(hw, rss_conf);
4362 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4363 struct rte_eth_rss_conf *rss_conf)
4365 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4370 if (hash_key != NULL) {
4371 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4372 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4373 rss_conf->rss_key_len = i * sizeof(uint32_t);
4375 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4376 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4377 rss_conf->rss_hf = i40e_parse_hena(hena);
4383 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4385 switch (filter_type) {
4386 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4387 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4389 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4390 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4392 case RTE_TUNNEL_FILTER_IMAC_TENID:
4393 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4395 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4396 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4398 case ETH_TUNNEL_FILTER_IMAC:
4399 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4402 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4410 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4411 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4415 uint8_t tun_type = 0;
4417 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4418 struct i40e_vsi *vsi = pf->main_vsi;
4419 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4420 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4422 cld_filter = rte_zmalloc("tunnel_filter",
4423 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4426 if (NULL == cld_filter) {
4427 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4430 pfilter = cld_filter;
4432 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4433 sizeof(struct ether_addr));
4434 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4435 sizeof(struct ether_addr));
4437 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4438 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4439 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4440 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4441 &tunnel_filter->ip_addr,
4442 sizeof(pfilter->ipaddr.v4.data));
4444 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4445 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4446 &tunnel_filter->ip_addr,
4447 sizeof(pfilter->ipaddr.v6.data));
4450 /* check tunneled type */
4451 switch (tunnel_filter->tunnel_type) {
4452 case RTE_TUNNEL_TYPE_VXLAN:
4453 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4456 /* Other tunnel types is not supported. */
4457 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4458 rte_free(cld_filter);
4462 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4465 rte_free(cld_filter);
4469 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4470 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4471 pfilter->tenant_id = tunnel_filter->tenant_id;
4472 pfilter->queue_number = tunnel_filter->queue_id;
4475 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4477 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4480 rte_free(cld_filter);
4485 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4489 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4490 if (pf->vxlan_ports[i] == port)
4498 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4502 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4504 idx = i40e_get_vxlan_port_idx(pf, port);
4506 /* Check if port already exists */
4508 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4512 /* Now check if there is space to add the new port */
4513 idx = i40e_get_vxlan_port_idx(pf, 0);
4515 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4516 "not adding port %d", port);
4520 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4523 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4527 PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4528 port, filter_index);
4530 /* New port: add it and mark its index in the bitmap */
4531 pf->vxlan_ports[idx] = port;
4532 pf->vxlan_bitmap |= (1 << idx);
4534 if (!(pf->flags & I40E_FLAG_VXLAN))
4535 pf->flags |= I40E_FLAG_VXLAN;
4541 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4544 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4546 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4547 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4551 idx = i40e_get_vxlan_port_idx(pf, port);
4554 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4558 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4559 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4563 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4566 pf->vxlan_ports[idx] = 0;
4567 pf->vxlan_bitmap &= ~(1 << idx);
4569 if (!pf->vxlan_bitmap)
4570 pf->flags &= ~I40E_FLAG_VXLAN;
4575 /* Add UDP tunneling port */
4577 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4578 struct rte_eth_udp_tunnel *udp_tunnel)
4581 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4583 if (udp_tunnel == NULL)
4586 switch (udp_tunnel->prot_type) {
4587 case RTE_TUNNEL_TYPE_VXLAN:
4588 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4591 case RTE_TUNNEL_TYPE_GENEVE:
4592 case RTE_TUNNEL_TYPE_TEREDO:
4593 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4598 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4606 /* Remove UDP tunneling port */
4608 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4609 struct rte_eth_udp_tunnel *udp_tunnel)
4612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4614 if (udp_tunnel == NULL)
4617 switch (udp_tunnel->prot_type) {
4618 case RTE_TUNNEL_TYPE_VXLAN:
4619 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4621 case RTE_TUNNEL_TYPE_GENEVE:
4622 case RTE_TUNNEL_TYPE_TEREDO:
4623 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4627 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4637 i40e_pf_config_rss(struct i40e_pf *pf)
4639 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4640 struct rte_eth_rss_conf rss_conf;
4641 uint32_t i, lut = 0;
4642 uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4644 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4647 lut = (lut << 8) | (j & ((0x1 <<
4648 hw->func_caps.rss_table_entry_width) - 1));
4650 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4653 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4654 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4655 i40e_pf_disable_rss(pf);
4658 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4659 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4660 /* Calculate the default hash key */
4661 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4662 rss_key_default[i] = (uint32_t)rte_rand();
4663 rss_conf.rss_key = (uint8_t *)rss_key_default;
4664 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4668 return i40e_hw_rss_hash_set(hw, &rss_conf);
4672 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4673 struct rte_eth_tunnel_filter_conf *filter)
4675 if (pf == NULL || filter == NULL) {
4676 PMD_DRV_LOG(ERR, "Invalid parameter");
4680 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4681 PMD_DRV_LOG(ERR, "Invalid queue ID");
4685 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4686 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4690 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4691 (is_zero_ether_addr(filter->outer_mac))) {
4692 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4696 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4697 (is_zero_ether_addr(filter->inner_mac))) {
4698 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4706 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4709 struct rte_eth_tunnel_filter_conf *filter;
4710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4711 int ret = I40E_SUCCESS;
4713 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4715 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4716 return I40E_ERR_PARAM;
4718 switch (filter_op) {
4719 case RTE_ETH_FILTER_NOP:
4720 if (!(pf->flags & I40E_FLAG_VXLAN))
4721 ret = I40E_NOT_SUPPORTED;
4722 case RTE_ETH_FILTER_ADD:
4723 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4725 case RTE_ETH_FILTER_DELETE:
4726 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4729 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4730 ret = I40E_ERR_PARAM;
4738 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4740 if (!pf->dev_data->sriov.active) {
4741 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4743 i40e_pf_config_rss(pf);
4746 i40e_pf_disable_rss(pf);
4755 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4756 enum rte_filter_type filter_type,
4757 enum rte_filter_op filter_op,
4765 switch (filter_type) {
4766 case RTE_ETH_FILTER_MACVLAN:
4767 ret = i40e_mac_filter_handle(dev, filter_op, arg);
4769 case RTE_ETH_FILTER_TUNNEL:
4770 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
4773 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",