lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 /* Maximun number of MAC addresses */
  62 #define I40E_NUM_MACADDR_MAX       64
  63 #define I40E_CLEAR_PXE_WAIT_MS     200
  64
  65 /* Maximun number of capability elements */
  66 #define I40E_MAX_CAP_ELE_NUM       128
  67
  68 /* Wait count and inteval */
  69 #define I40E_CHK_Q_ENA_COUNT       1000
  70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  71
  72 /* Maximun number of VSI */
  73 #define I40E_MAX_NUM_VSIS          (384UL)
  74
  75 /* Bit shift and mask */
  76 #define I40E_16_BIT_SHIFT 16
  77 #define I40E_16_BIT_MASK  0xFFFF
  78 #define I40E_32_BIT_SHIFT 32
  79 #define I40E_32_BIT_MASK  0xFFFFFFFF
  80 #define I40E_48_BIT_SHIFT 48
  81 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  82
  83 /* Default queue interrupt throttling time in microseconds*/
  84 #define I40E_ITR_INDEX_DEFAULT          0
  85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  86 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  87
  88 #define I40E_RSS_OFFLOAD_ALL ( \
  89         ETH_RSS_NONF_IPV4_UDP | \
  90         ETH_RSS_NONF_IPV4_TCP | \
  91         ETH_RSS_NONF_IPV4_SCTP | \
  92         ETH_RSS_NONF_IPV4_OTHER | \
  93         ETH_RSS_FRAG_IPV4 | \
  94         ETH_RSS_NONF_IPV6_UDP | \
  95         ETH_RSS_NONF_IPV6_TCP | \
  96         ETH_RSS_NONF_IPV6_SCTP | \
  97         ETH_RSS_NONF_IPV6_OTHER | \
  98         ETH_RSS_FRAG_IPV6 | \
  99         ETH_RSS_L2_PAYLOAD)
 100
 101 /* All bits of RSS hash enable */
 102 #define I40E_RSS_HENA_ALL ( \
 103         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 104         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 105         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 106         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 107         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 108         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 109         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 110         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 111         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 112         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 113         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 114         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 115         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 116         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 117
 118 static int eth_i40e_dev_init(\
 119                         __attribute__((unused)) struct eth_driver *eth_drv,
 120                         struct rte_eth_dev *eth_dev);
 121 static int i40e_dev_configure(struct rte_eth_dev *dev);
 122 static int i40e_dev_start(struct rte_eth_dev *dev);
 123 static void i40e_dev_stop(struct rte_eth_dev *dev);
 124 static void i40e_dev_close(struct rte_eth_dev *dev);
 125 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 130                                struct rte_eth_stats *stats);
 131 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 132 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 133                                             uint16_t queue_id,
 134                                             uint8_t stat_idx,
 135                                             uint8_t is_rx);
 136 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 137                               struct rte_eth_dev_info *dev_info);
 138 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 139                                 uint16_t vlan_id,
 140                                 int on);
 141 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 142 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 143 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 144                                       uint16_t queue,
 145                                       int on);
 146 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 147 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 148 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 149 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 150                               struct rte_eth_fc_conf *fc_conf);
 151 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 152                                        struct rte_eth_pfc_conf *pfc_conf);
 153 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 154                           struct ether_addr *mac_addr,
 155                           uint32_t index,
 156                           uint32_t pool);
 157 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 158 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 159                                     struct rte_eth_rss_reta *reta_conf);
 160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 161                                    struct rte_eth_rss_reta *reta_conf);
 162
 163 static int i40e_get_cap(struct i40e_hw *hw);
 164 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 165 static int i40e_pf_setup(struct i40e_pf *pf);
 166 static int i40e_vsi_init(struct i40e_vsi *vsi);
 167 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 168                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 169 static void i40e_stat_update_48(struct i40e_hw *hw,
 170                                uint32_t hireg,
 171                                uint32_t loreg,
 172                                bool offset_loaded,
 173                                uint64_t *offset,
 174                                uint64_t *stat);
 175 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 176 static void i40e_dev_interrupt_handler(
 177                 __rte_unused struct rte_intr_handle *handle, void *param);
 178 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 179                                 uint32_t base, uint32_t num);
 180 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 181 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 182                         uint32_t base);
 183 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 184                         uint16_t num);
 185 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 186 static int i40e_veb_release(struct i40e_veb *veb);
 187 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 188                                                 struct i40e_vsi *vsi);
 189 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 190 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 191 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 192                                              struct i40e_macvlan_filter *mv_f,
 193                                              int num,
 194                                              struct ether_addr *addr);
 195 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 196                                              struct i40e_macvlan_filter *mv_f,
 197                                              int num,
 198                                              uint16_t vlan);
 199 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 200 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 201                                     struct rte_eth_rss_conf *rss_conf);
 202 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 203                                       struct rte_eth_rss_conf *rss_conf);
 204
 205 /* Default hash key buffer for RSS */
 206 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 207
 208 static struct rte_pci_id pci_id_i40e_map[] = {
 209 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 210 #include "rte_pci_dev_ids.h"
 211 { .vendor_id = 0, /* sentinel */ },
 212 };
 213
 214 static struct eth_dev_ops i40e_eth_dev_ops = {
 215         .dev_configure                = i40e_dev_configure,
 216         .dev_start                    = i40e_dev_start,
 217         .dev_stop                     = i40e_dev_stop,
 218         .dev_close                    = i40e_dev_close,
 219         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 220         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 221         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 222         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 223         .link_update                  = i40e_dev_link_update,
 224         .stats_get                    = i40e_dev_stats_get,
 225         .stats_reset                  = i40e_dev_stats_reset,
 226         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 227         .dev_infos_get                = i40e_dev_info_get,
 228         .vlan_filter_set              = i40e_vlan_filter_set,
 229         .vlan_tpid_set                = i40e_vlan_tpid_set,
 230         .vlan_offload_set             = i40e_vlan_offload_set,
 231         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 232         .vlan_pvid_set                = i40e_vlan_pvid_set,
 233         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 234         .rx_queue_release             = i40e_dev_rx_queue_release,
 235         .rx_queue_count               = i40e_dev_rx_queue_count,
 236         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 237         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 238         .tx_queue_release             = i40e_dev_tx_queue_release,
 239         .dev_led_on                   = i40e_dev_led_on,
 240         .dev_led_off                  = i40e_dev_led_off,
 241         .flow_ctrl_set                = i40e_flow_ctrl_set,
 242         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 243         .mac_addr_add                 = i40e_macaddr_add,
 244         .mac_addr_remove              = i40e_macaddr_remove,
 245         .reta_update                  = i40e_dev_rss_reta_update,
 246         .reta_query                   = i40e_dev_rss_reta_query,
 247         .rss_hash_update              = i40e_dev_rss_hash_update,
 248         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 249 };
 250
 251 static struct eth_driver rte_i40e_pmd = {
 252         {
 253                 .name = "rte_i40e_pmd",
 254                 .id_table = pci_id_i40e_map,
 255                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 256         },
 257         .eth_dev_init = eth_i40e_dev_init,
 258         .dev_private_size = sizeof(struct i40e_adapter),
 259 };
 260
 261 static inline int
 262 i40e_prev_power_of_2(int n)
 263 {
 264        int p = n;
 265
 266        --p;
 267        p |= p >> 1;
 268        p |= p >> 2;
 269        p |= p >> 4;
 270        p |= p >> 8;
 271        p |= p >> 16;
 272        if (p == (n - 1))
 273                return n;
 274        p >>= 1;
 275
 276        return ++p;
 277 }
 278
 279 static inline int
 280 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 281                                      struct rte_eth_link *link)
 282 {
 283         struct rte_eth_link *dst = link;
 284         struct rte_eth_link *src = &(dev->data->dev_link);
 285
 286         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 287                                         *(uint64_t *)src) == 0)
 288                 return -1;
 289
 290         return 0;
 291 }
 292
 293 static inline int
 294 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 295                                       struct rte_eth_link *link)
 296 {
 297         struct rte_eth_link *dst = &(dev->data->dev_link);
 298         struct rte_eth_link *src = link;
 299
 300         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 301                                         *(uint64_t *)src) == 0)
 302                 return -1;
 303
 304         return 0;
 305 }
 306
 307 /*
 308  * Driver initialization routine.
 309  * Invoked once at EAL init time.
 310  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 311  */
 312 static int
 313 rte_i40e_pmd_init(const char *name __rte_unused,
 314                   const char *params __rte_unused)
 315 {
 316         PMD_INIT_FUNC_TRACE();
 317         rte_eth_driver_register(&rte_i40e_pmd);
 318
 319         return 0;
 320 }
 321
 322 static struct rte_driver rte_i40e_driver = {
 323         .type = PMD_PDEV,
 324         .init = rte_i40e_pmd_init,
 325 };
 326
 327 PMD_REGISTER_DRIVER(rte_i40e_driver);
 328
 329 static int
 330 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 331                   struct rte_eth_dev *dev)
 332 {
 333         struct rte_pci_device *pci_dev;
 334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 336         struct i40e_vsi *vsi;
 337         int ret;
 338         uint32_t len;
 339         uint8_t aq_fail = 0;
 340
 341         PMD_INIT_FUNC_TRACE();
 342
 343         dev->dev_ops = &i40e_eth_dev_ops;
 344         dev->rx_pkt_burst = i40e_recv_pkts;
 345         dev->tx_pkt_burst = i40e_xmit_pkts;
 346
 347         /* for secondary processes, we don't initialise any further as primary
 348          * has already done this work. Only check we don't need a different
 349          * RX function */
 350         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 351                 if (dev->data->scattered_rx)
 352                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 353                 return 0;
 354         }
 355         pci_dev = dev->pci_dev;
 356         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 357         pf->adapter->eth_dev = dev;
 358         pf->dev_data = dev->data;
 359
 360         hw->back = I40E_PF_TO_ADAPTER(pf);
 361         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 362         if (!hw->hw_addr) {
 363                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 364                                         "as address is NULL\n");
 365                 return -ENODEV;
 366         }
 367
 368         hw->vendor_id = pci_dev->id.vendor_id;
 369         hw->device_id = pci_dev->id.device_id;
 370         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 371         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 372         hw->bus.device = pci_dev->addr.devid;
 373         hw->bus.func = pci_dev->addr.function;
 374
 375         /* Make sure all is clean before doing PF reset */
 376         i40e_clear_hw(hw);
 377
 378         /* Reset here to make sure all is clean for each PF */
 379         ret = i40e_pf_reset(hw);
 380         if (ret) {
 381                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 382                 return ret;
 383         }
 384
 385         /* Initialize the shared code (base driver) */
 386         ret = i40e_init_shared_code(hw);
 387         if (ret) {
 388                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 389                 return ret;
 390         }
 391
 392         /* Initialize the parameters for adminq */
 393         i40e_init_adminq_parameter(hw);
 394         ret = i40e_init_adminq(hw);
 395         if (ret != I40E_SUCCESS) {
 396                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 397                 return -EIO;
 398         }
 399         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
 400                         "%02d.%02d.%02d eetrack %04x\n",
 401                         hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 402                         hw->aq.api_maj_ver, hw->aq.api_min_ver,
 403                         ((hw->nvm.version >> 12) & 0xf),
 404                         ((hw->nvm.version >> 4) & 0xff),
 405                         (hw->nvm.version & 0xf), hw->nvm.eetrack);
 406
 407         /* Disable LLDP */
 408         ret = i40e_aq_stop_lldp(hw, true, NULL);
 409         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 410                 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
 411
 412         /* Clear PXE mode */
 413         i40e_clear_pxe_mode(hw);
 414
 415         /* Get hw capabilities */
 416         ret = i40e_get_cap(hw);
 417         if (ret != I40E_SUCCESS) {
 418                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 419                 goto err_get_capabilities;
 420         }
 421
 422         /* Initialize parameters for PF */
 423         ret = i40e_pf_parameter_init(dev);
 424         if (ret != 0) {
 425                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 426                 goto err_parameter_init;
 427         }
 428
 429         /* Initialize the queue management */
 430         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 431         if (ret < 0) {
 432                 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
 433                 goto err_qp_pool_init;
 434         }
 435         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 436                                 hw->func_caps.num_msix_vectors - 1);
 437         if (ret < 0) {
 438                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
 439                 goto err_msix_pool_init;
 440         }
 441
 442         /* Initialize lan hmc */
 443         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 444                                 hw->func_caps.num_rx_qp, 0, 0);
 445         if (ret != I40E_SUCCESS) {
 446                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 447                 goto err_init_lan_hmc;
 448         }
 449
 450         /* Configure lan hmc */
 451         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 452         if (ret != I40E_SUCCESS) {
 453                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 454                 goto err_configure_lan_hmc;
 455         }
 456
 457         /* Get and check the mac address */
 458         i40e_get_mac_addr(hw, hw->mac.addr);
 459         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 460                 PMD_INIT_LOG(ERR, "mac address is not valid");
 461                 ret = -EIO;
 462                 goto err_get_mac_addr;
 463         }
 464         /* Copy the permanent MAC address */
 465         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 466                         (struct ether_addr *) hw->mac.perm_addr);
 467
 468         /* Disable flow control */
 469         hw->fc.requested_mode = I40E_FC_NONE;
 470         i40e_set_fc(hw, &aq_fail, TRUE);
 471
 472         /* PF setup, which includes VSI setup */
 473         ret = i40e_pf_setup(pf);
 474         if (ret) {
 475                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 476                 goto err_setup_pf_switch;
 477         }
 478
 479         vsi = pf->main_vsi;
 480
 481         /* Disable double vlan by default */
 482         i40e_vsi_config_double_vlan(vsi, FALSE);
 483
 484         if (!vsi->max_macaddrs)
 485                 len = ETHER_ADDR_LEN;
 486         else
 487                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 488
 489         /* Should be after VSI initialized */
 490         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 491         if (!dev->data->mac_addrs) {
 492                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 493                                         "for storing mac address");
 494                 goto err_get_mac_addr;
 495         }
 496         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 497                                         &dev->data->mac_addrs[0]);
 498
 499         /* initialize pf host driver to setup SRIOV resource if applicable */
 500         i40e_pf_host_init(dev);
 501
 502         /* register callback func to eal lib */
 503         rte_intr_callback_register(&(pci_dev->intr_handle),
 504                 i40e_dev_interrupt_handler, (void *)dev);
 505
 506         /* configure and enable device interrupt */
 507         i40e_pf_config_irq0(hw);
 508         i40e_pf_enable_irq0(hw);
 509
 510         /* enable uio intr after callback register */
 511         rte_intr_enable(&(pci_dev->intr_handle));
 512
 513         return 0;
 514
 515 err_setup_pf_switch:
 516         rte_free(pf->main_vsi);
 517 err_get_mac_addr:
 518 err_configure_lan_hmc:
 519         (void)i40e_shutdown_lan_hmc(hw);
 520 err_init_lan_hmc:
 521         i40e_res_pool_destroy(&pf->msix_pool);
 522 err_msix_pool_init:
 523         i40e_res_pool_destroy(&pf->qp_pool);
 524 err_qp_pool_init:
 525 err_parameter_init:
 526 err_get_capabilities:
 527         (void)i40e_shutdown_adminq(hw);
 528
 529         return ret;
 530 }
 531
 532 static int
 533 i40e_dev_configure(struct rte_eth_dev *dev)
 534 {
 535         return i40e_dev_init_vlan(dev);
 536 }
 537
 538 void
 539 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 540 {
 541         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 542         uint16_t msix_vect = vsi->msix_intr;
 543         uint16_t i;
 544
 545         for (i = 0; i < vsi->nb_qps; i++) {
 546                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 547                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 548                 rte_wmb();
 549         }
 550
 551         if (vsi->type != I40E_VSI_SRIOV) {
 552                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 553                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 554                                 msix_vect - 1), 0);
 555         } else {
 556                 uint32_t reg;
 557                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 558                         vsi->user_param + (msix_vect - 1);
 559
 560                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 561         }
 562         I40E_WRITE_FLUSH(hw);
 563 }
 564
 565 static inline uint16_t
 566 i40e_calc_itr_interval(int16_t interval)
 567 {
 568         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 569                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 570
 571         /* Convert to hardware count, as writing each 1 represents 2 us */
 572         return (interval/2);
 573 }
 574
 575 void
 576 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 577 {
 578         uint32_t val;
 579         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 580         uint16_t msix_vect = vsi->msix_intr;
 581         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 582         int i;
 583
 584         for (i = 0; i < vsi->nb_qps; i++)
 585                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 586
 587         /* Bind all RX queues to allocated MSIX interrupt */
 588         for (i = 0; i < vsi->nb_qps; i++) {
 589                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 590                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 591                         ((vsi->base_queue + i + 1) <<
 592                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 593                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 594                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 595
 596                 if (i == vsi->nb_qps - 1)
 597                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 598                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 599         }
 600
 601         /* Write first RX queue to Link list register as the head element */
 602         if (vsi->type != I40E_VSI_SRIOV) {
 603                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 604                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 605                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 606
 607                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 608                                 msix_vect - 1), interval);
 609
 610                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 611                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 612                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 613         }
 614         else {
 615                 uint32_t reg;
 616                 /* num_msix_vectors_vf needs to minus irq0 */
 617                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 618                         vsi->user_param + (msix_vect - 1);
 619
 620                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 621                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 622                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 623         }
 624
 625         I40E_WRITE_FLUSH(hw);
 626 }
 627
 628 static void
 629 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 630 {
 631         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 632         uint16_t interval = i40e_calc_itr_interval(\
 633                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 634
 635         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 636                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 637                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 638                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 639                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 640 }
 641
 642 static void
 643 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 644 {
 645         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 646
 647         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 648 }
 649
 650 static int
 651 i40e_dev_start(struct rte_eth_dev *dev)
 652 {
 653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         struct i40e_vsi *vsi = pf->main_vsi;
 656         int ret;
 657
 658         /* Initialize VSI */
 659         ret = i40e_vsi_init(vsi);
 660         if (ret != I40E_SUCCESS) {
 661                 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
 662                 goto err_up;
 663         }
 664
 665         /* Map queues with MSIX interrupt */
 666         i40e_vsi_queues_bind_intr(vsi);
 667         i40e_vsi_enable_queues_intr(vsi);
 668
 669         /* Enable all queues which have been configured */
 670         ret = i40e_vsi_switch_queues(vsi, TRUE);
 671         if (ret != I40E_SUCCESS) {
 672                 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
 673                 goto err_up;
 674         }
 675
 676         /* Enable receiving broadcast packets */
 677         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 678                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 679                 if (ret != I40E_SUCCESS)
 680                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
 681         }
 682
 683         return I40E_SUCCESS;
 684
 685 err_up:
 686         i40e_vsi_switch_queues(vsi, FALSE);
 687         i40e_dev_clear_queues(dev);
 688
 689         return ret;
 690 }
 691
 692 static void
 693 i40e_dev_stop(struct rte_eth_dev *dev)
 694 {
 695         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 696         struct i40e_vsi *vsi = pf->main_vsi;
 697
 698         /* Disable all queues */
 699         i40e_vsi_switch_queues(vsi, FALSE);
 700
 701         /* Clear all queues and release memory */
 702         i40e_dev_clear_queues(dev);
 703
 704         /* un-map queues with interrupt registers */
 705         i40e_vsi_disable_queues_intr(vsi);
 706         i40e_vsi_queues_unbind_intr(vsi);
 707 }
 708
 709 static void
 710 i40e_dev_close(struct rte_eth_dev *dev)
 711 {
 712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 714         uint32_t reg;
 715
 716         PMD_INIT_FUNC_TRACE();
 717
 718         i40e_dev_stop(dev);
 719
 720         /* Disable interrupt */
 721         i40e_pf_disable_irq0(hw);
 722         rte_intr_disable(&(dev->pci_dev->intr_handle));
 723
 724         /* shutdown and destroy the HMC */
 725         i40e_shutdown_lan_hmc(hw);
 726
 727         /* release all the existing VSIs and VEBs */
 728         i40e_vsi_release(pf->main_vsi);
 729
 730         /* shutdown the adminq */
 731         i40e_aq_queue_shutdown(hw, true);
 732         i40e_shutdown_adminq(hw);
 733
 734         i40e_res_pool_destroy(&pf->qp_pool);
 735         i40e_res_pool_destroy(&pf->msix_pool);
 736
 737         /* force a PF reset to clean anything leftover */
 738         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 739         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 740                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 741         I40E_WRITE_FLUSH(hw);
 742 }
 743
 744 static void
 745 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 746 {
 747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 749         struct i40e_vsi *vsi = pf->main_vsi;
 750         int status;
 751
 752         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 753                                                         true, NULL);
 754         if (status != I40E_SUCCESS)
 755                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
 756 }
 757
 758 static void
 759 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 760 {
 761         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 763         struct i40e_vsi *vsi = pf->main_vsi;
 764         int status;
 765
 766         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 767                                                         false, NULL);
 768         if (status != I40E_SUCCESS)
 769                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
 770 }
 771
 772 static void
 773 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 774 {
 775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 777         struct i40e_vsi *vsi = pf->main_vsi;
 778         int ret;
 779
 780         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 781         if (ret != I40E_SUCCESS)
 782                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
 783 }
 784
 785 static void
 786 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 787 {
 788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 790         struct i40e_vsi *vsi = pf->main_vsi;
 791         int ret;
 792
 793         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 794                                 vsi->seid, FALSE, NULL);
 795         if (ret != I40E_SUCCESS)
 796                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
 797 }
 798
 799 int
 800 i40e_dev_link_update(struct rte_eth_dev *dev,
 801                      __rte_unused int wait_to_complete)
 802 {
 803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 804         struct i40e_link_status link_status;
 805         struct rte_eth_link link, old;
 806         int status;
 807
 808         memset(&link, 0, sizeof(link));
 809         memset(&old, 0, sizeof(old));
 810         memset(&link_status, 0, sizeof(link_status));
 811         rte_i40e_dev_atomic_read_link_status(dev, &old);
 812
 813         /* Get link status information from hardware */
 814         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 815         if (status != I40E_SUCCESS) {
 816                 link.link_speed = ETH_LINK_SPEED_100;
 817                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 818                 PMD_DRV_LOG(ERR, "Failed to get link info\n");
 819                 goto out;
 820         }
 821
 822         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 823
 824         if (!link.link_status)
 825                 goto out;
 826
 827         /* i40e uses full duplex only */
 828         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 829
 830         /* Parse the link status */
 831         switch (link_status.link_speed) {
 832         case I40E_LINK_SPEED_100MB:
 833                 link.link_speed = ETH_LINK_SPEED_100;
 834                 break;
 835         case I40E_LINK_SPEED_1GB:
 836                 link.link_speed = ETH_LINK_SPEED_1000;
 837                 break;
 838         case I40E_LINK_SPEED_10GB:
 839                 link.link_speed = ETH_LINK_SPEED_10G;
 840                 break;
 841         case I40E_LINK_SPEED_20GB:
 842                 link.link_speed = ETH_LINK_SPEED_20G;
 843                 break;
 844         case I40E_LINK_SPEED_40GB:
 845                 link.link_speed = ETH_LINK_SPEED_40G;
 846                 break;
 847         default:
 848                 link.link_speed = ETH_LINK_SPEED_100;
 849                 break;
 850         }
 851
 852 out:
 853         rte_i40e_dev_atomic_write_link_status(dev, &link);
 854         if (link.link_status == old.link_status)
 855                 return -1;
 856
 857         return 0;
 858 }
 859
 860 /* Get all the statistics of a VSI */
 861 void
 862 i40e_update_vsi_stats(struct i40e_vsi *vsi)
 863 {
 864         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 865         struct i40e_eth_stats *nes = &vsi->eth_stats;
 866         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 867         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
 868
 869         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
 870                             vsi->offset_loaded, &oes->rx_bytes,
 871                             &nes->rx_bytes);
 872         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
 873                             vsi->offset_loaded, &oes->rx_unicast,
 874                             &nes->rx_unicast);
 875         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
 876                             vsi->offset_loaded, &oes->rx_multicast,
 877                             &nes->rx_multicast);
 878         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
 879                             vsi->offset_loaded, &oes->rx_broadcast,
 880                             &nes->rx_broadcast);
 881         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
 882                             &oes->rx_discards, &nes->rx_discards);
 883         /* GLV_REPC not supported */
 884         /* GLV_RMPC not supported */
 885         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
 886                             &oes->rx_unknown_protocol,
 887                             &nes->rx_unknown_protocol);
 888         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
 889                             vsi->offset_loaded, &oes->tx_bytes,
 890                             &nes->tx_bytes);
 891         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
 892                             vsi->offset_loaded, &oes->tx_unicast,
 893                             &nes->tx_unicast);
 894         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
 895                             vsi->offset_loaded, &oes->tx_multicast,
 896                             &nes->tx_multicast);
 897         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
 898                             vsi->offset_loaded,  &oes->tx_broadcast,
 899                             &nes->tx_broadcast);
 900         /* GLV_TDPC not supported */
 901         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
 902                             &oes->tx_errors, &nes->tx_errors);
 903         vsi->offset_loaded = true;
 904
 905 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
 906         printf("***************** VSI[%u] stats start *******************\n",
 907                                                                 vsi->vsi_id);
 908         printf("rx_bytes:            %lu\n", nes->rx_bytes);
 909         printf("rx_unicast:          %lu\n", nes->rx_unicast);
 910         printf("rx_multicast:        %lu\n", nes->rx_multicast);
 911         printf("rx_broadcast:        %lu\n", nes->rx_broadcast);
 912         printf("rx_discards:         %lu\n", nes->rx_discards);
 913         printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
 914         printf("tx_bytes:            %lu\n", nes->tx_bytes);
 915         printf("tx_unicast:          %lu\n", nes->tx_unicast);
 916         printf("tx_multicast:        %lu\n", nes->tx_multicast);
 917         printf("tx_broadcast:        %lu\n", nes->tx_broadcast);
 918         printf("tx_discards:         %lu\n", nes->tx_discards);
 919         printf("tx_errors:           %lu\n", nes->tx_errors);
 920         printf("***************** VSI[%u] stats end *******************\n",
 921                                                                 vsi->vsi_id);
 922 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
 923 }
 924
 925 /* Get all statistics of a port */
 926 static void
 927 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 928 {
 929         uint32_t i;
 930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
 933         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
 934
 935         /* Get statistics of struct i40e_eth_stats */
 936         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
 937                             I40E_GLPRT_GORCL(hw->port),
 938                             pf->offset_loaded, &os->eth.rx_bytes,
 939                             &ns->eth.rx_bytes);
 940         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
 941                             I40E_GLPRT_UPRCL(hw->port),
 942                             pf->offset_loaded, &os->eth.rx_unicast,
 943                             &ns->eth.rx_unicast);
 944         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
 945                             I40E_GLPRT_MPRCL(hw->port),
 946                             pf->offset_loaded, &os->eth.rx_multicast,
 947                             &ns->eth.rx_multicast);
 948         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
 949                             I40E_GLPRT_BPRCL(hw->port),
 950                             pf->offset_loaded, &os->eth.rx_broadcast,
 951                             &ns->eth.rx_broadcast);
 952         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
 953                             pf->offset_loaded, &os->eth.rx_discards,
 954                             &ns->eth.rx_discards);
 955         /* GLPRT_REPC not supported */
 956         /* GLPRT_RMPC not supported */
 957         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
 958                             pf->offset_loaded,
 959                             &os->eth.rx_unknown_protocol,
 960                             &ns->eth.rx_unknown_protocol);
 961         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
 962                             I40E_GLPRT_GOTCL(hw->port),
 963                             pf->offset_loaded, &os->eth.tx_bytes,
 964                             &ns->eth.tx_bytes);
 965         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
 966                             I40E_GLPRT_UPTCL(hw->port),
 967                             pf->offset_loaded, &os->eth.tx_unicast,
 968                             &ns->eth.tx_unicast);
 969         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
 970                             I40E_GLPRT_MPTCL(hw->port),
 971                             pf->offset_loaded, &os->eth.tx_multicast,
 972                             &ns->eth.tx_multicast);
 973         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
 974                             I40E_GLPRT_BPTCL(hw->port),
 975                             pf->offset_loaded, &os->eth.tx_broadcast,
 976                             &ns->eth.tx_broadcast);
 977         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
 978                             pf->offset_loaded, &os->eth.tx_discards,
 979                             &ns->eth.tx_discards);
 980         /* GLPRT_TEPC not supported */
 981
 982         /* additional port specific stats */
 983         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
 984                             pf->offset_loaded, &os->tx_dropped_link_down,
 985                             &ns->tx_dropped_link_down);
 986         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
 987                             pf->offset_loaded, &os->crc_errors,
 988                             &ns->crc_errors);
 989         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
 990                             pf->offset_loaded, &os->illegal_bytes,
 991                             &ns->illegal_bytes);
 992         /* GLPRT_ERRBC not supported */
 993         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
 994                             pf->offset_loaded, &os->mac_local_faults,
 995                             &ns->mac_local_faults);
 996         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
 997                             pf->offset_loaded, &os->mac_remote_faults,
 998                             &ns->mac_remote_faults);
 999         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1000                             pf->offset_loaded, &os->rx_length_errors,
1001                             &ns->rx_length_errors);
1002         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1003                             pf->offset_loaded, &os->link_xon_rx,
1004                             &ns->link_xon_rx);
1005         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1006                             pf->offset_loaded, &os->link_xoff_rx,
1007                             &ns->link_xoff_rx);
1008         for (i = 0; i < 8; i++) {
1009                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1010                                     pf->offset_loaded,
1011                                     &os->priority_xon_rx[i],
1012                                     &ns->priority_xon_rx[i]);
1013                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1014                                     pf->offset_loaded,
1015                                     &os->priority_xoff_rx[i],
1016                                     &ns->priority_xoff_rx[i]);
1017         }
1018         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1019                             pf->offset_loaded, &os->link_xon_tx,
1020                             &ns->link_xon_tx);
1021         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1022                             pf->offset_loaded, &os->link_xoff_tx,
1023                             &ns->link_xoff_tx);
1024         for (i = 0; i < 8; i++) {
1025                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1026                                     pf->offset_loaded,
1027                                     &os->priority_xon_tx[i],
1028                                     &ns->priority_xon_tx[i]);
1029                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1030                                     pf->offset_loaded,
1031                                     &os->priority_xoff_tx[i],
1032                                     &ns->priority_xoff_tx[i]);
1033                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1034                                     pf->offset_loaded,
1035                                     &os->priority_xon_2_xoff[i],
1036                                     &ns->priority_xon_2_xoff[i]);
1037         }
1038         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1039                             I40E_GLPRT_PRC64L(hw->port),
1040                             pf->offset_loaded, &os->rx_size_64,
1041                             &ns->rx_size_64);
1042         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1043                             I40E_GLPRT_PRC127L(hw->port),
1044                             pf->offset_loaded, &os->rx_size_127,
1045                             &ns->rx_size_127);
1046         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1047                             I40E_GLPRT_PRC255L(hw->port),
1048                             pf->offset_loaded, &os->rx_size_255,
1049                             &ns->rx_size_255);
1050         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1051                             I40E_GLPRT_PRC511L(hw->port),
1052                             pf->offset_loaded, &os->rx_size_511,
1053                             &ns->rx_size_511);
1054         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1055                             I40E_GLPRT_PRC1023L(hw->port),
1056                             pf->offset_loaded, &os->rx_size_1023,
1057                             &ns->rx_size_1023);
1058         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1059                             I40E_GLPRT_PRC1522L(hw->port),
1060                             pf->offset_loaded, &os->rx_size_1522,
1061                             &ns->rx_size_1522);
1062         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1063                             I40E_GLPRT_PRC9522L(hw->port),
1064                             pf->offset_loaded, &os->rx_size_big,
1065                             &ns->rx_size_big);
1066         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1067                             pf->offset_loaded, &os->rx_undersize,
1068                             &ns->rx_undersize);
1069         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1070                             pf->offset_loaded, &os->rx_fragments,
1071                             &ns->rx_fragments);
1072         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1073                             pf->offset_loaded, &os->rx_oversize,
1074                             &ns->rx_oversize);
1075         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1076                             pf->offset_loaded, &os->rx_jabber,
1077                             &ns->rx_jabber);
1078         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1079                             I40E_GLPRT_PTC64L(hw->port),
1080                             pf->offset_loaded, &os->tx_size_64,
1081                             &ns->tx_size_64);
1082         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1083                             I40E_GLPRT_PTC127L(hw->port),
1084                             pf->offset_loaded, &os->tx_size_127,
1085                             &ns->tx_size_127);
1086         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1087                             I40E_GLPRT_PTC255L(hw->port),
1088                             pf->offset_loaded, &os->tx_size_255,
1089                             &ns->tx_size_255);
1090         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1091                             I40E_GLPRT_PTC511L(hw->port),
1092                             pf->offset_loaded, &os->tx_size_511,
1093                             &ns->tx_size_511);
1094         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1095                             I40E_GLPRT_PTC1023L(hw->port),
1096                             pf->offset_loaded, &os->tx_size_1023,
1097                             &ns->tx_size_1023);
1098         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1099                             I40E_GLPRT_PTC1522L(hw->port),
1100                             pf->offset_loaded, &os->tx_size_1522,
1101                             &ns->tx_size_1522);
1102         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1103                             I40E_GLPRT_PTC9522L(hw->port),
1104                             pf->offset_loaded, &os->tx_size_big,
1105                             &ns->tx_size_big);
1106         /* GLPRT_MSPDC not supported */
1107         /* GLPRT_XEC not supported */
1108
1109         pf->offset_loaded = true;
1110
1111         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1112                                                 ns->eth.rx_broadcast;
1113         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1114                                                 ns->eth.tx_broadcast;
1115         stats->ibytes   = ns->eth.rx_bytes;
1116         stats->obytes   = ns->eth.tx_bytes;
1117         stats->oerrors  = ns->eth.tx_errors;
1118         stats->imcasts  = ns->eth.rx_multicast;
1119
1120         if (pf->main_vsi)
1121                 i40e_update_vsi_stats(pf->main_vsi);
1122
1123 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1124         printf("***************** PF stats start *******************\n");
1125         printf("rx_bytes:            %lu\n", ns->eth.rx_bytes);
1126         printf("rx_unicast:          %lu\n", ns->eth.rx_unicast);
1127         printf("rx_multicast:        %lu\n", ns->eth.rx_multicast);
1128         printf("rx_broadcast:        %lu\n", ns->eth.rx_broadcast);
1129         printf("rx_discards:         %lu\n", ns->eth.rx_discards);
1130         printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1131         printf("tx_bytes:            %lu\n", ns->eth.tx_bytes);
1132         printf("tx_unicast:          %lu\n", ns->eth.tx_unicast);
1133         printf("tx_multicast:        %lu\n", ns->eth.tx_multicast);
1134         printf("tx_broadcast:        %lu\n", ns->eth.tx_broadcast);
1135         printf("tx_discards:         %lu\n", ns->eth.tx_discards);
1136         printf("tx_errors:           %lu\n", ns->eth.tx_errors);
1137
1138         printf("tx_dropped_link_down:     %lu\n", ns->tx_dropped_link_down);
1139         printf("crc_errors:               %lu\n", ns->crc_errors);
1140         printf("illegal_bytes:            %lu\n", ns->illegal_bytes);
1141         printf("error_bytes:              %lu\n", ns->error_bytes);
1142         printf("mac_local_faults:         %lu\n", ns->mac_local_faults);
1143         printf("mac_remote_faults:        %lu\n", ns->mac_remote_faults);
1144         printf("rx_length_errors:         %lu\n", ns->rx_length_errors);
1145         printf("link_xon_rx:              %lu\n", ns->link_xon_rx);
1146         printf("link_xoff_rx:             %lu\n", ns->link_xoff_rx);
1147         for (i = 0; i < 8; i++) {
1148                 printf("priority_xon_rx[%d]:      %lu\n",
1149                                 i, ns->priority_xon_rx[i]);
1150                 printf("priority_xoff_rx[%d]:     %lu\n",
1151                                 i, ns->priority_xoff_rx[i]);
1152         }
1153         printf("link_xon_tx:              %lu\n", ns->link_xon_tx);
1154         printf("link_xoff_tx:             %lu\n", ns->link_xoff_tx);
1155         for (i = 0; i < 8; i++) {
1156                 printf("priority_xon_tx[%d]:      %lu\n",
1157                                 i, ns->priority_xon_tx[i]);
1158                 printf("priority_xoff_tx[%d]:     %lu\n",
1159                                 i, ns->priority_xoff_tx[i]);
1160                 printf("priority_xon_2_xoff[%d]:  %lu\n",
1161                                 i, ns->priority_xon_2_xoff[i]);
1162         }
1163         printf("rx_size_64:               %lu\n", ns->rx_size_64);
1164         printf("rx_size_127:              %lu\n", ns->rx_size_127);
1165         printf("rx_size_255:              %lu\n", ns->rx_size_255);
1166         printf("rx_size_511:              %lu\n", ns->rx_size_511);
1167         printf("rx_size_1023:             %lu\n", ns->rx_size_1023);
1168         printf("rx_size_1522:             %lu\n", ns->rx_size_1522);
1169         printf("rx_size_big:              %lu\n", ns->rx_size_big);
1170         printf("rx_undersize:             %lu\n", ns->rx_undersize);
1171         printf("rx_fragments:             %lu\n", ns->rx_fragments);
1172         printf("rx_oversize:              %lu\n", ns->rx_oversize);
1173         printf("rx_jabber:                %lu\n", ns->rx_jabber);
1174         printf("tx_size_64:               %lu\n", ns->tx_size_64);
1175         printf("tx_size_127:              %lu\n", ns->tx_size_127);
1176         printf("tx_size_255:              %lu\n", ns->tx_size_255);
1177         printf("tx_size_511:              %lu\n", ns->tx_size_511);
1178         printf("tx_size_1023:             %lu\n", ns->tx_size_1023);
1179         printf("tx_size_1522:             %lu\n", ns->tx_size_1522);
1180         printf("tx_size_big:              %lu\n", ns->tx_size_big);
1181         printf("mac_short_packet_dropped: %lu\n",
1182                         ns->mac_short_packet_dropped);
1183         printf("checksum_error:           %lu\n", ns->checksum_error);
1184         printf("***************** PF stats end ********************\n");
1185 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1186 }
1187
1188 /* Reset the statistics */
1189 static void
1190 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1191 {
1192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1193
1194         /* It results in reloading the start point of each counter */
1195         pf->offset_loaded = false;
1196 }
1197
1198 static int
1199 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1200                                  __rte_unused uint16_t queue_id,
1201                                  __rte_unused uint8_t stat_idx,
1202                                  __rte_unused uint8_t is_rx)
1203 {
1204         PMD_INIT_FUNC_TRACE();
1205
1206         return -ENOSYS;
1207 }
1208
1209 static void
1210 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1211 {
1212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1213         struct i40e_vsi *vsi = pf->main_vsi;
1214
1215         dev_info->max_rx_queues = vsi->nb_qps;
1216         dev_info->max_tx_queues = vsi->nb_qps;
1217         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1218         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1219         dev_info->max_mac_addrs = vsi->max_macaddrs;
1220         dev_info->max_vfs = dev->pci_dev->max_vfs;
1221         dev_info->rx_offload_capa =
1222                 DEV_RX_OFFLOAD_VLAN_STRIP |
1223                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1224                 DEV_RX_OFFLOAD_UDP_CKSUM |
1225                 DEV_RX_OFFLOAD_TCP_CKSUM;
1226         dev_info->tx_offload_capa =
1227                 DEV_TX_OFFLOAD_VLAN_INSERT |
1228                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1229                 DEV_TX_OFFLOAD_UDP_CKSUM |
1230                 DEV_TX_OFFLOAD_TCP_CKSUM |
1231                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1232 }
1233
1234 static int
1235 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1236 {
1237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1238         struct i40e_vsi *vsi = pf->main_vsi;
1239         PMD_INIT_FUNC_TRACE();
1240
1241         if (on)
1242                 return i40e_vsi_add_vlan(vsi, vlan_id);
1243         else
1244                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1245 }
1246
1247 static void
1248 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1249                    __rte_unused uint16_t tpid)
1250 {
1251         PMD_INIT_FUNC_TRACE();
1252 }
1253
1254 static void
1255 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1256 {
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         struct i40e_vsi *vsi = pf->main_vsi;
1259
1260         if (mask & ETH_VLAN_STRIP_MASK) {
1261                 /* Enable or disable VLAN stripping */
1262                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1263                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1264                 else
1265                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1266         }
1267
1268         if (mask & ETH_VLAN_EXTEND_MASK) {
1269                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1270                         i40e_vsi_config_double_vlan(vsi, TRUE);
1271                 else
1272                         i40e_vsi_config_double_vlan(vsi, FALSE);
1273         }
1274 }
1275
1276 static void
1277 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1278                           __rte_unused uint16_t queue,
1279                           __rte_unused int on)
1280 {
1281         PMD_INIT_FUNC_TRACE();
1282 }
1283
1284 static int
1285 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1286 {
1287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1288         struct i40e_vsi *vsi = pf->main_vsi;
1289         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1290         struct i40e_vsi_vlan_pvid_info info;
1291
1292         memset(&info, 0, sizeof(info));
1293         info.on = on;
1294         if (info.on)
1295                 info.config.pvid = pvid;
1296         else {
1297                 info.config.reject.tagged =
1298                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1299                 info.config.reject.untagged =
1300                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1301         }
1302
1303         return i40e_vsi_vlan_pvid_set(vsi, &info);
1304 }
1305
1306 static int
1307 i40e_dev_led_on(struct rte_eth_dev *dev)
1308 {
1309         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         uint32_t mode = i40e_led_get(hw);
1311
1312         if (mode == 0)
1313                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1314
1315         return 0;
1316 }
1317
1318 static int
1319 i40e_dev_led_off(struct rte_eth_dev *dev)
1320 {
1321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t mode = i40e_led_get(hw);
1323
1324         if (mode != 0)
1325                 i40e_led_set(hw, 0, false);
1326
1327         return 0;
1328 }
1329
1330 static int
1331 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1332                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1333 {
1334         PMD_INIT_FUNC_TRACE();
1335
1336         return -ENOSYS;
1337 }
1338
1339 static int
1340 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1341                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1342 {
1343         PMD_INIT_FUNC_TRACE();
1344
1345         return -ENOSYS;
1346 }
1347
1348 /* Add a MAC address, and update filters */
1349 static void
1350 i40e_macaddr_add(struct rte_eth_dev *dev,
1351                  struct ether_addr *mac_addr,
1352                  __attribute__((unused)) uint32_t index,
1353                  __attribute__((unused)) uint32_t pool)
1354 {
1355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357         struct i40e_vsi *vsi = pf->main_vsi;
1358         struct ether_addr old_mac;
1359         int ret;
1360
1361         if (!is_valid_assigned_ether_addr(mac_addr)) {
1362                 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1363                 return;
1364         }
1365
1366         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1367                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1368                 return;
1369         }
1370
1371         /* Write mac address */
1372         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1373                                         mac_addr->addr_bytes, NULL);
1374         if (ret != I40E_SUCCESS) {
1375                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1376                 return;
1377         }
1378
1379         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1380         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1381                         ETHER_ADDR_LEN);
1382
1383         ret = i40e_vsi_add_mac(vsi, mac_addr);
1384         if (ret != I40E_SUCCESS) {
1385                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1386                 return;
1387         }
1388
1389         ether_addr_copy(mac_addr, &pf->dev_addr);
1390         i40e_vsi_delete_mac(vsi, &old_mac);
1391 }
1392
1393 /* Remove a MAC address, and update filters */
1394 static void
1395 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1396 {
1397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1398         struct i40e_vsi *vsi = pf->main_vsi;
1399         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1400         struct ether_addr *macaddr;
1401         int ret;
1402         struct i40e_hw *hw =
1403                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1404
1405         if (index >= vsi->max_macaddrs)
1406                 return;
1407
1408         macaddr = &(data->mac_addrs[index]);
1409         if (!is_valid_assigned_ether_addr(macaddr))
1410                 return;
1411
1412         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1413                                         hw->mac.perm_addr, NULL);
1414         if (ret != I40E_SUCCESS) {
1415                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1416                 return;
1417         }
1418
1419         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1420
1421         ret = i40e_vsi_delete_mac(vsi, macaddr);
1422         if (ret != I40E_SUCCESS)
1423                 return;
1424
1425         /* Clear device address as it has been removed */
1426         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1427                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1428 }
1429
1430 static int
1431 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1432                          struct rte_eth_rss_reta *reta_conf)
1433 {
1434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435         uint32_t lut, l;
1436         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1437
1438         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1439                 if (i < max)
1440                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1441                 else
1442                         mask = (uint8_t)((reta_conf->mask_hi >>
1443                                                 (i - max)) & 0xF);
1444
1445                 if (!mask)
1446                         continue;
1447
1448                 if (mask == 0xF)
1449                         l = 0;
1450                 else
1451                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1452
1453                 for (j = 0, lut = 0; j < 4; j++) {
1454                         if (mask & (0x1 << j))
1455                                 lut |= reta_conf->reta[i + j] << (8 * j);
1456                         else
1457                                 lut |= l & (0xFF << (8 * j));
1458                 }
1459                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1460         }
1461
1462         return 0;
1463 }
1464
1465 static int
1466 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1467                         struct rte_eth_rss_reta *reta_conf)
1468 {
1469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470         uint32_t lut;
1471         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1472
1473         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1474                 if (i < max)
1475                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1476                 else
1477                         mask = (uint8_t)((reta_conf->mask_hi >>
1478                                                 (i - max)) & 0xF);
1479
1480                 if (!mask)
1481                         continue;
1482
1483                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1484                 for (j = 0; j < 4; j++) {
1485                         if (mask & (0x1 << j))
1486                                 reta_conf->reta[i + j] =
1487                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1488                 }
1489         }
1490
1491         return 0;
1492 }
1493
1494 /**
1495  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1496  * @hw:   pointer to the HW structure
1497  * @mem:  pointer to mem struct to fill out
1498  * @size: size of memory requested
1499  * @alignment: what to align the allocation to
1500  **/
1501 enum i40e_status_code
1502 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1503                         struct i40e_dma_mem *mem,
1504                         u64 size,
1505                         u32 alignment)
1506 {
1507         static uint64_t id = 0;
1508         const struct rte_memzone *mz = NULL;
1509         char z_name[RTE_MEMZONE_NAMESIZE];
1510
1511         if (!mem)
1512                 return I40E_ERR_PARAM;
1513
1514         id++;
1515         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1516         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1517         if (!mz)
1518                 return I40E_ERR_NO_MEMORY;
1519
1520         mem->id = id;
1521         mem->size = size;
1522         mem->va = mz->addr;
1523         mem->pa = mz->phys_addr;
1524
1525         return I40E_SUCCESS;
1526 }
1527
1528 /**
1529  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1530  * @hw:   pointer to the HW structure
1531  * @mem:  ptr to mem struct to free
1532  **/
1533 enum i40e_status_code
1534 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1535                     struct i40e_dma_mem *mem)
1536 {
1537         if (!mem || !mem->va)
1538                 return I40E_ERR_PARAM;
1539
1540         mem->va = NULL;
1541         mem->pa = (u64)0;
1542
1543         return I40E_SUCCESS;
1544 }
1545
1546 /**
1547  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1548  * @hw:   pointer to the HW structure
1549  * @mem:  pointer to mem struct to fill out
1550  * @size: size of memory requested
1551  **/
1552 enum i40e_status_code
1553 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1554                          struct i40e_virt_mem *mem,
1555                          u32 size)
1556 {
1557         if (!mem)
1558                 return I40E_ERR_PARAM;
1559
1560         mem->size = size;
1561         mem->va = rte_zmalloc("i40e", size, 0);
1562
1563         if (mem->va)
1564                 return I40E_SUCCESS;
1565         else
1566                 return I40E_ERR_NO_MEMORY;
1567 }
1568
1569 /**
1570  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1571  * @hw:   pointer to the HW structure
1572  * @mem:  pointer to mem struct to free
1573  **/
1574 enum i40e_status_code
1575 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1576                      struct i40e_virt_mem *mem)
1577 {
1578         if (!mem)
1579                 return I40E_ERR_PARAM;
1580
1581         rte_free(mem->va);
1582         mem->va = NULL;
1583
1584         return I40E_SUCCESS;
1585 }
1586
1587 void
1588 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1589 {
1590         rte_spinlock_init(&sp->spinlock);
1591 }
1592
1593 void
1594 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1595 {
1596         rte_spinlock_lock(&sp->spinlock);
1597 }
1598
1599 void
1600 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1601 {
1602         rte_spinlock_unlock(&sp->spinlock);
1603 }
1604
1605 void
1606 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1607 {
1608         return;
1609 }
1610
1611 /**
1612  * Get the hardware capabilities, which will be parsed
1613  * and saved into struct i40e_hw.
1614  */
1615 static int
1616 i40e_get_cap(struct i40e_hw *hw)
1617 {
1618         struct i40e_aqc_list_capabilities_element_resp *buf;
1619         uint16_t len, size = 0;
1620         int ret;
1621
1622         /* Calculate a huge enough buff for saving response data temporarily */
1623         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1624                                                 I40E_MAX_CAP_ELE_NUM;
1625         buf = rte_zmalloc("i40e", len, 0);
1626         if (!buf) {
1627                 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1628                 return I40E_ERR_NO_MEMORY;
1629         }
1630
1631         /* Get, parse the capabilities and save it to hw */
1632         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1633                         i40e_aqc_opc_list_func_capabilities, NULL);
1634         if (ret != I40E_SUCCESS)
1635                 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1636
1637         /* Free the temporary buffer after being used */
1638         rte_free(buf);
1639
1640         return ret;
1641 }
1642
1643 static int
1644 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1647         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1648         uint16_t sum_queues = 0, sum_vsis;
1649
1650         /* First check if FW support SRIOV */
1651         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1652                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1653                 return -EINVAL;
1654         }
1655
1656         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1657         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1658         PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1659         /* Allocate queues for pf */
1660         if (hw->func_caps.rss) {
1661                 pf->flags |= I40E_FLAG_RSS;
1662                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1663                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1664                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1665         } else
1666                 pf->lan_nb_qps = 1;
1667         sum_queues = pf->lan_nb_qps;
1668         /* Default VSI is not counted in */
1669         sum_vsis = 0;
1670         PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1671
1672         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1673                 pf->flags |= I40E_FLAG_SRIOV;
1674                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1675                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1676                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1677                                 "max supported %u.\n", dev->pci_dev->max_vfs,
1678                                                 hw->func_caps.num_vfs);
1679                         return -EINVAL;
1680                 }
1681                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1682                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1683                                 "max support %u queues.\n", pf->vf_nb_qps,
1684                                                 I40E_MAX_QP_NUM_PER_VF);
1685                         return -EINVAL;
1686                 }
1687                 pf->vf_num = dev->pci_dev->max_vfs;
1688                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1689                 sum_vsis   += pf->vf_num;
1690                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1691                                                 pf->vf_num, pf->vf_nb_qps);
1692         } else
1693                 pf->vf_num = 0;
1694
1695         if (hw->func_caps.vmdq) {
1696                 pf->flags |= I40E_FLAG_VMDQ;
1697                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1698                 sum_queues += pf->vmdq_nb_qps;
1699                 sum_vsis += 1;
1700                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1701         }
1702
1703         if (hw->func_caps.fd) {
1704                 pf->flags |= I40E_FLAG_FDIR;
1705                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1706                 /**
1707                  * Each flow director consumes one VSI and one queue,
1708                  * but can't calculate out predictably here.
1709                  */
1710         }
1711
1712         if (sum_vsis > pf->max_num_vsi ||
1713                 sum_queues > hw->func_caps.num_rx_qp) {
1714                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1715                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1716                                 pf->max_num_vsi, sum_vsis);
1717                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1718                                 hw->func_caps.num_rx_qp, sum_queues);
1719                 return -EINVAL;
1720         }
1721
1722         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1723         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1724                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1725                                 sum_vsis, hw->func_caps.num_msix_vectors);
1726                 return -EINVAL;
1727         }
1728         return I40E_SUCCESS;
1729 }
1730
1731 static int
1732 i40e_pf_get_switch_config(struct i40e_pf *pf)
1733 {
1734         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1735         struct i40e_aqc_get_switch_config_resp *switch_config;
1736         struct i40e_aqc_switch_config_element_resp *element;
1737         uint16_t start_seid = 0, num_reported;
1738         int ret;
1739
1740         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1741                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1742         if (!switch_config) {
1743                 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1744                 return -ENOMEM;
1745         }
1746
1747         /* Get the switch configurations */
1748         ret = i40e_aq_get_switch_config(hw, switch_config,
1749                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1750         if (ret != I40E_SUCCESS) {
1751                 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1752                 goto fail;
1753         }
1754         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1755         if (num_reported != 1) { /* The number should be 1 */
1756                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1757                 goto fail;
1758         }
1759
1760         /* Parse the switch configuration elements */
1761         element = &(switch_config->element[0]);
1762         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1763                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1764                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1765         } else
1766                 PMD_DRV_LOG(INFO, "Unknown element type\n");
1767
1768 fail:
1769         rte_free(switch_config);
1770
1771         return ret;
1772 }
1773
1774 static int
1775 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1776                         uint32_t num)
1777 {
1778         struct pool_entry *entry;
1779
1780         if (pool == NULL || num == 0)
1781                 return -EINVAL;
1782
1783         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1784         if (entry == NULL) {
1785                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1786                                                 "resource pool\n");
1787                 return -ENOMEM;
1788         }
1789
1790         /* queue heap initialize */
1791         pool->num_free = num;
1792         pool->num_alloc = 0;
1793         pool->base = base;
1794         LIST_INIT(&pool->alloc_list);
1795         LIST_INIT(&pool->free_list);
1796
1797         /* Initialize element  */
1798         entry->base = 0;
1799         entry->len = num;
1800
1801         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1802         return 0;
1803 }
1804
1805 static void
1806 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1807 {
1808         struct pool_entry *entry;
1809
1810         if (pool == NULL)
1811                 return;
1812
1813         LIST_FOREACH(entry, &pool->alloc_list, next) {
1814                 LIST_REMOVE(entry, next);
1815                 rte_free(entry);
1816         }
1817
1818         LIST_FOREACH(entry, &pool->free_list, next) {
1819                 LIST_REMOVE(entry, next);
1820                 rte_free(entry);
1821         }
1822
1823         pool->num_free = 0;
1824         pool->num_alloc = 0;
1825         pool->base = 0;
1826         LIST_INIT(&pool->alloc_list);
1827         LIST_INIT(&pool->free_list);
1828 }
1829
1830 static int
1831 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1832                        uint32_t base)
1833 {
1834         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
1835         uint32_t pool_offset;
1836         int insert;
1837
1838         if (pool == NULL) {
1839                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1840                 return -EINVAL;
1841         }
1842
1843         pool_offset = base - pool->base;
1844         /* Lookup in alloc list */
1845         LIST_FOREACH(entry, &pool->alloc_list, next) {
1846                 if (entry->base == pool_offset) {
1847                         valid_entry = entry;
1848                         LIST_REMOVE(entry, next);
1849                         break;
1850                 }
1851         }
1852
1853         /* Not find, return */
1854         if (valid_entry == NULL) {
1855                 PMD_DRV_LOG(ERR, "Failed to find entry\n");
1856                 return -EINVAL;
1857         }
1858
1859         /**
1860          * Found it, move it to free list  and try to merge.
1861          * In order to make merge easier, always sort it by qbase.
1862          * Find adjacent prev and last entries.
1863          */
1864         prev = next = NULL;
1865         LIST_FOREACH(entry, &pool->free_list, next) {
1866                 if (entry->base > valid_entry->base) {
1867                         next = entry;
1868                         break;
1869                 }
1870                 prev = entry;
1871         }
1872
1873         insert = 0;
1874         /* Try to merge with next one*/
1875         if (next != NULL) {
1876                 /* Merge with next one */
1877                 if (valid_entry->base + valid_entry->len == next->base) {
1878                         next->base = valid_entry->base;
1879                         next->len += valid_entry->len;
1880                         rte_free(valid_entry);
1881                         valid_entry = next;
1882                         insert = 1;
1883                 }
1884         }
1885
1886         if (prev != NULL) {
1887                 /* Merge with previous one */
1888                 if (prev->base + prev->len == valid_entry->base) {
1889                         prev->len += valid_entry->len;
1890                         /* If it merge with next one, remove next node */
1891                         if (insert == 1) {
1892                                 LIST_REMOVE(valid_entry, next);
1893                                 rte_free(valid_entry);
1894                         } else {
1895                                 rte_free(valid_entry);
1896                                 insert = 1;
1897                         }
1898                 }
1899         }
1900
1901         /* Not find any entry to merge, insert */
1902         if (insert == 0) {
1903                 if (prev != NULL)
1904                         LIST_INSERT_AFTER(prev, valid_entry, next);
1905                 else if (next != NULL)
1906                         LIST_INSERT_BEFORE(next, valid_entry, next);
1907                 else /* It's empty list, insert to head */
1908                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
1909         }
1910
1911         pool->num_free += valid_entry->len;
1912         pool->num_alloc -= valid_entry->len;
1913
1914         return 0;
1915 }
1916
1917 static int
1918 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
1919                        uint16_t num)
1920 {
1921         struct pool_entry *entry, *valid_entry;
1922
1923         if (pool == NULL || num == 0) {
1924                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1925                 return -EINVAL;
1926         }
1927
1928         if (pool->num_free < num) {
1929                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
1930                                 num, pool->num_free);
1931                 return -ENOMEM;
1932         }
1933
1934         valid_entry = NULL;
1935         /* Lookup  in free list and find most fit one */
1936         LIST_FOREACH(entry, &pool->free_list, next) {
1937                 if (entry->len >= num) {
1938                         /* Find best one */
1939                         if (entry->len == num) {
1940                                 valid_entry = entry;
1941                                 break;
1942                         }
1943                         if (valid_entry == NULL || valid_entry->len > entry->len)
1944                                 valid_entry = entry;
1945                 }
1946         }
1947
1948         /* Not find one to satisfy the request, return */
1949         if (valid_entry == NULL) {
1950                 PMD_DRV_LOG(ERR, "No valid entry found\n");
1951                 return -ENOMEM;
1952         }
1953         /**
1954          * The entry have equal queue number as requested,
1955          * remove it from alloc_list.
1956          */
1957         if (valid_entry->len == num) {
1958                 LIST_REMOVE(valid_entry, next);
1959         } else {
1960                 /**
1961                  * The entry have more numbers than requested,
1962                  * create a new entry for alloc_list and minus its
1963                  * queue base and number in free_list.
1964                  */
1965                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
1966                 if (entry == NULL) {
1967                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1968                                         "resource pool\n");
1969                         return -ENOMEM;
1970                 }
1971                 entry->base = valid_entry->base;
1972                 entry->len = num;
1973                 valid_entry->base += num;
1974                 valid_entry->len -= num;
1975                 valid_entry = entry;
1976         }
1977
1978         /* Insert it into alloc list, not sorted */
1979         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
1980
1981         pool->num_free -= valid_entry->len;
1982         pool->num_alloc += valid_entry->len;
1983
1984         return (valid_entry->base + pool->base);
1985 }
1986
1987 /**
1988  * bitmap_is_subset - Check whether src2 is subset of src1
1989  **/
1990 static inline int
1991 bitmap_is_subset(uint8_t src1, uint8_t src2)
1992 {
1993         return !((src1 ^ src2) & src2);
1994 }
1995
1996 static int
1997 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
1998 {
1999         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2000
2001         /* If DCB is not supported, only default TC is supported */
2002         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2003                 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2004                                 "only TC0 is supported\n");
2005                 return -EINVAL;
2006         }
2007
2008         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2009                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2010                         "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2011                                                         enabled_tcmap);
2012                 return -EINVAL;
2013         }
2014         return I40E_SUCCESS;
2015 }
2016
2017 int
2018 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2019                                 struct i40e_vsi_vlan_pvid_info *info)
2020 {
2021         struct i40e_hw *hw;
2022         struct i40e_vsi_context ctxt;
2023         uint8_t vlan_flags = 0;
2024         int ret;
2025
2026         if (vsi == NULL || info == NULL) {
2027                 PMD_DRV_LOG(ERR, "invalid parameters\n");
2028                 return I40E_ERR_PARAM;
2029         }
2030
2031         if (info->on) {
2032                 vsi->info.pvid = info->config.pvid;
2033                 /**
2034                  * If insert pvid is enabled, only tagged pkts are
2035                  * allowed to be sent out.
2036                  */
2037                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2038                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2039         } else {
2040                 vsi->info.pvid = 0;
2041                 if (info->config.reject.tagged == 0)
2042                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2043
2044                 if (info->config.reject.untagged == 0)
2045                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2046         }
2047         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2048                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2049         vsi->info.port_vlan_flags |= vlan_flags;
2050         vsi->info.valid_sections =
2051                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2052         memset(&ctxt, 0, sizeof(ctxt));
2053         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2054         ctxt.seid = vsi->seid;
2055
2056         hw = I40E_VSI_TO_HW(vsi);
2057         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2058         if (ret != I40E_SUCCESS)
2059                 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2060
2061         return ret;
2062 }
2063
2064 static int
2065 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2066 {
2067         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2068         int i, ret;
2069         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2070
2071         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2072         if (ret != I40E_SUCCESS)
2073                 return ret;
2074
2075         if (!vsi->seid) {
2076                 PMD_DRV_LOG(ERR, "seid not valid\n");
2077                 return -EINVAL;
2078         }
2079
2080         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2081         tc_bw_data.tc_valid_bits = enabled_tcmap;
2082         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2083                 tc_bw_data.tc_bw_credits[i] =
2084                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2085
2086         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2087         if (ret != I40E_SUCCESS) {
2088                 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2089                 return ret;
2090         }
2091
2092         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2093                                         sizeof(vsi->info.qs_handle));
2094         return I40E_SUCCESS;
2095 }
2096
2097 static int
2098 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2099                                  struct i40e_aqc_vsi_properties_data *info,
2100                                  uint8_t enabled_tcmap)
2101 {
2102         int ret, total_tc = 0, i;
2103         uint16_t qpnum_per_tc, bsf, qp_idx;
2104
2105         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2106         if (ret != I40E_SUCCESS)
2107                 return ret;
2108
2109         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2110                 if (enabled_tcmap & (1 << i))
2111                         total_tc++;
2112         vsi->enabled_tc = enabled_tcmap;
2113
2114         /* Number of queues per enabled TC */
2115         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2116         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2117         bsf = rte_bsf32(qpnum_per_tc);
2118
2119         /* Adjust the queue number to actual queues that can be applied */
2120         vsi->nb_qps = qpnum_per_tc * total_tc;
2121
2122         /**
2123          * Configure TC and queue mapping parameters, for enabled TC,
2124          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2125          * default queue will serve it.
2126          */
2127         qp_idx = 0;
2128         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2129                 if (vsi->enabled_tc & (1 << i)) {
2130                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2131                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2132                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2133                         qp_idx += qpnum_per_tc;
2134                 } else
2135                         info->tc_mapping[i] = 0;
2136         }
2137
2138         /* Associate queue number with VSI */
2139         if (vsi->type == I40E_VSI_SRIOV) {
2140                 info->mapping_flags |=
2141                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2142                 for (i = 0; i < vsi->nb_qps; i++)
2143                         info->queue_mapping[i] =
2144                                 rte_cpu_to_le_16(vsi->base_queue + i);
2145         } else {
2146                 info->mapping_flags |=
2147                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2148                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2149         }
2150         info->valid_sections =
2151                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2152
2153         return I40E_SUCCESS;
2154 }
2155
2156 static int
2157 i40e_veb_release(struct i40e_veb *veb)
2158 {
2159         struct i40e_vsi *vsi;
2160         struct i40e_hw *hw;
2161
2162         if (veb == NULL || veb->associate_vsi == NULL)
2163                 return -EINVAL;
2164
2165         if (!TAILQ_EMPTY(&veb->head)) {
2166                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2167                 return -EACCES;
2168         }
2169
2170         vsi = veb->associate_vsi;
2171         hw = I40E_VSI_TO_HW(vsi);
2172
2173         vsi->uplink_seid = veb->uplink_seid;
2174         i40e_aq_delete_element(hw, veb->seid, NULL);
2175         rte_free(veb);
2176         vsi->veb = NULL;
2177         return I40E_SUCCESS;
2178 }
2179
2180 /* Setup a veb */
2181 static struct i40e_veb *
2182 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2183 {
2184         struct i40e_veb *veb;
2185         int ret;
2186         struct i40e_hw *hw;
2187
2188         if (NULL == pf || vsi == NULL) {
2189                 PMD_DRV_LOG(ERR, "veb setup failed, "
2190                         "associated VSI shouldn't null\n");
2191                 return NULL;
2192         }
2193         hw = I40E_PF_TO_HW(pf);
2194
2195         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2196         if (!veb) {
2197                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2198                 goto fail;
2199         }
2200
2201         veb->associate_vsi = vsi;
2202         TAILQ_INIT(&veb->head);
2203         veb->uplink_seid = vsi->uplink_seid;
2204
2205         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2206                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2207
2208         if (ret != I40E_SUCCESS) {
2209                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2210                                         hw->aq.asq_last_status);
2211                 goto fail;
2212         }
2213
2214         /* get statistics index */
2215         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2216                                 &veb->stats_idx, NULL, NULL, NULL);
2217         if (ret != I40E_SUCCESS) {
2218                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2219                                                 hw->aq.asq_last_status);
2220                 goto fail;
2221         }
2222
2223         /* Get VEB bandwidth, to be implemented */
2224         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2225         vsi->uplink_seid = veb->seid;
2226
2227         return veb;
2228 fail:
2229         rte_free(veb);
2230         return NULL;
2231 }
2232
2233 int
2234 i40e_vsi_release(struct i40e_vsi *vsi)
2235 {
2236         struct i40e_pf *pf;
2237         struct i40e_hw *hw;
2238         struct i40e_vsi_list *vsi_list;
2239         int ret;
2240         struct i40e_mac_filter *f;
2241
2242         if (!vsi)
2243                 return I40E_SUCCESS;
2244
2245         pf = I40E_VSI_TO_PF(vsi);
2246         hw = I40E_VSI_TO_HW(vsi);
2247
2248         /* VSI has child to attach, release child first */
2249         if (vsi->veb) {
2250                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2251                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2252                                 return -1;
2253                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2254                 }
2255                 i40e_veb_release(vsi->veb);
2256         }
2257
2258         /* Remove all macvlan filters of the VSI */
2259         i40e_vsi_remove_all_macvlan_filter(vsi);
2260         TAILQ_FOREACH(f, &vsi->mac_list, next)
2261                 rte_free(f);
2262
2263         if (vsi->type != I40E_VSI_MAIN) {
2264                 /* Remove vsi from parent's sibling list */
2265                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2266                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2267                         return I40E_ERR_PARAM;
2268                 }
2269                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2270                                 &vsi->sib_vsi_list, list);
2271
2272                 /* Remove all switch element of the VSI */
2273                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2274                 if (ret != I40E_SUCCESS)
2275                         PMD_DRV_LOG(ERR, "Failed to delete element\n");
2276         }
2277         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2278
2279         if (vsi->type != I40E_VSI_SRIOV)
2280                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2281         rte_free(vsi);
2282
2283         return I40E_SUCCESS;
2284 }
2285
2286 static int
2287 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2288 {
2289         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2290         struct i40e_aqc_remove_macvlan_element_data def_filter;
2291         int ret;
2292
2293         if (vsi->type != I40E_VSI_MAIN)
2294                 return I40E_ERR_CONFIG;
2295         memset(&def_filter, 0, sizeof(def_filter));
2296         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2297                                         ETH_ADDR_LEN);
2298         def_filter.vlan_tag = 0;
2299         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2300                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2301         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2302         if (ret != I40E_SUCCESS) {
2303                 struct i40e_mac_filter *f;
2304
2305                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2306                                                 "macvlan filter\n");
2307                 /* It needs to add the permanent mac into mac list */
2308                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2309                 if (f == NULL) {
2310                         PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2311                         return I40E_ERR_NO_MEMORY;
2312                 }
2313                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2314                                 ETH_ADDR_LEN);
2315                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2316                 vsi->mac_num++;
2317
2318                 return ret;
2319         }
2320
2321         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2322 }
2323
2324 static int
2325 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2326 {
2327         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2328         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2329         struct i40e_hw *hw = &vsi->adapter->hw;
2330         i40e_status ret;
2331         int i;
2332
2333         memset(&bw_config, 0, sizeof(bw_config));
2334         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2335         if (ret != I40E_SUCCESS) {
2336                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2337                         "configuration %u\n", hw->aq.asq_last_status);
2338                 return ret;
2339         }
2340
2341         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2342         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2343                                         &ets_sla_config, NULL);
2344         if (ret != I40E_SUCCESS) {
2345                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2346                         "configuration %u\n", hw->aq.asq_last_status);
2347                 return ret;
2348         }
2349
2350         /* Not store the info yet, just print out */
2351         PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2352         PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2353         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2354                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2355                                         ets_sla_config.share_credits[i]);
2356                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2357                         rte_le_to_cpu_16(ets_sla_config.credits[i]));
2358                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2359                         rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2360                                                                 (i * 4));
2361         }
2362
2363         return 0;
2364 }
2365
2366 /* Setup a VSI */
2367 struct i40e_vsi *
2368 i40e_vsi_setup(struct i40e_pf *pf,
2369                enum i40e_vsi_type type,
2370                struct i40e_vsi *uplink_vsi,
2371                uint16_t user_param)
2372 {
2373         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2374         struct i40e_vsi *vsi;
2375         int ret;
2376         struct i40e_vsi_context ctxt;
2377         struct ether_addr broadcast =
2378                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2379
2380         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2381                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2382                         "VSI link shouldn't be NULL\n");
2383                 return NULL;
2384         }
2385
2386         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2387                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2388                                 "uplink VSI should be NULL\n");
2389                 return NULL;
2390         }
2391
2392         /* If uplink vsi didn't setup VEB, create one first */
2393         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2394                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2395
2396                 if (NULL == uplink_vsi->veb) {
2397                         PMD_DRV_LOG(ERR, "VEB setup failed\n");
2398                         return NULL;
2399                 }
2400         }
2401
2402         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2403         if (!vsi) {
2404                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2405                 return NULL;
2406         }
2407         TAILQ_INIT(&vsi->mac_list);
2408         vsi->type = type;
2409         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2410         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2411         vsi->parent_vsi = uplink_vsi;
2412         vsi->user_param = user_param;
2413         /* Allocate queues */
2414         switch (vsi->type) {
2415         case I40E_VSI_MAIN  :
2416                 vsi->nb_qps = pf->lan_nb_qps;
2417                 break;
2418         case I40E_VSI_SRIOV :
2419                 vsi->nb_qps = pf->vf_nb_qps;
2420                 break;
2421         default:
2422                 goto fail_mem;
2423         }
2424         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2425         if (ret < 0) {
2426                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2427                                 vsi->seid, ret);
2428                 goto fail_mem;
2429         }
2430         vsi->base_queue = ret;
2431
2432         /* VF has MSIX interrupt in VF range, don't allocate here */
2433         if (type != I40E_VSI_SRIOV) {
2434                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2435                 if (ret < 0) {
2436                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2437                         goto fail_queue_alloc;
2438                 }
2439                 vsi->msix_intr = ret;
2440         } else
2441                 vsi->msix_intr = 0;
2442         /* Add VSI */
2443         if (type == I40E_VSI_MAIN) {
2444                 /* For main VSI, no need to add since it's default one */
2445                 vsi->uplink_seid = pf->mac_seid;
2446                 vsi->seid = pf->main_vsi_seid;
2447                 /* Bind queues with specific MSIX interrupt */
2448                 /**
2449                  * Needs 2 interrupt at least, one for misc cause which will
2450                  * enabled from OS side, Another for queues binding the
2451                  * interrupt from device side only.
2452                  */
2453
2454                 /* Get default VSI parameters from hardware */
2455                 memset(&ctxt, 0, sizeof(ctxt));
2456                 ctxt.seid = vsi->seid;
2457                 ctxt.pf_num = hw->pf_id;
2458                 ctxt.uplink_seid = vsi->uplink_seid;
2459                 ctxt.vf_num = 0;
2460                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2461                 if (ret != I40E_SUCCESS) {
2462                         PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2463                         goto fail_msix_alloc;
2464                 }
2465                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2466                         sizeof(struct i40e_aqc_vsi_properties_data));
2467                 vsi->vsi_id = ctxt.vsi_number;
2468                 vsi->info.valid_sections = 0;
2469
2470                 /* Configure tc, enabled TC0 only */
2471                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2472                         I40E_SUCCESS) {
2473                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2474                         goto fail_msix_alloc;
2475                 }
2476
2477                 /* TC, queue mapping */
2478                 memset(&ctxt, 0, sizeof(ctxt));
2479                 vsi->info.valid_sections |=
2480                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2481                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2482                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2483                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2484                         sizeof(struct i40e_aqc_vsi_properties_data));
2485                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2486                                                 I40E_DEFAULT_TCMAP);
2487                 if (ret != I40E_SUCCESS) {
2488                         PMD_DRV_LOG(ERR, "Failed to configure "
2489                                         "TC queue mapping\n");
2490                         goto fail_msix_alloc;
2491                 }
2492                 ctxt.seid = vsi->seid;
2493                 ctxt.pf_num = hw->pf_id;
2494                 ctxt.uplink_seid = vsi->uplink_seid;
2495                 ctxt.vf_num = 0;
2496
2497                 /* Update VSI parameters */
2498                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2499                 if (ret != I40E_SUCCESS) {
2500                         PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2501                         goto fail_msix_alloc;
2502                 }
2503
2504                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2505                                                 sizeof(vsi->info.tc_mapping));
2506                 (void)rte_memcpy(&vsi->info.queue_mapping,
2507                                 &ctxt.info.queue_mapping,
2508                         sizeof(vsi->info.queue_mapping));
2509                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2510                 vsi->info.valid_sections = 0;
2511
2512                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2513                                 ETH_ADDR_LEN);
2514
2515                 /**
2516                  * Updating default filter settings are necessary to prevent
2517                  * reception of tagged packets.
2518                  * Some old firmware configurations load a default macvlan
2519                  * filter which accepts both tagged and untagged packets.
2520                  * The updating is to use a normal filter instead if needed.
2521                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2522                  * The firmware with correct configurations load the default
2523                  * macvlan filter which is expected and cannot be removed.
2524                  */
2525                 i40e_update_default_filter_setting(vsi);
2526         } else if (type == I40E_VSI_SRIOV) {
2527                 memset(&ctxt, 0, sizeof(ctxt));
2528                 /**
2529                  * For other VSI, the uplink_seid equals to uplink VSI's
2530                  * uplink_seid since they share same VEB
2531                  */
2532                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2533                 ctxt.pf_num = hw->pf_id;
2534                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2535                 ctxt.uplink_seid = vsi->uplink_seid;
2536                 ctxt.connection_type = 0x1;
2537                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2538
2539                 /* Configure switch ID */
2540                 ctxt.info.valid_sections |=
2541                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2542                 ctxt.info.switch_id =
2543                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2544                 /* Configure port/vlan */
2545                 ctxt.info.valid_sections |=
2546                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2547                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2548                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2549                                                 I40E_DEFAULT_TCMAP);
2550                 if (ret != I40E_SUCCESS) {
2551                         PMD_DRV_LOG(ERR, "Failed to configure "
2552                                         "TC queue mapping\n");
2553                         goto fail_msix_alloc;
2554                 }
2555                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2556                 ctxt.info.valid_sections |=
2557                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2558                 /**
2559                  * Since VSI is not created yet, only configure parameter,
2560                  * will add vsi below.
2561                  */
2562         }
2563         else {
2564                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2565                 goto fail_msix_alloc;
2566         }
2567
2568         if (vsi->type != I40E_VSI_MAIN) {
2569                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2570                 if (ret) {
2571                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2572                                  hw->aq.asq_last_status);
2573                         goto fail_msix_alloc;
2574                 }
2575                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2576                 vsi->info.valid_sections = 0;
2577                 vsi->seid = ctxt.seid;
2578                 vsi->vsi_id = ctxt.vsi_number;
2579                 vsi->sib_vsi_list.vsi = vsi;
2580                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2581                                 &vsi->sib_vsi_list, list);
2582         }
2583
2584         /* MAC/VLAN configuration */
2585         ret = i40e_vsi_add_mac(vsi, &broadcast);
2586         if (ret != I40E_SUCCESS) {
2587                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2588                 goto fail_msix_alloc;
2589         }
2590
2591         /* Get VSI BW information */
2592         i40e_vsi_dump_bw_config(vsi);
2593         return vsi;
2594 fail_msix_alloc:
2595         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2596 fail_queue_alloc:
2597         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2598 fail_mem:
2599         rte_free(vsi);
2600         return NULL;
2601 }
2602
2603 /* Configure vlan stripping on or off */
2604 int
2605 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2606 {
2607         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2608         struct i40e_vsi_context ctxt;
2609         uint8_t vlan_flags;
2610         int ret = I40E_SUCCESS;
2611
2612         /* Check if it has been already on or off */
2613         if (vsi->info.valid_sections &
2614                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2615                 if (on) {
2616                         if ((vsi->info.port_vlan_flags &
2617                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2618                                 return 0; /* already on */
2619                 } else {
2620                         if ((vsi->info.port_vlan_flags &
2621                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2622                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2623                                 return 0; /* already off */
2624                 }
2625         }
2626
2627         if (on)
2628                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2629         else
2630                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2631         vsi->info.valid_sections =
2632                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2633         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2634         vsi->info.port_vlan_flags |= vlan_flags;
2635         ctxt.seid = vsi->seid;
2636         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2637         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2638         if (ret)
2639                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2640                                                 on ? "enable" : "disable");
2641
2642         return ret;
2643 }
2644
2645 static int
2646 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2647 {
2648         struct rte_eth_dev_data *data = dev->data;
2649         int ret;
2650
2651         /* Apply vlan offload setting */
2652         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2653
2654         /* Apply double-vlan setting, not implemented yet */
2655
2656         /* Apply pvid setting */
2657         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2658                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2659         if (ret)
2660                 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2661
2662         return ret;
2663 }
2664
2665 static int
2666 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2667 {
2668         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2669
2670         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2671 }
2672
2673 static int
2674 i40e_update_flow_control(struct i40e_hw *hw)
2675 {
2676 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2677         struct i40e_link_status link_status;
2678         uint32_t rxfc = 0, txfc = 0, reg;
2679         uint8_t an_info;
2680         int ret;
2681
2682         memset(&link_status, 0, sizeof(link_status));
2683         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2684         if (ret != I40E_SUCCESS) {
2685                 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2686                 goto write_reg; /* Disable flow control */
2687         }
2688
2689         an_info = hw->phy.link_info.an_info;
2690         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2691                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2692                 ret = I40E_ERR_NOT_READY;
2693                 goto write_reg; /* Disable flow control */
2694         }
2695         /**
2696          * If link auto negotiation is enabled, flow control needs to
2697          * be configured according to it
2698          */
2699         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2700         case I40E_LINK_PAUSE_RXTX:
2701                 rxfc = 1;
2702                 txfc = 1;
2703                 hw->fc.current_mode = I40E_FC_FULL;
2704                 break;
2705         case I40E_AQ_LINK_PAUSE_RX:
2706                 rxfc = 1;
2707                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2708                 break;
2709         case I40E_AQ_LINK_PAUSE_TX:
2710                 txfc = 1;
2711                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2712                 break;
2713         default:
2714                 hw->fc.current_mode = I40E_FC_NONE;
2715                 break;
2716         }
2717
2718 write_reg:
2719         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2720                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2721         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2722         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2723         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2724         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2725
2726         return ret;
2727 }
2728
2729 /* PF setup */
2730 static int
2731 i40e_pf_setup(struct i40e_pf *pf)
2732 {
2733         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2734         struct i40e_filter_control_settings settings;
2735         struct rte_eth_dev_data *dev_data = pf->dev_data;
2736         struct i40e_vsi *vsi;
2737         int ret;
2738
2739         /* Clear all stats counters */
2740         pf->offset_loaded = FALSE;
2741         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2742         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2743
2744         ret = i40e_pf_get_switch_config(pf);
2745         if (ret != I40E_SUCCESS) {
2746                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2747                 return ret;
2748         }
2749
2750         /* VSI setup */
2751         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2752         if (!vsi) {
2753                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2754                 return I40E_ERR_NOT_READY;
2755         }
2756         pf->main_vsi = vsi;
2757         dev_data->nb_rx_queues = vsi->nb_qps;
2758         dev_data->nb_tx_queues = vsi->nb_qps;
2759
2760         /* Configure filter control */
2761         memset(&settings, 0, sizeof(settings));
2762         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2763         /* Enable ethtype and macvlan filters */
2764         settings.enable_ethtype = TRUE;
2765         settings.enable_macvlan = TRUE;
2766         ret = i40e_set_filter_control(hw, &settings);
2767         if (ret)
2768                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2769                                                                 ret);
2770
2771         /* Update flow control according to the auto negotiation */
2772         i40e_update_flow_control(hw);
2773
2774         return I40E_SUCCESS;
2775 }
2776
2777 int
2778 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2779 {
2780         uint32_t reg;
2781         uint16_t j;
2782
2783         /* Wait until the request is finished */
2784         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2785                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2786                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2787                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2788                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2789                                                         & 0x1))) {
2790                         break;
2791                 }
2792         }
2793         if (on) {
2794                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2795                         return I40E_SUCCESS; /* already on, skip next steps */
2796                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2797         } else {
2798                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2799                         return I40E_SUCCESS; /* already off, skip next steps */
2800                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2801         }
2802         /* Write the register */
2803         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2804         /* Check the result */
2805         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2806                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2807                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2808                 if (on) {
2809                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2810                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2811                                 break;
2812                 } else {
2813                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2814                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2815                                 break;
2816                 }
2817         }
2818         /* Check if it is timeout */
2819         if (j >= I40E_CHK_Q_ENA_COUNT) {
2820                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2821                         (on ? "enable" : "disable"), q_idx);
2822                 return I40E_ERR_TIMEOUT;
2823         }
2824         return I40E_SUCCESS;
2825 }
2826 /* Swith on or off the tx queues */
2827 static int
2828 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
2829 {
2830         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2831         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2832         struct i40e_tx_queue *txq;
2833         uint16_t i, pf_q;
2834         int ret;
2835
2836         pf_q = vsi->base_queue;
2837         for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
2838                 txq = dev_data->tx_queues[i];
2839                 if (!txq->q_set)
2840                         continue; /* Queue not configured */
2841                 ret = i40e_switch_tx_queue(hw, pf_q, on);
2842                 if ( ret != I40E_SUCCESS)
2843                         return ret;
2844         }
2845
2846         return I40E_SUCCESS;
2847 }
2848
2849 int
2850 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2851 {
2852         uint32_t reg;
2853         uint16_t j;
2854
2855         /* Wait until the request is finished */
2856         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2857                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2858                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2859                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2860                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
2861                         break;
2862         }
2863
2864         if (on) {
2865                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
2866                         return I40E_SUCCESS; /* Already on, skip next steps */
2867                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
2868         } else {
2869                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2870                         return I40E_SUCCESS; /* Already off, skip next steps */
2871                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
2872         }
2873
2874         /* Write the register */
2875         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
2876         /* Check the result */
2877         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2878                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2879                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2880                 if (on) {
2881                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2882                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
2883                                 break;
2884                 } else {
2885                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2886                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2887                                 break;
2888                 }
2889         }
2890
2891         /* Check if it is timeout */
2892         if (j >= I40E_CHK_Q_ENA_COUNT) {
2893                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
2894                         (on ? "enable" : "disable"), q_idx);
2895                 return I40E_ERR_TIMEOUT;
2896         }
2897
2898         return I40E_SUCCESS;
2899 }
2900 /* Switch on or off the rx queues */
2901 static int
2902 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
2903 {
2904         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2905         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2906         struct i40e_rx_queue *rxq;
2907         uint16_t i, pf_q;
2908         int ret;
2909
2910         pf_q = vsi->base_queue;
2911         for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
2912                 rxq = dev_data->rx_queues[i];
2913                 if (!rxq->q_set)
2914                         continue; /* Queue not configured */
2915                 ret = i40e_switch_rx_queue(hw, pf_q, on);
2916                 if ( ret != I40E_SUCCESS)
2917                         return ret;
2918         }
2919
2920         return I40E_SUCCESS;
2921 }
2922
2923 /* Switch on or off all the rx/tx queues */
2924 int
2925 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
2926 {
2927         int ret;
2928
2929         if (on) {
2930                 /* enable rx queues before enabling tx queues */
2931                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2932                 if (ret) {
2933                         PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
2934                         return ret;
2935                 }
2936                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2937         } else {
2938                 /* Stop tx queues before stopping rx queues */
2939                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2940                 if (ret) {
2941                         PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
2942                         return ret;
2943                 }
2944                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2945         }
2946
2947         return ret;
2948 }
2949
2950 /* Initialize VSI for TX */
2951 static int
2952 i40e_vsi_tx_init(struct i40e_vsi *vsi)
2953 {
2954         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2955         struct rte_eth_dev_data *data = pf->dev_data;
2956         uint16_t i;
2957         uint32_t ret = I40E_SUCCESS;
2958
2959         for (i = 0; i < data->nb_tx_queues; i++) {
2960                 ret = i40e_tx_queue_init(data->tx_queues[i]);
2961                 if (ret != I40E_SUCCESS)
2962                         break;
2963         }
2964
2965         return ret;
2966 }
2967
2968 /* Initialize VSI for RX */
2969 static int
2970 i40e_vsi_rx_init(struct i40e_vsi *vsi)
2971 {
2972         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2973         struct rte_eth_dev_data *data = pf->dev_data;
2974         int ret = I40E_SUCCESS;
2975         uint16_t i;
2976
2977         i40e_pf_config_mq_rx(pf);
2978         for (i = 0; i < data->nb_rx_queues; i++) {
2979                 ret = i40e_rx_queue_init(data->rx_queues[i]);
2980                 if (ret != I40E_SUCCESS) {
2981                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
2982                                         "initialization\n");
2983                         break;
2984                 }
2985         }
2986
2987         return ret;
2988 }
2989
2990 /* Initialize VSI */
2991 static int
2992 i40e_vsi_init(struct i40e_vsi *vsi)
2993 {
2994         int err;
2995
2996         err = i40e_vsi_tx_init(vsi);
2997         if (err) {
2998                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
2999                 return err;
3000         }
3001         err = i40e_vsi_rx_init(vsi);
3002         if (err) {
3003                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3004                 return err;
3005         }
3006
3007         return err;
3008 }
3009
3010 static void
3011 i40e_stat_update_32(struct i40e_hw *hw,
3012                    uint32_t reg,
3013                    bool offset_loaded,
3014                    uint64_t *offset,
3015                    uint64_t *stat)
3016 {
3017         uint64_t new_data;
3018
3019         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3020         if (!offset_loaded)
3021                 *offset = new_data;
3022
3023         if (new_data >= *offset)
3024                 *stat = (uint64_t)(new_data - *offset);
3025         else
3026                 *stat = (uint64_t)((new_data +
3027                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3028 }
3029
3030 static void
3031 i40e_stat_update_48(struct i40e_hw *hw,
3032                    uint32_t hireg,
3033                    uint32_t loreg,
3034                    bool offset_loaded,
3035                    uint64_t *offset,
3036                    uint64_t *stat)
3037 {
3038         uint64_t new_data;
3039
3040         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3041         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3042                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3043
3044         if (!offset_loaded)
3045                 *offset = new_data;
3046
3047         if (new_data >= *offset)
3048                 *stat = new_data - *offset;
3049         else
3050                 *stat = (uint64_t)((new_data +
3051                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3052
3053         *stat &= I40E_48_BIT_MASK;
3054 }
3055
3056 /* Disable IRQ0 */
3057 void
3058 i40e_pf_disable_irq0(struct i40e_hw *hw)
3059 {
3060         /* Disable all interrupt types */
3061         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3062         I40E_WRITE_FLUSH(hw);
3063 }
3064
3065 /* Enable IRQ0 */
3066 void
3067 i40e_pf_enable_irq0(struct i40e_hw *hw)
3068 {
3069         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3070                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3071                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3072                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3073         I40E_WRITE_FLUSH(hw);
3074 }
3075
3076 static void
3077 i40e_pf_config_irq0(struct i40e_hw *hw)
3078 {
3079         uint32_t enable;
3080
3081         /* read pending request and disable first */
3082         i40e_pf_disable_irq0(hw);
3083         /**
3084          * Enable all interrupt error options to detect possible errors,
3085          * other informative int are ignored
3086          */
3087         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3088                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3089                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3090                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3091                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3092                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3093                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3094                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3095
3096         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3097         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3098                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3099
3100         /* Link no queues with irq0 */
3101         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3102                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3103 }
3104
3105 static void
3106 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3107 {
3108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3110         int i;
3111         uint16_t abs_vf_id;
3112         uint32_t index, offset, val;
3113
3114         if (!pf->vfs)
3115                 return;
3116         /**
3117          * Try to find which VF trigger a reset, use absolute VF id to access
3118          * since the reg is global register.
3119          */
3120         for (i = 0; i < pf->vf_num; i++) {
3121                 abs_vf_id = hw->func_caps.vf_base_id + i;
3122                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3123                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3124                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3125                 /* VFR event occured */
3126                 if (val & (0x1 << offset)) {
3127                         int ret;
3128
3129                         /* Clear the event first */
3130                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3131                                                         (0x1 << offset));
3132                         PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3133                         /**
3134                          * Only notify a VF reset event occured,
3135                          * don't trigger another SW reset
3136                          */
3137                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3138                         if (ret != I40E_SUCCESS)
3139                                 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3140                 }
3141         }
3142 }
3143
3144 static void
3145 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3146 {
3147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148         struct i40e_arq_event_info info;
3149         uint16_t pending, opcode;
3150         int ret;
3151
3152         info.msg_size = I40E_AQ_BUF_SZ;
3153         info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3154         if (!info.msg_buf) {
3155                 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3156                 return;
3157         }
3158
3159         pending = 1;
3160         while (pending) {
3161                 ret = i40e_clean_arq_element(hw, &info, &pending);
3162
3163                 if (ret != I40E_SUCCESS) {
3164                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3165                                 "aq_err: %u\n", hw->aq.asq_last_status);
3166                         break;
3167                 }
3168                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3169
3170                 switch (opcode) {
3171                 case i40e_aqc_opc_send_msg_to_pf:
3172                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3173                         i40e_pf_host_handle_vf_msg(dev,
3174                                         rte_le_to_cpu_16(info.desc.retval),
3175                                         rte_le_to_cpu_32(info.desc.cookie_high),
3176                                         rte_le_to_cpu_32(info.desc.cookie_low),
3177                                         info.msg_buf,
3178                                         info.msg_size);
3179                         break;
3180                 default:
3181                         PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3182                                 opcode);
3183                         break;
3184                 }
3185                 /* Reset the buffer after processing one */
3186                 info.msg_size = I40E_AQ_BUF_SZ;
3187         }
3188         rte_free(info.msg_buf);
3189 }
3190
3191 /**
3192  * Interrupt handler triggered by NIC  for handling
3193  * specific interrupt.
3194  *
3195  * @param handle
3196  *  Pointer to interrupt handle.
3197  * @param param
3198  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3199  *
3200  * @return
3201  *  void
3202  */
3203 static void
3204 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3205                            void *param)
3206 {
3207         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3208         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209         uint32_t cause, enable;
3210
3211         i40e_pf_disable_irq0(hw);
3212
3213         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3214         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3215
3216         /* Shared IRQ case, return */
3217         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3218                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3219                         "no INT event to process\n", hw->pf_id);
3220                 goto done;
3221         }
3222
3223         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3224                 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3225                 i40e_dev_link_update(dev, 0);
3226         }
3227
3228         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3229                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3230
3231         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3232                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3233
3234         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3235                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3236
3237         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3238                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3239
3240         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3241                 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3242
3243         /* Add processing func to deal with VF reset vent */
3244         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3245                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3246                 i40e_dev_handle_vfr_event(dev);
3247         }
3248         /* Find admin queue event */
3249         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3250                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3251                 i40e_dev_handle_aq_msg(dev);
3252         }
3253
3254 done:
3255         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3256         /* Re-enable interrupt from device side */
3257         i40e_pf_enable_irq0(hw);
3258         /* Re-enable interrupt from host side */
3259         rte_intr_enable(&(dev->pci_dev->intr_handle));
3260 }
3261
3262 static int
3263 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3264                          struct i40e_macvlan_filter *filter,
3265                          int total)
3266 {
3267         int ele_num, ele_buff_size;
3268         int num, actual_num, i;
3269         int ret = I40E_SUCCESS;
3270         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3271         struct i40e_aqc_add_macvlan_element_data *req_list;
3272
3273         if (filter == NULL  || total == 0)
3274                 return I40E_ERR_PARAM;
3275         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3276         ele_buff_size = hw->aq.asq_buf_size;
3277
3278         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3279         if (req_list == NULL) {
3280                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3281                 return I40E_ERR_NO_MEMORY;
3282         }
3283
3284         num = 0;
3285         do {
3286                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3287                 memset(req_list, 0, ele_buff_size);
3288
3289                 for (i = 0; i < actual_num; i++) {
3290                         (void)rte_memcpy(req_list[i].mac_addr,
3291                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3292                         req_list[i].vlan_tag =
3293                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3294                         req_list[i].flags = rte_cpu_to_le_16(\
3295                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3296                         req_list[i].queue_number = 0;
3297                 }
3298
3299                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3300                                                 actual_num, NULL);
3301                 if (ret != I40E_SUCCESS) {
3302                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3303                         goto DONE;
3304                 }
3305                 num += actual_num;
3306         } while (num < total);
3307
3308 DONE:
3309         rte_free(req_list);
3310         return ret;
3311 }
3312
3313 static int
3314 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3315                             struct i40e_macvlan_filter *filter,
3316                             int total)
3317 {
3318         int ele_num, ele_buff_size;
3319         int num, actual_num, i;
3320         int ret = I40E_SUCCESS;
3321         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3322         struct i40e_aqc_remove_macvlan_element_data *req_list;
3323
3324         if (filter == NULL  || total == 0)
3325                 return I40E_ERR_PARAM;
3326
3327         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3328         ele_buff_size = hw->aq.asq_buf_size;
3329
3330         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3331         if (req_list == NULL) {
3332                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3333                 return I40E_ERR_NO_MEMORY;
3334         }
3335
3336         num = 0;
3337         do {
3338                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3339                 memset(req_list, 0, ele_buff_size);
3340
3341                 for (i = 0; i < actual_num; i++) {
3342                         (void)rte_memcpy(req_list[i].mac_addr,
3343                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3344                         req_list[i].vlan_tag =
3345                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3346                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3347                 }
3348
3349                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3350                                                 actual_num, NULL);
3351                 if (ret != I40E_SUCCESS) {
3352                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3353                         goto DONE;
3354                 }
3355                 num += actual_num;
3356         } while (num < total);
3357
3358 DONE:
3359         rte_free(req_list);
3360         return ret;
3361 }
3362
3363 /* Find out specific MAC filter */
3364 static struct i40e_mac_filter *
3365 i40e_find_mac_filter(struct i40e_vsi *vsi,
3366                          struct ether_addr *macaddr)
3367 {
3368         struct i40e_mac_filter *f;
3369
3370         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3371                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3372                         return f;
3373         }
3374
3375         return NULL;
3376 }
3377
3378 static bool
3379 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3380                          uint16_t vlan_id)
3381 {
3382         uint32_t vid_idx, vid_bit;
3383
3384         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3385         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3386
3387         if (vsi->vfta[vid_idx] & vid_bit)
3388                 return 1;
3389         else
3390                 return 0;
3391 }
3392
3393 static void
3394 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3395                          uint16_t vlan_id, bool on)
3396 {
3397         uint32_t vid_idx, vid_bit;
3398
3399 #define UINT32_BIT_MASK      0x1F
3400 #define VALID_VLAN_BIT_MASK  0xFFF
3401         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3402          *  element first, then find the bits it belongs to
3403          */
3404         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3405                   sizeof(uint32_t));
3406         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3407
3408         if (on)
3409                 vsi->vfta[vid_idx] |= vid_bit;
3410         else
3411                 vsi->vfta[vid_idx] &= ~vid_bit;
3412 }
3413
3414 /**
3415  * Find all vlan options for specific mac addr,
3416  * return with actual vlan found.
3417  */
3418 static inline int
3419 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3420                            struct i40e_macvlan_filter *mv_f,
3421                            int num, struct ether_addr *addr)
3422 {
3423         int i;
3424         uint32_t j, k;
3425
3426         /**
3427          * Not to use i40e_find_vlan_filter to decrease the loop time,
3428          * although the code looks complex.
3429           */
3430         if (num < vsi->vlan_num)
3431                 return I40E_ERR_PARAM;
3432
3433         i = 0;
3434         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3435                 if (vsi->vfta[j]) {
3436                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3437                                 if (vsi->vfta[j] & (1 << k)) {
3438                                         if (i > num - 1) {
3439                                                 PMD_DRV_LOG(ERR, "vlan number "
3440                                                                 "not match\n");
3441                                                 return I40E_ERR_PARAM;
3442                                         }
3443                                         (void)rte_memcpy(&mv_f[i].macaddr,
3444                                                         addr, ETH_ADDR_LEN);
3445                                         mv_f[i].vlan_id =
3446                                                 j * I40E_UINT32_BIT_SIZE + k;
3447                                         i++;
3448                                 }
3449                         }
3450                 }
3451         }
3452         return I40E_SUCCESS;
3453 }
3454
3455 static inline int
3456 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3457                            struct i40e_macvlan_filter *mv_f,
3458                            int num,
3459                            uint16_t vlan)
3460 {
3461         int i = 0;
3462         struct i40e_mac_filter *f;
3463
3464         if (num < vsi->mac_num)
3465                 return I40E_ERR_PARAM;
3466
3467         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3468                 if (i > num - 1) {
3469                         PMD_DRV_LOG(ERR, "buffer number not match\n");
3470                         return I40E_ERR_PARAM;
3471                 }
3472                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3473                 mv_f[i].vlan_id = vlan;
3474                 i++;
3475         }
3476
3477         return I40E_SUCCESS;
3478 }
3479
3480 static int
3481 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3482 {
3483         int i, num;
3484         struct i40e_mac_filter *f;
3485         struct i40e_macvlan_filter *mv_f;
3486         int ret = I40E_SUCCESS;
3487
3488         if (vsi == NULL || vsi->mac_num == 0)
3489                 return I40E_ERR_PARAM;
3490
3491         /* Case that no vlan is set */
3492         if (vsi->vlan_num == 0)
3493                 num = vsi->mac_num;
3494         else
3495                 num = vsi->mac_num * vsi->vlan_num;
3496
3497         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3498         if (mv_f == NULL) {
3499                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3500                 return I40E_ERR_NO_MEMORY;
3501         }
3502
3503         i = 0;
3504         if (vsi->vlan_num == 0) {
3505                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3506                         (void)rte_memcpy(&mv_f[i].macaddr,
3507                                 &f->macaddr, ETH_ADDR_LEN);
3508                         mv_f[i].vlan_id = 0;
3509                         i++;
3510                 }
3511         } else {
3512                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3513                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3514                                         vsi->vlan_num, &f->macaddr);
3515                         if (ret != I40E_SUCCESS)
3516                                 goto DONE;
3517                         i += vsi->vlan_num;
3518                 }
3519         }
3520
3521         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3522 DONE:
3523         rte_free(mv_f);
3524
3525         return ret;
3526 }
3527
3528 int
3529 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3530 {
3531         struct i40e_macvlan_filter *mv_f;
3532         int mac_num;
3533         int ret = I40E_SUCCESS;
3534
3535         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3536                 return I40E_ERR_PARAM;
3537
3538         /* If it's already set, just return */
3539         if (i40e_find_vlan_filter(vsi,vlan))
3540                 return I40E_SUCCESS;
3541
3542         mac_num = vsi->mac_num;
3543
3544         if (mac_num == 0) {
3545                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3546                 return I40E_ERR_PARAM;
3547         }
3548
3549         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3550
3551         if (mv_f == NULL) {
3552                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3553                 return I40E_ERR_NO_MEMORY;
3554         }
3555
3556         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3557
3558         if (ret != I40E_SUCCESS)
3559                 goto DONE;
3560
3561         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3562
3563         if (ret != I40E_SUCCESS)
3564                 goto DONE;
3565
3566         i40e_set_vlan_filter(vsi, vlan, 1);
3567
3568         vsi->vlan_num++;
3569         ret = I40E_SUCCESS;
3570 DONE:
3571         rte_free(mv_f);
3572         return ret;
3573 }
3574
3575 int
3576 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3577 {
3578         struct i40e_macvlan_filter *mv_f;
3579         int mac_num;
3580         int ret = I40E_SUCCESS;
3581
3582         /**
3583          * Vlan 0 is the generic filter for untagged packets
3584          * and can't be removed.
3585          */
3586         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3587                 return I40E_ERR_PARAM;
3588
3589         /* If can't find it, just return */
3590         if (!i40e_find_vlan_filter(vsi, vlan))
3591                 return I40E_ERR_PARAM;
3592
3593         mac_num = vsi->mac_num;
3594
3595         if (mac_num == 0) {
3596                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3597                 return I40E_ERR_PARAM;
3598         }
3599
3600         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3601
3602         if (mv_f == NULL) {
3603                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3604                 return I40E_ERR_NO_MEMORY;
3605         }
3606
3607         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3608
3609         if (ret != I40E_SUCCESS)
3610                 goto DONE;
3611
3612         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3613
3614         if (ret != I40E_SUCCESS)
3615                 goto DONE;
3616
3617         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3618         if (vsi->vlan_num == 1) {
3619                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3620                 if (ret != I40E_SUCCESS)
3621                         goto DONE;
3622
3623                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3624                 if (ret != I40E_SUCCESS)
3625                         goto DONE;
3626         }
3627
3628         i40e_set_vlan_filter(vsi, vlan, 0);
3629
3630         vsi->vlan_num--;
3631         ret = I40E_SUCCESS;
3632 DONE:
3633         rte_free(mv_f);
3634         return ret;
3635 }
3636
3637 int
3638 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3639 {
3640         struct i40e_mac_filter *f;
3641         struct i40e_macvlan_filter *mv_f;
3642         int vlan_num;
3643         int ret = I40E_SUCCESS;
3644
3645         /* If it's add and we've config it, return */
3646         f = i40e_find_mac_filter(vsi, addr);
3647         if (f != NULL)
3648                 return I40E_SUCCESS;
3649
3650         /**
3651          * If vlan_num is 0, that's the first time to add mac,
3652          * set mask for vlan_id 0.
3653          */
3654         if (vsi->vlan_num == 0) {
3655                 i40e_set_vlan_filter(vsi, 0, 1);
3656                 vsi->vlan_num = 1;
3657         }
3658
3659         vlan_num = vsi->vlan_num;
3660
3661         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3662         if (mv_f == NULL) {
3663                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3664                 return I40E_ERR_NO_MEMORY;
3665         }
3666
3667         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3668         if (ret != I40E_SUCCESS)
3669                 goto DONE;
3670
3671         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3672         if (ret != I40E_SUCCESS)
3673                 goto DONE;
3674
3675         /* Add the mac addr into mac list */
3676         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3677         if (f == NULL) {
3678                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3679                 ret = I40E_ERR_NO_MEMORY;
3680                 goto DONE;
3681         }
3682         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3683         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3684         vsi->mac_num++;
3685
3686         ret = I40E_SUCCESS;
3687 DONE:
3688         rte_free(mv_f);
3689
3690         return ret;
3691 }
3692
3693 int
3694 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3695 {
3696         struct i40e_mac_filter *f;
3697         struct i40e_macvlan_filter *mv_f;
3698         int vlan_num;
3699         int ret = I40E_SUCCESS;
3700
3701         /* Can't find it, return an error */
3702         f = i40e_find_mac_filter(vsi, addr);
3703         if (f == NULL)
3704                 return I40E_ERR_PARAM;
3705
3706         vlan_num = vsi->vlan_num;
3707         if (vlan_num == 0) {
3708                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3709                 return I40E_ERR_PARAM;
3710         }
3711         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3712         if (mv_f == NULL) {
3713                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3714                 return I40E_ERR_NO_MEMORY;
3715         }
3716
3717         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3718         if (ret != I40E_SUCCESS)
3719                 goto DONE;
3720
3721         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3722         if (ret != I40E_SUCCESS)
3723                 goto DONE;
3724
3725         /* Remove the mac addr into mac list */
3726         TAILQ_REMOVE(&vsi->mac_list, f, next);
3727         rte_free(f);
3728         vsi->mac_num--;
3729
3730         ret = I40E_SUCCESS;
3731 DONE:
3732         rte_free(mv_f);
3733         return ret;
3734 }
3735
3736 /* Configure hash enable flags for RSS */
3737 static uint64_t
3738 i40e_config_hena(uint64_t flags)
3739 {
3740         uint64_t hena = 0;
3741
3742         if (!flags)
3743                 return hena;
3744
3745         if (flags & ETH_RSS_NONF_IPV4_UDP)
3746                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3747         if (flags & ETH_RSS_NONF_IPV4_TCP)
3748                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3749         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3750                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3751         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3752                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3753         if (flags & ETH_RSS_FRAG_IPV4)
3754                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3755         if (flags & ETH_RSS_NONF_IPV6_UDP)
3756                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3757         if (flags & ETH_RSS_NONF_IPV6_TCP)
3758                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3759         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3760                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3761         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3762                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3763         if (flags & ETH_RSS_FRAG_IPV6)
3764                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3765         if (flags & ETH_RSS_L2_PAYLOAD)
3766                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3767
3768         return hena;
3769 }
3770
3771 /* Parse the hash enable flags */
3772 static uint64_t
3773 i40e_parse_hena(uint64_t flags)
3774 {
3775         uint64_t rss_hf = 0;
3776
3777         if (!flags)
3778                 return rss_hf;
3779
3780         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3781                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3782         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3783                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3784         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3785                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3786         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3787                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3788         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3789                 rss_hf |= ETH_RSS_FRAG_IPV4;
3790         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3791                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3792         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3793                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3794         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3795                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3796         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3797                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3798         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3799                 rss_hf |= ETH_RSS_FRAG_IPV6;
3800         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3801                 rss_hf |= ETH_RSS_L2_PAYLOAD;
3802
3803         return rss_hf;
3804 }
3805
3806 /* Disable RSS */
3807 static void
3808 i40e_pf_disable_rss(struct i40e_pf *pf)
3809 {
3810         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3811         uint64_t hena;
3812
3813         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3814         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3815         hena &= ~I40E_RSS_HENA_ALL;
3816         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3817         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3818         I40E_WRITE_FLUSH(hw);
3819 }
3820
3821 static int
3822 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
3823 {
3824         uint32_t *hash_key;
3825         uint8_t hash_key_len;
3826         uint64_t rss_hf;
3827         uint16_t i;
3828         uint64_t hena;
3829
3830         hash_key = (uint32_t *)(rss_conf->rss_key);
3831         hash_key_len = rss_conf->rss_key_len;
3832         if (hash_key != NULL && hash_key_len >=
3833                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3834                 /* Fill in RSS hash key */
3835                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3836                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
3837         }
3838
3839         rss_hf = rss_conf->rss_hf;
3840         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3841         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3842         hena &= ~I40E_RSS_HENA_ALL;
3843         hena |= i40e_config_hena(rss_hf);
3844         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3845         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3846         I40E_WRITE_FLUSH(hw);
3847
3848         return 0;
3849 }
3850
3851 static int
3852 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
3853                          struct rte_eth_rss_conf *rss_conf)
3854 {
3855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
3857         uint64_t hena;
3858
3859         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3860         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3861         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
3862                 if (rss_hf != 0) /* Enable RSS */
3863                         return -EINVAL;
3864                 return 0; /* Nothing to do */
3865         }
3866         /* RSS enabled */
3867         if (rss_hf == 0) /* Disable RSS */
3868                 return -EINVAL;
3869
3870         return i40e_hw_rss_hash_set(hw, rss_conf);
3871 }
3872
3873 static int
3874 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3875                            struct rte_eth_rss_conf *rss_conf)
3876 {
3877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3878         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
3879         uint64_t hena;
3880         uint16_t i;
3881
3882         if (hash_key != NULL) {
3883                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3884                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
3885                 rss_conf->rss_key_len = i * sizeof(uint32_t);
3886         }
3887         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3888         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3889         rss_conf->rss_hf = i40e_parse_hena(hena);
3890
3891         return 0;
3892 }
3893
3894 /* Configure RSS */
3895 static int
3896 i40e_pf_config_rss(struct i40e_pf *pf)
3897 {
3898         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3899         struct rte_eth_rss_conf rss_conf;
3900         uint32_t i, lut = 0;
3901         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
3902
3903         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
3904                 if (j == num)
3905                         j = 0;
3906                 lut = (lut << 8) | (j & ((0x1 <<
3907                         hw->func_caps.rss_table_entry_width) - 1));
3908                 if ((i & 3) == 3)
3909                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
3910         }
3911
3912         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
3913         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
3914                 i40e_pf_disable_rss(pf);
3915                 return 0;
3916         }
3917         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
3918                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3919                 /* Calculate the default hash key */
3920                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3921                         rss_key_default[i] = (uint32_t)rte_rand();
3922                 rss_conf.rss_key = (uint8_t *)rss_key_default;
3923                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3924                                                         sizeof(uint32_t);
3925         }
3926
3927         return i40e_hw_rss_hash_set(hw, &rss_conf);
3928 }
3929
3930 static int
3931 i40e_pf_config_mq_rx(struct i40e_pf *pf)
3932 {
3933         if (!pf->dev_data->sriov.active) {
3934                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
3935                 case ETH_MQ_RX_RSS:
3936                         i40e_pf_config_rss(pf);
3937                         break;
3938                 default:
3939                         i40e_pf_disable_rss(pf);
3940                         break;
3941                 }
3942         }
3943
3944         return 0;
3945 }