4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
52 #include "i40e_logs.h"
53 #include "i40e/i40e_register_x710_int.h"
54 #include "i40e/i40e_prototype.h"
55 #include "i40e/i40e_adminq_cmd.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
61 /* Maximun number of MAC addresses */
62 #define I40E_NUM_MACADDR_MAX 64
63 #define I40E_CLEAR_PXE_WAIT_MS 200
65 /* Maximun number of capability elements */
66 #define I40E_MAX_CAP_ELE_NUM 128
68 /* Wait count and inteval */
69 #define I40E_CHK_Q_ENA_COUNT 1000
70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
72 /* Maximun number of VSI */
73 #define I40E_MAX_NUM_VSIS (384UL)
75 /* Bit shift and mask */
76 #define I40E_16_BIT_SHIFT 16
77 #define I40E_16_BIT_MASK 0xFFFF
78 #define I40E_32_BIT_SHIFT 32
79 #define I40E_32_BIT_MASK 0xFFFFFFFF
80 #define I40E_48_BIT_SHIFT 48
81 #define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL
83 /* Default queue interrupt throttling time in microseconds*/
84 #define I40E_ITR_INDEX_DEFAULT 0
85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
86 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
88 #define I40E_RSS_OFFLOAD_ALL ( \
89 ETH_RSS_NONF_IPV4_UDP | \
90 ETH_RSS_NONF_IPV4_TCP | \
91 ETH_RSS_NONF_IPV4_SCTP | \
92 ETH_RSS_NONF_IPV4_OTHER | \
94 ETH_RSS_NONF_IPV6_UDP | \
95 ETH_RSS_NONF_IPV6_TCP | \
96 ETH_RSS_NONF_IPV6_SCTP | \
97 ETH_RSS_NONF_IPV6_OTHER | \
101 /* All bits of RSS hash enable */
102 #define I40E_RSS_HENA_ALL ( \
103 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
104 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
105 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
106 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
107 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
108 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
109 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
110 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
111 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
112 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
113 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
114 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
115 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
116 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
118 static int eth_i40e_dev_init(\
119 __attribute__((unused)) struct eth_driver *eth_drv,
120 struct rte_eth_dev *eth_dev);
121 static int i40e_dev_configure(struct rte_eth_dev *dev);
122 static int i40e_dev_start(struct rte_eth_dev *dev);
123 static void i40e_dev_stop(struct rte_eth_dev *dev);
124 static void i40e_dev_close(struct rte_eth_dev *dev);
125 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
126 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
127 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
128 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
129 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
130 struct rte_eth_stats *stats);
131 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
132 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
136 static void i40e_dev_info_get(struct rte_eth_dev *dev,
137 struct rte_eth_dev_info *dev_info);
138 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
141 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
142 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
143 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
146 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
147 static int i40e_dev_led_on(struct rte_eth_dev *dev);
148 static int i40e_dev_led_off(struct rte_eth_dev *dev);
149 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
150 struct rte_eth_fc_conf *fc_conf);
151 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
152 struct rte_eth_pfc_conf *pfc_conf);
153 static void i40e_macaddr_add(struct rte_eth_dev *dev,
154 struct ether_addr *mac_addr,
157 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
158 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
159 struct rte_eth_rss_reta *reta_conf);
160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
161 struct rte_eth_rss_reta *reta_conf);
163 static int i40e_get_cap(struct i40e_hw *hw);
164 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
165 static int i40e_pf_setup(struct i40e_pf *pf);
166 static int i40e_vsi_init(struct i40e_vsi *vsi);
167 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
168 bool offset_loaded, uint64_t *offset, uint64_t *stat);
169 static void i40e_stat_update_48(struct i40e_hw *hw,
175 static void i40e_pf_config_irq0(struct i40e_hw *hw);
176 static void i40e_dev_interrupt_handler(
177 __rte_unused struct rte_intr_handle *handle, void *param);
178 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
179 uint32_t base, uint32_t num);
180 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
181 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
183 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
185 static int i40e_vsi_init_vlan(struct i40e_vsi *vsi);
186 static int i40e_veb_release(struct i40e_veb *veb);
187 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
188 struct i40e_vsi *vsi);
189 static int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
190 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
191 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
192 static int i40e_pf_disable_all_queues(struct i40e_hw *hw);
193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
194 struct i40e_macvlan_filter *mv_f,
196 struct ether_addr *addr);
197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
198 struct i40e_macvlan_filter *mv_f,
201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
203 struct rte_eth_rss_conf *rss_conf);
204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
205 struct rte_eth_rss_conf *rss_conf);
207 /* Default hash key buffer for RSS */
208 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
210 static struct rte_pci_id pci_id_i40e_map[] = {
211 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
212 #include "rte_pci_dev_ids.h"
213 { .vendor_id = 0, /* sentinel */ },
216 static struct eth_dev_ops i40e_eth_dev_ops = {
217 .dev_configure = i40e_dev_configure,
218 .dev_start = i40e_dev_start,
219 .dev_stop = i40e_dev_stop,
220 .dev_close = i40e_dev_close,
221 .promiscuous_enable = i40e_dev_promiscuous_enable,
222 .promiscuous_disable = i40e_dev_promiscuous_disable,
223 .allmulticast_enable = i40e_dev_allmulticast_enable,
224 .allmulticast_disable = i40e_dev_allmulticast_disable,
225 .link_update = i40e_dev_link_update,
226 .stats_get = i40e_dev_stats_get,
227 .stats_reset = i40e_dev_stats_reset,
228 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
229 .dev_infos_get = i40e_dev_info_get,
230 .vlan_filter_set = i40e_vlan_filter_set,
231 .vlan_tpid_set = i40e_vlan_tpid_set,
232 .vlan_offload_set = i40e_vlan_offload_set,
233 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
234 .vlan_pvid_set = i40e_vlan_pvid_set,
235 .rx_queue_setup = i40e_dev_rx_queue_setup,
236 .rx_queue_release = i40e_dev_rx_queue_release,
237 .rx_queue_count = i40e_dev_rx_queue_count,
238 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
239 .tx_queue_setup = i40e_dev_tx_queue_setup,
240 .tx_queue_release = i40e_dev_tx_queue_release,
241 .dev_led_on = i40e_dev_led_on,
242 .dev_led_off = i40e_dev_led_off,
243 .flow_ctrl_set = i40e_flow_ctrl_set,
244 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
245 .mac_addr_add = i40e_macaddr_add,
246 .mac_addr_remove = i40e_macaddr_remove,
247 .reta_update = i40e_dev_rss_reta_update,
248 .reta_query = i40e_dev_rss_reta_query,
249 .rss_hash_update = i40e_dev_rss_hash_update,
250 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
253 static struct eth_driver rte_i40e_pmd = {
255 .name = "rte_i40e_pmd",
256 .id_table = pci_id_i40e_map,
257 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
259 .eth_dev_init = eth_i40e_dev_init,
260 .dev_private_size = sizeof(struct i40e_adapter),
264 i40e_prev_power_of_2(int n)
282 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
283 struct rte_eth_link *link)
285 struct rte_eth_link *dst = link;
286 struct rte_eth_link *src = &(dev->data->dev_link);
288 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
289 *(uint64_t *)src) == 0)
296 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
297 struct rte_eth_link *link)
299 struct rte_eth_link *dst = &(dev->data->dev_link);
300 struct rte_eth_link *src = link;
302 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
303 *(uint64_t *)src) == 0)
310 * Driver initialization routine.
311 * Invoked once at EAL init time.
312 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
315 rte_i40e_pmd_init(const char *name __rte_unused,
316 const char *params __rte_unused)
318 PMD_INIT_FUNC_TRACE();
319 rte_eth_driver_register(&rte_i40e_pmd);
324 static struct rte_driver rte_i40e_driver = {
326 .init = rte_i40e_pmd_init,
329 PMD_REGISTER_DRIVER(rte_i40e_driver);
332 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
333 struct rte_eth_dev *dev)
335 struct rte_pci_device *pci_dev;
336 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
337 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
338 struct i40e_vsi *vsi;
343 PMD_INIT_FUNC_TRACE();
345 dev->dev_ops = &i40e_eth_dev_ops;
346 dev->rx_pkt_burst = i40e_recv_pkts;
347 dev->tx_pkt_burst = i40e_xmit_pkts;
349 /* for secondary processes, we don't initialise any further as primary
350 * has already done this work. Only check we don't need a different
352 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
353 if (dev->data->scattered_rx)
354 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
357 pci_dev = dev->pci_dev;
358 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
359 pf->adapter->eth_dev = dev;
360 pf->dev_data = dev->data;
362 hw->back = I40E_PF_TO_ADAPTER(pf);
363 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
365 PMD_INIT_LOG(ERR, "Hardware is not available, "
366 "as address is NULL\n");
370 hw->vendor_id = pci_dev->id.vendor_id;
371 hw->device_id = pci_dev->id.device_id;
372 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
373 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
374 hw->bus.device = pci_dev->addr.devid;
375 hw->bus.func = pci_dev->addr.function;
377 /* Disable all queues before PF reset, as required */
378 ret = i40e_pf_disable_all_queues(hw);
379 if (ret != I40E_SUCCESS) {
380 PMD_INIT_LOG(ERR, "Failed to disable queues %u\n", ret);
384 /* Reset here to make sure all is clean for each PF */
385 ret = i40e_pf_reset(hw);
387 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
391 /* Initialize the shared code */
392 ret = i40e_init_shared_code(hw);
394 PMD_INIT_LOG(ERR, "Failed to init shared code: %d", ret);
398 /* Initialize the parameters for adminq */
399 i40e_init_adminq_parameter(hw);
400 ret = i40e_init_adminq(hw);
401 if (ret != I40E_SUCCESS) {
402 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
405 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
406 "%02d.%02d.%02d eetrack %04x\n",
407 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
408 hw->aq.api_maj_ver, hw->aq.api_min_ver,
409 ((hw->nvm.version >> 12) & 0xf),
410 ((hw->nvm.version >> 4) & 0xff),
411 (hw->nvm.version & 0xf), hw->nvm.eetrack);
414 ret = i40e_aq_stop_lldp(hw, true, NULL);
415 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
416 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
419 i40e_clear_pxe_mode(hw);
421 /* Get hw capabilities */
422 ret = i40e_get_cap(hw);
423 if (ret != I40E_SUCCESS) {
424 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
425 goto err_get_capabilities;
428 /* Initialize parameters for PF */
429 ret = i40e_pf_parameter_init(dev);
431 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
432 goto err_parameter_init;
435 /* Initialize the queue management */
436 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
438 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
439 goto err_qp_pool_init;
441 ret = i40e_res_pool_init(&pf->msix_pool, 1,
442 hw->func_caps.num_msix_vectors - 1);
444 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
445 goto err_msix_pool_init;
448 /* Initialize lan hmc */
449 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
450 hw->func_caps.num_rx_qp, 0, 0);
451 if (ret != I40E_SUCCESS) {
452 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
453 goto err_init_lan_hmc;
456 /* Configure lan hmc */
457 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
458 if (ret != I40E_SUCCESS) {
459 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
460 goto err_configure_lan_hmc;
463 /* Get and check the mac address */
464 i40e_get_mac_addr(hw, hw->mac.addr);
465 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
466 PMD_INIT_LOG(ERR, "mac address is not valid");
468 goto err_get_mac_addr;
470 /* Copy the permanent MAC address */
471 ether_addr_copy((struct ether_addr *) hw->mac.addr,
472 (struct ether_addr *) hw->mac.perm_addr);
474 /* Disable flow control */
475 hw->fc.requested_mode = I40E_FC_NONE;
476 i40e_set_fc(hw, &aq_fail, TRUE);
478 /* PF setup, which includes VSI setup */
479 ret = i40e_pf_setup(pf);
481 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
482 goto err_setup_pf_switch;
486 if (!vsi->max_macaddrs)
487 len = ETHER_ADDR_LEN;
489 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
491 /* Should be after VSI initialized */
492 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
493 if (!dev->data->mac_addrs) {
494 PMD_INIT_LOG(ERR, "Failed to allocated memory "
495 "for storing mac address");
496 goto err_get_mac_addr;
498 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
499 &dev->data->mac_addrs[0]);
501 /* initialize pf host driver to setup SRIOV resource if applicable */
502 i40e_pf_host_init(dev);
504 /* register callback func to eal lib */
505 rte_intr_callback_register(&(pci_dev->intr_handle),
506 i40e_dev_interrupt_handler, (void *)dev);
508 /* configure and enable device interrupt */
509 i40e_pf_config_irq0(hw);
510 i40e_pf_enable_irq0(hw);
512 /* enable uio intr after callback register */
513 rte_intr_enable(&(pci_dev->intr_handle));
518 rte_free(pf->main_vsi);
520 err_configure_lan_hmc:
521 (void)i40e_shutdown_lan_hmc(hw);
523 i40e_res_pool_destroy(&pf->msix_pool);
525 i40e_res_pool_destroy(&pf->qp_pool);
528 err_get_capabilities:
529 (void)i40e_shutdown_adminq(hw);
535 i40e_dev_configure(struct rte_eth_dev *dev)
537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
538 struct i40e_vsi *vsi = pf->main_vsi;
541 ret = i40e_vsi_init_vlan(vsi);
547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
549 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
550 uint16_t msix_vect = vsi->msix_intr;
553 for (i = 0; i < vsi->nb_qps; i++) {
554 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
555 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
559 if (vsi->type != I40E_VSI_SRIOV) {
560 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
561 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
565 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
566 vsi->user_param + (msix_vect - 1);
568 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
570 I40E_WRITE_FLUSH(hw);
573 static inline uint16_t
574 i40e_calc_itr_interval(int16_t interval)
576 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
577 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
579 /* Convert to hardware count, as writing each 1 represents 2 us */
584 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
587 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
588 uint16_t msix_vect = vsi->msix_intr;
589 uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
592 for (i = 0; i < vsi->nb_qps; i++)
593 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
595 /* Bind all RX queues to allocated MSIX interrupt */
596 for (i = 0; i < vsi->nb_qps; i++) {
597 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
598 (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
599 ((vsi->base_queue + i + 1) <<
600 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
601 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
602 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
604 if (i == vsi->nb_qps - 1)
605 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
609 /* Write first RX queue to Link list register as the head element */
610 if (vsi->type != I40E_VSI_SRIOV) {
611 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
612 (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
613 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
615 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
616 msix_vect - 1), interval);
618 /* Disable auto-mask on enabling of all none-zero interrupt */
619 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
620 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
624 /* num_msix_vectors_vf needs to minus irq0 */
625 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
626 vsi->user_param + (msix_vect - 1);
628 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
629 (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
630 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
633 I40E_WRITE_FLUSH(hw);
637 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
639 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
640 uint16_t interval = i40e_calc_itr_interval(\
641 RTE_LIBRTE_I40E_ITR_INTERVAL);
643 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
644 I40E_PFINT_DYN_CTLN_INTENA_MASK |
645 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
646 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
647 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
651 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
653 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
655 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
659 i40e_dev_start(struct rte_eth_dev *dev)
661 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
663 struct i40e_vsi *vsi = pf->main_vsi;
667 ret = i40e_vsi_init(vsi);
668 if (ret != I40E_SUCCESS) {
669 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
673 /* Map queues with MSIX interrupt */
674 i40e_vsi_queues_bind_intr(vsi);
675 i40e_vsi_enable_queues_intr(vsi);
677 /* Enable all queues which have been configured */
678 ret = i40e_vsi_switch_queues(vsi, TRUE);
679 if (ret != I40E_SUCCESS) {
680 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
684 /* Enable receiving broadcast packets */
685 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
686 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
687 if (ret != I40E_SUCCESS)
688 PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
694 i40e_vsi_switch_queues(vsi, FALSE);
695 i40e_dev_clear_queues(dev);
701 i40e_dev_stop(struct rte_eth_dev *dev)
703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
704 struct i40e_vsi *vsi = pf->main_vsi;
706 /* Disable all queues */
707 i40e_vsi_switch_queues(vsi, FALSE);
709 /* Clear all queues and release memory */
710 i40e_dev_clear_queues(dev);
712 /* un-map queues with interrupt registers */
713 i40e_vsi_disable_queues_intr(vsi);
714 i40e_vsi_queues_unbind_intr(vsi);
718 i40e_dev_close(struct rte_eth_dev *dev)
720 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
724 PMD_INIT_FUNC_TRACE();
728 /* Disable interrupt */
729 i40e_pf_disable_irq0(hw);
730 rte_intr_disable(&(dev->pci_dev->intr_handle));
732 /* shutdown and destroy the HMC */
733 i40e_shutdown_lan_hmc(hw);
735 /* release all the existing VSIs and VEBs */
736 i40e_vsi_release(pf->main_vsi);
738 /* shutdown the adminq */
739 i40e_aq_queue_shutdown(hw, true);
740 i40e_shutdown_adminq(hw);
742 i40e_res_pool_destroy(&pf->qp_pool);
743 i40e_res_pool_destroy(&pf->msix_pool);
745 /* force a PF reset to clean anything leftover */
746 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
747 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
748 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
749 I40E_WRITE_FLUSH(hw);
753 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
757 struct i40e_vsi *vsi = pf->main_vsi;
760 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
762 if (status != I40E_SUCCESS)
763 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
767 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
769 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
771 struct i40e_vsi *vsi = pf->main_vsi;
774 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
776 if (status != I40E_SUCCESS)
777 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
781 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
783 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
785 struct i40e_vsi *vsi = pf->main_vsi;
788 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
789 if (ret != I40E_SUCCESS)
790 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
794 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
798 struct i40e_vsi *vsi = pf->main_vsi;
801 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
802 vsi->seid, FALSE, NULL);
803 if (ret != I40E_SUCCESS)
804 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
808 i40e_dev_link_update(struct rte_eth_dev *dev,
809 __rte_unused int wait_to_complete)
811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
812 struct i40e_link_status link_status;
813 struct rte_eth_link link, old;
816 memset(&link, 0, sizeof(link));
817 memset(&old, 0, sizeof(old));
818 memset(&link_status, 0, sizeof(link_status));
819 rte_i40e_dev_atomic_read_link_status(dev, &old);
821 /* Get link status information from hardware */
822 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
823 if (status != I40E_SUCCESS) {
824 link.link_speed = ETH_LINK_SPEED_100;
825 link.link_duplex = ETH_LINK_FULL_DUPLEX;
826 PMD_DRV_LOG(ERR, "Failed to get link info\n");
830 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
832 if (!link.link_status)
835 /* i40e uses full duplex only */
836 link.link_duplex = ETH_LINK_FULL_DUPLEX;
838 /* Parse the link status */
839 switch (link_status.link_speed) {
840 case I40E_LINK_SPEED_100MB:
841 link.link_speed = ETH_LINK_SPEED_100;
843 case I40E_LINK_SPEED_1GB:
844 link.link_speed = ETH_LINK_SPEED_1000;
846 case I40E_LINK_SPEED_10GB:
847 link.link_speed = ETH_LINK_SPEED_10G;
849 case I40E_LINK_SPEED_20GB:
850 link.link_speed = ETH_LINK_SPEED_20G;
852 case I40E_LINK_SPEED_40GB:
853 link.link_speed = ETH_LINK_SPEED_40G;
856 link.link_speed = ETH_LINK_SPEED_100;
861 rte_i40e_dev_atomic_write_link_status(dev, &link);
862 if (link.link_status == old.link_status)
868 /* Get all the statistics of a VSI */
870 i40e_update_vsi_stats(struct i40e_vsi *vsi)
872 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
873 struct i40e_eth_stats *nes = &vsi->eth_stats;
874 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
875 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
877 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
878 vsi->offset_loaded, &oes->rx_bytes,
880 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
881 vsi->offset_loaded, &oes->rx_unicast,
883 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
884 vsi->offset_loaded, &oes->rx_multicast,
886 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
887 vsi->offset_loaded, &oes->rx_broadcast,
889 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
890 &oes->rx_discards, &nes->rx_discards);
891 /* GLV_REPC not supported */
892 /* GLV_RMPC not supported */
893 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
894 &oes->rx_unknown_protocol,
895 &nes->rx_unknown_protocol);
896 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
897 vsi->offset_loaded, &oes->tx_bytes,
899 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
900 vsi->offset_loaded, &oes->tx_unicast,
902 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
903 vsi->offset_loaded, &oes->tx_multicast,
905 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
906 vsi->offset_loaded, &oes->tx_broadcast,
908 /* GLV_TDPC not supported */
909 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
910 &oes->tx_errors, &nes->tx_errors);
911 vsi->offset_loaded = true;
913 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
914 printf("***************** VSI[%u] stats start *******************\n",
916 printf("rx_bytes: %lu\n", nes->rx_bytes);
917 printf("rx_unicast: %lu\n", nes->rx_unicast);
918 printf("rx_multicast: %lu\n", nes->rx_multicast);
919 printf("rx_broadcast: %lu\n", nes->rx_broadcast);
920 printf("rx_discards: %lu\n", nes->rx_discards);
921 printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
922 printf("tx_bytes: %lu\n", nes->tx_bytes);
923 printf("tx_unicast: %lu\n", nes->tx_unicast);
924 printf("tx_multicast: %lu\n", nes->tx_multicast);
925 printf("tx_broadcast: %lu\n", nes->tx_broadcast);
926 printf("tx_discards: %lu\n", nes->tx_discards);
927 printf("tx_errors: %lu\n", nes->tx_errors);
928 printf("***************** VSI[%u] stats end *******************\n",
930 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
933 /* Get all statistics of a port */
935 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
940 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
941 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
943 /* Get statistics of struct i40e_eth_stats */
944 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
945 I40E_GLPRT_GORCL(hw->port),
946 pf->offset_loaded, &os->eth.rx_bytes,
948 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
949 I40E_GLPRT_UPRCL(hw->port),
950 pf->offset_loaded, &os->eth.rx_unicast,
951 &ns->eth.rx_unicast);
952 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
953 I40E_GLPRT_MPRCL(hw->port),
954 pf->offset_loaded, &os->eth.rx_multicast,
955 &ns->eth.rx_multicast);
956 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
957 I40E_GLPRT_BPRCL(hw->port),
958 pf->offset_loaded, &os->eth.rx_broadcast,
959 &ns->eth.rx_broadcast);
960 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
961 pf->offset_loaded, &os->eth.rx_discards,
962 &ns->eth.rx_discards);
963 /* GLPRT_REPC not supported */
964 /* GLPRT_RMPC not supported */
965 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
967 &os->eth.rx_unknown_protocol,
968 &ns->eth.rx_unknown_protocol);
969 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
970 I40E_GLPRT_GOTCL(hw->port),
971 pf->offset_loaded, &os->eth.tx_bytes,
973 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
974 I40E_GLPRT_UPTCL(hw->port),
975 pf->offset_loaded, &os->eth.tx_unicast,
976 &ns->eth.tx_unicast);
977 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
978 I40E_GLPRT_MPTCL(hw->port),
979 pf->offset_loaded, &os->eth.tx_multicast,
980 &ns->eth.tx_multicast);
981 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
982 I40E_GLPRT_BPTCL(hw->port),
983 pf->offset_loaded, &os->eth.tx_broadcast,
984 &ns->eth.tx_broadcast);
985 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
986 pf->offset_loaded, &os->eth.tx_discards,
987 &ns->eth.tx_discards);
988 /* GLPRT_TEPC not supported */
990 /* additional port specific stats */
991 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
992 pf->offset_loaded, &os->tx_dropped_link_down,
993 &ns->tx_dropped_link_down);
994 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
995 pf->offset_loaded, &os->crc_errors,
997 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
998 pf->offset_loaded, &os->illegal_bytes,
1000 /* GLPRT_ERRBC not supported */
1001 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1002 pf->offset_loaded, &os->mac_local_faults,
1003 &ns->mac_local_faults);
1004 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1005 pf->offset_loaded, &os->mac_remote_faults,
1006 &ns->mac_remote_faults);
1007 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1008 pf->offset_loaded, &os->rx_length_errors,
1009 &ns->rx_length_errors);
1010 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1011 pf->offset_loaded, &os->link_xon_rx,
1013 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1014 pf->offset_loaded, &os->link_xoff_rx,
1016 for (i = 0; i < 8; i++) {
1017 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1019 &os->priority_xon_rx[i],
1020 &ns->priority_xon_rx[i]);
1021 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1023 &os->priority_xoff_rx[i],
1024 &ns->priority_xoff_rx[i]);
1026 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1027 pf->offset_loaded, &os->link_xon_tx,
1029 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1030 pf->offset_loaded, &os->link_xoff_tx,
1032 for (i = 0; i < 8; i++) {
1033 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1035 &os->priority_xon_tx[i],
1036 &ns->priority_xon_tx[i]);
1037 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1039 &os->priority_xoff_tx[i],
1040 &ns->priority_xoff_tx[i]);
1041 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1043 &os->priority_xon_2_xoff[i],
1044 &ns->priority_xon_2_xoff[i]);
1046 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1047 I40E_GLPRT_PRC64L(hw->port),
1048 pf->offset_loaded, &os->rx_size_64,
1050 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1051 I40E_GLPRT_PRC127L(hw->port),
1052 pf->offset_loaded, &os->rx_size_127,
1054 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1055 I40E_GLPRT_PRC255L(hw->port),
1056 pf->offset_loaded, &os->rx_size_255,
1058 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1059 I40E_GLPRT_PRC511L(hw->port),
1060 pf->offset_loaded, &os->rx_size_511,
1062 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1063 I40E_GLPRT_PRC1023L(hw->port),
1064 pf->offset_loaded, &os->rx_size_1023,
1066 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1067 I40E_GLPRT_PRC1522L(hw->port),
1068 pf->offset_loaded, &os->rx_size_1522,
1070 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1071 I40E_GLPRT_PRC9522L(hw->port),
1072 pf->offset_loaded, &os->rx_size_big,
1074 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->offset_loaded, &os->rx_undersize,
1077 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->offset_loaded, &os->rx_fragments,
1080 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->offset_loaded, &os->rx_oversize,
1083 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->offset_loaded, &os->rx_jabber,
1086 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1087 I40E_GLPRT_PTC64L(hw->port),
1088 pf->offset_loaded, &os->tx_size_64,
1090 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1091 I40E_GLPRT_PTC127L(hw->port),
1092 pf->offset_loaded, &os->tx_size_127,
1094 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1095 I40E_GLPRT_PTC255L(hw->port),
1096 pf->offset_loaded, &os->tx_size_255,
1098 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1099 I40E_GLPRT_PTC511L(hw->port),
1100 pf->offset_loaded, &os->tx_size_511,
1102 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1103 I40E_GLPRT_PTC1023L(hw->port),
1104 pf->offset_loaded, &os->tx_size_1023,
1106 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1107 I40E_GLPRT_PTC1522L(hw->port),
1108 pf->offset_loaded, &os->tx_size_1522,
1110 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1111 I40E_GLPRT_PTC9522L(hw->port),
1112 pf->offset_loaded, &os->tx_size_big,
1114 /* GLPRT_MSPDC not supported */
1115 /* GLPRT_XEC not supported */
1117 pf->offset_loaded = true;
1119 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1120 ns->eth.rx_broadcast;
1121 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1122 ns->eth.tx_broadcast;
1123 stats->ibytes = ns->eth.rx_bytes;
1124 stats->obytes = ns->eth.tx_bytes;
1125 stats->oerrors = ns->eth.tx_errors;
1126 stats->imcasts = ns->eth.rx_multicast;
1129 i40e_update_vsi_stats(pf->main_vsi);
1131 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1132 printf("***************** PF stats start *******************\n");
1133 printf("rx_bytes: %lu\n", ns->eth.rx_bytes);
1134 printf("rx_unicast: %lu\n", ns->eth.rx_unicast);
1135 printf("rx_multicast: %lu\n", ns->eth.rx_multicast);
1136 printf("rx_broadcast: %lu\n", ns->eth.rx_broadcast);
1137 printf("rx_discards: %lu\n", ns->eth.rx_discards);
1138 printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1139 printf("tx_bytes: %lu\n", ns->eth.tx_bytes);
1140 printf("tx_unicast: %lu\n", ns->eth.tx_unicast);
1141 printf("tx_multicast: %lu\n", ns->eth.tx_multicast);
1142 printf("tx_broadcast: %lu\n", ns->eth.tx_broadcast);
1143 printf("tx_discards: %lu\n", ns->eth.tx_discards);
1144 printf("tx_errors: %lu\n", ns->eth.tx_errors);
1146 printf("tx_dropped_link_down: %lu\n", ns->tx_dropped_link_down);
1147 printf("crc_errors: %lu\n", ns->crc_errors);
1148 printf("illegal_bytes: %lu\n", ns->illegal_bytes);
1149 printf("error_bytes: %lu\n", ns->error_bytes);
1150 printf("mac_local_faults: %lu\n", ns->mac_local_faults);
1151 printf("mac_remote_faults: %lu\n", ns->mac_remote_faults);
1152 printf("rx_length_errors: %lu\n", ns->rx_length_errors);
1153 printf("link_xon_rx: %lu\n", ns->link_xon_rx);
1154 printf("link_xoff_rx: %lu\n", ns->link_xoff_rx);
1155 for (i = 0; i < 8; i++) {
1156 printf("priority_xon_rx[%d]: %lu\n",
1157 i, ns->priority_xon_rx[i]);
1158 printf("priority_xoff_rx[%d]: %lu\n",
1159 i, ns->priority_xoff_rx[i]);
1161 printf("link_xon_tx: %lu\n", ns->link_xon_tx);
1162 printf("link_xoff_tx: %lu\n", ns->link_xoff_tx);
1163 for (i = 0; i < 8; i++) {
1164 printf("priority_xon_tx[%d]: %lu\n",
1165 i, ns->priority_xon_tx[i]);
1166 printf("priority_xoff_tx[%d]: %lu\n",
1167 i, ns->priority_xoff_tx[i]);
1168 printf("priority_xon_2_xoff[%d]: %lu\n",
1169 i, ns->priority_xon_2_xoff[i]);
1171 printf("rx_size_64: %lu\n", ns->rx_size_64);
1172 printf("rx_size_127: %lu\n", ns->rx_size_127);
1173 printf("rx_size_255: %lu\n", ns->rx_size_255);
1174 printf("rx_size_511: %lu\n", ns->rx_size_511);
1175 printf("rx_size_1023: %lu\n", ns->rx_size_1023);
1176 printf("rx_size_1522: %lu\n", ns->rx_size_1522);
1177 printf("rx_size_big: %lu\n", ns->rx_size_big);
1178 printf("rx_undersize: %lu\n", ns->rx_undersize);
1179 printf("rx_fragments: %lu\n", ns->rx_fragments);
1180 printf("rx_oversize: %lu\n", ns->rx_oversize);
1181 printf("rx_jabber: %lu\n", ns->rx_jabber);
1182 printf("tx_size_64: %lu\n", ns->tx_size_64);
1183 printf("tx_size_127: %lu\n", ns->tx_size_127);
1184 printf("tx_size_255: %lu\n", ns->tx_size_255);
1185 printf("tx_size_511: %lu\n", ns->tx_size_511);
1186 printf("tx_size_1023: %lu\n", ns->tx_size_1023);
1187 printf("tx_size_1522: %lu\n", ns->tx_size_1522);
1188 printf("tx_size_big: %lu\n", ns->tx_size_big);
1189 printf("mac_short_packet_dropped: %lu\n",
1190 ns->mac_short_packet_dropped);
1191 printf("checksum_error: %lu\n", ns->checksum_error);
1192 printf("***************** PF stats end ********************\n");
1193 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1196 /* Reset the statistics */
1198 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1202 /* It results in reloading the start point of each counter */
1203 pf->offset_loaded = false;
1207 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1208 __rte_unused uint16_t queue_id,
1209 __rte_unused uint8_t stat_idx,
1210 __rte_unused uint8_t is_rx)
1212 PMD_INIT_FUNC_TRACE();
1218 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1220 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1221 struct i40e_vsi *vsi = pf->main_vsi;
1223 dev_info->max_rx_queues = vsi->nb_qps;
1224 dev_info->max_tx_queues = vsi->nb_qps;
1225 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1226 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1227 dev_info->max_mac_addrs = vsi->max_macaddrs;
1228 dev_info->max_vfs = dev->pci_dev->max_vfs;
1229 dev_info->rx_offload_capa =
1230 DEV_RX_OFFLOAD_VLAN_STRIP |
1231 DEV_RX_OFFLOAD_IPV4_CKSUM |
1232 DEV_RX_OFFLOAD_UDP_CKSUM |
1233 DEV_RX_OFFLOAD_TCP_CKSUM;
1234 dev_info->tx_offload_capa =
1235 DEV_TX_OFFLOAD_VLAN_INSERT |
1236 DEV_TX_OFFLOAD_IPV4_CKSUM |
1237 DEV_TX_OFFLOAD_UDP_CKSUM |
1238 DEV_TX_OFFLOAD_TCP_CKSUM |
1239 DEV_TX_OFFLOAD_SCTP_CKSUM;
1243 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246 struct i40e_vsi *vsi = pf->main_vsi;
1247 PMD_INIT_FUNC_TRACE();
1250 return i40e_vsi_add_vlan(vsi, vlan_id);
1252 return i40e_vsi_delete_vlan(vsi, vlan_id);
1256 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1257 __rte_unused uint16_t tpid)
1259 PMD_INIT_FUNC_TRACE();
1263 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1265 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1266 struct i40e_vsi *vsi = pf->main_vsi;
1268 if (mask & ETH_VLAN_STRIP_MASK) {
1269 /* Enable or disable VLAN stripping */
1270 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1271 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1273 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1276 if (mask & ETH_VLAN_EXTEND_MASK) {
1277 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1278 i40e_vsi_config_double_vlan(vsi, TRUE);
1280 i40e_vsi_config_double_vlan(vsi, FALSE);
1285 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1286 __rte_unused uint16_t queue,
1287 __rte_unused int on)
1289 PMD_INIT_FUNC_TRACE();
1293 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1296 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1297 struct i40e_vsi *vsi = pf->main_vsi;
1298 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1299 struct i40e_vsi_context ctxt;
1300 uint8_t vlan_flags = 0;
1305 * If insert pvid is enabled, only tagged pkts are
1306 * allowed to be sent out.
1308 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
1309 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
1311 if (data->dev_conf.txmode.hw_vlan_reject_tagged == 0)
1312 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
1313 if (data->dev_conf.txmode.hw_vlan_reject_untagged == 0)
1314 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
1316 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
1317 I40E_AQ_VSI_PVLAN_MODE_MASK);
1318 vsi->info.port_vlan_flags |= vlan_flags;
1319 vsi->info.pvid = pvid;
1320 vsi->info.valid_sections =
1321 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
1322 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1323 ctxt.seid = vsi->seid;
1324 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
1325 if (ret != I40E_SUCCESS)
1326 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
1332 i40e_dev_led_on(struct rte_eth_dev *dev)
1334 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335 uint32_t mode = i40e_led_get(hw);
1338 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1344 i40e_dev_led_off(struct rte_eth_dev *dev)
1346 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347 uint32_t mode = i40e_led_get(hw);
1350 i40e_led_set(hw, 0, false);
1356 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1357 __rte_unused struct rte_eth_fc_conf *fc_conf)
1359 PMD_INIT_FUNC_TRACE();
1365 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1366 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1368 PMD_INIT_FUNC_TRACE();
1373 /* Add a MAC address, and update filters */
1375 i40e_macaddr_add(struct rte_eth_dev *dev,
1376 struct ether_addr *mac_addr,
1377 __attribute__((unused)) uint32_t index,
1378 __attribute__((unused)) uint32_t pool)
1380 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1381 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382 struct i40e_vsi *vsi = pf->main_vsi;
1383 struct ether_addr old_mac;
1386 if (!is_valid_assigned_ether_addr(mac_addr)) {
1387 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1391 if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1392 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1396 /* Write mac address */
1397 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1398 mac_addr->addr_bytes, NULL);
1399 if (ret != I40E_SUCCESS) {
1400 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1404 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1405 (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1408 ret = i40e_vsi_add_mac(vsi, mac_addr);
1409 if (ret != I40E_SUCCESS) {
1410 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1414 ether_addr_copy(mac_addr, &pf->dev_addr);
1415 i40e_vsi_delete_mac(vsi, &old_mac);
1418 /* Remove a MAC address, and update filters */
1420 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1422 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1423 struct i40e_vsi *vsi = pf->main_vsi;
1424 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1425 struct ether_addr *macaddr;
1427 struct i40e_hw *hw =
1428 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1430 if (index >= vsi->max_macaddrs)
1433 macaddr = &(data->mac_addrs[index]);
1434 if (!is_valid_assigned_ether_addr(macaddr))
1437 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1438 hw->mac.perm_addr, NULL);
1439 if (ret != I40E_SUCCESS) {
1440 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1444 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1446 ret = i40e_vsi_delete_mac(vsi, macaddr);
1447 if (ret != I40E_SUCCESS)
1450 /* Clear device address as it has been removed */
1451 if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1452 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1456 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1457 struct rte_eth_rss_reta *reta_conf)
1459 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1463 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1465 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1467 mask = (uint8_t)((reta_conf->mask_hi >>
1476 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1478 for (j = 0, lut = 0; j < 4; j++) {
1479 if (mask & (0x1 < j))
1480 lut |= reta_conf->reta[i + j] << (8 * j);
1482 lut |= l & (0xFF << (8 * j));
1484 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1491 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1492 struct rte_eth_rss_reta *reta_conf)
1494 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1498 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1500 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1502 mask = (uint8_t)((reta_conf->mask_hi >>
1508 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1509 for (j = 0; j < 4; j++) {
1510 if (mask & (0x1 << j))
1511 reta_conf->reta[i + j] =
1512 (uint8_t)((lut >> (8 * j)) & 0xFF);
1520 * i40e_allocate_dma_mem_d - specific memory alloc for shared code
1521 * @hw: pointer to the HW structure
1522 * @mem: pointer to mem struct to fill out
1523 * @size: size of memory requested
1524 * @alignment: what to align the allocation to
1526 enum i40e_status_code
1527 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1528 struct i40e_dma_mem *mem,
1532 static uint64_t id = 0;
1533 const struct rte_memzone *mz = NULL;
1534 char z_name[RTE_MEMZONE_NAMESIZE];
1537 return I40E_ERR_PARAM;
1540 rte_snprintf(z_name, sizeof(z_name), "i40e_dma_%lu", id);
1541 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1543 return I40E_ERR_NO_MEMORY;
1548 mem->pa = mz->phys_addr;
1550 return I40E_SUCCESS;
1554 * i40e_free_dma_mem_d - specific memory free for shared code
1555 * @hw: pointer to the HW structure
1556 * @mem: ptr to mem struct to free
1558 enum i40e_status_code
1559 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1560 struct i40e_dma_mem *mem)
1562 if (!mem || !mem->va)
1563 return I40E_ERR_PARAM;
1568 return I40E_SUCCESS;
1572 * i40e_allocate_virt_mem_d - specific memory alloc for shared code
1573 * @hw: pointer to the HW structure
1574 * @mem: pointer to mem struct to fill out
1575 * @size: size of memory requested
1577 enum i40e_status_code
1578 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1579 struct i40e_virt_mem *mem,
1583 return I40E_ERR_PARAM;
1586 mem->va = rte_zmalloc("i40e", size, 0);
1589 return I40E_SUCCESS;
1591 return I40E_ERR_NO_MEMORY;
1595 * i40e_free_virt_mem_d - specific memory free for shared code
1596 * @hw: pointer to the HW structure
1597 * @mem: pointer to mem struct to free
1599 enum i40e_status_code
1600 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1601 struct i40e_virt_mem *mem)
1604 return I40E_ERR_PARAM;
1609 return I40E_SUCCESS;
1613 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1615 rte_spinlock_init(&sp->spinlock);
1619 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1621 rte_spinlock_lock(&sp->spinlock);
1625 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1627 rte_spinlock_unlock(&sp->spinlock);
1631 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1637 * Get the hardware capabilities, which will be parsed
1638 * and saved into struct i40e_hw.
1641 i40e_get_cap(struct i40e_hw *hw)
1643 struct i40e_aqc_list_capabilities_element_resp *buf;
1644 uint16_t len, size = 0;
1647 /* Calculate a huge enough buff for saving response data temporarily */
1648 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1649 I40E_MAX_CAP_ELE_NUM;
1650 buf = rte_zmalloc("i40e", len, 0);
1652 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1653 return I40E_ERR_NO_MEMORY;
1656 /* Get, parse the capabilities and save it to hw */
1657 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1658 i40e_aqc_opc_list_func_capabilities, NULL);
1659 if (ret != I40E_SUCCESS)
1660 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1662 /* Free the temporary buffer after being used */
1669 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1671 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1672 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1673 uint16_t sum_queues = 0, sum_vsis;
1675 /* First check if FW support SRIOV */
1676 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1677 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1681 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1682 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1683 PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1684 /* Allocate queues for pf */
1685 if (hw->func_caps.rss) {
1686 pf->flags |= I40E_FLAG_RSS;
1687 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1688 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1689 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1692 sum_queues = pf->lan_nb_qps;
1693 /* Default VSI is not counted in */
1695 PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1697 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1698 pf->flags |= I40E_FLAG_SRIOV;
1699 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1700 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1701 PMD_INIT_LOG(ERR, "Config VF number %u, "
1702 "max supported %u.\n", dev->pci_dev->max_vfs,
1703 hw->func_caps.num_vfs);
1706 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1707 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1708 "max support %u queues.\n", pf->vf_nb_qps,
1709 I40E_MAX_QP_NUM_PER_VF);
1712 pf->vf_num = dev->pci_dev->max_vfs;
1713 sum_queues += pf->vf_nb_qps * pf->vf_num;
1714 sum_vsis += pf->vf_num;
1715 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1716 pf->vf_num, pf->vf_nb_qps);
1720 if (hw->func_caps.vmdq) {
1721 pf->flags |= I40E_FLAG_VMDQ;
1722 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1723 sum_queues += pf->vmdq_nb_qps;
1725 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1728 if (hw->func_caps.fd) {
1729 pf->flags |= I40E_FLAG_FDIR;
1730 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1732 * Each flow director consumes one VSI and one queue,
1733 * but can't calculate out predictably here.
1737 if (sum_vsis > pf->max_num_vsi ||
1738 sum_queues > hw->func_caps.num_rx_qp) {
1739 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1740 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1741 pf->max_num_vsi, sum_vsis);
1742 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1743 hw->func_caps.num_rx_qp, sum_queues);
1747 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1748 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1749 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1750 sum_vsis, hw->func_caps.num_msix_vectors);
1753 return I40E_SUCCESS;
1757 i40e_pf_get_switch_config(struct i40e_pf *pf)
1759 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1760 struct i40e_aqc_get_switch_config_resp *switch_config;
1761 struct i40e_aqc_switch_config_element_resp *element;
1762 uint16_t start_seid = 0, num_reported;
1765 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1766 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1767 if (!switch_config) {
1768 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1772 /* Get the switch configurations */
1773 ret = i40e_aq_get_switch_config(hw, switch_config,
1774 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1775 if (ret != I40E_SUCCESS) {
1776 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1779 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1780 if (num_reported != 1) { /* The number should be 1 */
1781 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1785 /* Parse the switch configuration elements */
1786 element = &(switch_config->element[0]);
1787 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1788 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1789 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1791 PMD_DRV_LOG(INFO, "Unknown element type\n");
1794 rte_free(switch_config);
1800 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1803 struct pool_entry *entry;
1805 if (pool == NULL || num == 0)
1808 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1809 if (entry == NULL) {
1810 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1815 /* queue heap initialize */
1816 pool->num_free = num;
1817 pool->num_alloc = 0;
1819 LIST_INIT(&pool->alloc_list);
1820 LIST_INIT(&pool->free_list);
1822 /* Initialize element */
1826 LIST_INSERT_HEAD(&pool->free_list, entry, next);
1831 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1833 struct pool_entry *entry;
1838 LIST_FOREACH(entry, &pool->alloc_list, next) {
1839 LIST_REMOVE(entry, next);
1843 LIST_FOREACH(entry, &pool->free_list, next) {
1844 LIST_REMOVE(entry, next);
1849 pool->num_alloc = 0;
1851 LIST_INIT(&pool->alloc_list);
1852 LIST_INIT(&pool->free_list);
1856 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1859 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
1860 uint32_t pool_offset;
1864 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1868 pool_offset = base - pool->base;
1869 /* Lookup in alloc list */
1870 LIST_FOREACH(entry, &pool->alloc_list, next) {
1871 if (entry->base == pool_offset) {
1872 valid_entry = entry;
1873 LIST_REMOVE(entry, next);
1878 /* Not find, return */
1879 if (valid_entry == NULL) {
1880 PMD_DRV_LOG(ERR, "Failed to find entry\n");
1885 * Found it, move it to free list and try to merge.
1886 * In order to make merge easier, always sort it by qbase.
1887 * Find adjacent prev and last entries.
1890 LIST_FOREACH(entry, &pool->free_list, next) {
1891 if (entry->base > valid_entry->base) {
1899 /* Try to merge with next one*/
1901 /* Merge with next one */
1902 if (valid_entry->base + valid_entry->len == next->base) {
1903 next->base = valid_entry->base;
1904 next->len += valid_entry->len;
1905 rte_free(valid_entry);
1912 /* Merge with previous one */
1913 if (prev->base + prev->len == valid_entry->base) {
1914 prev->len += valid_entry->len;
1915 /* If it merge with next one, remove next node */
1917 LIST_REMOVE(valid_entry, next);
1918 rte_free(valid_entry);
1920 rte_free(valid_entry);
1926 /* Not find any entry to merge, insert */
1929 LIST_INSERT_AFTER(prev, valid_entry, next);
1930 else if (next != NULL)
1931 LIST_INSERT_BEFORE(next, valid_entry, next);
1932 else /* It's empty list, insert to head */
1933 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
1936 pool->num_free += valid_entry->len;
1937 pool->num_alloc -= valid_entry->len;
1943 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
1946 struct pool_entry *entry, *valid_entry;
1948 if (pool == NULL || num == 0) {
1949 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1953 if (pool->num_free < num) {
1954 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
1955 num, pool->num_free);
1960 /* Lookup in free list and find most fit one */
1961 LIST_FOREACH(entry, &pool->free_list, next) {
1962 if (entry->len >= num) {
1964 if (entry->len == num) {
1965 valid_entry = entry;
1968 if (valid_entry == NULL || valid_entry->len > entry->len)
1969 valid_entry = entry;
1973 /* Not find one to satisfy the request, return */
1974 if (valid_entry == NULL) {
1975 PMD_DRV_LOG(ERR, "No valid entry found\n");
1979 * The entry have equal queue number as requested,
1980 * remove it from alloc_list.
1982 if (valid_entry->len == num) {
1983 LIST_REMOVE(valid_entry, next);
1986 * The entry have more numbers than requested,
1987 * create a new entry for alloc_list and minus its
1988 * queue base and number in free_list.
1990 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
1991 if (entry == NULL) {
1992 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1996 entry->base = valid_entry->base;
1998 valid_entry->base += num;
1999 valid_entry->len -= num;
2000 valid_entry = entry;
2003 /* Insert it into alloc list, not sorted */
2004 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2006 pool->num_free -= valid_entry->len;
2007 pool->num_alloc += valid_entry->len;
2009 return (valid_entry->base + pool->base);
2013 * bitmap_is_subset - Check whether src2 is subset of src1
2016 bitmap_is_subset(uint8_t src1, uint8_t src2)
2018 return !((src1 ^ src2) & src2);
2022 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2024 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2026 /* If DCB is not supported, only default TC is supported */
2027 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2028 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2029 "only TC0 is supported\n");
2033 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2034 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2035 "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2039 return I40E_SUCCESS;
2043 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2045 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2047 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2049 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2050 if (ret != I40E_SUCCESS)
2054 PMD_DRV_LOG(ERR, "seid not valid\n");
2058 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2059 tc_bw_data.tc_valid_bits = enabled_tcmap;
2060 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2061 tc_bw_data.tc_bw_credits[i] =
2062 (enabled_tcmap & (1 << i)) ? 1 : 0;
2064 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2065 if (ret != I40E_SUCCESS) {
2066 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2070 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2071 sizeof(vsi->info.qs_handle));
2072 return I40E_SUCCESS;
2076 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2077 struct i40e_aqc_vsi_properties_data *info,
2078 uint8_t enabled_tcmap)
2080 int ret, total_tc = 0, i;
2081 uint16_t qpnum_per_tc, bsf, qp_idx;
2083 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2084 if (ret != I40E_SUCCESS)
2087 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2088 if (enabled_tcmap & (1 << i))
2090 vsi->enabled_tc = enabled_tcmap;
2092 /* Number of queues per enabled TC */
2093 qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2094 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2095 bsf = rte_bsf32(qpnum_per_tc);
2097 /* Adjust the queue number to actual queues that can be applied */
2098 vsi->nb_qps = qpnum_per_tc * total_tc;
2101 * Configure TC and queue mapping parameters, for enabled TC,
2102 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2103 * default queue will serve it.
2106 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2107 if (vsi->enabled_tc & (1 << i)) {
2108 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2109 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2110 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2111 qp_idx += qpnum_per_tc;
2113 info->tc_mapping[i] = 0;
2116 /* Associate queue number with VSI */
2117 if (vsi->type == I40E_VSI_SRIOV) {
2118 info->mapping_flags |=
2119 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2120 for (i = 0; i < vsi->nb_qps; i++)
2121 info->queue_mapping[i] =
2122 rte_cpu_to_le_16(vsi->base_queue + i);
2124 info->mapping_flags |=
2125 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2126 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2128 info->valid_sections =
2129 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2131 return I40E_SUCCESS;
2135 i40e_veb_release(struct i40e_veb *veb)
2137 struct i40e_vsi *vsi;
2140 if (veb == NULL || veb->associate_vsi == NULL)
2143 if (!TAILQ_EMPTY(&veb->head)) {
2144 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2148 vsi = veb->associate_vsi;
2149 hw = I40E_VSI_TO_HW(vsi);
2151 vsi->uplink_seid = veb->uplink_seid;
2152 i40e_aq_delete_element(hw, veb->seid, NULL);
2155 return I40E_SUCCESS;
2159 static struct i40e_veb *
2160 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2162 struct i40e_veb *veb;
2166 if (NULL == pf || vsi == NULL) {
2167 PMD_DRV_LOG(ERR, "veb setup failed, "
2168 "associated VSI shouldn't null\n");
2171 hw = I40E_PF_TO_HW(pf);
2173 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2175 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2179 veb->associate_vsi = vsi;
2180 TAILQ_INIT(&veb->head);
2181 veb->uplink_seid = vsi->uplink_seid;
2183 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2184 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2186 if (ret != I40E_SUCCESS) {
2187 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2188 hw->aq.asq_last_status);
2192 /* get statistics index */
2193 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2194 &veb->stats_idx, NULL, NULL, NULL);
2195 if (ret != I40E_SUCCESS) {
2196 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2197 hw->aq.asq_last_status);
2201 /* Get VEB bandwidth, to be implemented */
2202 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2203 vsi->uplink_seid = veb->seid;
2212 i40e_vsi_release(struct i40e_vsi *vsi)
2216 struct i40e_vsi_list *vsi_list;
2218 struct i40e_mac_filter *f;
2221 return I40E_SUCCESS;
2223 pf = I40E_VSI_TO_PF(vsi);
2224 hw = I40E_VSI_TO_HW(vsi);
2226 /* VSI has child to attach, release child first */
2228 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2229 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2231 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2233 i40e_veb_release(vsi->veb);
2236 /* Remove all macvlan filters of the VSI */
2237 i40e_vsi_remove_all_macvlan_filter(vsi);
2238 TAILQ_FOREACH(f, &vsi->mac_list, next)
2241 if (vsi->type != I40E_VSI_MAIN) {
2242 /* Remove vsi from parent's sibling list */
2243 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2244 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2245 return I40E_ERR_PARAM;
2247 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2248 &vsi->sib_vsi_list, list);
2250 /* Remove all switch element of the VSI */
2251 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2252 if (ret != I40E_SUCCESS)
2253 PMD_DRV_LOG(ERR, "Failed to delete element\n");
2255 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2257 if (vsi->type != I40E_VSI_SRIOV)
2258 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2261 return I40E_SUCCESS;
2265 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2267 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2268 struct i40e_aqc_remove_macvlan_element_data def_filter;
2271 if (vsi->type != I40E_VSI_MAIN)
2272 return I40E_ERR_CONFIG;
2273 memset(&def_filter, 0, sizeof(def_filter));
2274 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2276 def_filter.vlan_tag = 0;
2277 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2278 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2279 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2280 if (ret != I40E_SUCCESS) {
2281 struct i40e_mac_filter *f;
2282 PMD_DRV_LOG(WARNING, "Failed to remove default [mac,vlan] config\n");
2284 /* Even failed to update default setting, still needs to add the permanent
2285 * mac into mac list.
2287 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2289 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2290 return I40E_ERR_NO_MEMORY;
2292 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2294 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2299 return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2303 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2305 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2306 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2307 struct i40e_hw *hw = &vsi->adapter->hw;
2311 memset(&bw_config, 0, sizeof(bw_config));
2312 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2313 if (ret != I40E_SUCCESS) {
2314 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2315 "configuration %u\n", hw->aq.asq_last_status);
2319 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2320 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2321 &ets_sla_config, NULL);
2322 if (ret != I40E_SUCCESS) {
2323 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2324 "configuration %u\n", hw->aq.asq_last_status);
2328 /* Not store the info yet, just print out */
2329 PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2330 PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2331 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2332 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2333 ets_sla_config.share_credits[i]);
2334 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2335 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2336 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2337 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2346 i40e_vsi_setup(struct i40e_pf *pf,
2347 enum i40e_vsi_type type,
2348 struct i40e_vsi *uplink_vsi,
2349 uint16_t user_param)
2351 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2352 struct i40e_vsi *vsi;
2354 struct i40e_vsi_context ctxt;
2355 struct ether_addr broadcast =
2356 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2358 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2359 PMD_DRV_LOG(ERR, "VSI setup failed, "
2360 "VSI link shouldn't be NULL\n");
2364 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2365 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2366 "uplink VSI should be NULL\n");
2370 /* If uplink vsi didn't setup VEB, create one first */
2371 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2372 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2374 if (NULL == uplink_vsi->veb) {
2375 PMD_DRV_LOG(ERR, "VEB setup failed\n");
2380 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2382 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2385 TAILQ_INIT(&vsi->mac_list);
2387 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2388 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2389 vsi->parent_vsi = uplink_vsi;
2390 vsi->user_param = user_param;
2391 /* Allocate queues */
2392 switch (vsi->type) {
2393 case I40E_VSI_MAIN :
2394 vsi->nb_qps = pf->lan_nb_qps;
2396 case I40E_VSI_SRIOV :
2397 vsi->nb_qps = pf->vf_nb_qps;
2402 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2404 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2408 vsi->base_queue = ret;
2410 /* VF has MSIX interrupt in VF range, don't allocate here */
2411 if (type != I40E_VSI_SRIOV) {
2412 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2414 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2415 goto fail_queue_alloc;
2417 vsi->msix_intr = ret;
2421 if (type == I40E_VSI_MAIN) {
2422 /* For main VSI, no need to add since it's default one */
2423 vsi->uplink_seid = pf->mac_seid;
2424 vsi->seid = pf->main_vsi_seid;
2425 /* Bind queues with specific MSIX interrupt */
2427 * Needs 2 interrupt at least, one for misc cause which will
2428 * enabled from OS side, Another for queues binding the
2429 * interrupt from device side only.
2432 /* Get default VSI parameters from hardware */
2433 memset(&ctxt, 0, sizeof(ctxt));
2434 ctxt.seid = vsi->seid;
2435 ctxt.pf_num = hw->pf_id;
2436 ctxt.uplink_seid = vsi->uplink_seid;
2438 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2439 if (ret != I40E_SUCCESS) {
2440 PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2441 goto fail_msix_alloc;
2443 (void)rte_memcpy(&vsi->info, &ctxt.info,
2444 sizeof(struct i40e_aqc_vsi_properties_data));
2445 vsi->vsi_id = ctxt.vsi_number;
2446 vsi->info.valid_sections = 0;
2448 /* Configure tc, enabled TC0 only */
2449 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2451 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2452 goto fail_msix_alloc;
2455 /* TC, queue mapping */
2456 memset(&ctxt, 0, sizeof(ctxt));
2457 vsi->info.valid_sections |=
2458 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2459 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2460 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2461 (void)rte_memcpy(&ctxt.info, &vsi->info,
2462 sizeof(struct i40e_aqc_vsi_properties_data));
2463 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2464 I40E_DEFAULT_TCMAP);
2465 if (ret != I40E_SUCCESS) {
2466 PMD_DRV_LOG(ERR, "Failed to configure "
2467 "TC queue mapping\n");
2468 goto fail_msix_alloc;
2470 ctxt.seid = vsi->seid;
2471 ctxt.pf_num = hw->pf_id;
2472 ctxt.uplink_seid = vsi->uplink_seid;
2475 /* Update VSI parameters */
2476 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2477 if (ret != I40E_SUCCESS) {
2478 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2479 goto fail_msix_alloc;
2482 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2483 sizeof(vsi->info.tc_mapping));
2484 (void)rte_memcpy(&vsi->info.queue_mapping,
2485 &ctxt.info.queue_mapping,
2486 sizeof(vsi->info.queue_mapping));
2487 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2488 vsi->info.valid_sections = 0;
2490 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2492 ret = i40e_update_default_filter_setting(vsi);
2493 if (ret != I40E_SUCCESS) {
2494 PMD_DRV_LOG(ERR, "Failed to remove default "
2495 "filter setting\n");
2496 goto fail_msix_alloc;
2499 else if (type == I40E_VSI_SRIOV) {
2500 memset(&ctxt, 0, sizeof(ctxt));
2502 * For other VSI, the uplink_seid equals to uplink VSI's
2503 * uplink_seid since they share same VEB
2505 vsi->uplink_seid = uplink_vsi->uplink_seid;
2506 ctxt.pf_num = hw->pf_id;
2507 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2508 ctxt.uplink_seid = vsi->uplink_seid;
2509 ctxt.connection_type = 0x1;
2510 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2512 /* Configure switch ID */
2513 ctxt.info.valid_sections |=
2514 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2515 ctxt.info.switch_id =
2516 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2517 /* Configure port/vlan */
2518 ctxt.info.valid_sections |=
2519 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2520 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2521 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2522 I40E_DEFAULT_TCMAP);
2523 if (ret != I40E_SUCCESS) {
2524 PMD_DRV_LOG(ERR, "Failed to configure "
2525 "TC queue mapping\n");
2526 goto fail_msix_alloc;
2528 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2529 ctxt.info.valid_sections |=
2530 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2532 * Since VSI is not created yet, only configure parameter,
2533 * will add vsi below.
2537 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2538 goto fail_msix_alloc;
2541 if (vsi->type != I40E_VSI_MAIN) {
2542 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2544 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2545 hw->aq.asq_last_status);
2546 goto fail_msix_alloc;
2548 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2549 vsi->info.valid_sections = 0;
2550 vsi->seid = ctxt.seid;
2551 vsi->vsi_id = ctxt.vsi_number;
2552 vsi->sib_vsi_list.vsi = vsi;
2553 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2554 &vsi->sib_vsi_list, list);
2557 /* MAC/VLAN configuration */
2558 ret = i40e_vsi_add_mac(vsi, &broadcast);
2559 if (ret != I40E_SUCCESS) {
2560 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2561 goto fail_msix_alloc;
2564 /* Get VSI BW information */
2565 i40e_vsi_dump_bw_config(vsi);
2568 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2570 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2576 /* Configure vlan stripping on or off */
2578 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2580 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2581 struct i40e_vsi_context ctxt;
2583 int ret = I40E_SUCCESS;
2585 /* Check if it has been already on or off */
2586 if (vsi->info.valid_sections &
2587 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2589 if ((vsi->info.port_vlan_flags &
2590 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2591 return 0; /* already on */
2593 if ((vsi->info.port_vlan_flags &
2594 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2595 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2596 return 0; /* already off */
2601 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2603 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2604 vsi->info.valid_sections =
2605 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2606 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2607 vsi->info.port_vlan_flags |= vlan_flags;
2608 ctxt.seid = vsi->seid;
2609 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2610 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2612 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2613 on ? "enable" : "disable");
2619 i40e_vsi_init_vlan(struct i40e_vsi *vsi)
2621 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2622 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2623 struct i40e_vsi_context ctxt;
2624 uint8_t vlan_flags = 0;
2628 if (data->dev_conf.txmode.hw_vlan_insert_pvid == 1) {
2630 * If insert pvid is enabled, only tagged pkts are
2631 * allowed to be sent out.
2633 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2634 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2636 if (data->dev_conf.txmode.hw_vlan_reject_tagged == 0)
2637 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2638 if (data->dev_conf.txmode.hw_vlan_reject_untagged == 0)
2639 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2642 /* Strip VLAN tag or not */
2643 if (data->dev_conf.rxmode.hw_vlan_strip == 0)
2644 vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2646 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_MODE_MASK |
2647 I40E_AQ_VSI_PVLAN_INSERT_PVID | I40E_AQ_VSI_PVLAN_EMOD_MASK);
2648 vsi->info.port_vlan_flags |= vlan_flags;
2649 vsi->info.pvid = data->dev_conf.txmode.pvid;
2650 vsi->info.valid_sections =
2651 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2653 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2654 ctxt.seid = vsi->seid;
2655 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2656 if (ret != I40E_SUCCESS)
2657 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2663 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2665 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2667 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2671 i40e_update_flow_control(struct i40e_hw *hw)
2673 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2674 struct i40e_link_status link_status;
2675 uint32_t rxfc = 0, txfc = 0, reg;
2679 memset(&link_status, 0, sizeof(link_status));
2680 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2681 if (ret != I40E_SUCCESS) {
2682 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2683 goto write_reg; /* Disable flow control */
2686 an_info = hw->phy.link_info.an_info;
2687 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2688 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2689 ret = I40E_ERR_NOT_READY;
2690 goto write_reg; /* Disable flow control */
2693 * If link auto negotiation is enabled, flow control needs to
2694 * be configured according to it
2696 switch (an_info & I40E_LINK_PAUSE_RXTX) {
2697 case I40E_LINK_PAUSE_RXTX:
2700 hw->fc.current_mode = I40E_FC_FULL;
2702 case I40E_AQ_LINK_PAUSE_RX:
2704 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2706 case I40E_AQ_LINK_PAUSE_TX:
2708 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2711 hw->fc.current_mode = I40E_FC_NONE;
2716 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2717 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2718 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2719 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2720 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2721 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2728 i40e_pf_setup(struct i40e_pf *pf)
2730 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2731 struct i40e_filter_control_settings settings;
2732 struct rte_eth_dev_data *dev_data = pf->dev_data;
2733 struct i40e_vsi *vsi;
2736 /* Clear all stats counters */
2737 pf->offset_loaded = FALSE;
2738 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2739 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2741 ret = i40e_pf_get_switch_config(pf);
2742 if (ret != I40E_SUCCESS) {
2743 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2748 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2750 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2751 return I40E_ERR_NOT_READY;
2754 dev_data->nb_rx_queues = vsi->nb_qps;
2755 dev_data->nb_tx_queues = vsi->nb_qps;
2757 /* Configure filter control */
2758 memset(&settings, 0, sizeof(settings));
2759 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2760 /* Enable ethtype and macvlan filters */
2761 settings.enable_ethtype = TRUE;
2762 settings.enable_macvlan = TRUE;
2763 ret = i40e_set_filter_control(hw, &settings);
2765 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2768 /* Update flow control according to the auto negotiation */
2769 i40e_update_flow_control(hw);
2771 return I40E_SUCCESS;
2775 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2780 /* Wait until the request is finished */
2781 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2782 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2783 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2784 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2785 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2791 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2792 return I40E_SUCCESS; /* already on, skip next steps */
2793 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2795 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2796 return I40E_SUCCESS; /* already off, skip next steps */
2797 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2799 /* Write the register */
2800 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2801 /* Check the result */
2802 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2803 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2804 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2806 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2807 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2810 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2811 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2815 /* Check if it is timeout */
2816 if (j >= I40E_CHK_Q_ENA_COUNT) {
2817 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2818 (on ? "enable" : "disable"), q_idx);
2819 return I40E_ERR_TIMEOUT;
2821 return I40E_SUCCESS;
2823 /* Swith on or off the tx queues */
2825 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
2827 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2828 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2829 struct i40e_tx_queue *txq;
2833 pf_q = vsi->base_queue;
2834 for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
2835 txq = dev_data->tx_queues[i];
2837 continue; /* Queue not configured */
2838 ret = i40e_switch_tx_queue(hw, pf_q, on);
2839 if ( ret != I40E_SUCCESS)
2843 return I40E_SUCCESS;
2847 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2852 /* Wait until the request is finished */
2853 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2854 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2855 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2856 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2857 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
2862 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
2863 return I40E_SUCCESS; /* Already on, skip next steps */
2864 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
2866 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2867 return I40E_SUCCESS; /* Already off, skip next steps */
2868 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
2871 /* Write the register */
2872 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
2873 /* Check the result */
2874 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2875 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2876 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2878 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2879 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
2882 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2883 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2888 /* Check if it is timeout */
2889 if (j >= I40E_CHK_Q_ENA_COUNT) {
2890 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
2891 (on ? "enable" : "disable"), q_idx);
2892 return I40E_ERR_TIMEOUT;
2895 return I40E_SUCCESS;
2897 /* Switch on or off the rx queues */
2899 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
2901 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2902 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2903 struct i40e_rx_queue *rxq;
2907 pf_q = vsi->base_queue;
2908 for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
2909 rxq = dev_data->rx_queues[i];
2911 continue; /* Queue not configured */
2912 ret = i40e_switch_rx_queue(hw, pf_q, on);
2913 if ( ret != I40E_SUCCESS)
2917 return I40E_SUCCESS;
2920 /* Switch on or off all the rx/tx queues */
2922 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
2927 /* enable rx queues before enabling tx queues */
2928 ret = i40e_vsi_switch_rx_queues(vsi, on);
2930 PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
2933 ret = i40e_vsi_switch_tx_queues(vsi, on);
2935 /* Stop tx queues before stopping rx queues */
2936 ret = i40e_vsi_switch_tx_queues(vsi, on);
2938 PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
2941 ret = i40e_vsi_switch_rx_queues(vsi, on);
2947 /* Initialize VSI for TX */
2949 i40e_vsi_tx_init(struct i40e_vsi *vsi)
2951 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2952 struct rte_eth_dev_data *data = pf->dev_data;
2954 uint32_t ret = I40E_SUCCESS;
2956 for (i = 0; i < data->nb_tx_queues; i++) {
2957 ret = i40e_tx_queue_init(data->tx_queues[i]);
2958 if (ret != I40E_SUCCESS)
2965 /* Initialize VSI for RX */
2967 i40e_vsi_rx_init(struct i40e_vsi *vsi)
2969 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2970 struct rte_eth_dev_data *data = pf->dev_data;
2971 int ret = I40E_SUCCESS;
2974 i40e_pf_config_mq_rx(pf);
2975 for (i = 0; i < data->nb_rx_queues; i++) {
2976 ret = i40e_rx_queue_init(data->rx_queues[i]);
2977 if (ret != I40E_SUCCESS) {
2978 PMD_DRV_LOG(ERR, "Failed to do RX queue "
2979 "initialization\n");
2987 /* Initialize VSI */
2989 i40e_vsi_init(struct i40e_vsi *vsi)
2993 err = i40e_vsi_tx_init(vsi);
2995 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
2998 err = i40e_vsi_rx_init(vsi);
3000 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3008 i40e_stat_update_32(struct i40e_hw *hw,
3016 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3020 if (new_data >= *offset)
3021 *stat = (uint64_t)(new_data - *offset);
3023 *stat = (uint64_t)((new_data +
3024 ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3028 i40e_stat_update_48(struct i40e_hw *hw,
3037 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3038 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3039 I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3044 if (new_data >= *offset)
3045 *stat = new_data - *offset;
3047 *stat = (uint64_t)((new_data +
3048 ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3050 *stat &= I40E_48_BIT_MASK;
3055 i40e_pf_disable_irq0(struct i40e_hw *hw)
3057 /* Disable all interrupt types */
3058 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3059 I40E_WRITE_FLUSH(hw);
3064 i40e_pf_enable_irq0(struct i40e_hw *hw)
3066 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3067 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3068 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3069 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3070 I40E_WRITE_FLUSH(hw);
3074 i40e_pf_config_irq0(struct i40e_hw *hw)
3078 /* read pending request and disable first */
3079 i40e_pf_disable_irq0(hw);
3081 * Enable all interrupt error options to detect possible errors,
3082 * other informative int are ignored
3084 enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3085 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3086 I40E_PFINT_ICR0_ENA_GRST_MASK |
3087 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3088 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3089 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3090 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3091 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3093 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3094 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3095 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3097 /* Link no queues with irq0 */
3098 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3099 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3103 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3109 uint32_t index, offset, val;
3114 * Try to find which VF trigger a reset, use absolute VF id to access
3115 * since the reg is global register.
3117 for (i = 0; i < pf->vf_num; i++) {
3118 abs_vf_id = hw->func_caps.vf_base_id + i;
3119 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3120 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3121 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3122 /* VFR event occured */
3123 if (val & (0x1 << offset)) {
3126 /* Clear the event first */
3127 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3129 PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3131 * Only notify a VF reset event occured,
3132 * don't trigger another SW reset
3134 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3135 if (ret != I40E_SUCCESS)
3136 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3142 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3144 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3145 struct i40e_arq_event_info info;
3146 uint16_t pending, opcode;
3149 info.msg_size = I40E_AQ_BUF_SZ;
3150 info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3151 if (!info.msg_buf) {
3152 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3158 ret = i40e_clean_arq_element(hw, &info, &pending);
3160 if (ret != I40E_SUCCESS) {
3161 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3162 "aq_err: %u\n", hw->aq.asq_last_status);
3165 opcode = rte_le_to_cpu_16(info.desc.opcode);
3168 case i40e_aqc_opc_send_msg_to_pf:
3169 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3170 i40e_pf_host_handle_vf_msg(dev,
3171 rte_le_to_cpu_16(info.desc.retval),
3172 rte_le_to_cpu_32(info.desc.cookie_high),
3173 rte_le_to_cpu_32(info.desc.cookie_low),
3178 PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3182 /* Reset the buffer after processing one */
3183 info.msg_size = I40E_AQ_BUF_SZ;
3185 rte_free(info.msg_buf);
3189 * Interrupt handler triggered by NIC for handling
3190 * specific interrupt.
3193 * Pointer to interrupt handle.
3195 * The address of parameter (struct rte_eth_dev *) regsitered before.
3201 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3204 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3205 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206 uint32_t cause, enable;
3208 i40e_pf_disable_irq0(hw);
3210 cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3211 enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3213 /* Shared IRQ case, return */
3214 if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3215 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3216 "no INT event to process\n", hw->pf_id);
3220 if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3221 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3222 i40e_dev_link_update(dev, 0);
3225 if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3226 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3228 if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3229 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3231 if (cause & I40E_PFINT_ICR0_GRST_MASK)
3232 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3234 if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3235 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3237 if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3238 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3240 /* Add processing func to deal with VF reset vent */
3241 if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3242 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3243 i40e_dev_handle_vfr_event(dev);
3245 /* Find admin queue event */
3246 if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3247 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3248 i40e_dev_handle_aq_msg(dev);
3252 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3253 /* Re-enable interrupt from device side */
3254 i40e_pf_enable_irq0(hw);
3255 /* Re-enable interrupt from host side */
3256 rte_intr_enable(&(dev->pci_dev->intr_handle));
3260 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3261 struct i40e_macvlan_filter *filter,
3264 int ele_num, ele_buff_size;
3265 int num, actual_num, i;
3266 int ret = I40E_SUCCESS;
3267 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3268 struct i40e_aqc_add_macvlan_element_data *req_list;
3270 if (filter == NULL || total == 0)
3271 return I40E_ERR_PARAM;
3272 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3273 ele_buff_size = hw->aq.asq_buf_size;
3275 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3276 if (req_list == NULL) {
3277 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3278 return I40E_ERR_NO_MEMORY;
3283 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3284 memset(req_list, 0, ele_buff_size);
3286 for (i = 0; i < actual_num; i++) {
3287 (void)rte_memcpy(req_list[i].mac_addr,
3288 &filter[num + i].macaddr, ETH_ADDR_LEN);
3289 req_list[i].vlan_tag =
3290 rte_cpu_to_le_16(filter[num + i].vlan_id);
3291 req_list[i].flags = rte_cpu_to_le_16(\
3292 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3293 req_list[i].queue_number = 0;
3296 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3298 if (ret != I40E_SUCCESS) {
3299 PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3303 } while (num < total);
3311 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3312 struct i40e_macvlan_filter *filter,
3315 int ele_num, ele_buff_size;
3316 int num, actual_num, i;
3317 int ret = I40E_SUCCESS;
3318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3319 struct i40e_aqc_remove_macvlan_element_data *req_list;
3321 if (filter == NULL || total == 0)
3322 return I40E_ERR_PARAM;
3324 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3325 ele_buff_size = hw->aq.asq_buf_size;
3327 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3328 if (req_list == NULL) {
3329 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3330 return I40E_ERR_NO_MEMORY;
3335 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3336 memset(req_list, 0, ele_buff_size);
3338 for (i = 0; i < actual_num; i++) {
3339 (void)rte_memcpy(req_list[i].mac_addr,
3340 &filter[num + i].macaddr, ETH_ADDR_LEN);
3341 req_list[i].vlan_tag =
3342 rte_cpu_to_le_16(filter[num + i].vlan_id);
3343 req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3346 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3348 if (ret != I40E_SUCCESS) {
3349 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3353 } while (num < total);
3360 /* Find out specific MAC filter */
3361 static struct i40e_mac_filter *
3362 i40e_find_mac_filter(struct i40e_vsi *vsi,
3363 struct ether_addr *macaddr)
3365 struct i40e_mac_filter *f;
3367 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3368 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3376 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3379 uint32_t vid_idx, vid_bit;
3381 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3382 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3384 if (vsi->vfta[vid_idx] & vid_bit)
3391 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3392 uint16_t vlan_id, bool on)
3394 uint32_t vid_idx, vid_bit;
3396 #define UINT32_BIT_MASK 0x1F
3397 #define VALID_VLAN_BIT_MASK 0xFFF
3398 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3399 * element first, then find the bits it belongs to
3401 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3403 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3406 vsi->vfta[vid_idx] |= vid_bit;
3408 vsi->vfta[vid_idx] &= ~vid_bit;
3412 * Find all vlan options for specific mac addr,
3413 * return with actual vlan found.
3416 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3417 struct i40e_macvlan_filter *mv_f,
3418 int num, struct ether_addr *addr)
3424 * Not to use i40e_find_vlan_filter to decrease the loop time,
3425 * although the code looks complex.
3427 if (num < vsi->vlan_num)
3428 return I40E_ERR_PARAM;
3431 for (j = 0; j < I40E_VFTA_SIZE; j++) {
3433 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3434 if (vsi->vfta[j] & (1 << k)) {
3436 PMD_DRV_LOG(ERR, "vlan number "
3438 return I40E_ERR_PARAM;
3440 (void)rte_memcpy(&mv_f[i].macaddr,
3441 addr, ETH_ADDR_LEN);
3443 j * I40E_UINT32_BIT_SIZE + k;
3449 return I40E_SUCCESS;
3453 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3454 struct i40e_macvlan_filter *mv_f,
3459 struct i40e_mac_filter *f;
3461 if (num < vsi->mac_num)
3462 return I40E_ERR_PARAM;
3464 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3466 PMD_DRV_LOG(ERR, "buffer number not match\n");
3467 return I40E_ERR_PARAM;
3469 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3470 mv_f[i].vlan_id = vlan;
3474 return I40E_SUCCESS;
3478 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3481 struct i40e_mac_filter *f;
3482 struct i40e_macvlan_filter *mv_f;
3483 int ret = I40E_SUCCESS;
3485 if (vsi == NULL || vsi->mac_num == 0)
3486 return I40E_ERR_PARAM;
3488 /* Case that no vlan is set */
3489 if (vsi->vlan_num == 0)
3492 num = vsi->mac_num * vsi->vlan_num;
3494 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3496 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3497 return I40E_ERR_NO_MEMORY;
3501 if (vsi->vlan_num == 0) {
3502 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3503 (void)rte_memcpy(&mv_f[i].macaddr,
3504 &f->macaddr, ETH_ADDR_LEN);
3505 mv_f[i].vlan_id = 0;
3509 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3510 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3511 vsi->vlan_num, &f->macaddr);
3512 if (ret != I40E_SUCCESS)
3518 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3526 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3528 struct i40e_macvlan_filter *mv_f;
3530 int ret = I40E_SUCCESS;
3532 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3533 return I40E_ERR_PARAM;
3535 /* If it's already set, just return */
3536 if (i40e_find_vlan_filter(vsi,vlan))
3537 return I40E_SUCCESS;
3539 mac_num = vsi->mac_num;
3542 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3543 return I40E_ERR_PARAM;
3546 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3549 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3550 return I40E_ERR_NO_MEMORY;
3553 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3555 if (ret != I40E_SUCCESS)
3558 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3560 if (ret != I40E_SUCCESS)
3563 i40e_set_vlan_filter(vsi, vlan, 1);
3573 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3575 struct i40e_macvlan_filter *mv_f;
3577 int ret = I40E_SUCCESS;
3580 * Vlan 0 is the generic filter for untagged packets
3581 * and can't be removed.
3583 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3584 return I40E_ERR_PARAM;
3586 /* If can't find it, just return */
3587 if (!i40e_find_vlan_filter(vsi, vlan))
3588 return I40E_ERR_PARAM;
3590 mac_num = vsi->mac_num;
3593 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3594 return I40E_ERR_PARAM;
3597 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3600 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3601 return I40E_ERR_NO_MEMORY;
3604 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3606 if (ret != I40E_SUCCESS)
3609 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3611 if (ret != I40E_SUCCESS)
3614 /* This is last vlan to remove, replace all mac filter with vlan 0 */
3615 if (vsi->vlan_num == 1) {
3616 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3617 if (ret != I40E_SUCCESS)
3620 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3621 if (ret != I40E_SUCCESS)
3625 i40e_set_vlan_filter(vsi, vlan, 0);
3635 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3637 struct i40e_mac_filter *f;
3638 struct i40e_macvlan_filter *mv_f;
3640 int ret = I40E_SUCCESS;
3642 /* If it's add and we've config it, return */
3643 f = i40e_find_mac_filter(vsi, addr);
3645 return I40E_SUCCESS;
3648 * If vlan_num is 0, that's the first time to add mac,
3649 * set mask for vlan_id 0.
3651 if (vsi->vlan_num == 0) {
3652 i40e_set_vlan_filter(vsi, 0, 1);
3656 vlan_num = vsi->vlan_num;
3658 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3660 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3661 return I40E_ERR_NO_MEMORY;
3664 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3665 if (ret != I40E_SUCCESS)
3668 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3669 if (ret != I40E_SUCCESS)
3672 /* Add the mac addr into mac list */
3673 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3675 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3676 ret = I40E_ERR_NO_MEMORY;
3679 (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3680 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3691 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3693 struct i40e_mac_filter *f;
3694 struct i40e_macvlan_filter *mv_f;
3696 int ret = I40E_SUCCESS;
3698 /* Can't find it, return an error */
3699 f = i40e_find_mac_filter(vsi, addr);
3701 return I40E_ERR_PARAM;
3703 vlan_num = vsi->vlan_num;
3704 if (vlan_num == 0) {
3705 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3706 return I40E_ERR_PARAM;
3708 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3710 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3711 return I40E_ERR_NO_MEMORY;
3714 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3715 if (ret != I40E_SUCCESS)
3718 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3719 if (ret != I40E_SUCCESS)
3722 /* Remove the mac addr into mac list */
3723 TAILQ_REMOVE(&vsi->mac_list, f, next);
3733 /* Configure hash enable flags for RSS */
3735 i40e_config_hena(uint64_t flags)
3742 if (flags & ETH_RSS_NONF_IPV4_UDP)
3743 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3744 if (flags & ETH_RSS_NONF_IPV4_TCP)
3745 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3746 if (flags & ETH_RSS_NONF_IPV4_SCTP)
3747 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3748 if (flags & ETH_RSS_NONF_IPV4_OTHER)
3749 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3750 if (flags & ETH_RSS_FRAG_IPV4)
3751 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3752 if (flags & ETH_RSS_NONF_IPV6_UDP)
3753 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3754 if (flags & ETH_RSS_NONF_IPV6_TCP)
3755 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3756 if (flags & ETH_RSS_NONF_IPV6_SCTP)
3757 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3758 if (flags & ETH_RSS_NONF_IPV6_OTHER)
3759 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3760 if (flags & ETH_RSS_FRAG_IPV6)
3761 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3762 if (flags & ETH_RSS_L2_PAYLOAD)
3763 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3768 /* Parse the hash enable flags */
3770 i40e_parse_hena(uint64_t flags)
3772 uint64_t rss_hf = 0;
3777 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3778 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3779 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3780 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3781 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3782 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3783 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3784 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3785 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3786 rss_hf |= ETH_RSS_FRAG_IPV4;
3787 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3788 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3789 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3790 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3791 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3792 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3793 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3794 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3795 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3796 rss_hf |= ETH_RSS_FRAG_IPV6;
3797 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3798 rss_hf |= ETH_RSS_L2_PAYLOAD;
3805 i40e_pf_disable_rss(struct i40e_pf *pf)
3807 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3810 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3811 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3812 hena &= ~I40E_RSS_HENA_ALL;
3813 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3814 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3815 I40E_WRITE_FLUSH(hw);
3819 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
3822 uint8_t hash_key_len;
3827 hash_key = (uint32_t *)(rss_conf->rss_key);
3828 hash_key_len = rss_conf->rss_key_len;
3829 if (hash_key != NULL && hash_key_len >=
3830 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3831 /* Fill in RSS hash key */
3832 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3833 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
3836 rss_hf = rss_conf->rss_hf;
3837 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3838 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3839 hena &= ~I40E_RSS_HENA_ALL;
3840 hena |= i40e_config_hena(rss_hf);
3841 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3842 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3843 I40E_WRITE_FLUSH(hw);
3849 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
3850 struct rte_eth_rss_conf *rss_conf)
3852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
3856 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3857 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3858 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
3859 if (rss_hf != 0) /* Enable RSS */
3861 return 0; /* Nothing to do */
3864 if (rss_hf == 0) /* Disable RSS */
3867 return i40e_hw_rss_hash_set(hw, rss_conf);
3871 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3872 struct rte_eth_rss_conf *rss_conf)
3874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
3879 if (hash_key != NULL) {
3880 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3881 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
3882 rss_conf->rss_key_len = i * sizeof(uint32_t);
3884 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3885 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3886 rss_conf->rss_hf = i40e_parse_hena(hena);
3893 i40e_pf_config_rss(struct i40e_pf *pf)
3895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3896 struct rte_eth_rss_conf rss_conf;
3897 uint32_t i, lut = 0;
3898 uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
3900 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
3903 lut = (lut << 8) | (j & ((0x1 <<
3904 hw->func_caps.rss_table_entry_width) - 1));
3906 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
3909 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
3910 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
3911 i40e_pf_disable_rss(pf);
3914 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
3915 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3916 /* Calculate the default hash key */
3917 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3918 rss_key_default[i] = (uint32_t)rte_rand();
3919 rss_conf.rss_key = (uint8_t *)rss_key_default;
3920 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3924 return i40e_hw_rss_hash_set(hw, &rss_conf);
3928 i40e_pf_config_mq_rx(struct i40e_pf *pf)
3930 if (!pf->dev_data->sriov.active) {
3931 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
3933 i40e_pf_config_rss(pf);
3936 i40e_pf_disable_rss(pf);
3945 i40e_disable_queue(struct i40e_hw *hw, uint16_t q_idx)
3950 /* Disable TX queue */
3951 for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3952 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3953 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3954 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 0x1)))
3956 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3958 if (i >= I40E_CHK_Q_ENA_COUNT) {
3959 PMD_DRV_LOG(ERR, "Failed to disable "
3960 "tx queue[%u]\n", q_idx);
3961 return I40E_ERR_TIMEOUT;
3964 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) {
3965 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3966 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3967 for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3968 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3969 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3970 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3971 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3974 if (i >= I40E_CHK_Q_ENA_COUNT) {
3975 PMD_DRV_LOG(ERR, "Failed to disable "
3976 "tx queue[%u]\n", q_idx);
3977 return I40E_ERR_TIMEOUT;
3981 /* Disable RX queue */
3982 for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3983 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3984 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3985 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3987 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3989 if (i >= I40E_CHK_Q_ENA_COUNT) {
3990 PMD_DRV_LOG(ERR, "Failed to disable "
3991 "rx queue[%u]\n", q_idx);
3992 return I40E_ERR_TIMEOUT;
3995 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) {
3996 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3997 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3998 for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3999 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4000 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4001 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4002 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4005 if (i >= I40E_CHK_Q_ENA_COUNT) {
4006 PMD_DRV_LOG(ERR, "Failed to disable "
4007 "rx queue[%u]\n", q_idx);
4008 return I40E_ERR_TIMEOUT;
4012 return I40E_SUCCESS;
4016 i40e_pf_disable_all_queues(struct i40e_hw *hw)
4019 uint16_t firstq, lastq, maxq, i;
4021 reg = I40E_READ_REG(hw, I40E_PFLAN_QALLOC);
4022 if (!(reg & I40E_PFLAN_QALLOC_VALID_MASK)) {
4023 PMD_DRV_LOG(INFO, "PF queue allocation is invalid\n");
4024 return I40E_ERR_PARAM;
4026 firstq = reg & I40E_PFLAN_QALLOC_FIRSTQ_MASK;
4027 lastq = (reg & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
4028 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
4029 maxq = lastq - firstq;
4030 for (i = 0; i <= maxq; i++) {
4031 ret = i40e_disable_queue(hw, i);
4032 if (ret != I40E_SUCCESS)
4035 return I40E_SUCCESS;