4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
51 #include <rte_eth_ctrl.h>
53 #include "i40e_logs.h"
54 #include "i40e/i40e_register_x710_int.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 #define I40E_DEFAULT_RX_FREE_THRESH 32
63 #define I40E_DEFAULT_RX_PTHRESH 8
64 #define I40E_DEFAULT_RX_HTHRESH 8
65 #define I40E_DEFAULT_RX_WTHRESH 0
67 #define I40E_DEFAULT_TX_FREE_THRESH 32
68 #define I40E_DEFAULT_TX_PTHRESH 32
69 #define I40E_DEFAULT_TX_HTHRESH 0
70 #define I40E_DEFAULT_TX_WTHRESH 0
71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
73 /* Maximun number of MAC addresses */
74 #define I40E_NUM_MACADDR_MAX 64
75 #define I40E_CLEAR_PXE_WAIT_MS 200
77 /* Maximun number of capability elements */
78 #define I40E_MAX_CAP_ELE_NUM 128
80 /* Wait count and inteval */
81 #define I40E_CHK_Q_ENA_COUNT 1000
82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
84 /* Maximun number of VSI */
85 #define I40E_MAX_NUM_VSIS (384UL)
87 /* Bit shift and mask */
88 #define I40E_16_BIT_SHIFT 16
89 #define I40E_16_BIT_MASK 0xFFFF
90 #define I40E_32_BIT_SHIFT 32
91 #define I40E_32_BIT_MASK 0xFFFFFFFF
92 #define I40E_48_BIT_SHIFT 48
93 #define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL
95 /* Default queue interrupt throttling time in microseconds*/
96 #define I40E_ITR_INDEX_DEFAULT 0
97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
98 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
100 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
102 static int eth_i40e_dev_init(\
103 __attribute__((unused)) struct eth_driver *eth_drv,
104 struct rte_eth_dev *eth_dev);
105 static int i40e_dev_configure(struct rte_eth_dev *dev);
106 static int i40e_dev_start(struct rte_eth_dev *dev);
107 static void i40e_dev_stop(struct rte_eth_dev *dev);
108 static void i40e_dev_close(struct rte_eth_dev *dev);
109 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
110 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
111 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
112 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
113 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
114 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
115 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
116 struct rte_eth_stats *stats);
117 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
118 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
122 static void i40e_dev_info_get(struct rte_eth_dev *dev,
123 struct rte_eth_dev_info *dev_info);
124 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
127 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
128 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
129 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
132 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
133 static int i40e_dev_led_on(struct rte_eth_dev *dev);
134 static int i40e_dev_led_off(struct rte_eth_dev *dev);
135 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
136 struct rte_eth_fc_conf *fc_conf);
137 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
138 struct rte_eth_pfc_conf *pfc_conf);
139 static void i40e_macaddr_add(struct rte_eth_dev *dev,
140 struct ether_addr *mac_addr,
143 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
144 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
145 struct rte_eth_rss_reta *reta_conf);
146 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta *reta_conf);
149 static int i40e_get_cap(struct i40e_hw *hw);
150 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
151 static int i40e_pf_setup(struct i40e_pf *pf);
152 static int i40e_vsi_init(struct i40e_vsi *vsi);
153 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
154 bool offset_loaded, uint64_t *offset, uint64_t *stat);
155 static void i40e_stat_update_48(struct i40e_hw *hw,
161 static void i40e_pf_config_irq0(struct i40e_hw *hw);
162 static void i40e_dev_interrupt_handler(
163 __rte_unused struct rte_intr_handle *handle, void *param);
164 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
165 uint32_t base, uint32_t num);
166 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
167 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
169 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
171 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
172 static int i40e_veb_release(struct i40e_veb *veb);
173 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
174 struct i40e_vsi *vsi);
175 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
176 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
177 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
178 struct i40e_macvlan_filter *mv_f,
180 struct ether_addr *addr);
181 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
182 struct i40e_macvlan_filter *mv_f,
185 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
186 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
187 struct rte_eth_rss_conf *rss_conf);
188 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
189 struct rte_eth_rss_conf *rss_conf);
190 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
191 struct rte_eth_udp_tunnel *udp_tunnel);
192 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
193 struct rte_eth_udp_tunnel *udp_tunnel);
194 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
195 enum rte_filter_type filter_type,
196 enum rte_filter_op filter_op,
199 /* Default hash key buffer for RSS */
200 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
202 static struct rte_pci_id pci_id_i40e_map[] = {
203 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
204 #include "rte_pci_dev_ids.h"
205 { .vendor_id = 0, /* sentinel */ },
208 static struct eth_dev_ops i40e_eth_dev_ops = {
209 .dev_configure = i40e_dev_configure,
210 .dev_start = i40e_dev_start,
211 .dev_stop = i40e_dev_stop,
212 .dev_close = i40e_dev_close,
213 .promiscuous_enable = i40e_dev_promiscuous_enable,
214 .promiscuous_disable = i40e_dev_promiscuous_disable,
215 .allmulticast_enable = i40e_dev_allmulticast_enable,
216 .allmulticast_disable = i40e_dev_allmulticast_disable,
217 .dev_set_link_up = i40e_dev_set_link_up,
218 .dev_set_link_down = i40e_dev_set_link_down,
219 .link_update = i40e_dev_link_update,
220 .stats_get = i40e_dev_stats_get,
221 .stats_reset = i40e_dev_stats_reset,
222 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
223 .dev_infos_get = i40e_dev_info_get,
224 .vlan_filter_set = i40e_vlan_filter_set,
225 .vlan_tpid_set = i40e_vlan_tpid_set,
226 .vlan_offload_set = i40e_vlan_offload_set,
227 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
228 .vlan_pvid_set = i40e_vlan_pvid_set,
229 .rx_queue_start = i40e_dev_rx_queue_start,
230 .rx_queue_stop = i40e_dev_rx_queue_stop,
231 .tx_queue_start = i40e_dev_tx_queue_start,
232 .tx_queue_stop = i40e_dev_tx_queue_stop,
233 .rx_queue_setup = i40e_dev_rx_queue_setup,
234 .rx_queue_release = i40e_dev_rx_queue_release,
235 .rx_queue_count = i40e_dev_rx_queue_count,
236 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
237 .tx_queue_setup = i40e_dev_tx_queue_setup,
238 .tx_queue_release = i40e_dev_tx_queue_release,
239 .dev_led_on = i40e_dev_led_on,
240 .dev_led_off = i40e_dev_led_off,
241 .flow_ctrl_set = i40e_flow_ctrl_set,
242 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
243 .mac_addr_add = i40e_macaddr_add,
244 .mac_addr_remove = i40e_macaddr_remove,
245 .reta_update = i40e_dev_rss_reta_update,
246 .reta_query = i40e_dev_rss_reta_query,
247 .rss_hash_update = i40e_dev_rss_hash_update,
248 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
249 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
250 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
251 .filter_ctrl = i40e_dev_filter_ctrl,
254 static struct eth_driver rte_i40e_pmd = {
256 .name = "rte_i40e_pmd",
257 .id_table = pci_id_i40e_map,
258 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
260 .eth_dev_init = eth_i40e_dev_init,
261 .dev_private_size = sizeof(struct i40e_adapter),
265 i40e_prev_power_of_2(int n)
283 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
284 struct rte_eth_link *link)
286 struct rte_eth_link *dst = link;
287 struct rte_eth_link *src = &(dev->data->dev_link);
289 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
290 *(uint64_t *)src) == 0)
297 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
298 struct rte_eth_link *link)
300 struct rte_eth_link *dst = &(dev->data->dev_link);
301 struct rte_eth_link *src = link;
303 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
304 *(uint64_t *)src) == 0)
311 * Driver initialization routine.
312 * Invoked once at EAL init time.
313 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
316 rte_i40e_pmd_init(const char *name __rte_unused,
317 const char *params __rte_unused)
319 PMD_INIT_FUNC_TRACE();
320 rte_eth_driver_register(&rte_i40e_pmd);
325 static struct rte_driver rte_i40e_driver = {
327 .init = rte_i40e_pmd_init,
330 PMD_REGISTER_DRIVER(rte_i40e_driver);
333 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
334 struct rte_eth_dev *dev)
336 struct rte_pci_device *pci_dev;
337 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
338 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
339 struct i40e_vsi *vsi;
344 PMD_INIT_FUNC_TRACE();
346 dev->dev_ops = &i40e_eth_dev_ops;
347 dev->rx_pkt_burst = i40e_recv_pkts;
348 dev->tx_pkt_burst = i40e_xmit_pkts;
350 /* for secondary processes, we don't initialise any further as primary
351 * has already done this work. Only check we don't need a different
353 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
354 if (dev->data->scattered_rx)
355 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
358 pci_dev = dev->pci_dev;
359 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
360 pf->adapter->eth_dev = dev;
361 pf->dev_data = dev->data;
363 hw->back = I40E_PF_TO_ADAPTER(pf);
364 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
366 PMD_INIT_LOG(ERR, "Hardware is not available, "
367 "as address is NULL");
371 hw->vendor_id = pci_dev->id.vendor_id;
372 hw->device_id = pci_dev->id.device_id;
373 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
374 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
375 hw->bus.device = pci_dev->addr.devid;
376 hw->bus.func = pci_dev->addr.function;
378 /* Make sure all is clean before doing PF reset */
381 /* Reset here to make sure all is clean for each PF */
382 ret = i40e_pf_reset(hw);
384 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
388 /* Initialize the shared code (base driver) */
389 ret = i40e_init_shared_code(hw);
391 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
395 /* Initialize the parameters for adminq */
396 i40e_init_adminq_parameter(hw);
397 ret = i40e_init_adminq(hw);
398 if (ret != I40E_SUCCESS) {
399 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
402 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
403 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
404 hw->aq.api_maj_ver, hw->aq.api_min_ver,
405 ((hw->nvm.version >> 12) & 0xf),
406 ((hw->nvm.version >> 4) & 0xff),
407 (hw->nvm.version & 0xf), hw->nvm.eetrack);
410 ret = i40e_aq_stop_lldp(hw, true, NULL);
411 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
412 PMD_INIT_LOG(INFO, "Failed to stop lldp");
415 i40e_clear_pxe_mode(hw);
417 /* Get hw capabilities */
418 ret = i40e_get_cap(hw);
419 if (ret != I40E_SUCCESS) {
420 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
421 goto err_get_capabilities;
424 /* Initialize parameters for PF */
425 ret = i40e_pf_parameter_init(dev);
427 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
428 goto err_parameter_init;
431 /* Initialize the queue management */
432 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
434 PMD_INIT_LOG(ERR, "Failed to init queue pool");
435 goto err_qp_pool_init;
437 ret = i40e_res_pool_init(&pf->msix_pool, 1,
438 hw->func_caps.num_msix_vectors - 1);
440 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
441 goto err_msix_pool_init;
444 /* Initialize lan hmc */
445 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
446 hw->func_caps.num_rx_qp, 0, 0);
447 if (ret != I40E_SUCCESS) {
448 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
449 goto err_init_lan_hmc;
452 /* Configure lan hmc */
453 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
454 if (ret != I40E_SUCCESS) {
455 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
456 goto err_configure_lan_hmc;
459 /* Get and check the mac address */
460 i40e_get_mac_addr(hw, hw->mac.addr);
461 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
462 PMD_INIT_LOG(ERR, "mac address is not valid");
464 goto err_get_mac_addr;
466 /* Copy the permanent MAC address */
467 ether_addr_copy((struct ether_addr *) hw->mac.addr,
468 (struct ether_addr *) hw->mac.perm_addr);
470 /* Disable flow control */
471 hw->fc.requested_mode = I40E_FC_NONE;
472 i40e_set_fc(hw, &aq_fail, TRUE);
474 /* PF setup, which includes VSI setup */
475 ret = i40e_pf_setup(pf);
477 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
478 goto err_setup_pf_switch;
483 /* Disable double vlan by default */
484 i40e_vsi_config_double_vlan(vsi, FALSE);
486 if (!vsi->max_macaddrs)
487 len = ETHER_ADDR_LEN;
489 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
491 /* Should be after VSI initialized */
492 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
493 if (!dev->data->mac_addrs) {
494 PMD_INIT_LOG(ERR, "Failed to allocated memory "
495 "for storing mac address");
496 goto err_get_mac_addr;
498 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
499 &dev->data->mac_addrs[0]);
501 /* initialize pf host driver to setup SRIOV resource if applicable */
502 i40e_pf_host_init(dev);
504 /* register callback func to eal lib */
505 rte_intr_callback_register(&(pci_dev->intr_handle),
506 i40e_dev_interrupt_handler, (void *)dev);
508 /* configure and enable device interrupt */
509 i40e_pf_config_irq0(hw);
510 i40e_pf_enable_irq0(hw);
512 /* enable uio intr after callback register */
513 rte_intr_enable(&(pci_dev->intr_handle));
518 rte_free(pf->main_vsi);
520 err_configure_lan_hmc:
521 (void)i40e_shutdown_lan_hmc(hw);
523 i40e_res_pool_destroy(&pf->msix_pool);
525 i40e_res_pool_destroy(&pf->qp_pool);
528 err_get_capabilities:
529 (void)i40e_shutdown_adminq(hw);
535 i40e_dev_configure(struct rte_eth_dev *dev)
537 return i40e_dev_init_vlan(dev);
541 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
543 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
544 uint16_t msix_vect = vsi->msix_intr;
547 for (i = 0; i < vsi->nb_qps; i++) {
548 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
549 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
553 if (vsi->type != I40E_VSI_SRIOV) {
554 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
555 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
559 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
560 vsi->user_param + (msix_vect - 1);
562 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
564 I40E_WRITE_FLUSH(hw);
567 static inline uint16_t
568 i40e_calc_itr_interval(int16_t interval)
570 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
571 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
573 /* Convert to hardware count, as writing each 1 represents 2 us */
578 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
581 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
582 uint16_t msix_vect = vsi->msix_intr;
583 uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
586 for (i = 0; i < vsi->nb_qps; i++)
587 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
589 /* Bind all RX queues to allocated MSIX interrupt */
590 for (i = 0; i < vsi->nb_qps; i++) {
591 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
592 (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
593 ((vsi->base_queue + i + 1) <<
594 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
595 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
596 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
598 if (i == vsi->nb_qps - 1)
599 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
600 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
603 /* Write first RX queue to Link list register as the head element */
604 if (vsi->type != I40E_VSI_SRIOV) {
605 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
606 (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
607 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
609 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
610 msix_vect - 1), interval);
612 /* Disable auto-mask on enabling of all none-zero interrupt */
613 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
614 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
618 /* num_msix_vectors_vf needs to minus irq0 */
619 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
620 vsi->user_param + (msix_vect - 1);
622 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
623 (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
624 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
627 I40E_WRITE_FLUSH(hw);
631 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
633 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
634 uint16_t interval = i40e_calc_itr_interval(\
635 RTE_LIBRTE_I40E_ITR_INTERVAL);
637 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
638 I40E_PFINT_DYN_CTLN_INTENA_MASK |
639 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
640 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
641 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
645 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
647 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
649 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
652 static inline uint8_t
653 i40e_parse_link_speed(uint16_t eth_link_speed)
655 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
657 switch (eth_link_speed) {
658 case ETH_LINK_SPEED_40G:
659 link_speed = I40E_LINK_SPEED_40GB;
661 case ETH_LINK_SPEED_20G:
662 link_speed = I40E_LINK_SPEED_20GB;
664 case ETH_LINK_SPEED_10G:
665 link_speed = I40E_LINK_SPEED_10GB;
667 case ETH_LINK_SPEED_1000:
668 link_speed = I40E_LINK_SPEED_1GB;
670 case ETH_LINK_SPEED_100:
671 link_speed = I40E_LINK_SPEED_100MB;
679 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
681 enum i40e_status_code status;
682 struct i40e_aq_get_phy_abilities_resp phy_ab;
683 struct i40e_aq_set_phy_config phy_conf;
684 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
685 I40E_AQ_PHY_FLAG_PAUSE_RX |
686 I40E_AQ_PHY_FLAG_LOW_POWER;
687 const uint8_t advt = I40E_LINK_SPEED_40GB |
688 I40E_LINK_SPEED_10GB |
689 I40E_LINK_SPEED_1GB |
690 I40E_LINK_SPEED_100MB;
693 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
698 memset(&phy_conf, 0, sizeof(phy_conf));
700 /* bits 0-2 use the values from get_phy_abilities_resp */
702 abilities |= phy_ab.abilities & mask;
704 /* update ablities and speed */
705 if (abilities & I40E_AQ_PHY_AN_ENABLED)
706 phy_conf.link_speed = advt;
708 phy_conf.link_speed = force_speed;
710 phy_conf.abilities = abilities;
712 /* use get_phy_abilities_resp value for the rest */
713 phy_conf.phy_type = phy_ab.phy_type;
714 phy_conf.eee_capability = phy_ab.eee_capability;
715 phy_conf.eeer = phy_ab.eeer_val;
716 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
718 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
719 phy_ab.abilities, phy_ab.link_speed);
720 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
721 phy_conf.abilities, phy_conf.link_speed);
723 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
731 i40e_apply_link_speed(struct rte_eth_dev *dev)
734 uint8_t abilities = 0;
735 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
736 struct rte_eth_conf *conf = &dev->data->dev_conf;
738 speed = i40e_parse_link_speed(conf->link_speed);
739 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
740 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
741 abilities |= I40E_AQ_PHY_AN_ENABLED;
743 abilities |= I40E_AQ_PHY_LINK_ENABLED;
745 return i40e_phy_conf_link(hw, abilities, speed);
749 i40e_dev_start(struct rte_eth_dev *dev)
751 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
753 struct i40e_vsi *vsi = pf->main_vsi;
756 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
757 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
758 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
759 dev->data->dev_conf.link_duplex,
765 ret = i40e_vsi_init(vsi);
766 if (ret != I40E_SUCCESS) {
767 PMD_DRV_LOG(ERR, "Failed to init VSI");
771 /* Map queues with MSIX interrupt */
772 i40e_vsi_queues_bind_intr(vsi);
773 i40e_vsi_enable_queues_intr(vsi);
775 /* Enable all queues which have been configured */
776 ret = i40e_vsi_switch_queues(vsi, TRUE);
777 if (ret != I40E_SUCCESS) {
778 PMD_DRV_LOG(ERR, "Failed to enable VSI");
782 /* Enable receiving broadcast packets */
783 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
784 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
785 if (ret != I40E_SUCCESS)
786 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
789 /* Apply link configure */
790 ret = i40e_apply_link_speed(dev);
791 if (I40E_SUCCESS != ret) {
792 PMD_DRV_LOG(ERR, "Fail to apply link setting");
799 i40e_vsi_switch_queues(vsi, FALSE);
805 i40e_dev_stop(struct rte_eth_dev *dev)
807 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
808 struct i40e_vsi *vsi = pf->main_vsi;
810 /* Disable all queues */
811 i40e_vsi_switch_queues(vsi, FALSE);
814 i40e_dev_set_link_down(dev);
816 /* un-map queues with interrupt registers */
817 i40e_vsi_disable_queues_intr(vsi);
818 i40e_vsi_queues_unbind_intr(vsi);
822 i40e_dev_close(struct rte_eth_dev *dev)
824 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
825 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
828 PMD_INIT_FUNC_TRACE();
832 /* Disable interrupt */
833 i40e_pf_disable_irq0(hw);
834 rte_intr_disable(&(dev->pci_dev->intr_handle));
836 /* shutdown and destroy the HMC */
837 i40e_shutdown_lan_hmc(hw);
839 /* release all the existing VSIs and VEBs */
840 i40e_vsi_release(pf->main_vsi);
842 /* shutdown the adminq */
843 i40e_aq_queue_shutdown(hw, true);
844 i40e_shutdown_adminq(hw);
846 i40e_res_pool_destroy(&pf->qp_pool);
847 i40e_res_pool_destroy(&pf->msix_pool);
849 /* force a PF reset to clean anything leftover */
850 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
851 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
852 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
853 I40E_WRITE_FLUSH(hw);
857 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
859 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
861 struct i40e_vsi *vsi = pf->main_vsi;
864 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
866 if (status != I40E_SUCCESS)
867 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
869 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
871 if (status != I40E_SUCCESS)
872 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
877 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
879 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
881 struct i40e_vsi *vsi = pf->main_vsi;
884 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
886 if (status != I40E_SUCCESS)
887 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
889 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
891 if (status != I40E_SUCCESS)
892 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
896 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
898 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
900 struct i40e_vsi *vsi = pf->main_vsi;
903 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
904 if (ret != I40E_SUCCESS)
905 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
909 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
913 struct i40e_vsi *vsi = pf->main_vsi;
916 if (dev->data->promiscuous == 1)
917 return; /* must remain in all_multicast mode */
919 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
920 vsi->seid, FALSE, NULL);
921 if (ret != I40E_SUCCESS)
922 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
926 * Set device link up.
929 i40e_dev_set_link_up(struct rte_eth_dev *dev)
931 /* re-apply link speed setting */
932 return i40e_apply_link_speed(dev);
936 * Set device link down.
939 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
941 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
942 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
945 return i40e_phy_conf_link(hw, abilities, speed);
949 i40e_dev_link_update(struct rte_eth_dev *dev,
950 __rte_unused int wait_to_complete)
952 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
953 struct i40e_link_status link_status;
954 struct rte_eth_link link, old;
957 memset(&link, 0, sizeof(link));
958 memset(&old, 0, sizeof(old));
959 memset(&link_status, 0, sizeof(link_status));
960 rte_i40e_dev_atomic_read_link_status(dev, &old);
962 /* Get link status information from hardware */
963 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
964 if (status != I40E_SUCCESS) {
965 link.link_speed = ETH_LINK_SPEED_100;
966 link.link_duplex = ETH_LINK_FULL_DUPLEX;
967 PMD_DRV_LOG(ERR, "Failed to get link info");
971 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
973 if (!link.link_status)
976 /* i40e uses full duplex only */
977 link.link_duplex = ETH_LINK_FULL_DUPLEX;
979 /* Parse the link status */
980 switch (link_status.link_speed) {
981 case I40E_LINK_SPEED_100MB:
982 link.link_speed = ETH_LINK_SPEED_100;
984 case I40E_LINK_SPEED_1GB:
985 link.link_speed = ETH_LINK_SPEED_1000;
987 case I40E_LINK_SPEED_10GB:
988 link.link_speed = ETH_LINK_SPEED_10G;
990 case I40E_LINK_SPEED_20GB:
991 link.link_speed = ETH_LINK_SPEED_20G;
993 case I40E_LINK_SPEED_40GB:
994 link.link_speed = ETH_LINK_SPEED_40G;
997 link.link_speed = ETH_LINK_SPEED_100;
1002 rte_i40e_dev_atomic_write_link_status(dev, &link);
1003 if (link.link_status == old.link_status)
1009 /* Get all the statistics of a VSI */
1011 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1013 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1014 struct i40e_eth_stats *nes = &vsi->eth_stats;
1015 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1016 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1018 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1019 vsi->offset_loaded, &oes->rx_bytes,
1021 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1022 vsi->offset_loaded, &oes->rx_unicast,
1024 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1025 vsi->offset_loaded, &oes->rx_multicast,
1026 &nes->rx_multicast);
1027 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1028 vsi->offset_loaded, &oes->rx_broadcast,
1029 &nes->rx_broadcast);
1030 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1031 &oes->rx_discards, &nes->rx_discards);
1032 /* GLV_REPC not supported */
1033 /* GLV_RMPC not supported */
1034 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1035 &oes->rx_unknown_protocol,
1036 &nes->rx_unknown_protocol);
1037 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1038 vsi->offset_loaded, &oes->tx_bytes,
1040 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1041 vsi->offset_loaded, &oes->tx_unicast,
1043 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1044 vsi->offset_loaded, &oes->tx_multicast,
1045 &nes->tx_multicast);
1046 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1047 vsi->offset_loaded, &oes->tx_broadcast,
1048 &nes->tx_broadcast);
1049 /* GLV_TDPC not supported */
1050 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1051 &oes->tx_errors, &nes->tx_errors);
1052 vsi->offset_loaded = true;
1054 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1056 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1057 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1058 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1059 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1060 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1061 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1062 nes->rx_unknown_protocol);
1063 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1064 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1065 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1066 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1067 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1068 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1069 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1073 /* Get all statistics of a port */
1075 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1078 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1079 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1080 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1081 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1083 /* Get statistics of struct i40e_eth_stats */
1084 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1085 I40E_GLPRT_GORCL(hw->port),
1086 pf->offset_loaded, &os->eth.rx_bytes,
1088 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1089 I40E_GLPRT_UPRCL(hw->port),
1090 pf->offset_loaded, &os->eth.rx_unicast,
1091 &ns->eth.rx_unicast);
1092 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1093 I40E_GLPRT_MPRCL(hw->port),
1094 pf->offset_loaded, &os->eth.rx_multicast,
1095 &ns->eth.rx_multicast);
1096 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1097 I40E_GLPRT_BPRCL(hw->port),
1098 pf->offset_loaded, &os->eth.rx_broadcast,
1099 &ns->eth.rx_broadcast);
1100 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1101 pf->offset_loaded, &os->eth.rx_discards,
1102 &ns->eth.rx_discards);
1103 /* GLPRT_REPC not supported */
1104 /* GLPRT_RMPC not supported */
1105 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1107 &os->eth.rx_unknown_protocol,
1108 &ns->eth.rx_unknown_protocol);
1109 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1110 I40E_GLPRT_GOTCL(hw->port),
1111 pf->offset_loaded, &os->eth.tx_bytes,
1113 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1114 I40E_GLPRT_UPTCL(hw->port),
1115 pf->offset_loaded, &os->eth.tx_unicast,
1116 &ns->eth.tx_unicast);
1117 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1118 I40E_GLPRT_MPTCL(hw->port),
1119 pf->offset_loaded, &os->eth.tx_multicast,
1120 &ns->eth.tx_multicast);
1121 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1122 I40E_GLPRT_BPTCL(hw->port),
1123 pf->offset_loaded, &os->eth.tx_broadcast,
1124 &ns->eth.tx_broadcast);
1125 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1126 pf->offset_loaded, &os->eth.tx_discards,
1127 &ns->eth.tx_discards);
1128 /* GLPRT_TEPC not supported */
1130 /* additional port specific stats */
1131 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1132 pf->offset_loaded, &os->tx_dropped_link_down,
1133 &ns->tx_dropped_link_down);
1134 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1135 pf->offset_loaded, &os->crc_errors,
1137 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1138 pf->offset_loaded, &os->illegal_bytes,
1139 &ns->illegal_bytes);
1140 /* GLPRT_ERRBC not supported */
1141 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1142 pf->offset_loaded, &os->mac_local_faults,
1143 &ns->mac_local_faults);
1144 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1145 pf->offset_loaded, &os->mac_remote_faults,
1146 &ns->mac_remote_faults);
1147 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1148 pf->offset_loaded, &os->rx_length_errors,
1149 &ns->rx_length_errors);
1150 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1151 pf->offset_loaded, &os->link_xon_rx,
1153 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1154 pf->offset_loaded, &os->link_xoff_rx,
1156 for (i = 0; i < 8; i++) {
1157 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1159 &os->priority_xon_rx[i],
1160 &ns->priority_xon_rx[i]);
1161 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1163 &os->priority_xoff_rx[i],
1164 &ns->priority_xoff_rx[i]);
1166 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1167 pf->offset_loaded, &os->link_xon_tx,
1169 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1170 pf->offset_loaded, &os->link_xoff_tx,
1172 for (i = 0; i < 8; i++) {
1173 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1175 &os->priority_xon_tx[i],
1176 &ns->priority_xon_tx[i]);
1177 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1179 &os->priority_xoff_tx[i],
1180 &ns->priority_xoff_tx[i]);
1181 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1183 &os->priority_xon_2_xoff[i],
1184 &ns->priority_xon_2_xoff[i]);
1186 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1187 I40E_GLPRT_PRC64L(hw->port),
1188 pf->offset_loaded, &os->rx_size_64,
1190 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1191 I40E_GLPRT_PRC127L(hw->port),
1192 pf->offset_loaded, &os->rx_size_127,
1194 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1195 I40E_GLPRT_PRC255L(hw->port),
1196 pf->offset_loaded, &os->rx_size_255,
1198 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1199 I40E_GLPRT_PRC511L(hw->port),
1200 pf->offset_loaded, &os->rx_size_511,
1202 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1203 I40E_GLPRT_PRC1023L(hw->port),
1204 pf->offset_loaded, &os->rx_size_1023,
1206 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1207 I40E_GLPRT_PRC1522L(hw->port),
1208 pf->offset_loaded, &os->rx_size_1522,
1210 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1211 I40E_GLPRT_PRC9522L(hw->port),
1212 pf->offset_loaded, &os->rx_size_big,
1214 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1215 pf->offset_loaded, &os->rx_undersize,
1217 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1218 pf->offset_loaded, &os->rx_fragments,
1220 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1221 pf->offset_loaded, &os->rx_oversize,
1223 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1224 pf->offset_loaded, &os->rx_jabber,
1226 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1227 I40E_GLPRT_PTC64L(hw->port),
1228 pf->offset_loaded, &os->tx_size_64,
1230 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1231 I40E_GLPRT_PTC127L(hw->port),
1232 pf->offset_loaded, &os->tx_size_127,
1234 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1235 I40E_GLPRT_PTC255L(hw->port),
1236 pf->offset_loaded, &os->tx_size_255,
1238 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1239 I40E_GLPRT_PTC511L(hw->port),
1240 pf->offset_loaded, &os->tx_size_511,
1242 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1243 I40E_GLPRT_PTC1023L(hw->port),
1244 pf->offset_loaded, &os->tx_size_1023,
1246 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1247 I40E_GLPRT_PTC1522L(hw->port),
1248 pf->offset_loaded, &os->tx_size_1522,
1250 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1251 I40E_GLPRT_PTC9522L(hw->port),
1252 pf->offset_loaded, &os->tx_size_big,
1254 /* GLPRT_MSPDC not supported */
1255 /* GLPRT_XEC not supported */
1257 pf->offset_loaded = true;
1260 i40e_update_vsi_stats(pf->main_vsi);
1262 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1263 ns->eth.rx_broadcast;
1264 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1265 ns->eth.tx_broadcast;
1266 stats->ibytes = ns->eth.rx_bytes;
1267 stats->obytes = ns->eth.tx_bytes;
1268 stats->oerrors = ns->eth.tx_errors;
1269 stats->imcasts = ns->eth.rx_multicast;
1272 stats->ibadcrc = ns->crc_errors;
1273 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1274 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1275 stats->imissed = ns->eth.rx_discards;
1276 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1278 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1279 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1280 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1281 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1282 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1283 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1284 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1285 ns->eth.rx_unknown_protocol);
1286 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1287 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1288 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1289 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1290 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1291 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1293 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1294 ns->tx_dropped_link_down);
1295 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1296 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1298 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1299 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1300 ns->mac_local_faults);
1301 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1302 ns->mac_remote_faults);
1303 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1304 ns->rx_length_errors);
1305 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1306 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1307 for (i = 0; i < 8; i++) {
1308 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1309 i, ns->priority_xon_rx[i]);
1310 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1311 i, ns->priority_xoff_rx[i]);
1313 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1314 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1315 for (i = 0; i < 8; i++) {
1316 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1317 i, ns->priority_xon_tx[i]);
1318 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1319 i, ns->priority_xoff_tx[i]);
1320 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1321 i, ns->priority_xon_2_xoff[i]);
1323 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1324 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1325 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1326 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1327 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1328 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1329 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1330 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1331 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1332 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1333 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1334 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1335 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1336 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1337 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1338 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1339 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1340 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1341 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1342 ns->mac_short_packet_dropped);
1343 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1344 ns->checksum_error);
1345 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1348 /* Reset the statistics */
1350 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1354 /* It results in reloading the start point of each counter */
1355 pf->offset_loaded = false;
1359 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1360 __rte_unused uint16_t queue_id,
1361 __rte_unused uint8_t stat_idx,
1362 __rte_unused uint8_t is_rx)
1364 PMD_INIT_FUNC_TRACE();
1370 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1372 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1373 struct i40e_vsi *vsi = pf->main_vsi;
1375 dev_info->max_rx_queues = vsi->nb_qps;
1376 dev_info->max_tx_queues = vsi->nb_qps;
1377 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1378 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1379 dev_info->max_mac_addrs = vsi->max_macaddrs;
1380 dev_info->max_vfs = dev->pci_dev->max_vfs;
1381 dev_info->rx_offload_capa =
1382 DEV_RX_OFFLOAD_VLAN_STRIP |
1383 DEV_RX_OFFLOAD_IPV4_CKSUM |
1384 DEV_RX_OFFLOAD_UDP_CKSUM |
1385 DEV_RX_OFFLOAD_TCP_CKSUM;
1386 dev_info->tx_offload_capa =
1387 DEV_TX_OFFLOAD_VLAN_INSERT |
1388 DEV_TX_OFFLOAD_IPV4_CKSUM |
1389 DEV_TX_OFFLOAD_UDP_CKSUM |
1390 DEV_TX_OFFLOAD_TCP_CKSUM |
1391 DEV_TX_OFFLOAD_SCTP_CKSUM;
1393 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1395 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1396 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1397 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1399 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1403 dev_info->default_txconf = (struct rte_eth_txconf) {
1405 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1406 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1407 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1409 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1410 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1411 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1417 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1419 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1420 struct i40e_vsi *vsi = pf->main_vsi;
1421 PMD_INIT_FUNC_TRACE();
1424 return i40e_vsi_add_vlan(vsi, vlan_id);
1426 return i40e_vsi_delete_vlan(vsi, vlan_id);
1430 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1431 __rte_unused uint16_t tpid)
1433 PMD_INIT_FUNC_TRACE();
1437 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440 struct i40e_vsi *vsi = pf->main_vsi;
1442 if (mask & ETH_VLAN_STRIP_MASK) {
1443 /* Enable or disable VLAN stripping */
1444 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1445 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1447 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1450 if (mask & ETH_VLAN_EXTEND_MASK) {
1451 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1452 i40e_vsi_config_double_vlan(vsi, TRUE);
1454 i40e_vsi_config_double_vlan(vsi, FALSE);
1459 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1460 __rte_unused uint16_t queue,
1461 __rte_unused int on)
1463 PMD_INIT_FUNC_TRACE();
1467 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1469 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1470 struct i40e_vsi *vsi = pf->main_vsi;
1471 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1472 struct i40e_vsi_vlan_pvid_info info;
1474 memset(&info, 0, sizeof(info));
1477 info.config.pvid = pvid;
1479 info.config.reject.tagged =
1480 data->dev_conf.txmode.hw_vlan_reject_tagged;
1481 info.config.reject.untagged =
1482 data->dev_conf.txmode.hw_vlan_reject_untagged;
1485 return i40e_vsi_vlan_pvid_set(vsi, &info);
1489 i40e_dev_led_on(struct rte_eth_dev *dev)
1491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492 uint32_t mode = i40e_led_get(hw);
1495 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1501 i40e_dev_led_off(struct rte_eth_dev *dev)
1503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 uint32_t mode = i40e_led_get(hw);
1507 i40e_led_set(hw, 0, false);
1513 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1514 __rte_unused struct rte_eth_fc_conf *fc_conf)
1516 PMD_INIT_FUNC_TRACE();
1522 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1523 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1525 PMD_INIT_FUNC_TRACE();
1530 /* Add a MAC address, and update filters */
1532 i40e_macaddr_add(struct rte_eth_dev *dev,
1533 struct ether_addr *mac_addr,
1534 __attribute__((unused)) uint32_t index,
1535 __attribute__((unused)) uint32_t pool)
1537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1538 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539 struct i40e_vsi *vsi = pf->main_vsi;
1540 struct ether_addr old_mac;
1543 if (!is_valid_assigned_ether_addr(mac_addr)) {
1544 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1548 if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1549 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1553 /* Write mac address */
1554 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1555 mac_addr->addr_bytes, NULL);
1556 if (ret != I40E_SUCCESS) {
1557 PMD_DRV_LOG(ERR, "Failed to write mac address");
1561 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1562 (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1565 ret = i40e_vsi_add_mac(vsi, mac_addr);
1566 if (ret != I40E_SUCCESS) {
1567 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1571 ether_addr_copy(mac_addr, &pf->dev_addr);
1572 i40e_vsi_delete_mac(vsi, &old_mac);
1575 /* Remove a MAC address, and update filters */
1577 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1579 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1580 struct i40e_vsi *vsi = pf->main_vsi;
1581 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1582 struct ether_addr *macaddr;
1584 struct i40e_hw *hw =
1585 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587 if (index >= vsi->max_macaddrs)
1590 macaddr = &(data->mac_addrs[index]);
1591 if (!is_valid_assigned_ether_addr(macaddr))
1594 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1595 hw->mac.perm_addr, NULL);
1596 if (ret != I40E_SUCCESS) {
1597 PMD_DRV_LOG(ERR, "Failed to write mac address");
1601 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1603 ret = i40e_vsi_delete_mac(vsi, macaddr);
1604 if (ret != I40E_SUCCESS)
1607 /* Clear device address as it has been removed */
1608 if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1609 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1613 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1614 struct rte_eth_rss_reta *reta_conf)
1616 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1620 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1622 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1624 mask = (uint8_t)((reta_conf->mask_hi >>
1633 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1635 for (j = 0, lut = 0; j < 4; j++) {
1636 if (mask & (0x1 << j))
1637 lut |= reta_conf->reta[i + j] << (8 * j);
1639 lut |= l & (0xFF << (8 * j));
1641 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1648 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1649 struct rte_eth_rss_reta *reta_conf)
1651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1655 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1657 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1659 mask = (uint8_t)((reta_conf->mask_hi >>
1665 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1666 for (j = 0; j < 4; j++) {
1667 if (mask & (0x1 << j))
1668 reta_conf->reta[i + j] =
1669 (uint8_t)((lut >> (8 * j)) & 0xFF);
1677 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1678 * @hw: pointer to the HW structure
1679 * @mem: pointer to mem struct to fill out
1680 * @size: size of memory requested
1681 * @alignment: what to align the allocation to
1683 enum i40e_status_code
1684 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1685 struct i40e_dma_mem *mem,
1689 static uint64_t id = 0;
1690 const struct rte_memzone *mz = NULL;
1691 char z_name[RTE_MEMZONE_NAMESIZE];
1694 return I40E_ERR_PARAM;
1697 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1698 #ifdef RTE_LIBRTE_XEN_DOM0
1699 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1702 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1705 return I40E_ERR_NO_MEMORY;
1710 #ifdef RTE_LIBRTE_XEN_DOM0
1711 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1713 mem->pa = mz->phys_addr;
1716 return I40E_SUCCESS;
1720 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1721 * @hw: pointer to the HW structure
1722 * @mem: ptr to mem struct to free
1724 enum i40e_status_code
1725 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1726 struct i40e_dma_mem *mem)
1728 if (!mem || !mem->va)
1729 return I40E_ERR_PARAM;
1734 return I40E_SUCCESS;
1738 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1739 * @hw: pointer to the HW structure
1740 * @mem: pointer to mem struct to fill out
1741 * @size: size of memory requested
1743 enum i40e_status_code
1744 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1745 struct i40e_virt_mem *mem,
1749 return I40E_ERR_PARAM;
1752 mem->va = rte_zmalloc("i40e", size, 0);
1755 return I40E_SUCCESS;
1757 return I40E_ERR_NO_MEMORY;
1761 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1762 * @hw: pointer to the HW structure
1763 * @mem: pointer to mem struct to free
1765 enum i40e_status_code
1766 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1767 struct i40e_virt_mem *mem)
1770 return I40E_ERR_PARAM;
1775 return I40E_SUCCESS;
1779 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1781 rte_spinlock_init(&sp->spinlock);
1785 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1787 rte_spinlock_lock(&sp->spinlock);
1791 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1793 rte_spinlock_unlock(&sp->spinlock);
1797 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1803 * Get the hardware capabilities, which will be parsed
1804 * and saved into struct i40e_hw.
1807 i40e_get_cap(struct i40e_hw *hw)
1809 struct i40e_aqc_list_capabilities_element_resp *buf;
1810 uint16_t len, size = 0;
1813 /* Calculate a huge enough buff for saving response data temporarily */
1814 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1815 I40E_MAX_CAP_ELE_NUM;
1816 buf = rte_zmalloc("i40e", len, 0);
1818 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1819 return I40E_ERR_NO_MEMORY;
1822 /* Get, parse the capabilities and save it to hw */
1823 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1824 i40e_aqc_opc_list_func_capabilities, NULL);
1825 if (ret != I40E_SUCCESS)
1826 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1828 /* Free the temporary buffer after being used */
1835 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1837 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1838 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1839 uint16_t sum_queues = 0, sum_vsis;
1841 /* First check if FW support SRIOV */
1842 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1843 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1847 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1848 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1849 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1850 /* Allocate queues for pf */
1851 if (hw->func_caps.rss) {
1852 pf->flags |= I40E_FLAG_RSS;
1853 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1854 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1855 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1858 sum_queues = pf->lan_nb_qps;
1859 /* Default VSI is not counted in */
1861 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1863 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1864 pf->flags |= I40E_FLAG_SRIOV;
1865 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1866 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1867 PMD_INIT_LOG(ERR, "Config VF number %u, "
1868 "max supported %u.",
1869 dev->pci_dev->max_vfs,
1870 hw->func_caps.num_vfs);
1873 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1874 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1875 "max support %u queues.",
1876 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1879 pf->vf_num = dev->pci_dev->max_vfs;
1880 sum_queues += pf->vf_nb_qps * pf->vf_num;
1881 sum_vsis += pf->vf_num;
1882 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1883 pf->vf_num, pf->vf_nb_qps);
1887 if (hw->func_caps.vmdq) {
1888 pf->flags |= I40E_FLAG_VMDQ;
1889 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1890 sum_queues += pf->vmdq_nb_qps;
1892 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1895 if (hw->func_caps.fd) {
1896 pf->flags |= I40E_FLAG_FDIR;
1897 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1899 * Each flow director consumes one VSI and one queue,
1900 * but can't calculate out predictably here.
1904 if (sum_vsis > pf->max_num_vsi ||
1905 sum_queues > hw->func_caps.num_rx_qp) {
1906 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1907 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1908 pf->max_num_vsi, sum_vsis);
1909 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1910 hw->func_caps.num_rx_qp, sum_queues);
1914 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1916 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1917 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1918 sum_vsis, hw->func_caps.num_msix_vectors);
1921 return I40E_SUCCESS;
1925 i40e_pf_get_switch_config(struct i40e_pf *pf)
1927 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1928 struct i40e_aqc_get_switch_config_resp *switch_config;
1929 struct i40e_aqc_switch_config_element_resp *element;
1930 uint16_t start_seid = 0, num_reported;
1933 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1934 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1935 if (!switch_config) {
1936 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1940 /* Get the switch configurations */
1941 ret = i40e_aq_get_switch_config(hw, switch_config,
1942 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1943 if (ret != I40E_SUCCESS) {
1944 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1947 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1948 if (num_reported != 1) { /* The number should be 1 */
1949 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1953 /* Parse the switch configuration elements */
1954 element = &(switch_config->element[0]);
1955 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1956 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1957 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1959 PMD_DRV_LOG(INFO, "Unknown element type");
1962 rte_free(switch_config);
1968 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1971 struct pool_entry *entry;
1973 if (pool == NULL || num == 0)
1976 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1977 if (entry == NULL) {
1978 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1982 /* queue heap initialize */
1983 pool->num_free = num;
1984 pool->num_alloc = 0;
1986 LIST_INIT(&pool->alloc_list);
1987 LIST_INIT(&pool->free_list);
1989 /* Initialize element */
1993 LIST_INSERT_HEAD(&pool->free_list, entry, next);
1998 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2000 struct pool_entry *entry;
2005 LIST_FOREACH(entry, &pool->alloc_list, next) {
2006 LIST_REMOVE(entry, next);
2010 LIST_FOREACH(entry, &pool->free_list, next) {
2011 LIST_REMOVE(entry, next);
2016 pool->num_alloc = 0;
2018 LIST_INIT(&pool->alloc_list);
2019 LIST_INIT(&pool->free_list);
2023 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2026 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2027 uint32_t pool_offset;
2031 PMD_DRV_LOG(ERR, "Invalid parameter");
2035 pool_offset = base - pool->base;
2036 /* Lookup in alloc list */
2037 LIST_FOREACH(entry, &pool->alloc_list, next) {
2038 if (entry->base == pool_offset) {
2039 valid_entry = entry;
2040 LIST_REMOVE(entry, next);
2045 /* Not find, return */
2046 if (valid_entry == NULL) {
2047 PMD_DRV_LOG(ERR, "Failed to find entry");
2052 * Found it, move it to free list and try to merge.
2053 * In order to make merge easier, always sort it by qbase.
2054 * Find adjacent prev and last entries.
2057 LIST_FOREACH(entry, &pool->free_list, next) {
2058 if (entry->base > valid_entry->base) {
2066 /* Try to merge with next one*/
2068 /* Merge with next one */
2069 if (valid_entry->base + valid_entry->len == next->base) {
2070 next->base = valid_entry->base;
2071 next->len += valid_entry->len;
2072 rte_free(valid_entry);
2079 /* Merge with previous one */
2080 if (prev->base + prev->len == valid_entry->base) {
2081 prev->len += valid_entry->len;
2082 /* If it merge with next one, remove next node */
2084 LIST_REMOVE(valid_entry, next);
2085 rte_free(valid_entry);
2087 rte_free(valid_entry);
2093 /* Not find any entry to merge, insert */
2096 LIST_INSERT_AFTER(prev, valid_entry, next);
2097 else if (next != NULL)
2098 LIST_INSERT_BEFORE(next, valid_entry, next);
2099 else /* It's empty list, insert to head */
2100 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2103 pool->num_free += valid_entry->len;
2104 pool->num_alloc -= valid_entry->len;
2110 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2113 struct pool_entry *entry, *valid_entry;
2115 if (pool == NULL || num == 0) {
2116 PMD_DRV_LOG(ERR, "Invalid parameter");
2120 if (pool->num_free < num) {
2121 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2122 num, pool->num_free);
2127 /* Lookup in free list and find most fit one */
2128 LIST_FOREACH(entry, &pool->free_list, next) {
2129 if (entry->len >= num) {
2131 if (entry->len == num) {
2132 valid_entry = entry;
2135 if (valid_entry == NULL || valid_entry->len > entry->len)
2136 valid_entry = entry;
2140 /* Not find one to satisfy the request, return */
2141 if (valid_entry == NULL) {
2142 PMD_DRV_LOG(ERR, "No valid entry found");
2146 * The entry have equal queue number as requested,
2147 * remove it from alloc_list.
2149 if (valid_entry->len == num) {
2150 LIST_REMOVE(valid_entry, next);
2153 * The entry have more numbers than requested,
2154 * create a new entry for alloc_list and minus its
2155 * queue base and number in free_list.
2157 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2158 if (entry == NULL) {
2159 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2163 entry->base = valid_entry->base;
2165 valid_entry->base += num;
2166 valid_entry->len -= num;
2167 valid_entry = entry;
2170 /* Insert it into alloc list, not sorted */
2171 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2173 pool->num_free -= valid_entry->len;
2174 pool->num_alloc += valid_entry->len;
2176 return (valid_entry->base + pool->base);
2180 * bitmap_is_subset - Check whether src2 is subset of src1
2183 bitmap_is_subset(uint8_t src1, uint8_t src2)
2185 return !((src1 ^ src2) & src2);
2189 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2191 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2193 /* If DCB is not supported, only default TC is supported */
2194 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2195 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2199 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2200 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2201 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2205 return I40E_SUCCESS;
2209 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2210 struct i40e_vsi_vlan_pvid_info *info)
2213 struct i40e_vsi_context ctxt;
2214 uint8_t vlan_flags = 0;
2217 if (vsi == NULL || info == NULL) {
2218 PMD_DRV_LOG(ERR, "invalid parameters");
2219 return I40E_ERR_PARAM;
2223 vsi->info.pvid = info->config.pvid;
2225 * If insert pvid is enabled, only tagged pkts are
2226 * allowed to be sent out.
2228 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2229 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2232 if (info->config.reject.tagged == 0)
2233 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2235 if (info->config.reject.untagged == 0)
2236 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2238 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2239 I40E_AQ_VSI_PVLAN_MODE_MASK);
2240 vsi->info.port_vlan_flags |= vlan_flags;
2241 vsi->info.valid_sections =
2242 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2243 memset(&ctxt, 0, sizeof(ctxt));
2244 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2245 ctxt.seid = vsi->seid;
2247 hw = I40E_VSI_TO_HW(vsi);
2248 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2249 if (ret != I40E_SUCCESS)
2250 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2256 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2258 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2260 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2262 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2263 if (ret != I40E_SUCCESS)
2267 PMD_DRV_LOG(ERR, "seid not valid");
2271 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2272 tc_bw_data.tc_valid_bits = enabled_tcmap;
2273 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2274 tc_bw_data.tc_bw_credits[i] =
2275 (enabled_tcmap & (1 << i)) ? 1 : 0;
2277 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2278 if (ret != I40E_SUCCESS) {
2279 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2283 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2284 sizeof(vsi->info.qs_handle));
2285 return I40E_SUCCESS;
2289 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2290 struct i40e_aqc_vsi_properties_data *info,
2291 uint8_t enabled_tcmap)
2293 int ret, total_tc = 0, i;
2294 uint16_t qpnum_per_tc, bsf, qp_idx;
2296 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2297 if (ret != I40E_SUCCESS)
2300 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2301 if (enabled_tcmap & (1 << i))
2303 vsi->enabled_tc = enabled_tcmap;
2305 /* Number of queues per enabled TC */
2306 qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2307 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2308 bsf = rte_bsf32(qpnum_per_tc);
2310 /* Adjust the queue number to actual queues that can be applied */
2311 vsi->nb_qps = qpnum_per_tc * total_tc;
2314 * Configure TC and queue mapping parameters, for enabled TC,
2315 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2316 * default queue will serve it.
2319 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2320 if (vsi->enabled_tc & (1 << i)) {
2321 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2322 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2323 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2324 qp_idx += qpnum_per_tc;
2326 info->tc_mapping[i] = 0;
2329 /* Associate queue number with VSI */
2330 if (vsi->type == I40E_VSI_SRIOV) {
2331 info->mapping_flags |=
2332 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2333 for (i = 0; i < vsi->nb_qps; i++)
2334 info->queue_mapping[i] =
2335 rte_cpu_to_le_16(vsi->base_queue + i);
2337 info->mapping_flags |=
2338 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2339 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2341 info->valid_sections =
2342 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2344 return I40E_SUCCESS;
2348 i40e_veb_release(struct i40e_veb *veb)
2350 struct i40e_vsi *vsi;
2353 if (veb == NULL || veb->associate_vsi == NULL)
2356 if (!TAILQ_EMPTY(&veb->head)) {
2357 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2361 vsi = veb->associate_vsi;
2362 hw = I40E_VSI_TO_HW(vsi);
2364 vsi->uplink_seid = veb->uplink_seid;
2365 i40e_aq_delete_element(hw, veb->seid, NULL);
2368 return I40E_SUCCESS;
2372 static struct i40e_veb *
2373 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2375 struct i40e_veb *veb;
2379 if (NULL == pf || vsi == NULL) {
2380 PMD_DRV_LOG(ERR, "veb setup failed, "
2381 "associated VSI shouldn't null");
2384 hw = I40E_PF_TO_HW(pf);
2386 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2388 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2392 veb->associate_vsi = vsi;
2393 TAILQ_INIT(&veb->head);
2394 veb->uplink_seid = vsi->uplink_seid;
2396 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2397 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2399 if (ret != I40E_SUCCESS) {
2400 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2401 hw->aq.asq_last_status);
2405 /* get statistics index */
2406 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2407 &veb->stats_idx, NULL, NULL, NULL);
2408 if (ret != I40E_SUCCESS) {
2409 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2410 hw->aq.asq_last_status);
2414 /* Get VEB bandwidth, to be implemented */
2415 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2416 vsi->uplink_seid = veb->seid;
2425 i40e_vsi_release(struct i40e_vsi *vsi)
2429 struct i40e_vsi_list *vsi_list;
2431 struct i40e_mac_filter *f;
2434 return I40E_SUCCESS;
2436 pf = I40E_VSI_TO_PF(vsi);
2437 hw = I40E_VSI_TO_HW(vsi);
2439 /* VSI has child to attach, release child first */
2441 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2442 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2444 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2446 i40e_veb_release(vsi->veb);
2449 /* Remove all macvlan filters of the VSI */
2450 i40e_vsi_remove_all_macvlan_filter(vsi);
2451 TAILQ_FOREACH(f, &vsi->mac_list, next)
2454 if (vsi->type != I40E_VSI_MAIN) {
2455 /* Remove vsi from parent's sibling list */
2456 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2457 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2458 return I40E_ERR_PARAM;
2460 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2461 &vsi->sib_vsi_list, list);
2463 /* Remove all switch element of the VSI */
2464 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2465 if (ret != I40E_SUCCESS)
2466 PMD_DRV_LOG(ERR, "Failed to delete element");
2468 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2470 if (vsi->type != I40E_VSI_SRIOV)
2471 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2474 return I40E_SUCCESS;
2478 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2480 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2481 struct i40e_aqc_remove_macvlan_element_data def_filter;
2484 if (vsi->type != I40E_VSI_MAIN)
2485 return I40E_ERR_CONFIG;
2486 memset(&def_filter, 0, sizeof(def_filter));
2487 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2489 def_filter.vlan_tag = 0;
2490 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2491 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2492 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2493 if (ret != I40E_SUCCESS) {
2494 struct i40e_mac_filter *f;
2496 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2498 /* It needs to add the permanent mac into mac list */
2499 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2501 PMD_DRV_LOG(ERR, "failed to allocate memory");
2502 return I40E_ERR_NO_MEMORY;
2504 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2506 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2512 return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2516 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2518 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2519 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2520 struct i40e_hw *hw = &vsi->adapter->hw;
2524 memset(&bw_config, 0, sizeof(bw_config));
2525 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2526 if (ret != I40E_SUCCESS) {
2527 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2528 hw->aq.asq_last_status);
2532 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2533 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2534 &ets_sla_config, NULL);
2535 if (ret != I40E_SUCCESS) {
2536 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2537 "configuration %u", hw->aq.asq_last_status);
2541 /* Not store the info yet, just print out */
2542 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2543 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2544 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2545 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2546 ets_sla_config.share_credits[i]);
2547 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2548 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2549 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2550 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2559 i40e_vsi_setup(struct i40e_pf *pf,
2560 enum i40e_vsi_type type,
2561 struct i40e_vsi *uplink_vsi,
2562 uint16_t user_param)
2564 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2565 struct i40e_vsi *vsi;
2567 struct i40e_vsi_context ctxt;
2568 struct ether_addr broadcast =
2569 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2571 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2572 PMD_DRV_LOG(ERR, "VSI setup failed, "
2573 "VSI link shouldn't be NULL");
2577 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2578 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2579 "uplink VSI should be NULL");
2583 /* If uplink vsi didn't setup VEB, create one first */
2584 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2585 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2587 if (NULL == uplink_vsi->veb) {
2588 PMD_DRV_LOG(ERR, "VEB setup failed");
2593 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2595 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2598 TAILQ_INIT(&vsi->mac_list);
2600 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2601 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2602 vsi->parent_vsi = uplink_vsi;
2603 vsi->user_param = user_param;
2604 /* Allocate queues */
2605 switch (vsi->type) {
2606 case I40E_VSI_MAIN :
2607 vsi->nb_qps = pf->lan_nb_qps;
2609 case I40E_VSI_SRIOV :
2610 vsi->nb_qps = pf->vf_nb_qps;
2615 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2617 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2621 vsi->base_queue = ret;
2623 /* VF has MSIX interrupt in VF range, don't allocate here */
2624 if (type != I40E_VSI_SRIOV) {
2625 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2627 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2628 goto fail_queue_alloc;
2630 vsi->msix_intr = ret;
2634 if (type == I40E_VSI_MAIN) {
2635 /* For main VSI, no need to add since it's default one */
2636 vsi->uplink_seid = pf->mac_seid;
2637 vsi->seid = pf->main_vsi_seid;
2638 /* Bind queues with specific MSIX interrupt */
2640 * Needs 2 interrupt at least, one for misc cause which will
2641 * enabled from OS side, Another for queues binding the
2642 * interrupt from device side only.
2645 /* Get default VSI parameters from hardware */
2646 memset(&ctxt, 0, sizeof(ctxt));
2647 ctxt.seid = vsi->seid;
2648 ctxt.pf_num = hw->pf_id;
2649 ctxt.uplink_seid = vsi->uplink_seid;
2651 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2652 if (ret != I40E_SUCCESS) {
2653 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2654 goto fail_msix_alloc;
2656 (void)rte_memcpy(&vsi->info, &ctxt.info,
2657 sizeof(struct i40e_aqc_vsi_properties_data));
2658 vsi->vsi_id = ctxt.vsi_number;
2659 vsi->info.valid_sections = 0;
2661 /* Configure tc, enabled TC0 only */
2662 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2664 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2665 goto fail_msix_alloc;
2668 /* TC, queue mapping */
2669 memset(&ctxt, 0, sizeof(ctxt));
2670 vsi->info.valid_sections |=
2671 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2672 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2673 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2674 (void)rte_memcpy(&ctxt.info, &vsi->info,
2675 sizeof(struct i40e_aqc_vsi_properties_data));
2676 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2677 I40E_DEFAULT_TCMAP);
2678 if (ret != I40E_SUCCESS) {
2679 PMD_DRV_LOG(ERR, "Failed to configure "
2680 "TC queue mapping");
2681 goto fail_msix_alloc;
2683 ctxt.seid = vsi->seid;
2684 ctxt.pf_num = hw->pf_id;
2685 ctxt.uplink_seid = vsi->uplink_seid;
2688 /* Update VSI parameters */
2689 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2690 if (ret != I40E_SUCCESS) {
2691 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2692 goto fail_msix_alloc;
2695 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2696 sizeof(vsi->info.tc_mapping));
2697 (void)rte_memcpy(&vsi->info.queue_mapping,
2698 &ctxt.info.queue_mapping,
2699 sizeof(vsi->info.queue_mapping));
2700 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2701 vsi->info.valid_sections = 0;
2703 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2707 * Updating default filter settings are necessary to prevent
2708 * reception of tagged packets.
2709 * Some old firmware configurations load a default macvlan
2710 * filter which accepts both tagged and untagged packets.
2711 * The updating is to use a normal filter instead if needed.
2712 * For NVM 4.2.2 or after, the updating is not needed anymore.
2713 * The firmware with correct configurations load the default
2714 * macvlan filter which is expected and cannot be removed.
2716 i40e_update_default_filter_setting(vsi);
2717 } else if (type == I40E_VSI_SRIOV) {
2718 memset(&ctxt, 0, sizeof(ctxt));
2720 * For other VSI, the uplink_seid equals to uplink VSI's
2721 * uplink_seid since they share same VEB
2723 vsi->uplink_seid = uplink_vsi->uplink_seid;
2724 ctxt.pf_num = hw->pf_id;
2725 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2726 ctxt.uplink_seid = vsi->uplink_seid;
2727 ctxt.connection_type = 0x1;
2728 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2730 /* Configure switch ID */
2731 ctxt.info.valid_sections |=
2732 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2733 ctxt.info.switch_id =
2734 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2735 /* Configure port/vlan */
2736 ctxt.info.valid_sections |=
2737 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2738 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2739 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2740 I40E_DEFAULT_TCMAP);
2741 if (ret != I40E_SUCCESS) {
2742 PMD_DRV_LOG(ERR, "Failed to configure "
2743 "TC queue mapping");
2744 goto fail_msix_alloc;
2746 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2747 ctxt.info.valid_sections |=
2748 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2750 * Since VSI is not created yet, only configure parameter,
2751 * will add vsi below.
2755 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2756 goto fail_msix_alloc;
2759 if (vsi->type != I40E_VSI_MAIN) {
2760 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2762 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2763 hw->aq.asq_last_status);
2764 goto fail_msix_alloc;
2766 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2767 vsi->info.valid_sections = 0;
2768 vsi->seid = ctxt.seid;
2769 vsi->vsi_id = ctxt.vsi_number;
2770 vsi->sib_vsi_list.vsi = vsi;
2771 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2772 &vsi->sib_vsi_list, list);
2775 /* MAC/VLAN configuration */
2776 ret = i40e_vsi_add_mac(vsi, &broadcast);
2777 if (ret != I40E_SUCCESS) {
2778 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2779 goto fail_msix_alloc;
2782 /* Get VSI BW information */
2783 i40e_vsi_dump_bw_config(vsi);
2786 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2788 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2794 /* Configure vlan stripping on or off */
2796 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2798 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2799 struct i40e_vsi_context ctxt;
2801 int ret = I40E_SUCCESS;
2803 /* Check if it has been already on or off */
2804 if (vsi->info.valid_sections &
2805 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2807 if ((vsi->info.port_vlan_flags &
2808 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2809 return 0; /* already on */
2811 if ((vsi->info.port_vlan_flags &
2812 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2813 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2814 return 0; /* already off */
2819 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2821 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2822 vsi->info.valid_sections =
2823 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2824 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2825 vsi->info.port_vlan_flags |= vlan_flags;
2826 ctxt.seid = vsi->seid;
2827 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2828 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2830 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2831 on ? "enable" : "disable");
2837 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2839 struct rte_eth_dev_data *data = dev->data;
2842 /* Apply vlan offload setting */
2843 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2845 /* Apply double-vlan setting, not implemented yet */
2847 /* Apply pvid setting */
2848 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2849 data->dev_conf.txmode.hw_vlan_insert_pvid);
2851 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2857 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2859 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2861 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2865 i40e_update_flow_control(struct i40e_hw *hw)
2867 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2868 struct i40e_link_status link_status;
2869 uint32_t rxfc = 0, txfc = 0, reg;
2873 memset(&link_status, 0, sizeof(link_status));
2874 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2875 if (ret != I40E_SUCCESS) {
2876 PMD_DRV_LOG(ERR, "Failed to get link status information");
2877 goto write_reg; /* Disable flow control */
2880 an_info = hw->phy.link_info.an_info;
2881 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2882 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2883 ret = I40E_ERR_NOT_READY;
2884 goto write_reg; /* Disable flow control */
2887 * If link auto negotiation is enabled, flow control needs to
2888 * be configured according to it
2890 switch (an_info & I40E_LINK_PAUSE_RXTX) {
2891 case I40E_LINK_PAUSE_RXTX:
2894 hw->fc.current_mode = I40E_FC_FULL;
2896 case I40E_AQ_LINK_PAUSE_RX:
2898 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2900 case I40E_AQ_LINK_PAUSE_TX:
2902 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2905 hw->fc.current_mode = I40E_FC_NONE;
2910 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2911 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2912 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2913 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2914 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2915 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2922 i40e_pf_setup(struct i40e_pf *pf)
2924 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2925 struct i40e_filter_control_settings settings;
2926 struct rte_eth_dev_data *dev_data = pf->dev_data;
2927 struct i40e_vsi *vsi;
2930 /* Clear all stats counters */
2931 pf->offset_loaded = FALSE;
2932 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2933 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2935 ret = i40e_pf_get_switch_config(pf);
2936 if (ret != I40E_SUCCESS) {
2937 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2942 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2944 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2945 return I40E_ERR_NOT_READY;
2948 dev_data->nb_rx_queues = vsi->nb_qps;
2949 dev_data->nb_tx_queues = vsi->nb_qps;
2951 /* Configure filter control */
2952 memset(&settings, 0, sizeof(settings));
2953 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2954 /* Enable ethtype and macvlan filters */
2955 settings.enable_ethtype = TRUE;
2956 settings.enable_macvlan = TRUE;
2957 ret = i40e_set_filter_control(hw, &settings);
2959 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2962 /* Update flow control according to the auto negotiation */
2963 i40e_update_flow_control(hw);
2965 return I40E_SUCCESS;
2969 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2975 * Set or clear TX Queue Disable flags,
2976 * which is required by hardware.
2978 i40e_pre_tx_queue_cfg(hw, q_idx, on);
2979 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2981 /* Wait until the request is finished */
2982 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2983 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2984 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2985 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2986 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2992 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2993 return I40E_SUCCESS; /* already on, skip next steps */
2995 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2996 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2998 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2999 return I40E_SUCCESS; /* already off, skip next steps */
3000 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3002 /* Write the register */
3003 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3004 /* Check the result */
3005 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3006 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3007 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3009 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3010 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3013 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3014 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3018 /* Check if it is timeout */
3019 if (j >= I40E_CHK_Q_ENA_COUNT) {
3020 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3021 (on ? "enable" : "disable"), q_idx);
3022 return I40E_ERR_TIMEOUT;
3025 return I40E_SUCCESS;
3028 /* Swith on or off the tx queues */
3030 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3032 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3033 struct i40e_tx_queue *txq;
3034 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3038 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3039 txq = dev_data->tx_queues[i];
3040 /* Don't operate the queue if not configured or
3041 * if starting only per queue */
3042 if (!txq->q_set || (on && txq->tx_deferred_start))
3045 ret = i40e_dev_tx_queue_start(dev, i);
3047 ret = i40e_dev_tx_queue_stop(dev, i);
3048 if ( ret != I40E_SUCCESS)
3052 return I40E_SUCCESS;
3056 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3061 /* Wait until the request is finished */
3062 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3063 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3064 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3065 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3066 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3071 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3072 return I40E_SUCCESS; /* Already on, skip next steps */
3073 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3075 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3076 return I40E_SUCCESS; /* Already off, skip next steps */
3077 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3080 /* Write the register */
3081 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3082 /* Check the result */
3083 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3084 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3085 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3087 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3088 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3091 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3092 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3097 /* Check if it is timeout */
3098 if (j >= I40E_CHK_Q_ENA_COUNT) {
3099 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3100 (on ? "enable" : "disable"), q_idx);
3101 return I40E_ERR_TIMEOUT;
3104 return I40E_SUCCESS;
3106 /* Switch on or off the rx queues */
3108 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3110 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3111 struct i40e_rx_queue *rxq;
3112 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3116 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3117 rxq = dev_data->rx_queues[i];
3118 /* Don't operate the queue if not configured or
3119 * if starting only per queue */
3120 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3123 ret = i40e_dev_rx_queue_start(dev, i);
3125 ret = i40e_dev_rx_queue_stop(dev, i);
3126 if (ret != I40E_SUCCESS)
3130 return I40E_SUCCESS;
3133 /* Switch on or off all the rx/tx queues */
3135 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3140 /* enable rx queues before enabling tx queues */
3141 ret = i40e_vsi_switch_rx_queues(vsi, on);
3143 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3146 ret = i40e_vsi_switch_tx_queues(vsi, on);
3148 /* Stop tx queues before stopping rx queues */
3149 ret = i40e_vsi_switch_tx_queues(vsi, on);
3151 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3154 ret = i40e_vsi_switch_rx_queues(vsi, on);
3160 /* Initialize VSI for TX */
3162 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3164 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3165 struct rte_eth_dev_data *data = pf->dev_data;
3167 uint32_t ret = I40E_SUCCESS;
3169 for (i = 0; i < data->nb_tx_queues; i++) {
3170 ret = i40e_tx_queue_init(data->tx_queues[i]);
3171 if (ret != I40E_SUCCESS)
3178 /* Initialize VSI for RX */
3180 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3182 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3183 struct rte_eth_dev_data *data = pf->dev_data;
3184 int ret = I40E_SUCCESS;
3187 i40e_pf_config_mq_rx(pf);
3188 for (i = 0; i < data->nb_rx_queues; i++) {
3189 ret = i40e_rx_queue_init(data->rx_queues[i]);
3190 if (ret != I40E_SUCCESS) {
3191 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3200 /* Initialize VSI */
3202 i40e_vsi_init(struct i40e_vsi *vsi)
3206 err = i40e_vsi_tx_init(vsi);
3208 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3211 err = i40e_vsi_rx_init(vsi);
3213 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3221 i40e_stat_update_32(struct i40e_hw *hw,
3229 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3233 if (new_data >= *offset)
3234 *stat = (uint64_t)(new_data - *offset);
3236 *stat = (uint64_t)((new_data +
3237 ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3241 i40e_stat_update_48(struct i40e_hw *hw,
3250 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3251 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3252 I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3257 if (new_data >= *offset)
3258 *stat = new_data - *offset;
3260 *stat = (uint64_t)((new_data +
3261 ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3263 *stat &= I40E_48_BIT_MASK;
3268 i40e_pf_disable_irq0(struct i40e_hw *hw)
3270 /* Disable all interrupt types */
3271 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3272 I40E_WRITE_FLUSH(hw);
3277 i40e_pf_enable_irq0(struct i40e_hw *hw)
3279 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3280 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3281 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3282 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3283 I40E_WRITE_FLUSH(hw);
3287 i40e_pf_config_irq0(struct i40e_hw *hw)
3291 /* read pending request and disable first */
3292 i40e_pf_disable_irq0(hw);
3294 * Enable all interrupt error options to detect possible errors,
3295 * other informative int are ignored
3297 enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3298 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3299 I40E_PFINT_ICR0_ENA_GRST_MASK |
3300 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3301 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3302 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3303 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3304 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3306 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3307 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3308 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3310 /* Link no queues with irq0 */
3311 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3312 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3316 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3322 uint32_t index, offset, val;
3327 * Try to find which VF trigger a reset, use absolute VF id to access
3328 * since the reg is global register.
3330 for (i = 0; i < pf->vf_num; i++) {
3331 abs_vf_id = hw->func_caps.vf_base_id + i;
3332 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3333 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3334 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3335 /* VFR event occured */
3336 if (val & (0x1 << offset)) {
3339 /* Clear the event first */
3340 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3342 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3344 * Only notify a VF reset event occured,
3345 * don't trigger another SW reset
3347 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3348 if (ret != I40E_SUCCESS)
3349 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3355 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3357 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358 struct i40e_arq_event_info info;
3359 uint16_t pending, opcode;
3362 info.buf_len = I40E_AQ_BUF_SZ;
3363 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3364 if (!info.msg_buf) {
3365 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3371 ret = i40e_clean_arq_element(hw, &info, &pending);
3373 if (ret != I40E_SUCCESS) {
3374 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3375 "aq_err: %u", hw->aq.asq_last_status);
3378 opcode = rte_le_to_cpu_16(info.desc.opcode);
3381 case i40e_aqc_opc_send_msg_to_pf:
3382 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3383 i40e_pf_host_handle_vf_msg(dev,
3384 rte_le_to_cpu_16(info.desc.retval),
3385 rte_le_to_cpu_32(info.desc.cookie_high),
3386 rte_le_to_cpu_32(info.desc.cookie_low),
3391 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3396 rte_free(info.msg_buf);
3400 * Interrupt handler triggered by NIC for handling
3401 * specific interrupt.
3404 * Pointer to interrupt handle.
3406 * The address of parameter (struct rte_eth_dev *) regsitered before.
3412 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3415 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3416 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417 uint32_t cause, enable;
3419 i40e_pf_disable_irq0(hw);
3421 cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3422 enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3424 /* Shared IRQ case, return */
3425 if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3426 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3427 "no INT event to process", hw->pf_id);
3431 if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3432 PMD_DRV_LOG(INFO, "INT:Link status changed");
3433 i40e_dev_link_update(dev, 0);
3436 if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3437 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3439 if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3440 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3442 if (cause & I40E_PFINT_ICR0_GRST_MASK)
3443 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3445 if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3446 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3448 if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3449 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3451 /* Add processing func to deal with VF reset vent */
3452 if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3453 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3454 i40e_dev_handle_vfr_event(dev);
3456 /* Find admin queue event */
3457 if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3458 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3459 i40e_dev_handle_aq_msg(dev);
3463 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3464 /* Re-enable interrupt from device side */
3465 i40e_pf_enable_irq0(hw);
3466 /* Re-enable interrupt from host side */
3467 rte_intr_enable(&(dev->pci_dev->intr_handle));
3471 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3472 struct i40e_macvlan_filter *filter,
3475 int ele_num, ele_buff_size;
3476 int num, actual_num, i;
3477 int ret = I40E_SUCCESS;
3478 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3479 struct i40e_aqc_add_macvlan_element_data *req_list;
3481 if (filter == NULL || total == 0)
3482 return I40E_ERR_PARAM;
3483 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3484 ele_buff_size = hw->aq.asq_buf_size;
3486 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3487 if (req_list == NULL) {
3488 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3489 return I40E_ERR_NO_MEMORY;
3494 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3495 memset(req_list, 0, ele_buff_size);
3497 for (i = 0; i < actual_num; i++) {
3498 (void)rte_memcpy(req_list[i].mac_addr,
3499 &filter[num + i].macaddr, ETH_ADDR_LEN);
3500 req_list[i].vlan_tag =
3501 rte_cpu_to_le_16(filter[num + i].vlan_id);
3502 req_list[i].flags = rte_cpu_to_le_16(\
3503 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3504 req_list[i].queue_number = 0;
3507 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3509 if (ret != I40E_SUCCESS) {
3510 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3514 } while (num < total);
3522 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3523 struct i40e_macvlan_filter *filter,
3526 int ele_num, ele_buff_size;
3527 int num, actual_num, i;
3528 int ret = I40E_SUCCESS;
3529 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3530 struct i40e_aqc_remove_macvlan_element_data *req_list;
3532 if (filter == NULL || total == 0)
3533 return I40E_ERR_PARAM;
3535 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3536 ele_buff_size = hw->aq.asq_buf_size;
3538 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3539 if (req_list == NULL) {
3540 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3541 return I40E_ERR_NO_MEMORY;
3546 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3547 memset(req_list, 0, ele_buff_size);
3549 for (i = 0; i < actual_num; i++) {
3550 (void)rte_memcpy(req_list[i].mac_addr,
3551 &filter[num + i].macaddr, ETH_ADDR_LEN);
3552 req_list[i].vlan_tag =
3553 rte_cpu_to_le_16(filter[num + i].vlan_id);
3554 req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3557 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3559 if (ret != I40E_SUCCESS) {
3560 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3564 } while (num < total);
3571 /* Find out specific MAC filter */
3572 static struct i40e_mac_filter *
3573 i40e_find_mac_filter(struct i40e_vsi *vsi,
3574 struct ether_addr *macaddr)
3576 struct i40e_mac_filter *f;
3578 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3579 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3587 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3590 uint32_t vid_idx, vid_bit;
3592 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3593 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3595 if (vsi->vfta[vid_idx] & vid_bit)
3602 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3603 uint16_t vlan_id, bool on)
3605 uint32_t vid_idx, vid_bit;
3607 #define UINT32_BIT_MASK 0x1F
3608 #define VALID_VLAN_BIT_MASK 0xFFF
3609 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3610 * element first, then find the bits it belongs to
3612 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3614 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3617 vsi->vfta[vid_idx] |= vid_bit;
3619 vsi->vfta[vid_idx] &= ~vid_bit;
3623 * Find all vlan options for specific mac addr,
3624 * return with actual vlan found.
3627 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3628 struct i40e_macvlan_filter *mv_f,
3629 int num, struct ether_addr *addr)
3635 * Not to use i40e_find_vlan_filter to decrease the loop time,
3636 * although the code looks complex.
3638 if (num < vsi->vlan_num)
3639 return I40E_ERR_PARAM;
3642 for (j = 0; j < I40E_VFTA_SIZE; j++) {
3644 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3645 if (vsi->vfta[j] & (1 << k)) {
3647 PMD_DRV_LOG(ERR, "vlan number "
3649 return I40E_ERR_PARAM;
3651 (void)rte_memcpy(&mv_f[i].macaddr,
3652 addr, ETH_ADDR_LEN);
3654 j * I40E_UINT32_BIT_SIZE + k;
3660 return I40E_SUCCESS;
3664 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3665 struct i40e_macvlan_filter *mv_f,
3670 struct i40e_mac_filter *f;
3672 if (num < vsi->mac_num)
3673 return I40E_ERR_PARAM;
3675 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3677 PMD_DRV_LOG(ERR, "buffer number not match");
3678 return I40E_ERR_PARAM;
3680 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3681 mv_f[i].vlan_id = vlan;
3685 return I40E_SUCCESS;
3689 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3692 struct i40e_mac_filter *f;
3693 struct i40e_macvlan_filter *mv_f;
3694 int ret = I40E_SUCCESS;
3696 if (vsi == NULL || vsi->mac_num == 0)
3697 return I40E_ERR_PARAM;
3699 /* Case that no vlan is set */
3700 if (vsi->vlan_num == 0)
3703 num = vsi->mac_num * vsi->vlan_num;
3705 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3707 PMD_DRV_LOG(ERR, "failed to allocate memory");
3708 return I40E_ERR_NO_MEMORY;
3712 if (vsi->vlan_num == 0) {
3713 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3714 (void)rte_memcpy(&mv_f[i].macaddr,
3715 &f->macaddr, ETH_ADDR_LEN);
3716 mv_f[i].vlan_id = 0;
3720 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3721 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3722 vsi->vlan_num, &f->macaddr);
3723 if (ret != I40E_SUCCESS)
3729 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3737 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3739 struct i40e_macvlan_filter *mv_f;
3741 int ret = I40E_SUCCESS;
3743 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3744 return I40E_ERR_PARAM;
3746 /* If it's already set, just return */
3747 if (i40e_find_vlan_filter(vsi,vlan))
3748 return I40E_SUCCESS;
3750 mac_num = vsi->mac_num;
3753 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3754 return I40E_ERR_PARAM;
3757 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3760 PMD_DRV_LOG(ERR, "failed to allocate memory");
3761 return I40E_ERR_NO_MEMORY;
3764 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3766 if (ret != I40E_SUCCESS)
3769 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3771 if (ret != I40E_SUCCESS)
3774 i40e_set_vlan_filter(vsi, vlan, 1);
3784 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3786 struct i40e_macvlan_filter *mv_f;
3788 int ret = I40E_SUCCESS;
3791 * Vlan 0 is the generic filter for untagged packets
3792 * and can't be removed.
3794 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3795 return I40E_ERR_PARAM;
3797 /* If can't find it, just return */
3798 if (!i40e_find_vlan_filter(vsi, vlan))
3799 return I40E_ERR_PARAM;
3801 mac_num = vsi->mac_num;
3804 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3805 return I40E_ERR_PARAM;
3808 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3811 PMD_DRV_LOG(ERR, "failed to allocate memory");
3812 return I40E_ERR_NO_MEMORY;
3815 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3817 if (ret != I40E_SUCCESS)
3820 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3822 if (ret != I40E_SUCCESS)
3825 /* This is last vlan to remove, replace all mac filter with vlan 0 */
3826 if (vsi->vlan_num == 1) {
3827 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3828 if (ret != I40E_SUCCESS)
3831 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3832 if (ret != I40E_SUCCESS)
3836 i40e_set_vlan_filter(vsi, vlan, 0);
3846 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3848 struct i40e_mac_filter *f;
3849 struct i40e_macvlan_filter *mv_f;
3851 int ret = I40E_SUCCESS;
3853 /* If it's add and we've config it, return */
3854 f = i40e_find_mac_filter(vsi, addr);
3856 return I40E_SUCCESS;
3859 * If vlan_num is 0, that's the first time to add mac,
3860 * set mask for vlan_id 0.
3862 if (vsi->vlan_num == 0) {
3863 i40e_set_vlan_filter(vsi, 0, 1);
3867 vlan_num = vsi->vlan_num;
3869 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3871 PMD_DRV_LOG(ERR, "failed to allocate memory");
3872 return I40E_ERR_NO_MEMORY;
3875 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3876 if (ret != I40E_SUCCESS)
3879 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3880 if (ret != I40E_SUCCESS)
3883 /* Add the mac addr into mac list */
3884 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3886 PMD_DRV_LOG(ERR, "failed to allocate memory");
3887 ret = I40E_ERR_NO_MEMORY;
3890 (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3891 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3902 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3904 struct i40e_mac_filter *f;
3905 struct i40e_macvlan_filter *mv_f;
3907 int ret = I40E_SUCCESS;
3909 /* Can't find it, return an error */
3910 f = i40e_find_mac_filter(vsi, addr);
3912 return I40E_ERR_PARAM;
3914 vlan_num = vsi->vlan_num;
3915 if (vlan_num == 0) {
3916 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3917 return I40E_ERR_PARAM;
3919 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3921 PMD_DRV_LOG(ERR, "failed to allocate memory");
3922 return I40E_ERR_NO_MEMORY;
3925 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3926 if (ret != I40E_SUCCESS)
3929 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3930 if (ret != I40E_SUCCESS)
3933 /* Remove the mac addr into mac list */
3934 TAILQ_REMOVE(&vsi->mac_list, f, next);
3944 /* Configure hash enable flags for RSS */
3946 i40e_config_hena(uint64_t flags)
3953 if (flags & ETH_RSS_NONF_IPV4_UDP)
3954 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3955 if (flags & ETH_RSS_NONF_IPV4_TCP)
3956 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3957 if (flags & ETH_RSS_NONF_IPV4_SCTP)
3958 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3959 if (flags & ETH_RSS_NONF_IPV4_OTHER)
3960 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3961 if (flags & ETH_RSS_FRAG_IPV4)
3962 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3963 if (flags & ETH_RSS_NONF_IPV6_UDP)
3964 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3965 if (flags & ETH_RSS_NONF_IPV6_TCP)
3966 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3967 if (flags & ETH_RSS_NONF_IPV6_SCTP)
3968 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3969 if (flags & ETH_RSS_NONF_IPV6_OTHER)
3970 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3971 if (flags & ETH_RSS_FRAG_IPV6)
3972 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3973 if (flags & ETH_RSS_L2_PAYLOAD)
3974 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3979 /* Parse the hash enable flags */
3981 i40e_parse_hena(uint64_t flags)
3983 uint64_t rss_hf = 0;
3988 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3989 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3990 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3991 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3992 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3993 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3994 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3995 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3996 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3997 rss_hf |= ETH_RSS_FRAG_IPV4;
3998 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3999 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4000 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4001 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4002 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4003 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4004 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4005 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4006 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4007 rss_hf |= ETH_RSS_FRAG_IPV6;
4008 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4009 rss_hf |= ETH_RSS_L2_PAYLOAD;
4016 i40e_pf_disable_rss(struct i40e_pf *pf)
4018 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4021 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4022 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4023 hena &= ~I40E_RSS_HENA_ALL;
4024 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4025 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4026 I40E_WRITE_FLUSH(hw);
4030 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4033 uint8_t hash_key_len;
4038 hash_key = (uint32_t *)(rss_conf->rss_key);
4039 hash_key_len = rss_conf->rss_key_len;
4040 if (hash_key != NULL && hash_key_len >=
4041 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4042 /* Fill in RSS hash key */
4043 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4044 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4047 rss_hf = rss_conf->rss_hf;
4048 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4049 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4050 hena &= ~I40E_RSS_HENA_ALL;
4051 hena |= i40e_config_hena(rss_hf);
4052 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4053 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4054 I40E_WRITE_FLUSH(hw);
4060 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4061 struct rte_eth_rss_conf *rss_conf)
4063 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4067 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4068 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4069 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4070 if (rss_hf != 0) /* Enable RSS */
4072 return 0; /* Nothing to do */
4075 if (rss_hf == 0) /* Disable RSS */
4078 return i40e_hw_rss_hash_set(hw, rss_conf);
4082 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4083 struct rte_eth_rss_conf *rss_conf)
4085 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4090 if (hash_key != NULL) {
4091 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4092 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4093 rss_conf->rss_key_len = i * sizeof(uint32_t);
4095 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4096 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4097 rss_conf->rss_hf = i40e_parse_hena(hena);
4103 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4105 switch (filter_type) {
4106 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4107 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4109 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4110 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4112 case RTE_TUNNEL_FILTER_IMAC_TENID:
4113 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4115 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4116 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4118 case ETH_TUNNEL_FILTER_IMAC:
4119 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4122 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4130 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4131 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4135 uint8_t tun_type = 0;
4137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4138 struct i40e_vsi *vsi = pf->main_vsi;
4139 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4140 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4142 cld_filter = rte_zmalloc("tunnel_filter",
4143 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4146 if (NULL == cld_filter) {
4147 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4150 pfilter = cld_filter;
4152 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4153 sizeof(struct ether_addr));
4154 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4155 sizeof(struct ether_addr));
4157 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4158 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4159 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4160 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4161 &tunnel_filter->ip_addr,
4162 sizeof(pfilter->ipaddr.v4.data));
4164 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4165 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4166 &tunnel_filter->ip_addr,
4167 sizeof(pfilter->ipaddr.v6.data));
4170 /* check tunneled type */
4171 switch (tunnel_filter->tunnel_type) {
4172 case RTE_TUNNEL_TYPE_VXLAN:
4173 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4176 /* Other tunnel types is not supported. */
4177 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4178 rte_free(cld_filter);
4182 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4185 rte_free(cld_filter);
4189 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4190 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4191 pfilter->tenant_id = tunnel_filter->tenant_id;
4192 pfilter->queue_number = tunnel_filter->queue_id;
4195 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4197 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4200 rte_free(cld_filter);
4205 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4209 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4210 if (pf->vxlan_ports[i] == port)
4218 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4222 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4224 idx = i40e_get_vxlan_port_idx(pf, port);
4226 /* Check if port already exists */
4228 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4232 /* Now check if there is space to add the new port */
4233 idx = i40e_get_vxlan_port_idx(pf, 0);
4235 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4236 "not adding port %d", port);
4240 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4243 PMD_DRV_LOG(ERR, "Failed to add VxLAN UDP port %d", port);
4247 PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4248 port, filter_index);
4250 /* New port: add it and mark its index in the bitmap */
4251 pf->vxlan_ports[idx] = port;
4252 pf->vxlan_bitmap |= (1 << idx);
4254 if (!(pf->flags & I40E_FLAG_VXLAN))
4255 pf->flags |= I40E_FLAG_VXLAN;
4261 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4264 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4266 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4267 PMD_DRV_LOG(ERR, "VxLAN UDP port was not configured.");
4271 idx = i40e_get_vxlan_port_idx(pf, port);
4274 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4278 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4279 PMD_DRV_LOG(ERR, "Failed to delete VxLAN UDP port %d", port);
4283 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4286 pf->vxlan_ports[idx] = 0;
4287 pf->vxlan_bitmap &= ~(1 << idx);
4289 if (!pf->vxlan_bitmap)
4290 pf->flags &= ~I40E_FLAG_VXLAN;
4295 /* Add UDP tunneling port */
4297 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4298 struct rte_eth_udp_tunnel *udp_tunnel)
4301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4303 if (udp_tunnel == NULL)
4306 switch (udp_tunnel->prot_type) {
4307 case RTE_TUNNEL_TYPE_VXLAN:
4308 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4311 case RTE_TUNNEL_TYPE_GENEVE:
4312 case RTE_TUNNEL_TYPE_TEREDO:
4313 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4318 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4326 /* Remove UDP tunneling port */
4328 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4329 struct rte_eth_udp_tunnel *udp_tunnel)
4332 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4334 if (udp_tunnel == NULL)
4337 switch (udp_tunnel->prot_type) {
4338 case RTE_TUNNEL_TYPE_VXLAN:
4339 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4341 case RTE_TUNNEL_TYPE_GENEVE:
4342 case RTE_TUNNEL_TYPE_TEREDO:
4343 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4347 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4357 i40e_pf_config_rss(struct i40e_pf *pf)
4359 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4360 struct rte_eth_rss_conf rss_conf;
4361 uint32_t i, lut = 0;
4362 uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4364 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4367 lut = (lut << 8) | (j & ((0x1 <<
4368 hw->func_caps.rss_table_entry_width) - 1));
4370 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4373 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4374 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4375 i40e_pf_disable_rss(pf);
4378 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4379 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4380 /* Calculate the default hash key */
4381 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4382 rss_key_default[i] = (uint32_t)rte_rand();
4383 rss_conf.rss_key = (uint8_t *)rss_key_default;
4384 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4388 return i40e_hw_rss_hash_set(hw, &rss_conf);
4392 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4393 struct rte_eth_tunnel_filter_conf *filter)
4395 if (pf == NULL || filter == NULL) {
4396 PMD_DRV_LOG(ERR, "Invalid parameter");
4400 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4401 PMD_DRV_LOG(ERR, "Invalid queue ID");
4405 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4406 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4410 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4411 (is_zero_ether_addr(filter->outer_mac))) {
4412 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4416 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4417 (is_zero_ether_addr(filter->inner_mac))) {
4418 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4426 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4429 struct rte_eth_tunnel_filter_conf *filter;
4430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4431 int ret = I40E_SUCCESS;
4433 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4435 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4436 return I40E_ERR_PARAM;
4438 switch (filter_op) {
4439 case RTE_ETH_FILTER_NOP:
4440 if (!(pf->flags & I40E_FLAG_VXLAN))
4441 ret = I40E_NOT_SUPPORTED;
4442 case RTE_ETH_FILTER_ADD:
4443 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4445 case RTE_ETH_FILTER_DELETE:
4446 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4449 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4450 ret = I40E_ERR_PARAM;
4458 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4460 if (!pf->dev_data->sriov.active) {
4461 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4463 i40e_pf_config_rss(pf);
4466 i40e_pf_disable_rss(pf);
4475 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4476 enum rte_filter_type filter_type,
4477 enum rte_filter_op filter_op,
4485 switch (filter_type) {
4486 case RTE_ETH_FILTER_TUNNEL:
4487 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
4490 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",