lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 /* Maximun number of MAC addresses */
  62 #define I40E_NUM_MACADDR_MAX       64
  63 #define I40E_CLEAR_PXE_WAIT_MS     200
  64
  65 /* Maximun number of capability elements */
  66 #define I40E_MAX_CAP_ELE_NUM       128
  67
  68 /* Wait count and inteval */
  69 #define I40E_CHK_Q_ENA_COUNT       1000
  70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  71
  72 /* Maximun number of VSI */
  73 #define I40E_MAX_NUM_VSIS          (384UL)
  74
  75 /* Bit shift and mask */
  76 #define I40E_16_BIT_SHIFT 16
  77 #define I40E_16_BIT_MASK  0xFFFF
  78 #define I40E_32_BIT_SHIFT 32
  79 #define I40E_32_BIT_MASK  0xFFFFFFFF
  80 #define I40E_48_BIT_SHIFT 48
  81 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  82
  83 /* Default queue interrupt throttling time in microseconds*/
  84 #define I40E_ITR_INDEX_DEFAULT          0
  85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  86 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  87
  88 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  89
  90 #define I40E_RSS_OFFLOAD_ALL ( \
  91         ETH_RSS_NONF_IPV4_UDP | \
  92         ETH_RSS_NONF_IPV4_TCP | \
  93         ETH_RSS_NONF_IPV4_SCTP | \
  94         ETH_RSS_NONF_IPV4_OTHER | \
  95         ETH_RSS_FRAG_IPV4 | \
  96         ETH_RSS_NONF_IPV6_UDP | \
  97         ETH_RSS_NONF_IPV6_TCP | \
  98         ETH_RSS_NONF_IPV6_SCTP | \
  99         ETH_RSS_NONF_IPV6_OTHER | \
 100         ETH_RSS_FRAG_IPV6 | \
 101         ETH_RSS_L2_PAYLOAD)
 102
 103 /* All bits of RSS hash enable */
 104 #define I40E_RSS_HENA_ALL ( \
 105         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 106         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 107         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 108         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 109         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 110         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 111         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 112         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 113         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 114         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 115         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 116         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 117         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 118         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 119
 120 static int eth_i40e_dev_init(\
 121                         __attribute__((unused)) struct eth_driver *eth_drv,
 122                         struct rte_eth_dev *eth_dev);
 123 static int i40e_dev_configure(struct rte_eth_dev *dev);
 124 static int i40e_dev_start(struct rte_eth_dev *dev);
 125 static void i40e_dev_stop(struct rte_eth_dev *dev);
 126 static void i40e_dev_close(struct rte_eth_dev *dev);
 127 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 128 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 129 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 130 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 131 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 132 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 133 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 134                                struct rte_eth_stats *stats);
 135 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 136 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 137                                             uint16_t queue_id,
 138                                             uint8_t stat_idx,
 139                                             uint8_t is_rx);
 140 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 141                               struct rte_eth_dev_info *dev_info);
 142 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 143                                 uint16_t vlan_id,
 144                                 int on);
 145 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 146 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 147 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 148                                       uint16_t queue,
 149                                       int on);
 150 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 151 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 152 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 153 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 154                               struct rte_eth_fc_conf *fc_conf);
 155 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 156                                        struct rte_eth_pfc_conf *pfc_conf);
 157 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 158                           struct ether_addr *mac_addr,
 159                           uint32_t index,
 160                           uint32_t pool);
 161 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 162 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 163                                     struct rte_eth_rss_reta *reta_conf);
 164 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 165                                    struct rte_eth_rss_reta *reta_conf);
 166
 167 static int i40e_get_cap(struct i40e_hw *hw);
 168 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 169 static int i40e_pf_setup(struct i40e_pf *pf);
 170 static int i40e_vsi_init(struct i40e_vsi *vsi);
 171 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 172                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 173 static void i40e_stat_update_48(struct i40e_hw *hw,
 174                                uint32_t hireg,
 175                                uint32_t loreg,
 176                                bool offset_loaded,
 177                                uint64_t *offset,
 178                                uint64_t *stat);
 179 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 180 static void i40e_dev_interrupt_handler(
 181                 __rte_unused struct rte_intr_handle *handle, void *param);
 182 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 183                                 uint32_t base, uint32_t num);
 184 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 185 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 186                         uint32_t base);
 187 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 188                         uint16_t num);
 189 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 190 static int i40e_veb_release(struct i40e_veb *veb);
 191 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 192                                                 struct i40e_vsi *vsi);
 193 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 194 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 195 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 196                                              struct i40e_macvlan_filter *mv_f,
 197                                              int num,
 198                                              struct ether_addr *addr);
 199 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 200                                              struct i40e_macvlan_filter *mv_f,
 201                                              int num,
 202                                              uint16_t vlan);
 203 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 204 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 205                                     struct rte_eth_rss_conf *rss_conf);
 206 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 207                                       struct rte_eth_rss_conf *rss_conf);
 208
 209 /* Default hash key buffer for RSS */
 210 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 211
 212 static struct rte_pci_id pci_id_i40e_map[] = {
 213 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 214 #include "rte_pci_dev_ids.h"
 215 { .vendor_id = 0, /* sentinel */ },
 216 };
 217
 218 static struct eth_dev_ops i40e_eth_dev_ops = {
 219         .dev_configure                = i40e_dev_configure,
 220         .dev_start                    = i40e_dev_start,
 221         .dev_stop                     = i40e_dev_stop,
 222         .dev_close                    = i40e_dev_close,
 223         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 224         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 225         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 226         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 227         .dev_set_link_up              = i40e_dev_set_link_up,
 228         .dev_set_link_down            = i40e_dev_set_link_down,
 229         .link_update                  = i40e_dev_link_update,
 230         .stats_get                    = i40e_dev_stats_get,
 231         .stats_reset                  = i40e_dev_stats_reset,
 232         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 233         .dev_infos_get                = i40e_dev_info_get,
 234         .vlan_filter_set              = i40e_vlan_filter_set,
 235         .vlan_tpid_set                = i40e_vlan_tpid_set,
 236         .vlan_offload_set             = i40e_vlan_offload_set,
 237         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 238         .vlan_pvid_set                = i40e_vlan_pvid_set,
 239         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 240         .rx_queue_release             = i40e_dev_rx_queue_release,
 241         .rx_queue_count               = i40e_dev_rx_queue_count,
 242         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 243         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 244         .tx_queue_release             = i40e_dev_tx_queue_release,
 245         .dev_led_on                   = i40e_dev_led_on,
 246         .dev_led_off                  = i40e_dev_led_off,
 247         .flow_ctrl_set                = i40e_flow_ctrl_set,
 248         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 249         .mac_addr_add                 = i40e_macaddr_add,
 250         .mac_addr_remove              = i40e_macaddr_remove,
 251         .reta_update                  = i40e_dev_rss_reta_update,
 252         .reta_query                   = i40e_dev_rss_reta_query,
 253         .rss_hash_update              = i40e_dev_rss_hash_update,
 254         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 255 };
 256
 257 static struct eth_driver rte_i40e_pmd = {
 258         {
 259                 .name = "rte_i40e_pmd",
 260                 .id_table = pci_id_i40e_map,
 261                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 262         },
 263         .eth_dev_init = eth_i40e_dev_init,
 264         .dev_private_size = sizeof(struct i40e_adapter),
 265 };
 266
 267 static inline int
 268 i40e_prev_power_of_2(int n)
 269 {
 270        int p = n;
 271
 272        --p;
 273        p |= p >> 1;
 274        p |= p >> 2;
 275        p |= p >> 4;
 276        p |= p >> 8;
 277        p |= p >> 16;
 278        if (p == (n - 1))
 279                return n;
 280        p >>= 1;
 281
 282        return ++p;
 283 }
 284
 285 static inline int
 286 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 287                                      struct rte_eth_link *link)
 288 {
 289         struct rte_eth_link *dst = link;
 290         struct rte_eth_link *src = &(dev->data->dev_link);
 291
 292         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 293                                         *(uint64_t *)src) == 0)
 294                 return -1;
 295
 296         return 0;
 297 }
 298
 299 static inline int
 300 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 301                                       struct rte_eth_link *link)
 302 {
 303         struct rte_eth_link *dst = &(dev->data->dev_link);
 304         struct rte_eth_link *src = link;
 305
 306         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 307                                         *(uint64_t *)src) == 0)
 308                 return -1;
 309
 310         return 0;
 311 }
 312
 313 /*
 314  * Driver initialization routine.
 315  * Invoked once at EAL init time.
 316  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 317  */
 318 static int
 319 rte_i40e_pmd_init(const char *name __rte_unused,
 320                   const char *params __rte_unused)
 321 {
 322         PMD_INIT_FUNC_TRACE();
 323         rte_eth_driver_register(&rte_i40e_pmd);
 324
 325         return 0;
 326 }
 327
 328 static struct rte_driver rte_i40e_driver = {
 329         .type = PMD_PDEV,
 330         .init = rte_i40e_pmd_init,
 331 };
 332
 333 PMD_REGISTER_DRIVER(rte_i40e_driver);
 334
 335 static int
 336 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 337                   struct rte_eth_dev *dev)
 338 {
 339         struct rte_pci_device *pci_dev;
 340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 342         struct i40e_vsi *vsi;
 343         int ret;
 344         uint32_t len;
 345         uint8_t aq_fail = 0;
 346
 347         PMD_INIT_FUNC_TRACE();
 348
 349         dev->dev_ops = &i40e_eth_dev_ops;
 350         dev->rx_pkt_burst = i40e_recv_pkts;
 351         dev->tx_pkt_burst = i40e_xmit_pkts;
 352
 353         /* for secondary processes, we don't initialise any further as primary
 354          * has already done this work. Only check we don't need a different
 355          * RX function */
 356         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 357                 if (dev->data->scattered_rx)
 358                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 359                 return 0;
 360         }
 361         pci_dev = dev->pci_dev;
 362         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 363         pf->adapter->eth_dev = dev;
 364         pf->dev_data = dev->data;
 365
 366         hw->back = I40E_PF_TO_ADAPTER(pf);
 367         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 368         if (!hw->hw_addr) {
 369                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 370                                         "as address is NULL\n");
 371                 return -ENODEV;
 372         }
 373
 374         hw->vendor_id = pci_dev->id.vendor_id;
 375         hw->device_id = pci_dev->id.device_id;
 376         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 377         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 378         hw->bus.device = pci_dev->addr.devid;
 379         hw->bus.func = pci_dev->addr.function;
 380
 381         /* Make sure all is clean before doing PF reset */
 382         i40e_clear_hw(hw);
 383
 384         /* Reset here to make sure all is clean for each PF */
 385         ret = i40e_pf_reset(hw);
 386         if (ret) {
 387                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 388                 return ret;
 389         }
 390
 391         /* Initialize the shared code (base driver) */
 392         ret = i40e_init_shared_code(hw);
 393         if (ret) {
 394                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 395                 return ret;
 396         }
 397
 398         /* Initialize the parameters for adminq */
 399         i40e_init_adminq_parameter(hw);
 400         ret = i40e_init_adminq(hw);
 401         if (ret != I40E_SUCCESS) {
 402                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 403                 return -EIO;
 404         }
 405         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
 406                         "%02d.%02d.%02d eetrack %04x\n",
 407                         hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 408                         hw->aq.api_maj_ver, hw->aq.api_min_ver,
 409                         ((hw->nvm.version >> 12) & 0xf),
 410                         ((hw->nvm.version >> 4) & 0xff),
 411                         (hw->nvm.version & 0xf), hw->nvm.eetrack);
 412
 413         /* Disable LLDP */
 414         ret = i40e_aq_stop_lldp(hw, true, NULL);
 415         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 416                 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
 417
 418         /* Clear PXE mode */
 419         i40e_clear_pxe_mode(hw);
 420
 421         /* Get hw capabilities */
 422         ret = i40e_get_cap(hw);
 423         if (ret != I40E_SUCCESS) {
 424                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 425                 goto err_get_capabilities;
 426         }
 427
 428         /* Initialize parameters for PF */
 429         ret = i40e_pf_parameter_init(dev);
 430         if (ret != 0) {
 431                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 432                 goto err_parameter_init;
 433         }
 434
 435         /* Initialize the queue management */
 436         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 437         if (ret < 0) {
 438                 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
 439                 goto err_qp_pool_init;
 440         }
 441         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 442                                 hw->func_caps.num_msix_vectors - 1);
 443         if (ret < 0) {
 444                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
 445                 goto err_msix_pool_init;
 446         }
 447
 448         /* Initialize lan hmc */
 449         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 450                                 hw->func_caps.num_rx_qp, 0, 0);
 451         if (ret != I40E_SUCCESS) {
 452                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 453                 goto err_init_lan_hmc;
 454         }
 455
 456         /* Configure lan hmc */
 457         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 458         if (ret != I40E_SUCCESS) {
 459                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 460                 goto err_configure_lan_hmc;
 461         }
 462
 463         /* Get and check the mac address */
 464         i40e_get_mac_addr(hw, hw->mac.addr);
 465         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 466                 PMD_INIT_LOG(ERR, "mac address is not valid");
 467                 ret = -EIO;
 468                 goto err_get_mac_addr;
 469         }
 470         /* Copy the permanent MAC address */
 471         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 472                         (struct ether_addr *) hw->mac.perm_addr);
 473
 474         /* Disable flow control */
 475         hw->fc.requested_mode = I40E_FC_NONE;
 476         i40e_set_fc(hw, &aq_fail, TRUE);
 477
 478         /* PF setup, which includes VSI setup */
 479         ret = i40e_pf_setup(pf);
 480         if (ret) {
 481                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 482                 goto err_setup_pf_switch;
 483         }
 484
 485         vsi = pf->main_vsi;
 486
 487         /* Disable double vlan by default */
 488         i40e_vsi_config_double_vlan(vsi, FALSE);
 489
 490         if (!vsi->max_macaddrs)
 491                 len = ETHER_ADDR_LEN;
 492         else
 493                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 494
 495         /* Should be after VSI initialized */
 496         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 497         if (!dev->data->mac_addrs) {
 498                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 499                                         "for storing mac address");
 500                 goto err_get_mac_addr;
 501         }
 502         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 503                                         &dev->data->mac_addrs[0]);
 504
 505         /* initialize pf host driver to setup SRIOV resource if applicable */
 506         i40e_pf_host_init(dev);
 507
 508         /* register callback func to eal lib */
 509         rte_intr_callback_register(&(pci_dev->intr_handle),
 510                 i40e_dev_interrupt_handler, (void *)dev);
 511
 512         /* configure and enable device interrupt */
 513         i40e_pf_config_irq0(hw);
 514         i40e_pf_enable_irq0(hw);
 515
 516         /* enable uio intr after callback register */
 517         rte_intr_enable(&(pci_dev->intr_handle));
 518
 519         return 0;
 520
 521 err_setup_pf_switch:
 522         rte_free(pf->main_vsi);
 523 err_get_mac_addr:
 524 err_configure_lan_hmc:
 525         (void)i40e_shutdown_lan_hmc(hw);
 526 err_init_lan_hmc:
 527         i40e_res_pool_destroy(&pf->msix_pool);
 528 err_msix_pool_init:
 529         i40e_res_pool_destroy(&pf->qp_pool);
 530 err_qp_pool_init:
 531 err_parameter_init:
 532 err_get_capabilities:
 533         (void)i40e_shutdown_adminq(hw);
 534
 535         return ret;
 536 }
 537
 538 static int
 539 i40e_dev_configure(struct rte_eth_dev *dev)
 540 {
 541         return i40e_dev_init_vlan(dev);
 542 }
 543
 544 void
 545 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 546 {
 547         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 548         uint16_t msix_vect = vsi->msix_intr;
 549         uint16_t i;
 550
 551         for (i = 0; i < vsi->nb_qps; i++) {
 552                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 553                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 554                 rte_wmb();
 555         }
 556
 557         if (vsi->type != I40E_VSI_SRIOV) {
 558                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 559                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 560                                 msix_vect - 1), 0);
 561         } else {
 562                 uint32_t reg;
 563                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 564                         vsi->user_param + (msix_vect - 1);
 565
 566                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 567         }
 568         I40E_WRITE_FLUSH(hw);
 569 }
 570
 571 static inline uint16_t
 572 i40e_calc_itr_interval(int16_t interval)
 573 {
 574         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 575                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 576
 577         /* Convert to hardware count, as writing each 1 represents 2 us */
 578         return (interval/2);
 579 }
 580
 581 void
 582 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 583 {
 584         uint32_t val;
 585         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 586         uint16_t msix_vect = vsi->msix_intr;
 587         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 588         int i;
 589
 590         for (i = 0; i < vsi->nb_qps; i++)
 591                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 592
 593         /* Bind all RX queues to allocated MSIX interrupt */
 594         for (i = 0; i < vsi->nb_qps; i++) {
 595                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 596                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 597                         ((vsi->base_queue + i + 1) <<
 598                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 599                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 600                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 601
 602                 if (i == vsi->nb_qps - 1)
 603                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 604                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 605         }
 606
 607         /* Write first RX queue to Link list register as the head element */
 608         if (vsi->type != I40E_VSI_SRIOV) {
 609                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 610                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 611                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 612
 613                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 614                                 msix_vect - 1), interval);
 615
 616                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 617                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 618                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 619         }
 620         else {
 621                 uint32_t reg;
 622                 /* num_msix_vectors_vf needs to minus irq0 */
 623                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 624                         vsi->user_param + (msix_vect - 1);
 625
 626                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 627                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 628                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 629         }
 630
 631         I40E_WRITE_FLUSH(hw);
 632 }
 633
 634 static void
 635 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 636 {
 637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 638         uint16_t interval = i40e_calc_itr_interval(\
 639                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 640
 641         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 642                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 643                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 644                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 645                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 646 }
 647
 648 static void
 649 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 650 {
 651         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 652
 653         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 654 }
 655
 656 static inline uint8_t
 657 i40e_parse_link_speed(uint16_t eth_link_speed)
 658 {
 659         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 660
 661         switch (eth_link_speed) {
 662         case ETH_LINK_SPEED_40G:
 663                 link_speed = I40E_LINK_SPEED_40GB;
 664                 break;
 665         case ETH_LINK_SPEED_20G:
 666                 link_speed = I40E_LINK_SPEED_20GB;
 667                 break;
 668         case ETH_LINK_SPEED_10G:
 669                 link_speed = I40E_LINK_SPEED_10GB;
 670                 break;
 671         case ETH_LINK_SPEED_1000:
 672                 link_speed = I40E_LINK_SPEED_1GB;
 673                 break;
 674         case ETH_LINK_SPEED_100:
 675                 link_speed = I40E_LINK_SPEED_100MB;
 676                 break;
 677         }
 678
 679         return link_speed;
 680 }
 681
 682 static int
 683 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 684 {
 685         enum i40e_status_code status;
 686         struct i40e_aq_get_phy_abilities_resp phy_ab;
 687         struct i40e_aq_set_phy_config phy_conf;
 688         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 689                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 690                         I40E_AQ_PHY_FLAG_LOW_POWER;
 691         const uint8_t advt = I40E_LINK_SPEED_40GB |
 692                         I40E_LINK_SPEED_10GB |
 693                         I40E_LINK_SPEED_1GB |
 694                         I40E_LINK_SPEED_100MB;
 695         int ret = -ENOTSUP;
 696
 697         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 698                                               NULL);
 699         if (status)
 700                 return ret;
 701
 702         memset(&phy_conf, 0, sizeof(phy_conf));
 703
 704         /* bits 0-2 use the values from get_phy_abilities_resp */
 705         abilities &= ~mask;
 706         abilities |= phy_ab.abilities & mask;
 707
 708         /* update ablities and speed */
 709         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 710                 phy_conf.link_speed = advt;
 711         else
 712                 phy_conf.link_speed = force_speed;
 713
 714         phy_conf.abilities = abilities;
 715
 716         /* use get_phy_abilities_resp value for the rest */
 717         phy_conf.phy_type = phy_ab.phy_type;
 718         phy_conf.eee_capability = phy_ab.eee_capability;
 719         phy_conf.eeer = phy_ab.eeer_val;
 720         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 721
 722         PMD_DRV_LOG(DEBUG, "\n\tCurrent: abilities %x, link_speed %x\n"
 723                     "\tConfig:  abilities %x, link_speed %x",
 724                     phy_ab.abilities, phy_ab.link_speed,
 725                     phy_conf.abilities, phy_conf.link_speed);
 726
 727         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 728         if (status)
 729                 return ret;
 730
 731         return I40E_SUCCESS;
 732 }
 733
 734 static int
 735 i40e_apply_link_speed(struct rte_eth_dev *dev)
 736 {
 737         uint8_t speed;
 738         uint8_t abilities = 0;
 739         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 740         struct rte_eth_conf *conf = &dev->data->dev_conf;
 741
 742         speed = i40e_parse_link_speed(conf->link_speed);
 743         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 744         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 745                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 746         else
 747                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 748
 749         return i40e_phy_conf_link(hw, abilities, speed);
 750 }
 751
 752 static int
 753 i40e_dev_start(struct rte_eth_dev *dev)
 754 {
 755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 757         struct i40e_vsi *vsi = pf->main_vsi;
 758         int ret;
 759
 760         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 761                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 762                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
 763                                 dev->data->dev_conf.link_duplex,
 764                                 dev->data->port_id);
 765                 return -EINVAL;
 766         }
 767
 768         /* Initialize VSI */
 769         ret = i40e_vsi_init(vsi);
 770         if (ret != I40E_SUCCESS) {
 771                 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
 772                 goto err_up;
 773         }
 774
 775         /* Map queues with MSIX interrupt */
 776         i40e_vsi_queues_bind_intr(vsi);
 777         i40e_vsi_enable_queues_intr(vsi);
 778
 779         /* Enable all queues which have been configured */
 780         ret = i40e_vsi_switch_queues(vsi, TRUE);
 781         if (ret != I40E_SUCCESS) {
 782                 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
 783                 goto err_up;
 784         }
 785
 786         /* Enable receiving broadcast packets */
 787         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 788                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 789                 if (ret != I40E_SUCCESS)
 790                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
 791         }
 792
 793         /* Apply link configure */
 794         ret = i40e_apply_link_speed(dev);
 795         if (I40E_SUCCESS != ret) {
 796                 PMD_DRV_LOG(ERR, "Fail to apply link setting\n");
 797                 goto err_up;
 798         }
 799
 800         return I40E_SUCCESS;
 801
 802 err_up:
 803         i40e_vsi_switch_queues(vsi, FALSE);
 804         i40e_dev_clear_queues(dev);
 805
 806         return ret;
 807 }
 808
 809 static void
 810 i40e_dev_stop(struct rte_eth_dev *dev)
 811 {
 812         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 813         struct i40e_vsi *vsi = pf->main_vsi;
 814
 815         /* Disable all queues */
 816         i40e_vsi_switch_queues(vsi, FALSE);
 817
 818         /* Clear all queues and release memory */
 819         i40e_dev_clear_queues(dev);
 820
 821         /* Set link down */
 822         i40e_dev_set_link_down(dev);
 823
 824         /* un-map queues with interrupt registers */
 825         i40e_vsi_disable_queues_intr(vsi);
 826         i40e_vsi_queues_unbind_intr(vsi);
 827 }
 828
 829 static void
 830 i40e_dev_close(struct rte_eth_dev *dev)
 831 {
 832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834         uint32_t reg;
 835
 836         PMD_INIT_FUNC_TRACE();
 837
 838         i40e_dev_stop(dev);
 839
 840         /* Disable interrupt */
 841         i40e_pf_disable_irq0(hw);
 842         rte_intr_disable(&(dev->pci_dev->intr_handle));
 843
 844         /* shutdown and destroy the HMC */
 845         i40e_shutdown_lan_hmc(hw);
 846
 847         /* release all the existing VSIs and VEBs */
 848         i40e_vsi_release(pf->main_vsi);
 849
 850         /* shutdown the adminq */
 851         i40e_aq_queue_shutdown(hw, true);
 852         i40e_shutdown_adminq(hw);
 853
 854         i40e_res_pool_destroy(&pf->qp_pool);
 855         i40e_res_pool_destroy(&pf->msix_pool);
 856
 857         /* force a PF reset to clean anything leftover */
 858         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 859         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 860                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 861         I40E_WRITE_FLUSH(hw);
 862 }
 863
 864 static void
 865 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 866 {
 867         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 869         struct i40e_vsi *vsi = pf->main_vsi;
 870         int status;
 871
 872         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 873                                                         true, NULL);
 874         if (status != I40E_SUCCESS)
 875                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
 876
 877         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 878                                                         TRUE, NULL);
 879         if (status != I40E_SUCCESS)
 880                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
 881
 882 }
 883
 884 static void
 885 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 886 {
 887         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 889         struct i40e_vsi *vsi = pf->main_vsi;
 890         int status;
 891
 892         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 893                                                         false, NULL);
 894         if (status != I40E_SUCCESS)
 895                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
 896
 897         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 898                                                         false, NULL);
 899         if (status != I40E_SUCCESS)
 900                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
 901 }
 902
 903 static void
 904 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 908         struct i40e_vsi *vsi = pf->main_vsi;
 909         int ret;
 910
 911         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 912         if (ret != I40E_SUCCESS)
 913                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
 914 }
 915
 916 static void
 917 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 918 {
 919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 921         struct i40e_vsi *vsi = pf->main_vsi;
 922         int ret;
 923
 924         if (dev->data->promiscuous == 1)
 925                 return; /* must remain in all_multicast mode */
 926
 927         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 928                                 vsi->seid, FALSE, NULL);
 929         if (ret != I40E_SUCCESS)
 930                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
 931 }
 932
 933 /*
 934  * Set device link up.
 935  */
 936 static int
 937 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 938 {
 939         /* re-apply link speed setting */
 940         return i40e_apply_link_speed(dev);
 941 }
 942
 943 /*
 944  * Set device link down.
 945  */
 946 static int
 947 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 948 {
 949         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 950         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 952
 953         return i40e_phy_conf_link(hw, abilities, speed);
 954 }
 955
 956 int
 957 i40e_dev_link_update(struct rte_eth_dev *dev,
 958                      __rte_unused int wait_to_complete)
 959 {
 960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         struct i40e_link_status link_status;
 962         struct rte_eth_link link, old;
 963         int status;
 964
 965         memset(&link, 0, sizeof(link));
 966         memset(&old, 0, sizeof(old));
 967         memset(&link_status, 0, sizeof(link_status));
 968         rte_i40e_dev_atomic_read_link_status(dev, &old);
 969
 970         /* Get link status information from hardware */
 971         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 972         if (status != I40E_SUCCESS) {
 973                 link.link_speed = ETH_LINK_SPEED_100;
 974                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 975                 PMD_DRV_LOG(ERR, "Failed to get link info\n");
 976                 goto out;
 977         }
 978
 979         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 980
 981         if (!link.link_status)
 982                 goto out;
 983
 984         /* i40e uses full duplex only */
 985         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 986
 987         /* Parse the link status */
 988         switch (link_status.link_speed) {
 989         case I40E_LINK_SPEED_100MB:
 990                 link.link_speed = ETH_LINK_SPEED_100;
 991                 break;
 992         case I40E_LINK_SPEED_1GB:
 993                 link.link_speed = ETH_LINK_SPEED_1000;
 994                 break;
 995         case I40E_LINK_SPEED_10GB:
 996                 link.link_speed = ETH_LINK_SPEED_10G;
 997                 break;
 998         case I40E_LINK_SPEED_20GB:
 999                 link.link_speed = ETH_LINK_SPEED_20G;
1000                 break;
1001         case I40E_LINK_SPEED_40GB:
1002                 link.link_speed = ETH_LINK_SPEED_40G;
1003                 break;
1004         default:
1005                 link.link_speed = ETH_LINK_SPEED_100;
1006                 break;
1007         }
1008
1009 out:
1010         rte_i40e_dev_atomic_write_link_status(dev, &link);
1011         if (link.link_status == old.link_status)
1012                 return -1;
1013
1014         return 0;
1015 }
1016
1017 /* Get all the statistics of a VSI */
1018 void
1019 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1020 {
1021         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1022         struct i40e_eth_stats *nes = &vsi->eth_stats;
1023         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1024         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1025
1026         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1027                             vsi->offset_loaded, &oes->rx_bytes,
1028                             &nes->rx_bytes);
1029         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1030                             vsi->offset_loaded, &oes->rx_unicast,
1031                             &nes->rx_unicast);
1032         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1033                             vsi->offset_loaded, &oes->rx_multicast,
1034                             &nes->rx_multicast);
1035         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1036                             vsi->offset_loaded, &oes->rx_broadcast,
1037                             &nes->rx_broadcast);
1038         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1039                             &oes->rx_discards, &nes->rx_discards);
1040         /* GLV_REPC not supported */
1041         /* GLV_RMPC not supported */
1042         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1043                             &oes->rx_unknown_protocol,
1044                             &nes->rx_unknown_protocol);
1045         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1046                             vsi->offset_loaded, &oes->tx_bytes,
1047                             &nes->tx_bytes);
1048         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1049                             vsi->offset_loaded, &oes->tx_unicast,
1050                             &nes->tx_unicast);
1051         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1052                             vsi->offset_loaded, &oes->tx_multicast,
1053                             &nes->tx_multicast);
1054         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1055                             vsi->offset_loaded,  &oes->tx_broadcast,
1056                             &nes->tx_broadcast);
1057         /* GLV_TDPC not supported */
1058         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1059                             &oes->tx_errors, &nes->tx_errors);
1060         vsi->offset_loaded = true;
1061
1062 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1063         printf("***************** VSI[%u] stats start *******************\n",
1064                                                                 vsi->vsi_id);
1065         printf("rx_bytes:            %lu\n", nes->rx_bytes);
1066         printf("rx_unicast:          %lu\n", nes->rx_unicast);
1067         printf("rx_multicast:        %lu\n", nes->rx_multicast);
1068         printf("rx_broadcast:        %lu\n", nes->rx_broadcast);
1069         printf("rx_discards:         %lu\n", nes->rx_discards);
1070         printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
1071         printf("tx_bytes:            %lu\n", nes->tx_bytes);
1072         printf("tx_unicast:          %lu\n", nes->tx_unicast);
1073         printf("tx_multicast:        %lu\n", nes->tx_multicast);
1074         printf("tx_broadcast:        %lu\n", nes->tx_broadcast);
1075         printf("tx_discards:         %lu\n", nes->tx_discards);
1076         printf("tx_errors:           %lu\n", nes->tx_errors);
1077         printf("***************** VSI[%u] stats end *******************\n",
1078                                                                 vsi->vsi_id);
1079 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1080 }
1081
1082 /* Get all statistics of a port */
1083 static void
1084 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1085 {
1086         uint32_t i;
1087         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1090         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1091
1092         /* Get statistics of struct i40e_eth_stats */
1093         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1094                             I40E_GLPRT_GORCL(hw->port),
1095                             pf->offset_loaded, &os->eth.rx_bytes,
1096                             &ns->eth.rx_bytes);
1097         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1098                             I40E_GLPRT_UPRCL(hw->port),
1099                             pf->offset_loaded, &os->eth.rx_unicast,
1100                             &ns->eth.rx_unicast);
1101         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1102                             I40E_GLPRT_MPRCL(hw->port),
1103                             pf->offset_loaded, &os->eth.rx_multicast,
1104                             &ns->eth.rx_multicast);
1105         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1106                             I40E_GLPRT_BPRCL(hw->port),
1107                             pf->offset_loaded, &os->eth.rx_broadcast,
1108                             &ns->eth.rx_broadcast);
1109         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1110                             pf->offset_loaded, &os->eth.rx_discards,
1111                             &ns->eth.rx_discards);
1112         /* GLPRT_REPC not supported */
1113         /* GLPRT_RMPC not supported */
1114         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1115                             pf->offset_loaded,
1116                             &os->eth.rx_unknown_protocol,
1117                             &ns->eth.rx_unknown_protocol);
1118         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1119                             I40E_GLPRT_GOTCL(hw->port),
1120                             pf->offset_loaded, &os->eth.tx_bytes,
1121                             &ns->eth.tx_bytes);
1122         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1123                             I40E_GLPRT_UPTCL(hw->port),
1124                             pf->offset_loaded, &os->eth.tx_unicast,
1125                             &ns->eth.tx_unicast);
1126         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1127                             I40E_GLPRT_MPTCL(hw->port),
1128                             pf->offset_loaded, &os->eth.tx_multicast,
1129                             &ns->eth.tx_multicast);
1130         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1131                             I40E_GLPRT_BPTCL(hw->port),
1132                             pf->offset_loaded, &os->eth.tx_broadcast,
1133                             &ns->eth.tx_broadcast);
1134         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1135                             pf->offset_loaded, &os->eth.tx_discards,
1136                             &ns->eth.tx_discards);
1137         /* GLPRT_TEPC not supported */
1138
1139         /* additional port specific stats */
1140         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1141                             pf->offset_loaded, &os->tx_dropped_link_down,
1142                             &ns->tx_dropped_link_down);
1143         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1144                             pf->offset_loaded, &os->crc_errors,
1145                             &ns->crc_errors);
1146         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1147                             pf->offset_loaded, &os->illegal_bytes,
1148                             &ns->illegal_bytes);
1149         /* GLPRT_ERRBC not supported */
1150         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1151                             pf->offset_loaded, &os->mac_local_faults,
1152                             &ns->mac_local_faults);
1153         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1154                             pf->offset_loaded, &os->mac_remote_faults,
1155                             &ns->mac_remote_faults);
1156         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1157                             pf->offset_loaded, &os->rx_length_errors,
1158                             &ns->rx_length_errors);
1159         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1160                             pf->offset_loaded, &os->link_xon_rx,
1161                             &ns->link_xon_rx);
1162         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1163                             pf->offset_loaded, &os->link_xoff_rx,
1164                             &ns->link_xoff_rx);
1165         for (i = 0; i < 8; i++) {
1166                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1167                                     pf->offset_loaded,
1168                                     &os->priority_xon_rx[i],
1169                                     &ns->priority_xon_rx[i]);
1170                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1171                                     pf->offset_loaded,
1172                                     &os->priority_xoff_rx[i],
1173                                     &ns->priority_xoff_rx[i]);
1174         }
1175         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1176                             pf->offset_loaded, &os->link_xon_tx,
1177                             &ns->link_xon_tx);
1178         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1179                             pf->offset_loaded, &os->link_xoff_tx,
1180                             &ns->link_xoff_tx);
1181         for (i = 0; i < 8; i++) {
1182                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1183                                     pf->offset_loaded,
1184                                     &os->priority_xon_tx[i],
1185                                     &ns->priority_xon_tx[i]);
1186                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1187                                     pf->offset_loaded,
1188                                     &os->priority_xoff_tx[i],
1189                                     &ns->priority_xoff_tx[i]);
1190                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1191                                     pf->offset_loaded,
1192                                     &os->priority_xon_2_xoff[i],
1193                                     &ns->priority_xon_2_xoff[i]);
1194         }
1195         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1196                             I40E_GLPRT_PRC64L(hw->port),
1197                             pf->offset_loaded, &os->rx_size_64,
1198                             &ns->rx_size_64);
1199         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1200                             I40E_GLPRT_PRC127L(hw->port),
1201                             pf->offset_loaded, &os->rx_size_127,
1202                             &ns->rx_size_127);
1203         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1204                             I40E_GLPRT_PRC255L(hw->port),
1205                             pf->offset_loaded, &os->rx_size_255,
1206                             &ns->rx_size_255);
1207         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1208                             I40E_GLPRT_PRC511L(hw->port),
1209                             pf->offset_loaded, &os->rx_size_511,
1210                             &ns->rx_size_511);
1211         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1212                             I40E_GLPRT_PRC1023L(hw->port),
1213                             pf->offset_loaded, &os->rx_size_1023,
1214                             &ns->rx_size_1023);
1215         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1216                             I40E_GLPRT_PRC1522L(hw->port),
1217                             pf->offset_loaded, &os->rx_size_1522,
1218                             &ns->rx_size_1522);
1219         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1220                             I40E_GLPRT_PRC9522L(hw->port),
1221                             pf->offset_loaded, &os->rx_size_big,
1222                             &ns->rx_size_big);
1223         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1224                             pf->offset_loaded, &os->rx_undersize,
1225                             &ns->rx_undersize);
1226         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1227                             pf->offset_loaded, &os->rx_fragments,
1228                             &ns->rx_fragments);
1229         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1230                             pf->offset_loaded, &os->rx_oversize,
1231                             &ns->rx_oversize);
1232         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1233                             pf->offset_loaded, &os->rx_jabber,
1234                             &ns->rx_jabber);
1235         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1236                             I40E_GLPRT_PTC64L(hw->port),
1237                             pf->offset_loaded, &os->tx_size_64,
1238                             &ns->tx_size_64);
1239         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1240                             I40E_GLPRT_PTC127L(hw->port),
1241                             pf->offset_loaded, &os->tx_size_127,
1242                             &ns->tx_size_127);
1243         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1244                             I40E_GLPRT_PTC255L(hw->port),
1245                             pf->offset_loaded, &os->tx_size_255,
1246                             &ns->tx_size_255);
1247         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1248                             I40E_GLPRT_PTC511L(hw->port),
1249                             pf->offset_loaded, &os->tx_size_511,
1250                             &ns->tx_size_511);
1251         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1252                             I40E_GLPRT_PTC1023L(hw->port),
1253                             pf->offset_loaded, &os->tx_size_1023,
1254                             &ns->tx_size_1023);
1255         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1256                             I40E_GLPRT_PTC1522L(hw->port),
1257                             pf->offset_loaded, &os->tx_size_1522,
1258                             &ns->tx_size_1522);
1259         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1260                             I40E_GLPRT_PTC9522L(hw->port),
1261                             pf->offset_loaded, &os->tx_size_big,
1262                             &ns->tx_size_big);
1263         /* GLPRT_MSPDC not supported */
1264         /* GLPRT_XEC not supported */
1265
1266         pf->offset_loaded = true;
1267
1268         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1269                                                 ns->eth.rx_broadcast;
1270         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1271                                                 ns->eth.tx_broadcast;
1272         stats->ibytes   = ns->eth.rx_bytes;
1273         stats->obytes   = ns->eth.tx_bytes;
1274         stats->oerrors  = ns->eth.tx_errors;
1275         stats->imcasts  = ns->eth.rx_multicast;
1276
1277         if (pf->main_vsi)
1278                 i40e_update_vsi_stats(pf->main_vsi);
1279
1280 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1281         printf("***************** PF stats start *******************\n");
1282         printf("rx_bytes:            %lu\n", ns->eth.rx_bytes);
1283         printf("rx_unicast:          %lu\n", ns->eth.rx_unicast);
1284         printf("rx_multicast:        %lu\n", ns->eth.rx_multicast);
1285         printf("rx_broadcast:        %lu\n", ns->eth.rx_broadcast);
1286         printf("rx_discards:         %lu\n", ns->eth.rx_discards);
1287         printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1288         printf("tx_bytes:            %lu\n", ns->eth.tx_bytes);
1289         printf("tx_unicast:          %lu\n", ns->eth.tx_unicast);
1290         printf("tx_multicast:        %lu\n", ns->eth.tx_multicast);
1291         printf("tx_broadcast:        %lu\n", ns->eth.tx_broadcast);
1292         printf("tx_discards:         %lu\n", ns->eth.tx_discards);
1293         printf("tx_errors:           %lu\n", ns->eth.tx_errors);
1294
1295         printf("tx_dropped_link_down:     %lu\n", ns->tx_dropped_link_down);
1296         printf("crc_errors:               %lu\n", ns->crc_errors);
1297         printf("illegal_bytes:            %lu\n", ns->illegal_bytes);
1298         printf("error_bytes:              %lu\n", ns->error_bytes);
1299         printf("mac_local_faults:         %lu\n", ns->mac_local_faults);
1300         printf("mac_remote_faults:        %lu\n", ns->mac_remote_faults);
1301         printf("rx_length_errors:         %lu\n", ns->rx_length_errors);
1302         printf("link_xon_rx:              %lu\n", ns->link_xon_rx);
1303         printf("link_xoff_rx:             %lu\n", ns->link_xoff_rx);
1304         for (i = 0; i < 8; i++) {
1305                 printf("priority_xon_rx[%d]:      %lu\n",
1306                                 i, ns->priority_xon_rx[i]);
1307                 printf("priority_xoff_rx[%d]:     %lu\n",
1308                                 i, ns->priority_xoff_rx[i]);
1309         }
1310         printf("link_xon_tx:              %lu\n", ns->link_xon_tx);
1311         printf("link_xoff_tx:             %lu\n", ns->link_xoff_tx);
1312         for (i = 0; i < 8; i++) {
1313                 printf("priority_xon_tx[%d]:      %lu\n",
1314                                 i, ns->priority_xon_tx[i]);
1315                 printf("priority_xoff_tx[%d]:     %lu\n",
1316                                 i, ns->priority_xoff_tx[i]);
1317                 printf("priority_xon_2_xoff[%d]:  %lu\n",
1318                                 i, ns->priority_xon_2_xoff[i]);
1319         }
1320         printf("rx_size_64:               %lu\n", ns->rx_size_64);
1321         printf("rx_size_127:              %lu\n", ns->rx_size_127);
1322         printf("rx_size_255:              %lu\n", ns->rx_size_255);
1323         printf("rx_size_511:              %lu\n", ns->rx_size_511);
1324         printf("rx_size_1023:             %lu\n", ns->rx_size_1023);
1325         printf("rx_size_1522:             %lu\n", ns->rx_size_1522);
1326         printf("rx_size_big:              %lu\n", ns->rx_size_big);
1327         printf("rx_undersize:             %lu\n", ns->rx_undersize);
1328         printf("rx_fragments:             %lu\n", ns->rx_fragments);
1329         printf("rx_oversize:              %lu\n", ns->rx_oversize);
1330         printf("rx_jabber:                %lu\n", ns->rx_jabber);
1331         printf("tx_size_64:               %lu\n", ns->tx_size_64);
1332         printf("tx_size_127:              %lu\n", ns->tx_size_127);
1333         printf("tx_size_255:              %lu\n", ns->tx_size_255);
1334         printf("tx_size_511:              %lu\n", ns->tx_size_511);
1335         printf("tx_size_1023:             %lu\n", ns->tx_size_1023);
1336         printf("tx_size_1522:             %lu\n", ns->tx_size_1522);
1337         printf("tx_size_big:              %lu\n", ns->tx_size_big);
1338         printf("mac_short_packet_dropped: %lu\n",
1339                         ns->mac_short_packet_dropped);
1340         printf("checksum_error:           %lu\n", ns->checksum_error);
1341         printf("***************** PF stats end ********************\n");
1342 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1343 }
1344
1345 /* Reset the statistics */
1346 static void
1347 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1348 {
1349         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1350
1351         /* It results in reloading the start point of each counter */
1352         pf->offset_loaded = false;
1353 }
1354
1355 static int
1356 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1357                                  __rte_unused uint16_t queue_id,
1358                                  __rte_unused uint8_t stat_idx,
1359                                  __rte_unused uint8_t is_rx)
1360 {
1361         PMD_INIT_FUNC_TRACE();
1362
1363         return -ENOSYS;
1364 }
1365
1366 static void
1367 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1368 {
1369         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1370         struct i40e_vsi *vsi = pf->main_vsi;
1371
1372         dev_info->max_rx_queues = vsi->nb_qps;
1373         dev_info->max_tx_queues = vsi->nb_qps;
1374         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1375         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1376         dev_info->max_mac_addrs = vsi->max_macaddrs;
1377         dev_info->max_vfs = dev->pci_dev->max_vfs;
1378         dev_info->rx_offload_capa =
1379                 DEV_RX_OFFLOAD_VLAN_STRIP |
1380                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1381                 DEV_RX_OFFLOAD_UDP_CKSUM |
1382                 DEV_RX_OFFLOAD_TCP_CKSUM;
1383         dev_info->tx_offload_capa =
1384                 DEV_TX_OFFLOAD_VLAN_INSERT |
1385                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1386                 DEV_TX_OFFLOAD_UDP_CKSUM |
1387                 DEV_TX_OFFLOAD_TCP_CKSUM |
1388                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1389 }
1390
1391 static int
1392 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1393 {
1394         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395         struct i40e_vsi *vsi = pf->main_vsi;
1396         PMD_INIT_FUNC_TRACE();
1397
1398         if (on)
1399                 return i40e_vsi_add_vlan(vsi, vlan_id);
1400         else
1401                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1402 }
1403
1404 static void
1405 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1406                    __rte_unused uint16_t tpid)
1407 {
1408         PMD_INIT_FUNC_TRACE();
1409 }
1410
1411 static void
1412 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1413 {
1414         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1415         struct i40e_vsi *vsi = pf->main_vsi;
1416
1417         if (mask & ETH_VLAN_STRIP_MASK) {
1418                 /* Enable or disable VLAN stripping */
1419                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1420                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1421                 else
1422                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1423         }
1424
1425         if (mask & ETH_VLAN_EXTEND_MASK) {
1426                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1427                         i40e_vsi_config_double_vlan(vsi, TRUE);
1428                 else
1429                         i40e_vsi_config_double_vlan(vsi, FALSE);
1430         }
1431 }
1432
1433 static void
1434 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1435                           __rte_unused uint16_t queue,
1436                           __rte_unused int on)
1437 {
1438         PMD_INIT_FUNC_TRACE();
1439 }
1440
1441 static int
1442 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1443 {
1444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1445         struct i40e_vsi *vsi = pf->main_vsi;
1446         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1447         struct i40e_vsi_vlan_pvid_info info;
1448
1449         memset(&info, 0, sizeof(info));
1450         info.on = on;
1451         if (info.on)
1452                 info.config.pvid = pvid;
1453         else {
1454                 info.config.reject.tagged =
1455                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1456                 info.config.reject.untagged =
1457                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1458         }
1459
1460         return i40e_vsi_vlan_pvid_set(vsi, &info);
1461 }
1462
1463 static int
1464 i40e_dev_led_on(struct rte_eth_dev *dev)
1465 {
1466         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467         uint32_t mode = i40e_led_get(hw);
1468
1469         if (mode == 0)
1470                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1471
1472         return 0;
1473 }
1474
1475 static int
1476 i40e_dev_led_off(struct rte_eth_dev *dev)
1477 {
1478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479         uint32_t mode = i40e_led_get(hw);
1480
1481         if (mode != 0)
1482                 i40e_led_set(hw, 0, false);
1483
1484         return 0;
1485 }
1486
1487 static int
1488 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1489                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1490 {
1491         PMD_INIT_FUNC_TRACE();
1492
1493         return -ENOSYS;
1494 }
1495
1496 static int
1497 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1498                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1499 {
1500         PMD_INIT_FUNC_TRACE();
1501
1502         return -ENOSYS;
1503 }
1504
1505 /* Add a MAC address, and update filters */
1506 static void
1507 i40e_macaddr_add(struct rte_eth_dev *dev,
1508                  struct ether_addr *mac_addr,
1509                  __attribute__((unused)) uint32_t index,
1510                  __attribute__((unused)) uint32_t pool)
1511 {
1512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1514         struct i40e_vsi *vsi = pf->main_vsi;
1515         struct ether_addr old_mac;
1516         int ret;
1517
1518         if (!is_valid_assigned_ether_addr(mac_addr)) {
1519                 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1520                 return;
1521         }
1522
1523         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1524                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1525                 return;
1526         }
1527
1528         /* Write mac address */
1529         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1530                                         mac_addr->addr_bytes, NULL);
1531         if (ret != I40E_SUCCESS) {
1532                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1533                 return;
1534         }
1535
1536         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1537         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1538                         ETHER_ADDR_LEN);
1539
1540         ret = i40e_vsi_add_mac(vsi, mac_addr);
1541         if (ret != I40E_SUCCESS) {
1542                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1543                 return;
1544         }
1545
1546         ether_addr_copy(mac_addr, &pf->dev_addr);
1547         i40e_vsi_delete_mac(vsi, &old_mac);
1548 }
1549
1550 /* Remove a MAC address, and update filters */
1551 static void
1552 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1553 {
1554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1555         struct i40e_vsi *vsi = pf->main_vsi;
1556         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1557         struct ether_addr *macaddr;
1558         int ret;
1559         struct i40e_hw *hw =
1560                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561
1562         if (index >= vsi->max_macaddrs)
1563                 return;
1564
1565         macaddr = &(data->mac_addrs[index]);
1566         if (!is_valid_assigned_ether_addr(macaddr))
1567                 return;
1568
1569         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1570                                         hw->mac.perm_addr, NULL);
1571         if (ret != I40E_SUCCESS) {
1572                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1573                 return;
1574         }
1575
1576         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1577
1578         ret = i40e_vsi_delete_mac(vsi, macaddr);
1579         if (ret != I40E_SUCCESS)
1580                 return;
1581
1582         /* Clear device address as it has been removed */
1583         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1584                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1585 }
1586
1587 static int
1588 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1589                          struct rte_eth_rss_reta *reta_conf)
1590 {
1591         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1592         uint32_t lut, l;
1593         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1594
1595         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1596                 if (i < max)
1597                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1598                 else
1599                         mask = (uint8_t)((reta_conf->mask_hi >>
1600                                                 (i - max)) & 0xF);
1601
1602                 if (!mask)
1603                         continue;
1604
1605                 if (mask == 0xF)
1606                         l = 0;
1607                 else
1608                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1609
1610                 for (j = 0, lut = 0; j < 4; j++) {
1611                         if (mask & (0x1 << j))
1612                                 lut |= reta_conf->reta[i + j] << (8 * j);
1613                         else
1614                                 lut |= l & (0xFF << (8 * j));
1615                 }
1616                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1617         }
1618
1619         return 0;
1620 }
1621
1622 static int
1623 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1624                         struct rte_eth_rss_reta *reta_conf)
1625 {
1626         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627         uint32_t lut;
1628         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1629
1630         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1631                 if (i < max)
1632                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1633                 else
1634                         mask = (uint8_t)((reta_conf->mask_hi >>
1635                                                 (i - max)) & 0xF);
1636
1637                 if (!mask)
1638                         continue;
1639
1640                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1641                 for (j = 0; j < 4; j++) {
1642                         if (mask & (0x1 << j))
1643                                 reta_conf->reta[i + j] =
1644                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1645                 }
1646         }
1647
1648         return 0;
1649 }
1650
1651 /**
1652  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1653  * @hw:   pointer to the HW structure
1654  * @mem:  pointer to mem struct to fill out
1655  * @size: size of memory requested
1656  * @alignment: what to align the allocation to
1657  **/
1658 enum i40e_status_code
1659 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1660                         struct i40e_dma_mem *mem,
1661                         u64 size,
1662                         u32 alignment)
1663 {
1664         static uint64_t id = 0;
1665         const struct rte_memzone *mz = NULL;
1666         char z_name[RTE_MEMZONE_NAMESIZE];
1667
1668         if (!mem)
1669                 return I40E_ERR_PARAM;
1670
1671         id++;
1672         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1673 #ifdef RTE_LIBRTE_XEN_DOM0
1674         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1675                                                         RTE_PGSIZE_2M);
1676 #else
1677         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1678 #endif
1679         if (!mz)
1680                 return I40E_ERR_NO_MEMORY;
1681
1682         mem->id = id;
1683         mem->size = size;
1684         mem->va = mz->addr;
1685 #ifdef RTE_LIBRTE_XEN_DOM0
1686         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1687 #else
1688         mem->pa = mz->phys_addr;
1689 #endif
1690
1691         return I40E_SUCCESS;
1692 }
1693
1694 /**
1695  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1696  * @hw:   pointer to the HW structure
1697  * @mem:  ptr to mem struct to free
1698  **/
1699 enum i40e_status_code
1700 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1701                     struct i40e_dma_mem *mem)
1702 {
1703         if (!mem || !mem->va)
1704                 return I40E_ERR_PARAM;
1705
1706         mem->va = NULL;
1707         mem->pa = (u64)0;
1708
1709         return I40E_SUCCESS;
1710 }
1711
1712 /**
1713  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1714  * @hw:   pointer to the HW structure
1715  * @mem:  pointer to mem struct to fill out
1716  * @size: size of memory requested
1717  **/
1718 enum i40e_status_code
1719 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1720                          struct i40e_virt_mem *mem,
1721                          u32 size)
1722 {
1723         if (!mem)
1724                 return I40E_ERR_PARAM;
1725
1726         mem->size = size;
1727         mem->va = rte_zmalloc("i40e", size, 0);
1728
1729         if (mem->va)
1730                 return I40E_SUCCESS;
1731         else
1732                 return I40E_ERR_NO_MEMORY;
1733 }
1734
1735 /**
1736  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1737  * @hw:   pointer to the HW structure
1738  * @mem:  pointer to mem struct to free
1739  **/
1740 enum i40e_status_code
1741 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1742                      struct i40e_virt_mem *mem)
1743 {
1744         if (!mem)
1745                 return I40E_ERR_PARAM;
1746
1747         rte_free(mem->va);
1748         mem->va = NULL;
1749
1750         return I40E_SUCCESS;
1751 }
1752
1753 void
1754 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1755 {
1756         rte_spinlock_init(&sp->spinlock);
1757 }
1758
1759 void
1760 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1761 {
1762         rte_spinlock_lock(&sp->spinlock);
1763 }
1764
1765 void
1766 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1767 {
1768         rte_spinlock_unlock(&sp->spinlock);
1769 }
1770
1771 void
1772 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1773 {
1774         return;
1775 }
1776
1777 /**
1778  * Get the hardware capabilities, which will be parsed
1779  * and saved into struct i40e_hw.
1780  */
1781 static int
1782 i40e_get_cap(struct i40e_hw *hw)
1783 {
1784         struct i40e_aqc_list_capabilities_element_resp *buf;
1785         uint16_t len, size = 0;
1786         int ret;
1787
1788         /* Calculate a huge enough buff for saving response data temporarily */
1789         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1790                                                 I40E_MAX_CAP_ELE_NUM;
1791         buf = rte_zmalloc("i40e", len, 0);
1792         if (!buf) {
1793                 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1794                 return I40E_ERR_NO_MEMORY;
1795         }
1796
1797         /* Get, parse the capabilities and save it to hw */
1798         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1799                         i40e_aqc_opc_list_func_capabilities, NULL);
1800         if (ret != I40E_SUCCESS)
1801                 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1802
1803         /* Free the temporary buffer after being used */
1804         rte_free(buf);
1805
1806         return ret;
1807 }
1808
1809 static int
1810 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1811 {
1812         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1813         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1814         uint16_t sum_queues = 0, sum_vsis;
1815
1816         /* First check if FW support SRIOV */
1817         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1818                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1819                 return -EINVAL;
1820         }
1821
1822         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1823         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1824         PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1825         /* Allocate queues for pf */
1826         if (hw->func_caps.rss) {
1827                 pf->flags |= I40E_FLAG_RSS;
1828                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1829                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1830                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1831         } else
1832                 pf->lan_nb_qps = 1;
1833         sum_queues = pf->lan_nb_qps;
1834         /* Default VSI is not counted in */
1835         sum_vsis = 0;
1836         PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1837
1838         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1839                 pf->flags |= I40E_FLAG_SRIOV;
1840                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1841                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1842                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1843                                 "max supported %u.\n", dev->pci_dev->max_vfs,
1844                                                 hw->func_caps.num_vfs);
1845                         return -EINVAL;
1846                 }
1847                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1848                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1849                                 "max support %u queues.\n", pf->vf_nb_qps,
1850                                                 I40E_MAX_QP_NUM_PER_VF);
1851                         return -EINVAL;
1852                 }
1853                 pf->vf_num = dev->pci_dev->max_vfs;
1854                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1855                 sum_vsis   += pf->vf_num;
1856                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1857                                                 pf->vf_num, pf->vf_nb_qps);
1858         } else
1859                 pf->vf_num = 0;
1860
1861         if (hw->func_caps.vmdq) {
1862                 pf->flags |= I40E_FLAG_VMDQ;
1863                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1864                 sum_queues += pf->vmdq_nb_qps;
1865                 sum_vsis += 1;
1866                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1867         }
1868
1869         if (hw->func_caps.fd) {
1870                 pf->flags |= I40E_FLAG_FDIR;
1871                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1872                 /**
1873                  * Each flow director consumes one VSI and one queue,
1874                  * but can't calculate out predictably here.
1875                  */
1876         }
1877
1878         if (sum_vsis > pf->max_num_vsi ||
1879                 sum_queues > hw->func_caps.num_rx_qp) {
1880                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1881                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1882                                 pf->max_num_vsi, sum_vsis);
1883                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1884                                 hw->func_caps.num_rx_qp, sum_queues);
1885                 return -EINVAL;
1886         }
1887
1888         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1889         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1890                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1891                                 sum_vsis, hw->func_caps.num_msix_vectors);
1892                 return -EINVAL;
1893         }
1894         return I40E_SUCCESS;
1895 }
1896
1897 static int
1898 i40e_pf_get_switch_config(struct i40e_pf *pf)
1899 {
1900         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1901         struct i40e_aqc_get_switch_config_resp *switch_config;
1902         struct i40e_aqc_switch_config_element_resp *element;
1903         uint16_t start_seid = 0, num_reported;
1904         int ret;
1905
1906         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1907                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1908         if (!switch_config) {
1909                 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1910                 return -ENOMEM;
1911         }
1912
1913         /* Get the switch configurations */
1914         ret = i40e_aq_get_switch_config(hw, switch_config,
1915                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1916         if (ret != I40E_SUCCESS) {
1917                 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1918                 goto fail;
1919         }
1920         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1921         if (num_reported != 1) { /* The number should be 1 */
1922                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1923                 goto fail;
1924         }
1925
1926         /* Parse the switch configuration elements */
1927         element = &(switch_config->element[0]);
1928         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1929                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1930                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1931         } else
1932                 PMD_DRV_LOG(INFO, "Unknown element type\n");
1933
1934 fail:
1935         rte_free(switch_config);
1936
1937         return ret;
1938 }
1939
1940 static int
1941 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1942                         uint32_t num)
1943 {
1944         struct pool_entry *entry;
1945
1946         if (pool == NULL || num == 0)
1947                 return -EINVAL;
1948
1949         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1950         if (entry == NULL) {
1951                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1952                                                 "resource pool\n");
1953                 return -ENOMEM;
1954         }
1955
1956         /* queue heap initialize */
1957         pool->num_free = num;
1958         pool->num_alloc = 0;
1959         pool->base = base;
1960         LIST_INIT(&pool->alloc_list);
1961         LIST_INIT(&pool->free_list);
1962
1963         /* Initialize element  */
1964         entry->base = 0;
1965         entry->len = num;
1966
1967         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1968         return 0;
1969 }
1970
1971 static void
1972 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1973 {
1974         struct pool_entry *entry;
1975
1976         if (pool == NULL)
1977                 return;
1978
1979         LIST_FOREACH(entry, &pool->alloc_list, next) {
1980                 LIST_REMOVE(entry, next);
1981                 rte_free(entry);
1982         }
1983
1984         LIST_FOREACH(entry, &pool->free_list, next) {
1985                 LIST_REMOVE(entry, next);
1986                 rte_free(entry);
1987         }
1988
1989         pool->num_free = 0;
1990         pool->num_alloc = 0;
1991         pool->base = 0;
1992         LIST_INIT(&pool->alloc_list);
1993         LIST_INIT(&pool->free_list);
1994 }
1995
1996 static int
1997 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1998                        uint32_t base)
1999 {
2000         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2001         uint32_t pool_offset;
2002         int insert;
2003
2004         if (pool == NULL) {
2005                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
2006                 return -EINVAL;
2007         }
2008
2009         pool_offset = base - pool->base;
2010         /* Lookup in alloc list */
2011         LIST_FOREACH(entry, &pool->alloc_list, next) {
2012                 if (entry->base == pool_offset) {
2013                         valid_entry = entry;
2014                         LIST_REMOVE(entry, next);
2015                         break;
2016                 }
2017         }
2018
2019         /* Not find, return */
2020         if (valid_entry == NULL) {
2021                 PMD_DRV_LOG(ERR, "Failed to find entry\n");
2022                 return -EINVAL;
2023         }
2024
2025         /**
2026          * Found it, move it to free list  and try to merge.
2027          * In order to make merge easier, always sort it by qbase.
2028          * Find adjacent prev and last entries.
2029          */
2030         prev = next = NULL;
2031         LIST_FOREACH(entry, &pool->free_list, next) {
2032                 if (entry->base > valid_entry->base) {
2033                         next = entry;
2034                         break;
2035                 }
2036                 prev = entry;
2037         }
2038
2039         insert = 0;
2040         /* Try to merge with next one*/
2041         if (next != NULL) {
2042                 /* Merge with next one */
2043                 if (valid_entry->base + valid_entry->len == next->base) {
2044                         next->base = valid_entry->base;
2045                         next->len += valid_entry->len;
2046                         rte_free(valid_entry);
2047                         valid_entry = next;
2048                         insert = 1;
2049                 }
2050         }
2051
2052         if (prev != NULL) {
2053                 /* Merge with previous one */
2054                 if (prev->base + prev->len == valid_entry->base) {
2055                         prev->len += valid_entry->len;
2056                         /* If it merge with next one, remove next node */
2057                         if (insert == 1) {
2058                                 LIST_REMOVE(valid_entry, next);
2059                                 rte_free(valid_entry);
2060                         } else {
2061                                 rte_free(valid_entry);
2062                                 insert = 1;
2063                         }
2064                 }
2065         }
2066
2067         /* Not find any entry to merge, insert */
2068         if (insert == 0) {
2069                 if (prev != NULL)
2070                         LIST_INSERT_AFTER(prev, valid_entry, next);
2071                 else if (next != NULL)
2072                         LIST_INSERT_BEFORE(next, valid_entry, next);
2073                 else /* It's empty list, insert to head */
2074                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2075         }
2076
2077         pool->num_free += valid_entry->len;
2078         pool->num_alloc -= valid_entry->len;
2079
2080         return 0;
2081 }
2082
2083 static int
2084 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2085                        uint16_t num)
2086 {
2087         struct pool_entry *entry, *valid_entry;
2088
2089         if (pool == NULL || num == 0) {
2090                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
2091                 return -EINVAL;
2092         }
2093
2094         if (pool->num_free < num) {
2095                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
2096                                 num, pool->num_free);
2097                 return -ENOMEM;
2098         }
2099
2100         valid_entry = NULL;
2101         /* Lookup  in free list and find most fit one */
2102         LIST_FOREACH(entry, &pool->free_list, next) {
2103                 if (entry->len >= num) {
2104                         /* Find best one */
2105                         if (entry->len == num) {
2106                                 valid_entry = entry;
2107                                 break;
2108                         }
2109                         if (valid_entry == NULL || valid_entry->len > entry->len)
2110                                 valid_entry = entry;
2111                 }
2112         }
2113
2114         /* Not find one to satisfy the request, return */
2115         if (valid_entry == NULL) {
2116                 PMD_DRV_LOG(ERR, "No valid entry found\n");
2117                 return -ENOMEM;
2118         }
2119         /**
2120          * The entry have equal queue number as requested,
2121          * remove it from alloc_list.
2122          */
2123         if (valid_entry->len == num) {
2124                 LIST_REMOVE(valid_entry, next);
2125         } else {
2126                 /**
2127                  * The entry have more numbers than requested,
2128                  * create a new entry for alloc_list and minus its
2129                  * queue base and number in free_list.
2130                  */
2131                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2132                 if (entry == NULL) {
2133                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2134                                         "resource pool\n");
2135                         return -ENOMEM;
2136                 }
2137                 entry->base = valid_entry->base;
2138                 entry->len = num;
2139                 valid_entry->base += num;
2140                 valid_entry->len -= num;
2141                 valid_entry = entry;
2142         }
2143
2144         /* Insert it into alloc list, not sorted */
2145         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2146
2147         pool->num_free -= valid_entry->len;
2148         pool->num_alloc += valid_entry->len;
2149
2150         return (valid_entry->base + pool->base);
2151 }
2152
2153 /**
2154  * bitmap_is_subset - Check whether src2 is subset of src1
2155  **/
2156 static inline int
2157 bitmap_is_subset(uint8_t src1, uint8_t src2)
2158 {
2159         return !((src1 ^ src2) & src2);
2160 }
2161
2162 static int
2163 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2164 {
2165         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2166
2167         /* If DCB is not supported, only default TC is supported */
2168         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2169                 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2170                                 "only TC0 is supported\n");
2171                 return -EINVAL;
2172         }
2173
2174         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2175                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2176                         "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2177                                                         enabled_tcmap);
2178                 return -EINVAL;
2179         }
2180         return I40E_SUCCESS;
2181 }
2182
2183 int
2184 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2185                                 struct i40e_vsi_vlan_pvid_info *info)
2186 {
2187         struct i40e_hw *hw;
2188         struct i40e_vsi_context ctxt;
2189         uint8_t vlan_flags = 0;
2190         int ret;
2191
2192         if (vsi == NULL || info == NULL) {
2193                 PMD_DRV_LOG(ERR, "invalid parameters\n");
2194                 return I40E_ERR_PARAM;
2195         }
2196
2197         if (info->on) {
2198                 vsi->info.pvid = info->config.pvid;
2199                 /**
2200                  * If insert pvid is enabled, only tagged pkts are
2201                  * allowed to be sent out.
2202                  */
2203                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2204                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2205         } else {
2206                 vsi->info.pvid = 0;
2207                 if (info->config.reject.tagged == 0)
2208                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2209
2210                 if (info->config.reject.untagged == 0)
2211                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2212         }
2213         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2214                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2215         vsi->info.port_vlan_flags |= vlan_flags;
2216         vsi->info.valid_sections =
2217                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2218         memset(&ctxt, 0, sizeof(ctxt));
2219         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2220         ctxt.seid = vsi->seid;
2221
2222         hw = I40E_VSI_TO_HW(vsi);
2223         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2224         if (ret != I40E_SUCCESS)
2225                 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2226
2227         return ret;
2228 }
2229
2230 static int
2231 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2232 {
2233         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2234         int i, ret;
2235         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2236
2237         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2238         if (ret != I40E_SUCCESS)
2239                 return ret;
2240
2241         if (!vsi->seid) {
2242                 PMD_DRV_LOG(ERR, "seid not valid\n");
2243                 return -EINVAL;
2244         }
2245
2246         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2247         tc_bw_data.tc_valid_bits = enabled_tcmap;
2248         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2249                 tc_bw_data.tc_bw_credits[i] =
2250                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2251
2252         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2253         if (ret != I40E_SUCCESS) {
2254                 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2255                 return ret;
2256         }
2257
2258         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2259                                         sizeof(vsi->info.qs_handle));
2260         return I40E_SUCCESS;
2261 }
2262
2263 static int
2264 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2265                                  struct i40e_aqc_vsi_properties_data *info,
2266                                  uint8_t enabled_tcmap)
2267 {
2268         int ret, total_tc = 0, i;
2269         uint16_t qpnum_per_tc, bsf, qp_idx;
2270
2271         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2272         if (ret != I40E_SUCCESS)
2273                 return ret;
2274
2275         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2276                 if (enabled_tcmap & (1 << i))
2277                         total_tc++;
2278         vsi->enabled_tc = enabled_tcmap;
2279
2280         /* Number of queues per enabled TC */
2281         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2282         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2283         bsf = rte_bsf32(qpnum_per_tc);
2284
2285         /* Adjust the queue number to actual queues that can be applied */
2286         vsi->nb_qps = qpnum_per_tc * total_tc;
2287
2288         /**
2289          * Configure TC and queue mapping parameters, for enabled TC,
2290          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2291          * default queue will serve it.
2292          */
2293         qp_idx = 0;
2294         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2295                 if (vsi->enabled_tc & (1 << i)) {
2296                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2297                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2298                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2299                         qp_idx += qpnum_per_tc;
2300                 } else
2301                         info->tc_mapping[i] = 0;
2302         }
2303
2304         /* Associate queue number with VSI */
2305         if (vsi->type == I40E_VSI_SRIOV) {
2306                 info->mapping_flags |=
2307                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2308                 for (i = 0; i < vsi->nb_qps; i++)
2309                         info->queue_mapping[i] =
2310                                 rte_cpu_to_le_16(vsi->base_queue + i);
2311         } else {
2312                 info->mapping_flags |=
2313                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2314                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2315         }
2316         info->valid_sections =
2317                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2318
2319         return I40E_SUCCESS;
2320 }
2321
2322 static int
2323 i40e_veb_release(struct i40e_veb *veb)
2324 {
2325         struct i40e_vsi *vsi;
2326         struct i40e_hw *hw;
2327
2328         if (veb == NULL || veb->associate_vsi == NULL)
2329                 return -EINVAL;
2330
2331         if (!TAILQ_EMPTY(&veb->head)) {
2332                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2333                 return -EACCES;
2334         }
2335
2336         vsi = veb->associate_vsi;
2337         hw = I40E_VSI_TO_HW(vsi);
2338
2339         vsi->uplink_seid = veb->uplink_seid;
2340         i40e_aq_delete_element(hw, veb->seid, NULL);
2341         rte_free(veb);
2342         vsi->veb = NULL;
2343         return I40E_SUCCESS;
2344 }
2345
2346 /* Setup a veb */
2347 static struct i40e_veb *
2348 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2349 {
2350         struct i40e_veb *veb;
2351         int ret;
2352         struct i40e_hw *hw;
2353
2354         if (NULL == pf || vsi == NULL) {
2355                 PMD_DRV_LOG(ERR, "veb setup failed, "
2356                         "associated VSI shouldn't null\n");
2357                 return NULL;
2358         }
2359         hw = I40E_PF_TO_HW(pf);
2360
2361         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2362         if (!veb) {
2363                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2364                 goto fail;
2365         }
2366
2367         veb->associate_vsi = vsi;
2368         TAILQ_INIT(&veb->head);
2369         veb->uplink_seid = vsi->uplink_seid;
2370
2371         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2372                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2373
2374         if (ret != I40E_SUCCESS) {
2375                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2376                                         hw->aq.asq_last_status);
2377                 goto fail;
2378         }
2379
2380         /* get statistics index */
2381         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2382                                 &veb->stats_idx, NULL, NULL, NULL);
2383         if (ret != I40E_SUCCESS) {
2384                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2385                                                 hw->aq.asq_last_status);
2386                 goto fail;
2387         }
2388
2389         /* Get VEB bandwidth, to be implemented */
2390         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2391         vsi->uplink_seid = veb->seid;
2392
2393         return veb;
2394 fail:
2395         rte_free(veb);
2396         return NULL;
2397 }
2398
2399 int
2400 i40e_vsi_release(struct i40e_vsi *vsi)
2401 {
2402         struct i40e_pf *pf;
2403         struct i40e_hw *hw;
2404         struct i40e_vsi_list *vsi_list;
2405         int ret;
2406         struct i40e_mac_filter *f;
2407
2408         if (!vsi)
2409                 return I40E_SUCCESS;
2410
2411         pf = I40E_VSI_TO_PF(vsi);
2412         hw = I40E_VSI_TO_HW(vsi);
2413
2414         /* VSI has child to attach, release child first */
2415         if (vsi->veb) {
2416                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2417                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2418                                 return -1;
2419                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2420                 }
2421                 i40e_veb_release(vsi->veb);
2422         }
2423
2424         /* Remove all macvlan filters of the VSI */
2425         i40e_vsi_remove_all_macvlan_filter(vsi);
2426         TAILQ_FOREACH(f, &vsi->mac_list, next)
2427                 rte_free(f);
2428
2429         if (vsi->type != I40E_VSI_MAIN) {
2430                 /* Remove vsi from parent's sibling list */
2431                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2432                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2433                         return I40E_ERR_PARAM;
2434                 }
2435                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2436                                 &vsi->sib_vsi_list, list);
2437
2438                 /* Remove all switch element of the VSI */
2439                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2440                 if (ret != I40E_SUCCESS)
2441                         PMD_DRV_LOG(ERR, "Failed to delete element\n");
2442         }
2443         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2444
2445         if (vsi->type != I40E_VSI_SRIOV)
2446                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2447         rte_free(vsi);
2448
2449         return I40E_SUCCESS;
2450 }
2451
2452 static int
2453 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2454 {
2455         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2456         struct i40e_aqc_remove_macvlan_element_data def_filter;
2457         int ret;
2458
2459         if (vsi->type != I40E_VSI_MAIN)
2460                 return I40E_ERR_CONFIG;
2461         memset(&def_filter, 0, sizeof(def_filter));
2462         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2463                                         ETH_ADDR_LEN);
2464         def_filter.vlan_tag = 0;
2465         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2466                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2467         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2468         if (ret != I40E_SUCCESS) {
2469                 struct i40e_mac_filter *f;
2470
2471                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2472                                                 "macvlan filter\n");
2473                 /* It needs to add the permanent mac into mac list */
2474                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2475                 if (f == NULL) {
2476                         PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2477                         return I40E_ERR_NO_MEMORY;
2478                 }
2479                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2480                                 ETH_ADDR_LEN);
2481                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2482                 vsi->mac_num++;
2483
2484                 return ret;
2485         }
2486
2487         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2488 }
2489
2490 static int
2491 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2492 {
2493         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2494         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2495         struct i40e_hw *hw = &vsi->adapter->hw;
2496         i40e_status ret;
2497         int i;
2498
2499         memset(&bw_config, 0, sizeof(bw_config));
2500         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2501         if (ret != I40E_SUCCESS) {
2502                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2503                         "configuration %u\n", hw->aq.asq_last_status);
2504                 return ret;
2505         }
2506
2507         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2508         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2509                                         &ets_sla_config, NULL);
2510         if (ret != I40E_SUCCESS) {
2511                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2512                         "configuration %u\n", hw->aq.asq_last_status);
2513                 return ret;
2514         }
2515
2516         /* Not store the info yet, just print out */
2517         PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2518         PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2519         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2520                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2521                                         ets_sla_config.share_credits[i]);
2522                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2523                         rte_le_to_cpu_16(ets_sla_config.credits[i]));
2524                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2525                         rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2526                                                                 (i * 4));
2527         }
2528
2529         return 0;
2530 }
2531
2532 /* Setup a VSI */
2533 struct i40e_vsi *
2534 i40e_vsi_setup(struct i40e_pf *pf,
2535                enum i40e_vsi_type type,
2536                struct i40e_vsi *uplink_vsi,
2537                uint16_t user_param)
2538 {
2539         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2540         struct i40e_vsi *vsi;
2541         int ret;
2542         struct i40e_vsi_context ctxt;
2543         struct ether_addr broadcast =
2544                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2545
2546         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2547                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2548                         "VSI link shouldn't be NULL\n");
2549                 return NULL;
2550         }
2551
2552         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2553                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2554                                 "uplink VSI should be NULL\n");
2555                 return NULL;
2556         }
2557
2558         /* If uplink vsi didn't setup VEB, create one first */
2559         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2560                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2561
2562                 if (NULL == uplink_vsi->veb) {
2563                         PMD_DRV_LOG(ERR, "VEB setup failed\n");
2564                         return NULL;
2565                 }
2566         }
2567
2568         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2569         if (!vsi) {
2570                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2571                 return NULL;
2572         }
2573         TAILQ_INIT(&vsi->mac_list);
2574         vsi->type = type;
2575         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2576         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2577         vsi->parent_vsi = uplink_vsi;
2578         vsi->user_param = user_param;
2579         /* Allocate queues */
2580         switch (vsi->type) {
2581         case I40E_VSI_MAIN  :
2582                 vsi->nb_qps = pf->lan_nb_qps;
2583                 break;
2584         case I40E_VSI_SRIOV :
2585                 vsi->nb_qps = pf->vf_nb_qps;
2586                 break;
2587         default:
2588                 goto fail_mem;
2589         }
2590         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2591         if (ret < 0) {
2592                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2593                                 vsi->seid, ret);
2594                 goto fail_mem;
2595         }
2596         vsi->base_queue = ret;
2597
2598         /* VF has MSIX interrupt in VF range, don't allocate here */
2599         if (type != I40E_VSI_SRIOV) {
2600                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2601                 if (ret < 0) {
2602                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2603                         goto fail_queue_alloc;
2604                 }
2605                 vsi->msix_intr = ret;
2606         } else
2607                 vsi->msix_intr = 0;
2608         /* Add VSI */
2609         if (type == I40E_VSI_MAIN) {
2610                 /* For main VSI, no need to add since it's default one */
2611                 vsi->uplink_seid = pf->mac_seid;
2612                 vsi->seid = pf->main_vsi_seid;
2613                 /* Bind queues with specific MSIX interrupt */
2614                 /**
2615                  * Needs 2 interrupt at least, one for misc cause which will
2616                  * enabled from OS side, Another for queues binding the
2617                  * interrupt from device side only.
2618                  */
2619
2620                 /* Get default VSI parameters from hardware */
2621                 memset(&ctxt, 0, sizeof(ctxt));
2622                 ctxt.seid = vsi->seid;
2623                 ctxt.pf_num = hw->pf_id;
2624                 ctxt.uplink_seid = vsi->uplink_seid;
2625                 ctxt.vf_num = 0;
2626                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2627                 if (ret != I40E_SUCCESS) {
2628                         PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2629                         goto fail_msix_alloc;
2630                 }
2631                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2632                         sizeof(struct i40e_aqc_vsi_properties_data));
2633                 vsi->vsi_id = ctxt.vsi_number;
2634                 vsi->info.valid_sections = 0;
2635
2636                 /* Configure tc, enabled TC0 only */
2637                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2638                         I40E_SUCCESS) {
2639                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2640                         goto fail_msix_alloc;
2641                 }
2642
2643                 /* TC, queue mapping */
2644                 memset(&ctxt, 0, sizeof(ctxt));
2645                 vsi->info.valid_sections |=
2646                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2647                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2648                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2649                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2650                         sizeof(struct i40e_aqc_vsi_properties_data));
2651                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2652                                                 I40E_DEFAULT_TCMAP);
2653                 if (ret != I40E_SUCCESS) {
2654                         PMD_DRV_LOG(ERR, "Failed to configure "
2655                                         "TC queue mapping\n");
2656                         goto fail_msix_alloc;
2657                 }
2658                 ctxt.seid = vsi->seid;
2659                 ctxt.pf_num = hw->pf_id;
2660                 ctxt.uplink_seid = vsi->uplink_seid;
2661                 ctxt.vf_num = 0;
2662
2663                 /* Update VSI parameters */
2664                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2665                 if (ret != I40E_SUCCESS) {
2666                         PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2667                         goto fail_msix_alloc;
2668                 }
2669
2670                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2671                                                 sizeof(vsi->info.tc_mapping));
2672                 (void)rte_memcpy(&vsi->info.queue_mapping,
2673                                 &ctxt.info.queue_mapping,
2674                         sizeof(vsi->info.queue_mapping));
2675                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2676                 vsi->info.valid_sections = 0;
2677
2678                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2679                                 ETH_ADDR_LEN);
2680
2681                 /**
2682                  * Updating default filter settings are necessary to prevent
2683                  * reception of tagged packets.
2684                  * Some old firmware configurations load a default macvlan
2685                  * filter which accepts both tagged and untagged packets.
2686                  * The updating is to use a normal filter instead if needed.
2687                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2688                  * The firmware with correct configurations load the default
2689                  * macvlan filter which is expected and cannot be removed.
2690                  */
2691                 i40e_update_default_filter_setting(vsi);
2692         } else if (type == I40E_VSI_SRIOV) {
2693                 memset(&ctxt, 0, sizeof(ctxt));
2694                 /**
2695                  * For other VSI, the uplink_seid equals to uplink VSI's
2696                  * uplink_seid since they share same VEB
2697                  */
2698                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2699                 ctxt.pf_num = hw->pf_id;
2700                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2701                 ctxt.uplink_seid = vsi->uplink_seid;
2702                 ctxt.connection_type = 0x1;
2703                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2704
2705                 /* Configure switch ID */
2706                 ctxt.info.valid_sections |=
2707                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2708                 ctxt.info.switch_id =
2709                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2710                 /* Configure port/vlan */
2711                 ctxt.info.valid_sections |=
2712                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2713                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2714                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2715                                                 I40E_DEFAULT_TCMAP);
2716                 if (ret != I40E_SUCCESS) {
2717                         PMD_DRV_LOG(ERR, "Failed to configure "
2718                                         "TC queue mapping\n");
2719                         goto fail_msix_alloc;
2720                 }
2721                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2722                 ctxt.info.valid_sections |=
2723                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2724                 /**
2725                  * Since VSI is not created yet, only configure parameter,
2726                  * will add vsi below.
2727                  */
2728         }
2729         else {
2730                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2731                 goto fail_msix_alloc;
2732         }
2733
2734         if (vsi->type != I40E_VSI_MAIN) {
2735                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2736                 if (ret) {
2737                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2738                                  hw->aq.asq_last_status);
2739                         goto fail_msix_alloc;
2740                 }
2741                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2742                 vsi->info.valid_sections = 0;
2743                 vsi->seid = ctxt.seid;
2744                 vsi->vsi_id = ctxt.vsi_number;
2745                 vsi->sib_vsi_list.vsi = vsi;
2746                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2747                                 &vsi->sib_vsi_list, list);
2748         }
2749
2750         /* MAC/VLAN configuration */
2751         ret = i40e_vsi_add_mac(vsi, &broadcast);
2752         if (ret != I40E_SUCCESS) {
2753                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2754                 goto fail_msix_alloc;
2755         }
2756
2757         /* Get VSI BW information */
2758         i40e_vsi_dump_bw_config(vsi);
2759         return vsi;
2760 fail_msix_alloc:
2761         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2762 fail_queue_alloc:
2763         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2764 fail_mem:
2765         rte_free(vsi);
2766         return NULL;
2767 }
2768
2769 /* Configure vlan stripping on or off */
2770 int
2771 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2772 {
2773         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2774         struct i40e_vsi_context ctxt;
2775         uint8_t vlan_flags;
2776         int ret = I40E_SUCCESS;
2777
2778         /* Check if it has been already on or off */
2779         if (vsi->info.valid_sections &
2780                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2781                 if (on) {
2782                         if ((vsi->info.port_vlan_flags &
2783                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2784                                 return 0; /* already on */
2785                 } else {
2786                         if ((vsi->info.port_vlan_flags &
2787                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2788                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2789                                 return 0; /* already off */
2790                 }
2791         }
2792
2793         if (on)
2794                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2795         else
2796                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2797         vsi->info.valid_sections =
2798                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2799         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2800         vsi->info.port_vlan_flags |= vlan_flags;
2801         ctxt.seid = vsi->seid;
2802         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2803         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2804         if (ret)
2805                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2806                                                 on ? "enable" : "disable");
2807
2808         return ret;
2809 }
2810
2811 static int
2812 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2813 {
2814         struct rte_eth_dev_data *data = dev->data;
2815         int ret;
2816
2817         /* Apply vlan offload setting */
2818         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2819
2820         /* Apply double-vlan setting, not implemented yet */
2821
2822         /* Apply pvid setting */
2823         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2824                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2825         if (ret)
2826                 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2827
2828         return ret;
2829 }
2830
2831 static int
2832 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2833 {
2834         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2835
2836         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2837 }
2838
2839 static int
2840 i40e_update_flow_control(struct i40e_hw *hw)
2841 {
2842 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2843         struct i40e_link_status link_status;
2844         uint32_t rxfc = 0, txfc = 0, reg;
2845         uint8_t an_info;
2846         int ret;
2847
2848         memset(&link_status, 0, sizeof(link_status));
2849         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2850         if (ret != I40E_SUCCESS) {
2851                 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2852                 goto write_reg; /* Disable flow control */
2853         }
2854
2855         an_info = hw->phy.link_info.an_info;
2856         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2857                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2858                 ret = I40E_ERR_NOT_READY;
2859                 goto write_reg; /* Disable flow control */
2860         }
2861         /**
2862          * If link auto negotiation is enabled, flow control needs to
2863          * be configured according to it
2864          */
2865         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2866         case I40E_LINK_PAUSE_RXTX:
2867                 rxfc = 1;
2868                 txfc = 1;
2869                 hw->fc.current_mode = I40E_FC_FULL;
2870                 break;
2871         case I40E_AQ_LINK_PAUSE_RX:
2872                 rxfc = 1;
2873                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2874                 break;
2875         case I40E_AQ_LINK_PAUSE_TX:
2876                 txfc = 1;
2877                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2878                 break;
2879         default:
2880                 hw->fc.current_mode = I40E_FC_NONE;
2881                 break;
2882         }
2883
2884 write_reg:
2885         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2886                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2887         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2888         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2889         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2890         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2891
2892         return ret;
2893 }
2894
2895 /* PF setup */
2896 static int
2897 i40e_pf_setup(struct i40e_pf *pf)
2898 {
2899         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2900         struct i40e_filter_control_settings settings;
2901         struct rte_eth_dev_data *dev_data = pf->dev_data;
2902         struct i40e_vsi *vsi;
2903         int ret;
2904
2905         /* Clear all stats counters */
2906         pf->offset_loaded = FALSE;
2907         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2908         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2909
2910         ret = i40e_pf_get_switch_config(pf);
2911         if (ret != I40E_SUCCESS) {
2912                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2913                 return ret;
2914         }
2915
2916         /* VSI setup */
2917         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2918         if (!vsi) {
2919                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2920                 return I40E_ERR_NOT_READY;
2921         }
2922         pf->main_vsi = vsi;
2923         dev_data->nb_rx_queues = vsi->nb_qps;
2924         dev_data->nb_tx_queues = vsi->nb_qps;
2925
2926         /* Configure filter control */
2927         memset(&settings, 0, sizeof(settings));
2928         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2929         /* Enable ethtype and macvlan filters */
2930         settings.enable_ethtype = TRUE;
2931         settings.enable_macvlan = TRUE;
2932         ret = i40e_set_filter_control(hw, &settings);
2933         if (ret)
2934                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2935                                                                 ret);
2936
2937         /* Update flow control according to the auto negotiation */
2938         i40e_update_flow_control(hw);
2939
2940         return I40E_SUCCESS;
2941 }
2942
2943 int
2944 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2945 {
2946         uint32_t reg;
2947         uint16_t j;
2948
2949         /**
2950          * Set or clear TX Queue Disable flags,
2951          * which is required by hardware.
2952          */
2953         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2954         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2955
2956         /* Wait until the request is finished */
2957         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2958                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2959                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2960                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2961                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2962                                                         & 0x1))) {
2963                         break;
2964                 }
2965         }
2966         if (on) {
2967                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2968                         return I40E_SUCCESS; /* already on, skip next steps */
2969
2970                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2971                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2972         } else {
2973                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2974                         return I40E_SUCCESS; /* already off, skip next steps */
2975                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2976         }
2977         /* Write the register */
2978         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2979         /* Check the result */
2980         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2981                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2982                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2983                 if (on) {
2984                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2985                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2986                                 break;
2987                 } else {
2988                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2989                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2990                                 break;
2991                 }
2992         }
2993         /* Check if it is timeout */
2994         if (j >= I40E_CHK_Q_ENA_COUNT) {
2995                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2996                         (on ? "enable" : "disable"), q_idx);
2997                 return I40E_ERR_TIMEOUT;
2998         }
2999
3000         return I40E_SUCCESS;
3001 }
3002
3003 /* Swith on or off the tx queues */
3004 static int
3005 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3006 {
3007         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3008         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3009         struct i40e_tx_queue *txq;
3010         uint16_t i, pf_q;
3011         int ret;
3012
3013         pf_q = vsi->base_queue;
3014         for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
3015                 txq = dev_data->tx_queues[i];
3016                 if (!txq->q_set)
3017                         continue; /* Queue not configured */
3018                 ret = i40e_switch_tx_queue(hw, pf_q, on);
3019                 if ( ret != I40E_SUCCESS)
3020                         return ret;
3021         }
3022
3023         return I40E_SUCCESS;
3024 }
3025
3026 int
3027 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3028 {
3029         uint32_t reg;
3030         uint16_t j;
3031
3032         /* Wait until the request is finished */
3033         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3034                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3035                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3036                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3037                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3038                         break;
3039         }
3040
3041         if (on) {
3042                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3043                         return I40E_SUCCESS; /* Already on, skip next steps */
3044                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3045         } else {
3046                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3047                         return I40E_SUCCESS; /* Already off, skip next steps */
3048                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3049         }
3050
3051         /* Write the register */
3052         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3053         /* Check the result */
3054         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3055                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3056                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3057                 if (on) {
3058                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3059                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3060                                 break;
3061                 } else {
3062                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3063                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3064                                 break;
3065                 }
3066         }
3067
3068         /* Check if it is timeout */
3069         if (j >= I40E_CHK_Q_ENA_COUNT) {
3070                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
3071                         (on ? "enable" : "disable"), q_idx);
3072                 return I40E_ERR_TIMEOUT;
3073         }
3074
3075         return I40E_SUCCESS;
3076 }
3077 /* Switch on or off the rx queues */
3078 static int
3079 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3080 {
3081         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3082         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3083         struct i40e_rx_queue *rxq;
3084         uint16_t i, pf_q;
3085         int ret;
3086
3087         pf_q = vsi->base_queue;
3088         for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
3089                 rxq = dev_data->rx_queues[i];
3090                 if (!rxq->q_set)
3091                         continue; /* Queue not configured */
3092                 ret = i40e_switch_rx_queue(hw, pf_q, on);
3093                 if ( ret != I40E_SUCCESS)
3094                         return ret;
3095         }
3096
3097         return I40E_SUCCESS;
3098 }
3099
3100 /* Switch on or off all the rx/tx queues */
3101 int
3102 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3103 {
3104         int ret;
3105
3106         if (on) {
3107                 /* enable rx queues before enabling tx queues */
3108                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3109                 if (ret) {
3110                         PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
3111                         return ret;
3112                 }
3113                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3114         } else {
3115                 /* Stop tx queues before stopping rx queues */
3116                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3117                 if (ret) {
3118                         PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
3119                         return ret;
3120                 }
3121                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3122         }
3123
3124         return ret;
3125 }
3126
3127 /* Initialize VSI for TX */
3128 static int
3129 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3130 {
3131         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3132         struct rte_eth_dev_data *data = pf->dev_data;
3133         uint16_t i;
3134         uint32_t ret = I40E_SUCCESS;
3135
3136         for (i = 0; i < data->nb_tx_queues; i++) {
3137                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3138                 if (ret != I40E_SUCCESS)
3139                         break;
3140         }
3141
3142         return ret;
3143 }
3144
3145 /* Initialize VSI for RX */
3146 static int
3147 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3148 {
3149         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3150         struct rte_eth_dev_data *data = pf->dev_data;
3151         int ret = I40E_SUCCESS;
3152         uint16_t i;
3153
3154         i40e_pf_config_mq_rx(pf);
3155         for (i = 0; i < data->nb_rx_queues; i++) {
3156                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3157                 if (ret != I40E_SUCCESS) {
3158                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3159                                         "initialization\n");
3160                         break;
3161                 }
3162         }
3163
3164         return ret;
3165 }
3166
3167 /* Initialize VSI */
3168 static int
3169 i40e_vsi_init(struct i40e_vsi *vsi)
3170 {
3171         int err;
3172
3173         err = i40e_vsi_tx_init(vsi);
3174         if (err) {
3175                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
3176                 return err;
3177         }
3178         err = i40e_vsi_rx_init(vsi);
3179         if (err) {
3180                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3181                 return err;
3182         }
3183
3184         return err;
3185 }
3186
3187 static void
3188 i40e_stat_update_32(struct i40e_hw *hw,
3189                    uint32_t reg,
3190                    bool offset_loaded,
3191                    uint64_t *offset,
3192                    uint64_t *stat)
3193 {
3194         uint64_t new_data;
3195
3196         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3197         if (!offset_loaded)
3198                 *offset = new_data;
3199
3200         if (new_data >= *offset)
3201                 *stat = (uint64_t)(new_data - *offset);
3202         else
3203                 *stat = (uint64_t)((new_data +
3204                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3205 }
3206
3207 static void
3208 i40e_stat_update_48(struct i40e_hw *hw,
3209                    uint32_t hireg,
3210                    uint32_t loreg,
3211                    bool offset_loaded,
3212                    uint64_t *offset,
3213                    uint64_t *stat)
3214 {
3215         uint64_t new_data;
3216
3217         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3218         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3219                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3220
3221         if (!offset_loaded)
3222                 *offset = new_data;
3223
3224         if (new_data >= *offset)
3225                 *stat = new_data - *offset;
3226         else
3227                 *stat = (uint64_t)((new_data +
3228                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3229
3230         *stat &= I40E_48_BIT_MASK;
3231 }
3232
3233 /* Disable IRQ0 */
3234 void
3235 i40e_pf_disable_irq0(struct i40e_hw *hw)
3236 {
3237         /* Disable all interrupt types */
3238         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3239         I40E_WRITE_FLUSH(hw);
3240 }
3241
3242 /* Enable IRQ0 */
3243 void
3244 i40e_pf_enable_irq0(struct i40e_hw *hw)
3245 {
3246         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3247                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3248                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3249                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3250         I40E_WRITE_FLUSH(hw);
3251 }
3252
3253 static void
3254 i40e_pf_config_irq0(struct i40e_hw *hw)
3255 {
3256         uint32_t enable;
3257
3258         /* read pending request and disable first */
3259         i40e_pf_disable_irq0(hw);
3260         /**
3261          * Enable all interrupt error options to detect possible errors,
3262          * other informative int are ignored
3263          */
3264         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3265                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3266                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3267                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3268                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3269                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3270                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3271                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3272
3273         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3274         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3275                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3276
3277         /* Link no queues with irq0 */
3278         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3279                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3280 }
3281
3282 static void
3283 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3284 {
3285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287         int i;
3288         uint16_t abs_vf_id;
3289         uint32_t index, offset, val;
3290
3291         if (!pf->vfs)
3292                 return;
3293         /**
3294          * Try to find which VF trigger a reset, use absolute VF id to access
3295          * since the reg is global register.
3296          */
3297         for (i = 0; i < pf->vf_num; i++) {
3298                 abs_vf_id = hw->func_caps.vf_base_id + i;
3299                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3300                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3301                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3302                 /* VFR event occured */
3303                 if (val & (0x1 << offset)) {
3304                         int ret;
3305
3306                         /* Clear the event first */
3307                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3308                                                         (0x1 << offset));
3309                         PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3310                         /**
3311                          * Only notify a VF reset event occured,
3312                          * don't trigger another SW reset
3313                          */
3314                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3315                         if (ret != I40E_SUCCESS)
3316                                 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3317                 }
3318         }
3319 }
3320
3321 static void
3322 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3323 {
3324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         struct i40e_arq_event_info info;
3326         uint16_t pending, opcode;
3327         int ret;
3328
3329         info.msg_size = I40E_AQ_BUF_SZ;
3330         info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3331         if (!info.msg_buf) {
3332                 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3333                 return;
3334         }
3335
3336         pending = 1;
3337         while (pending) {
3338                 ret = i40e_clean_arq_element(hw, &info, &pending);
3339
3340                 if (ret != I40E_SUCCESS) {
3341                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3342                                 "aq_err: %u\n", hw->aq.asq_last_status);
3343                         break;
3344                 }
3345                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3346
3347                 switch (opcode) {
3348                 case i40e_aqc_opc_send_msg_to_pf:
3349                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3350                         i40e_pf_host_handle_vf_msg(dev,
3351                                         rte_le_to_cpu_16(info.desc.retval),
3352                                         rte_le_to_cpu_32(info.desc.cookie_high),
3353                                         rte_le_to_cpu_32(info.desc.cookie_low),
3354                                         info.msg_buf,
3355                                         info.msg_size);
3356                         break;
3357                 default:
3358                         PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3359                                 opcode);
3360                         break;
3361                 }
3362                 /* Reset the buffer after processing one */
3363                 info.msg_size = I40E_AQ_BUF_SZ;
3364         }
3365         rte_free(info.msg_buf);
3366 }
3367
3368 /**
3369  * Interrupt handler triggered by NIC  for handling
3370  * specific interrupt.
3371  *
3372  * @param handle
3373  *  Pointer to interrupt handle.
3374  * @param param
3375  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3376  *
3377  * @return
3378  *  void
3379  */
3380 static void
3381 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3382                            void *param)
3383 {
3384         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3385         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386         uint32_t cause, enable;
3387
3388         i40e_pf_disable_irq0(hw);
3389
3390         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3391         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3392
3393         /* Shared IRQ case, return */
3394         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3395                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3396                         "no INT event to process\n", hw->pf_id);
3397                 goto done;
3398         }
3399
3400         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3401                 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3402                 i40e_dev_link_update(dev, 0);
3403         }
3404
3405         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3406                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3407
3408         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3409                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3410
3411         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3412                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3413
3414         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3415                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3416
3417         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3418                 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3419
3420         /* Add processing func to deal with VF reset vent */
3421         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3422                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3423                 i40e_dev_handle_vfr_event(dev);
3424         }
3425         /* Find admin queue event */
3426         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3427                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3428                 i40e_dev_handle_aq_msg(dev);
3429         }
3430
3431 done:
3432         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3433         /* Re-enable interrupt from device side */
3434         i40e_pf_enable_irq0(hw);
3435         /* Re-enable interrupt from host side */
3436         rte_intr_enable(&(dev->pci_dev->intr_handle));
3437 }
3438
3439 static int
3440 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3441                          struct i40e_macvlan_filter *filter,
3442                          int total)
3443 {
3444         int ele_num, ele_buff_size;
3445         int num, actual_num, i;
3446         int ret = I40E_SUCCESS;
3447         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3448         struct i40e_aqc_add_macvlan_element_data *req_list;
3449
3450         if (filter == NULL  || total == 0)
3451                 return I40E_ERR_PARAM;
3452         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3453         ele_buff_size = hw->aq.asq_buf_size;
3454
3455         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3456         if (req_list == NULL) {
3457                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3458                 return I40E_ERR_NO_MEMORY;
3459         }
3460
3461         num = 0;
3462         do {
3463                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3464                 memset(req_list, 0, ele_buff_size);
3465
3466                 for (i = 0; i < actual_num; i++) {
3467                         (void)rte_memcpy(req_list[i].mac_addr,
3468                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3469                         req_list[i].vlan_tag =
3470                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3471                         req_list[i].flags = rte_cpu_to_le_16(\
3472                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3473                         req_list[i].queue_number = 0;
3474                 }
3475
3476                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3477                                                 actual_num, NULL);
3478                 if (ret != I40E_SUCCESS) {
3479                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3480                         goto DONE;
3481                 }
3482                 num += actual_num;
3483         } while (num < total);
3484
3485 DONE:
3486         rte_free(req_list);
3487         return ret;
3488 }
3489
3490 static int
3491 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3492                             struct i40e_macvlan_filter *filter,
3493                             int total)
3494 {
3495         int ele_num, ele_buff_size;
3496         int num, actual_num, i;
3497         int ret = I40E_SUCCESS;
3498         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3499         struct i40e_aqc_remove_macvlan_element_data *req_list;
3500
3501         if (filter == NULL  || total == 0)
3502                 return I40E_ERR_PARAM;
3503
3504         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3505         ele_buff_size = hw->aq.asq_buf_size;
3506
3507         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3508         if (req_list == NULL) {
3509                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3510                 return I40E_ERR_NO_MEMORY;
3511         }
3512
3513         num = 0;
3514         do {
3515                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3516                 memset(req_list, 0, ele_buff_size);
3517
3518                 for (i = 0; i < actual_num; i++) {
3519                         (void)rte_memcpy(req_list[i].mac_addr,
3520                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3521                         req_list[i].vlan_tag =
3522                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3523                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3524                 }
3525
3526                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3527                                                 actual_num, NULL);
3528                 if (ret != I40E_SUCCESS) {
3529                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3530                         goto DONE;
3531                 }
3532                 num += actual_num;
3533         } while (num < total);
3534
3535 DONE:
3536         rte_free(req_list);
3537         return ret;
3538 }
3539
3540 /* Find out specific MAC filter */
3541 static struct i40e_mac_filter *
3542 i40e_find_mac_filter(struct i40e_vsi *vsi,
3543                          struct ether_addr *macaddr)
3544 {
3545         struct i40e_mac_filter *f;
3546
3547         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3548                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3549                         return f;
3550         }
3551
3552         return NULL;
3553 }
3554
3555 static bool
3556 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3557                          uint16_t vlan_id)
3558 {
3559         uint32_t vid_idx, vid_bit;
3560
3561         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3562         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3563
3564         if (vsi->vfta[vid_idx] & vid_bit)
3565                 return 1;
3566         else
3567                 return 0;
3568 }
3569
3570 static void
3571 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3572                          uint16_t vlan_id, bool on)
3573 {
3574         uint32_t vid_idx, vid_bit;
3575
3576 #define UINT32_BIT_MASK      0x1F
3577 #define VALID_VLAN_BIT_MASK  0xFFF
3578         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3579          *  element first, then find the bits it belongs to
3580          */
3581         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3582                   sizeof(uint32_t));
3583         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3584
3585         if (on)
3586                 vsi->vfta[vid_idx] |= vid_bit;
3587         else
3588                 vsi->vfta[vid_idx] &= ~vid_bit;
3589 }
3590
3591 /**
3592  * Find all vlan options for specific mac addr,
3593  * return with actual vlan found.
3594  */
3595 static inline int
3596 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3597                            struct i40e_macvlan_filter *mv_f,
3598                            int num, struct ether_addr *addr)
3599 {
3600         int i;
3601         uint32_t j, k;
3602
3603         /**
3604          * Not to use i40e_find_vlan_filter to decrease the loop time,
3605          * although the code looks complex.
3606           */
3607         if (num < vsi->vlan_num)
3608                 return I40E_ERR_PARAM;
3609
3610         i = 0;
3611         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3612                 if (vsi->vfta[j]) {
3613                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3614                                 if (vsi->vfta[j] & (1 << k)) {
3615                                         if (i > num - 1) {
3616                                                 PMD_DRV_LOG(ERR, "vlan number "
3617                                                                 "not match\n");
3618                                                 return I40E_ERR_PARAM;
3619                                         }
3620                                         (void)rte_memcpy(&mv_f[i].macaddr,
3621                                                         addr, ETH_ADDR_LEN);
3622                                         mv_f[i].vlan_id =
3623                                                 j * I40E_UINT32_BIT_SIZE + k;
3624                                         i++;
3625                                 }
3626                         }
3627                 }
3628         }
3629         return I40E_SUCCESS;
3630 }
3631
3632 static inline int
3633 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3634                            struct i40e_macvlan_filter *mv_f,
3635                            int num,
3636                            uint16_t vlan)
3637 {
3638         int i = 0;
3639         struct i40e_mac_filter *f;
3640
3641         if (num < vsi->mac_num)
3642                 return I40E_ERR_PARAM;
3643
3644         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3645                 if (i > num - 1) {
3646                         PMD_DRV_LOG(ERR, "buffer number not match\n");
3647                         return I40E_ERR_PARAM;
3648                 }
3649                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3650                 mv_f[i].vlan_id = vlan;
3651                 i++;
3652         }
3653
3654         return I40E_SUCCESS;
3655 }
3656
3657 static int
3658 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3659 {
3660         int i, num;
3661         struct i40e_mac_filter *f;
3662         struct i40e_macvlan_filter *mv_f;
3663         int ret = I40E_SUCCESS;
3664
3665         if (vsi == NULL || vsi->mac_num == 0)
3666                 return I40E_ERR_PARAM;
3667
3668         /* Case that no vlan is set */
3669         if (vsi->vlan_num == 0)
3670                 num = vsi->mac_num;
3671         else
3672                 num = vsi->mac_num * vsi->vlan_num;
3673
3674         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3675         if (mv_f == NULL) {
3676                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3677                 return I40E_ERR_NO_MEMORY;
3678         }
3679
3680         i = 0;
3681         if (vsi->vlan_num == 0) {
3682                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3683                         (void)rte_memcpy(&mv_f[i].macaddr,
3684                                 &f->macaddr, ETH_ADDR_LEN);
3685                         mv_f[i].vlan_id = 0;
3686                         i++;
3687                 }
3688         } else {
3689                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3690                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3691                                         vsi->vlan_num, &f->macaddr);
3692                         if (ret != I40E_SUCCESS)
3693                                 goto DONE;
3694                         i += vsi->vlan_num;
3695                 }
3696         }
3697
3698         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3699 DONE:
3700         rte_free(mv_f);
3701
3702         return ret;
3703 }
3704
3705 int
3706 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3707 {
3708         struct i40e_macvlan_filter *mv_f;
3709         int mac_num;
3710         int ret = I40E_SUCCESS;
3711
3712         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3713                 return I40E_ERR_PARAM;
3714
3715         /* If it's already set, just return */
3716         if (i40e_find_vlan_filter(vsi,vlan))
3717                 return I40E_SUCCESS;
3718
3719         mac_num = vsi->mac_num;
3720
3721         if (mac_num == 0) {
3722                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3723                 return I40E_ERR_PARAM;
3724         }
3725
3726         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3727
3728         if (mv_f == NULL) {
3729                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3730                 return I40E_ERR_NO_MEMORY;
3731         }
3732
3733         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3734
3735         if (ret != I40E_SUCCESS)
3736                 goto DONE;
3737
3738         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3739
3740         if (ret != I40E_SUCCESS)
3741                 goto DONE;
3742
3743         i40e_set_vlan_filter(vsi, vlan, 1);
3744
3745         vsi->vlan_num++;
3746         ret = I40E_SUCCESS;
3747 DONE:
3748         rte_free(mv_f);
3749         return ret;
3750 }
3751
3752 int
3753 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3754 {
3755         struct i40e_macvlan_filter *mv_f;
3756         int mac_num;
3757         int ret = I40E_SUCCESS;
3758
3759         /**
3760          * Vlan 0 is the generic filter for untagged packets
3761          * and can't be removed.
3762          */
3763         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3764                 return I40E_ERR_PARAM;
3765
3766         /* If can't find it, just return */
3767         if (!i40e_find_vlan_filter(vsi, vlan))
3768                 return I40E_ERR_PARAM;
3769
3770         mac_num = vsi->mac_num;
3771
3772         if (mac_num == 0) {
3773                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3774                 return I40E_ERR_PARAM;
3775         }
3776
3777         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3778
3779         if (mv_f == NULL) {
3780                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3781                 return I40E_ERR_NO_MEMORY;
3782         }
3783
3784         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3785
3786         if (ret != I40E_SUCCESS)
3787                 goto DONE;
3788
3789         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3790
3791         if (ret != I40E_SUCCESS)
3792                 goto DONE;
3793
3794         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3795         if (vsi->vlan_num == 1) {
3796                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3797                 if (ret != I40E_SUCCESS)
3798                         goto DONE;
3799
3800                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3801                 if (ret != I40E_SUCCESS)
3802                         goto DONE;
3803         }
3804
3805         i40e_set_vlan_filter(vsi, vlan, 0);
3806
3807         vsi->vlan_num--;
3808         ret = I40E_SUCCESS;
3809 DONE:
3810         rte_free(mv_f);
3811         return ret;
3812 }
3813
3814 int
3815 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3816 {
3817         struct i40e_mac_filter *f;
3818         struct i40e_macvlan_filter *mv_f;
3819         int vlan_num;
3820         int ret = I40E_SUCCESS;
3821
3822         /* If it's add and we've config it, return */
3823         f = i40e_find_mac_filter(vsi, addr);
3824         if (f != NULL)
3825                 return I40E_SUCCESS;
3826
3827         /**
3828          * If vlan_num is 0, that's the first time to add mac,
3829          * set mask for vlan_id 0.
3830          */
3831         if (vsi->vlan_num == 0) {
3832                 i40e_set_vlan_filter(vsi, 0, 1);
3833                 vsi->vlan_num = 1;
3834         }
3835
3836         vlan_num = vsi->vlan_num;
3837
3838         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3839         if (mv_f == NULL) {
3840                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3841                 return I40E_ERR_NO_MEMORY;
3842         }
3843
3844         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3845         if (ret != I40E_SUCCESS)
3846                 goto DONE;
3847
3848         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3849         if (ret != I40E_SUCCESS)
3850                 goto DONE;
3851
3852         /* Add the mac addr into mac list */
3853         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3854         if (f == NULL) {
3855                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3856                 ret = I40E_ERR_NO_MEMORY;
3857                 goto DONE;
3858         }
3859         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3860         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3861         vsi->mac_num++;
3862
3863         ret = I40E_SUCCESS;
3864 DONE:
3865         rte_free(mv_f);
3866
3867         return ret;
3868 }
3869
3870 int
3871 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3872 {
3873         struct i40e_mac_filter *f;
3874         struct i40e_macvlan_filter *mv_f;
3875         int vlan_num;
3876         int ret = I40E_SUCCESS;
3877
3878         /* Can't find it, return an error */
3879         f = i40e_find_mac_filter(vsi, addr);
3880         if (f == NULL)
3881                 return I40E_ERR_PARAM;
3882
3883         vlan_num = vsi->vlan_num;
3884         if (vlan_num == 0) {
3885                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3886                 return I40E_ERR_PARAM;
3887         }
3888         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3889         if (mv_f == NULL) {
3890                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3891                 return I40E_ERR_NO_MEMORY;
3892         }
3893
3894         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3895         if (ret != I40E_SUCCESS)
3896                 goto DONE;
3897
3898         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3899         if (ret != I40E_SUCCESS)
3900                 goto DONE;
3901
3902         /* Remove the mac addr into mac list */
3903         TAILQ_REMOVE(&vsi->mac_list, f, next);
3904         rte_free(f);
3905         vsi->mac_num--;
3906
3907         ret = I40E_SUCCESS;
3908 DONE:
3909         rte_free(mv_f);
3910         return ret;
3911 }
3912
3913 /* Configure hash enable flags for RSS */
3914 static uint64_t
3915 i40e_config_hena(uint64_t flags)
3916 {
3917         uint64_t hena = 0;
3918
3919         if (!flags)
3920                 return hena;
3921
3922         if (flags & ETH_RSS_NONF_IPV4_UDP)
3923                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3924         if (flags & ETH_RSS_NONF_IPV4_TCP)
3925                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3926         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3927                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3928         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3929                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3930         if (flags & ETH_RSS_FRAG_IPV4)
3931                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3932         if (flags & ETH_RSS_NONF_IPV6_UDP)
3933                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3934         if (flags & ETH_RSS_NONF_IPV6_TCP)
3935                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3936         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3937                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3938         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3939                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3940         if (flags & ETH_RSS_FRAG_IPV6)
3941                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3942         if (flags & ETH_RSS_L2_PAYLOAD)
3943                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3944
3945         return hena;
3946 }
3947
3948 /* Parse the hash enable flags */
3949 static uint64_t
3950 i40e_parse_hena(uint64_t flags)
3951 {
3952         uint64_t rss_hf = 0;
3953
3954         if (!flags)
3955                 return rss_hf;
3956
3957         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3958                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3959         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3960                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3961         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3962                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3963         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3964                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3965         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3966                 rss_hf |= ETH_RSS_FRAG_IPV4;
3967         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3968                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3969         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3970                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3971         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3972                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3973         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3974                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3975         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3976                 rss_hf |= ETH_RSS_FRAG_IPV6;
3977         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3978                 rss_hf |= ETH_RSS_L2_PAYLOAD;
3979
3980         return rss_hf;
3981 }
3982
3983 /* Disable RSS */
3984 static void
3985 i40e_pf_disable_rss(struct i40e_pf *pf)
3986 {
3987         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3988         uint64_t hena;
3989
3990         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3991         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3992         hena &= ~I40E_RSS_HENA_ALL;
3993         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3994         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3995         I40E_WRITE_FLUSH(hw);
3996 }
3997
3998 static int
3999 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4000 {
4001         uint32_t *hash_key;
4002         uint8_t hash_key_len;
4003         uint64_t rss_hf;
4004         uint16_t i;
4005         uint64_t hena;
4006
4007         hash_key = (uint32_t *)(rss_conf->rss_key);
4008         hash_key_len = rss_conf->rss_key_len;
4009         if (hash_key != NULL && hash_key_len >=
4010                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4011                 /* Fill in RSS hash key */
4012                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4013                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4014         }
4015
4016         rss_hf = rss_conf->rss_hf;
4017         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4018         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4019         hena &= ~I40E_RSS_HENA_ALL;
4020         hena |= i40e_config_hena(rss_hf);
4021         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4022         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4023         I40E_WRITE_FLUSH(hw);
4024
4025         return 0;
4026 }
4027
4028 static int
4029 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4030                          struct rte_eth_rss_conf *rss_conf)
4031 {
4032         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4033         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4034         uint64_t hena;
4035
4036         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4037         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4038         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4039                 if (rss_hf != 0) /* Enable RSS */
4040                         return -EINVAL;
4041                 return 0; /* Nothing to do */
4042         }
4043         /* RSS enabled */
4044         if (rss_hf == 0) /* Disable RSS */
4045                 return -EINVAL;
4046
4047         return i40e_hw_rss_hash_set(hw, rss_conf);
4048 }
4049
4050 static int
4051 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4052                            struct rte_eth_rss_conf *rss_conf)
4053 {
4054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4056         uint64_t hena;
4057         uint16_t i;
4058
4059         if (hash_key != NULL) {
4060                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4061                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4062                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4063         }
4064         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4065         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4066         rss_conf->rss_hf = i40e_parse_hena(hena);
4067
4068         return 0;
4069 }
4070
4071 /* Configure RSS */
4072 static int
4073 i40e_pf_config_rss(struct i40e_pf *pf)
4074 {
4075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4076         struct rte_eth_rss_conf rss_conf;
4077         uint32_t i, lut = 0;
4078         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4079
4080         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4081                 if (j == num)
4082                         j = 0;
4083                 lut = (lut << 8) | (j & ((0x1 <<
4084                         hw->func_caps.rss_table_entry_width) - 1));
4085                 if ((i & 3) == 3)
4086                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4087         }
4088
4089         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4090         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4091                 i40e_pf_disable_rss(pf);
4092                 return 0;
4093         }
4094         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4095                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4096                 /* Calculate the default hash key */
4097                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4098                         rss_key_default[i] = (uint32_t)rte_rand();
4099                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4100                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4101                                                         sizeof(uint32_t);
4102         }
4103
4104         return i40e_hw_rss_hash_set(hw, &rss_conf);
4105 }
4106
4107 static int
4108 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4109 {
4110         if (!pf->dev_data->sriov.active) {
4111                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4112                 case ETH_MQ_RX_RSS:
4113                         i40e_pf_config_rss(pf);
4114                         break;
4115                 default:
4116                         i40e_pf_disable_rss(pf);
4117                         break;
4118                 }
4119         }
4120
4121         return 0;
4122 }