4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds */
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 static int eth_i40e_dev_init(\
110 __attribute__((unused)) struct eth_driver *eth_drv,
111 struct rte_eth_dev *eth_dev);
112 static int i40e_dev_configure(struct rte_eth_dev *dev);
113 static int i40e_dev_start(struct rte_eth_dev *dev);
114 static void i40e_dev_stop(struct rte_eth_dev *dev);
115 static void i40e_dev_close(struct rte_eth_dev *dev);
116 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
117 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
118 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
119 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
120 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
121 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
122 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
123 struct rte_eth_stats *stats);
124 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
125 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
129 static void i40e_dev_info_get(struct rte_eth_dev *dev,
130 struct rte_eth_dev_info *dev_info);
131 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
134 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
135 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
136 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
139 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
140 static int i40e_dev_led_on(struct rte_eth_dev *dev);
141 static int i40e_dev_led_off(struct rte_eth_dev *dev);
142 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
143 struct rte_eth_fc_conf *fc_conf);
144 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
145 struct rte_eth_pfc_conf *pfc_conf);
146 static void i40e_macaddr_add(struct rte_eth_dev *dev,
147 struct ether_addr *mac_addr,
150 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
151 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
152 struct rte_eth_rss_reta_entry64 *reta_conf,
154 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
155 struct rte_eth_rss_reta_entry64 *reta_conf,
158 static int i40e_get_cap(struct i40e_hw *hw);
159 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
160 static int i40e_pf_setup(struct i40e_pf *pf);
161 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
162 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
163 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
164 bool offset_loaded, uint64_t *offset, uint64_t *stat);
165 static void i40e_stat_update_48(struct i40e_hw *hw,
171 static void i40e_pf_config_irq0(struct i40e_hw *hw);
172 static void i40e_dev_interrupt_handler(
173 __rte_unused struct rte_intr_handle *handle, void *param);
174 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
175 uint32_t base, uint32_t num);
176 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
177 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
179 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
181 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
182 static int i40e_veb_release(struct i40e_veb *veb);
183 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
184 struct i40e_vsi *vsi);
185 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
186 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
187 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
188 struct i40e_macvlan_filter *mv_f,
190 struct ether_addr *addr);
191 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
192 struct i40e_macvlan_filter *mv_f,
195 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
196 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
197 struct rte_eth_rss_conf *rss_conf);
198 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
199 struct rte_eth_rss_conf *rss_conf);
200 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
201 struct rte_eth_udp_tunnel *udp_tunnel);
202 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
203 struct rte_eth_udp_tunnel *udp_tunnel);
204 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
205 struct rte_eth_ethertype_filter *filter,
207 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
208 enum rte_filter_op filter_op,
210 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
211 enum rte_filter_type filter_type,
212 enum rte_filter_op filter_op,
214 static void i40e_configure_registers(struct i40e_hw *hw);
215 static void i40e_hw_init(struct i40e_hw *hw);
217 static struct rte_pci_id pci_id_i40e_map[] = {
218 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
219 #include "rte_pci_dev_ids.h"
220 { .vendor_id = 0, /* sentinel */ },
223 static struct eth_dev_ops i40e_eth_dev_ops = {
224 .dev_configure = i40e_dev_configure,
225 .dev_start = i40e_dev_start,
226 .dev_stop = i40e_dev_stop,
227 .dev_close = i40e_dev_close,
228 .promiscuous_enable = i40e_dev_promiscuous_enable,
229 .promiscuous_disable = i40e_dev_promiscuous_disable,
230 .allmulticast_enable = i40e_dev_allmulticast_enable,
231 .allmulticast_disable = i40e_dev_allmulticast_disable,
232 .dev_set_link_up = i40e_dev_set_link_up,
233 .dev_set_link_down = i40e_dev_set_link_down,
234 .link_update = i40e_dev_link_update,
235 .stats_get = i40e_dev_stats_get,
236 .stats_reset = i40e_dev_stats_reset,
237 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
238 .dev_infos_get = i40e_dev_info_get,
239 .vlan_filter_set = i40e_vlan_filter_set,
240 .vlan_tpid_set = i40e_vlan_tpid_set,
241 .vlan_offload_set = i40e_vlan_offload_set,
242 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
243 .vlan_pvid_set = i40e_vlan_pvid_set,
244 .rx_queue_start = i40e_dev_rx_queue_start,
245 .rx_queue_stop = i40e_dev_rx_queue_stop,
246 .tx_queue_start = i40e_dev_tx_queue_start,
247 .tx_queue_stop = i40e_dev_tx_queue_stop,
248 .rx_queue_setup = i40e_dev_rx_queue_setup,
249 .rx_queue_release = i40e_dev_rx_queue_release,
250 .rx_queue_count = i40e_dev_rx_queue_count,
251 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
252 .tx_queue_setup = i40e_dev_tx_queue_setup,
253 .tx_queue_release = i40e_dev_tx_queue_release,
254 .dev_led_on = i40e_dev_led_on,
255 .dev_led_off = i40e_dev_led_off,
256 .flow_ctrl_set = i40e_flow_ctrl_set,
257 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
258 .mac_addr_add = i40e_macaddr_add,
259 .mac_addr_remove = i40e_macaddr_remove,
260 .reta_update = i40e_dev_rss_reta_update,
261 .reta_query = i40e_dev_rss_reta_query,
262 .rss_hash_update = i40e_dev_rss_hash_update,
263 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
264 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
265 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
266 .filter_ctrl = i40e_dev_filter_ctrl,
269 static struct eth_driver rte_i40e_pmd = {
271 .name = "rte_i40e_pmd",
272 .id_table = pci_id_i40e_map,
273 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
275 .eth_dev_init = eth_i40e_dev_init,
276 .dev_private_size = sizeof(struct i40e_adapter),
280 i40e_align_floor(int n)
284 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
288 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
289 struct rte_eth_link *link)
291 struct rte_eth_link *dst = link;
292 struct rte_eth_link *src = &(dev->data->dev_link);
294 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
295 *(uint64_t *)src) == 0)
302 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
303 struct rte_eth_link *link)
305 struct rte_eth_link *dst = &(dev->data->dev_link);
306 struct rte_eth_link *src = link;
308 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
309 *(uint64_t *)src) == 0)
316 * Driver initialization routine.
317 * Invoked once at EAL init time.
318 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
321 rte_i40e_pmd_init(const char *name __rte_unused,
322 const char *params __rte_unused)
324 PMD_INIT_FUNC_TRACE();
325 rte_eth_driver_register(&rte_i40e_pmd);
330 static struct rte_driver rte_i40e_driver = {
332 .init = rte_i40e_pmd_init,
335 PMD_REGISTER_DRIVER(rte_i40e_driver);
338 * Initialize registers for flexible payload, which should be set by NVM.
339 * This should be removed from code once it is fixed in NVM.
341 #ifndef I40E_GLQF_ORT
342 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
344 #ifndef I40E_GLQF_PIT
345 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
348 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
350 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
351 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
352 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
353 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
354 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
355 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
356 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
357 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
358 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
359 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
361 /* GLQF_PIT Registers */
362 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
363 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
367 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
368 struct rte_eth_dev *dev)
370 struct rte_pci_device *pci_dev;
371 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
372 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
373 struct i40e_vsi *vsi;
378 PMD_INIT_FUNC_TRACE();
380 dev->dev_ops = &i40e_eth_dev_ops;
381 dev->rx_pkt_burst = i40e_recv_pkts;
382 dev->tx_pkt_burst = i40e_xmit_pkts;
384 /* for secondary processes, we don't initialise any further as primary
385 * has already done this work. Only check we don't need a different
387 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
388 if (dev->data->scattered_rx)
389 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
392 pci_dev = dev->pci_dev;
393 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
394 pf->adapter->eth_dev = dev;
395 pf->dev_data = dev->data;
397 hw->back = I40E_PF_TO_ADAPTER(pf);
398 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
400 PMD_INIT_LOG(ERR, "Hardware is not available, "
401 "as address is NULL");
405 hw->vendor_id = pci_dev->id.vendor_id;
406 hw->device_id = pci_dev->id.device_id;
407 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
408 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
409 hw->bus.device = pci_dev->addr.devid;
410 hw->bus.func = pci_dev->addr.function;
412 /* Make sure all is clean before doing PF reset */
415 /* Initialize the hardware */
418 /* Reset here to make sure all is clean for each PF */
419 ret = i40e_pf_reset(hw);
421 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
425 /* Initialize the shared code (base driver) */
426 ret = i40e_init_shared_code(hw);
428 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
433 * To work around the NVM issue,initialize registers
434 * for flexible payload by software.
435 * It should be removed once issues are fixed in NVM.
437 i40e_flex_payload_reg_init(hw);
439 /* Initialize the parameters for adminq */
440 i40e_init_adminq_parameter(hw);
441 ret = i40e_init_adminq(hw);
442 if (ret != I40E_SUCCESS) {
443 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
446 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
447 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
448 hw->aq.api_maj_ver, hw->aq.api_min_ver,
449 ((hw->nvm.version >> 12) & 0xf),
450 ((hw->nvm.version >> 4) & 0xff),
451 (hw->nvm.version & 0xf), hw->nvm.eetrack);
454 ret = i40e_aq_stop_lldp(hw, true, NULL);
455 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
456 PMD_INIT_LOG(INFO, "Failed to stop lldp");
459 i40e_clear_pxe_mode(hw);
462 * On X710, performance number is far from the expectation on recent
463 * firmware versions. The fix for this issue may not be integrated in
464 * the following firmware version. So the workaround in software driver
465 * is needed. It needs to modify the initial values of 3 internal only
466 * registers. Note that the workaround can be removed when it is fixed
467 * in firmware in the future.
469 i40e_configure_registers(hw);
471 /* Get hw capabilities */
472 ret = i40e_get_cap(hw);
473 if (ret != I40E_SUCCESS) {
474 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
475 goto err_get_capabilities;
478 /* Initialize parameters for PF */
479 ret = i40e_pf_parameter_init(dev);
481 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
482 goto err_parameter_init;
485 /* Initialize the queue management */
486 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
488 PMD_INIT_LOG(ERR, "Failed to init queue pool");
489 goto err_qp_pool_init;
491 ret = i40e_res_pool_init(&pf->msix_pool, 1,
492 hw->func_caps.num_msix_vectors - 1);
494 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
495 goto err_msix_pool_init;
498 /* Initialize lan hmc */
499 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
500 hw->func_caps.num_rx_qp, 0, 0);
501 if (ret != I40E_SUCCESS) {
502 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
503 goto err_init_lan_hmc;
506 /* Configure lan hmc */
507 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
508 if (ret != I40E_SUCCESS) {
509 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
510 goto err_configure_lan_hmc;
513 /* Get and check the mac address */
514 i40e_get_mac_addr(hw, hw->mac.addr);
515 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
516 PMD_INIT_LOG(ERR, "mac address is not valid");
518 goto err_get_mac_addr;
520 /* Copy the permanent MAC address */
521 ether_addr_copy((struct ether_addr *) hw->mac.addr,
522 (struct ether_addr *) hw->mac.perm_addr);
524 /* Disable flow control */
525 hw->fc.requested_mode = I40E_FC_NONE;
526 i40e_set_fc(hw, &aq_fail, TRUE);
528 /* PF setup, which includes VSI setup */
529 ret = i40e_pf_setup(pf);
531 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
532 goto err_setup_pf_switch;
537 /* Disable double vlan by default */
538 i40e_vsi_config_double_vlan(vsi, FALSE);
540 if (!vsi->max_macaddrs)
541 len = ETHER_ADDR_LEN;
543 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
545 /* Should be after VSI initialized */
546 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
547 if (!dev->data->mac_addrs) {
548 PMD_INIT_LOG(ERR, "Failed to allocated memory "
549 "for storing mac address");
552 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
553 &dev->data->mac_addrs[0]);
555 /* initialize pf host driver to setup SRIOV resource if applicable */
556 i40e_pf_host_init(dev);
558 /* register callback func to eal lib */
559 rte_intr_callback_register(&(pci_dev->intr_handle),
560 i40e_dev_interrupt_handler, (void *)dev);
562 /* configure and enable device interrupt */
563 i40e_pf_config_irq0(hw);
564 i40e_pf_enable_irq0(hw);
566 /* enable uio intr after callback register */
567 rte_intr_enable(&(pci_dev->intr_handle));
572 i40e_vsi_release(pf->main_vsi);
575 err_configure_lan_hmc:
576 (void)i40e_shutdown_lan_hmc(hw);
578 i40e_res_pool_destroy(&pf->msix_pool);
580 i40e_res_pool_destroy(&pf->qp_pool);
583 err_get_capabilities:
584 (void)i40e_shutdown_adminq(hw);
590 i40e_dev_configure(struct rte_eth_dev *dev)
592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
593 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
596 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
597 ret = i40e_fdir_setup(pf);
598 if (ret != I40E_SUCCESS) {
599 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
602 ret = i40e_fdir_configure(dev);
604 PMD_DRV_LOG(ERR, "failed to configure fdir.");
608 i40e_fdir_teardown(pf);
610 ret = i40e_dev_init_vlan(dev);
615 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
616 * RSS setting have different requirements.
617 * General PMD driver call sequence are NIC init, configure,
618 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
619 * will try to lookup the VSI that specific queue belongs to if VMDQ
620 * applicable. So, VMDQ setting has to be done before
621 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
622 * For RSS setting, it will try to calculate actual configured RX queue
623 * number, which will be available after rx_queue_setup(). dev_start()
624 * function is good to place RSS setup.
626 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
627 ret = i40e_vmdq_setup(dev);
633 i40e_fdir_teardown(pf);
638 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
640 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
641 uint16_t msix_vect = vsi->msix_intr;
644 for (i = 0; i < vsi->nb_qps; i++) {
645 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
646 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
650 if (vsi->type != I40E_VSI_SRIOV) {
651 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
652 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
656 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
657 vsi->user_param + (msix_vect - 1);
659 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
661 I40E_WRITE_FLUSH(hw);
664 static inline uint16_t
665 i40e_calc_itr_interval(int16_t interval)
667 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
668 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
670 /* Convert to hardware count, as writing each 1 represents 2 us */
675 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
678 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
679 uint16_t msix_vect = vsi->msix_intr;
682 for (i = 0; i < vsi->nb_qps; i++)
683 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
685 /* Bind all RX queues to allocated MSIX interrupt */
686 for (i = 0; i < vsi->nb_qps; i++) {
687 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
688 I40E_QINT_RQCTL_ITR_INDX_MASK |
689 ((vsi->base_queue + i + 1) <<
690 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
691 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
692 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
694 if (i == vsi->nb_qps - 1)
695 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
696 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
699 /* Write first RX queue to Link list register as the head element */
700 if (vsi->type != I40E_VSI_SRIOV) {
702 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
704 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
706 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
707 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
709 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
710 msix_vect - 1), interval);
712 #ifndef I40E_GLINT_CTL
713 #define I40E_GLINT_CTL 0x0003F800
714 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
716 /* Disable auto-mask on enabling of all none-zero interrupt */
717 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
718 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
722 /* num_msix_vectors_vf needs to minus irq0 */
723 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
724 vsi->user_param + (msix_vect - 1);
726 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
727 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
728 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
731 I40E_WRITE_FLUSH(hw);
735 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
737 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
738 uint16_t interval = i40e_calc_itr_interval(\
739 RTE_LIBRTE_I40E_ITR_INTERVAL);
741 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
742 I40E_PFINT_DYN_CTLN_INTENA_MASK |
743 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
744 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
745 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
749 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
751 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
753 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
756 static inline uint8_t
757 i40e_parse_link_speed(uint16_t eth_link_speed)
759 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
761 switch (eth_link_speed) {
762 case ETH_LINK_SPEED_40G:
763 link_speed = I40E_LINK_SPEED_40GB;
765 case ETH_LINK_SPEED_20G:
766 link_speed = I40E_LINK_SPEED_20GB;
768 case ETH_LINK_SPEED_10G:
769 link_speed = I40E_LINK_SPEED_10GB;
771 case ETH_LINK_SPEED_1000:
772 link_speed = I40E_LINK_SPEED_1GB;
774 case ETH_LINK_SPEED_100:
775 link_speed = I40E_LINK_SPEED_100MB;
783 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
785 enum i40e_status_code status;
786 struct i40e_aq_get_phy_abilities_resp phy_ab;
787 struct i40e_aq_set_phy_config phy_conf;
788 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
789 I40E_AQ_PHY_FLAG_PAUSE_RX |
790 I40E_AQ_PHY_FLAG_LOW_POWER;
791 const uint8_t advt = I40E_LINK_SPEED_40GB |
792 I40E_LINK_SPEED_10GB |
793 I40E_LINK_SPEED_1GB |
794 I40E_LINK_SPEED_100MB;
797 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
802 memset(&phy_conf, 0, sizeof(phy_conf));
804 /* bits 0-2 use the values from get_phy_abilities_resp */
806 abilities |= phy_ab.abilities & mask;
808 /* update ablities and speed */
809 if (abilities & I40E_AQ_PHY_AN_ENABLED)
810 phy_conf.link_speed = advt;
812 phy_conf.link_speed = force_speed;
814 phy_conf.abilities = abilities;
816 /* use get_phy_abilities_resp value for the rest */
817 phy_conf.phy_type = phy_ab.phy_type;
818 phy_conf.eee_capability = phy_ab.eee_capability;
819 phy_conf.eeer = phy_ab.eeer_val;
820 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
822 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
823 phy_ab.abilities, phy_ab.link_speed);
824 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
825 phy_conf.abilities, phy_conf.link_speed);
827 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
835 i40e_apply_link_speed(struct rte_eth_dev *dev)
838 uint8_t abilities = 0;
839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
840 struct rte_eth_conf *conf = &dev->data->dev_conf;
842 speed = i40e_parse_link_speed(conf->link_speed);
843 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
844 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
845 abilities |= I40E_AQ_PHY_AN_ENABLED;
847 abilities |= I40E_AQ_PHY_LINK_ENABLED;
849 return i40e_phy_conf_link(hw, abilities, speed);
853 i40e_dev_start(struct rte_eth_dev *dev)
855 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
856 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
857 struct i40e_vsi *main_vsi = pf->main_vsi;
860 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
861 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
862 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
863 dev->data->dev_conf.link_duplex,
869 ret = i40e_dev_rxtx_init(pf);
870 if (ret != I40E_SUCCESS) {
871 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
875 /* Map queues with MSIX interrupt */
876 i40e_vsi_queues_bind_intr(main_vsi);
877 i40e_vsi_enable_queues_intr(main_vsi);
879 /* Map VMDQ VSI queues with MSIX interrupt */
880 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
881 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
882 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
885 /* enable FDIR MSIX interrupt */
886 if (pf->fdir.fdir_vsi) {
887 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
888 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
891 /* Enable all queues which have been configured */
892 ret = i40e_dev_switch_queues(pf, TRUE);
893 if (ret != I40E_SUCCESS) {
894 PMD_DRV_LOG(ERR, "Failed to enable VSI");
898 /* Enable receiving broadcast packets */
899 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
900 if (ret != I40E_SUCCESS)
901 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
903 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
904 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
906 if (ret != I40E_SUCCESS)
907 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
910 /* Apply link configure */
911 ret = i40e_apply_link_speed(dev);
912 if (I40E_SUCCESS != ret) {
913 PMD_DRV_LOG(ERR, "Fail to apply link setting");
920 i40e_dev_switch_queues(pf, FALSE);
921 i40e_dev_clear_queues(dev);
927 i40e_dev_stop(struct rte_eth_dev *dev)
929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
930 struct i40e_vsi *main_vsi = pf->main_vsi;
933 /* Disable all queues */
934 i40e_dev_switch_queues(pf, FALSE);
936 /* un-map queues with interrupt registers */
937 i40e_vsi_disable_queues_intr(main_vsi);
938 i40e_vsi_queues_unbind_intr(main_vsi);
940 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
941 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
942 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
945 if (pf->fdir.fdir_vsi) {
946 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
947 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
949 /* Clear all queues and release memory */
950 i40e_dev_clear_queues(dev);
953 i40e_dev_set_link_down(dev);
958 i40e_dev_close(struct rte_eth_dev *dev)
960 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
964 PMD_INIT_FUNC_TRACE();
968 /* Disable interrupt */
969 i40e_pf_disable_irq0(hw);
970 rte_intr_disable(&(dev->pci_dev->intr_handle));
972 /* shutdown and destroy the HMC */
973 i40e_shutdown_lan_hmc(hw);
975 /* release all the existing VSIs and VEBs */
976 i40e_fdir_teardown(pf);
977 i40e_vsi_release(pf->main_vsi);
979 /* shutdown the adminq */
980 i40e_aq_queue_shutdown(hw, true);
981 i40e_shutdown_adminq(hw);
983 i40e_res_pool_destroy(&pf->qp_pool);
984 i40e_res_pool_destroy(&pf->msix_pool);
986 /* force a PF reset to clean anything leftover */
987 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
988 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
989 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
990 I40E_WRITE_FLUSH(hw);
994 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
998 struct i40e_vsi *vsi = pf->main_vsi;
1001 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1003 if (status != I40E_SUCCESS)
1004 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1006 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1008 if (status != I40E_SUCCESS)
1009 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1014 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1016 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018 struct i40e_vsi *vsi = pf->main_vsi;
1021 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1023 if (status != I40E_SUCCESS)
1024 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1026 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1028 if (status != I40E_SUCCESS)
1029 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1033 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1035 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 struct i40e_vsi *vsi = pf->main_vsi;
1040 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1041 if (ret != I40E_SUCCESS)
1042 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1046 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050 struct i40e_vsi *vsi = pf->main_vsi;
1053 if (dev->data->promiscuous == 1)
1054 return; /* must remain in all_multicast mode */
1056 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1057 vsi->seid, FALSE, NULL);
1058 if (ret != I40E_SUCCESS)
1059 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1063 * Set device link up.
1066 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1068 /* re-apply link speed setting */
1069 return i40e_apply_link_speed(dev);
1073 * Set device link down.
1076 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1078 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1079 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1080 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1082 return i40e_phy_conf_link(hw, abilities, speed);
1086 i40e_dev_link_update(struct rte_eth_dev *dev,
1087 __rte_unused int wait_to_complete)
1089 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090 struct i40e_link_status link_status;
1091 struct rte_eth_link link, old;
1094 memset(&link, 0, sizeof(link));
1095 memset(&old, 0, sizeof(old));
1096 memset(&link_status, 0, sizeof(link_status));
1097 rte_i40e_dev_atomic_read_link_status(dev, &old);
1099 /* Get link status information from hardware */
1100 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1101 if (status != I40E_SUCCESS) {
1102 link.link_speed = ETH_LINK_SPEED_100;
1103 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1104 PMD_DRV_LOG(ERR, "Failed to get link info");
1108 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1110 if (!link.link_status)
1113 /* i40e uses full duplex only */
1114 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1116 /* Parse the link status */
1117 switch (link_status.link_speed) {
1118 case I40E_LINK_SPEED_100MB:
1119 link.link_speed = ETH_LINK_SPEED_100;
1121 case I40E_LINK_SPEED_1GB:
1122 link.link_speed = ETH_LINK_SPEED_1000;
1124 case I40E_LINK_SPEED_10GB:
1125 link.link_speed = ETH_LINK_SPEED_10G;
1127 case I40E_LINK_SPEED_20GB:
1128 link.link_speed = ETH_LINK_SPEED_20G;
1130 case I40E_LINK_SPEED_40GB:
1131 link.link_speed = ETH_LINK_SPEED_40G;
1134 link.link_speed = ETH_LINK_SPEED_100;
1139 rte_i40e_dev_atomic_write_link_status(dev, &link);
1140 if (link.link_status == old.link_status)
1146 /* Get all the statistics of a VSI */
1148 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1150 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1151 struct i40e_eth_stats *nes = &vsi->eth_stats;
1152 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1153 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1155 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1156 vsi->offset_loaded, &oes->rx_bytes,
1158 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1159 vsi->offset_loaded, &oes->rx_unicast,
1161 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1162 vsi->offset_loaded, &oes->rx_multicast,
1163 &nes->rx_multicast);
1164 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1165 vsi->offset_loaded, &oes->rx_broadcast,
1166 &nes->rx_broadcast);
1167 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1168 &oes->rx_discards, &nes->rx_discards);
1169 /* GLV_REPC not supported */
1170 /* GLV_RMPC not supported */
1171 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1172 &oes->rx_unknown_protocol,
1173 &nes->rx_unknown_protocol);
1174 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1175 vsi->offset_loaded, &oes->tx_bytes,
1177 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1178 vsi->offset_loaded, &oes->tx_unicast,
1180 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1181 vsi->offset_loaded, &oes->tx_multicast,
1182 &nes->tx_multicast);
1183 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1184 vsi->offset_loaded, &oes->tx_broadcast,
1185 &nes->tx_broadcast);
1186 /* GLV_TDPC not supported */
1187 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1188 &oes->tx_errors, &nes->tx_errors);
1189 vsi->offset_loaded = true;
1191 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1193 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1194 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1195 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1196 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1197 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1198 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1199 nes->rx_unknown_protocol);
1200 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1201 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1202 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1203 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1204 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1205 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1206 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1210 /* Get all statistics of a port */
1212 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1218 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1220 /* Get statistics of struct i40e_eth_stats */
1221 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1222 I40E_GLPRT_GORCL(hw->port),
1223 pf->offset_loaded, &os->eth.rx_bytes,
1225 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1226 I40E_GLPRT_UPRCL(hw->port),
1227 pf->offset_loaded, &os->eth.rx_unicast,
1228 &ns->eth.rx_unicast);
1229 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1230 I40E_GLPRT_MPRCL(hw->port),
1231 pf->offset_loaded, &os->eth.rx_multicast,
1232 &ns->eth.rx_multicast);
1233 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1234 I40E_GLPRT_BPRCL(hw->port),
1235 pf->offset_loaded, &os->eth.rx_broadcast,
1236 &ns->eth.rx_broadcast);
1237 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1238 pf->offset_loaded, &os->eth.rx_discards,
1239 &ns->eth.rx_discards);
1240 /* GLPRT_REPC not supported */
1241 /* GLPRT_RMPC not supported */
1242 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1244 &os->eth.rx_unknown_protocol,
1245 &ns->eth.rx_unknown_protocol);
1246 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1247 I40E_GLPRT_GOTCL(hw->port),
1248 pf->offset_loaded, &os->eth.tx_bytes,
1250 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1251 I40E_GLPRT_UPTCL(hw->port),
1252 pf->offset_loaded, &os->eth.tx_unicast,
1253 &ns->eth.tx_unicast);
1254 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1255 I40E_GLPRT_MPTCL(hw->port),
1256 pf->offset_loaded, &os->eth.tx_multicast,
1257 &ns->eth.tx_multicast);
1258 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1259 I40E_GLPRT_BPTCL(hw->port),
1260 pf->offset_loaded, &os->eth.tx_broadcast,
1261 &ns->eth.tx_broadcast);
1262 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1263 pf->offset_loaded, &os->eth.tx_discards,
1264 &ns->eth.tx_discards);
1265 /* GLPRT_TEPC not supported */
1267 /* additional port specific stats */
1268 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1269 pf->offset_loaded, &os->tx_dropped_link_down,
1270 &ns->tx_dropped_link_down);
1271 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1272 pf->offset_loaded, &os->crc_errors,
1274 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1275 pf->offset_loaded, &os->illegal_bytes,
1276 &ns->illegal_bytes);
1277 /* GLPRT_ERRBC not supported */
1278 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1279 pf->offset_loaded, &os->mac_local_faults,
1280 &ns->mac_local_faults);
1281 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1282 pf->offset_loaded, &os->mac_remote_faults,
1283 &ns->mac_remote_faults);
1284 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1285 pf->offset_loaded, &os->rx_length_errors,
1286 &ns->rx_length_errors);
1287 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1288 pf->offset_loaded, &os->link_xon_rx,
1290 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1291 pf->offset_loaded, &os->link_xoff_rx,
1293 for (i = 0; i < 8; i++) {
1294 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1296 &os->priority_xon_rx[i],
1297 &ns->priority_xon_rx[i]);
1298 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1300 &os->priority_xoff_rx[i],
1301 &ns->priority_xoff_rx[i]);
1303 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1304 pf->offset_loaded, &os->link_xon_tx,
1306 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1307 pf->offset_loaded, &os->link_xoff_tx,
1309 for (i = 0; i < 8; i++) {
1310 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1312 &os->priority_xon_tx[i],
1313 &ns->priority_xon_tx[i]);
1314 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1316 &os->priority_xoff_tx[i],
1317 &ns->priority_xoff_tx[i]);
1318 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1320 &os->priority_xon_2_xoff[i],
1321 &ns->priority_xon_2_xoff[i]);
1323 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1324 I40E_GLPRT_PRC64L(hw->port),
1325 pf->offset_loaded, &os->rx_size_64,
1327 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1328 I40E_GLPRT_PRC127L(hw->port),
1329 pf->offset_loaded, &os->rx_size_127,
1331 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1332 I40E_GLPRT_PRC255L(hw->port),
1333 pf->offset_loaded, &os->rx_size_255,
1335 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1336 I40E_GLPRT_PRC511L(hw->port),
1337 pf->offset_loaded, &os->rx_size_511,
1339 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1340 I40E_GLPRT_PRC1023L(hw->port),
1341 pf->offset_loaded, &os->rx_size_1023,
1343 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1344 I40E_GLPRT_PRC1522L(hw->port),
1345 pf->offset_loaded, &os->rx_size_1522,
1347 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1348 I40E_GLPRT_PRC9522L(hw->port),
1349 pf->offset_loaded, &os->rx_size_big,
1351 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1352 pf->offset_loaded, &os->rx_undersize,
1354 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1355 pf->offset_loaded, &os->rx_fragments,
1357 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1358 pf->offset_loaded, &os->rx_oversize,
1360 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1361 pf->offset_loaded, &os->rx_jabber,
1363 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1364 I40E_GLPRT_PTC64L(hw->port),
1365 pf->offset_loaded, &os->tx_size_64,
1367 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1368 I40E_GLPRT_PTC127L(hw->port),
1369 pf->offset_loaded, &os->tx_size_127,
1371 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1372 I40E_GLPRT_PTC255L(hw->port),
1373 pf->offset_loaded, &os->tx_size_255,
1375 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1376 I40E_GLPRT_PTC511L(hw->port),
1377 pf->offset_loaded, &os->tx_size_511,
1379 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1380 I40E_GLPRT_PTC1023L(hw->port),
1381 pf->offset_loaded, &os->tx_size_1023,
1383 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1384 I40E_GLPRT_PTC1522L(hw->port),
1385 pf->offset_loaded, &os->tx_size_1522,
1387 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1388 I40E_GLPRT_PTC9522L(hw->port),
1389 pf->offset_loaded, &os->tx_size_big,
1391 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1393 &os->fd_sb_match, &ns->fd_sb_match);
1394 /* GLPRT_MSPDC not supported */
1395 /* GLPRT_XEC not supported */
1397 pf->offset_loaded = true;
1400 i40e_update_vsi_stats(pf->main_vsi);
1402 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1403 ns->eth.rx_broadcast;
1404 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1405 ns->eth.tx_broadcast;
1406 stats->ibytes = ns->eth.rx_bytes;
1407 stats->obytes = ns->eth.tx_bytes;
1408 stats->oerrors = ns->eth.tx_errors;
1409 stats->imcasts = ns->eth.rx_multicast;
1410 stats->fdirmatch = ns->fd_sb_match;
1413 stats->ibadcrc = ns->crc_errors;
1414 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1415 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1416 stats->imissed = ns->eth.rx_discards;
1417 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1419 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1420 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1421 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1422 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1423 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1424 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1425 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1426 ns->eth.rx_unknown_protocol);
1427 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1428 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1429 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1430 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1431 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1432 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1434 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1435 ns->tx_dropped_link_down);
1436 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1437 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1439 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1440 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1441 ns->mac_local_faults);
1442 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1443 ns->mac_remote_faults);
1444 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1445 ns->rx_length_errors);
1446 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1447 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1448 for (i = 0; i < 8; i++) {
1449 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1450 i, ns->priority_xon_rx[i]);
1451 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1452 i, ns->priority_xoff_rx[i]);
1454 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1455 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1456 for (i = 0; i < 8; i++) {
1457 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1458 i, ns->priority_xon_tx[i]);
1459 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1460 i, ns->priority_xoff_tx[i]);
1461 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1462 i, ns->priority_xon_2_xoff[i]);
1464 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1465 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1466 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1467 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1468 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1469 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1470 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1471 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1472 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1473 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1474 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1475 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1476 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1477 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1478 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1479 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1480 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1481 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1482 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1483 ns->mac_short_packet_dropped);
1484 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1485 ns->checksum_error);
1486 PMD_DRV_LOG(DEBUG, "fdir_match: %lu", ns->fd_sb_match);
1487 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1490 /* Reset the statistics */
1492 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1496 /* It results in reloading the start point of each counter */
1497 pf->offset_loaded = false;
1501 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1502 __rte_unused uint16_t queue_id,
1503 __rte_unused uint8_t stat_idx,
1504 __rte_unused uint8_t is_rx)
1506 PMD_INIT_FUNC_TRACE();
1512 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1514 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515 struct i40e_vsi *vsi = pf->main_vsi;
1517 dev_info->max_rx_queues = vsi->nb_qps;
1518 dev_info->max_tx_queues = vsi->nb_qps;
1519 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1520 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1521 dev_info->max_mac_addrs = vsi->max_macaddrs;
1522 dev_info->max_vfs = dev->pci_dev->max_vfs;
1523 dev_info->rx_offload_capa =
1524 DEV_RX_OFFLOAD_VLAN_STRIP |
1525 DEV_RX_OFFLOAD_IPV4_CKSUM |
1526 DEV_RX_OFFLOAD_UDP_CKSUM |
1527 DEV_RX_OFFLOAD_TCP_CKSUM;
1528 dev_info->tx_offload_capa =
1529 DEV_TX_OFFLOAD_VLAN_INSERT |
1530 DEV_TX_OFFLOAD_IPV4_CKSUM |
1531 DEV_TX_OFFLOAD_UDP_CKSUM |
1532 DEV_TX_OFFLOAD_TCP_CKSUM |
1533 DEV_TX_OFFLOAD_SCTP_CKSUM |
1534 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1535 dev_info->reta_size = pf->hash_lut_size;
1536 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1538 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1540 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1541 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1542 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1544 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1548 dev_info->default_txconf = (struct rte_eth_txconf) {
1550 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1551 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1552 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1554 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1555 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1556 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1557 ETH_TXQ_FLAGS_NOOFFLOADS,
1560 if (pf->flags | I40E_FLAG_VMDQ) {
1561 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1562 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1563 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1564 pf->max_nb_vmdq_vsi;
1565 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1566 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1567 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1572 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1575 struct i40e_vsi *vsi = pf->main_vsi;
1576 PMD_INIT_FUNC_TRACE();
1579 return i40e_vsi_add_vlan(vsi, vlan_id);
1581 return i40e_vsi_delete_vlan(vsi, vlan_id);
1585 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1586 __rte_unused uint16_t tpid)
1588 PMD_INIT_FUNC_TRACE();
1592 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1595 struct i40e_vsi *vsi = pf->main_vsi;
1597 if (mask & ETH_VLAN_STRIP_MASK) {
1598 /* Enable or disable VLAN stripping */
1599 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1600 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1602 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1605 if (mask & ETH_VLAN_EXTEND_MASK) {
1606 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1607 i40e_vsi_config_double_vlan(vsi, TRUE);
1609 i40e_vsi_config_double_vlan(vsi, FALSE);
1614 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1615 __rte_unused uint16_t queue,
1616 __rte_unused int on)
1618 PMD_INIT_FUNC_TRACE();
1622 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1624 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625 struct i40e_vsi *vsi = pf->main_vsi;
1626 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1627 struct i40e_vsi_vlan_pvid_info info;
1629 memset(&info, 0, sizeof(info));
1632 info.config.pvid = pvid;
1634 info.config.reject.tagged =
1635 data->dev_conf.txmode.hw_vlan_reject_tagged;
1636 info.config.reject.untagged =
1637 data->dev_conf.txmode.hw_vlan_reject_untagged;
1640 return i40e_vsi_vlan_pvid_set(vsi, &info);
1644 i40e_dev_led_on(struct rte_eth_dev *dev)
1646 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647 uint32_t mode = i40e_led_get(hw);
1650 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1656 i40e_dev_led_off(struct rte_eth_dev *dev)
1658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659 uint32_t mode = i40e_led_get(hw);
1662 i40e_led_set(hw, 0, false);
1668 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1669 __rte_unused struct rte_eth_fc_conf *fc_conf)
1671 PMD_INIT_FUNC_TRACE();
1677 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1678 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1680 PMD_INIT_FUNC_TRACE();
1685 /* Add a MAC address, and update filters */
1687 i40e_macaddr_add(struct rte_eth_dev *dev,
1688 struct ether_addr *mac_addr,
1689 __rte_unused uint32_t index,
1692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1693 struct i40e_mac_filter_info mac_filter;
1694 struct i40e_vsi *vsi;
1697 /* If VMDQ not enabled or configured, return */
1698 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1699 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1700 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1705 if (pool > pf->nb_cfg_vmdq_vsi) {
1706 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1707 pool, pf->nb_cfg_vmdq_vsi);
1711 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1712 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1717 vsi = pf->vmdq[pool - 1].vsi;
1719 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1720 if (ret != I40E_SUCCESS) {
1721 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1726 /* Remove a MAC address, and update filters */
1728 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1731 struct i40e_vsi *vsi;
1732 struct rte_eth_dev_data *data = dev->data;
1733 struct ether_addr *macaddr;
1738 macaddr = &(data->mac_addrs[index]);
1740 pool_sel = dev->data->mac_pool_sel[index];
1742 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1743 if (pool_sel & (1ULL << i)) {
1747 /* No VMDQ pool enabled or configured */
1748 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1749 (i > pf->nb_cfg_vmdq_vsi)) {
1750 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1754 vsi = pf->vmdq[i - 1].vsi;
1756 ret = i40e_vsi_delete_mac(vsi, macaddr);
1759 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1766 /* Set perfect match or hash match of MAC and VLAN for a VF */
1768 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1769 struct rte_eth_mac_filter *filter,
1773 struct i40e_mac_filter_info mac_filter;
1774 struct ether_addr old_mac;
1775 struct ether_addr *new_mac;
1776 struct i40e_pf_vf *vf = NULL;
1781 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1784 hw = I40E_PF_TO_HW(pf);
1786 if (filter == NULL) {
1787 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1791 new_mac = &filter->mac_addr;
1793 if (is_zero_ether_addr(new_mac)) {
1794 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1798 vf_id = filter->dst_id;
1800 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1801 PMD_DRV_LOG(ERR, "Invalid argument.");
1804 vf = &pf->vfs[vf_id];
1806 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1807 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1812 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1813 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1815 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1818 mac_filter.filter_type = filter->filter_type;
1819 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1820 if (ret != I40E_SUCCESS) {
1821 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1824 ether_addr_copy(new_mac, &pf->dev_addr);
1826 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1828 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1829 if (ret != I40E_SUCCESS) {
1830 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1834 /* Clear device address as it has been removed */
1835 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1836 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1842 /* MAC filter handle */
1844 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1847 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1848 struct rte_eth_mac_filter *filter;
1849 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1850 int ret = I40E_NOT_SUPPORTED;
1852 filter = (struct rte_eth_mac_filter *)(arg);
1854 switch (filter_op) {
1855 case RTE_ETH_FILTER_NOP:
1858 case RTE_ETH_FILTER_ADD:
1859 i40e_pf_disable_irq0(hw);
1861 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1862 i40e_pf_enable_irq0(hw);
1864 case RTE_ETH_FILTER_DELETE:
1865 i40e_pf_disable_irq0(hw);
1867 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1868 i40e_pf_enable_irq0(hw);
1871 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1872 ret = I40E_ERR_PARAM;
1880 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1881 struct rte_eth_rss_reta_entry64 *reta_conf,
1884 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1887 uint16_t i, j, lut_size = pf->hash_lut_size;
1888 uint16_t idx, shift;
1891 if (reta_size != lut_size ||
1892 reta_size > ETH_RSS_RETA_SIZE_512) {
1893 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1894 "(%d) doesn't match the number hardware can supported "
1895 "(%d)\n", reta_size, lut_size);
1899 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1900 idx = i / RTE_RETA_GROUP_SIZE;
1901 shift = i % RTE_RETA_GROUP_SIZE;
1902 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1906 if (mask == I40E_4_BIT_MASK)
1909 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1910 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1911 if (mask & (0x1 << j))
1912 lut |= reta_conf[idx].reta[shift + j] <<
1915 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1917 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1924 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1925 struct rte_eth_rss_reta_entry64 *reta_conf,
1928 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1929 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931 uint16_t i, j, lut_size = pf->hash_lut_size;
1932 uint16_t idx, shift;
1935 if (reta_size != lut_size ||
1936 reta_size > ETH_RSS_RETA_SIZE_512) {
1937 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1938 "(%d) doesn't match the number hardware can supported "
1939 "(%d)\n", reta_size, lut_size);
1943 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1944 idx = i / RTE_RETA_GROUP_SIZE;
1945 shift = i % RTE_RETA_GROUP_SIZE;
1946 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1951 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1952 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1953 if (mask & (0x1 << j))
1954 reta_conf[idx].reta[shift + j] = ((lut >>
1955 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1963 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1964 * @hw: pointer to the HW structure
1965 * @mem: pointer to mem struct to fill out
1966 * @size: size of memory requested
1967 * @alignment: what to align the allocation to
1969 enum i40e_status_code
1970 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1971 struct i40e_dma_mem *mem,
1975 static uint64_t id = 0;
1976 const struct rte_memzone *mz = NULL;
1977 char z_name[RTE_MEMZONE_NAMESIZE];
1980 return I40E_ERR_PARAM;
1983 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1984 #ifdef RTE_LIBRTE_XEN_DOM0
1985 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1988 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1991 return I40E_ERR_NO_MEMORY;
1996 #ifdef RTE_LIBRTE_XEN_DOM0
1997 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1999 mem->pa = mz->phys_addr;
2002 return I40E_SUCCESS;
2006 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2007 * @hw: pointer to the HW structure
2008 * @mem: ptr to mem struct to free
2010 enum i40e_status_code
2011 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2012 struct i40e_dma_mem *mem)
2014 if (!mem || !mem->va)
2015 return I40E_ERR_PARAM;
2020 return I40E_SUCCESS;
2024 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2025 * @hw: pointer to the HW structure
2026 * @mem: pointer to mem struct to fill out
2027 * @size: size of memory requested
2029 enum i40e_status_code
2030 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2031 struct i40e_virt_mem *mem,
2035 return I40E_ERR_PARAM;
2038 mem->va = rte_zmalloc("i40e", size, 0);
2041 return I40E_SUCCESS;
2043 return I40E_ERR_NO_MEMORY;
2047 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2048 * @hw: pointer to the HW structure
2049 * @mem: pointer to mem struct to free
2051 enum i40e_status_code
2052 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2053 struct i40e_virt_mem *mem)
2056 return I40E_ERR_PARAM;
2061 return I40E_SUCCESS;
2065 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2067 rte_spinlock_init(&sp->spinlock);
2071 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2073 rte_spinlock_lock(&sp->spinlock);
2077 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2079 rte_spinlock_unlock(&sp->spinlock);
2083 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2089 * Get the hardware capabilities, which will be parsed
2090 * and saved into struct i40e_hw.
2093 i40e_get_cap(struct i40e_hw *hw)
2095 struct i40e_aqc_list_capabilities_element_resp *buf;
2096 uint16_t len, size = 0;
2099 /* Calculate a huge enough buff for saving response data temporarily */
2100 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2101 I40E_MAX_CAP_ELE_NUM;
2102 buf = rte_zmalloc("i40e", len, 0);
2104 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2105 return I40E_ERR_NO_MEMORY;
2108 /* Get, parse the capabilities and save it to hw */
2109 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2110 i40e_aqc_opc_list_func_capabilities, NULL);
2111 if (ret != I40E_SUCCESS)
2112 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2114 /* Free the temporary buffer after being used */
2121 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2123 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2125 uint16_t sum_queues = 0, sum_vsis, left_queues;
2127 /* First check if FW support SRIOV */
2128 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2129 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2133 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2134 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2135 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2136 /* Allocate queues for pf */
2137 if (hw->func_caps.rss) {
2138 pf->flags |= I40E_FLAG_RSS;
2139 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2140 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2141 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2144 sum_queues = pf->lan_nb_qps;
2145 /* Default VSI is not counted in */
2147 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2149 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2150 pf->flags |= I40E_FLAG_SRIOV;
2151 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2152 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2153 PMD_INIT_LOG(ERR, "Config VF number %u, "
2154 "max supported %u.",
2155 dev->pci_dev->max_vfs,
2156 hw->func_caps.num_vfs);
2159 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2160 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2161 "max support %u queues.",
2162 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2165 pf->vf_num = dev->pci_dev->max_vfs;
2166 sum_queues += pf->vf_nb_qps * pf->vf_num;
2167 sum_vsis += pf->vf_num;
2168 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2169 pf->vf_num, pf->vf_nb_qps);
2173 if (hw->func_caps.vmdq) {
2174 pf->flags |= I40E_FLAG_VMDQ;
2175 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2176 pf->max_nb_vmdq_vsi = 1;
2178 * If VMDQ available, assume a single VSI can be created. Will adjust
2181 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2182 sum_vsis += pf->max_nb_vmdq_vsi;
2184 pf->vmdq_nb_qps = 0;
2185 pf->max_nb_vmdq_vsi = 0;
2187 pf->nb_cfg_vmdq_vsi = 0;
2189 if (hw->func_caps.fd) {
2190 pf->flags |= I40E_FLAG_FDIR;
2191 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2193 * Each flow director consumes one VSI and one queue,
2194 * but can't calculate out predictably here.
2198 if (sum_vsis > pf->max_num_vsi ||
2199 sum_queues > hw->func_caps.num_rx_qp) {
2200 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2201 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2202 pf->max_num_vsi, sum_vsis);
2203 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2204 hw->func_caps.num_rx_qp, sum_queues);
2208 /* Adjust VMDQ setting to support as many VMs as possible */
2209 if (pf->flags & I40E_FLAG_VMDQ) {
2210 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2212 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2213 pf->max_num_vsi - sum_vsis);
2215 /* Limit the max VMDQ number that rte_ether that can support */
2216 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2219 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2220 pf->max_nb_vmdq_vsi);
2221 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2224 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2226 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2227 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2228 sum_vsis, hw->func_caps.num_msix_vectors);
2231 return I40E_SUCCESS;
2235 i40e_pf_get_switch_config(struct i40e_pf *pf)
2237 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2238 struct i40e_aqc_get_switch_config_resp *switch_config;
2239 struct i40e_aqc_switch_config_element_resp *element;
2240 uint16_t start_seid = 0, num_reported;
2243 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2244 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2245 if (!switch_config) {
2246 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2250 /* Get the switch configurations */
2251 ret = i40e_aq_get_switch_config(hw, switch_config,
2252 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2253 if (ret != I40E_SUCCESS) {
2254 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2257 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2258 if (num_reported != 1) { /* The number should be 1 */
2259 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2263 /* Parse the switch configuration elements */
2264 element = &(switch_config->element[0]);
2265 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2266 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2267 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2269 PMD_DRV_LOG(INFO, "Unknown element type");
2272 rte_free(switch_config);
2278 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2281 struct pool_entry *entry;
2283 if (pool == NULL || num == 0)
2286 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2287 if (entry == NULL) {
2288 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2292 /* queue heap initialize */
2293 pool->num_free = num;
2294 pool->num_alloc = 0;
2296 LIST_INIT(&pool->alloc_list);
2297 LIST_INIT(&pool->free_list);
2299 /* Initialize element */
2303 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2308 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2310 struct pool_entry *entry;
2315 LIST_FOREACH(entry, &pool->alloc_list, next) {
2316 LIST_REMOVE(entry, next);
2320 LIST_FOREACH(entry, &pool->free_list, next) {
2321 LIST_REMOVE(entry, next);
2326 pool->num_alloc = 0;
2328 LIST_INIT(&pool->alloc_list);
2329 LIST_INIT(&pool->free_list);
2333 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2336 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2337 uint32_t pool_offset;
2341 PMD_DRV_LOG(ERR, "Invalid parameter");
2345 pool_offset = base - pool->base;
2346 /* Lookup in alloc list */
2347 LIST_FOREACH(entry, &pool->alloc_list, next) {
2348 if (entry->base == pool_offset) {
2349 valid_entry = entry;
2350 LIST_REMOVE(entry, next);
2355 /* Not find, return */
2356 if (valid_entry == NULL) {
2357 PMD_DRV_LOG(ERR, "Failed to find entry");
2362 * Found it, move it to free list and try to merge.
2363 * In order to make merge easier, always sort it by qbase.
2364 * Find adjacent prev and last entries.
2367 LIST_FOREACH(entry, &pool->free_list, next) {
2368 if (entry->base > valid_entry->base) {
2376 /* Try to merge with next one*/
2378 /* Merge with next one */
2379 if (valid_entry->base + valid_entry->len == next->base) {
2380 next->base = valid_entry->base;
2381 next->len += valid_entry->len;
2382 rte_free(valid_entry);
2389 /* Merge with previous one */
2390 if (prev->base + prev->len == valid_entry->base) {
2391 prev->len += valid_entry->len;
2392 /* If it merge with next one, remove next node */
2394 LIST_REMOVE(valid_entry, next);
2395 rte_free(valid_entry);
2397 rte_free(valid_entry);
2403 /* Not find any entry to merge, insert */
2406 LIST_INSERT_AFTER(prev, valid_entry, next);
2407 else if (next != NULL)
2408 LIST_INSERT_BEFORE(next, valid_entry, next);
2409 else /* It's empty list, insert to head */
2410 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2413 pool->num_free += valid_entry->len;
2414 pool->num_alloc -= valid_entry->len;
2420 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2423 struct pool_entry *entry, *valid_entry;
2425 if (pool == NULL || num == 0) {
2426 PMD_DRV_LOG(ERR, "Invalid parameter");
2430 if (pool->num_free < num) {
2431 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2432 num, pool->num_free);
2437 /* Lookup in free list and find most fit one */
2438 LIST_FOREACH(entry, &pool->free_list, next) {
2439 if (entry->len >= num) {
2441 if (entry->len == num) {
2442 valid_entry = entry;
2445 if (valid_entry == NULL || valid_entry->len > entry->len)
2446 valid_entry = entry;
2450 /* Not find one to satisfy the request, return */
2451 if (valid_entry == NULL) {
2452 PMD_DRV_LOG(ERR, "No valid entry found");
2456 * The entry have equal queue number as requested,
2457 * remove it from alloc_list.
2459 if (valid_entry->len == num) {
2460 LIST_REMOVE(valid_entry, next);
2463 * The entry have more numbers than requested,
2464 * create a new entry for alloc_list and minus its
2465 * queue base and number in free_list.
2467 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2468 if (entry == NULL) {
2469 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2473 entry->base = valid_entry->base;
2475 valid_entry->base += num;
2476 valid_entry->len -= num;
2477 valid_entry = entry;
2480 /* Insert it into alloc list, not sorted */
2481 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2483 pool->num_free -= valid_entry->len;
2484 pool->num_alloc += valid_entry->len;
2486 return (valid_entry->base + pool->base);
2490 * bitmap_is_subset - Check whether src2 is subset of src1
2493 bitmap_is_subset(uint8_t src1, uint8_t src2)
2495 return !((src1 ^ src2) & src2);
2499 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2501 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2503 /* If DCB is not supported, only default TC is supported */
2504 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2505 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2509 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2510 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2511 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2515 return I40E_SUCCESS;
2519 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2520 struct i40e_vsi_vlan_pvid_info *info)
2523 struct i40e_vsi_context ctxt;
2524 uint8_t vlan_flags = 0;
2527 if (vsi == NULL || info == NULL) {
2528 PMD_DRV_LOG(ERR, "invalid parameters");
2529 return I40E_ERR_PARAM;
2533 vsi->info.pvid = info->config.pvid;
2535 * If insert pvid is enabled, only tagged pkts are
2536 * allowed to be sent out.
2538 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2539 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2542 if (info->config.reject.tagged == 0)
2543 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2545 if (info->config.reject.untagged == 0)
2546 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2548 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2549 I40E_AQ_VSI_PVLAN_MODE_MASK);
2550 vsi->info.port_vlan_flags |= vlan_flags;
2551 vsi->info.valid_sections =
2552 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2553 memset(&ctxt, 0, sizeof(ctxt));
2554 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2555 ctxt.seid = vsi->seid;
2557 hw = I40E_VSI_TO_HW(vsi);
2558 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2559 if (ret != I40E_SUCCESS)
2560 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2566 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2568 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2570 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2572 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2573 if (ret != I40E_SUCCESS)
2577 PMD_DRV_LOG(ERR, "seid not valid");
2581 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2582 tc_bw_data.tc_valid_bits = enabled_tcmap;
2583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2584 tc_bw_data.tc_bw_credits[i] =
2585 (enabled_tcmap & (1 << i)) ? 1 : 0;
2587 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2588 if (ret != I40E_SUCCESS) {
2589 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2593 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2594 sizeof(vsi->info.qs_handle));
2595 return I40E_SUCCESS;
2599 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2600 struct i40e_aqc_vsi_properties_data *info,
2601 uint8_t enabled_tcmap)
2603 int ret, total_tc = 0, i;
2604 uint16_t qpnum_per_tc, bsf, qp_idx;
2606 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2607 if (ret != I40E_SUCCESS)
2610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2611 if (enabled_tcmap & (1 << i))
2613 vsi->enabled_tc = enabled_tcmap;
2615 /* Number of queues per enabled TC */
2616 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2617 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2618 bsf = rte_bsf32(qpnum_per_tc);
2620 /* Adjust the queue number to actual queues that can be applied */
2621 vsi->nb_qps = qpnum_per_tc * total_tc;
2624 * Configure TC and queue mapping parameters, for enabled TC,
2625 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2626 * default queue will serve it.
2629 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2630 if (vsi->enabled_tc & (1 << i)) {
2631 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2632 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2633 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2634 qp_idx += qpnum_per_tc;
2636 info->tc_mapping[i] = 0;
2639 /* Associate queue number with VSI */
2640 if (vsi->type == I40E_VSI_SRIOV) {
2641 info->mapping_flags |=
2642 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2643 for (i = 0; i < vsi->nb_qps; i++)
2644 info->queue_mapping[i] =
2645 rte_cpu_to_le_16(vsi->base_queue + i);
2647 info->mapping_flags |=
2648 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2649 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2651 info->valid_sections =
2652 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2654 return I40E_SUCCESS;
2658 i40e_veb_release(struct i40e_veb *veb)
2660 struct i40e_vsi *vsi;
2663 if (veb == NULL || veb->associate_vsi == NULL)
2666 if (!TAILQ_EMPTY(&veb->head)) {
2667 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2671 vsi = veb->associate_vsi;
2672 hw = I40E_VSI_TO_HW(vsi);
2674 vsi->uplink_seid = veb->uplink_seid;
2675 i40e_aq_delete_element(hw, veb->seid, NULL);
2678 return I40E_SUCCESS;
2682 static struct i40e_veb *
2683 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2685 struct i40e_veb *veb;
2689 if (NULL == pf || vsi == NULL) {
2690 PMD_DRV_LOG(ERR, "veb setup failed, "
2691 "associated VSI shouldn't null");
2694 hw = I40E_PF_TO_HW(pf);
2696 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2698 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2702 veb->associate_vsi = vsi;
2703 TAILQ_INIT(&veb->head);
2704 veb->uplink_seid = vsi->uplink_seid;
2706 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2707 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2709 if (ret != I40E_SUCCESS) {
2710 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2711 hw->aq.asq_last_status);
2715 /* get statistics index */
2716 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2717 &veb->stats_idx, NULL, NULL, NULL);
2718 if (ret != I40E_SUCCESS) {
2719 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2720 hw->aq.asq_last_status);
2724 /* Get VEB bandwidth, to be implemented */
2725 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2726 vsi->uplink_seid = veb->seid;
2735 i40e_vsi_release(struct i40e_vsi *vsi)
2739 struct i40e_vsi_list *vsi_list;
2741 struct i40e_mac_filter *f;
2744 return I40E_SUCCESS;
2746 pf = I40E_VSI_TO_PF(vsi);
2747 hw = I40E_VSI_TO_HW(vsi);
2749 /* VSI has child to attach, release child first */
2751 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2752 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2754 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2756 i40e_veb_release(vsi->veb);
2759 /* Remove all macvlan filters of the VSI */
2760 i40e_vsi_remove_all_macvlan_filter(vsi);
2761 TAILQ_FOREACH(f, &vsi->mac_list, next)
2764 if (vsi->type != I40E_VSI_MAIN) {
2765 /* Remove vsi from parent's sibling list */
2766 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2767 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2768 return I40E_ERR_PARAM;
2770 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2771 &vsi->sib_vsi_list, list);
2773 /* Remove all switch element of the VSI */
2774 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2775 if (ret != I40E_SUCCESS)
2776 PMD_DRV_LOG(ERR, "Failed to delete element");
2778 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2780 if (vsi->type != I40E_VSI_SRIOV)
2781 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2784 return I40E_SUCCESS;
2788 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2791 struct i40e_aqc_remove_macvlan_element_data def_filter;
2792 struct i40e_mac_filter_info filter;
2795 if (vsi->type != I40E_VSI_MAIN)
2796 return I40E_ERR_CONFIG;
2797 memset(&def_filter, 0, sizeof(def_filter));
2798 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2800 def_filter.vlan_tag = 0;
2801 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2802 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2803 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2804 if (ret != I40E_SUCCESS) {
2805 struct i40e_mac_filter *f;
2806 struct ether_addr *mac;
2808 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2810 /* It needs to add the permanent mac into mac list */
2811 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2813 PMD_DRV_LOG(ERR, "failed to allocate memory");
2814 return I40E_ERR_NO_MEMORY;
2816 mac = &f->mac_info.mac_addr;
2817 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2819 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2820 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2825 (void)rte_memcpy(&filter.mac_addr,
2826 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2827 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2828 return i40e_vsi_add_mac(vsi, &filter);
2832 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2834 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2835 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2836 struct i40e_hw *hw = &vsi->adapter->hw;
2840 memset(&bw_config, 0, sizeof(bw_config));
2841 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2842 if (ret != I40E_SUCCESS) {
2843 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2844 hw->aq.asq_last_status);
2848 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2849 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2850 &ets_sla_config, NULL);
2851 if (ret != I40E_SUCCESS) {
2852 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2853 "configuration %u", hw->aq.asq_last_status);
2857 /* Not store the info yet, just print out */
2858 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2859 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2860 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2861 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2862 ets_sla_config.share_credits[i]);
2863 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2864 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2865 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2866 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2875 i40e_vsi_setup(struct i40e_pf *pf,
2876 enum i40e_vsi_type type,
2877 struct i40e_vsi *uplink_vsi,
2878 uint16_t user_param)
2880 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2881 struct i40e_vsi *vsi;
2882 struct i40e_mac_filter_info filter;
2884 struct i40e_vsi_context ctxt;
2885 struct ether_addr broadcast =
2886 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2888 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2889 PMD_DRV_LOG(ERR, "VSI setup failed, "
2890 "VSI link shouldn't be NULL");
2894 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2895 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2896 "uplink VSI should be NULL");
2900 /* If uplink vsi didn't setup VEB, create one first */
2901 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2902 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2904 if (NULL == uplink_vsi->veb) {
2905 PMD_DRV_LOG(ERR, "VEB setup failed");
2910 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2912 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2915 TAILQ_INIT(&vsi->mac_list);
2917 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2918 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2919 vsi->parent_vsi = uplink_vsi;
2920 vsi->user_param = user_param;
2921 /* Allocate queues */
2922 switch (vsi->type) {
2923 case I40E_VSI_MAIN :
2924 vsi->nb_qps = pf->lan_nb_qps;
2926 case I40E_VSI_SRIOV :
2927 vsi->nb_qps = pf->vf_nb_qps;
2929 case I40E_VSI_VMDQ2:
2930 vsi->nb_qps = pf->vmdq_nb_qps;
2933 vsi->nb_qps = pf->fdir_nb_qps;
2939 * The filter status descriptor is reported in rx queue 0,
2940 * while the tx queue for fdir filter programming has no
2941 * such constraints, can be non-zero queues.
2942 * To simplify it, choose FDIR vsi use queue 0 pair.
2943 * To make sure it will use queue 0 pair, queue allocation
2944 * need be done before this function is called
2946 if (type != I40E_VSI_FDIR) {
2947 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2949 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2953 vsi->base_queue = ret;
2955 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2957 /* VF has MSIX interrupt in VF range, don't allocate here */
2958 if (type != I40E_VSI_SRIOV) {
2959 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2961 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2962 goto fail_queue_alloc;
2964 vsi->msix_intr = ret;
2968 if (type == I40E_VSI_MAIN) {
2969 /* For main VSI, no need to add since it's default one */
2970 vsi->uplink_seid = pf->mac_seid;
2971 vsi->seid = pf->main_vsi_seid;
2972 /* Bind queues with specific MSIX interrupt */
2974 * Needs 2 interrupt at least, one for misc cause which will
2975 * enabled from OS side, Another for queues binding the
2976 * interrupt from device side only.
2979 /* Get default VSI parameters from hardware */
2980 memset(&ctxt, 0, sizeof(ctxt));
2981 ctxt.seid = vsi->seid;
2982 ctxt.pf_num = hw->pf_id;
2983 ctxt.uplink_seid = vsi->uplink_seid;
2985 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2986 if (ret != I40E_SUCCESS) {
2987 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2988 goto fail_msix_alloc;
2990 (void)rte_memcpy(&vsi->info, &ctxt.info,
2991 sizeof(struct i40e_aqc_vsi_properties_data));
2992 vsi->vsi_id = ctxt.vsi_number;
2993 vsi->info.valid_sections = 0;
2995 /* Configure tc, enabled TC0 only */
2996 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2998 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2999 goto fail_msix_alloc;
3002 /* TC, queue mapping */
3003 memset(&ctxt, 0, sizeof(ctxt));
3004 vsi->info.valid_sections |=
3005 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3006 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3007 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3008 (void)rte_memcpy(&ctxt.info, &vsi->info,
3009 sizeof(struct i40e_aqc_vsi_properties_data));
3010 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3011 I40E_DEFAULT_TCMAP);
3012 if (ret != I40E_SUCCESS) {
3013 PMD_DRV_LOG(ERR, "Failed to configure "
3014 "TC queue mapping");
3015 goto fail_msix_alloc;
3017 ctxt.seid = vsi->seid;
3018 ctxt.pf_num = hw->pf_id;
3019 ctxt.uplink_seid = vsi->uplink_seid;
3022 /* Update VSI parameters */
3023 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3024 if (ret != I40E_SUCCESS) {
3025 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3026 goto fail_msix_alloc;
3029 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3030 sizeof(vsi->info.tc_mapping));
3031 (void)rte_memcpy(&vsi->info.queue_mapping,
3032 &ctxt.info.queue_mapping,
3033 sizeof(vsi->info.queue_mapping));
3034 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3035 vsi->info.valid_sections = 0;
3037 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3041 * Updating default filter settings are necessary to prevent
3042 * reception of tagged packets.
3043 * Some old firmware configurations load a default macvlan
3044 * filter which accepts both tagged and untagged packets.
3045 * The updating is to use a normal filter instead if needed.
3046 * For NVM 4.2.2 or after, the updating is not needed anymore.
3047 * The firmware with correct configurations load the default
3048 * macvlan filter which is expected and cannot be removed.
3050 i40e_update_default_filter_setting(vsi);
3051 } else if (type == I40E_VSI_SRIOV) {
3052 memset(&ctxt, 0, sizeof(ctxt));
3054 * For other VSI, the uplink_seid equals to uplink VSI's
3055 * uplink_seid since they share same VEB
3057 vsi->uplink_seid = uplink_vsi->uplink_seid;
3058 ctxt.pf_num = hw->pf_id;
3059 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3060 ctxt.uplink_seid = vsi->uplink_seid;
3061 ctxt.connection_type = 0x1;
3062 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3064 /* Configure switch ID */
3065 ctxt.info.valid_sections |=
3066 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3067 ctxt.info.switch_id =
3068 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3069 /* Configure port/vlan */
3070 ctxt.info.valid_sections |=
3071 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3072 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3073 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3074 I40E_DEFAULT_TCMAP);
3075 if (ret != I40E_SUCCESS) {
3076 PMD_DRV_LOG(ERR, "Failed to configure "
3077 "TC queue mapping");
3078 goto fail_msix_alloc;
3080 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3081 ctxt.info.valid_sections |=
3082 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3084 * Since VSI is not created yet, only configure parameter,
3085 * will add vsi below.
3087 } else if (type == I40E_VSI_VMDQ2) {
3088 memset(&ctxt, 0, sizeof(ctxt));
3090 * For other VSI, the uplink_seid equals to uplink VSI's
3091 * uplink_seid since they share same VEB
3093 vsi->uplink_seid = uplink_vsi->uplink_seid;
3094 ctxt.pf_num = hw->pf_id;
3096 ctxt.uplink_seid = vsi->uplink_seid;
3097 ctxt.connection_type = 0x1;
3098 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3100 ctxt.info.valid_sections |=
3101 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3102 /* user_param carries flag to enable loop back */
3104 ctxt.info.switch_id =
3105 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3106 ctxt.info.switch_id |=
3107 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3110 /* Configure port/vlan */
3111 ctxt.info.valid_sections |=
3112 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3113 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3114 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3115 I40E_DEFAULT_TCMAP);
3116 if (ret != I40E_SUCCESS) {
3117 PMD_DRV_LOG(ERR, "Failed to configure "
3118 "TC queue mapping");
3119 goto fail_msix_alloc;
3121 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3122 ctxt.info.valid_sections |=
3123 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3124 } else if (type == I40E_VSI_FDIR) {
3125 vsi->uplink_seid = uplink_vsi->uplink_seid;
3126 ctxt.pf_num = hw->pf_id;
3128 ctxt.uplink_seid = vsi->uplink_seid;
3129 ctxt.connection_type = 0x1; /* regular data port */
3130 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3131 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3132 I40E_DEFAULT_TCMAP);
3133 if (ret != I40E_SUCCESS) {
3134 PMD_DRV_LOG(ERR, "Failed to configure "
3135 "TC queue mapping.");
3136 goto fail_msix_alloc;
3138 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3139 ctxt.info.valid_sections |=
3140 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3142 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3143 goto fail_msix_alloc;
3146 if (vsi->type != I40E_VSI_MAIN) {
3147 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3149 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3150 hw->aq.asq_last_status);
3151 goto fail_msix_alloc;
3153 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3154 vsi->info.valid_sections = 0;
3155 vsi->seid = ctxt.seid;
3156 vsi->vsi_id = ctxt.vsi_number;
3157 vsi->sib_vsi_list.vsi = vsi;
3158 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3159 &vsi->sib_vsi_list, list);
3162 /* MAC/VLAN configuration */
3163 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3164 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3166 ret = i40e_vsi_add_mac(vsi, &filter);
3167 if (ret != I40E_SUCCESS) {
3168 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3169 goto fail_msix_alloc;
3172 /* Get VSI BW information */
3173 i40e_vsi_dump_bw_config(vsi);
3176 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3178 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3184 /* Configure vlan stripping on or off */
3186 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3188 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3189 struct i40e_vsi_context ctxt;
3191 int ret = I40E_SUCCESS;
3193 /* Check if it has been already on or off */
3194 if (vsi->info.valid_sections &
3195 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3197 if ((vsi->info.port_vlan_flags &
3198 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3199 return 0; /* already on */
3201 if ((vsi->info.port_vlan_flags &
3202 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3203 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3204 return 0; /* already off */
3209 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3211 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3212 vsi->info.valid_sections =
3213 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3214 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3215 vsi->info.port_vlan_flags |= vlan_flags;
3216 ctxt.seid = vsi->seid;
3217 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3218 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3220 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3221 on ? "enable" : "disable");
3227 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3229 struct rte_eth_dev_data *data = dev->data;
3232 /* Apply vlan offload setting */
3233 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3235 /* Apply double-vlan setting, not implemented yet */
3237 /* Apply pvid setting */
3238 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3239 data->dev_conf.txmode.hw_vlan_insert_pvid);
3241 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3247 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3249 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3251 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3255 i40e_update_flow_control(struct i40e_hw *hw)
3257 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3258 struct i40e_link_status link_status;
3259 uint32_t rxfc = 0, txfc = 0, reg;
3263 memset(&link_status, 0, sizeof(link_status));
3264 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3265 if (ret != I40E_SUCCESS) {
3266 PMD_DRV_LOG(ERR, "Failed to get link status information");
3267 goto write_reg; /* Disable flow control */
3270 an_info = hw->phy.link_info.an_info;
3271 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3272 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3273 ret = I40E_ERR_NOT_READY;
3274 goto write_reg; /* Disable flow control */
3277 * If link auto negotiation is enabled, flow control needs to
3278 * be configured according to it
3280 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3281 case I40E_LINK_PAUSE_RXTX:
3284 hw->fc.current_mode = I40E_FC_FULL;
3286 case I40E_AQ_LINK_PAUSE_RX:
3288 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3290 case I40E_AQ_LINK_PAUSE_TX:
3292 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3295 hw->fc.current_mode = I40E_FC_NONE;
3300 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3301 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3302 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3303 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3304 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3305 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3312 i40e_pf_setup(struct i40e_pf *pf)
3314 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3315 struct i40e_filter_control_settings settings;
3316 struct i40e_vsi *vsi;
3319 /* Clear all stats counters */
3320 pf->offset_loaded = FALSE;
3321 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3322 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3324 ret = i40e_pf_get_switch_config(pf);
3325 if (ret != I40E_SUCCESS) {
3326 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3329 if (pf->flags & I40E_FLAG_FDIR) {
3330 /* make queue allocated first, let FDIR use queue pair 0*/
3331 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3332 if (ret != I40E_FDIR_QUEUE_ID) {
3333 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3335 pf->flags &= ~I40E_FLAG_FDIR;
3338 /* main VSI setup */
3339 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3341 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3342 return I40E_ERR_NOT_READY;
3346 /* Configure filter control */
3347 memset(&settings, 0, sizeof(settings));
3348 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3349 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3350 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3351 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3353 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3354 hw->func_caps.rss_table_size);
3355 return I40E_ERR_PARAM;
3357 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3358 "size: %u\n", hw->func_caps.rss_table_size);
3359 pf->hash_lut_size = hw->func_caps.rss_table_size;
3361 /* Enable ethtype and macvlan filters */
3362 settings.enable_ethtype = TRUE;
3363 settings.enable_macvlan = TRUE;
3364 ret = i40e_set_filter_control(hw, &settings);
3366 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3369 /* Update flow control according to the auto negotiation */
3370 i40e_update_flow_control(hw);
3372 return I40E_SUCCESS;
3376 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3382 * Set or clear TX Queue Disable flags,
3383 * which is required by hardware.
3385 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3386 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3388 /* Wait until the request is finished */
3389 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3390 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3391 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3392 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3393 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3399 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3400 return I40E_SUCCESS; /* already on, skip next steps */
3402 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3403 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3405 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3406 return I40E_SUCCESS; /* already off, skip next steps */
3407 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3409 /* Write the register */
3410 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3411 /* Check the result */
3412 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3413 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3414 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3416 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3417 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3420 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3421 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3425 /* Check if it is timeout */
3426 if (j >= I40E_CHK_Q_ENA_COUNT) {
3427 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3428 (on ? "enable" : "disable"), q_idx);
3429 return I40E_ERR_TIMEOUT;
3432 return I40E_SUCCESS;
3435 /* Swith on or off the tx queues */
3437 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3439 struct rte_eth_dev_data *dev_data = pf->dev_data;
3440 struct i40e_tx_queue *txq;
3441 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3445 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3446 txq = dev_data->tx_queues[i];
3447 /* Don't operate the queue if not configured or
3448 * if starting only per queue */
3449 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3452 ret = i40e_dev_tx_queue_start(dev, i);
3454 ret = i40e_dev_tx_queue_stop(dev, i);
3455 if ( ret != I40E_SUCCESS)
3459 return I40E_SUCCESS;
3463 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3468 /* Wait until the request is finished */
3469 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3470 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3471 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3472 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3473 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3478 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3479 return I40E_SUCCESS; /* Already on, skip next steps */
3480 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3482 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3483 return I40E_SUCCESS; /* Already off, skip next steps */
3484 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3487 /* Write the register */
3488 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3489 /* Check the result */
3490 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3491 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3492 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3494 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3495 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3498 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3499 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3504 /* Check if it is timeout */
3505 if (j >= I40E_CHK_Q_ENA_COUNT) {
3506 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3507 (on ? "enable" : "disable"), q_idx);
3508 return I40E_ERR_TIMEOUT;
3511 return I40E_SUCCESS;
3513 /* Switch on or off the rx queues */
3515 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3517 struct rte_eth_dev_data *dev_data = pf->dev_data;
3518 struct i40e_rx_queue *rxq;
3519 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3523 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3524 rxq = dev_data->rx_queues[i];
3525 /* Don't operate the queue if not configured or
3526 * if starting only per queue */
3527 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3530 ret = i40e_dev_rx_queue_start(dev, i);
3532 ret = i40e_dev_rx_queue_stop(dev, i);
3533 if (ret != I40E_SUCCESS)
3537 return I40E_SUCCESS;
3540 /* Switch on or off all the rx/tx queues */
3542 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3547 /* enable rx queues before enabling tx queues */
3548 ret = i40e_dev_switch_rx_queues(pf, on);
3550 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3553 ret = i40e_dev_switch_tx_queues(pf, on);
3555 /* Stop tx queues before stopping rx queues */
3556 ret = i40e_dev_switch_tx_queues(pf, on);
3558 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3561 ret = i40e_dev_switch_rx_queues(pf, on);
3567 /* Initialize VSI for TX */
3569 i40e_dev_tx_init(struct i40e_pf *pf)
3571 struct rte_eth_dev_data *data = pf->dev_data;
3573 uint32_t ret = I40E_SUCCESS;
3574 struct i40e_tx_queue *txq;
3576 for (i = 0; i < data->nb_tx_queues; i++) {
3577 txq = data->tx_queues[i];
3578 if (!txq || !txq->q_set)
3580 ret = i40e_tx_queue_init(txq);
3581 if (ret != I40E_SUCCESS)
3588 /* Initialize VSI for RX */
3590 i40e_dev_rx_init(struct i40e_pf *pf)
3592 struct rte_eth_dev_data *data = pf->dev_data;
3593 int ret = I40E_SUCCESS;
3595 struct i40e_rx_queue *rxq;
3597 i40e_pf_config_mq_rx(pf);
3598 for (i = 0; i < data->nb_rx_queues; i++) {
3599 rxq = data->rx_queues[i];
3600 if (!rxq || !rxq->q_set)
3603 ret = i40e_rx_queue_init(rxq);
3604 if (ret != I40E_SUCCESS) {
3605 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3615 i40e_dev_rxtx_init(struct i40e_pf *pf)
3619 err = i40e_dev_tx_init(pf);
3621 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3624 err = i40e_dev_rx_init(pf);
3626 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3634 i40e_vmdq_setup(struct rte_eth_dev *dev)
3636 struct rte_eth_conf *conf = &dev->data->dev_conf;
3637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638 int i, err, conf_vsis, j, loop;
3639 struct i40e_vsi *vsi;
3640 struct i40e_vmdq_info *vmdq_info;
3641 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3642 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3645 * Disable interrupt to avoid message from VF. Furthermore, it will
3646 * avoid race condition in VSI creation/destroy.
3648 i40e_pf_disable_irq0(hw);
3650 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3651 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3655 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3656 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3657 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3658 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3659 pf->max_nb_vmdq_vsi);
3663 if (pf->vmdq != NULL) {
3664 PMD_INIT_LOG(INFO, "VMDQ already configured");
3668 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3669 sizeof(*vmdq_info) * conf_vsis, 0);
3671 if (pf->vmdq == NULL) {
3672 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3676 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3678 /* Create VMDQ VSI */
3679 for (i = 0; i < conf_vsis; i++) {
3680 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3681 vmdq_conf->enable_loop_back);
3683 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3687 vmdq_info = &pf->vmdq[i];
3689 vmdq_info->vsi = vsi;
3691 pf->nb_cfg_vmdq_vsi = conf_vsis;
3693 /* Configure Vlan */
3694 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3695 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3696 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3697 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3698 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3699 vmdq_conf->pool_map[i].vlan_id, j);
3701 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3702 vmdq_conf->pool_map[i].vlan_id);
3704 PMD_INIT_LOG(ERR, "Failed to add vlan");
3712 i40e_pf_enable_irq0(hw);
3717 for (i = 0; i < conf_vsis; i++)
3718 if (pf->vmdq[i].vsi == NULL)
3721 i40e_vsi_release(pf->vmdq[i].vsi);
3725 i40e_pf_enable_irq0(hw);
3730 i40e_stat_update_32(struct i40e_hw *hw,
3738 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3742 if (new_data >= *offset)
3743 *stat = (uint64_t)(new_data - *offset);
3745 *stat = (uint64_t)((new_data +
3746 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3750 i40e_stat_update_48(struct i40e_hw *hw,
3759 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3760 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3761 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3766 if (new_data >= *offset)
3767 *stat = new_data - *offset;
3769 *stat = (uint64_t)((new_data +
3770 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3772 *stat &= I40E_48_BIT_MASK;
3777 i40e_pf_disable_irq0(struct i40e_hw *hw)
3779 /* Disable all interrupt types */
3780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3781 I40E_WRITE_FLUSH(hw);
3786 i40e_pf_enable_irq0(struct i40e_hw *hw)
3788 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3789 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3790 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3791 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3792 I40E_WRITE_FLUSH(hw);
3796 i40e_pf_config_irq0(struct i40e_hw *hw)
3798 /* read pending request and disable first */
3799 i40e_pf_disable_irq0(hw);
3800 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3801 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3802 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3804 /* Link no queues with irq0 */
3805 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3806 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3810 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3812 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3816 uint32_t index, offset, val;
3821 * Try to find which VF trigger a reset, use absolute VF id to access
3822 * since the reg is global register.
3824 for (i = 0; i < pf->vf_num; i++) {
3825 abs_vf_id = hw->func_caps.vf_base_id + i;
3826 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3827 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3828 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3829 /* VFR event occured */
3830 if (val & (0x1 << offset)) {
3833 /* Clear the event first */
3834 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3836 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3838 * Only notify a VF reset event occured,
3839 * don't trigger another SW reset
3841 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3842 if (ret != I40E_SUCCESS)
3843 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3849 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3851 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852 struct i40e_arq_event_info info;
3853 uint16_t pending, opcode;
3856 info.buf_len = I40E_AQ_BUF_SZ;
3857 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3858 if (!info.msg_buf) {
3859 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3865 ret = i40e_clean_arq_element(hw, &info, &pending);
3867 if (ret != I40E_SUCCESS) {
3868 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3869 "aq_err: %u", hw->aq.asq_last_status);
3872 opcode = rte_le_to_cpu_16(info.desc.opcode);
3875 case i40e_aqc_opc_send_msg_to_pf:
3876 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3877 i40e_pf_host_handle_vf_msg(dev,
3878 rte_le_to_cpu_16(info.desc.retval),
3879 rte_le_to_cpu_32(info.desc.cookie_high),
3880 rte_le_to_cpu_32(info.desc.cookie_low),
3885 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3890 rte_free(info.msg_buf);
3894 * Interrupt handler is registered as the alarm callback for handling LSC
3895 * interrupt in a definite of time, in order to wait the NIC into a stable
3896 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3897 * no need for link down interrupt.
3900 i40e_dev_interrupt_delayed_handler(void *param)
3902 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3903 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3906 /* read interrupt causes again */
3907 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3909 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3910 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3911 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3912 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3913 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3914 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3915 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3916 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3917 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3918 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3919 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3921 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3922 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3923 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3924 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3925 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3927 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3928 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3929 i40e_dev_handle_vfr_event(dev);
3931 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3932 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3933 i40e_dev_handle_aq_msg(dev);
3936 /* handle the link up interrupt in an alarm callback */
3937 i40e_dev_link_update(dev, 0);
3938 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3940 i40e_pf_enable_irq0(hw);
3941 rte_intr_enable(&(dev->pci_dev->intr_handle));
3945 * Interrupt handler triggered by NIC for handling
3946 * specific interrupt.
3949 * Pointer to interrupt handle.
3951 * The address of parameter (struct rte_eth_dev *) regsitered before.
3957 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3960 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964 /* Disable interrupt */
3965 i40e_pf_disable_irq0(hw);
3967 /* read out interrupt causes */
3968 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3970 /* No interrupt event indicated */
3971 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3972 PMD_DRV_LOG(INFO, "No interrupt event");
3975 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3976 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3977 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3978 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3979 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3980 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3981 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3982 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3983 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3984 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3985 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3986 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3987 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3988 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3989 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3990 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3992 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3993 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3994 i40e_dev_handle_vfr_event(dev);
3996 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3997 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3998 i40e_dev_handle_aq_msg(dev);
4001 /* Link Status Change interrupt */
4002 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4003 #define I40E_US_PER_SECOND 1000000
4004 struct rte_eth_link link;
4006 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4007 memset(&link, 0, sizeof(link));
4008 rte_i40e_dev_atomic_read_link_status(dev, &link);
4009 i40e_dev_link_update(dev, 0);
4012 * For link up interrupt, it needs to wait 1 second to let the
4013 * hardware be a stable state. Otherwise several consecutive
4014 * interrupts can be observed.
4015 * For link down interrupt, no need to wait.
4017 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4018 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4021 _rte_eth_dev_callback_process(dev,
4022 RTE_ETH_EVENT_INTR_LSC);
4026 /* Enable interrupt */
4027 i40e_pf_enable_irq0(hw);
4028 rte_intr_enable(&(dev->pci_dev->intr_handle));
4032 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4033 struct i40e_macvlan_filter *filter,
4036 int ele_num, ele_buff_size;
4037 int num, actual_num, i;
4039 int ret = I40E_SUCCESS;
4040 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4041 struct i40e_aqc_add_macvlan_element_data *req_list;
4043 if (filter == NULL || total == 0)
4044 return I40E_ERR_PARAM;
4045 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4046 ele_buff_size = hw->aq.asq_buf_size;
4048 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4049 if (req_list == NULL) {
4050 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4051 return I40E_ERR_NO_MEMORY;
4056 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4057 memset(req_list, 0, ele_buff_size);
4059 for (i = 0; i < actual_num; i++) {
4060 (void)rte_memcpy(req_list[i].mac_addr,
4061 &filter[num + i].macaddr, ETH_ADDR_LEN);
4062 req_list[i].vlan_tag =
4063 rte_cpu_to_le_16(filter[num + i].vlan_id);
4065 switch (filter[num + i].filter_type) {
4066 case RTE_MAC_PERFECT_MATCH:
4067 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4068 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4070 case RTE_MACVLAN_PERFECT_MATCH:
4071 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4073 case RTE_MAC_HASH_MATCH:
4074 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4075 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4077 case RTE_MACVLAN_HASH_MATCH:
4078 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4081 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4082 ret = I40E_ERR_PARAM;
4086 req_list[i].queue_number = 0;
4088 req_list[i].flags = rte_cpu_to_le_16(flags);
4091 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4093 if (ret != I40E_SUCCESS) {
4094 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4098 } while (num < total);
4106 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4107 struct i40e_macvlan_filter *filter,
4110 int ele_num, ele_buff_size;
4111 int num, actual_num, i;
4113 int ret = I40E_SUCCESS;
4114 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4115 struct i40e_aqc_remove_macvlan_element_data *req_list;
4117 if (filter == NULL || total == 0)
4118 return I40E_ERR_PARAM;
4120 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4121 ele_buff_size = hw->aq.asq_buf_size;
4123 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4124 if (req_list == NULL) {
4125 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4126 return I40E_ERR_NO_MEMORY;
4131 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4132 memset(req_list, 0, ele_buff_size);
4134 for (i = 0; i < actual_num; i++) {
4135 (void)rte_memcpy(req_list[i].mac_addr,
4136 &filter[num + i].macaddr, ETH_ADDR_LEN);
4137 req_list[i].vlan_tag =
4138 rte_cpu_to_le_16(filter[num + i].vlan_id);
4140 switch (filter[num + i].filter_type) {
4141 case RTE_MAC_PERFECT_MATCH:
4142 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4143 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4145 case RTE_MACVLAN_PERFECT_MATCH:
4146 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4148 case RTE_MAC_HASH_MATCH:
4149 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4150 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4152 case RTE_MACVLAN_HASH_MATCH:
4153 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4156 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4157 ret = I40E_ERR_PARAM;
4160 req_list[i].flags = rte_cpu_to_le_16(flags);
4163 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4165 if (ret != I40E_SUCCESS) {
4166 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4170 } while (num < total);
4177 /* Find out specific MAC filter */
4178 static struct i40e_mac_filter *
4179 i40e_find_mac_filter(struct i40e_vsi *vsi,
4180 struct ether_addr *macaddr)
4182 struct i40e_mac_filter *f;
4184 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4185 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4193 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4196 uint32_t vid_idx, vid_bit;
4198 if (vlan_id > ETH_VLAN_ID_MAX)
4201 vid_idx = I40E_VFTA_IDX(vlan_id);
4202 vid_bit = I40E_VFTA_BIT(vlan_id);
4204 if (vsi->vfta[vid_idx] & vid_bit)
4211 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4212 uint16_t vlan_id, bool on)
4214 uint32_t vid_idx, vid_bit;
4216 if (vlan_id > ETH_VLAN_ID_MAX)
4219 vid_idx = I40E_VFTA_IDX(vlan_id);
4220 vid_bit = I40E_VFTA_BIT(vlan_id);
4223 vsi->vfta[vid_idx] |= vid_bit;
4225 vsi->vfta[vid_idx] &= ~vid_bit;
4229 * Find all vlan options for specific mac addr,
4230 * return with actual vlan found.
4233 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4234 struct i40e_macvlan_filter *mv_f,
4235 int num, struct ether_addr *addr)
4241 * Not to use i40e_find_vlan_filter to decrease the loop time,
4242 * although the code looks complex.
4244 if (num < vsi->vlan_num)
4245 return I40E_ERR_PARAM;
4248 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4250 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4251 if (vsi->vfta[j] & (1 << k)) {
4253 PMD_DRV_LOG(ERR, "vlan number "
4255 return I40E_ERR_PARAM;
4257 (void)rte_memcpy(&mv_f[i].macaddr,
4258 addr, ETH_ADDR_LEN);
4260 j * I40E_UINT32_BIT_SIZE + k;
4266 return I40E_SUCCESS;
4270 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4271 struct i40e_macvlan_filter *mv_f,
4276 struct i40e_mac_filter *f;
4278 if (num < vsi->mac_num)
4279 return I40E_ERR_PARAM;
4281 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4283 PMD_DRV_LOG(ERR, "buffer number not match");
4284 return I40E_ERR_PARAM;
4286 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4288 mv_f[i].vlan_id = vlan;
4289 mv_f[i].filter_type = f->mac_info.filter_type;
4293 return I40E_SUCCESS;
4297 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4300 struct i40e_mac_filter *f;
4301 struct i40e_macvlan_filter *mv_f;
4302 int ret = I40E_SUCCESS;
4304 if (vsi == NULL || vsi->mac_num == 0)
4305 return I40E_ERR_PARAM;
4307 /* Case that no vlan is set */
4308 if (vsi->vlan_num == 0)
4311 num = vsi->mac_num * vsi->vlan_num;
4313 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4315 PMD_DRV_LOG(ERR, "failed to allocate memory");
4316 return I40E_ERR_NO_MEMORY;
4320 if (vsi->vlan_num == 0) {
4321 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4322 (void)rte_memcpy(&mv_f[i].macaddr,
4323 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4324 mv_f[i].vlan_id = 0;
4328 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4329 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4330 vsi->vlan_num, &f->mac_info.mac_addr);
4331 if (ret != I40E_SUCCESS)
4337 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4345 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4347 struct i40e_macvlan_filter *mv_f;
4349 int ret = I40E_SUCCESS;
4351 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4352 return I40E_ERR_PARAM;
4354 /* If it's already set, just return */
4355 if (i40e_find_vlan_filter(vsi,vlan))
4356 return I40E_SUCCESS;
4358 mac_num = vsi->mac_num;
4361 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4362 return I40E_ERR_PARAM;
4365 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4368 PMD_DRV_LOG(ERR, "failed to allocate memory");
4369 return I40E_ERR_NO_MEMORY;
4372 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4374 if (ret != I40E_SUCCESS)
4377 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4379 if (ret != I40E_SUCCESS)
4382 i40e_set_vlan_filter(vsi, vlan, 1);
4392 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4394 struct i40e_macvlan_filter *mv_f;
4396 int ret = I40E_SUCCESS;
4399 * Vlan 0 is the generic filter for untagged packets
4400 * and can't be removed.
4402 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4403 return I40E_ERR_PARAM;
4405 /* If can't find it, just return */
4406 if (!i40e_find_vlan_filter(vsi, vlan))
4407 return I40E_ERR_PARAM;
4409 mac_num = vsi->mac_num;
4412 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4413 return I40E_ERR_PARAM;
4416 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4419 PMD_DRV_LOG(ERR, "failed to allocate memory");
4420 return I40E_ERR_NO_MEMORY;
4423 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4425 if (ret != I40E_SUCCESS)
4428 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4430 if (ret != I40E_SUCCESS)
4433 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4434 if (vsi->vlan_num == 1) {
4435 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4436 if (ret != I40E_SUCCESS)
4439 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4440 if (ret != I40E_SUCCESS)
4444 i40e_set_vlan_filter(vsi, vlan, 0);
4454 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4456 struct i40e_mac_filter *f;
4457 struct i40e_macvlan_filter *mv_f;
4458 int i, vlan_num = 0;
4459 int ret = I40E_SUCCESS;
4461 /* If it's add and we've config it, return */
4462 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4464 return I40E_SUCCESS;
4465 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4466 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4469 * If vlan_num is 0, that's the first time to add mac,
4470 * set mask for vlan_id 0.
4472 if (vsi->vlan_num == 0) {
4473 i40e_set_vlan_filter(vsi, 0, 1);
4476 vlan_num = vsi->vlan_num;
4477 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4478 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4481 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4483 PMD_DRV_LOG(ERR, "failed to allocate memory");
4484 return I40E_ERR_NO_MEMORY;
4487 for (i = 0; i < vlan_num; i++) {
4488 mv_f[i].filter_type = mac_filter->filter_type;
4489 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4493 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4494 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4495 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4496 &mac_filter->mac_addr);
4497 if (ret != I40E_SUCCESS)
4501 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4502 if (ret != I40E_SUCCESS)
4505 /* Add the mac addr into mac list */
4506 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4508 PMD_DRV_LOG(ERR, "failed to allocate memory");
4509 ret = I40E_ERR_NO_MEMORY;
4512 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4514 f->mac_info.filter_type = mac_filter->filter_type;
4515 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4526 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4528 struct i40e_mac_filter *f;
4529 struct i40e_macvlan_filter *mv_f;
4531 enum rte_mac_filter_type filter_type;
4532 int ret = I40E_SUCCESS;
4534 /* Can't find it, return an error */
4535 f = i40e_find_mac_filter(vsi, addr);
4537 return I40E_ERR_PARAM;
4539 vlan_num = vsi->vlan_num;
4540 filter_type = f->mac_info.filter_type;
4541 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4542 filter_type == RTE_MACVLAN_HASH_MATCH) {
4543 if (vlan_num == 0) {
4544 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4545 return I40E_ERR_PARAM;
4547 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4548 filter_type == RTE_MAC_HASH_MATCH)
4551 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4553 PMD_DRV_LOG(ERR, "failed to allocate memory");
4554 return I40E_ERR_NO_MEMORY;
4557 for (i = 0; i < vlan_num; i++) {
4558 mv_f[i].filter_type = filter_type;
4559 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4562 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4563 filter_type == RTE_MACVLAN_HASH_MATCH) {
4564 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4565 if (ret != I40E_SUCCESS)
4569 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4570 if (ret != I40E_SUCCESS)
4573 /* Remove the mac addr into mac list */
4574 TAILQ_REMOVE(&vsi->mac_list, f, next);
4584 /* Configure hash enable flags for RSS */
4586 i40e_config_hena(uint64_t flags)
4593 if (flags & ETH_RSS_FRAG_IPV4)
4594 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4595 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4596 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4597 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4598 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4599 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4600 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4601 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4602 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4603 if (flags & ETH_RSS_FRAG_IPV6)
4604 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4605 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4606 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4607 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4608 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4609 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4610 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4611 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4612 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4613 if (flags & ETH_RSS_L2_PAYLOAD)
4614 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4619 /* Parse the hash enable flags */
4621 i40e_parse_hena(uint64_t flags)
4623 uint64_t rss_hf = 0;
4627 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4628 rss_hf |= ETH_RSS_FRAG_IPV4;
4629 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4630 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4631 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4632 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4633 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4634 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4635 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4636 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4637 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4638 rss_hf |= ETH_RSS_FRAG_IPV6;
4639 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4640 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4641 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4642 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4643 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4644 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4645 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4646 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4647 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4648 rss_hf |= ETH_RSS_L2_PAYLOAD;
4655 i40e_pf_disable_rss(struct i40e_pf *pf)
4657 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4660 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4661 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4662 hena &= ~I40E_RSS_HENA_ALL;
4663 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4664 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4665 I40E_WRITE_FLUSH(hw);
4669 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4672 uint8_t hash_key_len;
4677 hash_key = (uint32_t *)(rss_conf->rss_key);
4678 hash_key_len = rss_conf->rss_key_len;
4679 if (hash_key != NULL && hash_key_len >=
4680 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4681 /* Fill in RSS hash key */
4682 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4683 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4686 rss_hf = rss_conf->rss_hf;
4687 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4688 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4689 hena &= ~I40E_RSS_HENA_ALL;
4690 hena |= i40e_config_hena(rss_hf);
4691 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4692 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4693 I40E_WRITE_FLUSH(hw);
4699 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4700 struct rte_eth_rss_conf *rss_conf)
4702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4706 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4707 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4708 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4709 if (rss_hf != 0) /* Enable RSS */
4711 return 0; /* Nothing to do */
4714 if (rss_hf == 0) /* Disable RSS */
4717 return i40e_hw_rss_hash_set(hw, rss_conf);
4721 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4722 struct rte_eth_rss_conf *rss_conf)
4724 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4729 if (hash_key != NULL) {
4730 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4731 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4732 rss_conf->rss_key_len = i * sizeof(uint32_t);
4734 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4735 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4736 rss_conf->rss_hf = i40e_parse_hena(hena);
4742 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4744 switch (filter_type) {
4745 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4746 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4748 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4749 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4751 case RTE_TUNNEL_FILTER_IMAC_TENID:
4752 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4754 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4755 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4757 case ETH_TUNNEL_FILTER_IMAC:
4758 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4761 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4769 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4770 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4774 uint8_t tun_type = 0;
4776 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4777 struct i40e_vsi *vsi = pf->main_vsi;
4778 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4779 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4781 cld_filter = rte_zmalloc("tunnel_filter",
4782 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4785 if (NULL == cld_filter) {
4786 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4789 pfilter = cld_filter;
4791 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4792 sizeof(struct ether_addr));
4793 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4794 sizeof(struct ether_addr));
4796 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4797 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4798 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4799 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4800 &tunnel_filter->ip_addr,
4801 sizeof(pfilter->ipaddr.v4.data));
4803 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4804 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4805 &tunnel_filter->ip_addr,
4806 sizeof(pfilter->ipaddr.v6.data));
4809 /* check tunneled type */
4810 switch (tunnel_filter->tunnel_type) {
4811 case RTE_TUNNEL_TYPE_VXLAN:
4812 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4815 /* Other tunnel types is not supported. */
4816 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4817 rte_free(cld_filter);
4821 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4824 rte_free(cld_filter);
4828 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4829 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4830 pfilter->tenant_id = tunnel_filter->tenant_id;
4831 pfilter->queue_number = tunnel_filter->queue_id;
4834 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4836 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4839 rte_free(cld_filter);
4844 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4848 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4849 if (pf->vxlan_ports[i] == port)
4857 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4861 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4863 idx = i40e_get_vxlan_port_idx(pf, port);
4865 /* Check if port already exists */
4867 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4871 /* Now check if there is space to add the new port */
4872 idx = i40e_get_vxlan_port_idx(pf, 0);
4874 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4875 "not adding port %d", port);
4879 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4882 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4886 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4889 /* New port: add it and mark its index in the bitmap */
4890 pf->vxlan_ports[idx] = port;
4891 pf->vxlan_bitmap |= (1 << idx);
4893 if (!(pf->flags & I40E_FLAG_VXLAN))
4894 pf->flags |= I40E_FLAG_VXLAN;
4900 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4903 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4905 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4906 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4910 idx = i40e_get_vxlan_port_idx(pf, port);
4913 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4917 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4918 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4922 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4925 pf->vxlan_ports[idx] = 0;
4926 pf->vxlan_bitmap &= ~(1 << idx);
4928 if (!pf->vxlan_bitmap)
4929 pf->flags &= ~I40E_FLAG_VXLAN;
4934 /* Add UDP tunneling port */
4936 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4937 struct rte_eth_udp_tunnel *udp_tunnel)
4940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4942 if (udp_tunnel == NULL)
4945 switch (udp_tunnel->prot_type) {
4946 case RTE_TUNNEL_TYPE_VXLAN:
4947 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4950 case RTE_TUNNEL_TYPE_GENEVE:
4951 case RTE_TUNNEL_TYPE_TEREDO:
4952 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4957 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4965 /* Remove UDP tunneling port */
4967 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4968 struct rte_eth_udp_tunnel *udp_tunnel)
4971 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4973 if (udp_tunnel == NULL)
4976 switch (udp_tunnel->prot_type) {
4977 case RTE_TUNNEL_TYPE_VXLAN:
4978 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4980 case RTE_TUNNEL_TYPE_GENEVE:
4981 case RTE_TUNNEL_TYPE_TEREDO:
4982 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4986 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4994 /* Calculate the maximum number of contiguous PF queues that are configured */
4996 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4998 struct rte_eth_dev_data *data = pf->dev_data;
5000 struct i40e_rx_queue *rxq;
5003 for (i = 0; i < pf->lan_nb_qps; i++) {
5004 rxq = data->rx_queues[i];
5005 if (rxq && rxq->q_set)
5016 i40e_pf_config_rss(struct i40e_pf *pf)
5018 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5019 struct rte_eth_rss_conf rss_conf;
5020 uint32_t i, lut = 0;
5024 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5025 * It's necessary to calulate the actual PF queues that are configured.
5027 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5028 num = i40e_pf_calc_configured_queues_num(pf);
5029 num = i40e_align_floor(num);
5031 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5033 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5037 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5041 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5044 lut = (lut << 8) | (j & ((0x1 <<
5045 hw->func_caps.rss_table_entry_width) - 1));
5047 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5050 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5051 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5052 i40e_pf_disable_rss(pf);
5055 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5056 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5057 /* Random default keys */
5058 static uint32_t rss_key_default[] = {0x6b793944,
5059 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5060 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5061 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5063 rss_conf.rss_key = (uint8_t *)rss_key_default;
5064 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5068 return i40e_hw_rss_hash_set(hw, &rss_conf);
5072 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5073 struct rte_eth_tunnel_filter_conf *filter)
5075 if (pf == NULL || filter == NULL) {
5076 PMD_DRV_LOG(ERR, "Invalid parameter");
5080 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5081 PMD_DRV_LOG(ERR, "Invalid queue ID");
5085 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5086 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5090 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5091 (is_zero_ether_addr(filter->outer_mac))) {
5092 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5096 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5097 (is_zero_ether_addr(filter->inner_mac))) {
5098 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5106 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5109 struct rte_eth_tunnel_filter_conf *filter;
5110 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5111 int ret = I40E_SUCCESS;
5113 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5115 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5116 return I40E_ERR_PARAM;
5118 switch (filter_op) {
5119 case RTE_ETH_FILTER_NOP:
5120 if (!(pf->flags & I40E_FLAG_VXLAN))
5121 ret = I40E_NOT_SUPPORTED;
5122 case RTE_ETH_FILTER_ADD:
5123 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5125 case RTE_ETH_FILTER_DELETE:
5126 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5129 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5130 ret = I40E_ERR_PARAM;
5138 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5141 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5143 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5144 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5149 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5150 ret = i40e_pf_config_rss(pf);
5152 i40e_pf_disable_rss(pf);
5157 /* Get the symmetric hash enable configurations per port */
5159 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5161 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5163 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5166 /* Set the symmetric hash enable configurations per port */
5168 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5170 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5173 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5174 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5178 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5180 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5181 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5185 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5187 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5188 I40E_WRITE_FLUSH(hw);
5192 * Get global configurations of hash function type and symmetric hash enable
5193 * per flow type (pctype). Note that global configuration means it affects all
5194 * the ports on the same NIC.
5197 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5198 struct rte_eth_hash_global_conf *g_cfg)
5200 uint32_t reg, mask = I40E_FLOW_TYPES;
5202 enum i40e_filter_pctype pctype;
5204 memset(g_cfg, 0, sizeof(*g_cfg));
5205 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5206 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5207 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5209 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5210 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5211 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5213 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5214 if (!(mask & (1UL << i)))
5216 mask &= ~(1UL << i);
5217 /* Bit set indicats the coresponding flow type is supported */
5218 g_cfg->valid_bit_mask[0] |= (1UL << i);
5219 pctype = i40e_flowtype_to_pctype(i);
5220 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5221 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5222 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5229 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5232 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5234 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5235 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5236 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5237 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5243 * As i40e supports less than 32 flow types, only first 32 bits need to
5246 mask0 = g_cfg->valid_bit_mask[0];
5247 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5249 /* Check if any unsupported flow type configured */
5250 if ((mask0 | i40e_mask) ^ i40e_mask)
5253 if (g_cfg->valid_bit_mask[i])
5261 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5267 * Set global configurations of hash function type and symmetric hash enable
5268 * per flow type (pctype). Note any modifying global configuration will affect
5269 * all the ports on the same NIC.
5272 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5273 struct rte_eth_hash_global_conf *g_cfg)
5278 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5279 enum i40e_filter_pctype pctype;
5281 /* Check the input parameters */
5282 ret = i40e_hash_global_config_check(g_cfg);
5286 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5287 if (!(mask0 & (1UL << i)))
5289 mask0 &= ~(1UL << i);
5290 pctype = i40e_flowtype_to_pctype(i);
5291 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5292 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5293 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5296 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5297 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5299 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5300 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5304 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5305 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5307 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5308 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5312 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5314 /* Use the default, and keep it as it is */
5317 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5320 I40E_WRITE_FLUSH(hw);
5326 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5331 PMD_DRV_LOG(ERR, "Invalid pointer");
5335 switch (info->info_type) {
5336 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5337 i40e_get_symmetric_hash_enable_per_port(hw,
5338 &(info->info.enable));
5340 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5341 ret = i40e_get_hash_filter_global_config(hw,
5342 &(info->info.global_conf));
5345 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5355 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5360 PMD_DRV_LOG(ERR, "Invalid pointer");
5364 switch (info->info_type) {
5365 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5366 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5368 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5369 ret = i40e_set_hash_filter_global_config(hw,
5370 &(info->info.global_conf));
5373 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5382 /* Operations for hash function */
5384 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5385 enum rte_filter_op filter_op,
5388 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391 switch (filter_op) {
5392 case RTE_ETH_FILTER_NOP:
5394 case RTE_ETH_FILTER_GET:
5395 ret = i40e_hash_filter_get(hw,
5396 (struct rte_eth_hash_filter_info *)arg);
5398 case RTE_ETH_FILTER_SET:
5399 ret = i40e_hash_filter_set(hw,
5400 (struct rte_eth_hash_filter_info *)arg);
5403 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5413 * Configure ethertype filter, which can director packet by filtering
5414 * with mac address and ether_type or only ether_type
5417 i40e_ethertype_filter_set(struct i40e_pf *pf,
5418 struct rte_eth_ethertype_filter *filter,
5421 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5422 struct i40e_control_filter_stats stats;
5426 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5427 PMD_DRV_LOG(ERR, "Invalid queue ID");
5430 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5431 filter->ether_type == ETHER_TYPE_IPv6) {
5432 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5433 " control packet filter.", filter->ether_type);
5436 if (filter->ether_type == ETHER_TYPE_VLAN)
5437 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5440 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5441 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5442 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5443 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5444 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5446 memset(&stats, 0, sizeof(stats));
5447 ret = i40e_aq_add_rem_control_packet_filter(hw,
5448 filter->mac_addr.addr_bytes,
5449 filter->ether_type, flags,
5451 filter->queue, add, &stats, NULL);
5453 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5454 " mac_etype_used = %u, etype_used = %u,"
5455 " mac_etype_free = %u, etype_free = %u\n",
5456 ret, stats.mac_etype_used, stats.etype_used,
5457 stats.mac_etype_free, stats.etype_free);
5464 * Handle operations for ethertype filter.
5467 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5468 enum rte_filter_op filter_op,
5471 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5474 if (filter_op == RTE_ETH_FILTER_NOP)
5478 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5483 switch (filter_op) {
5484 case RTE_ETH_FILTER_ADD:
5485 ret = i40e_ethertype_filter_set(pf,
5486 (struct rte_eth_ethertype_filter *)arg,
5489 case RTE_ETH_FILTER_DELETE:
5490 ret = i40e_ethertype_filter_set(pf,
5491 (struct rte_eth_ethertype_filter *)arg,
5495 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5503 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5504 enum rte_filter_type filter_type,
5505 enum rte_filter_op filter_op,
5513 switch (filter_type) {
5514 case RTE_ETH_FILTER_HASH:
5515 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5517 case RTE_ETH_FILTER_MACVLAN:
5518 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5520 case RTE_ETH_FILTER_ETHERTYPE:
5521 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5523 case RTE_ETH_FILTER_TUNNEL:
5524 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5526 case RTE_ETH_FILTER_FDIR:
5527 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5530 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5540 * As some registers wouldn't be reset unless a global hardware reset,
5541 * hardware initialization is needed to put those registers into an
5542 * expected initial state.
5545 i40e_hw_init(struct i40e_hw *hw)
5547 /* clear the PF Queue Filter control register */
5548 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5550 /* Disable symmetric hash per port */
5551 i40e_set_symmetric_hash_enable_per_port(hw, 0);
5554 enum i40e_filter_pctype
5555 i40e_flowtype_to_pctype(uint16_t flow_type)
5557 static const enum i40e_filter_pctype pctype_table[] = {
5558 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5559 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5560 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5561 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5562 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5563 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5564 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5565 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5566 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5567 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5568 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5569 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5570 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5571 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5572 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5573 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5574 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5575 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5576 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5579 return pctype_table[flow_type];
5583 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5585 static const uint16_t flowtype_table[] = {
5586 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5587 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5588 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5589 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5590 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5591 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5592 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5593 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5594 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5595 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5596 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5597 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5598 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5599 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5600 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5601 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5602 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5603 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5604 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5607 return flowtype_table[pctype];
5611 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5613 struct i40e_aq_desc desc;
5614 enum i40e_status_code status;
5616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5617 desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5618 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5622 *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5623 (CHAR_BIT * sizeof(uint32_t))) +
5624 rte_le_to_cpu_32(desc.params.internal.param3);
5630 * On X710, performance number is far from the expectation on recent firmware
5631 * versions. The fix for this issue may not be integrated in the following
5632 * firmware version. So the workaround in software driver is needed. It needs
5633 * to modify the initial values of 3 internal only registers. Note that the
5634 * workaround can be removed when it is fixed in firmware in the future.
5637 i40e_configure_registers(struct i40e_hw *hw)
5639 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
5640 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
5641 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
5642 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5643 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5644 #define I40E_GL_SWR_PM_UP_THR_VALUE 0x03030303
5646 static const struct {
5650 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5651 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5652 {I40E_GL_SWR_PM_UP_THR, I40E_GL_SWR_PM_UP_THR_VALUE},
5658 /* Below fix is for X710 only */
5659 if (i40e_is_40G_device(hw->device_id))
5662 for (i = 0; i < RTE_DIM(reg_table); i++) {
5663 ret = i40e_debug_read_register(hw, reg_table[i].addr, ®);
5665 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5669 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5670 reg_table[i].addr, reg);
5671 if (reg == reg_table[i].val)
5674 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5675 reg_table[i].val, NULL);
5677 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5678 "address of 0x%"PRIx32, reg_table[i].val,
5682 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5683 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);