4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_adminq_cmd.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 #define I40E_DEFAULT_RX_FREE_THRESH 32
63 #define I40E_DEFAULT_RX_PTHRESH 8
64 #define I40E_DEFAULT_RX_HTHRESH 8
65 #define I40E_DEFAULT_RX_WTHRESH 0
67 #define I40E_DEFAULT_TX_FREE_THRESH 32
68 #define I40E_DEFAULT_TX_PTHRESH 32
69 #define I40E_DEFAULT_TX_HTHRESH 0
70 #define I40E_DEFAULT_TX_WTHRESH 0
71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
73 /* Maximun number of MAC addresses */
74 #define I40E_NUM_MACADDR_MAX 64
75 #define I40E_CLEAR_PXE_WAIT_MS 200
77 /* Maximun number of capability elements */
78 #define I40E_MAX_CAP_ELE_NUM 128
80 /* Wait count and inteval */
81 #define I40E_CHK_Q_ENA_COUNT 1000
82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
84 /* Maximun number of VSI */
85 #define I40E_MAX_NUM_VSIS (384UL)
87 /* Bit shift and mask */
88 #define I40E_16_BIT_SHIFT 16
89 #define I40E_16_BIT_MASK 0xFFFF
90 #define I40E_32_BIT_SHIFT 32
91 #define I40E_32_BIT_MASK 0xFFFFFFFF
92 #define I40E_48_BIT_SHIFT 48
93 #define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL
95 /* Default queue interrupt throttling time in microseconds*/
96 #define I40E_ITR_INDEX_DEFAULT 0
97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
98 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
100 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
102 /* Mask of PF interrupt causes */
103 #define I40E_PFINT_ICR0_ENA_MASK ( \
104 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
105 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
106 I40E_PFINT_ICR0_ENA_GRST_MASK | \
107 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
108 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
109 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
110 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
112 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
113 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
115 static int eth_i40e_dev_init(\
116 __attribute__((unused)) struct eth_driver *eth_drv,
117 struct rte_eth_dev *eth_dev);
118 static int i40e_dev_configure(struct rte_eth_dev *dev);
119 static int i40e_dev_start(struct rte_eth_dev *dev);
120 static void i40e_dev_stop(struct rte_eth_dev *dev);
121 static void i40e_dev_close(struct rte_eth_dev *dev);
122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
129 struct rte_eth_stats *stats);
130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
149 struct rte_eth_fc_conf *fc_conf);
150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
151 struct rte_eth_pfc_conf *pfc_conf);
152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
153 struct ether_addr *mac_addr,
156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
158 struct rte_eth_rss_reta *reta_conf);
159 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
160 struct rte_eth_rss_reta *reta_conf);
162 static int i40e_get_cap(struct i40e_hw *hw);
163 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
164 static int i40e_pf_setup(struct i40e_pf *pf);
165 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
166 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
167 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
168 bool offset_loaded, uint64_t *offset, uint64_t *stat);
169 static void i40e_stat_update_48(struct i40e_hw *hw,
175 static void i40e_pf_config_irq0(struct i40e_hw *hw);
176 static void i40e_dev_interrupt_handler(
177 __rte_unused struct rte_intr_handle *handle, void *param);
178 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
179 uint32_t base, uint32_t num);
180 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
181 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
183 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
185 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
186 static int i40e_veb_release(struct i40e_veb *veb);
187 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
188 struct i40e_vsi *vsi);
189 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
190 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
191 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
192 struct i40e_macvlan_filter *mv_f,
194 struct ether_addr *addr);
195 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
196 struct i40e_macvlan_filter *mv_f,
199 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
200 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
201 struct rte_eth_rss_conf *rss_conf);
202 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
203 struct rte_eth_rss_conf *rss_conf);
204 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
205 struct rte_eth_udp_tunnel *udp_tunnel);
206 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
207 struct rte_eth_udp_tunnel *udp_tunnel);
208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
209 enum rte_filter_type filter_type,
210 enum rte_filter_op filter_op,
213 /* Default hash key buffer for RSS */
214 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
216 static struct rte_pci_id pci_id_i40e_map[] = {
217 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
218 #include "rte_pci_dev_ids.h"
219 { .vendor_id = 0, /* sentinel */ },
222 static struct eth_dev_ops i40e_eth_dev_ops = {
223 .dev_configure = i40e_dev_configure,
224 .dev_start = i40e_dev_start,
225 .dev_stop = i40e_dev_stop,
226 .dev_close = i40e_dev_close,
227 .promiscuous_enable = i40e_dev_promiscuous_enable,
228 .promiscuous_disable = i40e_dev_promiscuous_disable,
229 .allmulticast_enable = i40e_dev_allmulticast_enable,
230 .allmulticast_disable = i40e_dev_allmulticast_disable,
231 .dev_set_link_up = i40e_dev_set_link_up,
232 .dev_set_link_down = i40e_dev_set_link_down,
233 .link_update = i40e_dev_link_update,
234 .stats_get = i40e_dev_stats_get,
235 .stats_reset = i40e_dev_stats_reset,
236 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
237 .dev_infos_get = i40e_dev_info_get,
238 .vlan_filter_set = i40e_vlan_filter_set,
239 .vlan_tpid_set = i40e_vlan_tpid_set,
240 .vlan_offload_set = i40e_vlan_offload_set,
241 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
242 .vlan_pvid_set = i40e_vlan_pvid_set,
243 .rx_queue_start = i40e_dev_rx_queue_start,
244 .rx_queue_stop = i40e_dev_rx_queue_stop,
245 .tx_queue_start = i40e_dev_tx_queue_start,
246 .tx_queue_stop = i40e_dev_tx_queue_stop,
247 .rx_queue_setup = i40e_dev_rx_queue_setup,
248 .rx_queue_release = i40e_dev_rx_queue_release,
249 .rx_queue_count = i40e_dev_rx_queue_count,
250 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
251 .tx_queue_setup = i40e_dev_tx_queue_setup,
252 .tx_queue_release = i40e_dev_tx_queue_release,
253 .dev_led_on = i40e_dev_led_on,
254 .dev_led_off = i40e_dev_led_off,
255 .flow_ctrl_set = i40e_flow_ctrl_set,
256 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
257 .mac_addr_add = i40e_macaddr_add,
258 .mac_addr_remove = i40e_macaddr_remove,
259 .reta_update = i40e_dev_rss_reta_update,
260 .reta_query = i40e_dev_rss_reta_query,
261 .rss_hash_update = i40e_dev_rss_hash_update,
262 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
263 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
264 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
265 .filter_ctrl = i40e_dev_filter_ctrl,
268 static struct eth_driver rte_i40e_pmd = {
270 .name = "rte_i40e_pmd",
271 .id_table = pci_id_i40e_map,
272 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
274 .eth_dev_init = eth_i40e_dev_init,
275 .dev_private_size = sizeof(struct i40e_adapter),
279 i40e_align_floor(int n)
283 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
287 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
288 struct rte_eth_link *link)
290 struct rte_eth_link *dst = link;
291 struct rte_eth_link *src = &(dev->data->dev_link);
293 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
294 *(uint64_t *)src) == 0)
301 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
302 struct rte_eth_link *link)
304 struct rte_eth_link *dst = &(dev->data->dev_link);
305 struct rte_eth_link *src = link;
307 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
308 *(uint64_t *)src) == 0)
315 * Driver initialization routine.
316 * Invoked once at EAL init time.
317 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
320 rte_i40e_pmd_init(const char *name __rte_unused,
321 const char *params __rte_unused)
323 PMD_INIT_FUNC_TRACE();
324 rte_eth_driver_register(&rte_i40e_pmd);
329 static struct rte_driver rte_i40e_driver = {
331 .init = rte_i40e_pmd_init,
334 PMD_REGISTER_DRIVER(rte_i40e_driver);
337 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
338 struct rte_eth_dev *dev)
340 struct rte_pci_device *pci_dev;
341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
343 struct i40e_vsi *vsi;
348 PMD_INIT_FUNC_TRACE();
350 dev->dev_ops = &i40e_eth_dev_ops;
351 dev->rx_pkt_burst = i40e_recv_pkts;
352 dev->tx_pkt_burst = i40e_xmit_pkts;
354 /* for secondary processes, we don't initialise any further as primary
355 * has already done this work. Only check we don't need a different
357 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
358 if (dev->data->scattered_rx)
359 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
362 pci_dev = dev->pci_dev;
363 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
364 pf->adapter->eth_dev = dev;
365 pf->dev_data = dev->data;
367 hw->back = I40E_PF_TO_ADAPTER(pf);
368 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
370 PMD_INIT_LOG(ERR, "Hardware is not available, "
371 "as address is NULL");
375 hw->vendor_id = pci_dev->id.vendor_id;
376 hw->device_id = pci_dev->id.device_id;
377 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
378 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
379 hw->bus.device = pci_dev->addr.devid;
380 hw->bus.func = pci_dev->addr.function;
382 /* Make sure all is clean before doing PF reset */
385 /* Reset here to make sure all is clean for each PF */
386 ret = i40e_pf_reset(hw);
388 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
392 /* Initialize the shared code (base driver) */
393 ret = i40e_init_shared_code(hw);
395 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
399 /* Initialize the parameters for adminq */
400 i40e_init_adminq_parameter(hw);
401 ret = i40e_init_adminq(hw);
402 if (ret != I40E_SUCCESS) {
403 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
406 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
407 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
408 hw->aq.api_maj_ver, hw->aq.api_min_ver,
409 ((hw->nvm.version >> 12) & 0xf),
410 ((hw->nvm.version >> 4) & 0xff),
411 (hw->nvm.version & 0xf), hw->nvm.eetrack);
414 ret = i40e_aq_stop_lldp(hw, true, NULL);
415 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
416 PMD_INIT_LOG(INFO, "Failed to stop lldp");
419 i40e_clear_pxe_mode(hw);
421 /* Get hw capabilities */
422 ret = i40e_get_cap(hw);
423 if (ret != I40E_SUCCESS) {
424 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
425 goto err_get_capabilities;
428 /* Initialize parameters for PF */
429 ret = i40e_pf_parameter_init(dev);
431 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
432 goto err_parameter_init;
435 /* Initialize the queue management */
436 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
438 PMD_INIT_LOG(ERR, "Failed to init queue pool");
439 goto err_qp_pool_init;
441 ret = i40e_res_pool_init(&pf->msix_pool, 1,
442 hw->func_caps.num_msix_vectors - 1);
444 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
445 goto err_msix_pool_init;
448 /* Initialize lan hmc */
449 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
450 hw->func_caps.num_rx_qp, 0, 0);
451 if (ret != I40E_SUCCESS) {
452 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
453 goto err_init_lan_hmc;
456 /* Configure lan hmc */
457 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
458 if (ret != I40E_SUCCESS) {
459 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
460 goto err_configure_lan_hmc;
463 /* Get and check the mac address */
464 i40e_get_mac_addr(hw, hw->mac.addr);
465 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
466 PMD_INIT_LOG(ERR, "mac address is not valid");
468 goto err_get_mac_addr;
470 /* Copy the permanent MAC address */
471 ether_addr_copy((struct ether_addr *) hw->mac.addr,
472 (struct ether_addr *) hw->mac.perm_addr);
474 /* Disable flow control */
475 hw->fc.requested_mode = I40E_FC_NONE;
476 i40e_set_fc(hw, &aq_fail, TRUE);
478 /* PF setup, which includes VSI setup */
479 ret = i40e_pf_setup(pf);
481 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
482 goto err_setup_pf_switch;
487 /* Disable double vlan by default */
488 i40e_vsi_config_double_vlan(vsi, FALSE);
490 if (!vsi->max_macaddrs)
491 len = ETHER_ADDR_LEN;
493 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
495 /* Should be after VSI initialized */
496 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
497 if (!dev->data->mac_addrs) {
498 PMD_INIT_LOG(ERR, "Failed to allocated memory "
499 "for storing mac address");
502 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
503 &dev->data->mac_addrs[0]);
505 /* initialize pf host driver to setup SRIOV resource if applicable */
506 i40e_pf_host_init(dev);
508 /* register callback func to eal lib */
509 rte_intr_callback_register(&(pci_dev->intr_handle),
510 i40e_dev_interrupt_handler, (void *)dev);
512 /* configure and enable device interrupt */
513 i40e_pf_config_irq0(hw);
514 i40e_pf_enable_irq0(hw);
516 /* enable uio intr after callback register */
517 rte_intr_enable(&(pci_dev->intr_handle));
522 i40e_vsi_release(pf->main_vsi);
525 err_configure_lan_hmc:
526 (void)i40e_shutdown_lan_hmc(hw);
528 i40e_res_pool_destroy(&pf->msix_pool);
530 i40e_res_pool_destroy(&pf->qp_pool);
533 err_get_capabilities:
534 (void)i40e_shutdown_adminq(hw);
540 i40e_dev_configure(struct rte_eth_dev *dev)
543 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
546 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
547 * RSS setting have different requirements.
548 * General PMD driver call sequence are NIC init, configure,
549 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
550 * will try to lookup the VSI that specific queue belongs to if VMDQ
551 * applicable. So, VMDQ setting has to be done before
552 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
553 * For RSS setting, it will try to calculate actual configured RX queue
554 * number, which will be available after rx_queue_setup(). dev_start()
555 * function is good to place RSS setup.
557 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
558 ret = i40e_vmdq_setup(dev);
563 return i40e_dev_init_vlan(dev);
567 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
569 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
570 uint16_t msix_vect = vsi->msix_intr;
573 for (i = 0; i < vsi->nb_qps; i++) {
574 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
575 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
579 if (vsi->type != I40E_VSI_SRIOV) {
580 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
581 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
585 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
586 vsi->user_param + (msix_vect - 1);
588 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
590 I40E_WRITE_FLUSH(hw);
593 static inline uint16_t
594 i40e_calc_itr_interval(int16_t interval)
596 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
597 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
599 /* Convert to hardware count, as writing each 1 represents 2 us */
604 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
607 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
608 uint16_t msix_vect = vsi->msix_intr;
611 for (i = 0; i < vsi->nb_qps; i++)
612 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
614 /* Bind all RX queues to allocated MSIX interrupt */
615 for (i = 0; i < vsi->nb_qps; i++) {
616 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
617 I40E_QINT_RQCTL_ITR_INDX_MASK |
618 ((vsi->base_queue + i + 1) <<
619 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
620 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
621 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
623 if (i == vsi->nb_qps - 1)
624 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
625 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
628 /* Write first RX queue to Link list register as the head element */
629 if (vsi->type != I40E_VSI_SRIOV) {
631 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
633 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
635 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
636 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
638 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
639 msix_vect - 1), interval);
641 #ifndef I40E_GLINT_CTL
642 #define I40E_GLINT_CTL 0x0003F800
643 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
645 /* Disable auto-mask on enabling of all none-zero interrupt */
646 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
647 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
651 /* num_msix_vectors_vf needs to minus irq0 */
652 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
653 vsi->user_param + (msix_vect - 1);
655 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
656 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
657 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
660 I40E_WRITE_FLUSH(hw);
664 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
666 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
667 uint16_t interval = i40e_calc_itr_interval(\
668 RTE_LIBRTE_I40E_ITR_INTERVAL);
670 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
671 I40E_PFINT_DYN_CTLN_INTENA_MASK |
672 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
673 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
674 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
678 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
680 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
682 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
685 static inline uint8_t
686 i40e_parse_link_speed(uint16_t eth_link_speed)
688 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
690 switch (eth_link_speed) {
691 case ETH_LINK_SPEED_40G:
692 link_speed = I40E_LINK_SPEED_40GB;
694 case ETH_LINK_SPEED_20G:
695 link_speed = I40E_LINK_SPEED_20GB;
697 case ETH_LINK_SPEED_10G:
698 link_speed = I40E_LINK_SPEED_10GB;
700 case ETH_LINK_SPEED_1000:
701 link_speed = I40E_LINK_SPEED_1GB;
703 case ETH_LINK_SPEED_100:
704 link_speed = I40E_LINK_SPEED_100MB;
712 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
714 enum i40e_status_code status;
715 struct i40e_aq_get_phy_abilities_resp phy_ab;
716 struct i40e_aq_set_phy_config phy_conf;
717 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
718 I40E_AQ_PHY_FLAG_PAUSE_RX |
719 I40E_AQ_PHY_FLAG_LOW_POWER;
720 const uint8_t advt = I40E_LINK_SPEED_40GB |
721 I40E_LINK_SPEED_10GB |
722 I40E_LINK_SPEED_1GB |
723 I40E_LINK_SPEED_100MB;
726 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
731 memset(&phy_conf, 0, sizeof(phy_conf));
733 /* bits 0-2 use the values from get_phy_abilities_resp */
735 abilities |= phy_ab.abilities & mask;
737 /* update ablities and speed */
738 if (abilities & I40E_AQ_PHY_AN_ENABLED)
739 phy_conf.link_speed = advt;
741 phy_conf.link_speed = force_speed;
743 phy_conf.abilities = abilities;
745 /* use get_phy_abilities_resp value for the rest */
746 phy_conf.phy_type = phy_ab.phy_type;
747 phy_conf.eee_capability = phy_ab.eee_capability;
748 phy_conf.eeer = phy_ab.eeer_val;
749 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
751 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
752 phy_ab.abilities, phy_ab.link_speed);
753 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
754 phy_conf.abilities, phy_conf.link_speed);
756 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
764 i40e_apply_link_speed(struct rte_eth_dev *dev)
767 uint8_t abilities = 0;
768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
769 struct rte_eth_conf *conf = &dev->data->dev_conf;
771 speed = i40e_parse_link_speed(conf->link_speed);
772 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
773 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
774 abilities |= I40E_AQ_PHY_AN_ENABLED;
776 abilities |= I40E_AQ_PHY_LINK_ENABLED;
778 return i40e_phy_conf_link(hw, abilities, speed);
782 i40e_dev_start(struct rte_eth_dev *dev)
784 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
785 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
786 struct i40e_vsi *main_vsi = pf->main_vsi;
789 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
790 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
791 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
792 dev->data->dev_conf.link_duplex,
798 ret = i40e_dev_rxtx_init(pf);
799 if (ret != I40E_SUCCESS) {
800 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
804 /* Map queues with MSIX interrupt */
805 i40e_vsi_queues_bind_intr(main_vsi);
806 i40e_vsi_enable_queues_intr(main_vsi);
808 /* Map VMDQ VSI queues with MSIX interrupt */
809 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
810 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
811 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
814 /* Enable all queues which have been configured */
815 ret = i40e_dev_switch_queues(pf, TRUE);
816 if (ret != I40E_SUCCESS) {
817 PMD_DRV_LOG(ERR, "Failed to enable VSI");
821 /* Enable receiving broadcast packets */
822 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
823 if (ret != I40E_SUCCESS)
824 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
826 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
827 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
829 if (ret != I40E_SUCCESS)
830 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
833 /* Apply link configure */
834 ret = i40e_apply_link_speed(dev);
835 if (I40E_SUCCESS != ret) {
836 PMD_DRV_LOG(ERR, "Fail to apply link setting");
843 i40e_dev_switch_queues(pf, FALSE);
844 i40e_dev_clear_queues(dev);
850 i40e_dev_stop(struct rte_eth_dev *dev)
852 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
853 struct i40e_vsi *main_vsi = pf->main_vsi;
856 /* Disable all queues */
857 i40e_dev_switch_queues(pf, FALSE);
859 /* un-map queues with interrupt registers */
860 i40e_vsi_disable_queues_intr(main_vsi);
861 i40e_vsi_queues_unbind_intr(main_vsi);
863 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
864 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
865 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
868 /* Clear all queues and release memory */
869 i40e_dev_clear_queues(dev);
872 i40e_dev_set_link_down(dev);
876 i40e_dev_close(struct rte_eth_dev *dev)
878 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
879 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
882 PMD_INIT_FUNC_TRACE();
886 /* Disable interrupt */
887 i40e_pf_disable_irq0(hw);
888 rte_intr_disable(&(dev->pci_dev->intr_handle));
890 /* shutdown and destroy the HMC */
891 i40e_shutdown_lan_hmc(hw);
893 /* release all the existing VSIs and VEBs */
894 i40e_vsi_release(pf->main_vsi);
896 /* shutdown the adminq */
897 i40e_aq_queue_shutdown(hw, true);
898 i40e_shutdown_adminq(hw);
900 i40e_res_pool_destroy(&pf->qp_pool);
901 i40e_res_pool_destroy(&pf->msix_pool);
903 /* force a PF reset to clean anything leftover */
904 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
905 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
906 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
907 I40E_WRITE_FLUSH(hw);
911 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
913 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
914 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
915 struct i40e_vsi *vsi = pf->main_vsi;
918 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
920 if (status != I40E_SUCCESS)
921 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
923 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
925 if (status != I40E_SUCCESS)
926 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
931 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
935 struct i40e_vsi *vsi = pf->main_vsi;
938 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
940 if (status != I40E_SUCCESS)
941 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
943 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
945 if (status != I40E_SUCCESS)
946 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
950 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
952 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
954 struct i40e_vsi *vsi = pf->main_vsi;
957 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
958 if (ret != I40E_SUCCESS)
959 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
963 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
965 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
966 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
967 struct i40e_vsi *vsi = pf->main_vsi;
970 if (dev->data->promiscuous == 1)
971 return; /* must remain in all_multicast mode */
973 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
974 vsi->seid, FALSE, NULL);
975 if (ret != I40E_SUCCESS)
976 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
980 * Set device link up.
983 i40e_dev_set_link_up(struct rte_eth_dev *dev)
985 /* re-apply link speed setting */
986 return i40e_apply_link_speed(dev);
990 * Set device link down.
993 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
995 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
996 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
997 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
999 return i40e_phy_conf_link(hw, abilities, speed);
1003 i40e_dev_link_update(struct rte_eth_dev *dev,
1004 __rte_unused int wait_to_complete)
1006 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007 struct i40e_link_status link_status;
1008 struct rte_eth_link link, old;
1011 memset(&link, 0, sizeof(link));
1012 memset(&old, 0, sizeof(old));
1013 memset(&link_status, 0, sizeof(link_status));
1014 rte_i40e_dev_atomic_read_link_status(dev, &old);
1016 /* Get link status information from hardware */
1017 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1018 if (status != I40E_SUCCESS) {
1019 link.link_speed = ETH_LINK_SPEED_100;
1020 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1021 PMD_DRV_LOG(ERR, "Failed to get link info");
1025 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1027 if (!link.link_status)
1030 /* i40e uses full duplex only */
1031 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1033 /* Parse the link status */
1034 switch (link_status.link_speed) {
1035 case I40E_LINK_SPEED_100MB:
1036 link.link_speed = ETH_LINK_SPEED_100;
1038 case I40E_LINK_SPEED_1GB:
1039 link.link_speed = ETH_LINK_SPEED_1000;
1041 case I40E_LINK_SPEED_10GB:
1042 link.link_speed = ETH_LINK_SPEED_10G;
1044 case I40E_LINK_SPEED_20GB:
1045 link.link_speed = ETH_LINK_SPEED_20G;
1047 case I40E_LINK_SPEED_40GB:
1048 link.link_speed = ETH_LINK_SPEED_40G;
1051 link.link_speed = ETH_LINK_SPEED_100;
1056 rte_i40e_dev_atomic_write_link_status(dev, &link);
1057 if (link.link_status == old.link_status)
1063 /* Get all the statistics of a VSI */
1065 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1067 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1068 struct i40e_eth_stats *nes = &vsi->eth_stats;
1069 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1070 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1072 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1073 vsi->offset_loaded, &oes->rx_bytes,
1075 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1076 vsi->offset_loaded, &oes->rx_unicast,
1078 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1079 vsi->offset_loaded, &oes->rx_multicast,
1080 &nes->rx_multicast);
1081 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1082 vsi->offset_loaded, &oes->rx_broadcast,
1083 &nes->rx_broadcast);
1084 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1085 &oes->rx_discards, &nes->rx_discards);
1086 /* GLV_REPC not supported */
1087 /* GLV_RMPC not supported */
1088 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1089 &oes->rx_unknown_protocol,
1090 &nes->rx_unknown_protocol);
1091 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1092 vsi->offset_loaded, &oes->tx_bytes,
1094 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1095 vsi->offset_loaded, &oes->tx_unicast,
1097 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1098 vsi->offset_loaded, &oes->tx_multicast,
1099 &nes->tx_multicast);
1100 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1101 vsi->offset_loaded, &oes->tx_broadcast,
1102 &nes->tx_broadcast);
1103 /* GLV_TDPC not supported */
1104 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1105 &oes->tx_errors, &nes->tx_errors);
1106 vsi->offset_loaded = true;
1108 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1110 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", nes->rx_bytes);
1111 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", nes->rx_unicast);
1112 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", nes->rx_multicast);
1113 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", nes->rx_broadcast);
1114 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", nes->rx_discards);
1115 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1116 nes->rx_unknown_protocol);
1117 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", nes->tx_bytes);
1118 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", nes->tx_unicast);
1119 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", nes->tx_multicast);
1120 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", nes->tx_broadcast);
1121 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", nes->tx_discards);
1122 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", nes->tx_errors);
1123 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1127 /* Get all statistics of a port */
1129 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1133 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1134 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1135 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1137 /* Get statistics of struct i40e_eth_stats */
1138 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1139 I40E_GLPRT_GORCL(hw->port),
1140 pf->offset_loaded, &os->eth.rx_bytes,
1142 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1143 I40E_GLPRT_UPRCL(hw->port),
1144 pf->offset_loaded, &os->eth.rx_unicast,
1145 &ns->eth.rx_unicast);
1146 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1147 I40E_GLPRT_MPRCL(hw->port),
1148 pf->offset_loaded, &os->eth.rx_multicast,
1149 &ns->eth.rx_multicast);
1150 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1151 I40E_GLPRT_BPRCL(hw->port),
1152 pf->offset_loaded, &os->eth.rx_broadcast,
1153 &ns->eth.rx_broadcast);
1154 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1155 pf->offset_loaded, &os->eth.rx_discards,
1156 &ns->eth.rx_discards);
1157 /* GLPRT_REPC not supported */
1158 /* GLPRT_RMPC not supported */
1159 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1161 &os->eth.rx_unknown_protocol,
1162 &ns->eth.rx_unknown_protocol);
1163 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1164 I40E_GLPRT_GOTCL(hw->port),
1165 pf->offset_loaded, &os->eth.tx_bytes,
1167 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1168 I40E_GLPRT_UPTCL(hw->port),
1169 pf->offset_loaded, &os->eth.tx_unicast,
1170 &ns->eth.tx_unicast);
1171 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1172 I40E_GLPRT_MPTCL(hw->port),
1173 pf->offset_loaded, &os->eth.tx_multicast,
1174 &ns->eth.tx_multicast);
1175 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1176 I40E_GLPRT_BPTCL(hw->port),
1177 pf->offset_loaded, &os->eth.tx_broadcast,
1178 &ns->eth.tx_broadcast);
1179 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1180 pf->offset_loaded, &os->eth.tx_discards,
1181 &ns->eth.tx_discards);
1182 /* GLPRT_TEPC not supported */
1184 /* additional port specific stats */
1185 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1186 pf->offset_loaded, &os->tx_dropped_link_down,
1187 &ns->tx_dropped_link_down);
1188 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1189 pf->offset_loaded, &os->crc_errors,
1191 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1192 pf->offset_loaded, &os->illegal_bytes,
1193 &ns->illegal_bytes);
1194 /* GLPRT_ERRBC not supported */
1195 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1196 pf->offset_loaded, &os->mac_local_faults,
1197 &ns->mac_local_faults);
1198 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1199 pf->offset_loaded, &os->mac_remote_faults,
1200 &ns->mac_remote_faults);
1201 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1202 pf->offset_loaded, &os->rx_length_errors,
1203 &ns->rx_length_errors);
1204 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1205 pf->offset_loaded, &os->link_xon_rx,
1207 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1208 pf->offset_loaded, &os->link_xoff_rx,
1210 for (i = 0; i < 8; i++) {
1211 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1213 &os->priority_xon_rx[i],
1214 &ns->priority_xon_rx[i]);
1215 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1217 &os->priority_xoff_rx[i],
1218 &ns->priority_xoff_rx[i]);
1220 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1221 pf->offset_loaded, &os->link_xon_tx,
1223 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1224 pf->offset_loaded, &os->link_xoff_tx,
1226 for (i = 0; i < 8; i++) {
1227 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1229 &os->priority_xon_tx[i],
1230 &ns->priority_xon_tx[i]);
1231 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1233 &os->priority_xoff_tx[i],
1234 &ns->priority_xoff_tx[i]);
1235 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1237 &os->priority_xon_2_xoff[i],
1238 &ns->priority_xon_2_xoff[i]);
1240 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1241 I40E_GLPRT_PRC64L(hw->port),
1242 pf->offset_loaded, &os->rx_size_64,
1244 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1245 I40E_GLPRT_PRC127L(hw->port),
1246 pf->offset_loaded, &os->rx_size_127,
1248 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1249 I40E_GLPRT_PRC255L(hw->port),
1250 pf->offset_loaded, &os->rx_size_255,
1252 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1253 I40E_GLPRT_PRC511L(hw->port),
1254 pf->offset_loaded, &os->rx_size_511,
1256 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1257 I40E_GLPRT_PRC1023L(hw->port),
1258 pf->offset_loaded, &os->rx_size_1023,
1260 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1261 I40E_GLPRT_PRC1522L(hw->port),
1262 pf->offset_loaded, &os->rx_size_1522,
1264 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1265 I40E_GLPRT_PRC9522L(hw->port),
1266 pf->offset_loaded, &os->rx_size_big,
1268 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1269 pf->offset_loaded, &os->rx_undersize,
1271 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1272 pf->offset_loaded, &os->rx_fragments,
1274 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1275 pf->offset_loaded, &os->rx_oversize,
1277 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1278 pf->offset_loaded, &os->rx_jabber,
1280 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1281 I40E_GLPRT_PTC64L(hw->port),
1282 pf->offset_loaded, &os->tx_size_64,
1284 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1285 I40E_GLPRT_PTC127L(hw->port),
1286 pf->offset_loaded, &os->tx_size_127,
1288 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1289 I40E_GLPRT_PTC255L(hw->port),
1290 pf->offset_loaded, &os->tx_size_255,
1292 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1293 I40E_GLPRT_PTC511L(hw->port),
1294 pf->offset_loaded, &os->tx_size_511,
1296 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1297 I40E_GLPRT_PTC1023L(hw->port),
1298 pf->offset_loaded, &os->tx_size_1023,
1300 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1301 I40E_GLPRT_PTC1522L(hw->port),
1302 pf->offset_loaded, &os->tx_size_1522,
1304 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1305 I40E_GLPRT_PTC9522L(hw->port),
1306 pf->offset_loaded, &os->tx_size_big,
1308 /* GLPRT_MSPDC not supported */
1309 /* GLPRT_XEC not supported */
1311 pf->offset_loaded = true;
1314 i40e_update_vsi_stats(pf->main_vsi);
1316 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1317 ns->eth.rx_broadcast;
1318 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1319 ns->eth.tx_broadcast;
1320 stats->ibytes = ns->eth.rx_bytes;
1321 stats->obytes = ns->eth.tx_bytes;
1322 stats->oerrors = ns->eth.tx_errors;
1323 stats->imcasts = ns->eth.rx_multicast;
1326 stats->ibadcrc = ns->crc_errors;
1327 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1328 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1329 stats->imissed = ns->eth.rx_discards;
1330 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1332 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1333 PMD_DRV_LOG(DEBUG, "rx_bytes: %lu", ns->eth.rx_bytes);
1334 PMD_DRV_LOG(DEBUG, "rx_unicast: %lu", ns->eth.rx_unicast);
1335 PMD_DRV_LOG(DEBUG, "rx_multicast: %lu", ns->eth.rx_multicast);
1336 PMD_DRV_LOG(DEBUG, "rx_broadcast: %lu", ns->eth.rx_broadcast);
1337 PMD_DRV_LOG(DEBUG, "rx_discards: %lu", ns->eth.rx_discards);
1338 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1339 ns->eth.rx_unknown_protocol);
1340 PMD_DRV_LOG(DEBUG, "tx_bytes: %lu", ns->eth.tx_bytes);
1341 PMD_DRV_LOG(DEBUG, "tx_unicast: %lu", ns->eth.tx_unicast);
1342 PMD_DRV_LOG(DEBUG, "tx_multicast: %lu", ns->eth.tx_multicast);
1343 PMD_DRV_LOG(DEBUG, "tx_broadcast: %lu", ns->eth.tx_broadcast);
1344 PMD_DRV_LOG(DEBUG, "tx_discards: %lu", ns->eth.tx_discards);
1345 PMD_DRV_LOG(DEBUG, "tx_errors: %lu", ns->eth.tx_errors);
1347 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %lu",
1348 ns->tx_dropped_link_down);
1349 PMD_DRV_LOG(DEBUG, "crc_errors: %lu", ns->crc_errors);
1350 PMD_DRV_LOG(DEBUG, "illegal_bytes: %lu",
1352 PMD_DRV_LOG(DEBUG, "error_bytes: %lu", ns->error_bytes);
1353 PMD_DRV_LOG(DEBUG, "mac_local_faults: %lu",
1354 ns->mac_local_faults);
1355 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %lu",
1356 ns->mac_remote_faults);
1357 PMD_DRV_LOG(DEBUG, "rx_length_errors: %lu",
1358 ns->rx_length_errors);
1359 PMD_DRV_LOG(DEBUG, "link_xon_rx: %lu", ns->link_xon_rx);
1360 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %lu", ns->link_xoff_rx);
1361 for (i = 0; i < 8; i++) {
1362 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %lu",
1363 i, ns->priority_xon_rx[i]);
1364 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %lu",
1365 i, ns->priority_xoff_rx[i]);
1367 PMD_DRV_LOG(DEBUG, "link_xon_tx: %lu", ns->link_xon_tx);
1368 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %lu", ns->link_xoff_tx);
1369 for (i = 0; i < 8; i++) {
1370 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %lu",
1371 i, ns->priority_xon_tx[i]);
1372 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %lu",
1373 i, ns->priority_xoff_tx[i]);
1374 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %lu",
1375 i, ns->priority_xon_2_xoff[i]);
1377 PMD_DRV_LOG(DEBUG, "rx_size_64: %lu", ns->rx_size_64);
1378 PMD_DRV_LOG(DEBUG, "rx_size_127: %lu", ns->rx_size_127);
1379 PMD_DRV_LOG(DEBUG, "rx_size_255: %lu", ns->rx_size_255);
1380 PMD_DRV_LOG(DEBUG, "rx_size_511: %lu", ns->rx_size_511);
1381 PMD_DRV_LOG(DEBUG, "rx_size_1023: %lu", ns->rx_size_1023);
1382 PMD_DRV_LOG(DEBUG, "rx_size_1522: %lu", ns->rx_size_1522);
1383 PMD_DRV_LOG(DEBUG, "rx_size_big: %lu", ns->rx_size_big);
1384 PMD_DRV_LOG(DEBUG, "rx_undersize: %lu", ns->rx_undersize);
1385 PMD_DRV_LOG(DEBUG, "rx_fragments: %lu", ns->rx_fragments);
1386 PMD_DRV_LOG(DEBUG, "rx_oversize: %lu", ns->rx_oversize);
1387 PMD_DRV_LOG(DEBUG, "rx_jabber: %lu", ns->rx_jabber);
1388 PMD_DRV_LOG(DEBUG, "tx_size_64: %lu", ns->tx_size_64);
1389 PMD_DRV_LOG(DEBUG, "tx_size_127: %lu", ns->tx_size_127);
1390 PMD_DRV_LOG(DEBUG, "tx_size_255: %lu", ns->tx_size_255);
1391 PMD_DRV_LOG(DEBUG, "tx_size_511: %lu", ns->tx_size_511);
1392 PMD_DRV_LOG(DEBUG, "tx_size_1023: %lu", ns->tx_size_1023);
1393 PMD_DRV_LOG(DEBUG, "tx_size_1522: %lu", ns->tx_size_1522);
1394 PMD_DRV_LOG(DEBUG, "tx_size_big: %lu", ns->tx_size_big);
1395 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1396 ns->mac_short_packet_dropped);
1397 PMD_DRV_LOG(DEBUG, "checksum_error: %lu",
1398 ns->checksum_error);
1399 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1402 /* Reset the statistics */
1404 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1406 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1408 /* It results in reloading the start point of each counter */
1409 pf->offset_loaded = false;
1413 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1414 __rte_unused uint16_t queue_id,
1415 __rte_unused uint8_t stat_idx,
1416 __rte_unused uint8_t is_rx)
1418 PMD_INIT_FUNC_TRACE();
1424 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1426 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427 struct i40e_vsi *vsi = pf->main_vsi;
1429 dev_info->max_rx_queues = vsi->nb_qps;
1430 dev_info->max_tx_queues = vsi->nb_qps;
1431 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1432 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1433 dev_info->max_mac_addrs = vsi->max_macaddrs;
1434 dev_info->max_vfs = dev->pci_dev->max_vfs;
1435 dev_info->rx_offload_capa =
1436 DEV_RX_OFFLOAD_VLAN_STRIP |
1437 DEV_RX_OFFLOAD_IPV4_CKSUM |
1438 DEV_RX_OFFLOAD_UDP_CKSUM |
1439 DEV_RX_OFFLOAD_TCP_CKSUM;
1440 dev_info->tx_offload_capa =
1441 DEV_TX_OFFLOAD_VLAN_INSERT |
1442 DEV_TX_OFFLOAD_IPV4_CKSUM |
1443 DEV_TX_OFFLOAD_UDP_CKSUM |
1444 DEV_TX_OFFLOAD_TCP_CKSUM |
1445 DEV_TX_OFFLOAD_SCTP_CKSUM;
1447 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1449 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1450 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1451 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1453 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1457 dev_info->default_txconf = (struct rte_eth_txconf) {
1459 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1460 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1461 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1463 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1464 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1465 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1468 if (pf->flags | I40E_FLAG_VMDQ) {
1469 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1470 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1471 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1472 pf->max_nb_vmdq_vsi;
1473 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1474 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1475 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1480 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1482 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1483 struct i40e_vsi *vsi = pf->main_vsi;
1484 PMD_INIT_FUNC_TRACE();
1487 return i40e_vsi_add_vlan(vsi, vlan_id);
1489 return i40e_vsi_delete_vlan(vsi, vlan_id);
1493 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1494 __rte_unused uint16_t tpid)
1496 PMD_INIT_FUNC_TRACE();
1500 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1502 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1503 struct i40e_vsi *vsi = pf->main_vsi;
1505 if (mask & ETH_VLAN_STRIP_MASK) {
1506 /* Enable or disable VLAN stripping */
1507 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1508 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1510 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1513 if (mask & ETH_VLAN_EXTEND_MASK) {
1514 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1515 i40e_vsi_config_double_vlan(vsi, TRUE);
1517 i40e_vsi_config_double_vlan(vsi, FALSE);
1522 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1523 __rte_unused uint16_t queue,
1524 __rte_unused int on)
1526 PMD_INIT_FUNC_TRACE();
1530 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1532 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1533 struct i40e_vsi *vsi = pf->main_vsi;
1534 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1535 struct i40e_vsi_vlan_pvid_info info;
1537 memset(&info, 0, sizeof(info));
1540 info.config.pvid = pvid;
1542 info.config.reject.tagged =
1543 data->dev_conf.txmode.hw_vlan_reject_tagged;
1544 info.config.reject.untagged =
1545 data->dev_conf.txmode.hw_vlan_reject_untagged;
1548 return i40e_vsi_vlan_pvid_set(vsi, &info);
1552 i40e_dev_led_on(struct rte_eth_dev *dev)
1554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 uint32_t mode = i40e_led_get(hw);
1558 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1564 i40e_dev_led_off(struct rte_eth_dev *dev)
1566 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 uint32_t mode = i40e_led_get(hw);
1570 i40e_led_set(hw, 0, false);
1576 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1577 __rte_unused struct rte_eth_fc_conf *fc_conf)
1579 PMD_INIT_FUNC_TRACE();
1585 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1586 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1588 PMD_INIT_FUNC_TRACE();
1593 /* Add a MAC address, and update filters */
1595 i40e_macaddr_add(struct rte_eth_dev *dev,
1596 struct ether_addr *mac_addr,
1597 __rte_unused uint32_t index,
1600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1601 struct i40e_mac_filter_info mac_filter;
1602 struct i40e_vsi *vsi;
1605 /* If VMDQ not enabled or configured, return */
1606 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1607 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1608 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1613 if (pool > pf->nb_cfg_vmdq_vsi) {
1614 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1615 pool, pf->nb_cfg_vmdq_vsi);
1619 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1620 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1625 vsi = pf->vmdq[pool - 1].vsi;
1627 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1628 if (ret != I40E_SUCCESS) {
1629 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1634 /* Remove a MAC address, and update filters */
1636 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1638 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1639 struct i40e_vsi *vsi;
1640 struct rte_eth_dev_data *data = dev->data;
1641 struct ether_addr *macaddr;
1646 macaddr = &(data->mac_addrs[index]);
1648 pool_sel = dev->data->mac_pool_sel[index];
1650 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1651 if (pool_sel & (1ULL << i)) {
1655 /* No VMDQ pool enabled or configured */
1656 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1657 (i > pf->nb_cfg_vmdq_vsi)) {
1658 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1662 vsi = pf->vmdq[i - 1].vsi;
1664 ret = i40e_vsi_delete_mac(vsi, macaddr);
1667 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1674 /* Set perfect match or hash match of MAC and VLAN for a VF */
1676 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1677 struct rte_eth_mac_filter *filter,
1681 struct i40e_mac_filter_info mac_filter;
1682 struct ether_addr old_mac;
1683 struct ether_addr *new_mac;
1684 struct i40e_pf_vf *vf = NULL;
1689 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1692 hw = I40E_PF_TO_HW(pf);
1694 if (filter == NULL) {
1695 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1699 new_mac = &filter->mac_addr;
1701 if (is_zero_ether_addr(new_mac)) {
1702 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1706 vf_id = filter->dst_id;
1708 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1709 PMD_DRV_LOG(ERR, "Invalid argument.");
1712 vf = &pf->vfs[vf_id];
1714 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1715 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1720 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1721 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1723 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1726 mac_filter.filter_type = filter->filter_type;
1727 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1728 if (ret != I40E_SUCCESS) {
1729 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1732 ether_addr_copy(new_mac, &pf->dev_addr);
1734 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1736 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1737 if (ret != I40E_SUCCESS) {
1738 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1742 /* Clear device address as it has been removed */
1743 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1744 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1750 /* MAC filter handle */
1752 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1756 struct rte_eth_mac_filter *filter;
1757 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1758 int ret = I40E_NOT_SUPPORTED;
1760 filter = (struct rte_eth_mac_filter *)(arg);
1762 switch (filter_op) {
1763 case RTE_ETH_FILTER_NONE:
1766 case RTE_ETH_FILTER_ADD:
1767 i40e_pf_disable_irq0(hw);
1769 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1770 i40e_pf_enable_irq0(hw);
1772 case RTE_ETH_FILTER_DELETE:
1773 i40e_pf_disable_irq0(hw);
1775 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1776 i40e_pf_enable_irq0(hw);
1779 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1780 ret = I40E_ERR_PARAM;
1788 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1789 struct rte_eth_rss_reta *reta_conf)
1791 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1795 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1797 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1799 mask = (uint8_t)((reta_conf->mask_hi >>
1808 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1810 for (j = 0, lut = 0; j < 4; j++) {
1811 if (mask & (0x1 << j))
1812 lut |= reta_conf->reta[i + j] << (8 * j);
1814 lut |= l & (0xFF << (8 * j));
1816 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1823 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1824 struct rte_eth_rss_reta *reta_conf)
1826 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1830 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1832 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1834 mask = (uint8_t)((reta_conf->mask_hi >>
1840 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1841 for (j = 0; j < 4; j++) {
1842 if (mask & (0x1 << j))
1843 reta_conf->reta[i + j] =
1844 (uint8_t)((lut >> (8 * j)) & 0xFF);
1852 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1853 * @hw: pointer to the HW structure
1854 * @mem: pointer to mem struct to fill out
1855 * @size: size of memory requested
1856 * @alignment: what to align the allocation to
1858 enum i40e_status_code
1859 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1860 struct i40e_dma_mem *mem,
1864 static uint64_t id = 0;
1865 const struct rte_memzone *mz = NULL;
1866 char z_name[RTE_MEMZONE_NAMESIZE];
1869 return I40E_ERR_PARAM;
1872 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1873 #ifdef RTE_LIBRTE_XEN_DOM0
1874 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1877 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1880 return I40E_ERR_NO_MEMORY;
1885 #ifdef RTE_LIBRTE_XEN_DOM0
1886 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1888 mem->pa = mz->phys_addr;
1891 return I40E_SUCCESS;
1895 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1896 * @hw: pointer to the HW structure
1897 * @mem: ptr to mem struct to free
1899 enum i40e_status_code
1900 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1901 struct i40e_dma_mem *mem)
1903 if (!mem || !mem->va)
1904 return I40E_ERR_PARAM;
1909 return I40E_SUCCESS;
1913 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1914 * @hw: pointer to the HW structure
1915 * @mem: pointer to mem struct to fill out
1916 * @size: size of memory requested
1918 enum i40e_status_code
1919 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1920 struct i40e_virt_mem *mem,
1924 return I40E_ERR_PARAM;
1927 mem->va = rte_zmalloc("i40e", size, 0);
1930 return I40E_SUCCESS;
1932 return I40E_ERR_NO_MEMORY;
1936 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1937 * @hw: pointer to the HW structure
1938 * @mem: pointer to mem struct to free
1940 enum i40e_status_code
1941 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1942 struct i40e_virt_mem *mem)
1945 return I40E_ERR_PARAM;
1950 return I40E_SUCCESS;
1954 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1956 rte_spinlock_init(&sp->spinlock);
1960 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1962 rte_spinlock_lock(&sp->spinlock);
1966 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1968 rte_spinlock_unlock(&sp->spinlock);
1972 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1978 * Get the hardware capabilities, which will be parsed
1979 * and saved into struct i40e_hw.
1982 i40e_get_cap(struct i40e_hw *hw)
1984 struct i40e_aqc_list_capabilities_element_resp *buf;
1985 uint16_t len, size = 0;
1988 /* Calculate a huge enough buff for saving response data temporarily */
1989 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1990 I40E_MAX_CAP_ELE_NUM;
1991 buf = rte_zmalloc("i40e", len, 0);
1993 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1994 return I40E_ERR_NO_MEMORY;
1997 /* Get, parse the capabilities and save it to hw */
1998 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1999 i40e_aqc_opc_list_func_capabilities, NULL);
2000 if (ret != I40E_SUCCESS)
2001 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2003 /* Free the temporary buffer after being used */
2010 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2012 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2013 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2014 uint16_t sum_queues = 0, sum_vsis, left_queues;
2016 /* First check if FW support SRIOV */
2017 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2018 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2022 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2023 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2024 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2025 /* Allocate queues for pf */
2026 if (hw->func_caps.rss) {
2027 pf->flags |= I40E_FLAG_RSS;
2028 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2029 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2030 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2033 sum_queues = pf->lan_nb_qps;
2034 /* Default VSI is not counted in */
2036 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2038 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2039 pf->flags |= I40E_FLAG_SRIOV;
2040 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2041 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2042 PMD_INIT_LOG(ERR, "Config VF number %u, "
2043 "max supported %u.",
2044 dev->pci_dev->max_vfs,
2045 hw->func_caps.num_vfs);
2048 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2049 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2050 "max support %u queues.",
2051 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2054 pf->vf_num = dev->pci_dev->max_vfs;
2055 sum_queues += pf->vf_nb_qps * pf->vf_num;
2056 sum_vsis += pf->vf_num;
2057 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2058 pf->vf_num, pf->vf_nb_qps);
2062 if (hw->func_caps.vmdq) {
2063 pf->flags |= I40E_FLAG_VMDQ;
2064 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2065 pf->max_nb_vmdq_vsi = 1;
2067 * If VMDQ available, assume a single VSI can be created. Will adjust
2070 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2071 sum_vsis += pf->max_nb_vmdq_vsi;
2073 pf->vmdq_nb_qps = 0;
2074 pf->max_nb_vmdq_vsi = 0;
2076 pf->nb_cfg_vmdq_vsi = 0;
2078 if (hw->func_caps.fd) {
2079 pf->flags |= I40E_FLAG_FDIR;
2080 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2082 * Each flow director consumes one VSI and one queue,
2083 * but can't calculate out predictably here.
2087 if (sum_vsis > pf->max_num_vsi ||
2088 sum_queues > hw->func_caps.num_rx_qp) {
2089 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2090 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2091 pf->max_num_vsi, sum_vsis);
2092 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2093 hw->func_caps.num_rx_qp, sum_queues);
2097 /* Adjust VMDQ setting to support as many VMs as possible */
2098 if (pf->flags & I40E_FLAG_VMDQ) {
2099 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2101 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2102 pf->max_num_vsi - sum_vsis);
2104 /* Limit the max VMDQ number that rte_ether that can support */
2105 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2108 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2109 pf->max_nb_vmdq_vsi);
2110 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2113 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2115 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2116 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2117 sum_vsis, hw->func_caps.num_msix_vectors);
2120 return I40E_SUCCESS;
2124 i40e_pf_get_switch_config(struct i40e_pf *pf)
2126 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2127 struct i40e_aqc_get_switch_config_resp *switch_config;
2128 struct i40e_aqc_switch_config_element_resp *element;
2129 uint16_t start_seid = 0, num_reported;
2132 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2133 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2134 if (!switch_config) {
2135 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2139 /* Get the switch configurations */
2140 ret = i40e_aq_get_switch_config(hw, switch_config,
2141 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2142 if (ret != I40E_SUCCESS) {
2143 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2146 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2147 if (num_reported != 1) { /* The number should be 1 */
2148 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2152 /* Parse the switch configuration elements */
2153 element = &(switch_config->element[0]);
2154 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2155 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2156 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2158 PMD_DRV_LOG(INFO, "Unknown element type");
2161 rte_free(switch_config);
2167 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2170 struct pool_entry *entry;
2172 if (pool == NULL || num == 0)
2175 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2176 if (entry == NULL) {
2177 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2181 /* queue heap initialize */
2182 pool->num_free = num;
2183 pool->num_alloc = 0;
2185 LIST_INIT(&pool->alloc_list);
2186 LIST_INIT(&pool->free_list);
2188 /* Initialize element */
2192 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2197 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2199 struct pool_entry *entry;
2204 LIST_FOREACH(entry, &pool->alloc_list, next) {
2205 LIST_REMOVE(entry, next);
2209 LIST_FOREACH(entry, &pool->free_list, next) {
2210 LIST_REMOVE(entry, next);
2215 pool->num_alloc = 0;
2217 LIST_INIT(&pool->alloc_list);
2218 LIST_INIT(&pool->free_list);
2222 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2225 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2226 uint32_t pool_offset;
2230 PMD_DRV_LOG(ERR, "Invalid parameter");
2234 pool_offset = base - pool->base;
2235 /* Lookup in alloc list */
2236 LIST_FOREACH(entry, &pool->alloc_list, next) {
2237 if (entry->base == pool_offset) {
2238 valid_entry = entry;
2239 LIST_REMOVE(entry, next);
2244 /* Not find, return */
2245 if (valid_entry == NULL) {
2246 PMD_DRV_LOG(ERR, "Failed to find entry");
2251 * Found it, move it to free list and try to merge.
2252 * In order to make merge easier, always sort it by qbase.
2253 * Find adjacent prev and last entries.
2256 LIST_FOREACH(entry, &pool->free_list, next) {
2257 if (entry->base > valid_entry->base) {
2265 /* Try to merge with next one*/
2267 /* Merge with next one */
2268 if (valid_entry->base + valid_entry->len == next->base) {
2269 next->base = valid_entry->base;
2270 next->len += valid_entry->len;
2271 rte_free(valid_entry);
2278 /* Merge with previous one */
2279 if (prev->base + prev->len == valid_entry->base) {
2280 prev->len += valid_entry->len;
2281 /* If it merge with next one, remove next node */
2283 LIST_REMOVE(valid_entry, next);
2284 rte_free(valid_entry);
2286 rte_free(valid_entry);
2292 /* Not find any entry to merge, insert */
2295 LIST_INSERT_AFTER(prev, valid_entry, next);
2296 else if (next != NULL)
2297 LIST_INSERT_BEFORE(next, valid_entry, next);
2298 else /* It's empty list, insert to head */
2299 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2302 pool->num_free += valid_entry->len;
2303 pool->num_alloc -= valid_entry->len;
2309 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2312 struct pool_entry *entry, *valid_entry;
2314 if (pool == NULL || num == 0) {
2315 PMD_DRV_LOG(ERR, "Invalid parameter");
2319 if (pool->num_free < num) {
2320 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2321 num, pool->num_free);
2326 /* Lookup in free list and find most fit one */
2327 LIST_FOREACH(entry, &pool->free_list, next) {
2328 if (entry->len >= num) {
2330 if (entry->len == num) {
2331 valid_entry = entry;
2334 if (valid_entry == NULL || valid_entry->len > entry->len)
2335 valid_entry = entry;
2339 /* Not find one to satisfy the request, return */
2340 if (valid_entry == NULL) {
2341 PMD_DRV_LOG(ERR, "No valid entry found");
2345 * The entry have equal queue number as requested,
2346 * remove it from alloc_list.
2348 if (valid_entry->len == num) {
2349 LIST_REMOVE(valid_entry, next);
2352 * The entry have more numbers than requested,
2353 * create a new entry for alloc_list and minus its
2354 * queue base and number in free_list.
2356 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2357 if (entry == NULL) {
2358 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2362 entry->base = valid_entry->base;
2364 valid_entry->base += num;
2365 valid_entry->len -= num;
2366 valid_entry = entry;
2369 /* Insert it into alloc list, not sorted */
2370 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2372 pool->num_free -= valid_entry->len;
2373 pool->num_alloc += valid_entry->len;
2375 return (valid_entry->base + pool->base);
2379 * bitmap_is_subset - Check whether src2 is subset of src1
2382 bitmap_is_subset(uint8_t src1, uint8_t src2)
2384 return !((src1 ^ src2) & src2);
2388 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2390 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2392 /* If DCB is not supported, only default TC is supported */
2393 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2394 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2398 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2399 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2400 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2404 return I40E_SUCCESS;
2408 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2409 struct i40e_vsi_vlan_pvid_info *info)
2412 struct i40e_vsi_context ctxt;
2413 uint8_t vlan_flags = 0;
2416 if (vsi == NULL || info == NULL) {
2417 PMD_DRV_LOG(ERR, "invalid parameters");
2418 return I40E_ERR_PARAM;
2422 vsi->info.pvid = info->config.pvid;
2424 * If insert pvid is enabled, only tagged pkts are
2425 * allowed to be sent out.
2427 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2428 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2431 if (info->config.reject.tagged == 0)
2432 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2434 if (info->config.reject.untagged == 0)
2435 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2437 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2438 I40E_AQ_VSI_PVLAN_MODE_MASK);
2439 vsi->info.port_vlan_flags |= vlan_flags;
2440 vsi->info.valid_sections =
2441 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2442 memset(&ctxt, 0, sizeof(ctxt));
2443 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2444 ctxt.seid = vsi->seid;
2446 hw = I40E_VSI_TO_HW(vsi);
2447 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2448 if (ret != I40E_SUCCESS)
2449 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2455 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2457 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2459 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2461 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2462 if (ret != I40E_SUCCESS)
2466 PMD_DRV_LOG(ERR, "seid not valid");
2470 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2471 tc_bw_data.tc_valid_bits = enabled_tcmap;
2472 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2473 tc_bw_data.tc_bw_credits[i] =
2474 (enabled_tcmap & (1 << i)) ? 1 : 0;
2476 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2477 if (ret != I40E_SUCCESS) {
2478 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2482 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2483 sizeof(vsi->info.qs_handle));
2484 return I40E_SUCCESS;
2488 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2489 struct i40e_aqc_vsi_properties_data *info,
2490 uint8_t enabled_tcmap)
2492 int ret, total_tc = 0, i;
2493 uint16_t qpnum_per_tc, bsf, qp_idx;
2495 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2496 if (ret != I40E_SUCCESS)
2499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2500 if (enabled_tcmap & (1 << i))
2502 vsi->enabled_tc = enabled_tcmap;
2504 /* Number of queues per enabled TC */
2505 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2506 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2507 bsf = rte_bsf32(qpnum_per_tc);
2509 /* Adjust the queue number to actual queues that can be applied */
2510 vsi->nb_qps = qpnum_per_tc * total_tc;
2513 * Configure TC and queue mapping parameters, for enabled TC,
2514 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2515 * default queue will serve it.
2518 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2519 if (vsi->enabled_tc & (1 << i)) {
2520 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2521 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2522 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2523 qp_idx += qpnum_per_tc;
2525 info->tc_mapping[i] = 0;
2528 /* Associate queue number with VSI */
2529 if (vsi->type == I40E_VSI_SRIOV) {
2530 info->mapping_flags |=
2531 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2532 for (i = 0; i < vsi->nb_qps; i++)
2533 info->queue_mapping[i] =
2534 rte_cpu_to_le_16(vsi->base_queue + i);
2536 info->mapping_flags |=
2537 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2538 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2540 info->valid_sections =
2541 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2543 return I40E_SUCCESS;
2547 i40e_veb_release(struct i40e_veb *veb)
2549 struct i40e_vsi *vsi;
2552 if (veb == NULL || veb->associate_vsi == NULL)
2555 if (!TAILQ_EMPTY(&veb->head)) {
2556 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2560 vsi = veb->associate_vsi;
2561 hw = I40E_VSI_TO_HW(vsi);
2563 vsi->uplink_seid = veb->uplink_seid;
2564 i40e_aq_delete_element(hw, veb->seid, NULL);
2567 return I40E_SUCCESS;
2571 static struct i40e_veb *
2572 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2574 struct i40e_veb *veb;
2578 if (NULL == pf || vsi == NULL) {
2579 PMD_DRV_LOG(ERR, "veb setup failed, "
2580 "associated VSI shouldn't null");
2583 hw = I40E_PF_TO_HW(pf);
2585 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2587 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2591 veb->associate_vsi = vsi;
2592 TAILQ_INIT(&veb->head);
2593 veb->uplink_seid = vsi->uplink_seid;
2595 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2596 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2598 if (ret != I40E_SUCCESS) {
2599 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2600 hw->aq.asq_last_status);
2604 /* get statistics index */
2605 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2606 &veb->stats_idx, NULL, NULL, NULL);
2607 if (ret != I40E_SUCCESS) {
2608 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2609 hw->aq.asq_last_status);
2613 /* Get VEB bandwidth, to be implemented */
2614 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2615 vsi->uplink_seid = veb->seid;
2624 i40e_vsi_release(struct i40e_vsi *vsi)
2628 struct i40e_vsi_list *vsi_list;
2630 struct i40e_mac_filter *f;
2633 return I40E_SUCCESS;
2635 pf = I40E_VSI_TO_PF(vsi);
2636 hw = I40E_VSI_TO_HW(vsi);
2638 /* VSI has child to attach, release child first */
2640 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2641 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2643 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2645 i40e_veb_release(vsi->veb);
2648 /* Remove all macvlan filters of the VSI */
2649 i40e_vsi_remove_all_macvlan_filter(vsi);
2650 TAILQ_FOREACH(f, &vsi->mac_list, next)
2653 if (vsi->type != I40E_VSI_MAIN) {
2654 /* Remove vsi from parent's sibling list */
2655 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2656 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2657 return I40E_ERR_PARAM;
2659 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2660 &vsi->sib_vsi_list, list);
2662 /* Remove all switch element of the VSI */
2663 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2664 if (ret != I40E_SUCCESS)
2665 PMD_DRV_LOG(ERR, "Failed to delete element");
2667 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2669 if (vsi->type != I40E_VSI_SRIOV)
2670 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2673 return I40E_SUCCESS;
2677 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2679 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2680 struct i40e_aqc_remove_macvlan_element_data def_filter;
2681 struct i40e_mac_filter_info filter;
2684 if (vsi->type != I40E_VSI_MAIN)
2685 return I40E_ERR_CONFIG;
2686 memset(&def_filter, 0, sizeof(def_filter));
2687 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2689 def_filter.vlan_tag = 0;
2690 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2691 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2692 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2693 if (ret != I40E_SUCCESS) {
2694 struct i40e_mac_filter *f;
2695 struct ether_addr *mac;
2697 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2699 /* It needs to add the permanent mac into mac list */
2700 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2702 PMD_DRV_LOG(ERR, "failed to allocate memory");
2703 return I40E_ERR_NO_MEMORY;
2705 mac = &f->mac_info.mac_addr;
2706 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2708 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2709 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2714 (void)rte_memcpy(&filter.mac_addr,
2715 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2716 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2717 return i40e_vsi_add_mac(vsi, &filter);
2721 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2723 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2724 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2725 struct i40e_hw *hw = &vsi->adapter->hw;
2729 memset(&bw_config, 0, sizeof(bw_config));
2730 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2731 if (ret != I40E_SUCCESS) {
2732 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2733 hw->aq.asq_last_status);
2737 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2738 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2739 &ets_sla_config, NULL);
2740 if (ret != I40E_SUCCESS) {
2741 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2742 "configuration %u", hw->aq.asq_last_status);
2746 /* Not store the info yet, just print out */
2747 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2748 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2749 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2750 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2751 ets_sla_config.share_credits[i]);
2752 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2753 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2754 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2755 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2764 i40e_vsi_setup(struct i40e_pf *pf,
2765 enum i40e_vsi_type type,
2766 struct i40e_vsi *uplink_vsi,
2767 uint16_t user_param)
2769 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2770 struct i40e_vsi *vsi;
2771 struct i40e_mac_filter_info filter;
2773 struct i40e_vsi_context ctxt;
2774 struct ether_addr broadcast =
2775 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2777 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2778 PMD_DRV_LOG(ERR, "VSI setup failed, "
2779 "VSI link shouldn't be NULL");
2783 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2784 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2785 "uplink VSI should be NULL");
2789 /* If uplink vsi didn't setup VEB, create one first */
2790 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2791 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2793 if (NULL == uplink_vsi->veb) {
2794 PMD_DRV_LOG(ERR, "VEB setup failed");
2799 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2801 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2804 TAILQ_INIT(&vsi->mac_list);
2806 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2807 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2808 vsi->parent_vsi = uplink_vsi;
2809 vsi->user_param = user_param;
2810 /* Allocate queues */
2811 switch (vsi->type) {
2812 case I40E_VSI_MAIN :
2813 vsi->nb_qps = pf->lan_nb_qps;
2815 case I40E_VSI_SRIOV :
2816 vsi->nb_qps = pf->vf_nb_qps;
2818 case I40E_VSI_VMDQ2:
2819 vsi->nb_qps = pf->vmdq_nb_qps;
2824 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2826 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2830 vsi->base_queue = ret;
2832 /* VF has MSIX interrupt in VF range, don't allocate here */
2833 if (type != I40E_VSI_SRIOV) {
2834 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2836 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2837 goto fail_queue_alloc;
2839 vsi->msix_intr = ret;
2843 if (type == I40E_VSI_MAIN) {
2844 /* For main VSI, no need to add since it's default one */
2845 vsi->uplink_seid = pf->mac_seid;
2846 vsi->seid = pf->main_vsi_seid;
2847 /* Bind queues with specific MSIX interrupt */
2849 * Needs 2 interrupt at least, one for misc cause which will
2850 * enabled from OS side, Another for queues binding the
2851 * interrupt from device side only.
2854 /* Get default VSI parameters from hardware */
2855 memset(&ctxt, 0, sizeof(ctxt));
2856 ctxt.seid = vsi->seid;
2857 ctxt.pf_num = hw->pf_id;
2858 ctxt.uplink_seid = vsi->uplink_seid;
2860 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2861 if (ret != I40E_SUCCESS) {
2862 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2863 goto fail_msix_alloc;
2865 (void)rte_memcpy(&vsi->info, &ctxt.info,
2866 sizeof(struct i40e_aqc_vsi_properties_data));
2867 vsi->vsi_id = ctxt.vsi_number;
2868 vsi->info.valid_sections = 0;
2870 /* Configure tc, enabled TC0 only */
2871 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2873 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2874 goto fail_msix_alloc;
2877 /* TC, queue mapping */
2878 memset(&ctxt, 0, sizeof(ctxt));
2879 vsi->info.valid_sections |=
2880 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2881 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2882 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2883 (void)rte_memcpy(&ctxt.info, &vsi->info,
2884 sizeof(struct i40e_aqc_vsi_properties_data));
2885 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2886 I40E_DEFAULT_TCMAP);
2887 if (ret != I40E_SUCCESS) {
2888 PMD_DRV_LOG(ERR, "Failed to configure "
2889 "TC queue mapping");
2890 goto fail_msix_alloc;
2892 ctxt.seid = vsi->seid;
2893 ctxt.pf_num = hw->pf_id;
2894 ctxt.uplink_seid = vsi->uplink_seid;
2897 /* Update VSI parameters */
2898 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2899 if (ret != I40E_SUCCESS) {
2900 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2901 goto fail_msix_alloc;
2904 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2905 sizeof(vsi->info.tc_mapping));
2906 (void)rte_memcpy(&vsi->info.queue_mapping,
2907 &ctxt.info.queue_mapping,
2908 sizeof(vsi->info.queue_mapping));
2909 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2910 vsi->info.valid_sections = 0;
2912 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2916 * Updating default filter settings are necessary to prevent
2917 * reception of tagged packets.
2918 * Some old firmware configurations load a default macvlan
2919 * filter which accepts both tagged and untagged packets.
2920 * The updating is to use a normal filter instead if needed.
2921 * For NVM 4.2.2 or after, the updating is not needed anymore.
2922 * The firmware with correct configurations load the default
2923 * macvlan filter which is expected and cannot be removed.
2925 i40e_update_default_filter_setting(vsi);
2926 } else if (type == I40E_VSI_SRIOV) {
2927 memset(&ctxt, 0, sizeof(ctxt));
2929 * For other VSI, the uplink_seid equals to uplink VSI's
2930 * uplink_seid since they share same VEB
2932 vsi->uplink_seid = uplink_vsi->uplink_seid;
2933 ctxt.pf_num = hw->pf_id;
2934 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2935 ctxt.uplink_seid = vsi->uplink_seid;
2936 ctxt.connection_type = 0x1;
2937 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2939 /* Configure switch ID */
2940 ctxt.info.valid_sections |=
2941 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2942 ctxt.info.switch_id =
2943 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2944 /* Configure port/vlan */
2945 ctxt.info.valid_sections |=
2946 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2947 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2948 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2949 I40E_DEFAULT_TCMAP);
2950 if (ret != I40E_SUCCESS) {
2951 PMD_DRV_LOG(ERR, "Failed to configure "
2952 "TC queue mapping");
2953 goto fail_msix_alloc;
2955 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2956 ctxt.info.valid_sections |=
2957 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2959 * Since VSI is not created yet, only configure parameter,
2960 * will add vsi below.
2962 } else if (type == I40E_VSI_VMDQ2) {
2963 memset(&ctxt, 0, sizeof(ctxt));
2965 * For other VSI, the uplink_seid equals to uplink VSI's
2966 * uplink_seid since they share same VEB
2968 vsi->uplink_seid = uplink_vsi->uplink_seid;
2969 ctxt.pf_num = hw->pf_id;
2971 ctxt.uplink_seid = vsi->uplink_seid;
2972 ctxt.connection_type = 0x1;
2973 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
2975 ctxt.info.valid_sections |=
2976 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2977 /* user_param carries flag to enable loop back */
2979 ctxt.info.switch_id =
2980 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
2981 ctxt.info.switch_id |=
2982 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2985 /* Configure port/vlan */
2986 ctxt.info.valid_sections |=
2987 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2988 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2989 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2990 I40E_DEFAULT_TCMAP);
2991 if (ret != I40E_SUCCESS) {
2992 PMD_DRV_LOG(ERR, "Failed to configure "
2993 "TC queue mapping");
2994 goto fail_msix_alloc;
2996 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2997 ctxt.info.valid_sections |=
2998 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3000 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3001 goto fail_msix_alloc;
3004 if (vsi->type != I40E_VSI_MAIN) {
3005 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3007 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3008 hw->aq.asq_last_status);
3009 goto fail_msix_alloc;
3011 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3012 vsi->info.valid_sections = 0;
3013 vsi->seid = ctxt.seid;
3014 vsi->vsi_id = ctxt.vsi_number;
3015 vsi->sib_vsi_list.vsi = vsi;
3016 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3017 &vsi->sib_vsi_list, list);
3020 /* MAC/VLAN configuration */
3021 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3022 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3024 ret = i40e_vsi_add_mac(vsi, &filter);
3025 if (ret != I40E_SUCCESS) {
3026 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3027 goto fail_msix_alloc;
3030 /* Get VSI BW information */
3031 i40e_vsi_dump_bw_config(vsi);
3034 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3036 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3042 /* Configure vlan stripping on or off */
3044 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3046 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3047 struct i40e_vsi_context ctxt;
3049 int ret = I40E_SUCCESS;
3051 /* Check if it has been already on or off */
3052 if (vsi->info.valid_sections &
3053 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3055 if ((vsi->info.port_vlan_flags &
3056 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3057 return 0; /* already on */
3059 if ((vsi->info.port_vlan_flags &
3060 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3061 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3062 return 0; /* already off */
3067 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3069 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3070 vsi->info.valid_sections =
3071 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3072 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3073 vsi->info.port_vlan_flags |= vlan_flags;
3074 ctxt.seid = vsi->seid;
3075 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3076 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3078 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3079 on ? "enable" : "disable");
3085 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3087 struct rte_eth_dev_data *data = dev->data;
3090 /* Apply vlan offload setting */
3091 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3093 /* Apply double-vlan setting, not implemented yet */
3095 /* Apply pvid setting */
3096 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3097 data->dev_conf.txmode.hw_vlan_insert_pvid);
3099 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3105 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3107 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3109 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3113 i40e_update_flow_control(struct i40e_hw *hw)
3115 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3116 struct i40e_link_status link_status;
3117 uint32_t rxfc = 0, txfc = 0, reg;
3121 memset(&link_status, 0, sizeof(link_status));
3122 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3123 if (ret != I40E_SUCCESS) {
3124 PMD_DRV_LOG(ERR, "Failed to get link status information");
3125 goto write_reg; /* Disable flow control */
3128 an_info = hw->phy.link_info.an_info;
3129 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3130 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3131 ret = I40E_ERR_NOT_READY;
3132 goto write_reg; /* Disable flow control */
3135 * If link auto negotiation is enabled, flow control needs to
3136 * be configured according to it
3138 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3139 case I40E_LINK_PAUSE_RXTX:
3142 hw->fc.current_mode = I40E_FC_FULL;
3144 case I40E_AQ_LINK_PAUSE_RX:
3146 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3148 case I40E_AQ_LINK_PAUSE_TX:
3150 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3153 hw->fc.current_mode = I40E_FC_NONE;
3158 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3159 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3160 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3161 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3162 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3163 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3170 i40e_pf_setup(struct i40e_pf *pf)
3172 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3173 struct i40e_filter_control_settings settings;
3174 struct i40e_vsi *vsi;
3177 /* Clear all stats counters */
3178 pf->offset_loaded = FALSE;
3179 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3180 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3182 ret = i40e_pf_get_switch_config(pf);
3183 if (ret != I40E_SUCCESS) {
3184 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3189 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3191 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3192 return I40E_ERR_NOT_READY;
3196 /* Configure filter control */
3197 memset(&settings, 0, sizeof(settings));
3198 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3199 /* Enable ethtype and macvlan filters */
3200 settings.enable_ethtype = TRUE;
3201 settings.enable_macvlan = TRUE;
3202 ret = i40e_set_filter_control(hw, &settings);
3204 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3207 /* Update flow control according to the auto negotiation */
3208 i40e_update_flow_control(hw);
3210 return I40E_SUCCESS;
3214 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3220 * Set or clear TX Queue Disable flags,
3221 * which is required by hardware.
3223 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3224 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3226 /* Wait until the request is finished */
3227 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3228 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3229 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3230 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3231 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3237 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3238 return I40E_SUCCESS; /* already on, skip next steps */
3240 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3241 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3243 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3244 return I40E_SUCCESS; /* already off, skip next steps */
3245 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3247 /* Write the register */
3248 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3249 /* Check the result */
3250 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3251 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3252 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3254 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3255 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3258 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3259 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3263 /* Check if it is timeout */
3264 if (j >= I40E_CHK_Q_ENA_COUNT) {
3265 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3266 (on ? "enable" : "disable"), q_idx);
3267 return I40E_ERR_TIMEOUT;
3270 return I40E_SUCCESS;
3273 /* Swith on or off the tx queues */
3275 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3277 struct rte_eth_dev_data *dev_data = pf->dev_data;
3278 struct i40e_tx_queue *txq;
3279 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3283 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3284 txq = dev_data->tx_queues[i];
3285 /* Don't operate the queue if not configured or
3286 * if starting only per queue */
3287 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3290 ret = i40e_dev_tx_queue_start(dev, i);
3292 ret = i40e_dev_tx_queue_stop(dev, i);
3293 if ( ret != I40E_SUCCESS)
3297 return I40E_SUCCESS;
3301 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3306 /* Wait until the request is finished */
3307 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3308 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3309 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3310 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3311 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3316 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3317 return I40E_SUCCESS; /* Already on, skip next steps */
3318 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3320 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3321 return I40E_SUCCESS; /* Already off, skip next steps */
3322 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3325 /* Write the register */
3326 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3327 /* Check the result */
3328 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3329 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3330 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3332 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3333 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3336 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3337 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3342 /* Check if it is timeout */
3343 if (j >= I40E_CHK_Q_ENA_COUNT) {
3344 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3345 (on ? "enable" : "disable"), q_idx);
3346 return I40E_ERR_TIMEOUT;
3349 return I40E_SUCCESS;
3351 /* Switch on or off the rx queues */
3353 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3355 struct rte_eth_dev_data *dev_data = pf->dev_data;
3356 struct i40e_rx_queue *rxq;
3357 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3361 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3362 rxq = dev_data->rx_queues[i];
3363 /* Don't operate the queue if not configured or
3364 * if starting only per queue */
3365 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3368 ret = i40e_dev_rx_queue_start(dev, i);
3370 ret = i40e_dev_rx_queue_stop(dev, i);
3371 if (ret != I40E_SUCCESS)
3375 return I40E_SUCCESS;
3378 /* Switch on or off all the rx/tx queues */
3380 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3385 /* enable rx queues before enabling tx queues */
3386 ret = i40e_dev_switch_rx_queues(pf, on);
3388 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3391 ret = i40e_dev_switch_tx_queues(pf, on);
3393 /* Stop tx queues before stopping rx queues */
3394 ret = i40e_dev_switch_tx_queues(pf, on);
3396 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3399 ret = i40e_dev_switch_rx_queues(pf, on);
3405 /* Initialize VSI for TX */
3407 i40e_dev_tx_init(struct i40e_pf *pf)
3409 struct rte_eth_dev_data *data = pf->dev_data;
3411 uint32_t ret = I40E_SUCCESS;
3412 struct i40e_tx_queue *txq;
3414 for (i = 0; i < data->nb_tx_queues; i++) {
3415 txq = data->tx_queues[i];
3416 if (!txq || !txq->q_set)
3418 ret = i40e_tx_queue_init(txq);
3419 if (ret != I40E_SUCCESS)
3426 /* Initialize VSI for RX */
3428 i40e_dev_rx_init(struct i40e_pf *pf)
3430 struct rte_eth_dev_data *data = pf->dev_data;
3431 int ret = I40E_SUCCESS;
3433 struct i40e_rx_queue *rxq;
3435 i40e_pf_config_mq_rx(pf);
3436 for (i = 0; i < data->nb_rx_queues; i++) {
3437 rxq = data->rx_queues[i];
3438 if (!rxq || !rxq->q_set)
3441 ret = i40e_rx_queue_init(rxq);
3442 if (ret != I40E_SUCCESS) {
3443 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3453 i40e_dev_rxtx_init(struct i40e_pf *pf)
3457 err = i40e_dev_tx_init(pf);
3459 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3462 err = i40e_dev_rx_init(pf);
3464 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3472 i40e_vmdq_setup(struct rte_eth_dev *dev)
3474 struct rte_eth_conf *conf = &dev->data->dev_conf;
3475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3476 int i, err, conf_vsis, j, loop;
3477 struct i40e_vsi *vsi;
3478 struct i40e_vmdq_info *vmdq_info;
3479 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3480 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3483 * Disable interrupt to avoid message from VF. Furthermore, it will
3484 * avoid race condition in VSI creation/destroy.
3486 i40e_pf_disable_irq0(hw);
3488 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3489 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3493 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3494 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3495 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3496 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3497 pf->max_nb_vmdq_vsi);
3501 if (pf->vmdq != NULL) {
3502 PMD_INIT_LOG(INFO, "VMDQ already configured");
3506 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3507 sizeof(*vmdq_info) * conf_vsis, 0);
3509 if (pf->vmdq == NULL) {
3510 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3514 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3516 /* Create VMDQ VSI */
3517 for (i = 0; i < conf_vsis; i++) {
3518 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3519 vmdq_conf->enable_loop_back);
3521 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3525 vmdq_info = &pf->vmdq[i];
3527 vmdq_info->vsi = vsi;
3529 pf->nb_cfg_vmdq_vsi = conf_vsis;
3531 /* Configure Vlan */
3532 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3533 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3534 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3535 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3536 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3537 vmdq_conf->pool_map[i].vlan_id, j);
3539 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3540 vmdq_conf->pool_map[i].vlan_id);
3542 PMD_INIT_LOG(ERR, "Failed to add vlan");
3550 i40e_pf_enable_irq0(hw);
3555 for (i = 0; i < conf_vsis; i++)
3556 if (pf->vmdq[i].vsi == NULL)
3559 i40e_vsi_release(pf->vmdq[i].vsi);
3563 i40e_pf_enable_irq0(hw);
3568 i40e_stat_update_32(struct i40e_hw *hw,
3576 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3580 if (new_data >= *offset)
3581 *stat = (uint64_t)(new_data - *offset);
3583 *stat = (uint64_t)((new_data +
3584 ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3588 i40e_stat_update_48(struct i40e_hw *hw,
3597 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3598 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3599 I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3604 if (new_data >= *offset)
3605 *stat = new_data - *offset;
3607 *stat = (uint64_t)((new_data +
3608 ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3610 *stat &= I40E_48_BIT_MASK;
3615 i40e_pf_disable_irq0(struct i40e_hw *hw)
3617 /* Disable all interrupt types */
3618 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3619 I40E_WRITE_FLUSH(hw);
3624 i40e_pf_enable_irq0(struct i40e_hw *hw)
3626 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3627 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3628 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3629 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3630 I40E_WRITE_FLUSH(hw);
3634 i40e_pf_config_irq0(struct i40e_hw *hw)
3636 /* read pending request and disable first */
3637 i40e_pf_disable_irq0(hw);
3638 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3639 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3640 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3642 /* Link no queues with irq0 */
3643 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3644 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3648 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3654 uint32_t index, offset, val;
3659 * Try to find which VF trigger a reset, use absolute VF id to access
3660 * since the reg is global register.
3662 for (i = 0; i < pf->vf_num; i++) {
3663 abs_vf_id = hw->func_caps.vf_base_id + i;
3664 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3665 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3666 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3667 /* VFR event occured */
3668 if (val & (0x1 << offset)) {
3671 /* Clear the event first */
3672 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3674 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3676 * Only notify a VF reset event occured,
3677 * don't trigger another SW reset
3679 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3680 if (ret != I40E_SUCCESS)
3681 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3687 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3690 struct i40e_arq_event_info info;
3691 uint16_t pending, opcode;
3694 info.buf_len = I40E_AQ_BUF_SZ;
3695 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3696 if (!info.msg_buf) {
3697 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3703 ret = i40e_clean_arq_element(hw, &info, &pending);
3705 if (ret != I40E_SUCCESS) {
3706 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3707 "aq_err: %u", hw->aq.asq_last_status);
3710 opcode = rte_le_to_cpu_16(info.desc.opcode);
3713 case i40e_aqc_opc_send_msg_to_pf:
3714 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3715 i40e_pf_host_handle_vf_msg(dev,
3716 rte_le_to_cpu_16(info.desc.retval),
3717 rte_le_to_cpu_32(info.desc.cookie_high),
3718 rte_le_to_cpu_32(info.desc.cookie_low),
3723 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3728 rte_free(info.msg_buf);
3732 * Interrupt handler is registered as the alarm callback for handling LSC
3733 * interrupt in a definite of time, in order to wait the NIC into a stable
3734 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3735 * no need for link down interrupt.
3738 i40e_dev_interrupt_delayed_handler(void *param)
3740 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3741 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3744 /* read interrupt causes again */
3745 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3747 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3748 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3749 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3750 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3751 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3752 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3753 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3754 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3755 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3756 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3757 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3759 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3760 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3761 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3762 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3763 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3765 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3766 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3767 i40e_dev_handle_vfr_event(dev);
3769 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3770 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3771 i40e_dev_handle_aq_msg(dev);
3774 /* handle the link up interrupt in an alarm callback */
3775 i40e_dev_link_update(dev, 0);
3776 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3778 i40e_pf_enable_irq0(hw);
3779 rte_intr_enable(&(dev->pci_dev->intr_handle));
3783 * Interrupt handler triggered by NIC for handling
3784 * specific interrupt.
3787 * Pointer to interrupt handle.
3789 * The address of parameter (struct rte_eth_dev *) regsitered before.
3795 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3798 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802 /* Disable interrupt */
3803 i40e_pf_disable_irq0(hw);
3805 /* read out interrupt causes */
3806 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3808 /* No interrupt event indicated */
3809 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3810 PMD_DRV_LOG(INFO, "No interrupt event");
3813 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3814 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3815 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3816 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3817 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3818 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3819 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3820 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3821 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3822 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3823 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3824 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3825 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3826 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3827 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3828 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3830 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3831 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3832 i40e_dev_handle_vfr_event(dev);
3834 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3835 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3836 i40e_dev_handle_aq_msg(dev);
3839 /* Link Status Change interrupt */
3840 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3841 #define I40E_US_PER_SECOND 1000000
3842 struct rte_eth_link link;
3844 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3845 memset(&link, 0, sizeof(link));
3846 rte_i40e_dev_atomic_read_link_status(dev, &link);
3847 i40e_dev_link_update(dev, 0);
3850 * For link up interrupt, it needs to wait 1 second to let the
3851 * hardware be a stable state. Otherwise several consecutive
3852 * interrupts can be observed.
3853 * For link down interrupt, no need to wait.
3855 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3856 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3859 _rte_eth_dev_callback_process(dev,
3860 RTE_ETH_EVENT_INTR_LSC);
3864 /* Enable interrupt */
3865 i40e_pf_enable_irq0(hw);
3866 rte_intr_enable(&(dev->pci_dev->intr_handle));
3870 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3871 struct i40e_macvlan_filter *filter,
3874 int ele_num, ele_buff_size;
3875 int num, actual_num, i;
3877 int ret = I40E_SUCCESS;
3878 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3879 struct i40e_aqc_add_macvlan_element_data *req_list;
3881 if (filter == NULL || total == 0)
3882 return I40E_ERR_PARAM;
3883 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3884 ele_buff_size = hw->aq.asq_buf_size;
3886 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3887 if (req_list == NULL) {
3888 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3889 return I40E_ERR_NO_MEMORY;
3894 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3895 memset(req_list, 0, ele_buff_size);
3897 for (i = 0; i < actual_num; i++) {
3898 (void)rte_memcpy(req_list[i].mac_addr,
3899 &filter[num + i].macaddr, ETH_ADDR_LEN);
3900 req_list[i].vlan_tag =
3901 rte_cpu_to_le_16(filter[num + i].vlan_id);
3903 switch (filter[num + i].filter_type) {
3904 case RTE_MAC_PERFECT_MATCH:
3905 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3906 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3908 case RTE_MACVLAN_PERFECT_MATCH:
3909 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3911 case RTE_MAC_HASH_MATCH:
3912 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3913 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3915 case RTE_MACVLAN_HASH_MATCH:
3916 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
3919 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
3920 ret = I40E_ERR_PARAM;
3924 req_list[i].queue_number = 0;
3926 req_list[i].flags = rte_cpu_to_le_16(flags);
3929 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3931 if (ret != I40E_SUCCESS) {
3932 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3936 } while (num < total);
3944 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3945 struct i40e_macvlan_filter *filter,
3948 int ele_num, ele_buff_size;
3949 int num, actual_num, i;
3951 int ret = I40E_SUCCESS;
3952 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3953 struct i40e_aqc_remove_macvlan_element_data *req_list;
3955 if (filter == NULL || total == 0)
3956 return I40E_ERR_PARAM;
3958 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3959 ele_buff_size = hw->aq.asq_buf_size;
3961 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3962 if (req_list == NULL) {
3963 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3964 return I40E_ERR_NO_MEMORY;
3969 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3970 memset(req_list, 0, ele_buff_size);
3972 for (i = 0; i < actual_num; i++) {
3973 (void)rte_memcpy(req_list[i].mac_addr,
3974 &filter[num + i].macaddr, ETH_ADDR_LEN);
3975 req_list[i].vlan_tag =
3976 rte_cpu_to_le_16(filter[num + i].vlan_id);
3978 switch (filter[num + i].filter_type) {
3979 case RTE_MAC_PERFECT_MATCH:
3980 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3981 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3983 case RTE_MACVLAN_PERFECT_MATCH:
3984 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3986 case RTE_MAC_HASH_MATCH:
3987 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
3988 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3990 case RTE_MACVLAN_HASH_MATCH:
3991 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
3994 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
3995 ret = I40E_ERR_PARAM;
3998 req_list[i].flags = rte_cpu_to_le_16(flags);
4001 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4003 if (ret != I40E_SUCCESS) {
4004 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4008 } while (num < total);
4015 /* Find out specific MAC filter */
4016 static struct i40e_mac_filter *
4017 i40e_find_mac_filter(struct i40e_vsi *vsi,
4018 struct ether_addr *macaddr)
4020 struct i40e_mac_filter *f;
4022 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4023 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4031 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4034 uint32_t vid_idx, vid_bit;
4036 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4037 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4039 if (vsi->vfta[vid_idx] & vid_bit)
4046 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4047 uint16_t vlan_id, bool on)
4049 uint32_t vid_idx, vid_bit;
4051 #define UINT32_BIT_MASK 0x1F
4052 #define VALID_VLAN_BIT_MASK 0xFFF
4053 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4054 * element first, then find the bits it belongs to
4056 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4058 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4061 vsi->vfta[vid_idx] |= vid_bit;
4063 vsi->vfta[vid_idx] &= ~vid_bit;
4067 * Find all vlan options for specific mac addr,
4068 * return with actual vlan found.
4071 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4072 struct i40e_macvlan_filter *mv_f,
4073 int num, struct ether_addr *addr)
4079 * Not to use i40e_find_vlan_filter to decrease the loop time,
4080 * although the code looks complex.
4082 if (num < vsi->vlan_num)
4083 return I40E_ERR_PARAM;
4086 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4088 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4089 if (vsi->vfta[j] & (1 << k)) {
4091 PMD_DRV_LOG(ERR, "vlan number "
4093 return I40E_ERR_PARAM;
4095 (void)rte_memcpy(&mv_f[i].macaddr,
4096 addr, ETH_ADDR_LEN);
4098 j * I40E_UINT32_BIT_SIZE + k;
4104 return I40E_SUCCESS;
4108 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4109 struct i40e_macvlan_filter *mv_f,
4114 struct i40e_mac_filter *f;
4116 if (num < vsi->mac_num)
4117 return I40E_ERR_PARAM;
4119 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4121 PMD_DRV_LOG(ERR, "buffer number not match");
4122 return I40E_ERR_PARAM;
4124 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4126 mv_f[i].vlan_id = vlan;
4127 mv_f[i].filter_type = f->mac_info.filter_type;
4131 return I40E_SUCCESS;
4135 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4138 struct i40e_mac_filter *f;
4139 struct i40e_macvlan_filter *mv_f;
4140 int ret = I40E_SUCCESS;
4142 if (vsi == NULL || vsi->mac_num == 0)
4143 return I40E_ERR_PARAM;
4145 /* Case that no vlan is set */
4146 if (vsi->vlan_num == 0)
4149 num = vsi->mac_num * vsi->vlan_num;
4151 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4153 PMD_DRV_LOG(ERR, "failed to allocate memory");
4154 return I40E_ERR_NO_MEMORY;
4158 if (vsi->vlan_num == 0) {
4159 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4160 (void)rte_memcpy(&mv_f[i].macaddr,
4161 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4162 mv_f[i].vlan_id = 0;
4166 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4167 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4168 vsi->vlan_num, &f->mac_info.mac_addr);
4169 if (ret != I40E_SUCCESS)
4175 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4183 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4185 struct i40e_macvlan_filter *mv_f;
4187 int ret = I40E_SUCCESS;
4189 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4190 return I40E_ERR_PARAM;
4192 /* If it's already set, just return */
4193 if (i40e_find_vlan_filter(vsi,vlan))
4194 return I40E_SUCCESS;
4196 mac_num = vsi->mac_num;
4199 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4200 return I40E_ERR_PARAM;
4203 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4206 PMD_DRV_LOG(ERR, "failed to allocate memory");
4207 return I40E_ERR_NO_MEMORY;
4210 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4212 if (ret != I40E_SUCCESS)
4215 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4217 if (ret != I40E_SUCCESS)
4220 i40e_set_vlan_filter(vsi, vlan, 1);
4230 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4232 struct i40e_macvlan_filter *mv_f;
4234 int ret = I40E_SUCCESS;
4237 * Vlan 0 is the generic filter for untagged packets
4238 * and can't be removed.
4240 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4241 return I40E_ERR_PARAM;
4243 /* If can't find it, just return */
4244 if (!i40e_find_vlan_filter(vsi, vlan))
4245 return I40E_ERR_PARAM;
4247 mac_num = vsi->mac_num;
4250 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4251 return I40E_ERR_PARAM;
4254 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4257 PMD_DRV_LOG(ERR, "failed to allocate memory");
4258 return I40E_ERR_NO_MEMORY;
4261 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4263 if (ret != I40E_SUCCESS)
4266 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4268 if (ret != I40E_SUCCESS)
4271 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4272 if (vsi->vlan_num == 1) {
4273 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4274 if (ret != I40E_SUCCESS)
4277 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4278 if (ret != I40E_SUCCESS)
4282 i40e_set_vlan_filter(vsi, vlan, 0);
4292 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4294 struct i40e_mac_filter *f;
4295 struct i40e_macvlan_filter *mv_f;
4296 int i, vlan_num = 0;
4297 int ret = I40E_SUCCESS;
4299 /* If it's add and we've config it, return */
4300 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4302 return I40E_SUCCESS;
4303 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4304 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4307 * If vlan_num is 0, that's the first time to add mac,
4308 * set mask for vlan_id 0.
4310 if (vsi->vlan_num == 0) {
4311 i40e_set_vlan_filter(vsi, 0, 1);
4314 vlan_num = vsi->vlan_num;
4315 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4316 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4319 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4321 PMD_DRV_LOG(ERR, "failed to allocate memory");
4322 return I40E_ERR_NO_MEMORY;
4325 for (i = 0; i < vlan_num; i++) {
4326 mv_f[i].filter_type = mac_filter->filter_type;
4327 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4331 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4332 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4333 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4334 &mac_filter->mac_addr);
4335 if (ret != I40E_SUCCESS)
4339 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4340 if (ret != I40E_SUCCESS)
4343 /* Add the mac addr into mac list */
4344 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4346 PMD_DRV_LOG(ERR, "failed to allocate memory");
4347 ret = I40E_ERR_NO_MEMORY;
4350 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4352 f->mac_info.filter_type = mac_filter->filter_type;
4353 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4364 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4366 struct i40e_mac_filter *f;
4367 struct i40e_macvlan_filter *mv_f;
4369 enum rte_mac_filter_type filter_type;
4370 int ret = I40E_SUCCESS;
4372 /* Can't find it, return an error */
4373 f = i40e_find_mac_filter(vsi, addr);
4375 return I40E_ERR_PARAM;
4377 vlan_num = vsi->vlan_num;
4378 filter_type = f->mac_info.filter_type;
4379 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4380 filter_type == RTE_MACVLAN_HASH_MATCH) {
4381 if (vlan_num == 0) {
4382 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4383 return I40E_ERR_PARAM;
4385 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4386 filter_type == RTE_MAC_HASH_MATCH)
4389 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4391 PMD_DRV_LOG(ERR, "failed to allocate memory");
4392 return I40E_ERR_NO_MEMORY;
4395 for (i = 0; i < vlan_num; i++) {
4396 mv_f[i].filter_type = filter_type;
4397 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4400 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4401 filter_type == RTE_MACVLAN_HASH_MATCH) {
4402 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4403 if (ret != I40E_SUCCESS)
4407 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4408 if (ret != I40E_SUCCESS)
4411 /* Remove the mac addr into mac list */
4412 TAILQ_REMOVE(&vsi->mac_list, f, next);
4422 /* Configure hash enable flags for RSS */
4424 i40e_config_hena(uint64_t flags)
4431 if (flags & ETH_RSS_NONF_IPV4_UDP)
4432 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4433 if (flags & ETH_RSS_NONF_IPV4_TCP)
4434 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4435 if (flags & ETH_RSS_NONF_IPV4_SCTP)
4436 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4437 if (flags & ETH_RSS_NONF_IPV4_OTHER)
4438 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4439 if (flags & ETH_RSS_FRAG_IPV4)
4440 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4441 if (flags & ETH_RSS_NONF_IPV6_UDP)
4442 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4443 if (flags & ETH_RSS_NONF_IPV6_TCP)
4444 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4445 if (flags & ETH_RSS_NONF_IPV6_SCTP)
4446 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4447 if (flags & ETH_RSS_NONF_IPV6_OTHER)
4448 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4449 if (flags & ETH_RSS_FRAG_IPV6)
4450 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4451 if (flags & ETH_RSS_L2_PAYLOAD)
4452 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4457 /* Parse the hash enable flags */
4459 i40e_parse_hena(uint64_t flags)
4461 uint64_t rss_hf = 0;
4466 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4467 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4468 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4469 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4470 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4471 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4472 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4473 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4474 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4475 rss_hf |= ETH_RSS_FRAG_IPV4;
4476 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4477 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4478 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4479 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4480 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4481 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4482 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4483 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4484 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4485 rss_hf |= ETH_RSS_FRAG_IPV6;
4486 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4487 rss_hf |= ETH_RSS_L2_PAYLOAD;
4494 i40e_pf_disable_rss(struct i40e_pf *pf)
4496 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4499 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4500 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4501 hena &= ~I40E_RSS_HENA_ALL;
4502 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4503 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4504 I40E_WRITE_FLUSH(hw);
4508 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4511 uint8_t hash_key_len;
4516 hash_key = (uint32_t *)(rss_conf->rss_key);
4517 hash_key_len = rss_conf->rss_key_len;
4518 if (hash_key != NULL && hash_key_len >=
4519 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4520 /* Fill in RSS hash key */
4521 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4522 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4525 rss_hf = rss_conf->rss_hf;
4526 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4527 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4528 hena &= ~I40E_RSS_HENA_ALL;
4529 hena |= i40e_config_hena(rss_hf);
4530 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4531 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4532 I40E_WRITE_FLUSH(hw);
4538 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4539 struct rte_eth_rss_conf *rss_conf)
4541 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4542 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4545 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4546 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4547 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4548 if (rss_hf != 0) /* Enable RSS */
4550 return 0; /* Nothing to do */
4553 if (rss_hf == 0) /* Disable RSS */
4556 return i40e_hw_rss_hash_set(hw, rss_conf);
4560 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4561 struct rte_eth_rss_conf *rss_conf)
4563 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4568 if (hash_key != NULL) {
4569 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4570 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4571 rss_conf->rss_key_len = i * sizeof(uint32_t);
4573 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4574 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4575 rss_conf->rss_hf = i40e_parse_hena(hena);
4581 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4583 switch (filter_type) {
4584 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4585 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4587 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4588 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4590 case RTE_TUNNEL_FILTER_IMAC_TENID:
4591 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4593 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4594 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4596 case ETH_TUNNEL_FILTER_IMAC:
4597 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4600 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4608 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4609 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4613 uint8_t tun_type = 0;
4615 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4616 struct i40e_vsi *vsi = pf->main_vsi;
4617 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4618 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4620 cld_filter = rte_zmalloc("tunnel_filter",
4621 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4624 if (NULL == cld_filter) {
4625 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4628 pfilter = cld_filter;
4630 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4631 sizeof(struct ether_addr));
4632 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4633 sizeof(struct ether_addr));
4635 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4636 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4637 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4638 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4639 &tunnel_filter->ip_addr,
4640 sizeof(pfilter->ipaddr.v4.data));
4642 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4643 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4644 &tunnel_filter->ip_addr,
4645 sizeof(pfilter->ipaddr.v6.data));
4648 /* check tunneled type */
4649 switch (tunnel_filter->tunnel_type) {
4650 case RTE_TUNNEL_TYPE_VXLAN:
4651 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4654 /* Other tunnel types is not supported. */
4655 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4656 rte_free(cld_filter);
4660 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4663 rte_free(cld_filter);
4667 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4668 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4669 pfilter->tenant_id = tunnel_filter->tenant_id;
4670 pfilter->queue_number = tunnel_filter->queue_id;
4673 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4675 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4678 rte_free(cld_filter);
4683 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4687 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4688 if (pf->vxlan_ports[i] == port)
4696 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4700 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4702 idx = i40e_get_vxlan_port_idx(pf, port);
4704 /* Check if port already exists */
4706 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4710 /* Now check if there is space to add the new port */
4711 idx = i40e_get_vxlan_port_idx(pf, 0);
4713 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4714 "not adding port %d", port);
4718 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4721 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4725 PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4726 port, filter_index);
4728 /* New port: add it and mark its index in the bitmap */
4729 pf->vxlan_ports[idx] = port;
4730 pf->vxlan_bitmap |= (1 << idx);
4732 if (!(pf->flags & I40E_FLAG_VXLAN))
4733 pf->flags |= I40E_FLAG_VXLAN;
4739 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4742 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4744 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4745 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4749 idx = i40e_get_vxlan_port_idx(pf, port);
4752 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4756 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4757 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4761 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4764 pf->vxlan_ports[idx] = 0;
4765 pf->vxlan_bitmap &= ~(1 << idx);
4767 if (!pf->vxlan_bitmap)
4768 pf->flags &= ~I40E_FLAG_VXLAN;
4773 /* Add UDP tunneling port */
4775 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4776 struct rte_eth_udp_tunnel *udp_tunnel)
4779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4781 if (udp_tunnel == NULL)
4784 switch (udp_tunnel->prot_type) {
4785 case RTE_TUNNEL_TYPE_VXLAN:
4786 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4789 case RTE_TUNNEL_TYPE_GENEVE:
4790 case RTE_TUNNEL_TYPE_TEREDO:
4791 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4796 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4804 /* Remove UDP tunneling port */
4806 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4807 struct rte_eth_udp_tunnel *udp_tunnel)
4810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4812 if (udp_tunnel == NULL)
4815 switch (udp_tunnel->prot_type) {
4816 case RTE_TUNNEL_TYPE_VXLAN:
4817 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4819 case RTE_TUNNEL_TYPE_GENEVE:
4820 case RTE_TUNNEL_TYPE_TEREDO:
4821 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4825 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4833 /* Calculate the maximum number of contiguous PF queues that are configured */
4835 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4837 struct rte_eth_dev_data *data = pf->dev_data;
4839 struct i40e_rx_queue *rxq;
4842 for (i = 0; i < pf->lan_nb_qps; i++) {
4843 rxq = data->rx_queues[i];
4844 if (rxq && rxq->q_set)
4855 i40e_pf_config_rss(struct i40e_pf *pf)
4857 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4858 struct rte_eth_rss_conf rss_conf;
4859 uint32_t i, lut = 0;
4863 * If both VMDQ and RSS enabled, not all of PF queues are configured.
4864 * It's necessary to calulate the actual PF queues that are configured.
4866 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4867 num = i40e_pf_calc_configured_queues_num(pf);
4868 num = i40e_align_floor(num);
4870 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4872 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
4876 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
4880 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4883 lut = (lut << 8) | (j & ((0x1 <<
4884 hw->func_caps.rss_table_entry_width) - 1));
4886 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4889 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4890 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4891 i40e_pf_disable_rss(pf);
4894 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4895 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4896 /* Calculate the default hash key */
4897 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4898 rss_key_default[i] = (uint32_t)rte_rand();
4899 rss_conf.rss_key = (uint8_t *)rss_key_default;
4900 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4904 return i40e_hw_rss_hash_set(hw, &rss_conf);
4908 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4909 struct rte_eth_tunnel_filter_conf *filter)
4911 if (pf == NULL || filter == NULL) {
4912 PMD_DRV_LOG(ERR, "Invalid parameter");
4916 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4917 PMD_DRV_LOG(ERR, "Invalid queue ID");
4921 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4922 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4926 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4927 (is_zero_ether_addr(filter->outer_mac))) {
4928 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4932 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4933 (is_zero_ether_addr(filter->inner_mac))) {
4934 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4942 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4945 struct rte_eth_tunnel_filter_conf *filter;
4946 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4947 int ret = I40E_SUCCESS;
4949 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4951 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4952 return I40E_ERR_PARAM;
4954 switch (filter_op) {
4955 case RTE_ETH_FILTER_NOP:
4956 if (!(pf->flags & I40E_FLAG_VXLAN))
4957 ret = I40E_NOT_SUPPORTED;
4958 case RTE_ETH_FILTER_ADD:
4959 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4961 case RTE_ETH_FILTER_DELETE:
4962 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4965 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4966 ret = I40E_ERR_PARAM;
4974 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4977 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
4979 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
4980 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
4985 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
4986 ret = i40e_pf_config_rss(pf);
4988 i40e_pf_disable_rss(pf);
4994 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4995 enum rte_filter_type filter_type,
4996 enum rte_filter_op filter_op,
5004 switch (filter_type) {
5005 case RTE_ETH_FILTER_MACVLAN:
5006 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5008 case RTE_ETH_FILTER_TUNNEL:
5009 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5012 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",