lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 #define I40E_DEFAULT_RX_FREE_THRESH  32
  63 #define I40E_DEFAULT_RX_PTHRESH      8
  64 #define I40E_DEFAULT_RX_HTHRESH      8
  65 #define I40E_DEFAULT_RX_WTHRESH      0
  66
  67 #define I40E_DEFAULT_TX_FREE_THRESH  32
  68 #define I40E_DEFAULT_TX_PTHRESH      32
  69 #define I40E_DEFAULT_TX_HTHRESH      0
  70 #define I40E_DEFAULT_TX_WTHRESH      0
  71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  72
  73 /* Maximun number of MAC addresses */
  74 #define I40E_NUM_MACADDR_MAX       64
  75 #define I40E_CLEAR_PXE_WAIT_MS     200
  76
  77 /* Maximun number of capability elements */
  78 #define I40E_MAX_CAP_ELE_NUM       128
  79
  80 /* Wait count and inteval */
  81 #define I40E_CHK_Q_ENA_COUNT       1000
  82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  83
  84 /* Maximun number of VSI */
  85 #define I40E_MAX_NUM_VSIS          (384UL)
  86
  87 /* Bit shift and mask */
  88 #define I40E_16_BIT_SHIFT 16
  89 #define I40E_16_BIT_MASK  0xFFFF
  90 #define I40E_32_BIT_SHIFT 32
  91 #define I40E_32_BIT_MASK  0xFFFFFFFF
  92 #define I40E_48_BIT_SHIFT 48
  93 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  94
  95 /* Default queue interrupt throttling time in microseconds*/
  96 #define I40E_ITR_INDEX_DEFAULT          0
  97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  98 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  99
 100 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 static int eth_i40e_dev_init(\
 116                         __attribute__((unused)) struct eth_driver *eth_drv,
 117                         struct rte_eth_dev *eth_dev);
 118 static int i40e_dev_configure(struct rte_eth_dev *dev);
 119 static int i40e_dev_start(struct rte_eth_dev *dev);
 120 static void i40e_dev_stop(struct rte_eth_dev *dev);
 121 static void i40e_dev_close(struct rte_eth_dev *dev);
 122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 129                                struct rte_eth_stats *stats);
 130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 132                                             uint16_t queue_id,
 133                                             uint8_t stat_idx,
 134                                             uint8_t is_rx);
 135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 136                               struct rte_eth_dev_info *dev_info);
 137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 138                                 uint16_t vlan_id,
 139                                 int on);
 140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 143                                       uint16_t queue,
 144                                       int on);
 145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 149                               struct rte_eth_fc_conf *fc_conf);
 150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 151                                        struct rte_eth_pfc_conf *pfc_conf);
 152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 153                           struct ether_addr *mac_addr,
 154                           uint32_t index,
 155                           uint32_t pool);
 156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 158                                     struct rte_eth_rss_reta *reta_conf);
 159 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 160                                    struct rte_eth_rss_reta *reta_conf);
 161
 162 static int i40e_get_cap(struct i40e_hw *hw);
 163 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 164 static int i40e_pf_setup(struct i40e_pf *pf);
 165 static int i40e_vsi_init(struct i40e_vsi *vsi);
 166 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 167 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 168                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 169 static void i40e_stat_update_48(struct i40e_hw *hw,
 170                                uint32_t hireg,
 171                                uint32_t loreg,
 172                                bool offset_loaded,
 173                                uint64_t *offset,
 174                                uint64_t *stat);
 175 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 176 static void i40e_dev_interrupt_handler(
 177                 __rte_unused struct rte_intr_handle *handle, void *param);
 178 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 179                                 uint32_t base, uint32_t num);
 180 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 181 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 182                         uint32_t base);
 183 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 184                         uint16_t num);
 185 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 186 static int i40e_veb_release(struct i40e_veb *veb);
 187 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 188                                                 struct i40e_vsi *vsi);
 189 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 190 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 191 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 192                                              struct i40e_macvlan_filter *mv_f,
 193                                              int num,
 194                                              struct ether_addr *addr);
 195 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 196                                              struct i40e_macvlan_filter *mv_f,
 197                                              int num,
 198                                              uint16_t vlan);
 199 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 200 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 201                                     struct rte_eth_rss_conf *rss_conf);
 202 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 203                                       struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 205                                 struct rte_eth_udp_tunnel *udp_tunnel);
 206 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 207                                 struct rte_eth_udp_tunnel *udp_tunnel);
 208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 209                                 enum rte_filter_type filter_type,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212
 213 /* Default hash key buffer for RSS */
 214 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 215
 216 static struct rte_pci_id pci_id_i40e_map[] = {
 217 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 218 #include "rte_pci_dev_ids.h"
 219 { .vendor_id = 0, /* sentinel */ },
 220 };
 221
 222 static struct eth_dev_ops i40e_eth_dev_ops = {
 223         .dev_configure                = i40e_dev_configure,
 224         .dev_start                    = i40e_dev_start,
 225         .dev_stop                     = i40e_dev_stop,
 226         .dev_close                    = i40e_dev_close,
 227         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 228         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 229         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 230         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 231         .dev_set_link_up              = i40e_dev_set_link_up,
 232         .dev_set_link_down            = i40e_dev_set_link_down,
 233         .link_update                  = i40e_dev_link_update,
 234         .stats_get                    = i40e_dev_stats_get,
 235         .stats_reset                  = i40e_dev_stats_reset,
 236         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 237         .dev_infos_get                = i40e_dev_info_get,
 238         .vlan_filter_set              = i40e_vlan_filter_set,
 239         .vlan_tpid_set                = i40e_vlan_tpid_set,
 240         .vlan_offload_set             = i40e_vlan_offload_set,
 241         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 242         .vlan_pvid_set                = i40e_vlan_pvid_set,
 243         .rx_queue_start               = i40e_dev_rx_queue_start,
 244         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 245         .tx_queue_start               = i40e_dev_tx_queue_start,
 246         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 247         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 248         .rx_queue_release             = i40e_dev_rx_queue_release,
 249         .rx_queue_count               = i40e_dev_rx_queue_count,
 250         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 251         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 252         .tx_queue_release             = i40e_dev_tx_queue_release,
 253         .dev_led_on                   = i40e_dev_led_on,
 254         .dev_led_off                  = i40e_dev_led_off,
 255         .flow_ctrl_set                = i40e_flow_ctrl_set,
 256         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 257         .mac_addr_add                 = i40e_macaddr_add,
 258         .mac_addr_remove              = i40e_macaddr_remove,
 259         .reta_update                  = i40e_dev_rss_reta_update,
 260         .reta_query                   = i40e_dev_rss_reta_query,
 261         .rss_hash_update              = i40e_dev_rss_hash_update,
 262         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 263         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 264         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 265         .filter_ctrl                  = i40e_dev_filter_ctrl,
 266 };
 267
 268 static struct eth_driver rte_i40e_pmd = {
 269         {
 270                 .name = "rte_i40e_pmd",
 271                 .id_table = pci_id_i40e_map,
 272                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 273         },
 274         .eth_dev_init = eth_i40e_dev_init,
 275         .dev_private_size = sizeof(struct i40e_adapter),
 276 };
 277
 278 static inline int
 279 i40e_align_floor(int n)
 280 {
 281         if (n == 0)
 282                 return 0;
 283         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 284 }
 285
 286 static inline int
 287 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 288                                      struct rte_eth_link *link)
 289 {
 290         struct rte_eth_link *dst = link;
 291         struct rte_eth_link *src = &(dev->data->dev_link);
 292
 293         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 294                                         *(uint64_t *)src) == 0)
 295                 return -1;
 296
 297         return 0;
 298 }
 299
 300 static inline int
 301 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 302                                       struct rte_eth_link *link)
 303 {
 304         struct rte_eth_link *dst = &(dev->data->dev_link);
 305         struct rte_eth_link *src = link;
 306
 307         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 308                                         *(uint64_t *)src) == 0)
 309                 return -1;
 310
 311         return 0;
 312 }
 313
 314 /*
 315  * Driver initialization routine.
 316  * Invoked once at EAL init time.
 317  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 318  */
 319 static int
 320 rte_i40e_pmd_init(const char *name __rte_unused,
 321                   const char *params __rte_unused)
 322 {
 323         PMD_INIT_FUNC_TRACE();
 324         rte_eth_driver_register(&rte_i40e_pmd);
 325
 326         return 0;
 327 }
 328
 329 static struct rte_driver rte_i40e_driver = {
 330         .type = PMD_PDEV,
 331         .init = rte_i40e_pmd_init,
 332 };
 333
 334 PMD_REGISTER_DRIVER(rte_i40e_driver);
 335
 336 static int
 337 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 338                   struct rte_eth_dev *dev)
 339 {
 340         struct rte_pci_device *pci_dev;
 341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 343         struct i40e_vsi *vsi;
 344         int ret;
 345         uint32_t len;
 346         uint8_t aq_fail = 0;
 347
 348         PMD_INIT_FUNC_TRACE();
 349
 350         dev->dev_ops = &i40e_eth_dev_ops;
 351         dev->rx_pkt_burst = i40e_recv_pkts;
 352         dev->tx_pkt_burst = i40e_xmit_pkts;
 353
 354         /* for secondary processes, we don't initialise any further as primary
 355          * has already done this work. Only check we don't need a different
 356          * RX function */
 357         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 358                 if (dev->data->scattered_rx)
 359                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 360                 return 0;
 361         }
 362         pci_dev = dev->pci_dev;
 363         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 364         pf->adapter->eth_dev = dev;
 365         pf->dev_data = dev->data;
 366
 367         hw->back = I40E_PF_TO_ADAPTER(pf);
 368         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 369         if (!hw->hw_addr) {
 370                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 371                              "as address is NULL");
 372                 return -ENODEV;
 373         }
 374
 375         hw->vendor_id = pci_dev->id.vendor_id;
 376         hw->device_id = pci_dev->id.device_id;
 377         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 378         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 379         hw->bus.device = pci_dev->addr.devid;
 380         hw->bus.func = pci_dev->addr.function;
 381
 382         /* Make sure all is clean before doing PF reset */
 383         i40e_clear_hw(hw);
 384
 385         /* Reset here to make sure all is clean for each PF */
 386         ret = i40e_pf_reset(hw);
 387         if (ret) {
 388                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 389                 return ret;
 390         }
 391
 392         /* Initialize the shared code (base driver) */
 393         ret = i40e_init_shared_code(hw);
 394         if (ret) {
 395                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 396                 return ret;
 397         }
 398
 399         /* Initialize the parameters for adminq */
 400         i40e_init_adminq_parameter(hw);
 401         ret = i40e_init_adminq(hw);
 402         if (ret != I40E_SUCCESS) {
 403                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 404                 return -EIO;
 405         }
 406         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 407                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 408                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 409                      ((hw->nvm.version >> 12) & 0xf),
 410                      ((hw->nvm.version >> 4) & 0xff),
 411                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 412
 413         /* Disable LLDP */
 414         ret = i40e_aq_stop_lldp(hw, true, NULL);
 415         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 416                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 417
 418         /* Clear PXE mode */
 419         i40e_clear_pxe_mode(hw);
 420
 421         /* Get hw capabilities */
 422         ret = i40e_get_cap(hw);
 423         if (ret != I40E_SUCCESS) {
 424                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 425                 goto err_get_capabilities;
 426         }
 427
 428         /* Initialize parameters for PF */
 429         ret = i40e_pf_parameter_init(dev);
 430         if (ret != 0) {
 431                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 432                 goto err_parameter_init;
 433         }
 434
 435         /* Initialize the queue management */
 436         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 437         if (ret < 0) {
 438                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 439                 goto err_qp_pool_init;
 440         }
 441         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 442                                 hw->func_caps.num_msix_vectors - 1);
 443         if (ret < 0) {
 444                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 445                 goto err_msix_pool_init;
 446         }
 447
 448         /* Initialize lan hmc */
 449         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 450                                 hw->func_caps.num_rx_qp, 0, 0);
 451         if (ret != I40E_SUCCESS) {
 452                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 453                 goto err_init_lan_hmc;
 454         }
 455
 456         /* Configure lan hmc */
 457         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 458         if (ret != I40E_SUCCESS) {
 459                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 460                 goto err_configure_lan_hmc;
 461         }
 462
 463         /* Get and check the mac address */
 464         i40e_get_mac_addr(hw, hw->mac.addr);
 465         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 466                 PMD_INIT_LOG(ERR, "mac address is not valid");
 467                 ret = -EIO;
 468                 goto err_get_mac_addr;
 469         }
 470         /* Copy the permanent MAC address */
 471         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 472                         (struct ether_addr *) hw->mac.perm_addr);
 473
 474         /* Disable flow control */
 475         hw->fc.requested_mode = I40E_FC_NONE;
 476         i40e_set_fc(hw, &aq_fail, TRUE);
 477
 478         /* PF setup, which includes VSI setup */
 479         ret = i40e_pf_setup(pf);
 480         if (ret) {
 481                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 482                 goto err_setup_pf_switch;
 483         }
 484
 485         vsi = pf->main_vsi;
 486
 487         /* Disable double vlan by default */
 488         i40e_vsi_config_double_vlan(vsi, FALSE);
 489
 490         if (!vsi->max_macaddrs)
 491                 len = ETHER_ADDR_LEN;
 492         else
 493                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 494
 495         /* Should be after VSI initialized */
 496         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 497         if (!dev->data->mac_addrs) {
 498                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 499                                         "for storing mac address");
 500                 goto err_mac_alloc;
 501         }
 502         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 503                                         &dev->data->mac_addrs[0]);
 504
 505         /* initialize pf host driver to setup SRIOV resource if applicable */
 506         i40e_pf_host_init(dev);
 507
 508         /* register callback func to eal lib */
 509         rte_intr_callback_register(&(pci_dev->intr_handle),
 510                 i40e_dev_interrupt_handler, (void *)dev);
 511
 512         /* configure and enable device interrupt */
 513         i40e_pf_config_irq0(hw);
 514         i40e_pf_enable_irq0(hw);
 515
 516         /* enable uio intr after callback register */
 517         rte_intr_enable(&(pci_dev->intr_handle));
 518
 519         return 0;
 520
 521 err_mac_alloc:
 522         i40e_vsi_release(pf->main_vsi);
 523 err_setup_pf_switch:
 524 err_get_mac_addr:
 525 err_configure_lan_hmc:
 526         (void)i40e_shutdown_lan_hmc(hw);
 527 err_init_lan_hmc:
 528         i40e_res_pool_destroy(&pf->msix_pool);
 529 err_msix_pool_init:
 530         i40e_res_pool_destroy(&pf->qp_pool);
 531 err_qp_pool_init:
 532 err_parameter_init:
 533 err_get_capabilities:
 534         (void)i40e_shutdown_adminq(hw);
 535
 536         return ret;
 537 }
 538
 539 static int
 540 i40e_dev_configure(struct rte_eth_dev *dev)
 541 {
 542         int ret;
 543         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 544
 545         /* VMDQ setup.
 546          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 547          *  RSS setting have different requirements.
 548          *  General PMD driver call sequence are NIC init, configure,
 549          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 550          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 551          *  applicable. So, VMDQ setting has to be done before
 552          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 553          *  For RSS setting, it will try to calculate actual configured RX queue
 554          *  number, which will be available after rx_queue_setup(). dev_start()
 555          *  function is good to place RSS setup.
 556          */
 557         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 558                 ret = i40e_vmdq_setup(dev);
 559                 if (ret)
 560                         return ret;
 561         }
 562
 563         return i40e_dev_init_vlan(dev);
 564 }
 565
 566 void
 567 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 568 {
 569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 570         uint16_t msix_vect = vsi->msix_intr;
 571         uint16_t i;
 572
 573         for (i = 0; i < vsi->nb_qps; i++) {
 574                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 575                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 576                 rte_wmb();
 577         }
 578
 579         if (vsi->type != I40E_VSI_SRIOV) {
 580                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 581                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 582                                 msix_vect - 1), 0);
 583         } else {
 584                 uint32_t reg;
 585                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 586                         vsi->user_param + (msix_vect - 1);
 587
 588                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 589         }
 590         I40E_WRITE_FLUSH(hw);
 591 }
 592
 593 static inline uint16_t
 594 i40e_calc_itr_interval(int16_t interval)
 595 {
 596         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 597                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 598
 599         /* Convert to hardware count, as writing each 1 represents 2 us */
 600         return (interval/2);
 601 }
 602
 603 void
 604 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 605 {
 606         uint32_t val;
 607         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 608         uint16_t msix_vect = vsi->msix_intr;
 609         int i;
 610
 611         for (i = 0; i < vsi->nb_qps; i++)
 612                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 613
 614         /* Bind all RX queues to allocated MSIX interrupt */
 615         for (i = 0; i < vsi->nb_qps; i++) {
 616                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 617                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 618                         ((vsi->base_queue + i + 1) <<
 619                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 620                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 621                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 622
 623                 if (i == vsi->nb_qps - 1)
 624                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 625                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 626         }
 627
 628         /* Write first RX queue to Link list register as the head element */
 629         if (vsi->type != I40E_VSI_SRIOV) {
 630                 uint16_t interval =
 631                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 632
 633                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 634                                                 (vsi->base_queue <<
 635                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 636                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 637
 638                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 639                                                 msix_vect - 1), interval);
 640
 641 #ifndef I40E_GLINT_CTL
 642 #define I40E_GLINT_CTL                     0x0003F800
 643 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 644 #endif
 645                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 646                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 647                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 648         } else {
 649                 uint32_t reg;
 650
 651                 /* num_msix_vectors_vf needs to minus irq0 */
 652                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 653                         vsi->user_param + (msix_vect - 1);
 654
 655                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 656                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 657                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 658         }
 659
 660         I40E_WRITE_FLUSH(hw);
 661 }
 662
 663 static void
 664 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 665 {
 666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 667         uint16_t interval = i40e_calc_itr_interval(\
 668                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 669
 670         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 671                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 672                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 673                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 674                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 675 }
 676
 677 static void
 678 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 679 {
 680         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 681
 682         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 683 }
 684
 685 static inline uint8_t
 686 i40e_parse_link_speed(uint16_t eth_link_speed)
 687 {
 688         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 689
 690         switch (eth_link_speed) {
 691         case ETH_LINK_SPEED_40G:
 692                 link_speed = I40E_LINK_SPEED_40GB;
 693                 break;
 694         case ETH_LINK_SPEED_20G:
 695                 link_speed = I40E_LINK_SPEED_20GB;
 696                 break;
 697         case ETH_LINK_SPEED_10G:
 698                 link_speed = I40E_LINK_SPEED_10GB;
 699                 break;
 700         case ETH_LINK_SPEED_1000:
 701                 link_speed = I40E_LINK_SPEED_1GB;
 702                 break;
 703         case ETH_LINK_SPEED_100:
 704                 link_speed = I40E_LINK_SPEED_100MB;
 705                 break;
 706         }
 707
 708         return link_speed;
 709 }
 710
 711 static int
 712 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 713 {
 714         enum i40e_status_code status;
 715         struct i40e_aq_get_phy_abilities_resp phy_ab;
 716         struct i40e_aq_set_phy_config phy_conf;
 717         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 718                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 719                         I40E_AQ_PHY_FLAG_LOW_POWER;
 720         const uint8_t advt = I40E_LINK_SPEED_40GB |
 721                         I40E_LINK_SPEED_10GB |
 722                         I40E_LINK_SPEED_1GB |
 723                         I40E_LINK_SPEED_100MB;
 724         int ret = -ENOTSUP;
 725
 726         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 727                                               NULL);
 728         if (status)
 729                 return ret;
 730
 731         memset(&phy_conf, 0, sizeof(phy_conf));
 732
 733         /* bits 0-2 use the values from get_phy_abilities_resp */
 734         abilities &= ~mask;
 735         abilities |= phy_ab.abilities & mask;
 736
 737         /* update ablities and speed */
 738         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 739                 phy_conf.link_speed = advt;
 740         else
 741                 phy_conf.link_speed = force_speed;
 742
 743         phy_conf.abilities = abilities;
 744
 745         /* use get_phy_abilities_resp value for the rest */
 746         phy_conf.phy_type = phy_ab.phy_type;
 747         phy_conf.eee_capability = phy_ab.eee_capability;
 748         phy_conf.eeer = phy_ab.eeer_val;
 749         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 750
 751         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 752                     phy_ab.abilities, phy_ab.link_speed);
 753         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 754                     phy_conf.abilities, phy_conf.link_speed);
 755
 756         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 757         if (status)
 758                 return ret;
 759
 760         return I40E_SUCCESS;
 761 }
 762
 763 static int
 764 i40e_apply_link_speed(struct rte_eth_dev *dev)
 765 {
 766         uint8_t speed;
 767         uint8_t abilities = 0;
 768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 769         struct rte_eth_conf *conf = &dev->data->dev_conf;
 770
 771         speed = i40e_parse_link_speed(conf->link_speed);
 772         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 773         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 774                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 775         else
 776                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 777
 778         return i40e_phy_conf_link(hw, abilities, speed);
 779 }
 780
 781 static int
 782 i40e_dev_start(struct rte_eth_dev *dev)
 783 {
 784         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 786         struct i40e_vsi *vsi = pf->main_vsi;
 787         int ret;
 788
 789         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 790                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 791                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 792                              dev->data->dev_conf.link_duplex,
 793                              dev->data->port_id);
 794                 return -EINVAL;
 795         }
 796
 797         /* Initialize VSI */
 798         ret = i40e_vsi_init(vsi);
 799         if (ret != I40E_SUCCESS) {
 800                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 801                 goto err_up;
 802         }
 803
 804         /* Map queues with MSIX interrupt */
 805         i40e_vsi_queues_bind_intr(vsi);
 806         i40e_vsi_enable_queues_intr(vsi);
 807
 808         /* Enable all queues which have been configured */
 809         ret = i40e_vsi_switch_queues(vsi, TRUE);
 810         if (ret != I40E_SUCCESS) {
 811                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 812                 goto err_up;
 813         }
 814
 815         /* Enable receiving broadcast packets */
 816         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 817                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 818                 if (ret != I40E_SUCCESS)
 819                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 820         }
 821
 822         /* Apply link configure */
 823         ret = i40e_apply_link_speed(dev);
 824         if (I40E_SUCCESS != ret) {
 825                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 826                 goto err_up;
 827         }
 828
 829         return I40E_SUCCESS;
 830
 831 err_up:
 832         i40e_vsi_switch_queues(vsi, FALSE);
 833
 834         return ret;
 835 }
 836
 837 static void
 838 i40e_dev_stop(struct rte_eth_dev *dev)
 839 {
 840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 841         struct i40e_vsi *vsi = pf->main_vsi;
 842
 843         /* Disable all queues */
 844         i40e_vsi_switch_queues(vsi, FALSE);
 845
 846         /* Set link down */
 847         i40e_dev_set_link_down(dev);
 848
 849         /* un-map queues with interrupt registers */
 850         i40e_vsi_disable_queues_intr(vsi);
 851         i40e_vsi_queues_unbind_intr(vsi);
 852 }
 853
 854 static void
 855 i40e_dev_close(struct rte_eth_dev *dev)
 856 {
 857         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 859         uint32_t reg;
 860
 861         PMD_INIT_FUNC_TRACE();
 862
 863         i40e_dev_stop(dev);
 864
 865         /* Disable interrupt */
 866         i40e_pf_disable_irq0(hw);
 867         rte_intr_disable(&(dev->pci_dev->intr_handle));
 868
 869         /* shutdown and destroy the HMC */
 870         i40e_shutdown_lan_hmc(hw);
 871
 872         /* release all the existing VSIs and VEBs */
 873         i40e_vsi_release(pf->main_vsi);
 874
 875         /* shutdown the adminq */
 876         i40e_aq_queue_shutdown(hw, true);
 877         i40e_shutdown_adminq(hw);
 878
 879         i40e_res_pool_destroy(&pf->qp_pool);
 880         i40e_res_pool_destroy(&pf->msix_pool);
 881
 882         /* force a PF reset to clean anything leftover */
 883         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 884         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 885                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 886         I40E_WRITE_FLUSH(hw);
 887 }
 888
 889 static void
 890 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 891 {
 892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 894         struct i40e_vsi *vsi = pf->main_vsi;
 895         int status;
 896
 897         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 898                                                         true, NULL);
 899         if (status != I40E_SUCCESS)
 900                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 901
 902         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 903                                                         TRUE, NULL);
 904         if (status != I40E_SUCCESS)
 905                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 906
 907 }
 908
 909 static void
 910 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 911 {
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914         struct i40e_vsi *vsi = pf->main_vsi;
 915         int status;
 916
 917         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 918                                                         false, NULL);
 919         if (status != I40E_SUCCESS)
 920                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 921
 922         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 923                                                         false, NULL);
 924         if (status != I40E_SUCCESS)
 925                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 926 }
 927
 928 static void
 929 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 930 {
 931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933         struct i40e_vsi *vsi = pf->main_vsi;
 934         int ret;
 935
 936         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 937         if (ret != I40E_SUCCESS)
 938                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 939 }
 940
 941 static void
 942 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 943 {
 944         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 946         struct i40e_vsi *vsi = pf->main_vsi;
 947         int ret;
 948
 949         if (dev->data->promiscuous == 1)
 950                 return; /* must remain in all_multicast mode */
 951
 952         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 953                                 vsi->seid, FALSE, NULL);
 954         if (ret != I40E_SUCCESS)
 955                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 956 }
 957
 958 /*
 959  * Set device link up.
 960  */
 961 static int
 962 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 963 {
 964         /* re-apply link speed setting */
 965         return i40e_apply_link_speed(dev);
 966 }
 967
 968 /*
 969  * Set device link down.
 970  */
 971 static int
 972 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 973 {
 974         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 975         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 976         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 977
 978         return i40e_phy_conf_link(hw, abilities, speed);
 979 }
 980
 981 int
 982 i40e_dev_link_update(struct rte_eth_dev *dev,
 983                      __rte_unused int wait_to_complete)
 984 {
 985         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 986         struct i40e_link_status link_status;
 987         struct rte_eth_link link, old;
 988         int status;
 989
 990         memset(&link, 0, sizeof(link));
 991         memset(&old, 0, sizeof(old));
 992         memset(&link_status, 0, sizeof(link_status));
 993         rte_i40e_dev_atomic_read_link_status(dev, &old);
 994
 995         /* Get link status information from hardware */
 996         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 997         if (status != I40E_SUCCESS) {
 998                 link.link_speed = ETH_LINK_SPEED_100;
 999                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1000                 PMD_DRV_LOG(ERR, "Failed to get link info");
1001                 goto out;
1002         }
1003
1004         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1005
1006         if (!link.link_status)
1007                 goto out;
1008
1009         /* i40e uses full duplex only */
1010         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1011
1012         /* Parse the link status */
1013         switch (link_status.link_speed) {
1014         case I40E_LINK_SPEED_100MB:
1015                 link.link_speed = ETH_LINK_SPEED_100;
1016                 break;
1017         case I40E_LINK_SPEED_1GB:
1018                 link.link_speed = ETH_LINK_SPEED_1000;
1019                 break;
1020         case I40E_LINK_SPEED_10GB:
1021                 link.link_speed = ETH_LINK_SPEED_10G;
1022                 break;
1023         case I40E_LINK_SPEED_20GB:
1024                 link.link_speed = ETH_LINK_SPEED_20G;
1025                 break;
1026         case I40E_LINK_SPEED_40GB:
1027                 link.link_speed = ETH_LINK_SPEED_40G;
1028                 break;
1029         default:
1030                 link.link_speed = ETH_LINK_SPEED_100;
1031                 break;
1032         }
1033
1034 out:
1035         rte_i40e_dev_atomic_write_link_status(dev, &link);
1036         if (link.link_status == old.link_status)
1037                 return -1;
1038
1039         return 0;
1040 }
1041
1042 /* Get all the statistics of a VSI */
1043 void
1044 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1045 {
1046         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1047         struct i40e_eth_stats *nes = &vsi->eth_stats;
1048         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1049         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1050
1051         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1052                             vsi->offset_loaded, &oes->rx_bytes,
1053                             &nes->rx_bytes);
1054         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1055                             vsi->offset_loaded, &oes->rx_unicast,
1056                             &nes->rx_unicast);
1057         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1058                             vsi->offset_loaded, &oes->rx_multicast,
1059                             &nes->rx_multicast);
1060         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1061                             vsi->offset_loaded, &oes->rx_broadcast,
1062                             &nes->rx_broadcast);
1063         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1064                             &oes->rx_discards, &nes->rx_discards);
1065         /* GLV_REPC not supported */
1066         /* GLV_RMPC not supported */
1067         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1068                             &oes->rx_unknown_protocol,
1069                             &nes->rx_unknown_protocol);
1070         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1071                             vsi->offset_loaded, &oes->tx_bytes,
1072                             &nes->tx_bytes);
1073         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1074                             vsi->offset_loaded, &oes->tx_unicast,
1075                             &nes->tx_unicast);
1076         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1077                             vsi->offset_loaded, &oes->tx_multicast,
1078                             &nes->tx_multicast);
1079         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1080                             vsi->offset_loaded,  &oes->tx_broadcast,
1081                             &nes->tx_broadcast);
1082         /* GLV_TDPC not supported */
1083         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1084                             &oes->tx_errors, &nes->tx_errors);
1085         vsi->offset_loaded = true;
1086
1087         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1088                     vsi->vsi_id);
1089         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1090         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1091         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1092         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1093         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1094         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1095                     nes->rx_unknown_protocol);
1096         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1097         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1098         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1099         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1100         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1101         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1102         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1103                     vsi->vsi_id);
1104 }
1105
1106 /* Get all statistics of a port */
1107 static void
1108 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1109 {
1110         uint32_t i;
1111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1114         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1115
1116         /* Get statistics of struct i40e_eth_stats */
1117         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1118                             I40E_GLPRT_GORCL(hw->port),
1119                             pf->offset_loaded, &os->eth.rx_bytes,
1120                             &ns->eth.rx_bytes);
1121         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1122                             I40E_GLPRT_UPRCL(hw->port),
1123                             pf->offset_loaded, &os->eth.rx_unicast,
1124                             &ns->eth.rx_unicast);
1125         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1126                             I40E_GLPRT_MPRCL(hw->port),
1127                             pf->offset_loaded, &os->eth.rx_multicast,
1128                             &ns->eth.rx_multicast);
1129         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1130                             I40E_GLPRT_BPRCL(hw->port),
1131                             pf->offset_loaded, &os->eth.rx_broadcast,
1132                             &ns->eth.rx_broadcast);
1133         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1134                             pf->offset_loaded, &os->eth.rx_discards,
1135                             &ns->eth.rx_discards);
1136         /* GLPRT_REPC not supported */
1137         /* GLPRT_RMPC not supported */
1138         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1139                             pf->offset_loaded,
1140                             &os->eth.rx_unknown_protocol,
1141                             &ns->eth.rx_unknown_protocol);
1142         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1143                             I40E_GLPRT_GOTCL(hw->port),
1144                             pf->offset_loaded, &os->eth.tx_bytes,
1145                             &ns->eth.tx_bytes);
1146         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1147                             I40E_GLPRT_UPTCL(hw->port),
1148                             pf->offset_loaded, &os->eth.tx_unicast,
1149                             &ns->eth.tx_unicast);
1150         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1151                             I40E_GLPRT_MPTCL(hw->port),
1152                             pf->offset_loaded, &os->eth.tx_multicast,
1153                             &ns->eth.tx_multicast);
1154         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1155                             I40E_GLPRT_BPTCL(hw->port),
1156                             pf->offset_loaded, &os->eth.tx_broadcast,
1157                             &ns->eth.tx_broadcast);
1158         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1159                             pf->offset_loaded, &os->eth.tx_discards,
1160                             &ns->eth.tx_discards);
1161         /* GLPRT_TEPC not supported */
1162
1163         /* additional port specific stats */
1164         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1165                             pf->offset_loaded, &os->tx_dropped_link_down,
1166                             &ns->tx_dropped_link_down);
1167         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1168                             pf->offset_loaded, &os->crc_errors,
1169                             &ns->crc_errors);
1170         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1171                             pf->offset_loaded, &os->illegal_bytes,
1172                             &ns->illegal_bytes);
1173         /* GLPRT_ERRBC not supported */
1174         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1175                             pf->offset_loaded, &os->mac_local_faults,
1176                             &ns->mac_local_faults);
1177         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1178                             pf->offset_loaded, &os->mac_remote_faults,
1179                             &ns->mac_remote_faults);
1180         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1181                             pf->offset_loaded, &os->rx_length_errors,
1182                             &ns->rx_length_errors);
1183         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1184                             pf->offset_loaded, &os->link_xon_rx,
1185                             &ns->link_xon_rx);
1186         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1187                             pf->offset_loaded, &os->link_xoff_rx,
1188                             &ns->link_xoff_rx);
1189         for (i = 0; i < 8; i++) {
1190                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1191                                     pf->offset_loaded,
1192                                     &os->priority_xon_rx[i],
1193                                     &ns->priority_xon_rx[i]);
1194                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1195                                     pf->offset_loaded,
1196                                     &os->priority_xoff_rx[i],
1197                                     &ns->priority_xoff_rx[i]);
1198         }
1199         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1200                             pf->offset_loaded, &os->link_xon_tx,
1201                             &ns->link_xon_tx);
1202         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1203                             pf->offset_loaded, &os->link_xoff_tx,
1204                             &ns->link_xoff_tx);
1205         for (i = 0; i < 8; i++) {
1206                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1207                                     pf->offset_loaded,
1208                                     &os->priority_xon_tx[i],
1209                                     &ns->priority_xon_tx[i]);
1210                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1211                                     pf->offset_loaded,
1212                                     &os->priority_xoff_tx[i],
1213                                     &ns->priority_xoff_tx[i]);
1214                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1215                                     pf->offset_loaded,
1216                                     &os->priority_xon_2_xoff[i],
1217                                     &ns->priority_xon_2_xoff[i]);
1218         }
1219         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1220                             I40E_GLPRT_PRC64L(hw->port),
1221                             pf->offset_loaded, &os->rx_size_64,
1222                             &ns->rx_size_64);
1223         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1224                             I40E_GLPRT_PRC127L(hw->port),
1225                             pf->offset_loaded, &os->rx_size_127,
1226                             &ns->rx_size_127);
1227         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1228                             I40E_GLPRT_PRC255L(hw->port),
1229                             pf->offset_loaded, &os->rx_size_255,
1230                             &ns->rx_size_255);
1231         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1232                             I40E_GLPRT_PRC511L(hw->port),
1233                             pf->offset_loaded, &os->rx_size_511,
1234                             &ns->rx_size_511);
1235         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1236                             I40E_GLPRT_PRC1023L(hw->port),
1237                             pf->offset_loaded, &os->rx_size_1023,
1238                             &ns->rx_size_1023);
1239         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1240                             I40E_GLPRT_PRC1522L(hw->port),
1241                             pf->offset_loaded, &os->rx_size_1522,
1242                             &ns->rx_size_1522);
1243         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1244                             I40E_GLPRT_PRC9522L(hw->port),
1245                             pf->offset_loaded, &os->rx_size_big,
1246                             &ns->rx_size_big);
1247         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1248                             pf->offset_loaded, &os->rx_undersize,
1249                             &ns->rx_undersize);
1250         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1251                             pf->offset_loaded, &os->rx_fragments,
1252                             &ns->rx_fragments);
1253         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1254                             pf->offset_loaded, &os->rx_oversize,
1255                             &ns->rx_oversize);
1256         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1257                             pf->offset_loaded, &os->rx_jabber,
1258                             &ns->rx_jabber);
1259         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1260                             I40E_GLPRT_PTC64L(hw->port),
1261                             pf->offset_loaded, &os->tx_size_64,
1262                             &ns->tx_size_64);
1263         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1264                             I40E_GLPRT_PTC127L(hw->port),
1265                             pf->offset_loaded, &os->tx_size_127,
1266                             &ns->tx_size_127);
1267         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1268                             I40E_GLPRT_PTC255L(hw->port),
1269                             pf->offset_loaded, &os->tx_size_255,
1270                             &ns->tx_size_255);
1271         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1272                             I40E_GLPRT_PTC511L(hw->port),
1273                             pf->offset_loaded, &os->tx_size_511,
1274                             &ns->tx_size_511);
1275         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1276                             I40E_GLPRT_PTC1023L(hw->port),
1277                             pf->offset_loaded, &os->tx_size_1023,
1278                             &ns->tx_size_1023);
1279         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1280                             I40E_GLPRT_PTC1522L(hw->port),
1281                             pf->offset_loaded, &os->tx_size_1522,
1282                             &ns->tx_size_1522);
1283         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1284                             I40E_GLPRT_PTC9522L(hw->port),
1285                             pf->offset_loaded, &os->tx_size_big,
1286                             &ns->tx_size_big);
1287         /* GLPRT_MSPDC not supported */
1288         /* GLPRT_XEC not supported */
1289
1290         pf->offset_loaded = true;
1291
1292         if (pf->main_vsi)
1293                 i40e_update_vsi_stats(pf->main_vsi);
1294
1295         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1296                                                 ns->eth.rx_broadcast;
1297         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1298                                                 ns->eth.tx_broadcast;
1299         stats->ibytes   = ns->eth.rx_bytes;
1300         stats->obytes   = ns->eth.tx_bytes;
1301         stats->oerrors  = ns->eth.tx_errors;
1302         stats->imcasts  = ns->eth.rx_multicast;
1303
1304         /* Rx Errors */
1305         stats->ibadcrc  = ns->crc_errors;
1306         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1307                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1308         stats->imissed  = ns->eth.rx_discards;
1309         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1310
1311         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1312         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1313         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1314         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1315         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1316         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1317         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1318                     ns->eth.rx_unknown_protocol);
1319         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1320         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1321         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1322         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1323         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1324         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1325
1326         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1327                     ns->tx_dropped_link_down);
1328         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1329         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1330                     ns->illegal_bytes);
1331         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1332         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1333                     ns->mac_local_faults);
1334         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1335                     ns->mac_remote_faults);
1336         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1337                     ns->rx_length_errors);
1338         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1339         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1340         for (i = 0; i < 8; i++) {
1341                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1342                                 i, ns->priority_xon_rx[i]);
1343                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1344                                 i, ns->priority_xoff_rx[i]);
1345         }
1346         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1347         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1348         for (i = 0; i < 8; i++) {
1349                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1350                                 i, ns->priority_xon_tx[i]);
1351                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1352                                 i, ns->priority_xoff_tx[i]);
1353                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1354                                 i, ns->priority_xon_2_xoff[i]);
1355         }
1356         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1357         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1358         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1359         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1360         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1361         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1362         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1363         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1364         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1365         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1366         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1367         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1368         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1369         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1370         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1371         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1372         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1373         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1374         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1375                         ns->mac_short_packet_dropped);
1376         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1377                     ns->checksum_error);
1378         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1379 }
1380
1381 /* Reset the statistics */
1382 static void
1383 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1384 {
1385         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1386
1387         /* It results in reloading the start point of each counter */
1388         pf->offset_loaded = false;
1389 }
1390
1391 static int
1392 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1393                                  __rte_unused uint16_t queue_id,
1394                                  __rte_unused uint8_t stat_idx,
1395                                  __rte_unused uint8_t is_rx)
1396 {
1397         PMD_INIT_FUNC_TRACE();
1398
1399         return -ENOSYS;
1400 }
1401
1402 static void
1403 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1404 {
1405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1406         struct i40e_vsi *vsi = pf->main_vsi;
1407
1408         dev_info->max_rx_queues = vsi->nb_qps;
1409         dev_info->max_tx_queues = vsi->nb_qps;
1410         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1411         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1412         dev_info->max_mac_addrs = vsi->max_macaddrs;
1413         dev_info->max_vfs = dev->pci_dev->max_vfs;
1414         dev_info->rx_offload_capa =
1415                 DEV_RX_OFFLOAD_VLAN_STRIP |
1416                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1417                 DEV_RX_OFFLOAD_UDP_CKSUM |
1418                 DEV_RX_OFFLOAD_TCP_CKSUM;
1419         dev_info->tx_offload_capa =
1420                 DEV_TX_OFFLOAD_VLAN_INSERT |
1421                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1422                 DEV_TX_OFFLOAD_UDP_CKSUM |
1423                 DEV_TX_OFFLOAD_TCP_CKSUM |
1424                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1425
1426         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1427                 .rx_thresh = {
1428                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1429                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1430                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1431                 },
1432                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1433                 .rx_drop_en = 0,
1434         };
1435
1436         dev_info->default_txconf = (struct rte_eth_txconf) {
1437                 .tx_thresh = {
1438                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1439                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1440                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1441                 },
1442                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1443                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1444                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1445         };
1446
1447         if (pf->flags | I40E_FLAG_VMDQ) {
1448                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1449                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1450                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1451                                                 pf->max_nb_vmdq_vsi;
1452                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1453                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1454                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1455         }
1456 }
1457
1458 static int
1459 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1460 {
1461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1462         struct i40e_vsi *vsi = pf->main_vsi;
1463         PMD_INIT_FUNC_TRACE();
1464
1465         if (on)
1466                 return i40e_vsi_add_vlan(vsi, vlan_id);
1467         else
1468                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1469 }
1470
1471 static void
1472 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1473                    __rte_unused uint16_t tpid)
1474 {
1475         PMD_INIT_FUNC_TRACE();
1476 }
1477
1478 static void
1479 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1480 {
1481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1482         struct i40e_vsi *vsi = pf->main_vsi;
1483
1484         if (mask & ETH_VLAN_STRIP_MASK) {
1485                 /* Enable or disable VLAN stripping */
1486                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1487                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1488                 else
1489                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1490         }
1491
1492         if (mask & ETH_VLAN_EXTEND_MASK) {
1493                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1494                         i40e_vsi_config_double_vlan(vsi, TRUE);
1495                 else
1496                         i40e_vsi_config_double_vlan(vsi, FALSE);
1497         }
1498 }
1499
1500 static void
1501 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1502                           __rte_unused uint16_t queue,
1503                           __rte_unused int on)
1504 {
1505         PMD_INIT_FUNC_TRACE();
1506 }
1507
1508 static int
1509 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1510 {
1511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1512         struct i40e_vsi *vsi = pf->main_vsi;
1513         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1514         struct i40e_vsi_vlan_pvid_info info;
1515
1516         memset(&info, 0, sizeof(info));
1517         info.on = on;
1518         if (info.on)
1519                 info.config.pvid = pvid;
1520         else {
1521                 info.config.reject.tagged =
1522                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1523                 info.config.reject.untagged =
1524                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1525         }
1526
1527         return i40e_vsi_vlan_pvid_set(vsi, &info);
1528 }
1529
1530 static int
1531 i40e_dev_led_on(struct rte_eth_dev *dev)
1532 {
1533         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534         uint32_t mode = i40e_led_get(hw);
1535
1536         if (mode == 0)
1537                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1538
1539         return 0;
1540 }
1541
1542 static int
1543 i40e_dev_led_off(struct rte_eth_dev *dev)
1544 {
1545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1546         uint32_t mode = i40e_led_get(hw);
1547
1548         if (mode != 0)
1549                 i40e_led_set(hw, 0, false);
1550
1551         return 0;
1552 }
1553
1554 static int
1555 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1556                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1557 {
1558         PMD_INIT_FUNC_TRACE();
1559
1560         return -ENOSYS;
1561 }
1562
1563 static int
1564 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1565                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1566 {
1567         PMD_INIT_FUNC_TRACE();
1568
1569         return -ENOSYS;
1570 }
1571
1572 /* Add a MAC address, and update filters */
1573 static void
1574 i40e_macaddr_add(struct rte_eth_dev *dev,
1575                  struct ether_addr *mac_addr,
1576                  __attribute__((unused)) uint32_t index,
1577                  __attribute__((unused)) uint32_t pool)
1578 {
1579         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1580         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581         struct i40e_mac_filter_info mac_filter;
1582         struct i40e_vsi *vsi = pf->main_vsi;
1583         struct ether_addr old_mac;
1584         int ret;
1585
1586         if (!is_valid_assigned_ether_addr(mac_addr)) {
1587                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1588                 return;
1589         }
1590
1591         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1592                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1593                 return;
1594         }
1595
1596         /* Write mac address */
1597         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1598                                         mac_addr->addr_bytes, NULL);
1599         if (ret != I40E_SUCCESS) {
1600                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1601                 return;
1602         }
1603
1604         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1605         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1606                         ETHER_ADDR_LEN);
1607         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1608         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1609
1610         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1611         if (ret != I40E_SUCCESS) {
1612                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1613                 return;
1614         }
1615
1616         ether_addr_copy(mac_addr, &pf->dev_addr);
1617         i40e_vsi_delete_mac(vsi, &old_mac);
1618 }
1619
1620 /* Remove a MAC address, and update filters */
1621 static void
1622 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1623 {
1624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625         struct i40e_vsi *vsi = pf->main_vsi;
1626         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1627         struct ether_addr *macaddr;
1628         int ret;
1629         struct i40e_hw *hw =
1630                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631
1632         if (index >= vsi->max_macaddrs)
1633                 return;
1634
1635         macaddr = &(data->mac_addrs[index]);
1636         if (!is_valid_assigned_ether_addr(macaddr))
1637                 return;
1638
1639         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1640                                         hw->mac.perm_addr, NULL);
1641         if (ret != I40E_SUCCESS) {
1642                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1643                 return;
1644         }
1645
1646         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1647
1648         ret = i40e_vsi_delete_mac(vsi, macaddr);
1649         if (ret != I40E_SUCCESS)
1650                 return;
1651
1652         /* Clear device address as it has been removed */
1653         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1654                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1655 }
1656
1657 /* Set perfect match or hash match of MAC and VLAN for a VF */
1658 static int
1659 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1660                  struct rte_eth_mac_filter *filter,
1661                  bool add)
1662 {
1663         struct i40e_hw *hw;
1664         struct i40e_mac_filter_info mac_filter;
1665         struct ether_addr old_mac;
1666         struct ether_addr *new_mac;
1667         struct i40e_pf_vf *vf = NULL;
1668         uint16_t vf_id;
1669         int ret;
1670
1671         if (pf == NULL) {
1672                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1673                 return -EINVAL;
1674         }
1675         hw = I40E_PF_TO_HW(pf);
1676
1677         if (filter == NULL) {
1678                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1679                 return -EINVAL;
1680         }
1681
1682         new_mac = &filter->mac_addr;
1683
1684         if (is_zero_ether_addr(new_mac)) {
1685                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1686                 return -EINVAL;
1687         }
1688
1689         vf_id = filter->dst_id;
1690
1691         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1692                 PMD_DRV_LOG(ERR, "Invalid argument.");
1693                 return -EINVAL;
1694         }
1695         vf = &pf->vfs[vf_id];
1696
1697         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1698                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1699                 return -EINVAL;
1700         }
1701
1702         if (add) {
1703                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1704                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1705                                 ETHER_ADDR_LEN);
1706                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1707                                  ETHER_ADDR_LEN);
1708
1709                 mac_filter.filter_type = filter->filter_type;
1710                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1711                 if (ret != I40E_SUCCESS) {
1712                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1713                         return -1;
1714                 }
1715                 ether_addr_copy(new_mac, &pf->dev_addr);
1716         } else {
1717                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1718                                 ETHER_ADDR_LEN);
1719                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1720                 if (ret != I40E_SUCCESS) {
1721                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1722                         return -1;
1723                 }
1724
1725                 /* Clear device address as it has been removed */
1726                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1727                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1728         }
1729
1730         return 0;
1731 }
1732
1733 /* MAC filter handle */
1734 static int
1735 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1736                 void *arg)
1737 {
1738         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1739         struct rte_eth_mac_filter *filter;
1740         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1741         int ret = I40E_NOT_SUPPORTED;
1742
1743         filter = (struct rte_eth_mac_filter *)(arg);
1744
1745         switch (filter_op) {
1746         case RTE_ETH_FILTER_NONE:
1747                 ret = I40E_SUCCESS;
1748                 break;
1749         case RTE_ETH_FILTER_ADD:
1750                 i40e_pf_disable_irq0(hw);
1751                 if (filter->is_vf)
1752                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1753                 i40e_pf_enable_irq0(hw);
1754                 break;
1755         case RTE_ETH_FILTER_DELETE:
1756                 i40e_pf_disable_irq0(hw);
1757                 if (filter->is_vf)
1758                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1759                 i40e_pf_enable_irq0(hw);
1760                 break;
1761         default:
1762                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1763                 ret = I40E_ERR_PARAM;
1764                 break;
1765         }
1766
1767         return ret;
1768 }
1769
1770 static int
1771 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1772                          struct rte_eth_rss_reta *reta_conf)
1773 {
1774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t lut, l;
1776         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1777
1778         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1779                 if (i < max)
1780                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1781                 else
1782                         mask = (uint8_t)((reta_conf->mask_hi >>
1783                                                 (i - max)) & 0xF);
1784
1785                 if (!mask)
1786                         continue;
1787
1788                 if (mask == 0xF)
1789                         l = 0;
1790                 else
1791                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1792
1793                 for (j = 0, lut = 0; j < 4; j++) {
1794                         if (mask & (0x1 << j))
1795                                 lut |= reta_conf->reta[i + j] << (8 * j);
1796                         else
1797                                 lut |= l & (0xFF << (8 * j));
1798                 }
1799                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int
1806 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1807                         struct rte_eth_rss_reta *reta_conf)
1808 {
1809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810         uint32_t lut;
1811         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1812
1813         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1814                 if (i < max)
1815                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1816                 else
1817                         mask = (uint8_t)((reta_conf->mask_hi >>
1818                                                 (i - max)) & 0xF);
1819
1820                 if (!mask)
1821                         continue;
1822
1823                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1824                 for (j = 0; j < 4; j++) {
1825                         if (mask & (0x1 << j))
1826                                 reta_conf->reta[i + j] =
1827                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1828                 }
1829         }
1830
1831         return 0;
1832 }
1833
1834 /**
1835  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1836  * @hw:   pointer to the HW structure
1837  * @mem:  pointer to mem struct to fill out
1838  * @size: size of memory requested
1839  * @alignment: what to align the allocation to
1840  **/
1841 enum i40e_status_code
1842 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1843                         struct i40e_dma_mem *mem,
1844                         u64 size,
1845                         u32 alignment)
1846 {
1847         static uint64_t id = 0;
1848         const struct rte_memzone *mz = NULL;
1849         char z_name[RTE_MEMZONE_NAMESIZE];
1850
1851         if (!mem)
1852                 return I40E_ERR_PARAM;
1853
1854         id++;
1855         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1856 #ifdef RTE_LIBRTE_XEN_DOM0
1857         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1858                                                         RTE_PGSIZE_2M);
1859 #else
1860         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1861 #endif
1862         if (!mz)
1863                 return I40E_ERR_NO_MEMORY;
1864
1865         mem->id = id;
1866         mem->size = size;
1867         mem->va = mz->addr;
1868 #ifdef RTE_LIBRTE_XEN_DOM0
1869         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1870 #else
1871         mem->pa = mz->phys_addr;
1872 #endif
1873
1874         return I40E_SUCCESS;
1875 }
1876
1877 /**
1878  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1879  * @hw:   pointer to the HW structure
1880  * @mem:  ptr to mem struct to free
1881  **/
1882 enum i40e_status_code
1883 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1884                     struct i40e_dma_mem *mem)
1885 {
1886         if (!mem || !mem->va)
1887                 return I40E_ERR_PARAM;
1888
1889         mem->va = NULL;
1890         mem->pa = (u64)0;
1891
1892         return I40E_SUCCESS;
1893 }
1894
1895 /**
1896  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1897  * @hw:   pointer to the HW structure
1898  * @mem:  pointer to mem struct to fill out
1899  * @size: size of memory requested
1900  **/
1901 enum i40e_status_code
1902 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1903                          struct i40e_virt_mem *mem,
1904                          u32 size)
1905 {
1906         if (!mem)
1907                 return I40E_ERR_PARAM;
1908
1909         mem->size = size;
1910         mem->va = rte_zmalloc("i40e", size, 0);
1911
1912         if (mem->va)
1913                 return I40E_SUCCESS;
1914         else
1915                 return I40E_ERR_NO_MEMORY;
1916 }
1917
1918 /**
1919  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1920  * @hw:   pointer to the HW structure
1921  * @mem:  pointer to mem struct to free
1922  **/
1923 enum i40e_status_code
1924 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1925                      struct i40e_virt_mem *mem)
1926 {
1927         if (!mem)
1928                 return I40E_ERR_PARAM;
1929
1930         rte_free(mem->va);
1931         mem->va = NULL;
1932
1933         return I40E_SUCCESS;
1934 }
1935
1936 void
1937 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1938 {
1939         rte_spinlock_init(&sp->spinlock);
1940 }
1941
1942 void
1943 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1944 {
1945         rte_spinlock_lock(&sp->spinlock);
1946 }
1947
1948 void
1949 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1950 {
1951         rte_spinlock_unlock(&sp->spinlock);
1952 }
1953
1954 void
1955 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1956 {
1957         return;
1958 }
1959
1960 /**
1961  * Get the hardware capabilities, which will be parsed
1962  * and saved into struct i40e_hw.
1963  */
1964 static int
1965 i40e_get_cap(struct i40e_hw *hw)
1966 {
1967         struct i40e_aqc_list_capabilities_element_resp *buf;
1968         uint16_t len, size = 0;
1969         int ret;
1970
1971         /* Calculate a huge enough buff for saving response data temporarily */
1972         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1973                                                 I40E_MAX_CAP_ELE_NUM;
1974         buf = rte_zmalloc("i40e", len, 0);
1975         if (!buf) {
1976                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1977                 return I40E_ERR_NO_MEMORY;
1978         }
1979
1980         /* Get, parse the capabilities and save it to hw */
1981         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1982                         i40e_aqc_opc_list_func_capabilities, NULL);
1983         if (ret != I40E_SUCCESS)
1984                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1985
1986         /* Free the temporary buffer after being used */
1987         rte_free(buf);
1988
1989         return ret;
1990 }
1991
1992 static int
1993 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1994 {
1995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1997         uint16_t sum_queues = 0, sum_vsis, left_queues;
1998
1999         /* First check if FW support SRIOV */
2000         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2001                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2002                 return -EINVAL;
2003         }
2004
2005         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2006         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2007         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2008         /* Allocate queues for pf */
2009         if (hw->func_caps.rss) {
2010                 pf->flags |= I40E_FLAG_RSS;
2011                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2012                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2013                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2014         } else
2015                 pf->lan_nb_qps = 1;
2016         sum_queues = pf->lan_nb_qps;
2017         /* Default VSI is not counted in */
2018         sum_vsis = 0;
2019         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2020
2021         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2022                 pf->flags |= I40E_FLAG_SRIOV;
2023                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2024                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2025                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2026                                      "max supported %u.",
2027                                      dev->pci_dev->max_vfs,
2028                                      hw->func_caps.num_vfs);
2029                         return -EINVAL;
2030                 }
2031                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2032                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2033                                      "max support %u queues.",
2034                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2035                         return -EINVAL;
2036                 }
2037                 pf->vf_num = dev->pci_dev->max_vfs;
2038                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2039                 sum_vsis   += pf->vf_num;
2040                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2041                              pf->vf_num, pf->vf_nb_qps);
2042         } else
2043                 pf->vf_num = 0;
2044
2045         if (hw->func_caps.vmdq) {
2046                 pf->flags |= I40E_FLAG_VMDQ;
2047                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2048                 pf->max_nb_vmdq_vsi = 1;
2049                 /*
2050                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2051                  * later.
2052                  */
2053                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2054                 sum_vsis += pf->max_nb_vmdq_vsi;
2055         } else {
2056                 pf->vmdq_nb_qps = 0;
2057                 pf->max_nb_vmdq_vsi = 0;
2058         }
2059         pf->nb_cfg_vmdq_vsi = 0;
2060
2061         if (hw->func_caps.fd) {
2062                 pf->flags |= I40E_FLAG_FDIR;
2063                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2064                 /**
2065                  * Each flow director consumes one VSI and one queue,
2066                  * but can't calculate out predictably here.
2067                  */
2068         }
2069
2070         if (sum_vsis > pf->max_num_vsi ||
2071                 sum_queues > hw->func_caps.num_rx_qp) {
2072                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2073                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2074                              pf->max_num_vsi, sum_vsis);
2075                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2076                              hw->func_caps.num_rx_qp, sum_queues);
2077                 return -EINVAL;
2078         }
2079
2080         /* Adjust VMDQ setting to support as many VMs as possible */
2081         if (pf->flags & I40E_FLAG_VMDQ) {
2082                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2083
2084                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2085                                         pf->max_num_vsi - sum_vsis);
2086
2087                 /* Limit the max VMDQ number that rte_ether that can support  */
2088                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2089                                         ETH_64_POOLS - 1);
2090
2091                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2092                                 pf->max_nb_vmdq_vsi);
2093                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2094         }
2095
2096         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2097          * cause */
2098         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2099                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2100                              sum_vsis, hw->func_caps.num_msix_vectors);
2101                 return -EINVAL;
2102         }
2103         return I40E_SUCCESS;
2104 }
2105
2106 static int
2107 i40e_pf_get_switch_config(struct i40e_pf *pf)
2108 {
2109         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2110         struct i40e_aqc_get_switch_config_resp *switch_config;
2111         struct i40e_aqc_switch_config_element_resp *element;
2112         uint16_t start_seid = 0, num_reported;
2113         int ret;
2114
2115         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2116                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2117         if (!switch_config) {
2118                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2119                 return -ENOMEM;
2120         }
2121
2122         /* Get the switch configurations */
2123         ret = i40e_aq_get_switch_config(hw, switch_config,
2124                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2125         if (ret != I40E_SUCCESS) {
2126                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2127                 goto fail;
2128         }
2129         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2130         if (num_reported != 1) { /* The number should be 1 */
2131                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2132                 goto fail;
2133         }
2134
2135         /* Parse the switch configuration elements */
2136         element = &(switch_config->element[0]);
2137         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2138                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2139                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2140         } else
2141                 PMD_DRV_LOG(INFO, "Unknown element type");
2142
2143 fail:
2144         rte_free(switch_config);
2145
2146         return ret;
2147 }
2148
2149 static int
2150 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2151                         uint32_t num)
2152 {
2153         struct pool_entry *entry;
2154
2155         if (pool == NULL || num == 0)
2156                 return -EINVAL;
2157
2158         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2159         if (entry == NULL) {
2160                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2161                 return -ENOMEM;
2162         }
2163
2164         /* queue heap initialize */
2165         pool->num_free = num;
2166         pool->num_alloc = 0;
2167         pool->base = base;
2168         LIST_INIT(&pool->alloc_list);
2169         LIST_INIT(&pool->free_list);
2170
2171         /* Initialize element  */
2172         entry->base = 0;
2173         entry->len = num;
2174
2175         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2176         return 0;
2177 }
2178
2179 static void
2180 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2181 {
2182         struct pool_entry *entry;
2183
2184         if (pool == NULL)
2185                 return;
2186
2187         LIST_FOREACH(entry, &pool->alloc_list, next) {
2188                 LIST_REMOVE(entry, next);
2189                 rte_free(entry);
2190         }
2191
2192         LIST_FOREACH(entry, &pool->free_list, next) {
2193                 LIST_REMOVE(entry, next);
2194                 rte_free(entry);
2195         }
2196
2197         pool->num_free = 0;
2198         pool->num_alloc = 0;
2199         pool->base = 0;
2200         LIST_INIT(&pool->alloc_list);
2201         LIST_INIT(&pool->free_list);
2202 }
2203
2204 static int
2205 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2206                        uint32_t base)
2207 {
2208         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2209         uint32_t pool_offset;
2210         int insert;
2211
2212         if (pool == NULL) {
2213                 PMD_DRV_LOG(ERR, "Invalid parameter");
2214                 return -EINVAL;
2215         }
2216
2217         pool_offset = base - pool->base;
2218         /* Lookup in alloc list */
2219         LIST_FOREACH(entry, &pool->alloc_list, next) {
2220                 if (entry->base == pool_offset) {
2221                         valid_entry = entry;
2222                         LIST_REMOVE(entry, next);
2223                         break;
2224                 }
2225         }
2226
2227         /* Not find, return */
2228         if (valid_entry == NULL) {
2229                 PMD_DRV_LOG(ERR, "Failed to find entry");
2230                 return -EINVAL;
2231         }
2232
2233         /**
2234          * Found it, move it to free list  and try to merge.
2235          * In order to make merge easier, always sort it by qbase.
2236          * Find adjacent prev and last entries.
2237          */
2238         prev = next = NULL;
2239         LIST_FOREACH(entry, &pool->free_list, next) {
2240                 if (entry->base > valid_entry->base) {
2241                         next = entry;
2242                         break;
2243                 }
2244                 prev = entry;
2245         }
2246
2247         insert = 0;
2248         /* Try to merge with next one*/
2249         if (next != NULL) {
2250                 /* Merge with next one */
2251                 if (valid_entry->base + valid_entry->len == next->base) {
2252                         next->base = valid_entry->base;
2253                         next->len += valid_entry->len;
2254                         rte_free(valid_entry);
2255                         valid_entry = next;
2256                         insert = 1;
2257                 }
2258         }
2259
2260         if (prev != NULL) {
2261                 /* Merge with previous one */
2262                 if (prev->base + prev->len == valid_entry->base) {
2263                         prev->len += valid_entry->len;
2264                         /* If it merge with next one, remove next node */
2265                         if (insert == 1) {
2266                                 LIST_REMOVE(valid_entry, next);
2267                                 rte_free(valid_entry);
2268                         } else {
2269                                 rte_free(valid_entry);
2270                                 insert = 1;
2271                         }
2272                 }
2273         }
2274
2275         /* Not find any entry to merge, insert */
2276         if (insert == 0) {
2277                 if (prev != NULL)
2278                         LIST_INSERT_AFTER(prev, valid_entry, next);
2279                 else if (next != NULL)
2280                         LIST_INSERT_BEFORE(next, valid_entry, next);
2281                 else /* It's empty list, insert to head */
2282                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2283         }
2284
2285         pool->num_free += valid_entry->len;
2286         pool->num_alloc -= valid_entry->len;
2287
2288         return 0;
2289 }
2290
2291 static int
2292 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2293                        uint16_t num)
2294 {
2295         struct pool_entry *entry, *valid_entry;
2296
2297         if (pool == NULL || num == 0) {
2298                 PMD_DRV_LOG(ERR, "Invalid parameter");
2299                 return -EINVAL;
2300         }
2301
2302         if (pool->num_free < num) {
2303                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2304                             num, pool->num_free);
2305                 return -ENOMEM;
2306         }
2307
2308         valid_entry = NULL;
2309         /* Lookup  in free list and find most fit one */
2310         LIST_FOREACH(entry, &pool->free_list, next) {
2311                 if (entry->len >= num) {
2312                         /* Find best one */
2313                         if (entry->len == num) {
2314                                 valid_entry = entry;
2315                                 break;
2316                         }
2317                         if (valid_entry == NULL || valid_entry->len > entry->len)
2318                                 valid_entry = entry;
2319                 }
2320         }
2321
2322         /* Not find one to satisfy the request, return */
2323         if (valid_entry == NULL) {
2324                 PMD_DRV_LOG(ERR, "No valid entry found");
2325                 return -ENOMEM;
2326         }
2327         /**
2328          * The entry have equal queue number as requested,
2329          * remove it from alloc_list.
2330          */
2331         if (valid_entry->len == num) {
2332                 LIST_REMOVE(valid_entry, next);
2333         } else {
2334                 /**
2335                  * The entry have more numbers than requested,
2336                  * create a new entry for alloc_list and minus its
2337                  * queue base and number in free_list.
2338                  */
2339                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2340                 if (entry == NULL) {
2341                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2342                                     "resource pool");
2343                         return -ENOMEM;
2344                 }
2345                 entry->base = valid_entry->base;
2346                 entry->len = num;
2347                 valid_entry->base += num;
2348                 valid_entry->len -= num;
2349                 valid_entry = entry;
2350         }
2351
2352         /* Insert it into alloc list, not sorted */
2353         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2354
2355         pool->num_free -= valid_entry->len;
2356         pool->num_alloc += valid_entry->len;
2357
2358         return (valid_entry->base + pool->base);
2359 }
2360
2361 /**
2362  * bitmap_is_subset - Check whether src2 is subset of src1
2363  **/
2364 static inline int
2365 bitmap_is_subset(uint8_t src1, uint8_t src2)
2366 {
2367         return !((src1 ^ src2) & src2);
2368 }
2369
2370 static int
2371 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2372 {
2373         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2374
2375         /* If DCB is not supported, only default TC is supported */
2376         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2377                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2378                 return -EINVAL;
2379         }
2380
2381         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2382                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2383                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2384                             enabled_tcmap);
2385                 return -EINVAL;
2386         }
2387         return I40E_SUCCESS;
2388 }
2389
2390 int
2391 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2392                                 struct i40e_vsi_vlan_pvid_info *info)
2393 {
2394         struct i40e_hw *hw;
2395         struct i40e_vsi_context ctxt;
2396         uint8_t vlan_flags = 0;
2397         int ret;
2398
2399         if (vsi == NULL || info == NULL) {
2400                 PMD_DRV_LOG(ERR, "invalid parameters");
2401                 return I40E_ERR_PARAM;
2402         }
2403
2404         if (info->on) {
2405                 vsi->info.pvid = info->config.pvid;
2406                 /**
2407                  * If insert pvid is enabled, only tagged pkts are
2408                  * allowed to be sent out.
2409                  */
2410                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2411                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2412         } else {
2413                 vsi->info.pvid = 0;
2414                 if (info->config.reject.tagged == 0)
2415                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2416
2417                 if (info->config.reject.untagged == 0)
2418                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2419         }
2420         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2421                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2422         vsi->info.port_vlan_flags |= vlan_flags;
2423         vsi->info.valid_sections =
2424                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2425         memset(&ctxt, 0, sizeof(ctxt));
2426         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2427         ctxt.seid = vsi->seid;
2428
2429         hw = I40E_VSI_TO_HW(vsi);
2430         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2431         if (ret != I40E_SUCCESS)
2432                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2433
2434         return ret;
2435 }
2436
2437 static int
2438 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2439 {
2440         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2441         int i, ret;
2442         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2443
2444         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2445         if (ret != I40E_SUCCESS)
2446                 return ret;
2447
2448         if (!vsi->seid) {
2449                 PMD_DRV_LOG(ERR, "seid not valid");
2450                 return -EINVAL;
2451         }
2452
2453         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2454         tc_bw_data.tc_valid_bits = enabled_tcmap;
2455         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2456                 tc_bw_data.tc_bw_credits[i] =
2457                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2458
2459         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2460         if (ret != I40E_SUCCESS) {
2461                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2462                 return ret;
2463         }
2464
2465         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2466                                         sizeof(vsi->info.qs_handle));
2467         return I40E_SUCCESS;
2468 }
2469
2470 static int
2471 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2472                                  struct i40e_aqc_vsi_properties_data *info,
2473                                  uint8_t enabled_tcmap)
2474 {
2475         int ret, total_tc = 0, i;
2476         uint16_t qpnum_per_tc, bsf, qp_idx;
2477
2478         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2479         if (ret != I40E_SUCCESS)
2480                 return ret;
2481
2482         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2483                 if (enabled_tcmap & (1 << i))
2484                         total_tc++;
2485         vsi->enabled_tc = enabled_tcmap;
2486
2487         /* Number of queues per enabled TC */
2488         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2489         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2490         bsf = rte_bsf32(qpnum_per_tc);
2491
2492         /* Adjust the queue number to actual queues that can be applied */
2493         vsi->nb_qps = qpnum_per_tc * total_tc;
2494
2495         /**
2496          * Configure TC and queue mapping parameters, for enabled TC,
2497          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2498          * default queue will serve it.
2499          */
2500         qp_idx = 0;
2501         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2502                 if (vsi->enabled_tc & (1 << i)) {
2503                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2504                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2505                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2506                         qp_idx += qpnum_per_tc;
2507                 } else
2508                         info->tc_mapping[i] = 0;
2509         }
2510
2511         /* Associate queue number with VSI */
2512         if (vsi->type == I40E_VSI_SRIOV) {
2513                 info->mapping_flags |=
2514                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2515                 for (i = 0; i < vsi->nb_qps; i++)
2516                         info->queue_mapping[i] =
2517                                 rte_cpu_to_le_16(vsi->base_queue + i);
2518         } else {
2519                 info->mapping_flags |=
2520                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2521                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2522         }
2523         info->valid_sections =
2524                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2525
2526         return I40E_SUCCESS;
2527 }
2528
2529 static int
2530 i40e_veb_release(struct i40e_veb *veb)
2531 {
2532         struct i40e_vsi *vsi;
2533         struct i40e_hw *hw;
2534
2535         if (veb == NULL || veb->associate_vsi == NULL)
2536                 return -EINVAL;
2537
2538         if (!TAILQ_EMPTY(&veb->head)) {
2539                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2540                 return -EACCES;
2541         }
2542
2543         vsi = veb->associate_vsi;
2544         hw = I40E_VSI_TO_HW(vsi);
2545
2546         vsi->uplink_seid = veb->uplink_seid;
2547         i40e_aq_delete_element(hw, veb->seid, NULL);
2548         rte_free(veb);
2549         vsi->veb = NULL;
2550         return I40E_SUCCESS;
2551 }
2552
2553 /* Setup a veb */
2554 static struct i40e_veb *
2555 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2556 {
2557         struct i40e_veb *veb;
2558         int ret;
2559         struct i40e_hw *hw;
2560
2561         if (NULL == pf || vsi == NULL) {
2562                 PMD_DRV_LOG(ERR, "veb setup failed, "
2563                             "associated VSI shouldn't null");
2564                 return NULL;
2565         }
2566         hw = I40E_PF_TO_HW(pf);
2567
2568         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2569         if (!veb) {
2570                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2571                 goto fail;
2572         }
2573
2574         veb->associate_vsi = vsi;
2575         TAILQ_INIT(&veb->head);
2576         veb->uplink_seid = vsi->uplink_seid;
2577
2578         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2579                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2580
2581         if (ret != I40E_SUCCESS) {
2582                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2583                             hw->aq.asq_last_status);
2584                 goto fail;
2585         }
2586
2587         /* get statistics index */
2588         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2589                                 &veb->stats_idx, NULL, NULL, NULL);
2590         if (ret != I40E_SUCCESS) {
2591                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2592                             hw->aq.asq_last_status);
2593                 goto fail;
2594         }
2595
2596         /* Get VEB bandwidth, to be implemented */
2597         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2598         vsi->uplink_seid = veb->seid;
2599
2600         return veb;
2601 fail:
2602         rte_free(veb);
2603         return NULL;
2604 }
2605
2606 int
2607 i40e_vsi_release(struct i40e_vsi *vsi)
2608 {
2609         struct i40e_pf *pf;
2610         struct i40e_hw *hw;
2611         struct i40e_vsi_list *vsi_list;
2612         int ret;
2613         struct i40e_mac_filter *f;
2614
2615         if (!vsi)
2616                 return I40E_SUCCESS;
2617
2618         pf = I40E_VSI_TO_PF(vsi);
2619         hw = I40E_VSI_TO_HW(vsi);
2620
2621         /* VSI has child to attach, release child first */
2622         if (vsi->veb) {
2623                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2624                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2625                                 return -1;
2626                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2627                 }
2628                 i40e_veb_release(vsi->veb);
2629         }
2630
2631         /* Remove all macvlan filters of the VSI */
2632         i40e_vsi_remove_all_macvlan_filter(vsi);
2633         TAILQ_FOREACH(f, &vsi->mac_list, next)
2634                 rte_free(f);
2635
2636         if (vsi->type != I40E_VSI_MAIN) {
2637                 /* Remove vsi from parent's sibling list */
2638                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2639                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2640                         return I40E_ERR_PARAM;
2641                 }
2642                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2643                                 &vsi->sib_vsi_list, list);
2644
2645                 /* Remove all switch element of the VSI */
2646                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2647                 if (ret != I40E_SUCCESS)
2648                         PMD_DRV_LOG(ERR, "Failed to delete element");
2649         }
2650         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2651
2652         if (vsi->type != I40E_VSI_SRIOV)
2653                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2654         rte_free(vsi);
2655
2656         return I40E_SUCCESS;
2657 }
2658
2659 static int
2660 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2661 {
2662         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2663         struct i40e_aqc_remove_macvlan_element_data def_filter;
2664         struct i40e_mac_filter_info filter;
2665         int ret;
2666
2667         if (vsi->type != I40E_VSI_MAIN)
2668                 return I40E_ERR_CONFIG;
2669         memset(&def_filter, 0, sizeof(def_filter));
2670         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2671                                         ETH_ADDR_LEN);
2672         def_filter.vlan_tag = 0;
2673         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2674                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2675         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2676         if (ret != I40E_SUCCESS) {
2677                 struct i40e_mac_filter *f;
2678                 struct ether_addr *mac;
2679
2680                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2681                             "macvlan filter");
2682                 /* It needs to add the permanent mac into mac list */
2683                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2684                 if (f == NULL) {
2685                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2686                         return I40E_ERR_NO_MEMORY;
2687                 }
2688                 mac = &f->mac_info.mac_addr;
2689                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2690                                 ETH_ADDR_LEN);
2691                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2692                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2693                 vsi->mac_num++;
2694
2695                 return ret;
2696         }
2697         (void)rte_memcpy(&filter.mac_addr,
2698                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2699         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2700         return i40e_vsi_add_mac(vsi, &filter);
2701 }
2702
2703 static int
2704 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2705 {
2706         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2707         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2708         struct i40e_hw *hw = &vsi->adapter->hw;
2709         i40e_status ret;
2710         int i;
2711
2712         memset(&bw_config, 0, sizeof(bw_config));
2713         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2714         if (ret != I40E_SUCCESS) {
2715                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2716                             hw->aq.asq_last_status);
2717                 return ret;
2718         }
2719
2720         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2721         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2722                                         &ets_sla_config, NULL);
2723         if (ret != I40E_SUCCESS) {
2724                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2725                             "configuration %u", hw->aq.asq_last_status);
2726                 return ret;
2727         }
2728
2729         /* Not store the info yet, just print out */
2730         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2731         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2732         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2733                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2734                             ets_sla_config.share_credits[i]);
2735                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2736                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2737                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2738                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2739                             (i * 4));
2740         }
2741
2742         return 0;
2743 }
2744
2745 /* Setup a VSI */
2746 struct i40e_vsi *
2747 i40e_vsi_setup(struct i40e_pf *pf,
2748                enum i40e_vsi_type type,
2749                struct i40e_vsi *uplink_vsi,
2750                uint16_t user_param)
2751 {
2752         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2753         struct i40e_vsi *vsi;
2754         struct i40e_mac_filter_info filter;
2755         int ret;
2756         struct i40e_vsi_context ctxt;
2757         struct ether_addr broadcast =
2758                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2759
2760         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2761                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2762                             "VSI link shouldn't be NULL");
2763                 return NULL;
2764         }
2765
2766         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2767                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2768                             "uplink VSI should be NULL");
2769                 return NULL;
2770         }
2771
2772         /* If uplink vsi didn't setup VEB, create one first */
2773         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2774                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2775
2776                 if (NULL == uplink_vsi->veb) {
2777                         PMD_DRV_LOG(ERR, "VEB setup failed");
2778                         return NULL;
2779                 }
2780         }
2781
2782         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2783         if (!vsi) {
2784                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2785                 return NULL;
2786         }
2787         TAILQ_INIT(&vsi->mac_list);
2788         vsi->type = type;
2789         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2790         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2791         vsi->parent_vsi = uplink_vsi;
2792         vsi->user_param = user_param;
2793         /* Allocate queues */
2794         switch (vsi->type) {
2795         case I40E_VSI_MAIN  :
2796                 vsi->nb_qps = pf->lan_nb_qps;
2797                 break;
2798         case I40E_VSI_SRIOV :
2799                 vsi->nb_qps = pf->vf_nb_qps;
2800                 break;
2801         case I40E_VSI_VMDQ2:
2802                 vsi->nb_qps = pf->vmdq_nb_qps;
2803                 break;
2804         default:
2805                 goto fail_mem;
2806         }
2807         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2808         if (ret < 0) {
2809                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2810                                 vsi->seid, ret);
2811                 goto fail_mem;
2812         }
2813         vsi->base_queue = ret;
2814
2815         /* VF has MSIX interrupt in VF range, don't allocate here */
2816         if (type != I40E_VSI_SRIOV) {
2817                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2818                 if (ret < 0) {
2819                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2820                         goto fail_queue_alloc;
2821                 }
2822                 vsi->msix_intr = ret;
2823         } else
2824                 vsi->msix_intr = 0;
2825         /* Add VSI */
2826         if (type == I40E_VSI_MAIN) {
2827                 /* For main VSI, no need to add since it's default one */
2828                 vsi->uplink_seid = pf->mac_seid;
2829                 vsi->seid = pf->main_vsi_seid;
2830                 /* Bind queues with specific MSIX interrupt */
2831                 /**
2832                  * Needs 2 interrupt at least, one for misc cause which will
2833                  * enabled from OS side, Another for queues binding the
2834                  * interrupt from device side only.
2835                  */
2836
2837                 /* Get default VSI parameters from hardware */
2838                 memset(&ctxt, 0, sizeof(ctxt));
2839                 ctxt.seid = vsi->seid;
2840                 ctxt.pf_num = hw->pf_id;
2841                 ctxt.uplink_seid = vsi->uplink_seid;
2842                 ctxt.vf_num = 0;
2843                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2844                 if (ret != I40E_SUCCESS) {
2845                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2846                         goto fail_msix_alloc;
2847                 }
2848                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2849                         sizeof(struct i40e_aqc_vsi_properties_data));
2850                 vsi->vsi_id = ctxt.vsi_number;
2851                 vsi->info.valid_sections = 0;
2852
2853                 /* Configure tc, enabled TC0 only */
2854                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2855                         I40E_SUCCESS) {
2856                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2857                         goto fail_msix_alloc;
2858                 }
2859
2860                 /* TC, queue mapping */
2861                 memset(&ctxt, 0, sizeof(ctxt));
2862                 vsi->info.valid_sections |=
2863                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2864                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2865                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2866                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2867                         sizeof(struct i40e_aqc_vsi_properties_data));
2868                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2869                                                 I40E_DEFAULT_TCMAP);
2870                 if (ret != I40E_SUCCESS) {
2871                         PMD_DRV_LOG(ERR, "Failed to configure "
2872                                     "TC queue mapping");
2873                         goto fail_msix_alloc;
2874                 }
2875                 ctxt.seid = vsi->seid;
2876                 ctxt.pf_num = hw->pf_id;
2877                 ctxt.uplink_seid = vsi->uplink_seid;
2878                 ctxt.vf_num = 0;
2879
2880                 /* Update VSI parameters */
2881                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2882                 if (ret != I40E_SUCCESS) {
2883                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2884                         goto fail_msix_alloc;
2885                 }
2886
2887                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2888                                                 sizeof(vsi->info.tc_mapping));
2889                 (void)rte_memcpy(&vsi->info.queue_mapping,
2890                                 &ctxt.info.queue_mapping,
2891                         sizeof(vsi->info.queue_mapping));
2892                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2893                 vsi->info.valid_sections = 0;
2894
2895                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2896                                 ETH_ADDR_LEN);
2897
2898                 /**
2899                  * Updating default filter settings are necessary to prevent
2900                  * reception of tagged packets.
2901                  * Some old firmware configurations load a default macvlan
2902                  * filter which accepts both tagged and untagged packets.
2903                  * The updating is to use a normal filter instead if needed.
2904                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2905                  * The firmware with correct configurations load the default
2906                  * macvlan filter which is expected and cannot be removed.
2907                  */
2908                 i40e_update_default_filter_setting(vsi);
2909         } else if (type == I40E_VSI_SRIOV) {
2910                 memset(&ctxt, 0, sizeof(ctxt));
2911                 /**
2912                  * For other VSI, the uplink_seid equals to uplink VSI's
2913                  * uplink_seid since they share same VEB
2914                  */
2915                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2916                 ctxt.pf_num = hw->pf_id;
2917                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2918                 ctxt.uplink_seid = vsi->uplink_seid;
2919                 ctxt.connection_type = 0x1;
2920                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2921
2922                 /* Configure switch ID */
2923                 ctxt.info.valid_sections |=
2924                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2925                 ctxt.info.switch_id =
2926                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2927                 /* Configure port/vlan */
2928                 ctxt.info.valid_sections |=
2929                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2930                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2931                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2932                                                 I40E_DEFAULT_TCMAP);
2933                 if (ret != I40E_SUCCESS) {
2934                         PMD_DRV_LOG(ERR, "Failed to configure "
2935                                     "TC queue mapping");
2936                         goto fail_msix_alloc;
2937                 }
2938                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2939                 ctxt.info.valid_sections |=
2940                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2941                 /**
2942                  * Since VSI is not created yet, only configure parameter,
2943                  * will add vsi below.
2944                  */
2945         } else if (type == I40E_VSI_VMDQ2) {
2946                 memset(&ctxt, 0, sizeof(ctxt));
2947                 /*
2948                  * For other VSI, the uplink_seid equals to uplink VSI's
2949                  * uplink_seid since they share same VEB
2950                  */
2951                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2952                 ctxt.pf_num = hw->pf_id;
2953                 ctxt.vf_num = 0;
2954                 ctxt.uplink_seid = vsi->uplink_seid;
2955                 ctxt.connection_type = 0x1;
2956                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
2957
2958                 ctxt.info.valid_sections |=
2959                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2960                 /* user_param carries flag to enable loop back */
2961                 if (user_param) {
2962                         ctxt.info.switch_id =
2963                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
2964                         ctxt.info.switch_id |=
2965                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2966                 }
2967
2968                 /* Configure port/vlan */
2969                 ctxt.info.valid_sections |=
2970                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2971                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2972                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2973                                                 I40E_DEFAULT_TCMAP);
2974                 if (ret != I40E_SUCCESS) {
2975                         PMD_DRV_LOG(ERR, "Failed to configure "
2976                                         "TC queue mapping");
2977                         goto fail_msix_alloc;
2978                 }
2979                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2980                 ctxt.info.valid_sections |=
2981                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2982         } else {
2983                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2984                 goto fail_msix_alloc;
2985         }
2986
2987         if (vsi->type != I40E_VSI_MAIN) {
2988                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2989                 if (ret) {
2990                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2991                                     hw->aq.asq_last_status);
2992                         goto fail_msix_alloc;
2993                 }
2994                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2995                 vsi->info.valid_sections = 0;
2996                 vsi->seid = ctxt.seid;
2997                 vsi->vsi_id = ctxt.vsi_number;
2998                 vsi->sib_vsi_list.vsi = vsi;
2999                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3000                                 &vsi->sib_vsi_list, list);
3001         }
3002
3003         /* MAC/VLAN configuration */
3004         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3005         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3006
3007         ret = i40e_vsi_add_mac(vsi, &filter);
3008         if (ret != I40E_SUCCESS) {
3009                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3010                 goto fail_msix_alloc;
3011         }
3012
3013         /* Get VSI BW information */
3014         i40e_vsi_dump_bw_config(vsi);
3015         return vsi;
3016 fail_msix_alloc:
3017         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3018 fail_queue_alloc:
3019         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3020 fail_mem:
3021         rte_free(vsi);
3022         return NULL;
3023 }
3024
3025 /* Configure vlan stripping on or off */
3026 int
3027 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3028 {
3029         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3030         struct i40e_vsi_context ctxt;
3031         uint8_t vlan_flags;
3032         int ret = I40E_SUCCESS;
3033
3034         /* Check if it has been already on or off */
3035         if (vsi->info.valid_sections &
3036                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3037                 if (on) {
3038                         if ((vsi->info.port_vlan_flags &
3039                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3040                                 return 0; /* already on */
3041                 } else {
3042                         if ((vsi->info.port_vlan_flags &
3043                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3044                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3045                                 return 0; /* already off */
3046                 }
3047         }
3048
3049         if (on)
3050                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3051         else
3052                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3053         vsi->info.valid_sections =
3054                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3055         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3056         vsi->info.port_vlan_flags |= vlan_flags;
3057         ctxt.seid = vsi->seid;
3058         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3059         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3060         if (ret)
3061                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3062                             on ? "enable" : "disable");
3063
3064         return ret;
3065 }
3066
3067 static int
3068 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3069 {
3070         struct rte_eth_dev_data *data = dev->data;
3071         int ret;
3072
3073         /* Apply vlan offload setting */
3074         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3075
3076         /* Apply double-vlan setting, not implemented yet */
3077
3078         /* Apply pvid setting */
3079         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3080                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3081         if (ret)
3082                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3083
3084         return ret;
3085 }
3086
3087 static int
3088 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3089 {
3090         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3091
3092         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3093 }
3094
3095 static int
3096 i40e_update_flow_control(struct i40e_hw *hw)
3097 {
3098 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3099         struct i40e_link_status link_status;
3100         uint32_t rxfc = 0, txfc = 0, reg;
3101         uint8_t an_info;
3102         int ret;
3103
3104         memset(&link_status, 0, sizeof(link_status));
3105         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3106         if (ret != I40E_SUCCESS) {
3107                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3108                 goto write_reg; /* Disable flow control */
3109         }
3110
3111         an_info = hw->phy.link_info.an_info;
3112         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3113                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3114                 ret = I40E_ERR_NOT_READY;
3115                 goto write_reg; /* Disable flow control */
3116         }
3117         /**
3118          * If link auto negotiation is enabled, flow control needs to
3119          * be configured according to it
3120          */
3121         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3122         case I40E_LINK_PAUSE_RXTX:
3123                 rxfc = 1;
3124                 txfc = 1;
3125                 hw->fc.current_mode = I40E_FC_FULL;
3126                 break;
3127         case I40E_AQ_LINK_PAUSE_RX:
3128                 rxfc = 1;
3129                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3130                 break;
3131         case I40E_AQ_LINK_PAUSE_TX:
3132                 txfc = 1;
3133                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3134                 break;
3135         default:
3136                 hw->fc.current_mode = I40E_FC_NONE;
3137                 break;
3138         }
3139
3140 write_reg:
3141         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3142                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3143         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3144         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3145         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3146         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3147
3148         return ret;
3149 }
3150
3151 /* PF setup */
3152 static int
3153 i40e_pf_setup(struct i40e_pf *pf)
3154 {
3155         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3156         struct i40e_filter_control_settings settings;
3157         struct i40e_vsi *vsi;
3158         int ret;
3159
3160         /* Clear all stats counters */
3161         pf->offset_loaded = FALSE;
3162         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3163         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3164
3165         ret = i40e_pf_get_switch_config(pf);
3166         if (ret != I40E_SUCCESS) {
3167                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3168                 return ret;
3169         }
3170
3171         /* VSI setup */
3172         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3173         if (!vsi) {
3174                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3175                 return I40E_ERR_NOT_READY;
3176         }
3177         pf->main_vsi = vsi;
3178
3179         /* Configure filter control */
3180         memset(&settings, 0, sizeof(settings));
3181         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3182         /* Enable ethtype and macvlan filters */
3183         settings.enable_ethtype = TRUE;
3184         settings.enable_macvlan = TRUE;
3185         ret = i40e_set_filter_control(hw, &settings);
3186         if (ret)
3187                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3188                                                                 ret);
3189
3190         /* Update flow control according to the auto negotiation */
3191         i40e_update_flow_control(hw);
3192
3193         return I40E_SUCCESS;
3194 }
3195
3196 int
3197 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3198 {
3199         uint32_t reg;
3200         uint16_t j;
3201
3202         /**
3203          * Set or clear TX Queue Disable flags,
3204          * which is required by hardware.
3205          */
3206         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3207         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3208
3209         /* Wait until the request is finished */
3210         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3211                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3212                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3213                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3214                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3215                                                         & 0x1))) {
3216                         break;
3217                 }
3218         }
3219         if (on) {
3220                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3221                         return I40E_SUCCESS; /* already on, skip next steps */
3222
3223                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3224                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3225         } else {
3226                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3227                         return I40E_SUCCESS; /* already off, skip next steps */
3228                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3229         }
3230         /* Write the register */
3231         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3232         /* Check the result */
3233         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3234                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3235                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3236                 if (on) {
3237                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3238                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3239                                 break;
3240                 } else {
3241                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3242                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3243                                 break;
3244                 }
3245         }
3246         /* Check if it is timeout */
3247         if (j >= I40E_CHK_Q_ENA_COUNT) {
3248                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3249                             (on ? "enable" : "disable"), q_idx);
3250                 return I40E_ERR_TIMEOUT;
3251         }
3252
3253         return I40E_SUCCESS;
3254 }
3255
3256 /* Swith on or off the tx queues */
3257 static int
3258 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3259 {
3260         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3261         struct i40e_tx_queue *txq;
3262         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3263         uint16_t i;
3264         int ret;
3265
3266         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3267                 txq = dev_data->tx_queues[i];
3268                 /* Don't operate the queue if not configured or
3269                  * if starting only per queue */
3270                 if (!txq->q_set || (on && txq->tx_deferred_start))
3271                         continue;
3272                 if (on)
3273                         ret = i40e_dev_tx_queue_start(dev, i);
3274                 else
3275                         ret = i40e_dev_tx_queue_stop(dev, i);
3276                 if ( ret != I40E_SUCCESS)
3277                         return ret;
3278         }
3279
3280         return I40E_SUCCESS;
3281 }
3282
3283 int
3284 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3285 {
3286         uint32_t reg;
3287         uint16_t j;
3288
3289         /* Wait until the request is finished */
3290         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3291                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3292                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3293                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3294                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3295                         break;
3296         }
3297
3298         if (on) {
3299                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3300                         return I40E_SUCCESS; /* Already on, skip next steps */
3301                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3302         } else {
3303                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3304                         return I40E_SUCCESS; /* Already off, skip next steps */
3305                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3306         }
3307
3308         /* Write the register */
3309         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3310         /* Check the result */
3311         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3312                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3313                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3314                 if (on) {
3315                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3316                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3317                                 break;
3318                 } else {
3319                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3320                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3321                                 break;
3322                 }
3323         }
3324
3325         /* Check if it is timeout */
3326         if (j >= I40E_CHK_Q_ENA_COUNT) {
3327                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3328                             (on ? "enable" : "disable"), q_idx);
3329                 return I40E_ERR_TIMEOUT;
3330         }
3331
3332         return I40E_SUCCESS;
3333 }
3334 /* Switch on or off the rx queues */
3335 static int
3336 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3337 {
3338         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3339         struct i40e_rx_queue *rxq;
3340         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3341         uint16_t i;
3342         int ret;
3343
3344         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3345                 rxq = dev_data->rx_queues[i];
3346                 /* Don't operate the queue if not configured or
3347                  * if starting only per queue */
3348                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3349                         continue;
3350                 if (on)
3351                         ret = i40e_dev_rx_queue_start(dev, i);
3352                 else
3353                         ret = i40e_dev_rx_queue_stop(dev, i);
3354                 if (ret != I40E_SUCCESS)
3355                         return ret;
3356         }
3357
3358         return I40E_SUCCESS;
3359 }
3360
3361 /* Switch on or off all the rx/tx queues */
3362 int
3363 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3364 {
3365         int ret;
3366
3367         if (on) {
3368                 /* enable rx queues before enabling tx queues */
3369                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3370                 if (ret) {
3371                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3372                         return ret;
3373                 }
3374                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3375         } else {
3376                 /* Stop tx queues before stopping rx queues */
3377                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3378                 if (ret) {
3379                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3380                         return ret;
3381                 }
3382                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3383         }
3384
3385         return ret;
3386 }
3387
3388 /* Initialize VSI for TX */
3389 static int
3390 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3391 {
3392         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3393         struct rte_eth_dev_data *data = pf->dev_data;
3394         uint16_t i;
3395         uint32_t ret = I40E_SUCCESS;
3396
3397         for (i = 0; i < data->nb_tx_queues; i++) {
3398                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3399                 if (ret != I40E_SUCCESS)
3400                         break;
3401         }
3402
3403         return ret;
3404 }
3405
3406 /* Initialize VSI for RX */
3407 static int
3408 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3409 {
3410         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3411         struct rte_eth_dev_data *data = pf->dev_data;
3412         int ret = I40E_SUCCESS;
3413         uint16_t i;
3414
3415         i40e_pf_config_mq_rx(pf);
3416         for (i = 0; i < data->nb_rx_queues; i++) {
3417                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3418                 if (ret != I40E_SUCCESS) {
3419                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3420                                     "initialization");
3421                         break;
3422                 }
3423         }
3424
3425         return ret;
3426 }
3427
3428 /* Initialize VSI */
3429 static int
3430 i40e_vsi_init(struct i40e_vsi *vsi)
3431 {
3432         int err;
3433
3434         err = i40e_vsi_tx_init(vsi);
3435         if (err) {
3436                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3437                 return err;
3438         }
3439         err = i40e_vsi_rx_init(vsi);
3440         if (err) {
3441                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3442                 return err;
3443         }
3444
3445         return err;
3446 }
3447
3448 static int
3449 i40e_vmdq_setup(struct rte_eth_dev *dev)
3450 {
3451         struct rte_eth_conf *conf = &dev->data->dev_conf;
3452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3453         int i, err, conf_vsis, j, loop;
3454         struct i40e_vsi *vsi;
3455         struct i40e_vmdq_info *vmdq_info;
3456         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3457         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3458
3459         /*
3460          * Disable interrupt to avoid message from VF. Furthermore, it will
3461          * avoid race condition in VSI creation/destroy.
3462          */
3463         i40e_pf_disable_irq0(hw);
3464
3465         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3466                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3467                 return -ENOTSUP;
3468         }
3469
3470         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3471         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3472                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3473                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3474                         pf->max_nb_vmdq_vsi);
3475                 return -ENOTSUP;
3476         }
3477
3478         if (pf->vmdq != NULL) {
3479                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3480                 return 0;
3481         }
3482
3483         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3484                                 sizeof(*vmdq_info) * conf_vsis, 0);
3485
3486         if (pf->vmdq == NULL) {
3487                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3488                 return -ENOMEM;
3489         }
3490
3491         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3492
3493         /* Create VMDQ VSI */
3494         for (i = 0; i < conf_vsis; i++) {
3495                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3496                                 vmdq_conf->enable_loop_back);
3497                 if (vsi == NULL) {
3498                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3499                         err = -1;
3500                         goto err_vsi_setup;
3501                 }
3502                 vmdq_info = &pf->vmdq[i];
3503                 vmdq_info->pf = pf;
3504                 vmdq_info->vsi = vsi;
3505         }
3506         pf->nb_cfg_vmdq_vsi = conf_vsis;
3507
3508         /* Configure Vlan */
3509         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3510         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3511                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3512                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3513                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3514                                         vmdq_conf->pool_map[i].vlan_id, j);
3515
3516                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3517                                                 vmdq_conf->pool_map[i].vlan_id);
3518                                 if (err) {
3519                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3520                                         err = -1;
3521                                         goto err_vsi_setup;
3522                                 }
3523                         }
3524                 }
3525         }
3526
3527         i40e_pf_enable_irq0(hw);
3528
3529         return 0;
3530
3531 err_vsi_setup:
3532         for (i = 0; i < conf_vsis; i++)
3533                 if (pf->vmdq[i].vsi == NULL)
3534                         break;
3535                 else
3536                         i40e_vsi_release(pf->vmdq[i].vsi);
3537
3538         rte_free(pf->vmdq);
3539         pf->vmdq = NULL;
3540         i40e_pf_enable_irq0(hw);
3541         return err;
3542 }
3543
3544 static void
3545 i40e_stat_update_32(struct i40e_hw *hw,
3546                    uint32_t reg,
3547                    bool offset_loaded,
3548                    uint64_t *offset,
3549                    uint64_t *stat)
3550 {
3551         uint64_t new_data;
3552
3553         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3554         if (!offset_loaded)
3555                 *offset = new_data;
3556
3557         if (new_data >= *offset)
3558                 *stat = (uint64_t)(new_data - *offset);
3559         else
3560                 *stat = (uint64_t)((new_data +
3561                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3562 }
3563
3564 static void
3565 i40e_stat_update_48(struct i40e_hw *hw,
3566                    uint32_t hireg,
3567                    uint32_t loreg,
3568                    bool offset_loaded,
3569                    uint64_t *offset,
3570                    uint64_t *stat)
3571 {
3572         uint64_t new_data;
3573
3574         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3575         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3576                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3577
3578         if (!offset_loaded)
3579                 *offset = new_data;
3580
3581         if (new_data >= *offset)
3582                 *stat = new_data - *offset;
3583         else
3584                 *stat = (uint64_t)((new_data +
3585                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3586
3587         *stat &= I40E_48_BIT_MASK;
3588 }
3589
3590 /* Disable IRQ0 */
3591 void
3592 i40e_pf_disable_irq0(struct i40e_hw *hw)
3593 {
3594         /* Disable all interrupt types */
3595         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3596         I40E_WRITE_FLUSH(hw);
3597 }
3598
3599 /* Enable IRQ0 */
3600 void
3601 i40e_pf_enable_irq0(struct i40e_hw *hw)
3602 {
3603         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3604                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3605                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3606                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3607         I40E_WRITE_FLUSH(hw);
3608 }
3609
3610 static void
3611 i40e_pf_config_irq0(struct i40e_hw *hw)
3612 {
3613         /* read pending request and disable first */
3614         i40e_pf_disable_irq0(hw);
3615         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3616         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3617                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3618
3619         /* Link no queues with irq0 */
3620         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3621                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3622 }
3623
3624 static void
3625 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3626 {
3627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3629         int i;
3630         uint16_t abs_vf_id;
3631         uint32_t index, offset, val;
3632
3633         if (!pf->vfs)
3634                 return;
3635         /**
3636          * Try to find which VF trigger a reset, use absolute VF id to access
3637          * since the reg is global register.
3638          */
3639         for (i = 0; i < pf->vf_num; i++) {
3640                 abs_vf_id = hw->func_caps.vf_base_id + i;
3641                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3642                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3643                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3644                 /* VFR event occured */
3645                 if (val & (0x1 << offset)) {
3646                         int ret;
3647
3648                         /* Clear the event first */
3649                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3650                                                         (0x1 << offset));
3651                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3652                         /**
3653                          * Only notify a VF reset event occured,
3654                          * don't trigger another SW reset
3655                          */
3656                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3657                         if (ret != I40E_SUCCESS)
3658                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3659                 }
3660         }
3661 }
3662
3663 static void
3664 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3665 {
3666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3667         struct i40e_arq_event_info info;
3668         uint16_t pending, opcode;
3669         int ret;
3670
3671         info.buf_len = I40E_AQ_BUF_SZ;
3672         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3673         if (!info.msg_buf) {
3674                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3675                 return;
3676         }
3677
3678         pending = 1;
3679         while (pending) {
3680                 ret = i40e_clean_arq_element(hw, &info, &pending);
3681
3682                 if (ret != I40E_SUCCESS) {
3683                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3684                                     "aq_err: %u", hw->aq.asq_last_status);
3685                         break;
3686                 }
3687                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3688
3689                 switch (opcode) {
3690                 case i40e_aqc_opc_send_msg_to_pf:
3691                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3692                         i40e_pf_host_handle_vf_msg(dev,
3693                                         rte_le_to_cpu_16(info.desc.retval),
3694                                         rte_le_to_cpu_32(info.desc.cookie_high),
3695                                         rte_le_to_cpu_32(info.desc.cookie_low),
3696                                         info.msg_buf,
3697                                         info.msg_len);
3698                         break;
3699                 default:
3700                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3701                                     opcode);
3702                         break;
3703                 }
3704         }
3705         rte_free(info.msg_buf);
3706 }
3707
3708 /*
3709  * Interrupt handler is registered as the alarm callback for handling LSC
3710  * interrupt in a definite of time, in order to wait the NIC into a stable
3711  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3712  * no need for link down interrupt.
3713  */
3714 static void
3715 i40e_dev_interrupt_delayed_handler(void *param)
3716 {
3717         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719         uint32_t icr0;
3720
3721         /* read interrupt causes again */
3722         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3723
3724 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3725         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3726                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3727         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3728                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3729         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3730                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3731         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3732                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3733         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3734                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3735                                                                 "state\n");
3736         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3737                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3738         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3739                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3740 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3741
3742         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3743                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3744                 i40e_dev_handle_vfr_event(dev);
3745         }
3746         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3747                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3748                 i40e_dev_handle_aq_msg(dev);
3749         }
3750
3751         /* handle the link up interrupt in an alarm callback */
3752         i40e_dev_link_update(dev, 0);
3753         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3754
3755         i40e_pf_enable_irq0(hw);
3756         rte_intr_enable(&(dev->pci_dev->intr_handle));
3757 }
3758
3759 /**
3760  * Interrupt handler triggered by NIC  for handling
3761  * specific interrupt.
3762  *
3763  * @param handle
3764  *  Pointer to interrupt handle.
3765  * @param param
3766  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3767  *
3768  * @return
3769  *  void
3770  */
3771 static void
3772 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3773                            void *param)
3774 {
3775         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3777         uint32_t icr0;
3778
3779         /* Disable interrupt */
3780         i40e_pf_disable_irq0(hw);
3781
3782         /* read out interrupt causes */
3783         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3784
3785         /* No interrupt event indicated */
3786         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3787                 PMD_DRV_LOG(INFO, "No interrupt event");
3788                 goto done;
3789         }
3790 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3791         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3792                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3793         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3794                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3795         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3796                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3797         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3798                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3799         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3800                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3801         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3802                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3803         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3804                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3805 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3806
3807         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3808                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3809                 i40e_dev_handle_vfr_event(dev);
3810         }
3811         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3812                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3813                 i40e_dev_handle_aq_msg(dev);
3814         }
3815
3816         /* Link Status Change interrupt */
3817         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3818 #define I40E_US_PER_SECOND 1000000
3819                 struct rte_eth_link link;
3820
3821                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3822                 memset(&link, 0, sizeof(link));
3823                 rte_i40e_dev_atomic_read_link_status(dev, &link);
3824                 i40e_dev_link_update(dev, 0);
3825
3826                 /*
3827                  * For link up interrupt, it needs to wait 1 second to let the
3828                  * hardware be a stable state. Otherwise several consecutive
3829                  * interrupts can be observed.
3830                  * For link down interrupt, no need to wait.
3831                  */
3832                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3833                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3834                         return;
3835                 else
3836                         _rte_eth_dev_callback_process(dev,
3837                                 RTE_ETH_EVENT_INTR_LSC);
3838         }
3839
3840 done:
3841         /* Enable interrupt */
3842         i40e_pf_enable_irq0(hw);
3843         rte_intr_enable(&(dev->pci_dev->intr_handle));
3844 }
3845
3846 static int
3847 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3848                          struct i40e_macvlan_filter *filter,
3849                          int total)
3850 {
3851         int ele_num, ele_buff_size;
3852         int num, actual_num, i;
3853         uint16_t flags;
3854         int ret = I40E_SUCCESS;
3855         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3856         struct i40e_aqc_add_macvlan_element_data *req_list;
3857
3858         if (filter == NULL  || total == 0)
3859                 return I40E_ERR_PARAM;
3860         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3861         ele_buff_size = hw->aq.asq_buf_size;
3862
3863         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3864         if (req_list == NULL) {
3865                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3866                 return I40E_ERR_NO_MEMORY;
3867         }
3868
3869         num = 0;
3870         do {
3871                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3872                 memset(req_list, 0, ele_buff_size);
3873
3874                 for (i = 0; i < actual_num; i++) {
3875                         (void)rte_memcpy(req_list[i].mac_addr,
3876                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3877                         req_list[i].vlan_tag =
3878                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3879
3880                         switch (filter[num + i].filter_type) {
3881                         case RTE_MAC_PERFECT_MATCH:
3882                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3883                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3884                                 break;
3885                         case RTE_MACVLAN_PERFECT_MATCH:
3886                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3887                                 break;
3888                         case RTE_MAC_HASH_MATCH:
3889                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3890                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3891                                 break;
3892                         case RTE_MACVLAN_HASH_MATCH:
3893                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
3894                                 break;
3895                         default:
3896                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
3897                                 ret = I40E_ERR_PARAM;
3898                                 goto DONE;
3899                         }
3900
3901                         req_list[i].queue_number = 0;
3902
3903                         req_list[i].flags = rte_cpu_to_le_16(flags);
3904                 }
3905
3906                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3907                                                 actual_num, NULL);
3908                 if (ret != I40E_SUCCESS) {
3909                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3910                         goto DONE;
3911                 }
3912                 num += actual_num;
3913         } while (num < total);
3914
3915 DONE:
3916         rte_free(req_list);
3917         return ret;
3918 }
3919
3920 static int
3921 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3922                             struct i40e_macvlan_filter *filter,
3923                             int total)
3924 {
3925         int ele_num, ele_buff_size;
3926         int num, actual_num, i;
3927         uint16_t flags;
3928         int ret = I40E_SUCCESS;
3929         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3930         struct i40e_aqc_remove_macvlan_element_data *req_list;
3931
3932         if (filter == NULL  || total == 0)
3933                 return I40E_ERR_PARAM;
3934
3935         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3936         ele_buff_size = hw->aq.asq_buf_size;
3937
3938         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3939         if (req_list == NULL) {
3940                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3941                 return I40E_ERR_NO_MEMORY;
3942         }
3943
3944         num = 0;
3945         do {
3946                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3947                 memset(req_list, 0, ele_buff_size);
3948
3949                 for (i = 0; i < actual_num; i++) {
3950                         (void)rte_memcpy(req_list[i].mac_addr,
3951                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3952                         req_list[i].vlan_tag =
3953                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3954
3955                         switch (filter[num + i].filter_type) {
3956                         case RTE_MAC_PERFECT_MATCH:
3957                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3958                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3959                                 break;
3960                         case RTE_MACVLAN_PERFECT_MATCH:
3961                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3962                                 break;
3963                         case RTE_MAC_HASH_MATCH:
3964                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
3965                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3966                                 break;
3967                         case RTE_MACVLAN_HASH_MATCH:
3968                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
3969                                 break;
3970                         default:
3971                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
3972                                 ret = I40E_ERR_PARAM;
3973                                 goto DONE;
3974                         }
3975                         req_list[i].flags = rte_cpu_to_le_16(flags);
3976                 }
3977
3978                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3979                                                 actual_num, NULL);
3980                 if (ret != I40E_SUCCESS) {
3981                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3982                         goto DONE;
3983                 }
3984                 num += actual_num;
3985         } while (num < total);
3986
3987 DONE:
3988         rte_free(req_list);
3989         return ret;
3990 }
3991
3992 /* Find out specific MAC filter */
3993 static struct i40e_mac_filter *
3994 i40e_find_mac_filter(struct i40e_vsi *vsi,
3995                          struct ether_addr *macaddr)
3996 {
3997         struct i40e_mac_filter *f;
3998
3999         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4000                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4001                         return f;
4002         }
4003
4004         return NULL;
4005 }
4006
4007 static bool
4008 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4009                          uint16_t vlan_id)
4010 {
4011         uint32_t vid_idx, vid_bit;
4012
4013         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4014         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4015
4016         if (vsi->vfta[vid_idx] & vid_bit)
4017                 return 1;
4018         else
4019                 return 0;
4020 }
4021
4022 static void
4023 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4024                          uint16_t vlan_id, bool on)
4025 {
4026         uint32_t vid_idx, vid_bit;
4027
4028 #define UINT32_BIT_MASK      0x1F
4029 #define VALID_VLAN_BIT_MASK  0xFFF
4030         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4031          *  element first, then find the bits it belongs to
4032          */
4033         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4034                   sizeof(uint32_t));
4035         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4036
4037         if (on)
4038                 vsi->vfta[vid_idx] |= vid_bit;
4039         else
4040                 vsi->vfta[vid_idx] &= ~vid_bit;
4041 }
4042
4043 /**
4044  * Find all vlan options for specific mac addr,
4045  * return with actual vlan found.
4046  */
4047 static inline int
4048 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4049                            struct i40e_macvlan_filter *mv_f,
4050                            int num, struct ether_addr *addr)
4051 {
4052         int i;
4053         uint32_t j, k;
4054
4055         /**
4056          * Not to use i40e_find_vlan_filter to decrease the loop time,
4057          * although the code looks complex.
4058           */
4059         if (num < vsi->vlan_num)
4060                 return I40E_ERR_PARAM;
4061
4062         i = 0;
4063         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4064                 if (vsi->vfta[j]) {
4065                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4066                                 if (vsi->vfta[j] & (1 << k)) {
4067                                         if (i > num - 1) {
4068                                                 PMD_DRV_LOG(ERR, "vlan number "
4069                                                             "not match");
4070                                                 return I40E_ERR_PARAM;
4071                                         }
4072                                         (void)rte_memcpy(&mv_f[i].macaddr,
4073                                                         addr, ETH_ADDR_LEN);
4074                                         mv_f[i].vlan_id =
4075                                                 j * I40E_UINT32_BIT_SIZE + k;
4076                                         i++;
4077                                 }
4078                         }
4079                 }
4080         }
4081         return I40E_SUCCESS;
4082 }
4083
4084 static inline int
4085 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4086                            struct i40e_macvlan_filter *mv_f,
4087                            int num,
4088                            uint16_t vlan)
4089 {
4090         int i = 0;
4091         struct i40e_mac_filter *f;
4092
4093         if (num < vsi->mac_num)
4094                 return I40E_ERR_PARAM;
4095
4096         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4097                 if (i > num - 1) {
4098                         PMD_DRV_LOG(ERR, "buffer number not match");
4099                         return I40E_ERR_PARAM;
4100                 }
4101                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4102                                 ETH_ADDR_LEN);
4103                 mv_f[i].vlan_id = vlan;
4104                 mv_f[i].filter_type = f->mac_info.filter_type;
4105                 i++;
4106         }
4107
4108         return I40E_SUCCESS;
4109 }
4110
4111 static int
4112 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4113 {
4114         int i, num;
4115         struct i40e_mac_filter *f;
4116         struct i40e_macvlan_filter *mv_f;
4117         int ret = I40E_SUCCESS;
4118
4119         if (vsi == NULL || vsi->mac_num == 0)
4120                 return I40E_ERR_PARAM;
4121
4122         /* Case that no vlan is set */
4123         if (vsi->vlan_num == 0)
4124                 num = vsi->mac_num;
4125         else
4126                 num = vsi->mac_num * vsi->vlan_num;
4127
4128         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4129         if (mv_f == NULL) {
4130                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4131                 return I40E_ERR_NO_MEMORY;
4132         }
4133
4134         i = 0;
4135         if (vsi->vlan_num == 0) {
4136                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4137                         (void)rte_memcpy(&mv_f[i].macaddr,
4138                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4139                         mv_f[i].vlan_id = 0;
4140                         i++;
4141                 }
4142         } else {
4143                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4144                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4145                                         vsi->vlan_num, &f->mac_info.mac_addr);
4146                         if (ret != I40E_SUCCESS)
4147                                 goto DONE;
4148                         i += vsi->vlan_num;
4149                 }
4150         }
4151
4152         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4153 DONE:
4154         rte_free(mv_f);
4155
4156         return ret;
4157 }
4158
4159 int
4160 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4161 {
4162         struct i40e_macvlan_filter *mv_f;
4163         int mac_num;
4164         int ret = I40E_SUCCESS;
4165
4166         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4167                 return I40E_ERR_PARAM;
4168
4169         /* If it's already set, just return */
4170         if (i40e_find_vlan_filter(vsi,vlan))
4171                 return I40E_SUCCESS;
4172
4173         mac_num = vsi->mac_num;
4174
4175         if (mac_num == 0) {
4176                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4177                 return I40E_ERR_PARAM;
4178         }
4179
4180         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4181
4182         if (mv_f == NULL) {
4183                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4184                 return I40E_ERR_NO_MEMORY;
4185         }
4186
4187         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4188
4189         if (ret != I40E_SUCCESS)
4190                 goto DONE;
4191
4192         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4193
4194         if (ret != I40E_SUCCESS)
4195                 goto DONE;
4196
4197         i40e_set_vlan_filter(vsi, vlan, 1);
4198
4199         vsi->vlan_num++;
4200         ret = I40E_SUCCESS;
4201 DONE:
4202         rte_free(mv_f);
4203         return ret;
4204 }
4205
4206 int
4207 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4208 {
4209         struct i40e_macvlan_filter *mv_f;
4210         int mac_num;
4211         int ret = I40E_SUCCESS;
4212
4213         /**
4214          * Vlan 0 is the generic filter for untagged packets
4215          * and can't be removed.
4216          */
4217         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4218                 return I40E_ERR_PARAM;
4219
4220         /* If can't find it, just return */
4221         if (!i40e_find_vlan_filter(vsi, vlan))
4222                 return I40E_ERR_PARAM;
4223
4224         mac_num = vsi->mac_num;
4225
4226         if (mac_num == 0) {
4227                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4228                 return I40E_ERR_PARAM;
4229         }
4230
4231         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4232
4233         if (mv_f == NULL) {
4234                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4235                 return I40E_ERR_NO_MEMORY;
4236         }
4237
4238         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4239
4240         if (ret != I40E_SUCCESS)
4241                 goto DONE;
4242
4243         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4244
4245         if (ret != I40E_SUCCESS)
4246                 goto DONE;
4247
4248         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4249         if (vsi->vlan_num == 1) {
4250                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4251                 if (ret != I40E_SUCCESS)
4252                         goto DONE;
4253
4254                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4255                 if (ret != I40E_SUCCESS)
4256                         goto DONE;
4257         }
4258
4259         i40e_set_vlan_filter(vsi, vlan, 0);
4260
4261         vsi->vlan_num--;
4262         ret = I40E_SUCCESS;
4263 DONE:
4264         rte_free(mv_f);
4265         return ret;
4266 }
4267
4268 int
4269 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4270 {
4271         struct i40e_mac_filter *f;
4272         struct i40e_macvlan_filter *mv_f;
4273         int i, vlan_num = 0;
4274         int ret = I40E_SUCCESS;
4275
4276         /* If it's add and we've config it, return */
4277         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4278         if (f != NULL)
4279                 return I40E_SUCCESS;
4280         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4281                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4282
4283                 /**
4284                  * If vlan_num is 0, that's the first time to add mac,
4285                  * set mask for vlan_id 0.
4286                  */
4287                 if (vsi->vlan_num == 0) {
4288                         i40e_set_vlan_filter(vsi, 0, 1);
4289                         vsi->vlan_num = 1;
4290                 }
4291                 vlan_num = vsi->vlan_num;
4292         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4293                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4294                 vlan_num = 1;
4295
4296         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4297         if (mv_f == NULL) {
4298                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4299                 return I40E_ERR_NO_MEMORY;
4300         }
4301
4302         for (i = 0; i < vlan_num; i++) {
4303                 mv_f[i].filter_type = mac_filter->filter_type;
4304                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4305                                 ETH_ADDR_LEN);
4306         }
4307
4308         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4309                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4310                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4311                                         &mac_filter->mac_addr);
4312                 if (ret != I40E_SUCCESS)
4313                         goto DONE;
4314         }
4315
4316         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4317         if (ret != I40E_SUCCESS)
4318                 goto DONE;
4319
4320         /* Add the mac addr into mac list */
4321         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4322         if (f == NULL) {
4323                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4324                 ret = I40E_ERR_NO_MEMORY;
4325                 goto DONE;
4326         }
4327         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4328                         ETH_ADDR_LEN);
4329         f->mac_info.filter_type = mac_filter->filter_type;
4330         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4331         vsi->mac_num++;
4332
4333         ret = I40E_SUCCESS;
4334 DONE:
4335         rte_free(mv_f);
4336
4337         return ret;
4338 }
4339
4340 int
4341 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4342 {
4343         struct i40e_mac_filter *f;
4344         struct i40e_macvlan_filter *mv_f;
4345         int i, vlan_num;
4346         enum rte_mac_filter_type filter_type;
4347         int ret = I40E_SUCCESS;
4348
4349         /* Can't find it, return an error */
4350         f = i40e_find_mac_filter(vsi, addr);
4351         if (f == NULL)
4352                 return I40E_ERR_PARAM;
4353
4354         vlan_num = vsi->vlan_num;
4355         filter_type = f->mac_info.filter_type;
4356         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4357                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4358                 if (vlan_num == 0) {
4359                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4360                         return I40E_ERR_PARAM;
4361                 }
4362         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4363                         filter_type == RTE_MAC_HASH_MATCH)
4364                 vlan_num = 1;
4365
4366         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4367         if (mv_f == NULL) {
4368                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4369                 return I40E_ERR_NO_MEMORY;
4370         }
4371
4372         for (i = 0; i < vlan_num; i++) {
4373                 mv_f[i].filter_type = filter_type;
4374                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4375                                 ETH_ADDR_LEN);
4376         }
4377         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4378                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4379                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4380                 if (ret != I40E_SUCCESS)
4381                         goto DONE;
4382         }
4383
4384         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4385         if (ret != I40E_SUCCESS)
4386                 goto DONE;
4387
4388         /* Remove the mac addr into mac list */
4389         TAILQ_REMOVE(&vsi->mac_list, f, next);
4390         rte_free(f);
4391         vsi->mac_num--;
4392
4393         ret = I40E_SUCCESS;
4394 DONE:
4395         rte_free(mv_f);
4396         return ret;
4397 }
4398
4399 /* Configure hash enable flags for RSS */
4400 uint64_t
4401 i40e_config_hena(uint64_t flags)
4402 {
4403         uint64_t hena = 0;
4404
4405         if (!flags)
4406                 return hena;
4407
4408         if (flags & ETH_RSS_NONF_IPV4_UDP)
4409                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4410         if (flags & ETH_RSS_NONF_IPV4_TCP)
4411                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4412         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4413                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4414         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4415                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4416         if (flags & ETH_RSS_FRAG_IPV4)
4417                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4418         if (flags & ETH_RSS_NONF_IPV6_UDP)
4419                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4420         if (flags & ETH_RSS_NONF_IPV6_TCP)
4421                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4422         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4423                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4424         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4425                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4426         if (flags & ETH_RSS_FRAG_IPV6)
4427                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4428         if (flags & ETH_RSS_L2_PAYLOAD)
4429                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4430
4431         return hena;
4432 }
4433
4434 /* Parse the hash enable flags */
4435 uint64_t
4436 i40e_parse_hena(uint64_t flags)
4437 {
4438         uint64_t rss_hf = 0;
4439
4440         if (!flags)
4441                 return rss_hf;
4442
4443         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4444                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4445         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4446                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4447         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4448                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4449         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4450                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4451         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4452                 rss_hf |= ETH_RSS_FRAG_IPV4;
4453         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4454                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4455         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4456                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4457         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4458                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4459         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4460                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4461         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4462                 rss_hf |= ETH_RSS_FRAG_IPV6;
4463         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4464                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4465
4466         return rss_hf;
4467 }
4468
4469 /* Disable RSS */
4470 static void
4471 i40e_pf_disable_rss(struct i40e_pf *pf)
4472 {
4473         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4474         uint64_t hena;
4475
4476         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4477         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4478         hena &= ~I40E_RSS_HENA_ALL;
4479         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4480         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4481         I40E_WRITE_FLUSH(hw);
4482 }
4483
4484 static int
4485 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4486 {
4487         uint32_t *hash_key;
4488         uint8_t hash_key_len;
4489         uint64_t rss_hf;
4490         uint16_t i;
4491         uint64_t hena;
4492
4493         hash_key = (uint32_t *)(rss_conf->rss_key);
4494         hash_key_len = rss_conf->rss_key_len;
4495         if (hash_key != NULL && hash_key_len >=
4496                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4497                 /* Fill in RSS hash key */
4498                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4499                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4500         }
4501
4502         rss_hf = rss_conf->rss_hf;
4503         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4504         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4505         hena &= ~I40E_RSS_HENA_ALL;
4506         hena |= i40e_config_hena(rss_hf);
4507         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4508         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4509         I40E_WRITE_FLUSH(hw);
4510
4511         return 0;
4512 }
4513
4514 static int
4515 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4516                          struct rte_eth_rss_conf *rss_conf)
4517 {
4518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4520         uint64_t hena;
4521
4522         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4523         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4524         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4525                 if (rss_hf != 0) /* Enable RSS */
4526                         return -EINVAL;
4527                 return 0; /* Nothing to do */
4528         }
4529         /* RSS enabled */
4530         if (rss_hf == 0) /* Disable RSS */
4531                 return -EINVAL;
4532
4533         return i40e_hw_rss_hash_set(hw, rss_conf);
4534 }
4535
4536 static int
4537 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4538                            struct rte_eth_rss_conf *rss_conf)
4539 {
4540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4542         uint64_t hena;
4543         uint16_t i;
4544
4545         if (hash_key != NULL) {
4546                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4547                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4548                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4549         }
4550         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4551         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4552         rss_conf->rss_hf = i40e_parse_hena(hena);
4553
4554         return 0;
4555 }
4556
4557 static int
4558 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4559 {
4560         switch (filter_type) {
4561         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4562                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4563                 break;
4564         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4565                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4566                 break;
4567         case RTE_TUNNEL_FILTER_IMAC_TENID:
4568                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4569                 break;
4570         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4571                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4572                 break;
4573         case ETH_TUNNEL_FILTER_IMAC:
4574                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4575                 break;
4576         default:
4577                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4578                 return -EINVAL;
4579         }
4580
4581         return 0;
4582 }
4583
4584 static int
4585 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4586                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4587                         uint8_t add)
4588 {
4589         uint16_t ip_type;
4590         uint8_t tun_type = 0;
4591         int val, ret = 0;
4592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4593         struct i40e_vsi *vsi = pf->main_vsi;
4594         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4595         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4596
4597         cld_filter = rte_zmalloc("tunnel_filter",
4598                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4599                 0);
4600
4601         if (NULL == cld_filter) {
4602                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4603                 return -EINVAL;
4604         }
4605         pfilter = cld_filter;
4606
4607         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4608                         sizeof(struct ether_addr));
4609         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4610                         sizeof(struct ether_addr));
4611
4612         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4613         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4614                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4615                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4616                                 &tunnel_filter->ip_addr,
4617                                 sizeof(pfilter->ipaddr.v4.data));
4618         } else {
4619                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4620                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4621                                 &tunnel_filter->ip_addr,
4622                                 sizeof(pfilter->ipaddr.v6.data));
4623         }
4624
4625         /* check tunneled type */
4626         switch (tunnel_filter->tunnel_type) {
4627         case RTE_TUNNEL_TYPE_VXLAN:
4628                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4629                 break;
4630         default:
4631                 /* Other tunnel types is not supported. */
4632                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4633                 rte_free(cld_filter);
4634                 return -EINVAL;
4635         }
4636
4637         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4638                                                 &pfilter->flags);
4639         if (val < 0) {
4640                 rte_free(cld_filter);
4641                 return -EINVAL;
4642         }
4643
4644         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4645                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4646         pfilter->tenant_id = tunnel_filter->tenant_id;
4647         pfilter->queue_number = tunnel_filter->queue_id;
4648
4649         if (add)
4650                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4651         else
4652                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4653                                                 cld_filter, 1);
4654
4655         rte_free(cld_filter);
4656         return ret;
4657 }
4658
4659 static int
4660 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4661 {
4662         uint8_t i;
4663
4664         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4665                 if (pf->vxlan_ports[i] == port)
4666                         return i;
4667         }
4668
4669         return -1;
4670 }
4671
4672 static int
4673 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4674 {
4675         int  idx, ret;
4676         uint8_t filter_idx;
4677         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4678
4679         idx = i40e_get_vxlan_port_idx(pf, port);
4680
4681         /* Check if port already exists */
4682         if (idx >= 0) {
4683                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4684                 return -EINVAL;
4685         }
4686
4687         /* Now check if there is space to add the new port */
4688         idx = i40e_get_vxlan_port_idx(pf, 0);
4689         if (idx < 0) {
4690                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4691                         "not adding port %d", port);
4692                 return -ENOSPC;
4693         }
4694
4695         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4696                                         &filter_idx, NULL);
4697         if (ret < 0) {
4698                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4699                 return -1;
4700         }
4701
4702         PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4703                          port,  filter_index);
4704
4705         /* New port: add it and mark its index in the bitmap */
4706         pf->vxlan_ports[idx] = port;
4707         pf->vxlan_bitmap |= (1 << idx);
4708
4709         if (!(pf->flags & I40E_FLAG_VXLAN))
4710                 pf->flags |= I40E_FLAG_VXLAN;
4711
4712         return 0;
4713 }
4714
4715 static int
4716 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4717 {
4718         int idx;
4719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4720
4721         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4722                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4723                 return -EINVAL;
4724         }
4725
4726         idx = i40e_get_vxlan_port_idx(pf, port);
4727
4728         if (idx < 0) {
4729                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4730                 return -EINVAL;
4731         }
4732
4733         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4734                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4735                 return -1;
4736         }
4737
4738         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4739                         port, idx);
4740
4741         pf->vxlan_ports[idx] = 0;
4742         pf->vxlan_bitmap &= ~(1 << idx);
4743
4744         if (!pf->vxlan_bitmap)
4745                 pf->flags &= ~I40E_FLAG_VXLAN;
4746
4747         return 0;
4748 }
4749
4750 /* Add UDP tunneling port */
4751 static int
4752 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4753                         struct rte_eth_udp_tunnel *udp_tunnel)
4754 {
4755         int ret = 0;
4756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4757
4758         if (udp_tunnel == NULL)
4759                 return -EINVAL;
4760
4761         switch (udp_tunnel->prot_type) {
4762         case RTE_TUNNEL_TYPE_VXLAN:
4763                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4764                 break;
4765
4766         case RTE_TUNNEL_TYPE_GENEVE:
4767         case RTE_TUNNEL_TYPE_TEREDO:
4768                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4769                 ret = -1;
4770                 break;
4771
4772         default:
4773                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4774                 ret = -1;
4775                 break;
4776         }
4777
4778         return ret;
4779 }
4780
4781 /* Remove UDP tunneling port */
4782 static int
4783 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4784                         struct rte_eth_udp_tunnel *udp_tunnel)
4785 {
4786         int ret = 0;
4787         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4788
4789         if (udp_tunnel == NULL)
4790                 return -EINVAL;
4791
4792         switch (udp_tunnel->prot_type) {
4793         case RTE_TUNNEL_TYPE_VXLAN:
4794                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4795                 break;
4796         case RTE_TUNNEL_TYPE_GENEVE:
4797         case RTE_TUNNEL_TYPE_TEREDO:
4798                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4799                 ret = -1;
4800                 break;
4801         default:
4802                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4803                 ret = -1;
4804                 break;
4805         }
4806
4807         return ret;
4808 }
4809
4810 /* Configure RSS */
4811 static int
4812 i40e_pf_config_rss(struct i40e_pf *pf)
4813 {
4814         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4815         struct rte_eth_rss_conf rss_conf;
4816         uint32_t i, lut = 0;
4817         uint16_t j, num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4818
4819         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4820                 if (j == num)
4821                         j = 0;
4822                 lut = (lut << 8) | (j & ((0x1 <<
4823                         hw->func_caps.rss_table_entry_width) - 1));
4824                 if ((i & 3) == 3)
4825                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4826         }
4827
4828         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4829         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4830                 i40e_pf_disable_rss(pf);
4831                 return 0;
4832         }
4833         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4834                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4835                 /* Calculate the default hash key */
4836                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4837                         rss_key_default[i] = (uint32_t)rte_rand();
4838                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4839                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4840                                                         sizeof(uint32_t);
4841         }
4842
4843         return i40e_hw_rss_hash_set(hw, &rss_conf);
4844 }
4845
4846 static int
4847 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4848                         struct rte_eth_tunnel_filter_conf *filter)
4849 {
4850         if (pf == NULL || filter == NULL) {
4851                 PMD_DRV_LOG(ERR, "Invalid parameter");
4852                 return -EINVAL;
4853         }
4854
4855         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4856                 PMD_DRV_LOG(ERR, "Invalid queue ID");
4857                 return -EINVAL;
4858         }
4859
4860         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4861                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4862                 return -EINVAL;
4863         }
4864
4865         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4866                 (is_zero_ether_addr(filter->outer_mac))) {
4867                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4868                 return -EINVAL;
4869         }
4870
4871         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4872                 (is_zero_ether_addr(filter->inner_mac))) {
4873                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4874                 return -EINVAL;
4875         }
4876
4877         return 0;
4878 }
4879
4880 static int
4881 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4882                         void *arg)
4883 {
4884         struct rte_eth_tunnel_filter_conf *filter;
4885         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4886         int ret = I40E_SUCCESS;
4887
4888         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4889
4890         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4891                 return I40E_ERR_PARAM;
4892
4893         switch (filter_op) {
4894         case RTE_ETH_FILTER_NOP:
4895                 if (!(pf->flags & I40E_FLAG_VXLAN))
4896                         ret = I40E_NOT_SUPPORTED;
4897         case RTE_ETH_FILTER_ADD:
4898                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4899                 break;
4900         case RTE_ETH_FILTER_DELETE:
4901                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4902                 break;
4903         default:
4904                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4905                 ret = I40E_ERR_PARAM;
4906                 break;
4907         }
4908
4909         return ret;
4910 }
4911
4912 static int
4913 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4914 {
4915         if (!pf->dev_data->sriov.active) {
4916                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4917                 case ETH_MQ_RX_RSS:
4918                         i40e_pf_config_rss(pf);
4919                         break;
4920                 default:
4921                         i40e_pf_disable_rss(pf);
4922                         break;
4923                 }
4924         }
4925
4926         return 0;
4927 }
4928
4929 static int
4930 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4931                      enum rte_filter_type filter_type,
4932                      enum rte_filter_op filter_op,
4933                      void *arg)
4934 {
4935         int ret = 0;
4936
4937         if (dev == NULL)
4938                 return -EINVAL;
4939
4940         switch (filter_type) {
4941         case RTE_ETH_FILTER_MACVLAN:
4942                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
4943                 break;
4944         case RTE_ETH_FILTER_TUNNEL:
4945                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
4946                 break;
4947         default:
4948                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4949                                                         filter_type);
4950                 ret = -EINVAL;
4951                 break;
4952         }
4953
4954         return ret;
4955 }