lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(\
 110                         __attribute__((unused)) struct eth_driver *eth_drv,
 111                         struct rte_eth_dev *eth_dev);
 112 static int i40e_dev_configure(struct rte_eth_dev *dev);
 113 static int i40e_dev_start(struct rte_eth_dev *dev);
 114 static void i40e_dev_stop(struct rte_eth_dev *dev);
 115 static void i40e_dev_close(struct rte_eth_dev *dev);
 116 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 118 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 119 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 120 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 121 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 122 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 123                                struct rte_eth_stats *stats);
 124 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 125 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 126                                             uint16_t queue_id,
 127                                             uint8_t stat_idx,
 128                                             uint8_t is_rx);
 129 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 130                               struct rte_eth_dev_info *dev_info);
 131 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 132                                 uint16_t vlan_id,
 133                                 int on);
 134 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 135 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 136 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 137                                       uint16_t queue,
 138                                       int on);
 139 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 140 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 141 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 142 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 143                               struct rte_eth_fc_conf *fc_conf);
 144 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                                        struct rte_eth_pfc_conf *pfc_conf);
 146 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 147                           struct ether_addr *mac_addr,
 148                           uint32_t index,
 149                           uint32_t pool);
 150 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 151 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 152                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 153                                     uint16_t reta_size);
 154 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 155                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 156                                    uint16_t reta_size);
 157
 158 static int i40e_get_cap(struct i40e_hw *hw);
 159 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 160 static int i40e_pf_setup(struct i40e_pf *pf);
 161 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 162 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 163 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 164                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 165 static void i40e_stat_update_48(struct i40e_hw *hw,
 166                                uint32_t hireg,
 167                                uint32_t loreg,
 168                                bool offset_loaded,
 169                                uint64_t *offset,
 170                                uint64_t *stat);
 171 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 172 static void i40e_dev_interrupt_handler(
 173                 __rte_unused struct rte_intr_handle *handle, void *param);
 174 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 175                                 uint32_t base, uint32_t num);
 176 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 177 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 178                         uint32_t base);
 179 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 180                         uint16_t num);
 181 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 182 static int i40e_veb_release(struct i40e_veb *veb);
 183 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 184                                                 struct i40e_vsi *vsi);
 185 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 186 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 187 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 188                                              struct i40e_macvlan_filter *mv_f,
 189                                              int num,
 190                                              struct ether_addr *addr);
 191 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 192                                              struct i40e_macvlan_filter *mv_f,
 193                                              int num,
 194                                              uint16_t vlan);
 195 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 196 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 197                                     struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 199                                       struct rte_eth_rss_conf *rss_conf);
 200 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 203                                 struct rte_eth_udp_tunnel *udp_tunnel);
 204 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 205                         struct rte_eth_ethertype_filter *filter,
 206                         bool add);
 207 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 211                                 enum rte_filter_type filter_type,
 212                                 enum rte_filter_op filter_op,
 213                                 void *arg);
 214 static void i40e_configure_registers(struct i40e_hw *hw);
 215 static void i40e_hw_init(struct i40e_hw *hw);
 216
 217 static struct rte_pci_id pci_id_i40e_map[] = {
 218 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 219 #include "rte_pci_dev_ids.h"
 220 { .vendor_id = 0, /* sentinel */ },
 221 };
 222
 223 static struct eth_dev_ops i40e_eth_dev_ops = {
 224         .dev_configure                = i40e_dev_configure,
 225         .dev_start                    = i40e_dev_start,
 226         .dev_stop                     = i40e_dev_stop,
 227         .dev_close                    = i40e_dev_close,
 228         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 229         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 230         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 231         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 232         .dev_set_link_up              = i40e_dev_set_link_up,
 233         .dev_set_link_down            = i40e_dev_set_link_down,
 234         .link_update                  = i40e_dev_link_update,
 235         .stats_get                    = i40e_dev_stats_get,
 236         .stats_reset                  = i40e_dev_stats_reset,
 237         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 238         .dev_infos_get                = i40e_dev_info_get,
 239         .vlan_filter_set              = i40e_vlan_filter_set,
 240         .vlan_tpid_set                = i40e_vlan_tpid_set,
 241         .vlan_offload_set             = i40e_vlan_offload_set,
 242         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 243         .vlan_pvid_set                = i40e_vlan_pvid_set,
 244         .rx_queue_start               = i40e_dev_rx_queue_start,
 245         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 246         .tx_queue_start               = i40e_dev_tx_queue_start,
 247         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 248         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 249         .rx_queue_release             = i40e_dev_rx_queue_release,
 250         .rx_queue_count               = i40e_dev_rx_queue_count,
 251         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 252         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 253         .tx_queue_release             = i40e_dev_tx_queue_release,
 254         .dev_led_on                   = i40e_dev_led_on,
 255         .dev_led_off                  = i40e_dev_led_off,
 256         .flow_ctrl_set                = i40e_flow_ctrl_set,
 257         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 258         .mac_addr_add                 = i40e_macaddr_add,
 259         .mac_addr_remove              = i40e_macaddr_remove,
 260         .reta_update                  = i40e_dev_rss_reta_update,
 261         .reta_query                   = i40e_dev_rss_reta_query,
 262         .rss_hash_update              = i40e_dev_rss_hash_update,
 263         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 264         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 265         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 266         .filter_ctrl                  = i40e_dev_filter_ctrl,
 267 };
 268
 269 static struct eth_driver rte_i40e_pmd = {
 270         {
 271                 .name = "rte_i40e_pmd",
 272                 .id_table = pci_id_i40e_map,
 273                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 274         },
 275         .eth_dev_init = eth_i40e_dev_init,
 276         .dev_private_size = sizeof(struct i40e_adapter),
 277 };
 278
 279 static inline int
 280 i40e_align_floor(int n)
 281 {
 282         if (n == 0)
 283                 return 0;
 284         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 285 }
 286
 287 static inline int
 288 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 289                                      struct rte_eth_link *link)
 290 {
 291         struct rte_eth_link *dst = link;
 292         struct rte_eth_link *src = &(dev->data->dev_link);
 293
 294         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 295                                         *(uint64_t *)src) == 0)
 296                 return -1;
 297
 298         return 0;
 299 }
 300
 301 static inline int
 302 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 303                                       struct rte_eth_link *link)
 304 {
 305         struct rte_eth_link *dst = &(dev->data->dev_link);
 306         struct rte_eth_link *src = link;
 307
 308         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 309                                         *(uint64_t *)src) == 0)
 310                 return -1;
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Driver initialization routine.
 317  * Invoked once at EAL init time.
 318  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 319  */
 320 static int
 321 rte_i40e_pmd_init(const char *name __rte_unused,
 322                   const char *params __rte_unused)
 323 {
 324         PMD_INIT_FUNC_TRACE();
 325         rte_eth_driver_register(&rte_i40e_pmd);
 326
 327         return 0;
 328 }
 329
 330 static struct rte_driver rte_i40e_driver = {
 331         .type = PMD_PDEV,
 332         .init = rte_i40e_pmd_init,
 333 };
 334
 335 PMD_REGISTER_DRIVER(rte_i40e_driver);
 336
 337 /*
 338  * Initialize registers for flexible payload, which should be set by NVM.
 339  * This should be removed from code once it is fixed in NVM.
 340  */
 341 #ifndef I40E_GLQF_ORT
 342 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 343 #endif
 344 #ifndef I40E_GLQF_PIT
 345 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 346 #endif
 347
 348 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 349 {
 350         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 351         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 352         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 353         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 354         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 359         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 360
 361         /* GLQF_PIT Registers */
 362         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 363         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 364 }
 365
 366 static int
 367 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 368                   struct rte_eth_dev *dev)
 369 {
 370         struct rte_pci_device *pci_dev;
 371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373         struct i40e_vsi *vsi;
 374         int ret;
 375         uint32_t len;
 376         uint8_t aq_fail = 0;
 377
 378         PMD_INIT_FUNC_TRACE();
 379
 380         dev->dev_ops = &i40e_eth_dev_ops;
 381         dev->rx_pkt_burst = i40e_recv_pkts;
 382         dev->tx_pkt_burst = i40e_xmit_pkts;
 383
 384         /* for secondary processes, we don't initialise any further as primary
 385          * has already done this work. Only check we don't need a different
 386          * RX function */
 387         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 388                 if (dev->data->scattered_rx)
 389                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 390                 return 0;
 391         }
 392         pci_dev = dev->pci_dev;
 393         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 394         pf->adapter->eth_dev = dev;
 395         pf->dev_data = dev->data;
 396
 397         hw->back = I40E_PF_TO_ADAPTER(pf);
 398         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 399         if (!hw->hw_addr) {
 400                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 401                              "as address is NULL");
 402                 return -ENODEV;
 403         }
 404
 405         hw->vendor_id = pci_dev->id.vendor_id;
 406         hw->device_id = pci_dev->id.device_id;
 407         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 408         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 409         hw->bus.device = pci_dev->addr.devid;
 410         hw->bus.func = pci_dev->addr.function;
 411
 412         /* Make sure all is clean before doing PF reset */
 413         i40e_clear_hw(hw);
 414
 415         /* Initialize the hardware */
 416         i40e_hw_init(hw);
 417
 418         /* Reset here to make sure all is clean for each PF */
 419         ret = i40e_pf_reset(hw);
 420         if (ret) {
 421                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 422                 return ret;
 423         }
 424
 425         /* Initialize the shared code (base driver) */
 426         ret = i40e_init_shared_code(hw);
 427         if (ret) {
 428                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 429                 return ret;
 430         }
 431
 432         /*
 433          * To work around the NVM issue,initialize registers
 434          * for flexible payload by software.
 435          * It should be removed once issues are fixed in NVM.
 436          */
 437         i40e_flex_payload_reg_init(hw);
 438
 439         /* Initialize the parameters for adminq */
 440         i40e_init_adminq_parameter(hw);
 441         ret = i40e_init_adminq(hw);
 442         if (ret != I40E_SUCCESS) {
 443                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 444                 return -EIO;
 445         }
 446         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 447                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 448                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 449                      ((hw->nvm.version >> 12) & 0xf),
 450                      ((hw->nvm.version >> 4) & 0xff),
 451                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 452
 453         /* Disable LLDP */
 454         ret = i40e_aq_stop_lldp(hw, true, NULL);
 455         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 456                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 457
 458         /* Clear PXE mode */
 459         i40e_clear_pxe_mode(hw);
 460
 461         /*
 462          * On X710, performance number is far from the expectation on recent
 463          * firmware versions. The fix for this issue may not be integrated in
 464          * the following firmware version. So the workaround in software driver
 465          * is needed. It needs to modify the initial values of 3 internal only
 466          * registers. Note that the workaround can be removed when it is fixed
 467          * in firmware in the future.
 468          */
 469         i40e_configure_registers(hw);
 470
 471         /* Get hw capabilities */
 472         ret = i40e_get_cap(hw);
 473         if (ret != I40E_SUCCESS) {
 474                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 475                 goto err_get_capabilities;
 476         }
 477
 478         /* Initialize parameters for PF */
 479         ret = i40e_pf_parameter_init(dev);
 480         if (ret != 0) {
 481                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 482                 goto err_parameter_init;
 483         }
 484
 485         /* Initialize the queue management */
 486         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 487         if (ret < 0) {
 488                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 489                 goto err_qp_pool_init;
 490         }
 491         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 492                                 hw->func_caps.num_msix_vectors - 1);
 493         if (ret < 0) {
 494                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 495                 goto err_msix_pool_init;
 496         }
 497
 498         /* Initialize lan hmc */
 499         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 500                                 hw->func_caps.num_rx_qp, 0, 0);
 501         if (ret != I40E_SUCCESS) {
 502                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 503                 goto err_init_lan_hmc;
 504         }
 505
 506         /* Configure lan hmc */
 507         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 508         if (ret != I40E_SUCCESS) {
 509                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 510                 goto err_configure_lan_hmc;
 511         }
 512
 513         /* Get and check the mac address */
 514         i40e_get_mac_addr(hw, hw->mac.addr);
 515         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 516                 PMD_INIT_LOG(ERR, "mac address is not valid");
 517                 ret = -EIO;
 518                 goto err_get_mac_addr;
 519         }
 520         /* Copy the permanent MAC address */
 521         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 522                         (struct ether_addr *) hw->mac.perm_addr);
 523
 524         /* Disable flow control */
 525         hw->fc.requested_mode = I40E_FC_NONE;
 526         i40e_set_fc(hw, &aq_fail, TRUE);
 527
 528         /* PF setup, which includes VSI setup */
 529         ret = i40e_pf_setup(pf);
 530         if (ret) {
 531                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 532                 goto err_setup_pf_switch;
 533         }
 534
 535         vsi = pf->main_vsi;
 536
 537         /* Disable double vlan by default */
 538         i40e_vsi_config_double_vlan(vsi, FALSE);
 539
 540         if (!vsi->max_macaddrs)
 541                 len = ETHER_ADDR_LEN;
 542         else
 543                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 544
 545         /* Should be after VSI initialized */
 546         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 547         if (!dev->data->mac_addrs) {
 548                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 549                                         "for storing mac address");
 550                 goto err_mac_alloc;
 551         }
 552         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 553                                         &dev->data->mac_addrs[0]);
 554
 555         /* initialize pf host driver to setup SRIOV resource if applicable */
 556         i40e_pf_host_init(dev);
 557
 558         /* register callback func to eal lib */
 559         rte_intr_callback_register(&(pci_dev->intr_handle),
 560                 i40e_dev_interrupt_handler, (void *)dev);
 561
 562         /* configure and enable device interrupt */
 563         i40e_pf_config_irq0(hw);
 564         i40e_pf_enable_irq0(hw);
 565
 566         /* enable uio intr after callback register */
 567         rte_intr_enable(&(pci_dev->intr_handle));
 568
 569         return 0;
 570
 571 err_mac_alloc:
 572         i40e_vsi_release(pf->main_vsi);
 573 err_setup_pf_switch:
 574 err_get_mac_addr:
 575 err_configure_lan_hmc:
 576         (void)i40e_shutdown_lan_hmc(hw);
 577 err_init_lan_hmc:
 578         i40e_res_pool_destroy(&pf->msix_pool);
 579 err_msix_pool_init:
 580         i40e_res_pool_destroy(&pf->qp_pool);
 581 err_qp_pool_init:
 582 err_parameter_init:
 583 err_get_capabilities:
 584         (void)i40e_shutdown_adminq(hw);
 585
 586         return ret;
 587 }
 588
 589 static int
 590 i40e_dev_configure(struct rte_eth_dev *dev)
 591 {
 592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 593         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 594         int ret;
 595
 596         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 597                 ret = i40e_fdir_setup(pf);
 598                 if (ret != I40E_SUCCESS) {
 599                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 600                         return -ENOTSUP;
 601                 }
 602                 ret = i40e_fdir_configure(dev);
 603                 if (ret < 0) {
 604                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 605                         goto err;
 606                 }
 607         } else
 608                 i40e_fdir_teardown(pf);
 609
 610         ret = i40e_dev_init_vlan(dev);
 611         if (ret < 0)
 612                 goto err;
 613
 614         /* VMDQ setup.
 615          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 616          *  RSS setting have different requirements.
 617          *  General PMD driver call sequence are NIC init, configure,
 618          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 619          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 620          *  applicable. So, VMDQ setting has to be done before
 621          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 622          *  For RSS setting, it will try to calculate actual configured RX queue
 623          *  number, which will be available after rx_queue_setup(). dev_start()
 624          *  function is good to place RSS setup.
 625          */
 626         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 627                 ret = i40e_vmdq_setup(dev);
 628                 if (ret)
 629                         goto err;
 630         }
 631         return 0;
 632 err:
 633         i40e_fdir_teardown(pf);
 634         return ret;
 635 }
 636
 637 void
 638 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 639 {
 640         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 641         uint16_t msix_vect = vsi->msix_intr;
 642         uint16_t i;
 643
 644         for (i = 0; i < vsi->nb_qps; i++) {
 645                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 646                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 647                 rte_wmb();
 648         }
 649
 650         if (vsi->type != I40E_VSI_SRIOV) {
 651                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 652                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 653                                 msix_vect - 1), 0);
 654         } else {
 655                 uint32_t reg;
 656                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 657                         vsi->user_param + (msix_vect - 1);
 658
 659                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 660         }
 661         I40E_WRITE_FLUSH(hw);
 662 }
 663
 664 static inline uint16_t
 665 i40e_calc_itr_interval(int16_t interval)
 666 {
 667         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 668                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 669
 670         /* Convert to hardware count, as writing each 1 represents 2 us */
 671         return (interval/2);
 672 }
 673
 674 void
 675 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 676 {
 677         uint32_t val;
 678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 679         uint16_t msix_vect = vsi->msix_intr;
 680         int i;
 681
 682         for (i = 0; i < vsi->nb_qps; i++)
 683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 684
 685         /* Bind all RX queues to allocated MSIX interrupt */
 686         for (i = 0; i < vsi->nb_qps; i++) {
 687                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 688                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 689                         ((vsi->base_queue + i + 1) <<
 690                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 691                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 692                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 693
 694                 if (i == vsi->nb_qps - 1)
 695                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 696                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 697         }
 698
 699         /* Write first RX queue to Link list register as the head element */
 700         if (vsi->type != I40E_VSI_SRIOV) {
 701                 uint16_t interval =
 702                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 703
 704                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 705                                                 (vsi->base_queue <<
 706                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 707                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 708
 709                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 710                                                 msix_vect - 1), interval);
 711
 712 #ifndef I40E_GLINT_CTL
 713 #define I40E_GLINT_CTL                     0x0003F800
 714 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 715 #endif
 716                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 717                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 718                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 719         } else {
 720                 uint32_t reg;
 721
 722                 /* num_msix_vectors_vf needs to minus irq0 */
 723                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 724                         vsi->user_param + (msix_vect - 1);
 725
 726                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 727                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 728                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 729         }
 730
 731         I40E_WRITE_FLUSH(hw);
 732 }
 733
 734 static void
 735 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 736 {
 737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 738         uint16_t interval = i40e_calc_itr_interval(\
 739                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 740
 741         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 742                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 743                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 744                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 745                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 746 }
 747
 748 static void
 749 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 750 {
 751         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 752
 753         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 754 }
 755
 756 static inline uint8_t
 757 i40e_parse_link_speed(uint16_t eth_link_speed)
 758 {
 759         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 760
 761         switch (eth_link_speed) {
 762         case ETH_LINK_SPEED_40G:
 763                 link_speed = I40E_LINK_SPEED_40GB;
 764                 break;
 765         case ETH_LINK_SPEED_20G:
 766                 link_speed = I40E_LINK_SPEED_20GB;
 767                 break;
 768         case ETH_LINK_SPEED_10G:
 769                 link_speed = I40E_LINK_SPEED_10GB;
 770                 break;
 771         case ETH_LINK_SPEED_1000:
 772                 link_speed = I40E_LINK_SPEED_1GB;
 773                 break;
 774         case ETH_LINK_SPEED_100:
 775                 link_speed = I40E_LINK_SPEED_100MB;
 776                 break;
 777         }
 778
 779         return link_speed;
 780 }
 781
 782 static int
 783 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 784 {
 785         enum i40e_status_code status;
 786         struct i40e_aq_get_phy_abilities_resp phy_ab;
 787         struct i40e_aq_set_phy_config phy_conf;
 788         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 789                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 790                         I40E_AQ_PHY_FLAG_LOW_POWER;
 791         const uint8_t advt = I40E_LINK_SPEED_40GB |
 792                         I40E_LINK_SPEED_10GB |
 793                         I40E_LINK_SPEED_1GB |
 794                         I40E_LINK_SPEED_100MB;
 795         int ret = -ENOTSUP;
 796
 797         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 798                                               NULL);
 799         if (status)
 800                 return ret;
 801
 802         memset(&phy_conf, 0, sizeof(phy_conf));
 803
 804         /* bits 0-2 use the values from get_phy_abilities_resp */
 805         abilities &= ~mask;
 806         abilities |= phy_ab.abilities & mask;
 807
 808         /* update ablities and speed */
 809         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 810                 phy_conf.link_speed = advt;
 811         else
 812                 phy_conf.link_speed = force_speed;
 813
 814         phy_conf.abilities = abilities;
 815
 816         /* use get_phy_abilities_resp value for the rest */
 817         phy_conf.phy_type = phy_ab.phy_type;
 818         phy_conf.eee_capability = phy_ab.eee_capability;
 819         phy_conf.eeer = phy_ab.eeer_val;
 820         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 821
 822         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 823                     phy_ab.abilities, phy_ab.link_speed);
 824         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 825                     phy_conf.abilities, phy_conf.link_speed);
 826
 827         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 828         if (status)
 829                 return ret;
 830
 831         return I40E_SUCCESS;
 832 }
 833
 834 static int
 835 i40e_apply_link_speed(struct rte_eth_dev *dev)
 836 {
 837         uint8_t speed;
 838         uint8_t abilities = 0;
 839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 840         struct rte_eth_conf *conf = &dev->data->dev_conf;
 841
 842         speed = i40e_parse_link_speed(conf->link_speed);
 843         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 844         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 845                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 846         else
 847                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 848
 849         return i40e_phy_conf_link(hw, abilities, speed);
 850 }
 851
 852 static int
 853 i40e_dev_start(struct rte_eth_dev *dev)
 854 {
 855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 857         struct i40e_vsi *main_vsi = pf->main_vsi;
 858         int ret, i;
 859
 860         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 861                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 862                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 863                              dev->data->dev_conf.link_duplex,
 864                              dev->data->port_id);
 865                 return -EINVAL;
 866         }
 867
 868         /* Initialize VSI */
 869         ret = i40e_dev_rxtx_init(pf);
 870         if (ret != I40E_SUCCESS) {
 871                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 872                 goto err_up;
 873         }
 874
 875         /* Map queues with MSIX interrupt */
 876         i40e_vsi_queues_bind_intr(main_vsi);
 877         i40e_vsi_enable_queues_intr(main_vsi);
 878
 879         /* Map VMDQ VSI queues with MSIX interrupt */
 880         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 881                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 882                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 883         }
 884
 885         /* enable FDIR MSIX interrupt */
 886         if (pf->fdir.fdir_vsi) {
 887                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 888                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 889         }
 890
 891         /* Enable all queues which have been configured */
 892         ret = i40e_dev_switch_queues(pf, TRUE);
 893         if (ret != I40E_SUCCESS) {
 894                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 895                 goto err_up;
 896         }
 897
 898         /* Enable receiving broadcast packets */
 899         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 900         if (ret != I40E_SUCCESS)
 901                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 902
 903         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 904                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 905                                                 true, NULL);
 906                 if (ret != I40E_SUCCESS)
 907                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 908         }
 909
 910         /* Apply link configure */
 911         ret = i40e_apply_link_speed(dev);
 912         if (I40E_SUCCESS != ret) {
 913                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 914                 goto err_up;
 915         }
 916
 917         return I40E_SUCCESS;
 918
 919 err_up:
 920         i40e_dev_switch_queues(pf, FALSE);
 921         i40e_dev_clear_queues(dev);
 922
 923         return ret;
 924 }
 925
 926 static void
 927 i40e_dev_stop(struct rte_eth_dev *dev)
 928 {
 929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 930         struct i40e_vsi *main_vsi = pf->main_vsi;
 931         int i;
 932
 933         /* Disable all queues */
 934         i40e_dev_switch_queues(pf, FALSE);
 935
 936         /* un-map queues with interrupt registers */
 937         i40e_vsi_disable_queues_intr(main_vsi);
 938         i40e_vsi_queues_unbind_intr(main_vsi);
 939
 940         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 941                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 942                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 943         }
 944
 945         if (pf->fdir.fdir_vsi) {
 946                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 947                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 948         }
 949         /* Clear all queues and release memory */
 950         i40e_dev_clear_queues(dev);
 951
 952         /* Set link down */
 953         i40e_dev_set_link_down(dev);
 954
 955 }
 956
 957 static void
 958 i40e_dev_close(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         uint32_t reg;
 963
 964         PMD_INIT_FUNC_TRACE();
 965
 966         i40e_dev_stop(dev);
 967
 968         /* Disable interrupt */
 969         i40e_pf_disable_irq0(hw);
 970         rte_intr_disable(&(dev->pci_dev->intr_handle));
 971
 972         /* shutdown and destroy the HMC */
 973         i40e_shutdown_lan_hmc(hw);
 974
 975         /* release all the existing VSIs and VEBs */
 976         i40e_fdir_teardown(pf);
 977         i40e_vsi_release(pf->main_vsi);
 978
 979         /* shutdown the adminq */
 980         i40e_aq_queue_shutdown(hw, true);
 981         i40e_shutdown_adminq(hw);
 982
 983         i40e_res_pool_destroy(&pf->qp_pool);
 984         i40e_res_pool_destroy(&pf->msix_pool);
 985
 986         /* force a PF reset to clean anything leftover */
 987         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 988         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 989                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 990         I40E_WRITE_FLUSH(hw);
 991 }
 992
 993 static void
 994 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998         struct i40e_vsi *vsi = pf->main_vsi;
 999         int status;
1000
1001         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1002                                                         true, NULL);
1003         if (status != I40E_SUCCESS)
1004                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1005
1006         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1007                                                         TRUE, NULL);
1008         if (status != I40E_SUCCESS)
1009                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1010
1011 }
1012
1013 static void
1014 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1015 {
1016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018         struct i40e_vsi *vsi = pf->main_vsi;
1019         int status;
1020
1021         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1022                                                         false, NULL);
1023         if (status != I40E_SUCCESS)
1024                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1025
1026         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1027                                                         false, NULL);
1028         if (status != I40E_SUCCESS)
1029                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1030 }
1031
1032 static void
1033 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1034 {
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *vsi = pf->main_vsi;
1038         int ret;
1039
1040         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1041         if (ret != I40E_SUCCESS)
1042                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1043 }
1044
1045 static void
1046 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050         struct i40e_vsi *vsi = pf->main_vsi;
1051         int ret;
1052
1053         if (dev->data->promiscuous == 1)
1054                 return; /* must remain in all_multicast mode */
1055
1056         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1057                                 vsi->seid, FALSE, NULL);
1058         if (ret != I40E_SUCCESS)
1059                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1060 }
1061
1062 /*
1063  * Set device link up.
1064  */
1065 static int
1066 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1067 {
1068         /* re-apply link speed setting */
1069         return i40e_apply_link_speed(dev);
1070 }
1071
1072 /*
1073  * Set device link down.
1074  */
1075 static int
1076 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1077 {
1078         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1079         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081
1082         return i40e_phy_conf_link(hw, abilities, speed);
1083 }
1084
1085 int
1086 i40e_dev_link_update(struct rte_eth_dev *dev,
1087                      __rte_unused int wait_to_complete)
1088 {
1089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         struct i40e_link_status link_status;
1091         struct rte_eth_link link, old;
1092         int status;
1093
1094         memset(&link, 0, sizeof(link));
1095         memset(&old, 0, sizeof(old));
1096         memset(&link_status, 0, sizeof(link_status));
1097         rte_i40e_dev_atomic_read_link_status(dev, &old);
1098
1099         /* Get link status information from hardware */
1100         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1101         if (status != I40E_SUCCESS) {
1102                 link.link_speed = ETH_LINK_SPEED_100;
1103                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1104                 PMD_DRV_LOG(ERR, "Failed to get link info");
1105                 goto out;
1106         }
1107
1108         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1109
1110         if (!link.link_status)
1111                 goto out;
1112
1113         /* i40e uses full duplex only */
1114         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1115
1116         /* Parse the link status */
1117         switch (link_status.link_speed) {
1118         case I40E_LINK_SPEED_100MB:
1119                 link.link_speed = ETH_LINK_SPEED_100;
1120                 break;
1121         case I40E_LINK_SPEED_1GB:
1122                 link.link_speed = ETH_LINK_SPEED_1000;
1123                 break;
1124         case I40E_LINK_SPEED_10GB:
1125                 link.link_speed = ETH_LINK_SPEED_10G;
1126                 break;
1127         case I40E_LINK_SPEED_20GB:
1128                 link.link_speed = ETH_LINK_SPEED_20G;
1129                 break;
1130         case I40E_LINK_SPEED_40GB:
1131                 link.link_speed = ETH_LINK_SPEED_40G;
1132                 break;
1133         default:
1134                 link.link_speed = ETH_LINK_SPEED_100;
1135                 break;
1136         }
1137
1138 out:
1139         rte_i40e_dev_atomic_write_link_status(dev, &link);
1140         if (link.link_status == old.link_status)
1141                 return -1;
1142
1143         return 0;
1144 }
1145
1146 /* Get all the statistics of a VSI */
1147 void
1148 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1149 {
1150         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1151         struct i40e_eth_stats *nes = &vsi->eth_stats;
1152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1153         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1154
1155         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1156                             vsi->offset_loaded, &oes->rx_bytes,
1157                             &nes->rx_bytes);
1158         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1159                             vsi->offset_loaded, &oes->rx_unicast,
1160                             &nes->rx_unicast);
1161         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1162                             vsi->offset_loaded, &oes->rx_multicast,
1163                             &nes->rx_multicast);
1164         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1165                             vsi->offset_loaded, &oes->rx_broadcast,
1166                             &nes->rx_broadcast);
1167         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1168                             &oes->rx_discards, &nes->rx_discards);
1169         /* GLV_REPC not supported */
1170         /* GLV_RMPC not supported */
1171         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1172                             &oes->rx_unknown_protocol,
1173                             &nes->rx_unknown_protocol);
1174         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1175                             vsi->offset_loaded, &oes->tx_bytes,
1176                             &nes->tx_bytes);
1177         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1178                             vsi->offset_loaded, &oes->tx_unicast,
1179                             &nes->tx_unicast);
1180         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1181                             vsi->offset_loaded, &oes->tx_multicast,
1182                             &nes->tx_multicast);
1183         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1184                             vsi->offset_loaded,  &oes->tx_broadcast,
1185                             &nes->tx_broadcast);
1186         /* GLV_TDPC not supported */
1187         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1188                             &oes->tx_errors, &nes->tx_errors);
1189         vsi->offset_loaded = true;
1190
1191         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1192                     vsi->vsi_id);
1193         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1194         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1195         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1196         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1197         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1198         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1199                     nes->rx_unknown_protocol);
1200         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1201         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1202         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1203         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1204         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1205         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1206         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1207                     vsi->vsi_id);
1208 }
1209
1210 /* Get all statistics of a port */
1211 static void
1212 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1213 {
1214         uint32_t i;
1215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1218         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1219
1220         /* Get statistics of struct i40e_eth_stats */
1221         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1222                             I40E_GLPRT_GORCL(hw->port),
1223                             pf->offset_loaded, &os->eth.rx_bytes,
1224                             &ns->eth.rx_bytes);
1225         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1226                             I40E_GLPRT_UPRCL(hw->port),
1227                             pf->offset_loaded, &os->eth.rx_unicast,
1228                             &ns->eth.rx_unicast);
1229         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1230                             I40E_GLPRT_MPRCL(hw->port),
1231                             pf->offset_loaded, &os->eth.rx_multicast,
1232                             &ns->eth.rx_multicast);
1233         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1234                             I40E_GLPRT_BPRCL(hw->port),
1235                             pf->offset_loaded, &os->eth.rx_broadcast,
1236                             &ns->eth.rx_broadcast);
1237         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1238                             pf->offset_loaded, &os->eth.rx_discards,
1239                             &ns->eth.rx_discards);
1240         /* GLPRT_REPC not supported */
1241         /* GLPRT_RMPC not supported */
1242         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1243                             pf->offset_loaded,
1244                             &os->eth.rx_unknown_protocol,
1245                             &ns->eth.rx_unknown_protocol);
1246         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1247                             I40E_GLPRT_GOTCL(hw->port),
1248                             pf->offset_loaded, &os->eth.tx_bytes,
1249                             &ns->eth.tx_bytes);
1250         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1251                             I40E_GLPRT_UPTCL(hw->port),
1252                             pf->offset_loaded, &os->eth.tx_unicast,
1253                             &ns->eth.tx_unicast);
1254         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1255                             I40E_GLPRT_MPTCL(hw->port),
1256                             pf->offset_loaded, &os->eth.tx_multicast,
1257                             &ns->eth.tx_multicast);
1258         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1259                             I40E_GLPRT_BPTCL(hw->port),
1260                             pf->offset_loaded, &os->eth.tx_broadcast,
1261                             &ns->eth.tx_broadcast);
1262         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1263                             pf->offset_loaded, &os->eth.tx_discards,
1264                             &ns->eth.tx_discards);
1265         /* GLPRT_TEPC not supported */
1266
1267         /* additional port specific stats */
1268         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1269                             pf->offset_loaded, &os->tx_dropped_link_down,
1270                             &ns->tx_dropped_link_down);
1271         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1272                             pf->offset_loaded, &os->crc_errors,
1273                             &ns->crc_errors);
1274         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1275                             pf->offset_loaded, &os->illegal_bytes,
1276                             &ns->illegal_bytes);
1277         /* GLPRT_ERRBC not supported */
1278         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1279                             pf->offset_loaded, &os->mac_local_faults,
1280                             &ns->mac_local_faults);
1281         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1282                             pf->offset_loaded, &os->mac_remote_faults,
1283                             &ns->mac_remote_faults);
1284         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1285                             pf->offset_loaded, &os->rx_length_errors,
1286                             &ns->rx_length_errors);
1287         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1288                             pf->offset_loaded, &os->link_xon_rx,
1289                             &ns->link_xon_rx);
1290         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1291                             pf->offset_loaded, &os->link_xoff_rx,
1292                             &ns->link_xoff_rx);
1293         for (i = 0; i < 8; i++) {
1294                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1295                                     pf->offset_loaded,
1296                                     &os->priority_xon_rx[i],
1297                                     &ns->priority_xon_rx[i]);
1298                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1299                                     pf->offset_loaded,
1300                                     &os->priority_xoff_rx[i],
1301                                     &ns->priority_xoff_rx[i]);
1302         }
1303         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1304                             pf->offset_loaded, &os->link_xon_tx,
1305                             &ns->link_xon_tx);
1306         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1307                             pf->offset_loaded, &os->link_xoff_tx,
1308                             &ns->link_xoff_tx);
1309         for (i = 0; i < 8; i++) {
1310                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1311                                     pf->offset_loaded,
1312                                     &os->priority_xon_tx[i],
1313                                     &ns->priority_xon_tx[i]);
1314                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1315                                     pf->offset_loaded,
1316                                     &os->priority_xoff_tx[i],
1317                                     &ns->priority_xoff_tx[i]);
1318                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1319                                     pf->offset_loaded,
1320                                     &os->priority_xon_2_xoff[i],
1321                                     &ns->priority_xon_2_xoff[i]);
1322         }
1323         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1324                             I40E_GLPRT_PRC64L(hw->port),
1325                             pf->offset_loaded, &os->rx_size_64,
1326                             &ns->rx_size_64);
1327         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1328                             I40E_GLPRT_PRC127L(hw->port),
1329                             pf->offset_loaded, &os->rx_size_127,
1330                             &ns->rx_size_127);
1331         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1332                             I40E_GLPRT_PRC255L(hw->port),
1333                             pf->offset_loaded, &os->rx_size_255,
1334                             &ns->rx_size_255);
1335         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1336                             I40E_GLPRT_PRC511L(hw->port),
1337                             pf->offset_loaded, &os->rx_size_511,
1338                             &ns->rx_size_511);
1339         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1340                             I40E_GLPRT_PRC1023L(hw->port),
1341                             pf->offset_loaded, &os->rx_size_1023,
1342                             &ns->rx_size_1023);
1343         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1344                             I40E_GLPRT_PRC1522L(hw->port),
1345                             pf->offset_loaded, &os->rx_size_1522,
1346                             &ns->rx_size_1522);
1347         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1348                             I40E_GLPRT_PRC9522L(hw->port),
1349                             pf->offset_loaded, &os->rx_size_big,
1350                             &ns->rx_size_big);
1351         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1352                             pf->offset_loaded, &os->rx_undersize,
1353                             &ns->rx_undersize);
1354         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1355                             pf->offset_loaded, &os->rx_fragments,
1356                             &ns->rx_fragments);
1357         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1358                             pf->offset_loaded, &os->rx_oversize,
1359                             &ns->rx_oversize);
1360         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1361                             pf->offset_loaded, &os->rx_jabber,
1362                             &ns->rx_jabber);
1363         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1364                             I40E_GLPRT_PTC64L(hw->port),
1365                             pf->offset_loaded, &os->tx_size_64,
1366                             &ns->tx_size_64);
1367         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1368                             I40E_GLPRT_PTC127L(hw->port),
1369                             pf->offset_loaded, &os->tx_size_127,
1370                             &ns->tx_size_127);
1371         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1372                             I40E_GLPRT_PTC255L(hw->port),
1373                             pf->offset_loaded, &os->tx_size_255,
1374                             &ns->tx_size_255);
1375         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1376                             I40E_GLPRT_PTC511L(hw->port),
1377                             pf->offset_loaded, &os->tx_size_511,
1378                             &ns->tx_size_511);
1379         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1380                             I40E_GLPRT_PTC1023L(hw->port),
1381                             pf->offset_loaded, &os->tx_size_1023,
1382                             &ns->tx_size_1023);
1383         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1384                             I40E_GLPRT_PTC1522L(hw->port),
1385                             pf->offset_loaded, &os->tx_size_1522,
1386                             &ns->tx_size_1522);
1387         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1388                             I40E_GLPRT_PTC9522L(hw->port),
1389                             pf->offset_loaded, &os->tx_size_big,
1390                             &ns->tx_size_big);
1391         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1392                            pf->offset_loaded,
1393                            &os->fd_sb_match, &ns->fd_sb_match);
1394         /* GLPRT_MSPDC not supported */
1395         /* GLPRT_XEC not supported */
1396
1397         pf->offset_loaded = true;
1398
1399         if (pf->main_vsi)
1400                 i40e_update_vsi_stats(pf->main_vsi);
1401
1402         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1403                                                 ns->eth.rx_broadcast;
1404         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1405                                                 ns->eth.tx_broadcast;
1406         stats->ibytes   = ns->eth.rx_bytes;
1407         stats->obytes   = ns->eth.tx_bytes;
1408         stats->oerrors  = ns->eth.tx_errors;
1409         stats->imcasts  = ns->eth.rx_multicast;
1410         stats->fdirmatch = ns->fd_sb_match;
1411
1412         /* Rx Errors */
1413         stats->ibadcrc  = ns->crc_errors;
1414         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1415                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1416         stats->imissed  = ns->eth.rx_discards;
1417         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1418
1419         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1420         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1421         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1422         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1423         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1424         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1425         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1426                     ns->eth.rx_unknown_protocol);
1427         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1428         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1429         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1430         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1431         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1432         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1433
1434         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1435                     ns->tx_dropped_link_down);
1436         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1437         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1438                     ns->illegal_bytes);
1439         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1440         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1441                     ns->mac_local_faults);
1442         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1443                     ns->mac_remote_faults);
1444         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1445                     ns->rx_length_errors);
1446         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1447         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1448         for (i = 0; i < 8; i++) {
1449                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1450                                 i, ns->priority_xon_rx[i]);
1451                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1452                                 i, ns->priority_xoff_rx[i]);
1453         }
1454         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1455         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1456         for (i = 0; i < 8; i++) {
1457                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1458                                 i, ns->priority_xon_tx[i]);
1459                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1460                                 i, ns->priority_xoff_tx[i]);
1461                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1462                                 i, ns->priority_xon_2_xoff[i]);
1463         }
1464         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1465         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1466         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1467         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1468         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1469         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1470         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1471         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1472         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1473         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1474         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1475         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1476         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1477         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1478         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1479         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1480         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1481         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1482         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1483                         ns->mac_short_packet_dropped);
1484         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1485                     ns->checksum_error);
1486         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1487         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1488 }
1489
1490 /* Reset the statistics */
1491 static void
1492 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1493 {
1494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495
1496         /* It results in reloading the start point of each counter */
1497         pf->offset_loaded = false;
1498 }
1499
1500 static int
1501 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1502                                  __rte_unused uint16_t queue_id,
1503                                  __rte_unused uint8_t stat_idx,
1504                                  __rte_unused uint8_t is_rx)
1505 {
1506         PMD_INIT_FUNC_TRACE();
1507
1508         return -ENOSYS;
1509 }
1510
1511 static void
1512 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1513 {
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_vsi *vsi = pf->main_vsi;
1516
1517         dev_info->max_rx_queues = vsi->nb_qps;
1518         dev_info->max_tx_queues = vsi->nb_qps;
1519         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1520         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1521         dev_info->max_mac_addrs = vsi->max_macaddrs;
1522         dev_info->max_vfs = dev->pci_dev->max_vfs;
1523         dev_info->rx_offload_capa =
1524                 DEV_RX_OFFLOAD_VLAN_STRIP |
1525                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1526                 DEV_RX_OFFLOAD_UDP_CKSUM |
1527                 DEV_RX_OFFLOAD_TCP_CKSUM;
1528         dev_info->tx_offload_capa =
1529                 DEV_TX_OFFLOAD_VLAN_INSERT |
1530                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1531                 DEV_TX_OFFLOAD_UDP_CKSUM |
1532                 DEV_TX_OFFLOAD_TCP_CKSUM |
1533                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1534                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1535                 DEV_TX_OFFLOAD_TCP_TSO;
1536         dev_info->reta_size = pf->hash_lut_size;
1537         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1538
1539         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1540                 .rx_thresh = {
1541                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1542                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1543                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1544                 },
1545                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1546                 .rx_drop_en = 0,
1547         };
1548
1549         dev_info->default_txconf = (struct rte_eth_txconf) {
1550                 .tx_thresh = {
1551                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1552                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1553                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1554                 },
1555                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1556                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1557                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1558                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1559         };
1560
1561         if (pf->flags | I40E_FLAG_VMDQ) {
1562                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1563                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1564                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1565                                                 pf->max_nb_vmdq_vsi;
1566                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1567                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1568                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1569         }
1570 }
1571
1572 static int
1573 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1574 {
1575         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1576         struct i40e_vsi *vsi = pf->main_vsi;
1577         PMD_INIT_FUNC_TRACE();
1578
1579         if (on)
1580                 return i40e_vsi_add_vlan(vsi, vlan_id);
1581         else
1582                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1583 }
1584
1585 static void
1586 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1587                    __rte_unused uint16_t tpid)
1588 {
1589         PMD_INIT_FUNC_TRACE();
1590 }
1591
1592 static void
1593 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1594 {
1595         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1596         struct i40e_vsi *vsi = pf->main_vsi;
1597
1598         if (mask & ETH_VLAN_STRIP_MASK) {
1599                 /* Enable or disable VLAN stripping */
1600                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1601                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1602                 else
1603                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1604         }
1605
1606         if (mask & ETH_VLAN_EXTEND_MASK) {
1607                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1608                         i40e_vsi_config_double_vlan(vsi, TRUE);
1609                 else
1610                         i40e_vsi_config_double_vlan(vsi, FALSE);
1611         }
1612 }
1613
1614 static void
1615 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1616                           __rte_unused uint16_t queue,
1617                           __rte_unused int on)
1618 {
1619         PMD_INIT_FUNC_TRACE();
1620 }
1621
1622 static int
1623 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1624 {
1625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1626         struct i40e_vsi *vsi = pf->main_vsi;
1627         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1628         struct i40e_vsi_vlan_pvid_info info;
1629
1630         memset(&info, 0, sizeof(info));
1631         info.on = on;
1632         if (info.on)
1633                 info.config.pvid = pvid;
1634         else {
1635                 info.config.reject.tagged =
1636                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1637                 info.config.reject.untagged =
1638                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1639         }
1640
1641         return i40e_vsi_vlan_pvid_set(vsi, &info);
1642 }
1643
1644 static int
1645 i40e_dev_led_on(struct rte_eth_dev *dev)
1646 {
1647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         uint32_t mode = i40e_led_get(hw);
1649
1650         if (mode == 0)
1651                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1652
1653         return 0;
1654 }
1655
1656 static int
1657 i40e_dev_led_off(struct rte_eth_dev *dev)
1658 {
1659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         uint32_t mode = i40e_led_get(hw);
1661
1662         if (mode != 0)
1663                 i40e_led_set(hw, 0, false);
1664
1665         return 0;
1666 }
1667
1668 static int
1669 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1670                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1671 {
1672         PMD_INIT_FUNC_TRACE();
1673
1674         return -ENOSYS;
1675 }
1676
1677 static int
1678 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1679                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1680 {
1681         PMD_INIT_FUNC_TRACE();
1682
1683         return -ENOSYS;
1684 }
1685
1686 /* Add a MAC address, and update filters */
1687 static void
1688 i40e_macaddr_add(struct rte_eth_dev *dev,
1689                  struct ether_addr *mac_addr,
1690                  __rte_unused uint32_t index,
1691                  uint32_t pool)
1692 {
1693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1694         struct i40e_mac_filter_info mac_filter;
1695         struct i40e_vsi *vsi;
1696         int ret;
1697
1698         /* If VMDQ not enabled or configured, return */
1699         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1700                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1701                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1702                         pool);
1703                 return;
1704         }
1705
1706         if (pool > pf->nb_cfg_vmdq_vsi) {
1707                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1708                                 pool, pf->nb_cfg_vmdq_vsi);
1709                 return;
1710         }
1711
1712         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1713         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1714
1715         if (pool == 0)
1716                 vsi = pf->main_vsi;
1717         else
1718                 vsi = pf->vmdq[pool - 1].vsi;
1719
1720         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1721         if (ret != I40E_SUCCESS) {
1722                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1723                 return;
1724         }
1725 }
1726
1727 /* Remove a MAC address, and update filters */
1728 static void
1729 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1730 {
1731         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1732         struct i40e_vsi *vsi;
1733         struct rte_eth_dev_data *data = dev->data;
1734         struct ether_addr *macaddr;
1735         int ret;
1736         uint32_t i;
1737         uint64_t pool_sel;
1738
1739         macaddr = &(data->mac_addrs[index]);
1740
1741         pool_sel = dev->data->mac_pool_sel[index];
1742
1743         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1744                 if (pool_sel & (1ULL << i)) {
1745                         if (i == 0)
1746                                 vsi = pf->main_vsi;
1747                         else {
1748                                 /* No VMDQ pool enabled or configured */
1749                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1750                                         (i > pf->nb_cfg_vmdq_vsi)) {
1751                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1752                                                         "/configured");
1753                                         return;
1754                                 }
1755                                 vsi = pf->vmdq[i - 1].vsi;
1756                         }
1757                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1758
1759                         if (ret) {
1760                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1761                                 return;
1762                         }
1763                 }
1764         }
1765 }
1766
1767 /* Set perfect match or hash match of MAC and VLAN for a VF */
1768 static int
1769 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1770                  struct rte_eth_mac_filter *filter,
1771                  bool add)
1772 {
1773         struct i40e_hw *hw;
1774         struct i40e_mac_filter_info mac_filter;
1775         struct ether_addr old_mac;
1776         struct ether_addr *new_mac;
1777         struct i40e_pf_vf *vf = NULL;
1778         uint16_t vf_id;
1779         int ret;
1780
1781         if (pf == NULL) {
1782                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1783                 return -EINVAL;
1784         }
1785         hw = I40E_PF_TO_HW(pf);
1786
1787         if (filter == NULL) {
1788                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1789                 return -EINVAL;
1790         }
1791
1792         new_mac = &filter->mac_addr;
1793
1794         if (is_zero_ether_addr(new_mac)) {
1795                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1796                 return -EINVAL;
1797         }
1798
1799         vf_id = filter->dst_id;
1800
1801         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1802                 PMD_DRV_LOG(ERR, "Invalid argument.");
1803                 return -EINVAL;
1804         }
1805         vf = &pf->vfs[vf_id];
1806
1807         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1808                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1809                 return -EINVAL;
1810         }
1811
1812         if (add) {
1813                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1814                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1815                                 ETHER_ADDR_LEN);
1816                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1817                                  ETHER_ADDR_LEN);
1818
1819                 mac_filter.filter_type = filter->filter_type;
1820                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1821                 if (ret != I40E_SUCCESS) {
1822                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1823                         return -1;
1824                 }
1825                 ether_addr_copy(new_mac, &pf->dev_addr);
1826         } else {
1827                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1828                                 ETHER_ADDR_LEN);
1829                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1830                 if (ret != I40E_SUCCESS) {
1831                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1832                         return -1;
1833                 }
1834
1835                 /* Clear device address as it has been removed */
1836                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1837                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1838         }
1839
1840         return 0;
1841 }
1842
1843 /* MAC filter handle */
1844 static int
1845 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1846                 void *arg)
1847 {
1848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1849         struct rte_eth_mac_filter *filter;
1850         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1851         int ret = I40E_NOT_SUPPORTED;
1852
1853         filter = (struct rte_eth_mac_filter *)(arg);
1854
1855         switch (filter_op) {
1856         case RTE_ETH_FILTER_NOP:
1857                 ret = I40E_SUCCESS;
1858                 break;
1859         case RTE_ETH_FILTER_ADD:
1860                 i40e_pf_disable_irq0(hw);
1861                 if (filter->is_vf)
1862                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1863                 i40e_pf_enable_irq0(hw);
1864                 break;
1865         case RTE_ETH_FILTER_DELETE:
1866                 i40e_pf_disable_irq0(hw);
1867                 if (filter->is_vf)
1868                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1869                 i40e_pf_enable_irq0(hw);
1870                 break;
1871         default:
1872                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1873                 ret = I40E_ERR_PARAM;
1874                 break;
1875         }
1876
1877         return ret;
1878 }
1879
1880 static int
1881 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1882                          struct rte_eth_rss_reta_entry64 *reta_conf,
1883                          uint16_t reta_size)
1884 {
1885         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1887         uint32_t lut, l;
1888         uint16_t i, j, lut_size = pf->hash_lut_size;
1889         uint16_t idx, shift;
1890         uint8_t mask;
1891
1892         if (reta_size != lut_size ||
1893                 reta_size > ETH_RSS_RETA_SIZE_512) {
1894                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1895                         "(%d) doesn't match the number hardware can supported "
1896                                         "(%d)\n", reta_size, lut_size);
1897                 return -EINVAL;
1898         }
1899
1900         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1901                 idx = i / RTE_RETA_GROUP_SIZE;
1902                 shift = i % RTE_RETA_GROUP_SIZE;
1903                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1904                                                 I40E_4_BIT_MASK);
1905                 if (!mask)
1906                         continue;
1907                 if (mask == I40E_4_BIT_MASK)
1908                         l = 0;
1909                 else
1910                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1911                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1912                         if (mask & (0x1 << j))
1913                                 lut |= reta_conf[idx].reta[shift + j] <<
1914                                                         (CHAR_BIT * j);
1915                         else
1916                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1917                 }
1918                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1919         }
1920
1921         return 0;
1922 }
1923
1924 static int
1925 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1926                         struct rte_eth_rss_reta_entry64 *reta_conf,
1927                         uint16_t reta_size)
1928 {
1929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931         uint32_t lut;
1932         uint16_t i, j, lut_size = pf->hash_lut_size;
1933         uint16_t idx, shift;
1934         uint8_t mask;
1935
1936         if (reta_size != lut_size ||
1937                 reta_size > ETH_RSS_RETA_SIZE_512) {
1938                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1939                         "(%d) doesn't match the number hardware can supported "
1940                                         "(%d)\n", reta_size, lut_size);
1941                 return -EINVAL;
1942         }
1943
1944         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1945                 idx = i / RTE_RETA_GROUP_SIZE;
1946                 shift = i % RTE_RETA_GROUP_SIZE;
1947                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1948                                                 I40E_4_BIT_MASK);
1949                 if (!mask)
1950                         continue;
1951
1952                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1953                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1954                         if (mask & (0x1 << j))
1955                                 reta_conf[idx].reta[shift + j] = ((lut >>
1956                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1957                 }
1958         }
1959
1960         return 0;
1961 }
1962
1963 /**
1964  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1965  * @hw:   pointer to the HW structure
1966  * @mem:  pointer to mem struct to fill out
1967  * @size: size of memory requested
1968  * @alignment: what to align the allocation to
1969  **/
1970 enum i40e_status_code
1971 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1972                         struct i40e_dma_mem *mem,
1973                         u64 size,
1974                         u32 alignment)
1975 {
1976         static uint64_t id = 0;
1977         const struct rte_memzone *mz = NULL;
1978         char z_name[RTE_MEMZONE_NAMESIZE];
1979
1980         if (!mem)
1981                 return I40E_ERR_PARAM;
1982
1983         id++;
1984         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1985 #ifdef RTE_LIBRTE_XEN_DOM0
1986         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1987                                                         RTE_PGSIZE_2M);
1988 #else
1989         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1990 #endif
1991         if (!mz)
1992                 return I40E_ERR_NO_MEMORY;
1993
1994         mem->id = id;
1995         mem->size = size;
1996         mem->va = mz->addr;
1997 #ifdef RTE_LIBRTE_XEN_DOM0
1998         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1999 #else
2000         mem->pa = mz->phys_addr;
2001 #endif
2002
2003         return I40E_SUCCESS;
2004 }
2005
2006 /**
2007  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2008  * @hw:   pointer to the HW structure
2009  * @mem:  ptr to mem struct to free
2010  **/
2011 enum i40e_status_code
2012 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2013                     struct i40e_dma_mem *mem)
2014 {
2015         if (!mem || !mem->va)
2016                 return I40E_ERR_PARAM;
2017
2018         mem->va = NULL;
2019         mem->pa = (u64)0;
2020
2021         return I40E_SUCCESS;
2022 }
2023
2024 /**
2025  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2026  * @hw:   pointer to the HW structure
2027  * @mem:  pointer to mem struct to fill out
2028  * @size: size of memory requested
2029  **/
2030 enum i40e_status_code
2031 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2032                          struct i40e_virt_mem *mem,
2033                          u32 size)
2034 {
2035         if (!mem)
2036                 return I40E_ERR_PARAM;
2037
2038         mem->size = size;
2039         mem->va = rte_zmalloc("i40e", size, 0);
2040
2041         if (mem->va)
2042                 return I40E_SUCCESS;
2043         else
2044                 return I40E_ERR_NO_MEMORY;
2045 }
2046
2047 /**
2048  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2049  * @hw:   pointer to the HW structure
2050  * @mem:  pointer to mem struct to free
2051  **/
2052 enum i40e_status_code
2053 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2054                      struct i40e_virt_mem *mem)
2055 {
2056         if (!mem)
2057                 return I40E_ERR_PARAM;
2058
2059         rte_free(mem->va);
2060         mem->va = NULL;
2061
2062         return I40E_SUCCESS;
2063 }
2064
2065 void
2066 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2067 {
2068         rte_spinlock_init(&sp->spinlock);
2069 }
2070
2071 void
2072 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2073 {
2074         rte_spinlock_lock(&sp->spinlock);
2075 }
2076
2077 void
2078 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2079 {
2080         rte_spinlock_unlock(&sp->spinlock);
2081 }
2082
2083 void
2084 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2085 {
2086         return;
2087 }
2088
2089 /**
2090  * Get the hardware capabilities, which will be parsed
2091  * and saved into struct i40e_hw.
2092  */
2093 static int
2094 i40e_get_cap(struct i40e_hw *hw)
2095 {
2096         struct i40e_aqc_list_capabilities_element_resp *buf;
2097         uint16_t len, size = 0;
2098         int ret;
2099
2100         /* Calculate a huge enough buff for saving response data temporarily */
2101         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2102                                                 I40E_MAX_CAP_ELE_NUM;
2103         buf = rte_zmalloc("i40e", len, 0);
2104         if (!buf) {
2105                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2106                 return I40E_ERR_NO_MEMORY;
2107         }
2108
2109         /* Get, parse the capabilities and save it to hw */
2110         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2111                         i40e_aqc_opc_list_func_capabilities, NULL);
2112         if (ret != I40E_SUCCESS)
2113                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2114
2115         /* Free the temporary buffer after being used */
2116         rte_free(buf);
2117
2118         return ret;
2119 }
2120
2121 static int
2122 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2123 {
2124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2126         uint16_t sum_queues = 0, sum_vsis, left_queues;
2127
2128         /* First check if FW support SRIOV */
2129         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2130                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2131                 return -EINVAL;
2132         }
2133
2134         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2135         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2136         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2137         /* Allocate queues for pf */
2138         if (hw->func_caps.rss) {
2139                 pf->flags |= I40E_FLAG_RSS;
2140                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2141                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2142                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2143         } else
2144                 pf->lan_nb_qps = 1;
2145         sum_queues = pf->lan_nb_qps;
2146         /* Default VSI is not counted in */
2147         sum_vsis = 0;
2148         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2149
2150         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2151                 pf->flags |= I40E_FLAG_SRIOV;
2152                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2153                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2154                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2155                                      "max supported %u.",
2156                                      dev->pci_dev->max_vfs,
2157                                      hw->func_caps.num_vfs);
2158                         return -EINVAL;
2159                 }
2160                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2161                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2162                                      "max support %u queues.",
2163                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2164                         return -EINVAL;
2165                 }
2166                 pf->vf_num = dev->pci_dev->max_vfs;
2167                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2168                 sum_vsis   += pf->vf_num;
2169                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2170                              pf->vf_num, pf->vf_nb_qps);
2171         } else
2172                 pf->vf_num = 0;
2173
2174         if (hw->func_caps.vmdq) {
2175                 pf->flags |= I40E_FLAG_VMDQ;
2176                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2177                 pf->max_nb_vmdq_vsi = 1;
2178                 /*
2179                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2180                  * later.
2181                  */
2182                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2183                 sum_vsis += pf->max_nb_vmdq_vsi;
2184         } else {
2185                 pf->vmdq_nb_qps = 0;
2186                 pf->max_nb_vmdq_vsi = 0;
2187         }
2188         pf->nb_cfg_vmdq_vsi = 0;
2189
2190         if (hw->func_caps.fd) {
2191                 pf->flags |= I40E_FLAG_FDIR;
2192                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2193                 /**
2194                  * Each flow director consumes one VSI and one queue,
2195                  * but can't calculate out predictably here.
2196                  */
2197         }
2198
2199         if (sum_vsis > pf->max_num_vsi ||
2200                 sum_queues > hw->func_caps.num_rx_qp) {
2201                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2202                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2203                              pf->max_num_vsi, sum_vsis);
2204                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2205                              hw->func_caps.num_rx_qp, sum_queues);
2206                 return -EINVAL;
2207         }
2208
2209         /* Adjust VMDQ setting to support as many VMs as possible */
2210         if (pf->flags & I40E_FLAG_VMDQ) {
2211                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2212
2213                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2214                                         pf->max_num_vsi - sum_vsis);
2215
2216                 /* Limit the max VMDQ number that rte_ether that can support  */
2217                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2218                                         ETH_64_POOLS - 1);
2219
2220                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2221                                 pf->max_nb_vmdq_vsi);
2222                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2223         }
2224
2225         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2226          * cause */
2227         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2228                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2229                              sum_vsis, hw->func_caps.num_msix_vectors);
2230                 return -EINVAL;
2231         }
2232         return I40E_SUCCESS;
2233 }
2234
2235 static int
2236 i40e_pf_get_switch_config(struct i40e_pf *pf)
2237 {
2238         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2239         struct i40e_aqc_get_switch_config_resp *switch_config;
2240         struct i40e_aqc_switch_config_element_resp *element;
2241         uint16_t start_seid = 0, num_reported;
2242         int ret;
2243
2244         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2245                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2246         if (!switch_config) {
2247                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2248                 return -ENOMEM;
2249         }
2250
2251         /* Get the switch configurations */
2252         ret = i40e_aq_get_switch_config(hw, switch_config,
2253                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2254         if (ret != I40E_SUCCESS) {
2255                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2256                 goto fail;
2257         }
2258         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2259         if (num_reported != 1) { /* The number should be 1 */
2260                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2261                 goto fail;
2262         }
2263
2264         /* Parse the switch configuration elements */
2265         element = &(switch_config->element[0]);
2266         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2267                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2268                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2269         } else
2270                 PMD_DRV_LOG(INFO, "Unknown element type");
2271
2272 fail:
2273         rte_free(switch_config);
2274
2275         return ret;
2276 }
2277
2278 static int
2279 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2280                         uint32_t num)
2281 {
2282         struct pool_entry *entry;
2283
2284         if (pool == NULL || num == 0)
2285                 return -EINVAL;
2286
2287         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2288         if (entry == NULL) {
2289                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2290                 return -ENOMEM;
2291         }
2292
2293         /* queue heap initialize */
2294         pool->num_free = num;
2295         pool->num_alloc = 0;
2296         pool->base = base;
2297         LIST_INIT(&pool->alloc_list);
2298         LIST_INIT(&pool->free_list);
2299
2300         /* Initialize element  */
2301         entry->base = 0;
2302         entry->len = num;
2303
2304         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2305         return 0;
2306 }
2307
2308 static void
2309 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2310 {
2311         struct pool_entry *entry;
2312
2313         if (pool == NULL)
2314                 return;
2315
2316         LIST_FOREACH(entry, &pool->alloc_list, next) {
2317                 LIST_REMOVE(entry, next);
2318                 rte_free(entry);
2319         }
2320
2321         LIST_FOREACH(entry, &pool->free_list, next) {
2322                 LIST_REMOVE(entry, next);
2323                 rte_free(entry);
2324         }
2325
2326         pool->num_free = 0;
2327         pool->num_alloc = 0;
2328         pool->base = 0;
2329         LIST_INIT(&pool->alloc_list);
2330         LIST_INIT(&pool->free_list);
2331 }
2332
2333 static int
2334 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2335                        uint32_t base)
2336 {
2337         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2338         uint32_t pool_offset;
2339         int insert;
2340
2341         if (pool == NULL) {
2342                 PMD_DRV_LOG(ERR, "Invalid parameter");
2343                 return -EINVAL;
2344         }
2345
2346         pool_offset = base - pool->base;
2347         /* Lookup in alloc list */
2348         LIST_FOREACH(entry, &pool->alloc_list, next) {
2349                 if (entry->base == pool_offset) {
2350                         valid_entry = entry;
2351                         LIST_REMOVE(entry, next);
2352                         break;
2353                 }
2354         }
2355
2356         /* Not find, return */
2357         if (valid_entry == NULL) {
2358                 PMD_DRV_LOG(ERR, "Failed to find entry");
2359                 return -EINVAL;
2360         }
2361
2362         /**
2363          * Found it, move it to free list  and try to merge.
2364          * In order to make merge easier, always sort it by qbase.
2365          * Find adjacent prev and last entries.
2366          */
2367         prev = next = NULL;
2368         LIST_FOREACH(entry, &pool->free_list, next) {
2369                 if (entry->base > valid_entry->base) {
2370                         next = entry;
2371                         break;
2372                 }
2373                 prev = entry;
2374         }
2375
2376         insert = 0;
2377         /* Try to merge with next one*/
2378         if (next != NULL) {
2379                 /* Merge with next one */
2380                 if (valid_entry->base + valid_entry->len == next->base) {
2381                         next->base = valid_entry->base;
2382                         next->len += valid_entry->len;
2383                         rte_free(valid_entry);
2384                         valid_entry = next;
2385                         insert = 1;
2386                 }
2387         }
2388
2389         if (prev != NULL) {
2390                 /* Merge with previous one */
2391                 if (prev->base + prev->len == valid_entry->base) {
2392                         prev->len += valid_entry->len;
2393                         /* If it merge with next one, remove next node */
2394                         if (insert == 1) {
2395                                 LIST_REMOVE(valid_entry, next);
2396                                 rte_free(valid_entry);
2397                         } else {
2398                                 rte_free(valid_entry);
2399                                 insert = 1;
2400                         }
2401                 }
2402         }
2403
2404         /* Not find any entry to merge, insert */
2405         if (insert == 0) {
2406                 if (prev != NULL)
2407                         LIST_INSERT_AFTER(prev, valid_entry, next);
2408                 else if (next != NULL)
2409                         LIST_INSERT_BEFORE(next, valid_entry, next);
2410                 else /* It's empty list, insert to head */
2411                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2412         }
2413
2414         pool->num_free += valid_entry->len;
2415         pool->num_alloc -= valid_entry->len;
2416
2417         return 0;
2418 }
2419
2420 static int
2421 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2422                        uint16_t num)
2423 {
2424         struct pool_entry *entry, *valid_entry;
2425
2426         if (pool == NULL || num == 0) {
2427                 PMD_DRV_LOG(ERR, "Invalid parameter");
2428                 return -EINVAL;
2429         }
2430
2431         if (pool->num_free < num) {
2432                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2433                             num, pool->num_free);
2434                 return -ENOMEM;
2435         }
2436
2437         valid_entry = NULL;
2438         /* Lookup  in free list and find most fit one */
2439         LIST_FOREACH(entry, &pool->free_list, next) {
2440                 if (entry->len >= num) {
2441                         /* Find best one */
2442                         if (entry->len == num) {
2443                                 valid_entry = entry;
2444                                 break;
2445                         }
2446                         if (valid_entry == NULL || valid_entry->len > entry->len)
2447                                 valid_entry = entry;
2448                 }
2449         }
2450
2451         /* Not find one to satisfy the request, return */
2452         if (valid_entry == NULL) {
2453                 PMD_DRV_LOG(ERR, "No valid entry found");
2454                 return -ENOMEM;
2455         }
2456         /**
2457          * The entry have equal queue number as requested,
2458          * remove it from alloc_list.
2459          */
2460         if (valid_entry->len == num) {
2461                 LIST_REMOVE(valid_entry, next);
2462         } else {
2463                 /**
2464                  * The entry have more numbers than requested,
2465                  * create a new entry for alloc_list and minus its
2466                  * queue base and number in free_list.
2467                  */
2468                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2469                 if (entry == NULL) {
2470                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2471                                     "resource pool");
2472                         return -ENOMEM;
2473                 }
2474                 entry->base = valid_entry->base;
2475                 entry->len = num;
2476                 valid_entry->base += num;
2477                 valid_entry->len -= num;
2478                 valid_entry = entry;
2479         }
2480
2481         /* Insert it into alloc list, not sorted */
2482         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2483
2484         pool->num_free -= valid_entry->len;
2485         pool->num_alloc += valid_entry->len;
2486
2487         return (valid_entry->base + pool->base);
2488 }
2489
2490 /**
2491  * bitmap_is_subset - Check whether src2 is subset of src1
2492  **/
2493 static inline int
2494 bitmap_is_subset(uint8_t src1, uint8_t src2)
2495 {
2496         return !((src1 ^ src2) & src2);
2497 }
2498
2499 static int
2500 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2501 {
2502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2503
2504         /* If DCB is not supported, only default TC is supported */
2505         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2506                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2507                 return -EINVAL;
2508         }
2509
2510         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2511                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2512                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2513                             enabled_tcmap);
2514                 return -EINVAL;
2515         }
2516         return I40E_SUCCESS;
2517 }
2518
2519 int
2520 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2521                                 struct i40e_vsi_vlan_pvid_info *info)
2522 {
2523         struct i40e_hw *hw;
2524         struct i40e_vsi_context ctxt;
2525         uint8_t vlan_flags = 0;
2526         int ret;
2527
2528         if (vsi == NULL || info == NULL) {
2529                 PMD_DRV_LOG(ERR, "invalid parameters");
2530                 return I40E_ERR_PARAM;
2531         }
2532
2533         if (info->on) {
2534                 vsi->info.pvid = info->config.pvid;
2535                 /**
2536                  * If insert pvid is enabled, only tagged pkts are
2537                  * allowed to be sent out.
2538                  */
2539                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2540                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2541         } else {
2542                 vsi->info.pvid = 0;
2543                 if (info->config.reject.tagged == 0)
2544                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2545
2546                 if (info->config.reject.untagged == 0)
2547                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2548         }
2549         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2550                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2551         vsi->info.port_vlan_flags |= vlan_flags;
2552         vsi->info.valid_sections =
2553                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2554         memset(&ctxt, 0, sizeof(ctxt));
2555         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2556         ctxt.seid = vsi->seid;
2557
2558         hw = I40E_VSI_TO_HW(vsi);
2559         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2560         if (ret != I40E_SUCCESS)
2561                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2562
2563         return ret;
2564 }
2565
2566 static int
2567 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2568 {
2569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2570         int i, ret;
2571         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2572
2573         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2574         if (ret != I40E_SUCCESS)
2575                 return ret;
2576
2577         if (!vsi->seid) {
2578                 PMD_DRV_LOG(ERR, "seid not valid");
2579                 return -EINVAL;
2580         }
2581
2582         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2583         tc_bw_data.tc_valid_bits = enabled_tcmap;
2584         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2585                 tc_bw_data.tc_bw_credits[i] =
2586                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2587
2588         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2589         if (ret != I40E_SUCCESS) {
2590                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2591                 return ret;
2592         }
2593
2594         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2595                                         sizeof(vsi->info.qs_handle));
2596         return I40E_SUCCESS;
2597 }
2598
2599 static int
2600 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2601                                  struct i40e_aqc_vsi_properties_data *info,
2602                                  uint8_t enabled_tcmap)
2603 {
2604         int ret, total_tc = 0, i;
2605         uint16_t qpnum_per_tc, bsf, qp_idx;
2606
2607         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2608         if (ret != I40E_SUCCESS)
2609                 return ret;
2610
2611         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2612                 if (enabled_tcmap & (1 << i))
2613                         total_tc++;
2614         vsi->enabled_tc = enabled_tcmap;
2615
2616         /* Number of queues per enabled TC */
2617         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2618         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2619         bsf = rte_bsf32(qpnum_per_tc);
2620
2621         /* Adjust the queue number to actual queues that can be applied */
2622         vsi->nb_qps = qpnum_per_tc * total_tc;
2623
2624         /**
2625          * Configure TC and queue mapping parameters, for enabled TC,
2626          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2627          * default queue will serve it.
2628          */
2629         qp_idx = 0;
2630         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2631                 if (vsi->enabled_tc & (1 << i)) {
2632                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2633                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2634                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2635                         qp_idx += qpnum_per_tc;
2636                 } else
2637                         info->tc_mapping[i] = 0;
2638         }
2639
2640         /* Associate queue number with VSI */
2641         if (vsi->type == I40E_VSI_SRIOV) {
2642                 info->mapping_flags |=
2643                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2644                 for (i = 0; i < vsi->nb_qps; i++)
2645                         info->queue_mapping[i] =
2646                                 rte_cpu_to_le_16(vsi->base_queue + i);
2647         } else {
2648                 info->mapping_flags |=
2649                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2650                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2651         }
2652         info->valid_sections |=
2653                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2654
2655         return I40E_SUCCESS;
2656 }
2657
2658 static int
2659 i40e_veb_release(struct i40e_veb *veb)
2660 {
2661         struct i40e_vsi *vsi;
2662         struct i40e_hw *hw;
2663
2664         if (veb == NULL || veb->associate_vsi == NULL)
2665                 return -EINVAL;
2666
2667         if (!TAILQ_EMPTY(&veb->head)) {
2668                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2669                 return -EACCES;
2670         }
2671
2672         vsi = veb->associate_vsi;
2673         hw = I40E_VSI_TO_HW(vsi);
2674
2675         vsi->uplink_seid = veb->uplink_seid;
2676         i40e_aq_delete_element(hw, veb->seid, NULL);
2677         rte_free(veb);
2678         vsi->veb = NULL;
2679         return I40E_SUCCESS;
2680 }
2681
2682 /* Setup a veb */
2683 static struct i40e_veb *
2684 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2685 {
2686         struct i40e_veb *veb;
2687         int ret;
2688         struct i40e_hw *hw;
2689
2690         if (NULL == pf || vsi == NULL) {
2691                 PMD_DRV_LOG(ERR, "veb setup failed, "
2692                             "associated VSI shouldn't null");
2693                 return NULL;
2694         }
2695         hw = I40E_PF_TO_HW(pf);
2696
2697         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2698         if (!veb) {
2699                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2700                 goto fail;
2701         }
2702
2703         veb->associate_vsi = vsi;
2704         TAILQ_INIT(&veb->head);
2705         veb->uplink_seid = vsi->uplink_seid;
2706
2707         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2708                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2709
2710         if (ret != I40E_SUCCESS) {
2711                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2712                             hw->aq.asq_last_status);
2713                 goto fail;
2714         }
2715
2716         /* get statistics index */
2717         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2718                                 &veb->stats_idx, NULL, NULL, NULL);
2719         if (ret != I40E_SUCCESS) {
2720                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2721                             hw->aq.asq_last_status);
2722                 goto fail;
2723         }
2724
2725         /* Get VEB bandwidth, to be implemented */
2726         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2727         vsi->uplink_seid = veb->seid;
2728
2729         return veb;
2730 fail:
2731         rte_free(veb);
2732         return NULL;
2733 }
2734
2735 int
2736 i40e_vsi_release(struct i40e_vsi *vsi)
2737 {
2738         struct i40e_pf *pf;
2739         struct i40e_hw *hw;
2740         struct i40e_vsi_list *vsi_list;
2741         int ret;
2742         struct i40e_mac_filter *f;
2743
2744         if (!vsi)
2745                 return I40E_SUCCESS;
2746
2747         pf = I40E_VSI_TO_PF(vsi);
2748         hw = I40E_VSI_TO_HW(vsi);
2749
2750         /* VSI has child to attach, release child first */
2751         if (vsi->veb) {
2752                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2753                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2754                                 return -1;
2755                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2756                 }
2757                 i40e_veb_release(vsi->veb);
2758         }
2759
2760         /* Remove all macvlan filters of the VSI */
2761         i40e_vsi_remove_all_macvlan_filter(vsi);
2762         TAILQ_FOREACH(f, &vsi->mac_list, next)
2763                 rte_free(f);
2764
2765         if (vsi->type != I40E_VSI_MAIN) {
2766                 /* Remove vsi from parent's sibling list */
2767                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2768                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2769                         return I40E_ERR_PARAM;
2770                 }
2771                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2772                                 &vsi->sib_vsi_list, list);
2773
2774                 /* Remove all switch element of the VSI */
2775                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2776                 if (ret != I40E_SUCCESS)
2777                         PMD_DRV_LOG(ERR, "Failed to delete element");
2778         }
2779         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2780
2781         if (vsi->type != I40E_VSI_SRIOV)
2782                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2783         rte_free(vsi);
2784
2785         return I40E_SUCCESS;
2786 }
2787
2788 static int
2789 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2790 {
2791         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2792         struct i40e_aqc_remove_macvlan_element_data def_filter;
2793         struct i40e_mac_filter_info filter;
2794         int ret;
2795
2796         if (vsi->type != I40E_VSI_MAIN)
2797                 return I40E_ERR_CONFIG;
2798         memset(&def_filter, 0, sizeof(def_filter));
2799         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2800                                         ETH_ADDR_LEN);
2801         def_filter.vlan_tag = 0;
2802         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2803                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2804         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2805         if (ret != I40E_SUCCESS) {
2806                 struct i40e_mac_filter *f;
2807                 struct ether_addr *mac;
2808
2809                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2810                             "macvlan filter");
2811                 /* It needs to add the permanent mac into mac list */
2812                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2813                 if (f == NULL) {
2814                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2815                         return I40E_ERR_NO_MEMORY;
2816                 }
2817                 mac = &f->mac_info.mac_addr;
2818                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2819                                 ETH_ADDR_LEN);
2820                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2821                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2822                 vsi->mac_num++;
2823
2824                 return ret;
2825         }
2826         (void)rte_memcpy(&filter.mac_addr,
2827                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2828         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2829         return i40e_vsi_add_mac(vsi, &filter);
2830 }
2831
2832 static int
2833 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2834 {
2835         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2836         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2837         struct i40e_hw *hw = &vsi->adapter->hw;
2838         i40e_status ret;
2839         int i;
2840
2841         memset(&bw_config, 0, sizeof(bw_config));
2842         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2843         if (ret != I40E_SUCCESS) {
2844                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2845                             hw->aq.asq_last_status);
2846                 return ret;
2847         }
2848
2849         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2850         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2851                                         &ets_sla_config, NULL);
2852         if (ret != I40E_SUCCESS) {
2853                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2854                             "configuration %u", hw->aq.asq_last_status);
2855                 return ret;
2856         }
2857
2858         /* Not store the info yet, just print out */
2859         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2860         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2861         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2862                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2863                             ets_sla_config.share_credits[i]);
2864                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2865                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2866                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2867                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2868                             (i * 4));
2869         }
2870
2871         return 0;
2872 }
2873
2874 /*
2875  * i40e_enable_pf_lb
2876  * @pf: pointer to the pf structure
2877  *
2878  * allow loopback on pf
2879  */
2880 static inline void
2881 i40e_enable_pf_lb(struct i40e_pf *pf)
2882 {
2883         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2884         struct i40e_vsi_context ctxt;
2885         int ret;
2886
2887         memset(&ctxt, 0, sizeof(ctxt));
2888         ctxt.seid = pf->main_vsi_seid;
2889         ctxt.pf_num = hw->pf_id;
2890         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2891         if (ret) {
2892                 PMD_DRV_LOG(ERR, "couldn't get pf vsi config, err %d, aq_err %d",
2893                         ret, hw->aq.asq_last_status);
2894                 return;
2895         }
2896         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
2897         ctxt.info.valid_sections =
2898                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2899         ctxt.info.switch_id |=
2900                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2901
2902         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2903         if (ret)
2904                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
2905                         hw->aq.asq_last_status);
2906 }
2907
2908 /* Setup a VSI */
2909 struct i40e_vsi *
2910 i40e_vsi_setup(struct i40e_pf *pf,
2911                enum i40e_vsi_type type,
2912                struct i40e_vsi *uplink_vsi,
2913                uint16_t user_param)
2914 {
2915         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2916         struct i40e_vsi *vsi;
2917         struct i40e_mac_filter_info filter;
2918         int ret;
2919         struct i40e_vsi_context ctxt;
2920         struct ether_addr broadcast =
2921                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2922
2923         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2924                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2925                             "VSI link shouldn't be NULL");
2926                 return NULL;
2927         }
2928
2929         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2930                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2931                             "uplink VSI should be NULL");
2932                 return NULL;
2933         }
2934
2935         /* If uplink vsi didn't setup VEB, create one first */
2936         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2937                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2938
2939                 if (NULL == uplink_vsi->veb) {
2940                         PMD_DRV_LOG(ERR, "VEB setup failed");
2941                         return NULL;
2942                 }
2943                 /* set ALLOWLOOPBACk on pf, when veb is created */
2944                 i40e_enable_pf_lb(pf);
2945         }
2946
2947         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2948         if (!vsi) {
2949                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2950                 return NULL;
2951         }
2952         TAILQ_INIT(&vsi->mac_list);
2953         vsi->type = type;
2954         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2955         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2956         vsi->parent_vsi = uplink_vsi;
2957         vsi->user_param = user_param;
2958         /* Allocate queues */
2959         switch (vsi->type) {
2960         case I40E_VSI_MAIN  :
2961                 vsi->nb_qps = pf->lan_nb_qps;
2962                 break;
2963         case I40E_VSI_SRIOV :
2964                 vsi->nb_qps = pf->vf_nb_qps;
2965                 break;
2966         case I40E_VSI_VMDQ2:
2967                 vsi->nb_qps = pf->vmdq_nb_qps;
2968                 break;
2969         case I40E_VSI_FDIR:
2970                 vsi->nb_qps = pf->fdir_nb_qps;
2971                 break;
2972         default:
2973                 goto fail_mem;
2974         }
2975         /*
2976          * The filter status descriptor is reported in rx queue 0,
2977          * while the tx queue for fdir filter programming has no
2978          * such constraints, can be non-zero queues.
2979          * To simplify it, choose FDIR vsi use queue 0 pair.
2980          * To make sure it will use queue 0 pair, queue allocation
2981          * need be done before this function is called
2982          */
2983         if (type != I40E_VSI_FDIR) {
2984                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2985                         if (ret < 0) {
2986                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2987                                                 vsi->seid, ret);
2988                                 goto fail_mem;
2989                         }
2990                         vsi->base_queue = ret;
2991         } else
2992                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2993
2994         /* VF has MSIX interrupt in VF range, don't allocate here */
2995         if (type != I40E_VSI_SRIOV) {
2996                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2997                 if (ret < 0) {
2998                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2999                         goto fail_queue_alloc;
3000                 }
3001                 vsi->msix_intr = ret;
3002         } else
3003                 vsi->msix_intr = 0;
3004         /* Add VSI */
3005         if (type == I40E_VSI_MAIN) {
3006                 /* For main VSI, no need to add since it's default one */
3007                 vsi->uplink_seid = pf->mac_seid;
3008                 vsi->seid = pf->main_vsi_seid;
3009                 /* Bind queues with specific MSIX interrupt */
3010                 /**
3011                  * Needs 2 interrupt at least, one for misc cause which will
3012                  * enabled from OS side, Another for queues binding the
3013                  * interrupt from device side only.
3014                  */
3015
3016                 /* Get default VSI parameters from hardware */
3017                 memset(&ctxt, 0, sizeof(ctxt));
3018                 ctxt.seid = vsi->seid;
3019                 ctxt.pf_num = hw->pf_id;
3020                 ctxt.uplink_seid = vsi->uplink_seid;
3021                 ctxt.vf_num = 0;
3022                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3023                 if (ret != I40E_SUCCESS) {
3024                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3025                         goto fail_msix_alloc;
3026                 }
3027                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3028                         sizeof(struct i40e_aqc_vsi_properties_data));
3029                 vsi->vsi_id = ctxt.vsi_number;
3030                 vsi->info.valid_sections = 0;
3031
3032                 /* Configure tc, enabled TC0 only */
3033                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3034                         I40E_SUCCESS) {
3035                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3036                         goto fail_msix_alloc;
3037                 }
3038
3039                 /* TC, queue mapping */
3040                 memset(&ctxt, 0, sizeof(ctxt));
3041                 vsi->info.valid_sections |=
3042                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3043                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3044                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3045                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3046                         sizeof(struct i40e_aqc_vsi_properties_data));
3047                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3048                                                 I40E_DEFAULT_TCMAP);
3049                 if (ret != I40E_SUCCESS) {
3050                         PMD_DRV_LOG(ERR, "Failed to configure "
3051                                     "TC queue mapping");
3052                         goto fail_msix_alloc;
3053                 }
3054                 ctxt.seid = vsi->seid;
3055                 ctxt.pf_num = hw->pf_id;
3056                 ctxt.uplink_seid = vsi->uplink_seid;
3057                 ctxt.vf_num = 0;
3058
3059                 /* Update VSI parameters */
3060                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3061                 if (ret != I40E_SUCCESS) {
3062                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3063                         goto fail_msix_alloc;
3064                 }
3065
3066                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3067                                                 sizeof(vsi->info.tc_mapping));
3068                 (void)rte_memcpy(&vsi->info.queue_mapping,
3069                                 &ctxt.info.queue_mapping,
3070                         sizeof(vsi->info.queue_mapping));
3071                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3072                 vsi->info.valid_sections = 0;
3073
3074                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3075                                 ETH_ADDR_LEN);
3076
3077                 /**
3078                  * Updating default filter settings are necessary to prevent
3079                  * reception of tagged packets.
3080                  * Some old firmware configurations load a default macvlan
3081                  * filter which accepts both tagged and untagged packets.
3082                  * The updating is to use a normal filter instead if needed.
3083                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3084                  * The firmware with correct configurations load the default
3085                  * macvlan filter which is expected and cannot be removed.
3086                  */
3087                 i40e_update_default_filter_setting(vsi);
3088         } else if (type == I40E_VSI_SRIOV) {
3089                 memset(&ctxt, 0, sizeof(ctxt));
3090                 /**
3091                  * For other VSI, the uplink_seid equals to uplink VSI's
3092                  * uplink_seid since they share same VEB
3093                  */
3094                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3095                 ctxt.pf_num = hw->pf_id;
3096                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3097                 ctxt.uplink_seid = vsi->uplink_seid;
3098                 ctxt.connection_type = 0x1;
3099                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3100
3101                 /* Configure switch ID */
3102                 ctxt.info.valid_sections |=
3103                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3104                 ctxt.info.switch_id =
3105                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3106                 /* Configure port/vlan */
3107                 ctxt.info.valid_sections |=
3108                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3109                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3110                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3111                                                 I40E_DEFAULT_TCMAP);
3112                 if (ret != I40E_SUCCESS) {
3113                         PMD_DRV_LOG(ERR, "Failed to configure "
3114                                     "TC queue mapping");
3115                         goto fail_msix_alloc;
3116                 }
3117                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3118                 ctxt.info.valid_sections |=
3119                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3120                 /**
3121                  * Since VSI is not created yet, only configure parameter,
3122                  * will add vsi below.
3123                  */
3124         } else if (type == I40E_VSI_VMDQ2) {
3125                 memset(&ctxt, 0, sizeof(ctxt));
3126                 /*
3127                  * For other VSI, the uplink_seid equals to uplink VSI's
3128                  * uplink_seid since they share same VEB
3129                  */
3130                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3131                 ctxt.pf_num = hw->pf_id;
3132                 ctxt.vf_num = 0;
3133                 ctxt.uplink_seid = vsi->uplink_seid;
3134                 ctxt.connection_type = 0x1;
3135                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3136
3137                 ctxt.info.valid_sections |=
3138                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3139                 /* user_param carries flag to enable loop back */
3140                 if (user_param) {
3141                         ctxt.info.switch_id =
3142                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3143                         ctxt.info.switch_id |=
3144                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3145                 }
3146
3147                 /* Configure port/vlan */
3148                 ctxt.info.valid_sections |=
3149                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3150                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3151                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3152                                                 I40E_DEFAULT_TCMAP);
3153                 if (ret != I40E_SUCCESS) {
3154                         PMD_DRV_LOG(ERR, "Failed to configure "
3155                                         "TC queue mapping");
3156                         goto fail_msix_alloc;
3157                 }
3158                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3159                 ctxt.info.valid_sections |=
3160                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3161         } else if (type == I40E_VSI_FDIR) {
3162                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3163                 ctxt.pf_num = hw->pf_id;
3164                 ctxt.vf_num = 0;
3165                 ctxt.uplink_seid = vsi->uplink_seid;
3166                 ctxt.connection_type = 0x1;     /* regular data port */
3167                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3168                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3169                                                 I40E_DEFAULT_TCMAP);
3170                 if (ret != I40E_SUCCESS) {
3171                         PMD_DRV_LOG(ERR, "Failed to configure "
3172                                         "TC queue mapping.");
3173                         goto fail_msix_alloc;
3174                 }
3175                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3176                 ctxt.info.valid_sections |=
3177                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3178         } else {
3179                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3180                 goto fail_msix_alloc;
3181         }
3182
3183         if (vsi->type != I40E_VSI_MAIN) {
3184                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3185                 if (ret) {
3186                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3187                                     hw->aq.asq_last_status);
3188                         goto fail_msix_alloc;
3189                 }
3190                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3191                 vsi->info.valid_sections = 0;
3192                 vsi->seid = ctxt.seid;
3193                 vsi->vsi_id = ctxt.vsi_number;
3194                 vsi->sib_vsi_list.vsi = vsi;
3195                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3196                                 &vsi->sib_vsi_list, list);
3197         }
3198
3199         /* MAC/VLAN configuration */
3200         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3201         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3202
3203         ret = i40e_vsi_add_mac(vsi, &filter);
3204         if (ret != I40E_SUCCESS) {
3205                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3206                 goto fail_msix_alloc;
3207         }
3208
3209         /* Get VSI BW information */
3210         i40e_vsi_dump_bw_config(vsi);
3211         return vsi;
3212 fail_msix_alloc:
3213         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3214 fail_queue_alloc:
3215         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3216 fail_mem:
3217         rte_free(vsi);
3218         return NULL;
3219 }
3220
3221 /* Configure vlan stripping on or off */
3222 int
3223 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3224 {
3225         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3226         struct i40e_vsi_context ctxt;
3227         uint8_t vlan_flags;
3228         int ret = I40E_SUCCESS;
3229
3230         /* Check if it has been already on or off */
3231         if (vsi->info.valid_sections &
3232                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3233                 if (on) {
3234                         if ((vsi->info.port_vlan_flags &
3235                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3236                                 return 0; /* already on */
3237                 } else {
3238                         if ((vsi->info.port_vlan_flags &
3239                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3240                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3241                                 return 0; /* already off */
3242                 }
3243         }
3244
3245         if (on)
3246                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3247         else
3248                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3249         vsi->info.valid_sections =
3250                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3251         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3252         vsi->info.port_vlan_flags |= vlan_flags;
3253         ctxt.seid = vsi->seid;
3254         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3255         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3256         if (ret)
3257                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3258                             on ? "enable" : "disable");
3259
3260         return ret;
3261 }
3262
3263 static int
3264 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3265 {
3266         struct rte_eth_dev_data *data = dev->data;
3267         int ret;
3268
3269         /* Apply vlan offload setting */
3270         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3271
3272         /* Apply double-vlan setting, not implemented yet */
3273
3274         /* Apply pvid setting */
3275         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3276                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3277         if (ret)
3278                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3279
3280         return ret;
3281 }
3282
3283 static int
3284 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3285 {
3286         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3287
3288         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3289 }
3290
3291 static int
3292 i40e_update_flow_control(struct i40e_hw *hw)
3293 {
3294 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3295         struct i40e_link_status link_status;
3296         uint32_t rxfc = 0, txfc = 0, reg;
3297         uint8_t an_info;
3298         int ret;
3299
3300         memset(&link_status, 0, sizeof(link_status));
3301         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3302         if (ret != I40E_SUCCESS) {
3303                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3304                 goto write_reg; /* Disable flow control */
3305         }
3306
3307         an_info = hw->phy.link_info.an_info;
3308         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3309                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3310                 ret = I40E_ERR_NOT_READY;
3311                 goto write_reg; /* Disable flow control */
3312         }
3313         /**
3314          * If link auto negotiation is enabled, flow control needs to
3315          * be configured according to it
3316          */
3317         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3318         case I40E_LINK_PAUSE_RXTX:
3319                 rxfc = 1;
3320                 txfc = 1;
3321                 hw->fc.current_mode = I40E_FC_FULL;
3322                 break;
3323         case I40E_AQ_LINK_PAUSE_RX:
3324                 rxfc = 1;
3325                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3326                 break;
3327         case I40E_AQ_LINK_PAUSE_TX:
3328                 txfc = 1;
3329                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3330                 break;
3331         default:
3332                 hw->fc.current_mode = I40E_FC_NONE;
3333                 break;
3334         }
3335
3336 write_reg:
3337         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3338                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3339         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3340         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3341         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3342         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3343
3344         return ret;
3345 }
3346
3347 /* PF setup */
3348 static int
3349 i40e_pf_setup(struct i40e_pf *pf)
3350 {
3351         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3352         struct i40e_filter_control_settings settings;
3353         struct i40e_vsi *vsi;
3354         int ret;
3355
3356         /* Clear all stats counters */
3357         pf->offset_loaded = FALSE;
3358         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3359         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3360
3361         ret = i40e_pf_get_switch_config(pf);
3362         if (ret != I40E_SUCCESS) {
3363                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3364                 return ret;
3365         }
3366         if (pf->flags & I40E_FLAG_FDIR) {
3367                 /* make queue allocated first, let FDIR use queue pair 0*/
3368                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3369                 if (ret != I40E_FDIR_QUEUE_ID) {
3370                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3371                                     " ret =%d", ret);
3372                         pf->flags &= ~I40E_FLAG_FDIR;
3373                 }
3374         }
3375         /*  main VSI setup */
3376         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3377         if (!vsi) {
3378                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3379                 return I40E_ERR_NOT_READY;
3380         }
3381         pf->main_vsi = vsi;
3382
3383         /* Configure filter control */
3384         memset(&settings, 0, sizeof(settings));
3385         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3386                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3387         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3388                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3389         else {
3390                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3391                                                 hw->func_caps.rss_table_size);
3392                 return I40E_ERR_PARAM;
3393         }
3394         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3395                         "size: %u\n", hw->func_caps.rss_table_size);
3396         pf->hash_lut_size = hw->func_caps.rss_table_size;
3397
3398         /* Enable ethtype and macvlan filters */
3399         settings.enable_ethtype = TRUE;
3400         settings.enable_macvlan = TRUE;
3401         ret = i40e_set_filter_control(hw, &settings);
3402         if (ret)
3403                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3404                                                                 ret);
3405
3406         /* Update flow control according to the auto negotiation */
3407         i40e_update_flow_control(hw);
3408
3409         return I40E_SUCCESS;
3410 }
3411
3412 int
3413 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3414 {
3415         uint32_t reg;
3416         uint16_t j;
3417
3418         /**
3419          * Set or clear TX Queue Disable flags,
3420          * which is required by hardware.
3421          */
3422         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3423         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3424
3425         /* Wait until the request is finished */
3426         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3427                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3428                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3429                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3430                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3431                                                         & 0x1))) {
3432                         break;
3433                 }
3434         }
3435         if (on) {
3436                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3437                         return I40E_SUCCESS; /* already on, skip next steps */
3438
3439                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3440                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3441         } else {
3442                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3443                         return I40E_SUCCESS; /* already off, skip next steps */
3444                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3445         }
3446         /* Write the register */
3447         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3448         /* Check the result */
3449         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3450                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3451                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3452                 if (on) {
3453                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3454                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3455                                 break;
3456                 } else {
3457                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3458                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3459                                 break;
3460                 }
3461         }
3462         /* Check if it is timeout */
3463         if (j >= I40E_CHK_Q_ENA_COUNT) {
3464                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3465                             (on ? "enable" : "disable"), q_idx);
3466                 return I40E_ERR_TIMEOUT;
3467         }
3468
3469         return I40E_SUCCESS;
3470 }
3471
3472 /* Swith on or off the tx queues */
3473 static int
3474 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3475 {
3476         struct rte_eth_dev_data *dev_data = pf->dev_data;
3477         struct i40e_tx_queue *txq;
3478         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3479         uint16_t i;
3480         int ret;
3481
3482         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3483                 txq = dev_data->tx_queues[i];
3484                 /* Don't operate the queue if not configured or
3485                  * if starting only per queue */
3486                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3487                         continue;
3488                 if (on)
3489                         ret = i40e_dev_tx_queue_start(dev, i);
3490                 else
3491                         ret = i40e_dev_tx_queue_stop(dev, i);
3492                 if ( ret != I40E_SUCCESS)
3493                         return ret;
3494         }
3495
3496         return I40E_SUCCESS;
3497 }
3498
3499 int
3500 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3501 {
3502         uint32_t reg;
3503         uint16_t j;
3504
3505         /* Wait until the request is finished */
3506         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3507                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3508                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3509                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3510                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3511                         break;
3512         }
3513
3514         if (on) {
3515                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3516                         return I40E_SUCCESS; /* Already on, skip next steps */
3517                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3518         } else {
3519                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3520                         return I40E_SUCCESS; /* Already off, skip next steps */
3521                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3522         }
3523
3524         /* Write the register */
3525         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3526         /* Check the result */
3527         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3528                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3529                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3530                 if (on) {
3531                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3532                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3533                                 break;
3534                 } else {
3535                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3536                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3537                                 break;
3538                 }
3539         }
3540
3541         /* Check if it is timeout */
3542         if (j >= I40E_CHK_Q_ENA_COUNT) {
3543                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3544                             (on ? "enable" : "disable"), q_idx);
3545                 return I40E_ERR_TIMEOUT;
3546         }
3547
3548         return I40E_SUCCESS;
3549 }
3550 /* Switch on or off the rx queues */
3551 static int
3552 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3553 {
3554         struct rte_eth_dev_data *dev_data = pf->dev_data;
3555         struct i40e_rx_queue *rxq;
3556         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3557         uint16_t i;
3558         int ret;
3559
3560         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3561                 rxq = dev_data->rx_queues[i];
3562                 /* Don't operate the queue if not configured or
3563                  * if starting only per queue */
3564                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3565                         continue;
3566                 if (on)
3567                         ret = i40e_dev_rx_queue_start(dev, i);
3568                 else
3569                         ret = i40e_dev_rx_queue_stop(dev, i);
3570                 if (ret != I40E_SUCCESS)
3571                         return ret;
3572         }
3573
3574         return I40E_SUCCESS;
3575 }
3576
3577 /* Switch on or off all the rx/tx queues */
3578 int
3579 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3580 {
3581         int ret;
3582
3583         if (on) {
3584                 /* enable rx queues before enabling tx queues */
3585                 ret = i40e_dev_switch_rx_queues(pf, on);
3586                 if (ret) {
3587                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3588                         return ret;
3589                 }
3590                 ret = i40e_dev_switch_tx_queues(pf, on);
3591         } else {
3592                 /* Stop tx queues before stopping rx queues */
3593                 ret = i40e_dev_switch_tx_queues(pf, on);
3594                 if (ret) {
3595                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3596                         return ret;
3597                 }
3598                 ret = i40e_dev_switch_rx_queues(pf, on);
3599         }
3600
3601         return ret;
3602 }
3603
3604 /* Initialize VSI for TX */
3605 static int
3606 i40e_dev_tx_init(struct i40e_pf *pf)
3607 {
3608         struct rte_eth_dev_data *data = pf->dev_data;
3609         uint16_t i;
3610         uint32_t ret = I40E_SUCCESS;
3611         struct i40e_tx_queue *txq;
3612
3613         for (i = 0; i < data->nb_tx_queues; i++) {
3614                 txq = data->tx_queues[i];
3615                 if (!txq || !txq->q_set)
3616                         continue;
3617                 ret = i40e_tx_queue_init(txq);
3618                 if (ret != I40E_SUCCESS)
3619                         break;
3620         }
3621
3622         return ret;
3623 }
3624
3625 /* Initialize VSI for RX */
3626 static int
3627 i40e_dev_rx_init(struct i40e_pf *pf)
3628 {
3629         struct rte_eth_dev_data *data = pf->dev_data;
3630         int ret = I40E_SUCCESS;
3631         uint16_t i;
3632         struct i40e_rx_queue *rxq;
3633
3634         i40e_pf_config_mq_rx(pf);
3635         for (i = 0; i < data->nb_rx_queues; i++) {
3636                 rxq = data->rx_queues[i];
3637                 if (!rxq || !rxq->q_set)
3638                         continue;
3639
3640                 ret = i40e_rx_queue_init(rxq);
3641                 if (ret != I40E_SUCCESS) {
3642                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3643                                     "initialization");
3644                         break;
3645                 }
3646         }
3647
3648         return ret;
3649 }
3650
3651 static int
3652 i40e_dev_rxtx_init(struct i40e_pf *pf)
3653 {
3654         int err;
3655
3656         err = i40e_dev_tx_init(pf);
3657         if (err) {
3658                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3659                 return err;
3660         }
3661         err = i40e_dev_rx_init(pf);
3662         if (err) {
3663                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3664                 return err;
3665         }
3666
3667         return err;
3668 }
3669
3670 static int
3671 i40e_vmdq_setup(struct rte_eth_dev *dev)
3672 {
3673         struct rte_eth_conf *conf = &dev->data->dev_conf;
3674         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3675         int i, err, conf_vsis, j, loop;
3676         struct i40e_vsi *vsi;
3677         struct i40e_vmdq_info *vmdq_info;
3678         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3680
3681         /*
3682          * Disable interrupt to avoid message from VF. Furthermore, it will
3683          * avoid race condition in VSI creation/destroy.
3684          */
3685         i40e_pf_disable_irq0(hw);
3686
3687         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3688                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3689                 return -ENOTSUP;
3690         }
3691
3692         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3693         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3694                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3695                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3696                         pf->max_nb_vmdq_vsi);
3697                 return -ENOTSUP;
3698         }
3699
3700         if (pf->vmdq != NULL) {
3701                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3702                 return 0;
3703         }
3704
3705         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3706                                 sizeof(*vmdq_info) * conf_vsis, 0);
3707
3708         if (pf->vmdq == NULL) {
3709                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3710                 return -ENOMEM;
3711         }
3712
3713         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3714
3715         /* Create VMDQ VSI */
3716         for (i = 0; i < conf_vsis; i++) {
3717                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3718                                 vmdq_conf->enable_loop_back);
3719                 if (vsi == NULL) {
3720                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3721                         err = -1;
3722                         goto err_vsi_setup;
3723                 }
3724                 vmdq_info = &pf->vmdq[i];
3725                 vmdq_info->pf = pf;
3726                 vmdq_info->vsi = vsi;
3727         }
3728         pf->nb_cfg_vmdq_vsi = conf_vsis;
3729
3730         /* Configure Vlan */
3731         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3732         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3733                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3734                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3735                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3736                                         vmdq_conf->pool_map[i].vlan_id, j);
3737
3738                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3739                                                 vmdq_conf->pool_map[i].vlan_id);
3740                                 if (err) {
3741                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3742                                         err = -1;
3743                                         goto err_vsi_setup;
3744                                 }
3745                         }
3746                 }
3747         }
3748
3749         i40e_pf_enable_irq0(hw);
3750
3751         return 0;
3752
3753 err_vsi_setup:
3754         for (i = 0; i < conf_vsis; i++)
3755                 if (pf->vmdq[i].vsi == NULL)
3756                         break;
3757                 else
3758                         i40e_vsi_release(pf->vmdq[i].vsi);
3759
3760         rte_free(pf->vmdq);
3761         pf->vmdq = NULL;
3762         i40e_pf_enable_irq0(hw);
3763         return err;
3764 }
3765
3766 static void
3767 i40e_stat_update_32(struct i40e_hw *hw,
3768                    uint32_t reg,
3769                    bool offset_loaded,
3770                    uint64_t *offset,
3771                    uint64_t *stat)
3772 {
3773         uint64_t new_data;
3774
3775         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3776         if (!offset_loaded)
3777                 *offset = new_data;
3778
3779         if (new_data >= *offset)
3780                 *stat = (uint64_t)(new_data - *offset);
3781         else
3782                 *stat = (uint64_t)((new_data +
3783                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3784 }
3785
3786 static void
3787 i40e_stat_update_48(struct i40e_hw *hw,
3788                    uint32_t hireg,
3789                    uint32_t loreg,
3790                    bool offset_loaded,
3791                    uint64_t *offset,
3792                    uint64_t *stat)
3793 {
3794         uint64_t new_data;
3795
3796         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3797         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3798                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3799
3800         if (!offset_loaded)
3801                 *offset = new_data;
3802
3803         if (new_data >= *offset)
3804                 *stat = new_data - *offset;
3805         else
3806                 *stat = (uint64_t)((new_data +
3807                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3808
3809         *stat &= I40E_48_BIT_MASK;
3810 }
3811
3812 /* Disable IRQ0 */
3813 void
3814 i40e_pf_disable_irq0(struct i40e_hw *hw)
3815 {
3816         /* Disable all interrupt types */
3817         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3818         I40E_WRITE_FLUSH(hw);
3819 }
3820
3821 /* Enable IRQ0 */
3822 void
3823 i40e_pf_enable_irq0(struct i40e_hw *hw)
3824 {
3825         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3826                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3827                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3828                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3829         I40E_WRITE_FLUSH(hw);
3830 }
3831
3832 static void
3833 i40e_pf_config_irq0(struct i40e_hw *hw)
3834 {
3835         /* read pending request and disable first */
3836         i40e_pf_disable_irq0(hw);
3837         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3838         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3839                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3840
3841         /* Link no queues with irq0 */
3842         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3843                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3844 }
3845
3846 static void
3847 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3848 {
3849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851         int i;
3852         uint16_t abs_vf_id;
3853         uint32_t index, offset, val;
3854
3855         if (!pf->vfs)
3856                 return;
3857         /**
3858          * Try to find which VF trigger a reset, use absolute VF id to access
3859          * since the reg is global register.
3860          */
3861         for (i = 0; i < pf->vf_num; i++) {
3862                 abs_vf_id = hw->func_caps.vf_base_id + i;
3863                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3864                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3865                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3866                 /* VFR event occured */
3867                 if (val & (0x1 << offset)) {
3868                         int ret;
3869
3870                         /* Clear the event first */
3871                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3872                                                         (0x1 << offset));
3873                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3874                         /**
3875                          * Only notify a VF reset event occured,
3876                          * don't trigger another SW reset
3877                          */
3878                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3879                         if (ret != I40E_SUCCESS)
3880                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3881                 }
3882         }
3883 }
3884
3885 static void
3886 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3887 {
3888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889         struct i40e_arq_event_info info;
3890         uint16_t pending, opcode;
3891         int ret;
3892
3893         info.buf_len = I40E_AQ_BUF_SZ;
3894         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3895         if (!info.msg_buf) {
3896                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3897                 return;
3898         }
3899
3900         pending = 1;
3901         while (pending) {
3902                 ret = i40e_clean_arq_element(hw, &info, &pending);
3903
3904                 if (ret != I40E_SUCCESS) {
3905                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3906                                     "aq_err: %u", hw->aq.asq_last_status);
3907                         break;
3908                 }
3909                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3910
3911                 switch (opcode) {
3912                 case i40e_aqc_opc_send_msg_to_pf:
3913                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3914                         i40e_pf_host_handle_vf_msg(dev,
3915                                         rte_le_to_cpu_16(info.desc.retval),
3916                                         rte_le_to_cpu_32(info.desc.cookie_high),
3917                                         rte_le_to_cpu_32(info.desc.cookie_low),
3918                                         info.msg_buf,
3919                                         info.msg_len);
3920                         break;
3921                 default:
3922                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3923                                     opcode);
3924                         break;
3925                 }
3926         }
3927         rte_free(info.msg_buf);
3928 }
3929
3930 /*
3931  * Interrupt handler is registered as the alarm callback for handling LSC
3932  * interrupt in a definite of time, in order to wait the NIC into a stable
3933  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3934  * no need for link down interrupt.
3935  */
3936 static void
3937 i40e_dev_interrupt_delayed_handler(void *param)
3938 {
3939         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941         uint32_t icr0;
3942
3943         /* read interrupt causes again */
3944         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3945
3946 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3947         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3948                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3949         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3950                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3951         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3952                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3953         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3954                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3955         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3956                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3957                                                                 "state\n");
3958         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3959                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3960         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3961                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3962 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3963
3964         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3965                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3966                 i40e_dev_handle_vfr_event(dev);
3967         }
3968         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3969                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3970                 i40e_dev_handle_aq_msg(dev);
3971         }
3972
3973         /* handle the link up interrupt in an alarm callback */
3974         i40e_dev_link_update(dev, 0);
3975         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3976
3977         i40e_pf_enable_irq0(hw);
3978         rte_intr_enable(&(dev->pci_dev->intr_handle));
3979 }
3980
3981 /**
3982  * Interrupt handler triggered by NIC  for handling
3983  * specific interrupt.
3984  *
3985  * @param handle
3986  *  Pointer to interrupt handle.
3987  * @param param
3988  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3989  *
3990  * @return
3991  *  void
3992  */
3993 static void
3994 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3995                            void *param)
3996 {
3997         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         uint32_t icr0;
4000
4001         /* Disable interrupt */
4002         i40e_pf_disable_irq0(hw);
4003
4004         /* read out interrupt causes */
4005         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4006
4007         /* No interrupt event indicated */
4008         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4009                 PMD_DRV_LOG(INFO, "No interrupt event");
4010                 goto done;
4011         }
4012 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4013         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4014                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4015         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4016                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4017         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4018                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4019         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4020                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4021         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4022                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4023         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4024                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4025         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4026                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4027 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4028
4029         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4030                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4031                 i40e_dev_handle_vfr_event(dev);
4032         }
4033         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4034                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4035                 i40e_dev_handle_aq_msg(dev);
4036         }
4037
4038         /* Link Status Change interrupt */
4039         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4040 #define I40E_US_PER_SECOND 1000000
4041                 struct rte_eth_link link;
4042
4043                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4044                 memset(&link, 0, sizeof(link));
4045                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4046                 i40e_dev_link_update(dev, 0);
4047
4048                 /*
4049                  * For link up interrupt, it needs to wait 1 second to let the
4050                  * hardware be a stable state. Otherwise several consecutive
4051                  * interrupts can be observed.
4052                  * For link down interrupt, no need to wait.
4053                  */
4054                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4055                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4056                         return;
4057                 else
4058                         _rte_eth_dev_callback_process(dev,
4059                                 RTE_ETH_EVENT_INTR_LSC);
4060         }
4061
4062 done:
4063         /* Enable interrupt */
4064         i40e_pf_enable_irq0(hw);
4065         rte_intr_enable(&(dev->pci_dev->intr_handle));
4066 }
4067
4068 static int
4069 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4070                          struct i40e_macvlan_filter *filter,
4071                          int total)
4072 {
4073         int ele_num, ele_buff_size;
4074         int num, actual_num, i;
4075         uint16_t flags;
4076         int ret = I40E_SUCCESS;
4077         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4078         struct i40e_aqc_add_macvlan_element_data *req_list;
4079
4080         if (filter == NULL  || total == 0)
4081                 return I40E_ERR_PARAM;
4082         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4083         ele_buff_size = hw->aq.asq_buf_size;
4084
4085         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4086         if (req_list == NULL) {
4087                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4088                 return I40E_ERR_NO_MEMORY;
4089         }
4090
4091         num = 0;
4092         do {
4093                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4094                 memset(req_list, 0, ele_buff_size);
4095
4096                 for (i = 0; i < actual_num; i++) {
4097                         (void)rte_memcpy(req_list[i].mac_addr,
4098                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4099                         req_list[i].vlan_tag =
4100                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4101
4102                         switch (filter[num + i].filter_type) {
4103                         case RTE_MAC_PERFECT_MATCH:
4104                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4105                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4106                                 break;
4107                         case RTE_MACVLAN_PERFECT_MATCH:
4108                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4109                                 break;
4110                         case RTE_MAC_HASH_MATCH:
4111                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4112                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4113                                 break;
4114                         case RTE_MACVLAN_HASH_MATCH:
4115                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4116                                 break;
4117                         default:
4118                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4119                                 ret = I40E_ERR_PARAM;
4120                                 goto DONE;
4121                         }
4122
4123                         req_list[i].queue_number = 0;
4124
4125                         req_list[i].flags = rte_cpu_to_le_16(flags);
4126                 }
4127
4128                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4129                                                 actual_num, NULL);
4130                 if (ret != I40E_SUCCESS) {
4131                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4132                         goto DONE;
4133                 }
4134                 num += actual_num;
4135         } while (num < total);
4136
4137 DONE:
4138         rte_free(req_list);
4139         return ret;
4140 }
4141
4142 static int
4143 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4144                             struct i40e_macvlan_filter *filter,
4145                             int total)
4146 {
4147         int ele_num, ele_buff_size;
4148         int num, actual_num, i;
4149         uint16_t flags;
4150         int ret = I40E_SUCCESS;
4151         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4152         struct i40e_aqc_remove_macvlan_element_data *req_list;
4153
4154         if (filter == NULL  || total == 0)
4155                 return I40E_ERR_PARAM;
4156
4157         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4158         ele_buff_size = hw->aq.asq_buf_size;
4159
4160         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4161         if (req_list == NULL) {
4162                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4163                 return I40E_ERR_NO_MEMORY;
4164         }
4165
4166         num = 0;
4167         do {
4168                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4169                 memset(req_list, 0, ele_buff_size);
4170
4171                 for (i = 0; i < actual_num; i++) {
4172                         (void)rte_memcpy(req_list[i].mac_addr,
4173                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4174                         req_list[i].vlan_tag =
4175                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4176
4177                         switch (filter[num + i].filter_type) {
4178                         case RTE_MAC_PERFECT_MATCH:
4179                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4180                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4181                                 break;
4182                         case RTE_MACVLAN_PERFECT_MATCH:
4183                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4184                                 break;
4185                         case RTE_MAC_HASH_MATCH:
4186                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4187                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4188                                 break;
4189                         case RTE_MACVLAN_HASH_MATCH:
4190                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4191                                 break;
4192                         default:
4193                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4194                                 ret = I40E_ERR_PARAM;
4195                                 goto DONE;
4196                         }
4197                         req_list[i].flags = rte_cpu_to_le_16(flags);
4198                 }
4199
4200                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4201                                                 actual_num, NULL);
4202                 if (ret != I40E_SUCCESS) {
4203                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4204                         goto DONE;
4205                 }
4206                 num += actual_num;
4207         } while (num < total);
4208
4209 DONE:
4210         rte_free(req_list);
4211         return ret;
4212 }
4213
4214 /* Find out specific MAC filter */
4215 static struct i40e_mac_filter *
4216 i40e_find_mac_filter(struct i40e_vsi *vsi,
4217                          struct ether_addr *macaddr)
4218 {
4219         struct i40e_mac_filter *f;
4220
4221         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4222                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4223                         return f;
4224         }
4225
4226         return NULL;
4227 }
4228
4229 static bool
4230 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4231                          uint16_t vlan_id)
4232 {
4233         uint32_t vid_idx, vid_bit;
4234
4235         if (vlan_id > ETH_VLAN_ID_MAX)
4236                 return 0;
4237
4238         vid_idx = I40E_VFTA_IDX(vlan_id);
4239         vid_bit = I40E_VFTA_BIT(vlan_id);
4240
4241         if (vsi->vfta[vid_idx] & vid_bit)
4242                 return 1;
4243         else
4244                 return 0;
4245 }
4246
4247 static void
4248 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4249                          uint16_t vlan_id, bool on)
4250 {
4251         uint32_t vid_idx, vid_bit;
4252
4253         if (vlan_id > ETH_VLAN_ID_MAX)
4254                 return;
4255
4256         vid_idx = I40E_VFTA_IDX(vlan_id);
4257         vid_bit = I40E_VFTA_BIT(vlan_id);
4258
4259         if (on)
4260                 vsi->vfta[vid_idx] |= vid_bit;
4261         else
4262                 vsi->vfta[vid_idx] &= ~vid_bit;
4263 }
4264
4265 /**
4266  * Find all vlan options for specific mac addr,
4267  * return with actual vlan found.
4268  */
4269 static inline int
4270 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4271                            struct i40e_macvlan_filter *mv_f,
4272                            int num, struct ether_addr *addr)
4273 {
4274         int i;
4275         uint32_t j, k;
4276
4277         /**
4278          * Not to use i40e_find_vlan_filter to decrease the loop time,
4279          * although the code looks complex.
4280           */
4281         if (num < vsi->vlan_num)
4282                 return I40E_ERR_PARAM;
4283
4284         i = 0;
4285         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4286                 if (vsi->vfta[j]) {
4287                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4288                                 if (vsi->vfta[j] & (1 << k)) {
4289                                         if (i > num - 1) {
4290                                                 PMD_DRV_LOG(ERR, "vlan number "
4291                                                             "not match");
4292                                                 return I40E_ERR_PARAM;
4293                                         }
4294                                         (void)rte_memcpy(&mv_f[i].macaddr,
4295                                                         addr, ETH_ADDR_LEN);
4296                                         mv_f[i].vlan_id =
4297                                                 j * I40E_UINT32_BIT_SIZE + k;
4298                                         i++;
4299                                 }
4300                         }
4301                 }
4302         }
4303         return I40E_SUCCESS;
4304 }
4305
4306 static inline int
4307 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4308                            struct i40e_macvlan_filter *mv_f,
4309                            int num,
4310                            uint16_t vlan)
4311 {
4312         int i = 0;
4313         struct i40e_mac_filter *f;
4314
4315         if (num < vsi->mac_num)
4316                 return I40E_ERR_PARAM;
4317
4318         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4319                 if (i > num - 1) {
4320                         PMD_DRV_LOG(ERR, "buffer number not match");
4321                         return I40E_ERR_PARAM;
4322                 }
4323                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4324                                 ETH_ADDR_LEN);
4325                 mv_f[i].vlan_id = vlan;
4326                 mv_f[i].filter_type = f->mac_info.filter_type;
4327                 i++;
4328         }
4329
4330         return I40E_SUCCESS;
4331 }
4332
4333 static int
4334 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4335 {
4336         int i, num;
4337         struct i40e_mac_filter *f;
4338         struct i40e_macvlan_filter *mv_f;
4339         int ret = I40E_SUCCESS;
4340
4341         if (vsi == NULL || vsi->mac_num == 0)
4342                 return I40E_ERR_PARAM;
4343
4344         /* Case that no vlan is set */
4345         if (vsi->vlan_num == 0)
4346                 num = vsi->mac_num;
4347         else
4348                 num = vsi->mac_num * vsi->vlan_num;
4349
4350         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4351         if (mv_f == NULL) {
4352                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4353                 return I40E_ERR_NO_MEMORY;
4354         }
4355
4356         i = 0;
4357         if (vsi->vlan_num == 0) {
4358                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4359                         (void)rte_memcpy(&mv_f[i].macaddr,
4360                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4361                         mv_f[i].vlan_id = 0;
4362                         i++;
4363                 }
4364         } else {
4365                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4366                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4367                                         vsi->vlan_num, &f->mac_info.mac_addr);
4368                         if (ret != I40E_SUCCESS)
4369                                 goto DONE;
4370                         i += vsi->vlan_num;
4371                 }
4372         }
4373
4374         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4375 DONE:
4376         rte_free(mv_f);
4377
4378         return ret;
4379 }
4380
4381 int
4382 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4383 {
4384         struct i40e_macvlan_filter *mv_f;
4385         int mac_num;
4386         int ret = I40E_SUCCESS;
4387
4388         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4389                 return I40E_ERR_PARAM;
4390
4391         /* If it's already set, just return */
4392         if (i40e_find_vlan_filter(vsi,vlan))
4393                 return I40E_SUCCESS;
4394
4395         mac_num = vsi->mac_num;
4396
4397         if (mac_num == 0) {
4398                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4399                 return I40E_ERR_PARAM;
4400         }
4401
4402         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4403
4404         if (mv_f == NULL) {
4405                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4406                 return I40E_ERR_NO_MEMORY;
4407         }
4408
4409         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4410
4411         if (ret != I40E_SUCCESS)
4412                 goto DONE;
4413
4414         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4415
4416         if (ret != I40E_SUCCESS)
4417                 goto DONE;
4418
4419         i40e_set_vlan_filter(vsi, vlan, 1);
4420
4421         vsi->vlan_num++;
4422         ret = I40E_SUCCESS;
4423 DONE:
4424         rte_free(mv_f);
4425         return ret;
4426 }
4427
4428 int
4429 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4430 {
4431         struct i40e_macvlan_filter *mv_f;
4432         int mac_num;
4433         int ret = I40E_SUCCESS;
4434
4435         /**
4436          * Vlan 0 is the generic filter for untagged packets
4437          * and can't be removed.
4438          */
4439         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4440                 return I40E_ERR_PARAM;
4441
4442         /* If can't find it, just return */
4443         if (!i40e_find_vlan_filter(vsi, vlan))
4444                 return I40E_ERR_PARAM;
4445
4446         mac_num = vsi->mac_num;
4447
4448         if (mac_num == 0) {
4449                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4450                 return I40E_ERR_PARAM;
4451         }
4452
4453         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4454
4455         if (mv_f == NULL) {
4456                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4457                 return I40E_ERR_NO_MEMORY;
4458         }
4459
4460         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4461
4462         if (ret != I40E_SUCCESS)
4463                 goto DONE;
4464
4465         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4466
4467         if (ret != I40E_SUCCESS)
4468                 goto DONE;
4469
4470         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4471         if (vsi->vlan_num == 1) {
4472                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4473                 if (ret != I40E_SUCCESS)
4474                         goto DONE;
4475
4476                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4477                 if (ret != I40E_SUCCESS)
4478                         goto DONE;
4479         }
4480
4481         i40e_set_vlan_filter(vsi, vlan, 0);
4482
4483         vsi->vlan_num--;
4484         ret = I40E_SUCCESS;
4485 DONE:
4486         rte_free(mv_f);
4487         return ret;
4488 }
4489
4490 int
4491 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4492 {
4493         struct i40e_mac_filter *f;
4494         struct i40e_macvlan_filter *mv_f;
4495         int i, vlan_num = 0;
4496         int ret = I40E_SUCCESS;
4497
4498         /* If it's add and we've config it, return */
4499         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4500         if (f != NULL)
4501                 return I40E_SUCCESS;
4502         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4503                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4504
4505                 /**
4506                  * If vlan_num is 0, that's the first time to add mac,
4507                  * set mask for vlan_id 0.
4508                  */
4509                 if (vsi->vlan_num == 0) {
4510                         i40e_set_vlan_filter(vsi, 0, 1);
4511                         vsi->vlan_num = 1;
4512                 }
4513                 vlan_num = vsi->vlan_num;
4514         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4515                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4516                 vlan_num = 1;
4517
4518         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4519         if (mv_f == NULL) {
4520                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4521                 return I40E_ERR_NO_MEMORY;
4522         }
4523
4524         for (i = 0; i < vlan_num; i++) {
4525                 mv_f[i].filter_type = mac_filter->filter_type;
4526                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4527                                 ETH_ADDR_LEN);
4528         }
4529
4530         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4531                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4532                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4533                                         &mac_filter->mac_addr);
4534                 if (ret != I40E_SUCCESS)
4535                         goto DONE;
4536         }
4537
4538         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4539         if (ret != I40E_SUCCESS)
4540                 goto DONE;
4541
4542         /* Add the mac addr into mac list */
4543         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4544         if (f == NULL) {
4545                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4546                 ret = I40E_ERR_NO_MEMORY;
4547                 goto DONE;
4548         }
4549         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4550                         ETH_ADDR_LEN);
4551         f->mac_info.filter_type = mac_filter->filter_type;
4552         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4553         vsi->mac_num++;
4554
4555         ret = I40E_SUCCESS;
4556 DONE:
4557         rte_free(mv_f);
4558
4559         return ret;
4560 }
4561
4562 int
4563 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4564 {
4565         struct i40e_mac_filter *f;
4566         struct i40e_macvlan_filter *mv_f;
4567         int i, vlan_num;
4568         enum rte_mac_filter_type filter_type;
4569         int ret = I40E_SUCCESS;
4570
4571         /* Can't find it, return an error */
4572         f = i40e_find_mac_filter(vsi, addr);
4573         if (f == NULL)
4574                 return I40E_ERR_PARAM;
4575
4576         vlan_num = vsi->vlan_num;
4577         filter_type = f->mac_info.filter_type;
4578         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4579                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4580                 if (vlan_num == 0) {
4581                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4582                         return I40E_ERR_PARAM;
4583                 }
4584         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4585                         filter_type == RTE_MAC_HASH_MATCH)
4586                 vlan_num = 1;
4587
4588         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4589         if (mv_f == NULL) {
4590                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4591                 return I40E_ERR_NO_MEMORY;
4592         }
4593
4594         for (i = 0; i < vlan_num; i++) {
4595                 mv_f[i].filter_type = filter_type;
4596                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4597                                 ETH_ADDR_LEN);
4598         }
4599         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4600                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4601                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4602                 if (ret != I40E_SUCCESS)
4603                         goto DONE;
4604         }
4605
4606         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4607         if (ret != I40E_SUCCESS)
4608                 goto DONE;
4609
4610         /* Remove the mac addr into mac list */
4611         TAILQ_REMOVE(&vsi->mac_list, f, next);
4612         rte_free(f);
4613         vsi->mac_num--;
4614
4615         ret = I40E_SUCCESS;
4616 DONE:
4617         rte_free(mv_f);
4618         return ret;
4619 }
4620
4621 /* Configure hash enable flags for RSS */
4622 uint64_t
4623 i40e_config_hena(uint64_t flags)
4624 {
4625         uint64_t hena = 0;
4626
4627         if (!flags)
4628                 return hena;
4629
4630         if (flags & ETH_RSS_FRAG_IPV4)
4631                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4632         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4633                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4634         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4635                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4636         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4637                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4638         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4639                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4640         if (flags & ETH_RSS_FRAG_IPV6)
4641                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4642         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4643                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4644         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4645                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4646         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4647                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4648         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4649                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4650         if (flags & ETH_RSS_L2_PAYLOAD)
4651                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4652
4653         return hena;
4654 }
4655
4656 /* Parse the hash enable flags */
4657 uint64_t
4658 i40e_parse_hena(uint64_t flags)
4659 {
4660         uint64_t rss_hf = 0;
4661
4662         if (!flags)
4663                 return rss_hf;
4664         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4665                 rss_hf |= ETH_RSS_FRAG_IPV4;
4666         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4667                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4668         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4669                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4670         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4671                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4672         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4673                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4674         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4675                 rss_hf |= ETH_RSS_FRAG_IPV6;
4676         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4677                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4678         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4679                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4680         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4681                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4682         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4683                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4684         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4685                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4686
4687         return rss_hf;
4688 }
4689
4690 /* Disable RSS */
4691 static void
4692 i40e_pf_disable_rss(struct i40e_pf *pf)
4693 {
4694         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4695         uint64_t hena;
4696
4697         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4698         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4699         hena &= ~I40E_RSS_HENA_ALL;
4700         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4701         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4702         I40E_WRITE_FLUSH(hw);
4703 }
4704
4705 static int
4706 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4707 {
4708         uint32_t *hash_key;
4709         uint8_t hash_key_len;
4710         uint64_t rss_hf;
4711         uint16_t i;
4712         uint64_t hena;
4713
4714         hash_key = (uint32_t *)(rss_conf->rss_key);
4715         hash_key_len = rss_conf->rss_key_len;
4716         if (hash_key != NULL && hash_key_len >=
4717                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4718                 /* Fill in RSS hash key */
4719                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4720                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4721         }
4722
4723         rss_hf = rss_conf->rss_hf;
4724         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4725         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4726         hena &= ~I40E_RSS_HENA_ALL;
4727         hena |= i40e_config_hena(rss_hf);
4728         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4729         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4730         I40E_WRITE_FLUSH(hw);
4731
4732         return 0;
4733 }
4734
4735 static int
4736 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4737                          struct rte_eth_rss_conf *rss_conf)
4738 {
4739         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4740         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4741         uint64_t hena;
4742
4743         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4744         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4745         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4746                 if (rss_hf != 0) /* Enable RSS */
4747                         return -EINVAL;
4748                 return 0; /* Nothing to do */
4749         }
4750         /* RSS enabled */
4751         if (rss_hf == 0) /* Disable RSS */
4752                 return -EINVAL;
4753
4754         return i40e_hw_rss_hash_set(hw, rss_conf);
4755 }
4756
4757 static int
4758 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4759                            struct rte_eth_rss_conf *rss_conf)
4760 {
4761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4763         uint64_t hena;
4764         uint16_t i;
4765
4766         if (hash_key != NULL) {
4767                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4768                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4769                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4770         }
4771         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4772         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4773         rss_conf->rss_hf = i40e_parse_hena(hena);
4774
4775         return 0;
4776 }
4777
4778 static int
4779 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4780 {
4781         switch (filter_type) {
4782         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4783                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4784                 break;
4785         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4786                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4787                 break;
4788         case RTE_TUNNEL_FILTER_IMAC_TENID:
4789                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4790                 break;
4791         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4792                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4793                 break;
4794         case ETH_TUNNEL_FILTER_IMAC:
4795                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4796                 break;
4797         default:
4798                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4799                 return -EINVAL;
4800         }
4801
4802         return 0;
4803 }
4804
4805 static int
4806 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4807                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4808                         uint8_t add)
4809 {
4810         uint16_t ip_type;
4811         uint8_t tun_type = 0;
4812         int val, ret = 0;
4813         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4814         struct i40e_vsi *vsi = pf->main_vsi;
4815         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4816         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4817
4818         cld_filter = rte_zmalloc("tunnel_filter",
4819                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4820                 0);
4821
4822         if (NULL == cld_filter) {
4823                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4824                 return -EINVAL;
4825         }
4826         pfilter = cld_filter;
4827
4828         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4829                         sizeof(struct ether_addr));
4830         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4831                         sizeof(struct ether_addr));
4832
4833         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4834         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4835                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4836                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4837                                 &tunnel_filter->ip_addr,
4838                                 sizeof(pfilter->ipaddr.v4.data));
4839         } else {
4840                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4841                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4842                                 &tunnel_filter->ip_addr,
4843                                 sizeof(pfilter->ipaddr.v6.data));
4844         }
4845
4846         /* check tunneled type */
4847         switch (tunnel_filter->tunnel_type) {
4848         case RTE_TUNNEL_TYPE_VXLAN:
4849                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4850                 break;
4851         case RTE_TUNNEL_TYPE_NVGRE:
4852                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4853                 break;
4854         default:
4855                 /* Other tunnel types is not supported. */
4856                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4857                 rte_free(cld_filter);
4858                 return -EINVAL;
4859         }
4860
4861         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4862                                                 &pfilter->flags);
4863         if (val < 0) {
4864                 rte_free(cld_filter);
4865                 return -EINVAL;
4866         }
4867
4868         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4869                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4870         pfilter->tenant_id = tunnel_filter->tenant_id;
4871         pfilter->queue_number = tunnel_filter->queue_id;
4872
4873         if (add)
4874                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4875         else
4876                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4877                                                 cld_filter, 1);
4878
4879         rte_free(cld_filter);
4880         return ret;
4881 }
4882
4883 static int
4884 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4885 {
4886         uint8_t i;
4887
4888         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4889                 if (pf->vxlan_ports[i] == port)
4890                         return i;
4891         }
4892
4893         return -1;
4894 }
4895
4896 static int
4897 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4898 {
4899         int  idx, ret;
4900         uint8_t filter_idx;
4901         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4902
4903         idx = i40e_get_vxlan_port_idx(pf, port);
4904
4905         /* Check if port already exists */
4906         if (idx >= 0) {
4907                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4908                 return -EINVAL;
4909         }
4910
4911         /* Now check if there is space to add the new port */
4912         idx = i40e_get_vxlan_port_idx(pf, 0);
4913         if (idx < 0) {
4914                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4915                         "not adding port %d", port);
4916                 return -ENOSPC;
4917         }
4918
4919         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4920                                         &filter_idx, NULL);
4921         if (ret < 0) {
4922                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4923                 return -1;
4924         }
4925
4926         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4927                          port,  filter_idx);
4928
4929         /* New port: add it and mark its index in the bitmap */
4930         pf->vxlan_ports[idx] = port;
4931         pf->vxlan_bitmap |= (1 << idx);
4932
4933         if (!(pf->flags & I40E_FLAG_VXLAN))
4934                 pf->flags |= I40E_FLAG_VXLAN;
4935
4936         return 0;
4937 }
4938
4939 static int
4940 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4941 {
4942         int idx;
4943         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4944
4945         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4946                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4947                 return -EINVAL;
4948         }
4949
4950         idx = i40e_get_vxlan_port_idx(pf, port);
4951
4952         if (idx < 0) {
4953                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4954                 return -EINVAL;
4955         }
4956
4957         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4958                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4959                 return -1;
4960         }
4961
4962         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4963                         port, idx);
4964
4965         pf->vxlan_ports[idx] = 0;
4966         pf->vxlan_bitmap &= ~(1 << idx);
4967
4968         if (!pf->vxlan_bitmap)
4969                 pf->flags &= ~I40E_FLAG_VXLAN;
4970
4971         return 0;
4972 }
4973
4974 /* Add UDP tunneling port */
4975 static int
4976 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4977                         struct rte_eth_udp_tunnel *udp_tunnel)
4978 {
4979         int ret = 0;
4980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4981
4982         if (udp_tunnel == NULL)
4983                 return -EINVAL;
4984
4985         switch (udp_tunnel->prot_type) {
4986         case RTE_TUNNEL_TYPE_VXLAN:
4987                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4988                 break;
4989
4990         case RTE_TUNNEL_TYPE_GENEVE:
4991         case RTE_TUNNEL_TYPE_TEREDO:
4992                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4993                 ret = -1;
4994                 break;
4995
4996         default:
4997                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4998                 ret = -1;
4999                 break;
5000         }
5001
5002         return ret;
5003 }
5004
5005 /* Remove UDP tunneling port */
5006 static int
5007 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5008                         struct rte_eth_udp_tunnel *udp_tunnel)
5009 {
5010         int ret = 0;
5011         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5012
5013         if (udp_tunnel == NULL)
5014                 return -EINVAL;
5015
5016         switch (udp_tunnel->prot_type) {
5017         case RTE_TUNNEL_TYPE_VXLAN:
5018                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5019                 break;
5020         case RTE_TUNNEL_TYPE_GENEVE:
5021         case RTE_TUNNEL_TYPE_TEREDO:
5022                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5023                 ret = -1;
5024                 break;
5025         default:
5026                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5027                 ret = -1;
5028                 break;
5029         }
5030
5031         return ret;
5032 }
5033
5034 /* Calculate the maximum number of contiguous PF queues that are configured */
5035 static int
5036 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5037 {
5038         struct rte_eth_dev_data *data = pf->dev_data;
5039         int i, num;
5040         struct i40e_rx_queue *rxq;
5041
5042         num = 0;
5043         for (i = 0; i < pf->lan_nb_qps; i++) {
5044                 rxq = data->rx_queues[i];
5045                 if (rxq && rxq->q_set)
5046                         num++;
5047                 else
5048                         break;
5049         }
5050
5051         return num;
5052 }
5053
5054 /* Configure RSS */
5055 static int
5056 i40e_pf_config_rss(struct i40e_pf *pf)
5057 {
5058         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5059         struct rte_eth_rss_conf rss_conf;
5060         uint32_t i, lut = 0;
5061         uint16_t j, num;
5062
5063         /*
5064          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5065          * It's necessary to calulate the actual PF queues that are configured.
5066          */
5067         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5068                 num = i40e_pf_calc_configured_queues_num(pf);
5069                 num = i40e_align_floor(num);
5070         } else
5071                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5072
5073         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5074                         num);
5075
5076         if (num == 0) {
5077                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5078                 return -ENOTSUP;
5079         }
5080
5081         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5082                 if (j == num)
5083                         j = 0;
5084                 lut = (lut << 8) | (j & ((0x1 <<
5085                         hw->func_caps.rss_table_entry_width) - 1));
5086                 if ((i & 3) == 3)
5087                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5088         }
5089
5090         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5091         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5092                 i40e_pf_disable_rss(pf);
5093                 return 0;
5094         }
5095         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5096                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5097                 /* Random default keys */
5098                 static uint32_t rss_key_default[] = {0x6b793944,
5099                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5100                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5101                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5102
5103                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5104                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5105                                                         sizeof(uint32_t);
5106         }
5107
5108         return i40e_hw_rss_hash_set(hw, &rss_conf);
5109 }
5110
5111 static int
5112 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5113                         struct rte_eth_tunnel_filter_conf *filter)
5114 {
5115         if (pf == NULL || filter == NULL) {
5116                 PMD_DRV_LOG(ERR, "Invalid parameter");
5117                 return -EINVAL;
5118         }
5119
5120         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5121                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5122                 return -EINVAL;
5123         }
5124
5125         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5126                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5127                 return -EINVAL;
5128         }
5129
5130         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5131                 (is_zero_ether_addr(filter->outer_mac))) {
5132                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5133                 return -EINVAL;
5134         }
5135
5136         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5137                 (is_zero_ether_addr(filter->inner_mac))) {
5138                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5139                 return -EINVAL;
5140         }
5141
5142         return 0;
5143 }
5144
5145 static int
5146 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5147                         void *arg)
5148 {
5149         struct rte_eth_tunnel_filter_conf *filter;
5150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5151         int ret = I40E_SUCCESS;
5152
5153         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5154
5155         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5156                 return I40E_ERR_PARAM;
5157
5158         switch (filter_op) {
5159         case RTE_ETH_FILTER_NOP:
5160                 if (!(pf->flags & I40E_FLAG_VXLAN))
5161                         ret = I40E_NOT_SUPPORTED;
5162         case RTE_ETH_FILTER_ADD:
5163                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5164                 break;
5165         case RTE_ETH_FILTER_DELETE:
5166                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5167                 break;
5168         default:
5169                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5170                 ret = I40E_ERR_PARAM;
5171                 break;
5172         }
5173
5174         return ret;
5175 }
5176
5177 static int
5178 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5179 {
5180         int ret = 0;
5181         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5182
5183         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5184                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5185                 return -ENOTSUP;
5186         }
5187
5188         /* RSS setup */
5189         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5190                 ret = i40e_pf_config_rss(pf);
5191         else
5192                 i40e_pf_disable_rss(pf);
5193
5194         return ret;
5195 }
5196
5197 /* Get the symmetric hash enable configurations per port */
5198 static void
5199 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5200 {
5201         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5202
5203         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5204 }
5205
5206 /* Set the symmetric hash enable configurations per port */
5207 static void
5208 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5209 {
5210         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5211
5212         if (enable > 0) {
5213                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5214                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5215                                                         "been enabled");
5216                         return;
5217                 }
5218                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5219         } else {
5220                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5221                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5222                                                         "been disabled");
5223                         return;
5224                 }
5225                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5226         }
5227         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5228         I40E_WRITE_FLUSH(hw);
5229 }
5230
5231 /*
5232  * Get global configurations of hash function type and symmetric hash enable
5233  * per flow type (pctype). Note that global configuration means it affects all
5234  * the ports on the same NIC.
5235  */
5236 static int
5237 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5238                                    struct rte_eth_hash_global_conf *g_cfg)
5239 {
5240         uint32_t reg, mask = I40E_FLOW_TYPES;
5241         uint16_t i;
5242         enum i40e_filter_pctype pctype;
5243
5244         memset(g_cfg, 0, sizeof(*g_cfg));
5245         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5246         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5247                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5248         else
5249                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5250         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5251                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5252
5253         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5254                 if (!(mask & (1UL << i)))
5255                         continue;
5256                 mask &= ~(1UL << i);
5257                 /* Bit set indicats the coresponding flow type is supported */
5258                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5259                 pctype = i40e_flowtype_to_pctype(i);
5260                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5261                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5262                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5263         }
5264
5265         return 0;
5266 }
5267
5268 static int
5269 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5270 {
5271         uint32_t i;
5272         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5273
5274         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5275                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5276                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5277                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5278                                                 g_cfg->hash_func);
5279                 return -EINVAL;
5280         }
5281
5282         /*
5283          * As i40e supports less than 32 flow types, only first 32 bits need to
5284          * be checked.
5285          */
5286         mask0 = g_cfg->valid_bit_mask[0];
5287         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5288                 if (i == 0) {
5289                         /* Check if any unsupported flow type configured */
5290                         if ((mask0 | i40e_mask) ^ i40e_mask)
5291                                 goto mask_err;
5292                 } else {
5293                         if (g_cfg->valid_bit_mask[i])
5294                                 goto mask_err;
5295                 }
5296         }
5297
5298         return 0;
5299
5300 mask_err:
5301         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5302
5303         return -EINVAL;
5304 }
5305
5306 /*
5307  * Set global configurations of hash function type and symmetric hash enable
5308  * per flow type (pctype). Note any modifying global configuration will affect
5309  * all the ports on the same NIC.
5310  */
5311 static int
5312 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5313                                    struct rte_eth_hash_global_conf *g_cfg)
5314 {
5315         int ret;
5316         uint16_t i;
5317         uint32_t reg;
5318         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5319         enum i40e_filter_pctype pctype;
5320
5321         /* Check the input parameters */
5322         ret = i40e_hash_global_config_check(g_cfg);
5323         if (ret < 0)
5324                 return ret;
5325
5326         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5327                 if (!(mask0 & (1UL << i)))
5328                         continue;
5329                 mask0 &= ~(1UL << i);
5330                 pctype = i40e_flowtype_to_pctype(i);
5331                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5332                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5333                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5334         }
5335
5336         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5337         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5338                 /* Toeplitz */
5339                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5340                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5341                                                                 "Toeplitz");
5342                         goto out;
5343                 }
5344                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5345         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5346                 /* Simple XOR */
5347                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5348                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5349                                                         "Simple XOR");
5350                         goto out;
5351                 }
5352                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5353         } else
5354                 /* Use the default, and keep it as it is */
5355                 goto out;
5356
5357         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5358
5359 out:
5360         I40E_WRITE_FLUSH(hw);
5361
5362         return 0;
5363 }
5364
5365 static int
5366 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5367 {
5368         int ret = 0;
5369
5370         if (!hw || !info) {
5371                 PMD_DRV_LOG(ERR, "Invalid pointer");
5372                 return -EFAULT;
5373         }
5374
5375         switch (info->info_type) {
5376         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5377                 i40e_get_symmetric_hash_enable_per_port(hw,
5378                                         &(info->info.enable));
5379                 break;
5380         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5381                 ret = i40e_get_hash_filter_global_config(hw,
5382                                 &(info->info.global_conf));
5383                 break;
5384         default:
5385                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5386                                                         info->info_type);
5387                 ret = -EINVAL;
5388                 break;
5389         }
5390
5391         return ret;
5392 }
5393
5394 static int
5395 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5396 {
5397         int ret = 0;
5398
5399         if (!hw || !info) {
5400                 PMD_DRV_LOG(ERR, "Invalid pointer");
5401                 return -EFAULT;
5402         }
5403
5404         switch (info->info_type) {
5405         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5406                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5407                 break;
5408         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5409                 ret = i40e_set_hash_filter_global_config(hw,
5410                                 &(info->info.global_conf));
5411                 break;
5412         default:
5413                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5414                                                         info->info_type);
5415                 ret = -EINVAL;
5416                 break;
5417         }
5418
5419         return ret;
5420 }
5421
5422 /* Operations for hash function */
5423 static int
5424 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5425                       enum rte_filter_op filter_op,
5426                       void *arg)
5427 {
5428         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5429         int ret = 0;
5430
5431         switch (filter_op) {
5432         case RTE_ETH_FILTER_NOP:
5433                 break;
5434         case RTE_ETH_FILTER_GET:
5435                 ret = i40e_hash_filter_get(hw,
5436                         (struct rte_eth_hash_filter_info *)arg);
5437                 break;
5438         case RTE_ETH_FILTER_SET:
5439                 ret = i40e_hash_filter_set(hw,
5440                         (struct rte_eth_hash_filter_info *)arg);
5441                 break;
5442         default:
5443                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5444                                                                 filter_op);
5445                 ret = -ENOTSUP;
5446                 break;
5447         }
5448
5449         return ret;
5450 }
5451
5452 /*
5453  * Configure ethertype filter, which can director packet by filtering
5454  * with mac address and ether_type or only ether_type
5455  */
5456 static int
5457 i40e_ethertype_filter_set(struct i40e_pf *pf,
5458                         struct rte_eth_ethertype_filter *filter,
5459                         bool add)
5460 {
5461         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5462         struct i40e_control_filter_stats stats;
5463         uint16_t flags = 0;
5464         int ret;
5465
5466         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5467                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5468                 return -EINVAL;
5469         }
5470         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5471                 filter->ether_type == ETHER_TYPE_IPv6) {
5472                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5473                         " control packet filter.", filter->ether_type);
5474                 return -EINVAL;
5475         }
5476         if (filter->ether_type == ETHER_TYPE_VLAN)
5477                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5478                         " not supported.");
5479
5480         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5481                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5482         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5483                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5484         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5485
5486         memset(&stats, 0, sizeof(stats));
5487         ret = i40e_aq_add_rem_control_packet_filter(hw,
5488                         filter->mac_addr.addr_bytes,
5489                         filter->ether_type, flags,
5490                         pf->main_vsi->seid,
5491                         filter->queue, add, &stats, NULL);
5492
5493         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5494                          " mac_etype_used = %u, etype_used = %u,"
5495                          " mac_etype_free = %u, etype_free = %u\n",
5496                          ret, stats.mac_etype_used, stats.etype_used,
5497                          stats.mac_etype_free, stats.etype_free);
5498         if (ret < 0)
5499                 return -ENOSYS;
5500         return 0;
5501 }
5502
5503 /*
5504  * Handle operations for ethertype filter.
5505  */
5506 static int
5507 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5508                                 enum rte_filter_op filter_op,
5509                                 void *arg)
5510 {
5511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5512         int ret = 0;
5513
5514         if (filter_op == RTE_ETH_FILTER_NOP)
5515                 return ret;
5516
5517         if (arg == NULL) {
5518                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5519                             filter_op);
5520                 return -EINVAL;
5521         }
5522
5523         switch (filter_op) {
5524         case RTE_ETH_FILTER_ADD:
5525                 ret = i40e_ethertype_filter_set(pf,
5526                         (struct rte_eth_ethertype_filter *)arg,
5527                         TRUE);
5528                 break;
5529         case RTE_ETH_FILTER_DELETE:
5530                 ret = i40e_ethertype_filter_set(pf,
5531                         (struct rte_eth_ethertype_filter *)arg,
5532                         FALSE);
5533                 break;
5534         default:
5535                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5536                 ret = -ENOSYS;
5537                 break;
5538         }
5539         return ret;
5540 }
5541
5542 static int
5543 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5544                      enum rte_filter_type filter_type,
5545                      enum rte_filter_op filter_op,
5546                      void *arg)
5547 {
5548         int ret = 0;
5549
5550         if (dev == NULL)
5551                 return -EINVAL;
5552
5553         switch (filter_type) {
5554         case RTE_ETH_FILTER_HASH:
5555                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5556                 break;
5557         case RTE_ETH_FILTER_MACVLAN:
5558                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5559                 break;
5560         case RTE_ETH_FILTER_ETHERTYPE:
5561                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5562                 break;
5563         case RTE_ETH_FILTER_TUNNEL:
5564                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5565                 break;
5566         case RTE_ETH_FILTER_FDIR:
5567                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5568                 break;
5569         default:
5570                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5571                                                         filter_type);
5572                 ret = -EINVAL;
5573                 break;
5574         }
5575
5576         return ret;
5577 }
5578
5579 /*
5580  * As some registers wouldn't be reset unless a global hardware reset,
5581  * hardware initialization is needed to put those registers into an
5582  * expected initial state.
5583  */
5584 static void
5585 i40e_hw_init(struct i40e_hw *hw)
5586 {
5587         /* clear the PF Queue Filter control register */
5588         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5589
5590         /* Disable symmetric hash per port */
5591         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5592 }
5593
5594 enum i40e_filter_pctype
5595 i40e_flowtype_to_pctype(uint16_t flow_type)
5596 {
5597         static const enum i40e_filter_pctype pctype_table[] = {
5598                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5599                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5600                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5601                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5602                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5603                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5604                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5605                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5606                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5607                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5608                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5609                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5610                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5611                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5612                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5613                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5614                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5615                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5616                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5617         };
5618
5619         return pctype_table[flow_type];
5620 }
5621
5622 uint16_t
5623 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5624 {
5625         static const uint16_t flowtype_table[] = {
5626                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5627                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5628                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5629                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5630                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5631                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5632                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5633                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5634                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5635                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5636                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5637                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5638                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5639                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5640                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5641                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5642                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5643                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5644                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5645         };
5646
5647         return flowtype_table[pctype];
5648 }
5649
5650 static int
5651 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5652 {
5653         struct i40e_aq_desc desc;
5654         enum i40e_status_code status;
5655
5656         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5657         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5658         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5659         if (status < 0)
5660                 return status;
5661
5662         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5663                                         (CHAR_BIT * sizeof(uint32_t))) +
5664                                 rte_le_to_cpu_32(desc.params.internal.param3);
5665
5666         return status;
5667 }
5668
5669 /*
5670  * On X710, performance number is far from the expectation on recent firmware
5671  * versions; on XL710, performance number is also far from the expectation on
5672  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5673  * mode is enabled and port MAC address is equal to the packet destination MAC
5674  * address. The fix for this issue may not be integrated in the following
5675  * firmware version. So the workaround in software driver is needed. It needs
5676  * to modify the initial values of 3 internal only registers for both X710 and
5677  * XL710. Note that the values for X710 or XL710 could be different, and the
5678  * workaround can be removed when it is fixed in firmware in the future.
5679  */
5680
5681 /* For both X710 and XL710 */
5682 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5683 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5684
5685 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5686 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5687
5688 /* For X710 */
5689 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5690 /* For XL710 */
5691 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5692 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5693
5694 static void
5695 i40e_configure_registers(struct i40e_hw *hw)
5696 {
5697         static struct {
5698                 uint32_t addr;
5699                 uint64_t val;
5700         } reg_table[] = {
5701                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5702                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5703                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5704         };
5705         uint64_t reg;
5706         uint32_t i;
5707         int ret;
5708
5709         for (i = 0; i < RTE_DIM(reg_table); i++) {
5710                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5711                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5712                                 reg_table[i].val =
5713                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5714                         else /* For X710 */
5715                                 reg_table[i].val =
5716                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5717                 }
5718
5719                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5720                 if (ret < 0) {
5721                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5722                                                         reg_table[i].addr);
5723                         break;
5724                 }
5725                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5726                                                 reg_table[i].addr, reg);
5727                 if (reg == reg_table[i].val)
5728                         continue;
5729
5730                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5731                                                 reg_table[i].val, NULL);
5732                 if (ret < 0) {
5733                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5734                                 "address of 0x%"PRIx32, reg_table[i].val,
5735                                                         reg_table[i].addr);
5736                         break;
5737                 }
5738                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5739                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5740         }
5741 }