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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #define I40E_AQ_LEN 32
40 #define I40E_AQ_BUF_SZ 4096
41 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
42 #define I40E_MAX_Q_PER_TC 64
43 #define I40E_NUM_DESC_DEFAULT 512
44 #define I40E_NUM_DESC_ALIGN 32
45 #define I40E_BUF_SIZE_MIN 1024
46 #define I40E_FRAME_SIZE_MAX 9728
47 #define I40E_QUEUE_BASE_ADDR_UNIT 128
48 /* number of VSIs and queue default setting */
49 #define I40E_MAX_QP_NUM_PER_VF 16
50 #define I40E_DEFAULT_QP_NUM_FDIR 1
51 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
52 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
54 * vlan_id is a 12 bit number.
55 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
56 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
57 * The higher 7 bit val specifies VFTA array index.
59 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
60 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
62 /* Default TC traffic in case DCB is not enabled */
63 #define I40E_DEFAULT_TCMAP 0x1
64 #define I40E_FDIR_QUEUE_ID 0
66 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
67 #define I40E_VMDQ_POOL_BASE 1
69 #define I40E_DEFAULT_RX_FREE_THRESH 32
70 #define I40E_DEFAULT_RX_PTHRESH 8
71 #define I40E_DEFAULT_RX_HTHRESH 8
72 #define I40E_DEFAULT_RX_WTHRESH 0
74 #define I40E_DEFAULT_TX_FREE_THRESH 32
75 #define I40E_DEFAULT_TX_PTHRESH 32
76 #define I40E_DEFAULT_TX_HTHRESH 0
77 #define I40E_DEFAULT_TX_WTHRESH 0
78 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
80 /* Bit shift and mask */
81 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
82 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
83 #define I40E_8_BIT_WIDTH CHAR_BIT
84 #define I40E_8_BIT_MASK UINT8_MAX
85 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
86 #define I40E_16_BIT_MASK UINT16_MAX
87 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
88 #define I40E_32_BIT_MASK UINT32_MAX
89 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
90 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
92 /* index flex payload per layer */
93 enum i40e_flxpld_layer_idx {
94 I40E_FLXPLD_L2_IDX = 0,
95 I40E_FLXPLD_L3_IDX = 1,
96 I40E_FLXPLD_L4_IDX = 2,
97 I40E_MAX_FLXPLD_LAYER = 3,
99 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
100 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
101 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
102 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
105 #define I40E_FLAG_RSS (1ULL << 0)
106 #define I40E_FLAG_DCB (1ULL << 1)
107 #define I40E_FLAG_VMDQ (1ULL << 2)
108 #define I40E_FLAG_SRIOV (1ULL << 3)
109 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
110 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
111 #define I40E_FLAG_FDIR (1ULL << 6)
112 #define I40E_FLAG_VXLAN (1ULL << 7)
113 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
117 I40E_FLAG_HEADER_SPLIT_DISABLED | \
118 I40E_FLAG_HEADER_SPLIT_ENABLED | \
122 #define I40E_RSS_OFFLOAD_ALL ( \
123 ETH_RSS_FRAG_IPV4 | \
124 ETH_RSS_NONFRAG_IPV4_TCP | \
125 ETH_RSS_NONFRAG_IPV4_UDP | \
126 ETH_RSS_NONFRAG_IPV4_SCTP | \
127 ETH_RSS_NONFRAG_IPV4_OTHER | \
128 ETH_RSS_FRAG_IPV6 | \
129 ETH_RSS_NONFRAG_IPV6_TCP | \
130 ETH_RSS_NONFRAG_IPV6_UDP | \
131 ETH_RSS_NONFRAG_IPV6_SCTP | \
132 ETH_RSS_NONFRAG_IPV6_OTHER | \
135 /* All bits of RSS hash enable */
136 #define I40E_RSS_HENA_ALL ( \
137 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
138 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
139 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
140 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
141 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
143 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
144 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
146 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
147 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
148 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
149 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
150 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
155 * MAC filter structure
157 struct i40e_mac_filter_info {
158 enum rte_mac_filter_type filter_type;
159 struct ether_addr mac_addr;
162 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
164 /* MAC filter list structure */
165 struct i40e_mac_filter {
166 TAILQ_ENTRY(i40e_mac_filter) next;
167 struct i40e_mac_filter_info mac_info;
170 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
174 /* VSI list structure */
175 struct i40e_vsi_list {
176 TAILQ_ENTRY(i40e_vsi_list) list;
177 struct i40e_vsi *vsi;
180 struct i40e_rx_queue;
181 struct i40e_tx_queue;
183 /* Structure that defines a VEB */
185 struct i40e_vsi_list_head head;
186 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
187 uint16_t seid; /* The seid of VEB itself */
188 uint16_t uplink_seid; /* The uplink seid of this VEB */
190 struct i40e_eth_stats stats;
193 /* i40e MACVLAN filter structure */
194 struct i40e_macvlan_filter {
195 struct ether_addr macaddr;
196 enum rte_mac_filter_type filter_type;
201 * Structure that defines a VSI, associated with a adapter.
204 struct i40e_adapter *adapter; /* Backreference to associated adapter */
205 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
207 struct i40e_eth_stats eth_stats_offset;
208 struct i40e_eth_stats eth_stats;
210 * When drivers loaded, only a default main VSI exists. In case new VSI
211 * needs to add, HW needs to know the layout that VSIs are organized.
212 * Besides that, VSI isan element and can't switch packets, which needs
213 * to add new component VEB to perform switching. So, a new VSI needs
214 * to specify the the uplink VSI (Parent VSI) before created. The
215 * uplink VSI will check whether it had a VEB to switch packets. If no,
216 * it will try to create one. Then, uplink VSI will move the new VSI
217 * into its' sib_vsi_list to manage all the downlink VSI.
218 * sib_vsi_list: the VSI list that shared the same uplink VSI.
219 * parent_vsi : the uplink VSI. It's NULL for main VSI.
220 * veb : the VEB associates with the VSI.
222 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
223 struct i40e_vsi *parent_vsi;
224 struct i40e_veb *veb; /* Associated veb, could be null */
226 enum i40e_vsi_type type; /* VSI types */
227 uint16_t vlan_num; /* Total VLAN number */
228 uint16_t mac_num; /* Total mac number */
229 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
230 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
231 /* specific VSI-defined parameters, SRIOV stored the vf_id */
233 uint16_t seid; /* The seid of VSI itself */
234 uint16_t uplink_seid; /* The uplink seid of this VSI */
235 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
236 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
237 uint16_t base_queue; /* The first queue index of this VSI */
239 * The offset to visit VSI related register, assigned by HW when
243 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
244 uint8_t enabled_tc; /* The traffic class enabled */
248 LIST_ENTRY(pool_entry) next;
253 LIST_HEAD(res_list, pool_entry);
255 struct i40e_res_pool_info {
256 uint32_t base; /* Resource start index */
257 uint32_t num_alloc; /* Allocated resource number */
258 uint32_t num_free; /* Total available resource number */
259 struct res_list alloc_list; /* Allocated resource list */
260 struct res_list free_list; /* Available resource list */
264 I40E_VF_INACTIVE = 0,
271 * Structure to store private data for PF host.
275 struct i40e_vsi *vsi;
276 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
277 uint16_t vf_idx; /* VF index in pf->vfs */
278 uint16_t lan_nb_qps; /* Actual queues allocated */
279 uint16_t reset_cnt; /* Total vf reset times */
283 * Structure to store private data for VMDQ instance
285 struct i40e_vmdq_info {
287 struct i40e_vsi *vsi;
291 * Structure to store flex pit for flow diretor.
293 struct i40e_fdir_flex_pit {
294 uint8_t src_offset; /* offset in words from the beginning of payload */
295 uint8_t size; /* size in words */
296 uint8_t dst_offset; /* offset in words of flexible payload */
299 struct i40e_fdir_flex_mask {
300 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
304 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
307 #define I40E_FILTER_PCTYPE_MAX 64
309 * A structure used to define fields of a FDIR related info.
311 struct i40e_fdir_info {
312 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
313 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
314 struct i40e_tx_queue *txq;
315 struct i40e_rx_queue *rxq;
316 void *prg_pkt; /* memory for fdir program packet */
317 uint64_t dma_addr; /* physic address of packet memory*/
319 * the rule how bytes stream is extracted as flexible payload
320 * for each payload layer, the setting can up to three elements
322 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
323 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
327 * Structure to store private data specific for PF instance.
330 struct i40e_adapter *adapter; /* The adapter this PF associate to */
331 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
332 uint16_t mac_seid; /* The seid of the MAC of this PF */
333 uint16_t main_vsi_seid; /* The seid of the main VSI */
334 uint16_t max_num_vsi;
335 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
336 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
338 struct i40e_hw_port_stats stats_offset;
339 struct i40e_hw_port_stats stats;
342 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
343 struct ether_addr dev_addr; /* PF device mac address */
344 uint64_t flags; /* PF featuer flags */
345 /* All kinds of queue pair setting for different VSIs */
346 struct i40e_pf_vf *vfs;
348 /* Each of below queue pairs should be power of 2 since it's the
349 precondition after TC configuration applied */
350 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
351 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
352 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
353 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
354 uint16_t hash_lut_size; /* The size of hash lookup table */
355 /* store VXLAN UDP ports */
356 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
357 uint16_t vxlan_bitmap; /* Vxlan bit mask */
359 /* VMDQ related info */
360 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
361 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
362 struct i40e_vmdq_info *vmdq;
364 struct i40e_fdir_info fdir; /* flow director info */
368 PFMSG_LINK_CHANGE = 0x1,
369 PFMSG_RESET_IMPENDING = 0x2,
370 PFMSG_DRIVER_CLOSE = 0x4,
373 struct i40e_vsi_vlan_pvid_info {
374 uint16_t on; /* Enable or disable pvid */
376 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
378 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
379 * while 'untagged' will reject untagged packets.
387 struct i40e_vf_rx_queues {
388 uint64_t rx_dma_addr;
389 uint32_t rx_ring_len;
393 struct i40e_vf_tx_queues {
394 uint64_t tx_dma_addr;
395 uint32_t tx_ring_len;
399 * Structure to store private data specific for VF instance.
402 struct i40e_adapter *adapter; /* The adapter this VF associate to */
403 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
404 uint16_t num_queue_pairs;
405 uint16_t max_pkt_len; /* Maximum packet length */
406 bool promisc_unicast_enabled;
407 bool promisc_multicast_enabled;
409 uint32_t version_major; /* Major version number */
410 uint32_t version_minor; /* Minor version number */
411 uint16_t promisc_flags; /* Promiscuous setting */
412 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
418 volatile uint32_t pend_cmd; /* pending command not finished yet */
419 u16 pend_msg; /* flags indicates events from pf not handled yet */
422 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
423 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
428 * Structure to store private data for each PF/VF instance.
430 struct i40e_adapter {
431 /* Common for both PF and VF */
433 struct rte_eth_dev *eth_dev;
435 /* Specific for PF or VF */
442 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
443 int i40e_vsi_release(struct i40e_vsi *vsi);
444 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
445 enum i40e_vsi_type type,
446 struct i40e_vsi *uplink_vsi,
447 uint16_t user_param);
448 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
449 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
450 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
451 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
452 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
453 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
454 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
455 void i40e_pf_disable_irq0(struct i40e_hw *hw);
456 void i40e_pf_enable_irq0(struct i40e_hw *hw);
457 int i40e_dev_link_update(struct rte_eth_dev *dev,
458 __rte_unused int wait_to_complete);
459 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
460 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
461 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
462 struct i40e_vsi_vlan_pvid_info *info);
463 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
464 uint64_t i40e_config_hena(uint64_t flags);
465 uint64_t i40e_parse_hena(uint64_t flags);
466 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
467 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
468 int i40e_fdir_setup(struct i40e_pf *pf);
469 const struct rte_memzone *i40e_memzone_reserve(const char *name,
472 int i40e_fdir_configure(struct rte_eth_dev *dev);
473 void i40e_fdir_teardown(struct i40e_pf *pf);
474 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
475 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
476 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
477 enum rte_filter_op filter_op,
480 /* I40E_DEV_PRIVATE_TO */
481 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
482 (&((struct i40e_adapter *)adapter)->pf)
483 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
484 (&((struct i40e_adapter *)adapter)->hw)
485 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
486 ((struct i40e_adapter *)adapter)
488 /* I40EVF_DEV_PRIVATE_TO */
489 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
490 (&((struct i40e_adapter *)adapter)->vf)
492 static inline struct i40e_vsi *
493 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
500 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
501 if (hw->mac.type == I40E_MAC_VF) {
502 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
505 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
509 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
510 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
513 #define I40E_VSI_TO_HW(vsi) \
514 (&(((struct i40e_vsi *)vsi)->adapter->hw))
515 #define I40E_VSI_TO_PF(vsi) \
516 (&(((struct i40e_vsi *)vsi)->adapter->pf))
517 #define I40E_VSI_TO_DEV_DATA(vsi) \
518 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
519 #define I40E_VSI_TO_ETH_DEV(vsi) \
520 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
523 #define I40E_PF_TO_HW(pf) \
524 (&(((struct i40e_pf *)pf)->adapter->hw))
525 #define I40E_PF_TO_ADAPTER(pf) \
526 ((struct i40e_adapter *)pf->adapter)
529 #define I40E_VF_TO_HW(vf) \
530 (&(((struct i40e_vf *)vf)->adapter->hw))
533 i40e_init_adminq_parameter(struct i40e_hw *hw)
535 hw->aq.num_arq_entries = I40E_AQ_LEN;
536 hw->aq.num_asq_entries = I40E_AQ_LEN;
537 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
538 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
541 #define I40E_VALID_FLOW(flow_type) \
542 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
543 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
544 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
545 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
546 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
547 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
548 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
549 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
550 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
551 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
552 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
554 #define I40E_VALID_PCTYPE(pctype) \
555 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
556 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
557 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
558 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
559 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
560 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
561 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
562 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
563 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
564 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
565 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
567 #endif /* _I40E_ETHDEV_H_ */