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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #define I40E_AQ_LEN 32
40 #define I40E_AQ_BUF_SZ 4096
41 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
42 #define I40E_MAX_Q_PER_TC 64
43 #define I40E_NUM_DESC_DEFAULT 512
44 #define I40E_NUM_DESC_ALIGN 32
45 #define I40E_BUF_SIZE_MIN 1024
46 #define I40E_FRAME_SIZE_MAX 9728
47 #define I40E_QUEUE_BASE_ADDR_UNIT 128
48 /* number of VSIs and queue default setting */
49 #define I40E_MAX_QP_NUM_PER_VF 16
50 #define I40E_DEFAULT_QP_NUM_FDIR 1
51 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
52 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
53 /* Default TC traffic in case DCB is not enabled */
54 #define I40E_DEFAULT_TCMAP 0x1
55 #define I40E_FDIR_QUEUE_ID 0
57 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
58 #define I40E_VMDQ_POOL_BASE 1
60 #define I40E_DEFAULT_RX_FREE_THRESH 32
61 #define I40E_DEFAULT_RX_PTHRESH 8
62 #define I40E_DEFAULT_RX_HTHRESH 8
63 #define I40E_DEFAULT_RX_WTHRESH 0
65 #define I40E_DEFAULT_TX_FREE_THRESH 32
66 #define I40E_DEFAULT_TX_PTHRESH 32
67 #define I40E_DEFAULT_TX_HTHRESH 0
68 #define I40E_DEFAULT_TX_WTHRESH 0
69 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
71 /* Bit shift and mask */
72 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
73 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
74 #define I40E_8_BIT_WIDTH CHAR_BIT
75 #define I40E_8_BIT_MASK UINT8_MAX
76 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
77 #define I40E_16_BIT_MASK UINT16_MAX
78 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
79 #define I40E_32_BIT_MASK UINT32_MAX
80 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
81 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
83 /* index flex payload per layer */
84 enum i40e_flxpld_layer_idx {
85 I40E_FLXPLD_L2_IDX = 0,
86 I40E_FLXPLD_L3_IDX = 1,
87 I40E_FLXPLD_L4_IDX = 2,
88 I40E_MAX_FLXPLD_LAYER = 3,
90 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
91 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
92 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
93 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
96 #define I40E_FLAG_RSS (1ULL << 0)
97 #define I40E_FLAG_DCB (1ULL << 1)
98 #define I40E_FLAG_VMDQ (1ULL << 2)
99 #define I40E_FLAG_SRIOV (1ULL << 3)
100 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
101 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
102 #define I40E_FLAG_FDIR (1ULL << 6)
103 #define I40E_FLAG_VXLAN (1ULL << 7)
104 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
108 I40E_FLAG_HEADER_SPLIT_DISABLED | \
109 I40E_FLAG_HEADER_SPLIT_ENABLED | \
113 #define I40E_RSS_OFFLOAD_ALL ( \
114 ETH_RSS_NONF_IPV4_UDP | \
115 ETH_RSS_NONF_IPV4_TCP | \
116 ETH_RSS_NONF_IPV4_SCTP | \
117 ETH_RSS_NONF_IPV4_OTHER | \
118 ETH_RSS_FRAG_IPV4 | \
119 ETH_RSS_NONF_IPV6_UDP | \
120 ETH_RSS_NONF_IPV6_TCP | \
121 ETH_RSS_NONF_IPV6_SCTP | \
122 ETH_RSS_NONF_IPV6_OTHER | \
123 ETH_RSS_FRAG_IPV6 | \
126 /* All bits of RSS hash enable */
127 #define I40E_RSS_HENA_ALL ( \
128 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
129 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
130 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
131 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
132 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
133 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
134 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
135 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
136 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
137 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
138 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
139 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
140 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
141 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
146 * MAC filter structure
148 struct i40e_mac_filter_info {
149 enum rte_mac_filter_type filter_type;
150 struct ether_addr mac_addr;
153 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
155 /* MAC filter list structure */
156 struct i40e_mac_filter {
157 TAILQ_ENTRY(i40e_mac_filter) next;
158 struct i40e_mac_filter_info mac_info;
161 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
165 /* VSI list structure */
166 struct i40e_vsi_list {
167 TAILQ_ENTRY(i40e_vsi_list) list;
168 struct i40e_vsi *vsi;
171 struct i40e_rx_queue;
172 struct i40e_tx_queue;
174 /* Structure that defines a VEB */
176 struct i40e_vsi_list_head head;
177 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
178 uint16_t seid; /* The seid of VEB itself */
179 uint16_t uplink_seid; /* The uplink seid of this VEB */
181 struct i40e_eth_stats stats;
184 /* i40e MACVLAN filter structure */
185 struct i40e_macvlan_filter {
186 struct ether_addr macaddr;
187 enum rte_mac_filter_type filter_type;
192 * Structure that defines a VSI, associated with a adapter.
195 struct i40e_adapter *adapter; /* Backreference to associated adapter */
196 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
198 struct i40e_eth_stats eth_stats_offset;
199 struct i40e_eth_stats eth_stats;
201 * When drivers loaded, only a default main VSI exists. In case new VSI
202 * needs to add, HW needs to know the layout that VSIs are organized.
203 * Besides that, VSI isan element and can't switch packets, which needs
204 * to add new component VEB to perform switching. So, a new VSI needs
205 * to specify the the uplink VSI (Parent VSI) before created. The
206 * uplink VSI will check whether it had a VEB to switch packets. If no,
207 * it will try to create one. Then, uplink VSI will move the new VSI
208 * into its' sib_vsi_list to manage all the downlink VSI.
209 * sib_vsi_list: the VSI list that shared the same uplink VSI.
210 * parent_vsi : the uplink VSI. It's NULL for main VSI.
211 * veb : the VEB associates with the VSI.
213 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
214 struct i40e_vsi *parent_vsi;
215 struct i40e_veb *veb; /* Associated veb, could be null */
217 enum i40e_vsi_type type; /* VSI types */
218 uint16_t vlan_num; /* Total VLAN number */
219 uint16_t mac_num; /* Total mac number */
220 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
221 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
222 /* specific VSI-defined parameters, SRIOV stored the vf_id */
224 uint16_t seid; /* The seid of VSI itself */
225 uint16_t uplink_seid; /* The uplink seid of this VSI */
226 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
227 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
228 uint16_t base_queue; /* The first queue index of this VSI */
230 * The offset to visit VSI related register, assigned by HW when
234 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
235 uint8_t enabled_tc; /* The traffic class enabled */
239 LIST_ENTRY(pool_entry) next;
244 LIST_HEAD(res_list, pool_entry);
246 struct i40e_res_pool_info {
247 uint32_t base; /* Resource start index */
248 uint32_t num_alloc; /* Allocated resource number */
249 uint32_t num_free; /* Total available resource number */
250 struct res_list alloc_list; /* Allocated resource list */
251 struct res_list free_list; /* Available resource list */
255 I40E_VF_INACTIVE = 0,
262 * Structure to store private data for PF host.
266 struct i40e_vsi *vsi;
267 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
268 uint16_t vf_idx; /* VF index in pf->vfs */
269 uint16_t lan_nb_qps; /* Actual queues allocated */
270 uint16_t reset_cnt; /* Total vf reset times */
274 * Structure to store private data for VMDQ instance
276 struct i40e_vmdq_info {
278 struct i40e_vsi *vsi;
282 * Structure to store flex pit for flow diretor.
284 struct i40e_fdir_flex_pit {
285 uint8_t src_offset; /* offset in words from the beginning of payload */
286 uint8_t size; /* size in words */
287 uint8_t dst_offset; /* offset in words of flexible payload */
290 struct i40e_fdir_flex_mask {
291 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
295 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
298 #define I40E_FILTER_PCTYPE_MAX 64
300 * A structure used to define fields of a FDIR related info.
302 struct i40e_fdir_info {
303 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
304 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
305 struct i40e_tx_queue *txq;
306 struct i40e_rx_queue *rxq;
307 void *prg_pkt; /* memory for fdir program packet */
308 uint64_t dma_addr; /* physic address of packet memory*/
310 * the rule how bytes stream is extracted as flexible payload
311 * for each payload layer, the setting can up to three elements
313 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
314 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
318 * Structure to store private data specific for PF instance.
321 struct i40e_adapter *adapter; /* The adapter this PF associate to */
322 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
323 uint16_t mac_seid; /* The seid of the MAC of this PF */
324 uint16_t main_vsi_seid; /* The seid of the main VSI */
325 uint16_t max_num_vsi;
326 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
327 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
329 struct i40e_hw_port_stats stats_offset;
330 struct i40e_hw_port_stats stats;
333 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
334 struct ether_addr dev_addr; /* PF device mac address */
335 uint64_t flags; /* PF featuer flags */
336 /* All kinds of queue pair setting for different VSIs */
337 struct i40e_pf_vf *vfs;
339 /* Each of below queue pairs should be power of 2 since it's the
340 precondition after TC configuration applied */
341 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
342 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
343 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
344 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
345 uint16_t hash_lut_size; /* The size of hash lookup table */
346 /* store VXLAN UDP ports */
347 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
348 uint16_t vxlan_bitmap; /* Vxlan bit mask */
350 /* VMDQ related info */
351 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
352 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
353 struct i40e_vmdq_info *vmdq;
355 struct i40e_fdir_info fdir; /* flow director info */
359 PFMSG_LINK_CHANGE = 0x1,
360 PFMSG_RESET_IMPENDING = 0x2,
361 PFMSG_DRIVER_CLOSE = 0x4,
364 struct i40e_vsi_vlan_pvid_info {
365 uint16_t on; /* Enable or disable pvid */
367 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
369 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
370 * while 'untagged' will reject untagged packets.
378 struct i40e_vf_rx_queues {
379 uint64_t rx_dma_addr;
380 uint32_t rx_ring_len;
384 struct i40e_vf_tx_queues {
385 uint64_t tx_dma_addr;
386 uint32_t tx_ring_len;
390 * Structure to store private data specific for VF instance.
393 struct i40e_adapter *adapter; /* The adapter this VF associate to */
394 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
395 uint16_t num_queue_pairs;
396 uint16_t max_pkt_len; /* Maximum packet length */
397 bool promisc_unicast_enabled;
398 bool promisc_multicast_enabled;
400 uint32_t version_major; /* Major version number */
401 uint32_t version_minor; /* Minor version number */
402 uint16_t promisc_flags; /* Promiscuous setting */
403 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
409 volatile uint32_t pend_cmd; /* pending command not finished yet */
410 u16 pend_msg; /* flags indicates events from pf not handled yet */
413 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
414 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
419 * Structure to store private data for each PF/VF instance.
421 struct i40e_adapter {
422 /* Common for both PF and VF */
424 struct rte_eth_dev *eth_dev;
426 /* Specific for PF or VF */
433 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
434 int i40e_vsi_release(struct i40e_vsi *vsi);
435 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
436 enum i40e_vsi_type type,
437 struct i40e_vsi *uplink_vsi,
438 uint16_t user_param);
439 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
440 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
441 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
442 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
443 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
444 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
445 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
446 void i40e_pf_disable_irq0(struct i40e_hw *hw);
447 void i40e_pf_enable_irq0(struct i40e_hw *hw);
448 int i40e_dev_link_update(struct rte_eth_dev *dev,
449 __rte_unused int wait_to_complete);
450 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
451 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
452 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
453 struct i40e_vsi_vlan_pvid_info *info);
454 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
455 uint64_t i40e_config_hena(uint64_t flags);
456 uint64_t i40e_parse_hena(uint64_t flags);
457 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
458 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
459 int i40e_fdir_setup(struct i40e_pf *pf);
460 const struct rte_memzone *i40e_memzone_reserve(const char *name,
463 int i40e_fdir_configure(struct rte_eth_dev *dev);
464 void i40e_fdir_teardown(struct i40e_pf *pf);
465 enum i40e_filter_pctype i40e_flowtype_to_pctype(
466 enum rte_eth_flow_type flow_type);
467 enum rte_eth_flow_type i40e_pctype_to_flowtype(
468 enum i40e_filter_pctype pctype);
469 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
470 enum rte_filter_op filter_op,
473 /* I40E_DEV_PRIVATE_TO */
474 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
475 (&((struct i40e_adapter *)adapter)->pf)
476 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
477 (&((struct i40e_adapter *)adapter)->hw)
478 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
479 ((struct i40e_adapter *)adapter)
481 /* I40EVF_DEV_PRIVATE_TO */
482 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
483 (&((struct i40e_adapter *)adapter)->vf)
485 static inline struct i40e_vsi *
486 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
493 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
494 if (hw->mac.type == I40E_MAC_VF) {
495 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
502 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
503 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
506 #define I40E_VSI_TO_HW(vsi) \
507 (&(((struct i40e_vsi *)vsi)->adapter->hw))
508 #define I40E_VSI_TO_PF(vsi) \
509 (&(((struct i40e_vsi *)vsi)->adapter->pf))
510 #define I40E_VSI_TO_DEV_DATA(vsi) \
511 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
512 #define I40E_VSI_TO_ETH_DEV(vsi) \
513 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
516 #define I40E_PF_TO_HW(pf) \
517 (&(((struct i40e_pf *)pf)->adapter->hw))
518 #define I40E_PF_TO_ADAPTER(pf) \
519 ((struct i40e_adapter *)pf->adapter)
522 #define I40E_VF_TO_HW(vf) \
523 (&(((struct i40e_vf *)vf)->adapter->hw))
526 i40e_init_adminq_parameter(struct i40e_hw *hw)
528 hw->aq.num_arq_entries = I40E_AQ_LEN;
529 hw->aq.num_asq_entries = I40E_AQ_LEN;
530 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
531 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
534 #define I40E_VALID_FLOW_TYPE(flow_type) \
535 ((flow_type) == RTE_ETH_FLOW_TYPE_UDPV4 || \
536 (flow_type) == RTE_ETH_FLOW_TYPE_TCPV4 || \
537 (flow_type) == RTE_ETH_FLOW_TYPE_SCTPV4 || \
538 (flow_type) == RTE_ETH_FLOW_TYPE_IPV4_OTHER || \
539 (flow_type) == RTE_ETH_FLOW_TYPE_FRAG_IPV4 || \
540 (flow_type) == RTE_ETH_FLOW_TYPE_UDPV6 || \
541 (flow_type) == RTE_ETH_FLOW_TYPE_TCPV6 || \
542 (flow_type) == RTE_ETH_FLOW_TYPE_SCTPV6 || \
543 (flow_type) == RTE_ETH_FLOW_TYPE_IPV6_OTHER || \
544 (flow_type) == RTE_ETH_FLOW_TYPE_FRAG_IPV6)
546 #define I40E_VALID_PCTYPE(pctype) \
547 ((pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
548 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
549 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
550 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
551 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
552 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
553 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
554 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
555 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
556 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6)
558 #endif /* _I40E_ETHDEV_H_ */