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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #define I40E_AQ_LEN 32
40 #define I40E_AQ_BUF_SZ 4096
41 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
42 #define I40E_MAX_Q_PER_TC 64
43 #define I40E_NUM_DESC_DEFAULT 512
44 #define I40E_NUM_DESC_ALIGN 32
45 #define I40E_BUF_SIZE_MIN 1024
46 #define I40E_FRAME_SIZE_MAX 9728
47 #define I40E_QUEUE_BASE_ADDR_UNIT 128
48 /* number of VSIs and queue default setting */
49 #define I40E_MAX_QP_NUM_PER_VF 16
50 #define I40E_DEFAULT_QP_NUM_FDIR 1
51 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
52 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
53 /* Default TC traffic in case DCB is not enabled */
54 #define I40E_DEFAULT_TCMAP 0x1
55 #define I40E_FDIR_QUEUE_ID 0
57 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
58 #define I40E_VMDQ_POOL_BASE 1
60 #define I40E_DEFAULT_RX_FREE_THRESH 32
61 #define I40E_DEFAULT_RX_PTHRESH 8
62 #define I40E_DEFAULT_RX_HTHRESH 8
63 #define I40E_DEFAULT_RX_WTHRESH 0
65 #define I40E_DEFAULT_TX_FREE_THRESH 32
66 #define I40E_DEFAULT_TX_PTHRESH 32
67 #define I40E_DEFAULT_TX_HTHRESH 0
68 #define I40E_DEFAULT_TX_WTHRESH 0
69 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
71 /* Bit shift and mask */
72 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
73 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
74 #define I40E_8_BIT_WIDTH CHAR_BIT
75 #define I40E_8_BIT_MASK UINT8_MAX
76 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
77 #define I40E_16_BIT_MASK UINT16_MAX
78 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
79 #define I40E_32_BIT_MASK UINT32_MAX
80 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
81 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
83 /* index flex payload per layer */
84 enum i40e_flxpld_layer_idx {
85 I40E_FLXPLD_L2_IDX = 0,
86 I40E_FLXPLD_L3_IDX = 1,
87 I40E_FLXPLD_L4_IDX = 2,
88 I40E_MAX_FLXPLD_LAYER = 3,
90 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
91 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
92 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
95 #define I40E_FLAG_RSS (1ULL << 0)
96 #define I40E_FLAG_DCB (1ULL << 1)
97 #define I40E_FLAG_VMDQ (1ULL << 2)
98 #define I40E_FLAG_SRIOV (1ULL << 3)
99 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
100 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
101 #define I40E_FLAG_FDIR (1ULL << 6)
102 #define I40E_FLAG_VXLAN (1ULL << 7)
103 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
107 I40E_FLAG_HEADER_SPLIT_DISABLED | \
108 I40E_FLAG_HEADER_SPLIT_ENABLED | \
112 #define I40E_RSS_OFFLOAD_ALL ( \
113 ETH_RSS_NONF_IPV4_UDP | \
114 ETH_RSS_NONF_IPV4_TCP | \
115 ETH_RSS_NONF_IPV4_SCTP | \
116 ETH_RSS_NONF_IPV4_OTHER | \
117 ETH_RSS_FRAG_IPV4 | \
118 ETH_RSS_NONF_IPV6_UDP | \
119 ETH_RSS_NONF_IPV6_TCP | \
120 ETH_RSS_NONF_IPV6_SCTP | \
121 ETH_RSS_NONF_IPV6_OTHER | \
122 ETH_RSS_FRAG_IPV6 | \
125 /* All bits of RSS hash enable */
126 #define I40E_RSS_HENA_ALL ( \
127 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
128 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
129 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
130 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
131 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
132 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
133 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
134 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
135 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
136 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
137 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
138 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
139 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
140 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
145 * MAC filter structure
147 struct i40e_mac_filter_info {
148 enum rte_mac_filter_type filter_type;
149 struct ether_addr mac_addr;
152 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
154 /* MAC filter list structure */
155 struct i40e_mac_filter {
156 TAILQ_ENTRY(i40e_mac_filter) next;
157 struct i40e_mac_filter_info mac_info;
160 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
164 /* VSI list structure */
165 struct i40e_vsi_list {
166 TAILQ_ENTRY(i40e_vsi_list) list;
167 struct i40e_vsi *vsi;
170 struct i40e_rx_queue;
171 struct i40e_tx_queue;
173 /* Structure that defines a VEB */
175 struct i40e_vsi_list_head head;
176 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
177 uint16_t seid; /* The seid of VEB itself */
178 uint16_t uplink_seid; /* The uplink seid of this VEB */
180 struct i40e_eth_stats stats;
183 /* i40e MACVLAN filter structure */
184 struct i40e_macvlan_filter {
185 struct ether_addr macaddr;
186 enum rte_mac_filter_type filter_type;
191 * Structure that defines a VSI, associated with a adapter.
194 struct i40e_adapter *adapter; /* Backreference to associated adapter */
195 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
197 struct i40e_eth_stats eth_stats_offset;
198 struct i40e_eth_stats eth_stats;
200 * When drivers loaded, only a default main VSI exists. In case new VSI
201 * needs to add, HW needs to know the layout that VSIs are organized.
202 * Besides that, VSI isan element and can't switch packets, which needs
203 * to add new component VEB to perform switching. So, a new VSI needs
204 * to specify the the uplink VSI (Parent VSI) before created. The
205 * uplink VSI will check whether it had a VEB to switch packets. If no,
206 * it will try to create one. Then, uplink VSI will move the new VSI
207 * into its' sib_vsi_list to manage all the downlink VSI.
208 * sib_vsi_list: the VSI list that shared the same uplink VSI.
209 * parent_vsi : the uplink VSI. It's NULL for main VSI.
210 * veb : the VEB associates with the VSI.
212 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
213 struct i40e_vsi *parent_vsi;
214 struct i40e_veb *veb; /* Associated veb, could be null */
216 enum i40e_vsi_type type; /* VSI types */
217 uint16_t vlan_num; /* Total VLAN number */
218 uint16_t mac_num; /* Total mac number */
219 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
220 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
221 /* specific VSI-defined parameters, SRIOV stored the vf_id */
223 uint16_t seid; /* The seid of VSI itself */
224 uint16_t uplink_seid; /* The uplink seid of this VSI */
225 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
226 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
227 uint16_t base_queue; /* The first queue index of this VSI */
229 * The offset to visit VSI related register, assigned by HW when
233 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
234 uint8_t enabled_tc; /* The traffic class enabled */
238 LIST_ENTRY(pool_entry) next;
243 LIST_HEAD(res_list, pool_entry);
245 struct i40e_res_pool_info {
246 uint32_t base; /* Resource start index */
247 uint32_t num_alloc; /* Allocated resource number */
248 uint32_t num_free; /* Total available resource number */
249 struct res_list alloc_list; /* Allocated resource list */
250 struct res_list free_list; /* Available resource list */
254 I40E_VF_INACTIVE = 0,
261 * Structure to store private data for PF host.
265 struct i40e_vsi *vsi;
266 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
267 uint16_t vf_idx; /* VF index in pf->vfs */
268 uint16_t lan_nb_qps; /* Actual queues allocated */
269 uint16_t reset_cnt; /* Total vf reset times */
273 * Structure to store private data for VMDQ instance
275 struct i40e_vmdq_info {
277 struct i40e_vsi *vsi;
281 * Structure to store flex pit for flow diretor.
283 struct i40e_fdir_flex_pit {
284 uint8_t src_offset; /* offset in words from the beginning of payload */
285 uint8_t size; /* size in words */
286 uint8_t dst_offset; /* offset in words of flexible payload */
289 struct i40e_fdir_flex_mask {
290 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
294 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
297 #define I40E_FILTER_PCTYPE_MAX 64
299 * A structure used to define fields of a FDIR related info.
301 struct i40e_fdir_info {
302 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
303 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
304 struct i40e_tx_queue *txq;
305 struct i40e_rx_queue *rxq;
306 void *prg_pkt; /* memory for fdir program packet */
307 uint64_t dma_addr; /* physic address of packet memory*/
309 * the rule how bytes stream is extracted as flexible payload
310 * for each payload layer, the setting can up to three elements
312 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
313 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
317 * Structure to store private data specific for PF instance.
320 struct i40e_adapter *adapter; /* The adapter this PF associate to */
321 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
322 uint16_t mac_seid; /* The seid of the MAC of this PF */
323 uint16_t main_vsi_seid; /* The seid of the main VSI */
324 uint16_t max_num_vsi;
325 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
326 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
328 struct i40e_hw_port_stats stats_offset;
329 struct i40e_hw_port_stats stats;
332 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
333 struct ether_addr dev_addr; /* PF device mac address */
334 uint64_t flags; /* PF featuer flags */
335 /* All kinds of queue pair setting for different VSIs */
336 struct i40e_pf_vf *vfs;
338 /* Each of below queue pairs should be power of 2 since it's the
339 precondition after TC configuration applied */
340 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
341 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
342 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
343 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
344 uint16_t hash_lut_size; /* The size of hash lookup table */
345 /* store VXLAN UDP ports */
346 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
347 uint16_t vxlan_bitmap; /* Vxlan bit mask */
349 /* VMDQ related info */
350 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
351 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
352 struct i40e_vmdq_info *vmdq;
354 struct i40e_fdir_info fdir; /* flow director info */
358 PFMSG_LINK_CHANGE = 0x1,
359 PFMSG_RESET_IMPENDING = 0x2,
360 PFMSG_DRIVER_CLOSE = 0x4,
363 struct i40e_vsi_vlan_pvid_info {
364 uint16_t on; /* Enable or disable pvid */
366 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
368 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
369 * while 'untagged' will reject untagged packets.
377 struct i40e_vf_rx_queues {
378 uint64_t rx_dma_addr;
379 uint32_t rx_ring_len;
383 struct i40e_vf_tx_queues {
384 uint64_t tx_dma_addr;
385 uint32_t tx_ring_len;
389 * Structure to store private data specific for VF instance.
392 struct i40e_adapter *adapter; /* The adapter this VF associate to */
393 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
394 uint16_t num_queue_pairs;
395 uint16_t max_pkt_len; /* Maximum packet length */
396 bool promisc_unicast_enabled;
397 bool promisc_multicast_enabled;
399 uint32_t version_major; /* Major version number */
400 uint32_t version_minor; /* Minor version number */
401 uint16_t promisc_flags; /* Promiscuous setting */
402 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
408 volatile uint32_t pend_cmd; /* pending command not finished yet */
409 u16 pend_msg; /* flags indicates events from pf not handled yet */
412 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
413 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
418 * Structure to store private data for each PF/VF instance.
420 struct i40e_adapter {
421 /* Common for both PF and VF */
423 struct rte_eth_dev *eth_dev;
425 /* Specific for PF or VF */
432 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
433 int i40e_vsi_release(struct i40e_vsi *vsi);
434 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
435 enum i40e_vsi_type type,
436 struct i40e_vsi *uplink_vsi,
437 uint16_t user_param);
438 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
439 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
440 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
441 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
442 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
443 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
444 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
445 void i40e_pf_disable_irq0(struct i40e_hw *hw);
446 void i40e_pf_enable_irq0(struct i40e_hw *hw);
447 int i40e_dev_link_update(struct rte_eth_dev *dev,
448 __rte_unused int wait_to_complete);
449 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
450 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
451 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
452 struct i40e_vsi_vlan_pvid_info *info);
453 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
454 uint64_t i40e_config_hena(uint64_t flags);
455 uint64_t i40e_parse_hena(uint64_t flags);
456 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
457 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
458 int i40e_fdir_setup(struct i40e_pf *pf);
459 const struct rte_memzone *i40e_memzone_reserve(const char *name,
462 int i40e_fdir_configure(struct rte_eth_dev *dev);
463 void i40e_fdir_teardown(struct i40e_pf *pf);
464 enum i40e_filter_pctype i40e_flowtype_to_pctype(
465 enum rte_eth_flow_type flow_type);
466 enum rte_eth_flow_type i40e_pctype_to_flowtype(
467 enum i40e_filter_pctype pctype);
469 /* I40E_DEV_PRIVATE_TO */
470 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
471 (&((struct i40e_adapter *)adapter)->pf)
472 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
473 (&((struct i40e_adapter *)adapter)->hw)
474 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
475 ((struct i40e_adapter *)adapter)
477 /* I40EVF_DEV_PRIVATE_TO */
478 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
479 (&((struct i40e_adapter *)adapter)->vf)
481 static inline struct i40e_vsi *
482 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
489 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
490 if (hw->mac.type == I40E_MAC_VF) {
491 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
498 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
499 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
502 #define I40E_VSI_TO_HW(vsi) \
503 (&(((struct i40e_vsi *)vsi)->adapter->hw))
504 #define I40E_VSI_TO_PF(vsi) \
505 (&(((struct i40e_vsi *)vsi)->adapter->pf))
506 #define I40E_VSI_TO_DEV_DATA(vsi) \
507 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
508 #define I40E_VSI_TO_ETH_DEV(vsi) \
509 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
512 #define I40E_PF_TO_HW(pf) \
513 (&(((struct i40e_pf *)pf)->adapter->hw))
514 #define I40E_PF_TO_ADAPTER(pf) \
515 ((struct i40e_adapter *)pf->adapter)
518 #define I40E_VF_TO_HW(vf) \
519 (&(((struct i40e_vf *)vf)->adapter->hw))
522 i40e_init_adminq_parameter(struct i40e_hw *hw)
524 hw->aq.num_arq_entries = I40E_AQ_LEN;
525 hw->aq.num_asq_entries = I40E_AQ_LEN;
526 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
527 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
530 #define I40E_VALID_FLOW_TYPE(flow_type) \
531 ((flow_type) == RTE_ETH_FLOW_TYPE_UDPV4 || \
532 (flow_type) == RTE_ETH_FLOW_TYPE_TCPV4 || \
533 (flow_type) == RTE_ETH_FLOW_TYPE_SCTPV4 || \
534 (flow_type) == RTE_ETH_FLOW_TYPE_IPV4_OTHER || \
535 (flow_type) == RTE_ETH_FLOW_TYPE_FRAG_IPV4 || \
536 (flow_type) == RTE_ETH_FLOW_TYPE_UDPV6 || \
537 (flow_type) == RTE_ETH_FLOW_TYPE_TCPV6 || \
538 (flow_type) == RTE_ETH_FLOW_TYPE_SCTPV6 || \
539 (flow_type) == RTE_ETH_FLOW_TYPE_IPV6_OTHER || \
540 (flow_type) == RTE_ETH_FLOW_TYPE_FRAG_IPV6)
542 #define I40E_VALID_PCTYPE(pctype) \
543 ((pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
544 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
545 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
546 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
547 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
548 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
549 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
550 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
551 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
552 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6)
554 #endif /* _I40E_ETHDEV_H_ */