lib/librte_pmd_i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_ip.h>
  48 #include <rte_udp.h>
  49 #include <rte_tcp.h>
  50 #include <rte_sctp.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_type.h"
  54 #include "i40e_ethdev.h"
  55 #include "i40e_rxtx.h"
  56
  57 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  58 #ifndef IPV6_ADDR_LEN
  59 #define IPV6_ADDR_LEN              16
  60 #endif
  61
  62 #define I40E_FDIR_PKT_LEN                   512
  63 #define I40E_FDIR_IP_DEFAULT_LEN            420
  64 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  65 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  66 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  67 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000
  68 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  69 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  70 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  71
  72 /* Wait count and interval for fdir filter programming */
  73 #define I40E_FDIR_WAIT_COUNT       10
  74 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  75
  76 /* Wait count and interval for fdir filter flush */
  77 #define I40E_FDIR_FLUSH_RETRY       50
  78 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  79
  80 #define I40E_COUNTER_PF           2
  81 /* Statistic counter index for one pf */
  82 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  83 #define I40E_MAX_FLX_SOURCE_OFF           480
  84 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  85
  86 #define NONUSE_FLX_PIT_DEST_OFF 63
  87 #define NONUSE_FLX_PIT_FSIZE    1
  88 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  89         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  90                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  91         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  92                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  93         ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
  94                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
  95                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
  96
  97 #define I40E_FDIR_FLOW_TYPES ( \
  98         (1 << RTE_ETH_FLOW_TYPE_UDPV4) | \
  99         (1 << RTE_ETH_FLOW_TYPE_TCPV4) | \
 100         (1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \
 101         (1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
 102         (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
 103         (1 << RTE_ETH_FLOW_TYPE_UDPV6) | \
 104         (1 << RTE_ETH_FLOW_TYPE_TCPV6) | \
 105         (1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \
 106         (1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
 107         (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
 108
 109 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 110
 111 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
 112 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
 113                                      const struct rte_eth_fdir_input *fdir_input,
 114                                      unsigned char *raw_pkt);
 115 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 116                             const struct rte_eth_fdir_filter *filter,
 117                             bool add);
 118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 119                         enum i40e_filter_pctype pctype,
 120                         const struct rte_eth_fdir_filter *filter,
 121                         bool add);
 122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 123 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
 124                            struct rte_eth_fdir_info *fdir);
 125 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
 126                            struct rte_eth_fdir_stats *stat);
 127
 128 static int
 129 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 130 {
 131         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 132         struct i40e_hmc_obj_rxq rx_ctx;
 133         int err = I40E_SUCCESS;
 134
 135         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 136         /* Init the RX queue in hardware */
 137         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 138         rx_ctx.hbuff = 0;
 139         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 140         rx_ctx.qlen = rxq->nb_rx_desc;
 141 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 142         rx_ctx.dsize = 1;
 143 #endif
 144         rx_ctx.dtype = i40e_header_split_none;
 145         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 146         rx_ctx.rxmax = ETHER_MAX_LEN;
 147         rx_ctx.tphrdesc_ena = 1;
 148         rx_ctx.tphwdesc_ena = 1;
 149         rx_ctx.tphdata_ena = 1;
 150         rx_ctx.tphhead_ena = 1;
 151         rx_ctx.lrxqthresh = 2;
 152         rx_ctx.crcstrip = 0;
 153         rx_ctx.l2tsel = 1;
 154         rx_ctx.showiv = 1;
 155         rx_ctx.prefena = 1;
 156
 157         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 158         if (err != I40E_SUCCESS) {
 159                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 160                 return err;
 161         }
 162         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 163         if (err != I40E_SUCCESS) {
 164                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 165                 return err;
 166         }
 167         rxq->qrx_tail = hw->hw_addr +
 168                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 169
 170         rte_wmb();
 171         /* Init the RX tail regieter. */
 172         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 173         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 174
 175         return err;
 176 }
 177
 178 /*
 179  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 180  * @pf: board private structure
 181  */
 182 int
 183 i40e_fdir_setup(struct i40e_pf *pf)
 184 {
 185         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 186         struct i40e_vsi *vsi;
 187         int err = I40E_SUCCESS;
 188         char z_name[RTE_MEMZONE_NAMESIZE];
 189         const struct rte_memzone *mz = NULL;
 190         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 191
 192         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 193                         " num_filters_best_effort = %u.",
 194                         hw->func_caps.fd_filters_guaranteed,
 195                         hw->func_caps.fd_filters_best_effort);
 196
 197         vsi = pf->fdir.fdir_vsi;
 198         if (vsi) {
 199                 PMD_DRV_LOG(ERR, "FDIR vsi pointer needs "
 200                                  "to be null before creation.");
 201                 return I40E_ERR_BAD_PTR;
 202         }
 203         /* make new FDIR VSI */
 204         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 205         if (!vsi) {
 206                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 207                 return I40E_ERR_NO_AVAILABLE_VSI;
 208         }
 209         pf->fdir.fdir_vsi = vsi;
 210
 211         /*Fdir tx queue setup*/
 212         err = i40e_fdir_setup_tx_resources(pf);
 213         if (err) {
 214                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 215                 goto fail_setup_tx;
 216         }
 217
 218         /*Fdir rx queue setup*/
 219         err = i40e_fdir_setup_rx_resources(pf);
 220         if (err) {
 221                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 222                 goto fail_setup_rx;
 223         }
 224
 225         err = i40e_tx_queue_init(pf->fdir.txq);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 228                 goto fail_mem;
 229         }
 230
 231         /* need switch on before dev start*/
 232         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 233         if (err) {
 234                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 235                 goto fail_mem;
 236         }
 237
 238         /* Init the rx queue in hardware */
 239         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 240         if (err) {
 241                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 242                 goto fail_mem;
 243         }
 244
 245         /* switch on rx queue */
 246         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 247         if (err) {
 248                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 249                 goto fail_mem;
 250         }
 251
 252         /* reserve memory for the fdir programming packet */
 253         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 254                         eth_dev->driver->pci_drv.name,
 255                         I40E_FDIR_MZ_NAME,
 256                         eth_dev->data->port_id);
 257         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 258         if (!mz) {
 259                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 260                                  "flow director program packet.");
 261                 err = I40E_ERR_NO_MEMORY;
 262                 goto fail_mem;
 263         }
 264         pf->fdir.prg_pkt = mz->addr;
 265 #ifdef RTE_LIBRTE_XEN_DOM0
 266         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 267 #else
 268         pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
 269 #endif
 270         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 271         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 272                     vsi->base_queue);
 273         return I40E_SUCCESS;
 274
 275 fail_mem:
 276         i40e_dev_rx_queue_release(pf->fdir.rxq);
 277         pf->fdir.rxq = NULL;
 278 fail_setup_rx:
 279         i40e_dev_tx_queue_release(pf->fdir.txq);
 280         pf->fdir.txq = NULL;
 281 fail_setup_tx:
 282         i40e_vsi_release(vsi);
 283         pf->fdir.fdir_vsi = NULL;
 284         return err;
 285 }
 286
 287 /*
 288  * i40e_fdir_teardown - release the Flow Director resources
 289  * @pf: board private structure
 290  */
 291 void
 292 i40e_fdir_teardown(struct i40e_pf *pf)
 293 {
 294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 295         struct i40e_vsi *vsi;
 296
 297         vsi = pf->fdir.fdir_vsi;
 298         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 299         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 300         i40e_dev_rx_queue_release(pf->fdir.rxq);
 301         pf->fdir.rxq = NULL;
 302         i40e_dev_tx_queue_release(pf->fdir.txq);
 303         pf->fdir.txq = NULL;
 304         i40e_vsi_release(vsi);
 305         pf->fdir.fdir_vsi = NULL;
 306 }
 307
 308 /* check whether the flow director table in empty */
 309 static inline int
 310 i40e_fdir_empty(struct i40e_hw *hw)
 311 {
 312         uint32_t guarant_cnt, best_cnt;
 313
 314         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 315                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 316                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 317         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 318                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 319                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 320         if (best_cnt + guarant_cnt > 0)
 321                 return -1;
 322
 323         return 0;
 324 }
 325
 326 /*
 327  * Initialize the configuration about bytes stream extracted as flexible payload
 328  * and mask setting
 329  */
 330 static inline void
 331 i40e_init_flx_pld(struct i40e_pf *pf)
 332 {
 333         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 334         uint8_t pctype;
 335         int i, index;
 336
 337         /*
 338          * Define the bytes stream extracted as flexible payload in
 339          * field vector. By default, select 8 words from the beginning
 340          * of payload as flexible payload.
 341          */
 342         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 343                 index = i * I40E_MAX_FLXPLD_FIED;
 344                 pf->fdir.flex_set[index].src_offset = 0;
 345                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 346                 pf->fdir.flex_set[index].dst_offset = 0;
 347                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 348                 I40E_WRITE_REG(hw,
 349                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 350                 I40E_WRITE_REG(hw,
 351                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 352         }
 353
 354         /* initialize the masks */
 355         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 356              pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
 357                 pf->fdir.flex_mask[pctype].word_mask = 0;
 358                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 359                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 360                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 361                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 362                         I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 363                 }
 364         }
 365 }
 366
 367 /*
 368  * Configure flow director related setting
 369  */
 370 int
 371 i40e_fdir_configure(struct rte_eth_dev *dev)
 372 {
 373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 375         uint32_t val;
 376         int ret = 0;
 377
 378         /*
 379         * configuration need to be done before
 380         * flow director filters are added
 381         * If filters exist, flush them.
 382         */
 383         if (i40e_fdir_empty(hw) < 0) {
 384                 ret = i40e_fdir_flush(dev);
 385                 if (ret) {
 386                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 387                         return ret;
 388                 }
 389         }
 390
 391         val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
 392         if ((pf->flags & I40E_FLAG_FDIR) &&
 393                 dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 394                 /* enable FDIR filter */
 395                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 396                 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 397
 398                 i40e_init_flx_pld(pf); /* set flex config to default value */
 399         } else {
 400                 /* disable FDIR filter */
 401                 val &= ~I40E_PFQF_CTL_0_FD_ENA_MASK;
 402                 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 403                 pf->flags &= ~I40E_FLAG_FDIR;
 404         }
 405
 406         return ret;
 407 }
 408
 409 static inline void
 410 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 411                                unsigned char *raw_pkt)
 412 {
 413         struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
 414         struct ipv4_hdr *ip;
 415         struct ipv6_hdr *ip6;
 416         static const uint8_t next_proto[] = {
 417                 [RTE_ETH_FLOW_TYPE_UDPV4] = IPPROTO_UDP,
 418                 [RTE_ETH_FLOW_TYPE_TCPV4] = IPPROTO_TCP,
 419                 [RTE_ETH_FLOW_TYPE_SCTPV4] = IPPROTO_SCTP,
 420                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] = IPPROTO_IP,
 421                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] = IPPROTO_IP,
 422                 [RTE_ETH_FLOW_TYPE_UDPV6] = IPPROTO_UDP,
 423                 [RTE_ETH_FLOW_TYPE_TCPV6] = IPPROTO_TCP,
 424                 [RTE_ETH_FLOW_TYPE_SCTPV6] = IPPROTO_SCTP,
 425                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] = IPPROTO_NONE,
 426                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] = IPPROTO_NONE,
 427         };
 428
 429         switch (fdir_input->flow_type) {
 430         case RTE_ETH_FLOW_TYPE_UDPV4:
 431         case RTE_ETH_FLOW_TYPE_TCPV4:
 432         case RTE_ETH_FLOW_TYPE_SCTPV4:
 433         case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
 434         case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
 435                 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 436
 437                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 438                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 439                 /* set len to by default */
 440                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 441                 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
 442                 /*
 443                  * The source and destination fields in the transmitted packet
 444                  * need to be presented in a reversed order with respect
 445                  * to the expected received packets.
 446                  */
 447                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 448                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 449                 ip->next_proto_id = next_proto[fdir_input->flow_type];
 450                 break;
 451         case RTE_ETH_FLOW_TYPE_UDPV6:
 452         case RTE_ETH_FLOW_TYPE_TCPV6:
 453         case RTE_ETH_FLOW_TYPE_SCTPV6:
 454         case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
 455         case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
 456                 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 457
 458                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 459                 ip6->vtc_flow =
 460                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
 461                 ip6->payload_len =
 462                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 463                 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 464
 465                 /*
 466                  * The source and destination fields in the transmitted packet
 467                  * need to be presented in a reversed order with respect
 468                  * to the expected received packets.
 469                  */
 470                 rte_memcpy(&(ip6->src_addr),
 471                            &(fdir_input->flow.ip6_flow.dst_ip),
 472                            IPV6_ADDR_LEN);
 473                 rte_memcpy(&(ip6->dst_addr),
 474                            &(fdir_input->flow.ip6_flow.src_ip),
 475                            IPV6_ADDR_LEN);
 476                 ip6->proto = next_proto[fdir_input->flow_type];
 477                 break;
 478         default:
 479                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 480                             fdir_input->flow_type);
 481                 break;
 482         }
 483 }
 484
 485
 486 /*
 487  * i40e_fdir_construct_pkt - construct packet based on fields in input
 488  * @pf: board private structure
 489  * @fdir_input: input set of the flow director entry
 490  * @raw_pkt: a packet to be constructed
 491  */
 492 static int
 493 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 494                              const struct rte_eth_fdir_input *fdir_input,
 495                              unsigned char *raw_pkt)
 496 {
 497         unsigned char *payload, *ptr;
 498         struct udp_hdr *udp;
 499         struct tcp_hdr *tcp;
 500         struct sctp_hdr *sctp;
 501         uint8_t size, dst = 0;
 502         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 503
 504         /* fill the ethernet and IP head */
 505         i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
 506
 507         /* fill the L4 head */
 508         switch (fdir_input->flow_type) {
 509         case RTE_ETH_FLOW_TYPE_UDPV4:
 510                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 511                                 sizeof(struct ipv4_hdr));
 512                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 513                 /*
 514                  * The source and destination fields in the transmitted packet
 515                  * need to be presented in a reversed order with respect
 516                  * to the expected received packets.
 517                  */
 518                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 519                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 520                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 521                 break;
 522
 523         case RTE_ETH_FLOW_TYPE_TCPV4:
 524                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 525                                          sizeof(struct ipv4_hdr));
 526                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 527                 /*
 528                  * The source and destination fields in the transmitted packet
 529                  * need to be presented in a reversed order with respect
 530                  * to the expected received packets.
 531                  */
 532                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 533                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 534                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 535                 break;
 536
 537         case RTE_ETH_FLOW_TYPE_SCTPV4:
 538                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 539                                            sizeof(struct ipv4_hdr));
 540                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 541                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 542                 break;
 543
 544         case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
 545         case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
 546                 payload = raw_pkt + sizeof(struct ether_hdr) +
 547                           sizeof(struct ipv4_hdr);
 548                 set_idx = I40E_FLXPLD_L3_IDX;
 549                 break;
 550
 551         case RTE_ETH_FLOW_TYPE_UDPV6:
 552                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 553                                          sizeof(struct ipv6_hdr));
 554                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 555                 /*
 556                  * The source and destination fields in the transmitted packet
 557                  * need to be presented in a reversed order with respect
 558                  * to the expected received packets.
 559                  */
 560                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 561                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 562                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 563                 break;
 564
 565         case RTE_ETH_FLOW_TYPE_TCPV6:
 566                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 567                                          sizeof(struct ipv6_hdr));
 568                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 569                 /*
 570                  * The source and destination fields in the transmitted packet
 571                  * need to be presented in a reversed order with respect
 572                  * to the expected received packets.
 573                  */
 574                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 575                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 576                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 577                 break;
 578
 579         case RTE_ETH_FLOW_TYPE_SCTPV6:
 580                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 581                                            sizeof(struct ipv6_hdr));
 582                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 583                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 584                 break;
 585
 586         case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
 587         case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
 588                 payload = raw_pkt + sizeof(struct ether_hdr) +
 589                           sizeof(struct ipv6_hdr);
 590                 set_idx = I40E_FLXPLD_L3_IDX;
 591                 break;
 592         default:
 593                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 594                 return -EINVAL;
 595         }
 596
 597         /* fill the flexbytes to payload */
 598         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 599                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 600                 size = pf->fdir.flex_set[pit_idx].size;
 601                 if (size == 0)
 602                         continue;
 603                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 604                 ptr = payload +
 605                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 606                 (void)rte_memcpy(ptr,
 607                                  &fdir_input->flow_ext.flexbytes[dst],
 608                                  size * sizeof(uint16_t));
 609         }
 610
 611         return 0;
 612 }
 613
 614 /* Construct the tx flags */
 615 static inline uint64_t
 616 i40e_build_ctob(uint32_t td_cmd,
 617                 uint32_t td_offset,
 618                 unsigned int size,
 619                 uint32_t td_tag)
 620 {
 621         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 622                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 623                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 624                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 625                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 626 }
 627
 628 /*
 629  * check the programming status descriptor in rx queue.
 630  * done after Programming Flow Director is programmed on
 631  * tx queue
 632  */
 633 static inline int
 634 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 635 {
 636         volatile union i40e_rx_desc *rxdp;
 637         uint64_t qword1;
 638         uint32_t rx_status;
 639         uint32_t len, id;
 640         uint32_t error;
 641         int ret = 0;
 642
 643         rxdp = &rxq->rx_ring[rxq->rx_tail];
 644         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 645         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 646                         >> I40E_RXD_QW1_STATUS_SHIFT;
 647
 648         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 649                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 650                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 651                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 652
 653                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 654                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 655                         error = (qword1 &
 656                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 657                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 658                         if (error == (0x1 <<
 659                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 660                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 661                                             " (FD_ID %u): programming status"
 662                                             " reported.",
 663                                             rxdp->wb.qword0.hi_dword.fd_id);
 664                                 ret = -1;
 665                         } else if (error == (0x1 <<
 666                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 667                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 668                                             " (FD_ID %u): programming status"
 669                                             " reported.",
 670                                             rxdp->wb.qword0.hi_dword.fd_id);
 671                                 ret = -1;
 672                         } else
 673                                 PMD_DRV_LOG(ERR, "invalid programming status"
 674                                             " reported, error = %u.", error);
 675                 } else
 676                         PMD_DRV_LOG(ERR, "unknown programming status"
 677                                     " reported, len = %d, id = %u.", len, id);
 678                 rxdp->wb.qword1.status_error_len = 0;
 679                 rxq->rx_tail++;
 680                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 681                         rxq->rx_tail = 0;
 682         }
 683         return ret;
 684 }
 685
 686 /*
 687  * i40e_add_del_fdir_filter - add or remove a flow director filter.
 688  * @pf: board private structure
 689  * @filter: fdir filter entry
 690  * @add: 0 - delete, 1 - add
 691  */
 692 static int
 693 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 694                             const struct rte_eth_fdir_filter *filter,
 695                             bool add)
 696 {
 697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 698         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
 699         enum i40e_filter_pctype pctype;
 700         int ret = 0;
 701
 702         if (!(pf->flags & I40E_FLAG_FDIR)) {
 703                 PMD_DRV_LOG(ERR, "FDIR is not enabled.");
 704                 return -ENOTSUP;
 705         }
 706         if (!I40E_VALID_FLOW_TYPE(filter->input.flow_type)) {
 707                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
 708                 return -EINVAL;
 709         }
 710         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
 711                 PMD_DRV_LOG(ERR, "Invalid queue ID");
 712                 return -EINVAL;
 713         }
 714
 715         memset(pkt, 0, I40E_FDIR_PKT_LEN);
 716
 717         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
 718         if (ret < 0) {
 719                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
 720                 return ret;
 721         }
 722         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
 723         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
 724         if (ret < 0) {
 725                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
 726                             pctype);
 727                 return ret;
 728         }
 729         return ret;
 730 }
 731
 732 /*
 733  * i40e_fdir_filter_programming - Program a flow director filter rule.
 734  * Is done by Flow Director Programming Descriptor followed by packet
 735  * structure that contains the filter fields need to match.
 736  * @pf: board private structure
 737  * @pctype: pctype
 738  * @filter: fdir filter entry
 739  * @add: 0 - delelet, 1 - add
 740  */
 741 static int
 742 i40e_fdir_filter_programming(struct i40e_pf *pf,
 743                         enum i40e_filter_pctype pctype,
 744                         const struct rte_eth_fdir_filter *filter,
 745                         bool add)
 746 {
 747         struct i40e_tx_queue *txq = pf->fdir.txq;
 748         struct i40e_rx_queue *rxq = pf->fdir.rxq;
 749         const struct rte_eth_fdir_action *fdir_action = &filter->action;
 750         volatile struct i40e_tx_desc *txdp;
 751         volatile struct i40e_filter_program_desc *fdirdp;
 752         uint32_t td_cmd;
 753         uint16_t i;
 754         uint8_t dest;
 755
 756         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
 757         fdirdp = (volatile struct i40e_filter_program_desc *)
 758                         (&(txq->tx_ring[txq->tx_tail]));
 759
 760         fdirdp->qindex_flex_ptype_vsi =
 761                         rte_cpu_to_le_32((fdir_action->rx_queue <<
 762                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
 763                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
 764
 765         fdirdp->qindex_flex_ptype_vsi |=
 766                         rte_cpu_to_le_32((fdir_action->flex_off <<
 767                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
 768                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
 769
 770         fdirdp->qindex_flex_ptype_vsi |=
 771                         rte_cpu_to_le_32((pctype <<
 772                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
 773                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
 774
 775         /* Use LAN VSI Id by default */
 776         fdirdp->qindex_flex_ptype_vsi |=
 777                 rte_cpu_to_le_32((pf->main_vsi->vsi_id <<
 778                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
 779                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
 780
 781         fdirdp->dtype_cmd_cntindex =
 782                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
 783
 784         if (add)
 785                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
 786                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
 787                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
 788         else
 789                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
 790                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
 791                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
 792
 793         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
 794                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
 795         else
 796                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
 797         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
 798                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
 799                                 I40E_TXD_FLTR_QW1_DEST_MASK);
 800
 801         fdirdp->dtype_cmd_cntindex |=
 802                 rte_cpu_to_le_32((fdir_action->report_status<<
 803                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
 804                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
 805
 806         fdirdp->dtype_cmd_cntindex |=
 807                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
 808         fdirdp->dtype_cmd_cntindex |=
 809                         rte_cpu_to_le_32((pf->fdir.match_counter_index <<
 810                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 811                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
 812
 813         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
 814
 815         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
 816         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
 817         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
 818         td_cmd = I40E_TX_DESC_CMD_EOP |
 819                  I40E_TX_DESC_CMD_RS  |
 820                  I40E_TX_DESC_CMD_DUMMY;
 821
 822         txdp->cmd_type_offset_bsz =
 823                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
 824
 825         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
 826         if (txq->tx_tail >= txq->nb_tx_desc)
 827                 txq->tx_tail = 0;
 828         /* Update the tx tail register */
 829         rte_wmb();
 830         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 831
 832         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
 833                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
 834                 if (txdp->cmd_type_offset_bsz &
 835                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
 836                         break;
 837         }
 838         if (i >= I40E_FDIR_WAIT_COUNT) {
 839                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
 840                             " time out to get DD on tx queue.");
 841                 return -ETIMEDOUT;
 842         }
 843         /* totally delay 10 ms to check programming status*/
 844         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
 845         if (i40e_check_fdir_programming_status(rxq) < 0) {
 846                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
 847                             " programming status reported.");
 848                 return -ENOSYS;
 849         }
 850
 851         return 0;
 852 }
 853
 854 /*
 855  * i40e_fdir_flush - clear all filters of Flow Director table
 856  * @pf: board private structure
 857  */
 858 static int
 859 i40e_fdir_flush(struct rte_eth_dev *dev)
 860 {
 861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 862         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 863         uint32_t reg;
 864         uint16_t guarant_cnt, best_cnt;
 865         uint16_t i;
 866
 867         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
 868         I40E_WRITE_FLUSH(hw);
 869
 870         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
 871                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
 872                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
 873                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
 874                         break;
 875         }
 876         if (i >= I40E_FDIR_FLUSH_RETRY) {
 877                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
 878                 return -ETIMEDOUT;
 879         }
 880         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 881                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 882                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 883         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 884                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 885                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 886         if (guarant_cnt != 0 || best_cnt != 0) {
 887                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
 888                 return -ENOSYS;
 889         } else
 890                 PMD_DRV_LOG(INFO, "FD table Flush success.");
 891         return 0;
 892 }
 893
 894 static inline void
 895 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
 896                         struct rte_eth_flex_payload_cfg *flex_set,
 897                         uint16_t *num)
 898 {
 899         struct i40e_fdir_flex_pit *flex_pit;
 900         struct rte_eth_flex_payload_cfg *ptr = flex_set;
 901         uint16_t src, dst, size, j, k;
 902         uint8_t i, layer_idx;
 903
 904         for (layer_idx = I40E_FLXPLD_L2_IDX;
 905              layer_idx <= I40E_FLXPLD_L4_IDX;
 906              layer_idx++) {
 907                 if (layer_idx == I40E_FLXPLD_L2_IDX)
 908                         ptr->type = RTE_ETH_L2_PAYLOAD;
 909                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
 910                         ptr->type = RTE_ETH_L3_PAYLOAD;
 911                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
 912                         ptr->type = RTE_ETH_L4_PAYLOAD;
 913
 914                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 915                         flex_pit = &pf->fdir.flex_set[layer_idx *
 916                                 I40E_MAX_FLXPLD_FIED + i];
 917                         if (flex_pit->size == 0)
 918                                 continue;
 919                         src = flex_pit->src_offset * sizeof(uint16_t);
 920                         dst = flex_pit->dst_offset * sizeof(uint16_t);
 921                         size = flex_pit->size * sizeof(uint16_t);
 922                         for (j = src, k = dst; j < src + size; j++, k++)
 923                                 ptr->src_offset[k] = j;
 924                 }
 925                 (*num)++;
 926                 ptr++;
 927         }
 928 }
 929
 930 static inline void
 931 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
 932                         struct rte_eth_fdir_flex_mask *flex_mask,
 933                         uint16_t *num)
 934 {
 935         struct i40e_fdir_flex_mask *mask;
 936         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
 937         enum rte_eth_flow_type flow_type;
 938         uint8_t i, j;
 939         uint16_t off_bytes, mask_tmp;
 940
 941         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 942              i <= I40E_FILTER_PCTYPE_FRAG_IPV6;
 943              i++) {
 944                 mask =  &pf->fdir.flex_mask[i];
 945                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
 946                         continue;
 947                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
 948                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
 949                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
 950                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
 951                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
 952                         } else {
 953                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
 954                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
 955                         }
 956                 }
 957                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
 958                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
 959                         mask_tmp = ~mask->bitmask[j].mask;
 960                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
 961                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
 962                 }
 963                 ptr->flow_type = flow_type;
 964                 ptr++;
 965                 (*num)++;
 966         }
 967 }
 968
 969 /*
 970  * i40e_fdir_info_get - get information of Flow Director
 971  * @pf: ethernet device to get info from
 972  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
 973  *    the flow director information.
 974  */
 975 static void
 976 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
 977 {
 978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 979         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 980         uint16_t num_flex_set = 0;
 981         uint16_t num_flex_mask = 0;
 982
 983         fdir->mode = (pf->flags & I40E_FLAG_FDIR) ?
 984                         RTE_FDIR_MODE_PERFECT : RTE_FDIR_MODE_NONE;
 985         fdir->guarant_spc =
 986                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
 987         fdir->best_spc =
 988                 (uint32_t)hw->func_caps.fd_filters_best_effort;
 989         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
 990         fdir->flow_types_mask[0] = I40E_FDIR_FLOW_TYPES;
 991         fdir->flex_payload_unit = sizeof(uint16_t);
 992         fdir->flex_bitmask_unit = sizeof(uint16_t);
 993         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
 994         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
 995         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
 996
 997         i40e_fdir_info_get_flex_set(pf,
 998                                 fdir->flex_conf.flex_set,
 999                                 &num_flex_set);
1000         i40e_fdir_info_get_flex_mask(pf,
1001                                 fdir->flex_conf.flex_mask,
1002                                 &num_flex_mask);
1003
1004         fdir->flex_conf.nb_payloads = num_flex_set;
1005         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1006 }
1007
1008 /*
1009  * i40e_fdir_stat_get - get statistics of Flow Director
1010  * @pf: ethernet device to get info from
1011  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1012  *    the flow director statistics.
1013  */
1014 static void
1015 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1016 {
1017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1018         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1019         uint32_t fdstat;
1020
1021         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1022         stat->guarant_cnt =
1023                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1024                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1025         stat->best_cnt =
1026                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1027                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1028 }
1029
1030 /*
1031  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1032  * @pf: board private structure
1033  * @filter_op:operation will be taken.
1034  * @arg: a pointer to specific structure corresponding to the filter_op
1035  */
1036 int
1037 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1038                        enum rte_filter_op filter_op,
1039                        void *arg)
1040 {
1041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042         int ret = 0;
1043
1044         if (filter_op == RTE_ETH_FILTER_NOP) {
1045                 if (!(pf->flags & I40E_FLAG_FDIR))
1046                         ret = -ENOTSUP;
1047                 return ret;
1048         }
1049
1050         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1051                 return -EINVAL;
1052
1053         switch (filter_op) {
1054         case RTE_ETH_FILTER_ADD:
1055                 ret = i40e_add_del_fdir_filter(dev,
1056                         (struct rte_eth_fdir_filter *)arg,
1057                         TRUE);
1058                 break;
1059         case RTE_ETH_FILTER_DELETE:
1060                 ret = i40e_add_del_fdir_filter(dev,
1061                         (struct rte_eth_fdir_filter *)arg,
1062                         FALSE);
1063                 break;
1064         case RTE_ETH_FILTER_FLUSH:
1065                 ret = i40e_fdir_flush(dev);
1066                 break;
1067         case RTE_ETH_FILTER_INFO:
1068                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1069                 break;
1070         case RTE_ETH_FILTER_STATS:
1071                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1072                 break;
1073         default:
1074                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1075                 ret = -EINVAL;
1076                 break;
1077         }
1078         return ret;
1079 }