4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
52 #include "i40e_logs.h"
53 #include "i40e/i40e_type.h"
54 #include "i40e_ethdev.h"
55 #include "i40e_rxtx.h"
57 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
59 #define IPV6_ADDR_LEN 16
62 #define I40E_FDIR_PKT_LEN 512
63 #define I40E_FDIR_IP_DEFAULT_LEN 420
64 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
65 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
66 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
67 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60300000
68 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
69 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
70 #define I40E_FDIR_UDP_DEFAULT_LEN 400
72 /* Wait count and interval for fdir filter programming */
73 #define I40E_FDIR_WAIT_COUNT 10
74 #define I40E_FDIR_WAIT_INTERVAL_US 1000
76 /* Wait count and interval for fdir filter flush */
77 #define I40E_FDIR_FLUSH_RETRY 50
78 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
80 #define I40E_COUNTER_PF 2
81 /* Statistic counter index for one pf */
82 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
83 #define I40E_MAX_FLX_SOURCE_OFF 480
84 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
86 #define NONUSE_FLX_PIT_DEST_OFF 63
87 #define NONUSE_FLX_PIT_FSIZE 1
88 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
89 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
90 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
91 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
92 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
93 ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
94 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
95 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
97 #define I40E_FDIR_FLOWS ( \
98 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
99 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
101 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
102 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
103 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
104 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
106 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
107 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
109 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
111 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
112 static int i40e_check_fdir_flex_conf(
113 const struct rte_eth_fdir_flex_conf *conf);
114 static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,
115 const struct rte_eth_flex_payload_cfg *cfg);
116 static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
117 enum i40e_filter_pctype pctype,
118 const struct rte_eth_fdir_flex_mask *mask_cfg);
119 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
120 const struct rte_eth_fdir_input *fdir_input,
121 unsigned char *raw_pkt);
122 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
123 const struct rte_eth_fdir_filter *filter,
125 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
126 enum i40e_filter_pctype pctype,
127 const struct rte_eth_fdir_filter *filter,
129 static int i40e_fdir_flush(struct rte_eth_dev *dev);
130 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
131 struct rte_eth_fdir_info *fdir);
132 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
133 struct rte_eth_fdir_stats *stat);
136 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
138 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
139 struct i40e_hmc_obj_rxq rx_ctx;
140 int err = I40E_SUCCESS;
142 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
143 /* Init the RX queue in hardware */
144 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
146 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
147 rx_ctx.qlen = rxq->nb_rx_desc;
148 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
151 rx_ctx.dtype = i40e_header_split_none;
152 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
153 rx_ctx.rxmax = ETHER_MAX_LEN;
154 rx_ctx.tphrdesc_ena = 1;
155 rx_ctx.tphwdesc_ena = 1;
156 rx_ctx.tphdata_ena = 1;
157 rx_ctx.tphhead_ena = 1;
158 rx_ctx.lrxqthresh = 2;
164 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
165 if (err != I40E_SUCCESS) {
166 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
169 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
170 if (err != I40E_SUCCESS) {
171 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
174 rxq->qrx_tail = hw->hw_addr +
175 I40E_QRX_TAIL(rxq->vsi->base_queue);
178 /* Init the RX tail regieter. */
179 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
180 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
186 * i40e_fdir_setup - reserve and initialize the Flow Director resources
187 * @pf: board private structure
190 i40e_fdir_setup(struct i40e_pf *pf)
192 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
193 struct i40e_vsi *vsi;
194 int err = I40E_SUCCESS;
195 char z_name[RTE_MEMZONE_NAMESIZE];
196 const struct rte_memzone *mz = NULL;
197 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
199 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
200 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
201 return I40E_NOT_SUPPORTED;
204 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
205 " num_filters_best_effort = %u.",
206 hw->func_caps.fd_filters_guaranteed,
207 hw->func_caps.fd_filters_best_effort);
209 vsi = pf->fdir.fdir_vsi;
211 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
214 /* make new FDIR VSI */
215 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
217 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
218 return I40E_ERR_NO_AVAILABLE_VSI;
220 pf->fdir.fdir_vsi = vsi;
222 /*Fdir tx queue setup*/
223 err = i40e_fdir_setup_tx_resources(pf);
225 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
229 /*Fdir rx queue setup*/
230 err = i40e_fdir_setup_rx_resources(pf);
232 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
236 err = i40e_tx_queue_init(pf->fdir.txq);
238 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
242 /* need switch on before dev start*/
243 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
245 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
249 /* Init the rx queue in hardware */
250 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
252 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
256 /* switch on rx queue */
257 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
259 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
263 /* reserve memory for the fdir programming packet */
264 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
265 eth_dev->driver->pci_drv.name,
267 eth_dev->data->port_id);
268 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
270 PMD_DRV_LOG(ERR, "Cannot init memzone for "
271 "flow director program packet.");
272 err = I40E_ERR_NO_MEMORY;
275 pf->fdir.prg_pkt = mz->addr;
276 #ifdef RTE_LIBRTE_XEN_DOM0
277 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
279 pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
281 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
282 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
287 i40e_dev_rx_queue_release(pf->fdir.rxq);
290 i40e_dev_tx_queue_release(pf->fdir.txq);
293 i40e_vsi_release(vsi);
294 pf->fdir.fdir_vsi = NULL;
299 * i40e_fdir_teardown - release the Flow Director resources
300 * @pf: board private structure
303 i40e_fdir_teardown(struct i40e_pf *pf)
305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
306 struct i40e_vsi *vsi;
308 vsi = pf->fdir.fdir_vsi;
311 i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
312 i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
313 i40e_dev_rx_queue_release(pf->fdir.rxq);
315 i40e_dev_tx_queue_release(pf->fdir.txq);
317 i40e_vsi_release(vsi);
318 pf->fdir.fdir_vsi = NULL;
321 /* check whether the flow director table in empty */
323 i40e_fdir_empty(struct i40e_hw *hw)
325 uint32_t guarant_cnt, best_cnt;
327 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
328 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
329 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
330 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
331 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
332 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
333 if (best_cnt + guarant_cnt > 0)
340 * Initialize the configuration about bytes stream extracted as flexible payload
344 i40e_init_flx_pld(struct i40e_pf *pf)
346 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
351 * Define the bytes stream extracted as flexible payload in
352 * field vector. By default, select 8 words from the beginning
353 * of payload as flexible payload.
355 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
356 index = i * I40E_MAX_FLXPLD_FIED;
357 pf->fdir.flex_set[index].src_offset = 0;
358 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
359 pf->fdir.flex_set[index].dst_offset = 0;
360 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
362 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
364 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
367 /* initialize the masks */
368 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
369 pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
370 pf->fdir.flex_mask[pctype].word_mask = 0;
371 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
372 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
373 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
374 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
375 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
380 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
382 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
383 if ((flex_pit2).src_offset < \
384 (flex_pit1).src_offset + (flex_pit1).size) { \
385 PMD_DRV_LOG(ERR, "src_offset should be not" \
386 " less than than previous offset" \
387 " + previous FSIZE."); \
393 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
394 * and the flex_pit will be sorted by it's src_offset value
396 static inline uint16_t
397 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
398 struct i40e_fdir_flex_pit *flex_pit)
400 uint16_t src_tmp, size, num = 0;
401 uint16_t i, k, j = 0;
403 while (j < I40E_FDIR_MAX_FLEX_LEN) {
405 for (; j < I40E_FDIR_MAX_FLEX_LEN; j++) {
406 if (src_offset[j + 1] == src_offset[j] + 1)
409 src_tmp = src_offset[j] + 1 - size;
410 /* the flex_pit need to be sort by scr_offset */
411 for (i = 0; i < num; i++) {
412 if (src_tmp < flex_pit[i].src_offset)
415 /* if insert required, move backward */
416 for (k = num; k > i; k--)
417 flex_pit[k] = flex_pit[k - 1];
419 flex_pit[i].dst_offset = j + 1 - size;
420 flex_pit[i].src_offset = src_tmp;
421 flex_pit[i].size = size;
431 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
433 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
435 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
438 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
439 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
440 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
445 memset(flex_pit, 0, sizeof(flex_pit));
446 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
447 if (num > I40E_MAX_FLXPLD_FIED) {
448 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
451 for (i = 0; i < num; i++) {
452 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
453 flex_pit[i].src_offset & 0x01) {
454 PMD_DRV_LOG(ERR, "flexpayload should be measured"
459 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
465 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
466 * arguments are valid
469 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
471 const struct rte_eth_flex_payload_cfg *flex_cfg;
472 const struct rte_eth_fdir_flex_mask *flex_mask;
479 PMD_DRV_LOG(INFO, "NULL pointer.");
482 /* check flexible payload setting configuration */
483 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
484 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
487 for (i = 0; i < conf->nb_payloads; i++) {
488 flex_cfg = &conf->flex_set[i];
489 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
490 PMD_DRV_LOG(ERR, "invalid payload type.");
493 ret = i40e_check_fdir_flex_payload(flex_cfg);
495 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
500 /* check flex mask setting configuration */
501 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
502 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
505 for (i = 0; i < conf->nb_flexmasks; i++) {
506 flex_mask = &conf->flex_mask[i];
507 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
508 PMD_DRV_LOG(WARNING, "invalid flow type.");
512 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
513 mask_tmp = I40E_WORD(flex_mask->mask[j],
514 flex_mask->mask[j + 1]);
515 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
517 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
518 PMD_DRV_LOG(ERR, " exceed maximal"
519 " number of bitmasks.");
529 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
530 * @pf: board private structure
531 * @cfg: the rule how bytes stream is extracted as flexible payload
534 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
535 const struct rte_eth_flex_payload_cfg *cfg)
537 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
538 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
540 uint16_t num, min_next_off; /* in words */
541 uint8_t field_idx = 0;
542 uint8_t layer_idx = 0;
545 if (cfg->type == RTE_ETH_L2_PAYLOAD)
546 layer_idx = I40E_FLXPLD_L2_IDX;
547 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
548 layer_idx = I40E_FLXPLD_L3_IDX;
549 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
550 layer_idx = I40E_FLXPLD_L4_IDX;
552 memset(flex_pit, 0, sizeof(flex_pit));
553 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
555 for (i = 0; i < num; i++) {
556 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
557 /* record the info in fdir structure */
558 pf->fdir.flex_set[field_idx].src_offset =
559 flex_pit[i].src_offset / sizeof(uint16_t);
560 pf->fdir.flex_set[field_idx].size =
561 flex_pit[i].size / sizeof(uint16_t);
562 pf->fdir.flex_set[field_idx].dst_offset =
563 flex_pit[i].dst_offset / sizeof(uint16_t);
564 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
565 pf->fdir.flex_set[field_idx].size,
566 pf->fdir.flex_set[field_idx].dst_offset);
568 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
570 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
571 pf->fdir.flex_set[field_idx].size;
573 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
574 /* set the non-used register obeying register's constrain */
575 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
576 NONUSE_FLX_PIT_DEST_OFF);
578 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
585 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
586 * @pf: board private structure
587 * @pctype: packet classify type
588 * @flex_masks: mask for flexible payload
591 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
592 enum i40e_filter_pctype pctype,
593 const struct rte_eth_fdir_flex_mask *mask_cfg)
595 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
596 struct i40e_fdir_flex_mask *flex_mask;
597 uint32_t flxinset, fd_mask;
599 uint8_t i, nb_bitmask = 0;
601 flex_mask = &pf->fdir.flex_mask[pctype];
602 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
603 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
604 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
605 if (mask_tmp != 0x0) {
606 flex_mask->word_mask |=
607 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
608 if (mask_tmp != UINT16_MAX) {
610 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
611 flex_mask->bitmask[nb_bitmask].offset =
612 i / sizeof(uint16_t);
617 /* write mask to hw */
618 flxinset = (flex_mask->word_mask <<
619 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
620 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
621 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
623 for (i = 0; i < nb_bitmask; i++) {
624 fd_mask = (flex_mask->bitmask[i].mask <<
625 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
626 I40E_PRTQF_FD_MSK_MASK_MASK;
627 fd_mask |= ((flex_mask->bitmask[i].offset +
628 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
629 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
630 I40E_PRTQF_FD_MSK_OFFSET_MASK;
631 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
636 * Configure flow director related setting
639 i40e_fdir_configure(struct rte_eth_dev *dev)
641 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
642 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
643 struct rte_eth_fdir_flex_conf *conf;
644 enum i40e_filter_pctype pctype;
650 * configuration need to be done before
651 * flow director filters are added
652 * If filters exist, flush them.
654 if (i40e_fdir_empty(hw) < 0) {
655 ret = i40e_fdir_flush(dev);
657 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
662 /* enable FDIR filter */
663 val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
664 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
665 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
667 i40e_init_flx_pld(pf); /* set flex config to default value */
669 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
670 ret = i40e_check_fdir_flex_conf(conf);
672 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
675 /* configure flex payload */
676 for (i = 0; i < conf->nb_payloads; i++)
677 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
678 /* configure flex mask*/
679 for (i = 0; i < conf->nb_flexmasks; i++) {
680 pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);
681 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
688 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
689 unsigned char *raw_pkt)
691 struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
693 struct ipv6_hdr *ip6;
694 static const uint8_t next_proto[] = {
695 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
696 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
697 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
698 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
699 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
700 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
701 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
702 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
703 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
704 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
707 switch (fdir_input->flow_type) {
708 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
709 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
710 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
711 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
712 case RTE_ETH_FLOW_FRAG_IPV4:
713 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
715 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
716 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
717 /* set len to by default */
718 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
719 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
721 * The source and destination fields in the transmitted packet
722 * need to be presented in a reversed order with respect
723 * to the expected received packets.
725 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
726 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
727 ip->next_proto_id = next_proto[fdir_input->flow_type];
729 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
730 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
731 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
732 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
733 case RTE_ETH_FLOW_FRAG_IPV6:
734 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
736 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
738 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
740 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
741 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
744 * The source and destination fields in the transmitted packet
745 * need to be presented in a reversed order with respect
746 * to the expected received packets.
748 rte_memcpy(&(ip6->src_addr),
749 &(fdir_input->flow.ipv6_flow.dst_ip),
751 rte_memcpy(&(ip6->dst_addr),
752 &(fdir_input->flow.ipv6_flow.src_ip),
754 ip6->proto = next_proto[fdir_input->flow_type];
757 PMD_DRV_LOG(ERR, "unknown flow type %u.",
758 fdir_input->flow_type);
765 * i40e_fdir_construct_pkt - construct packet based on fields in input
766 * @pf: board private structure
767 * @fdir_input: input set of the flow director entry
768 * @raw_pkt: a packet to be constructed
771 i40e_fdir_construct_pkt(struct i40e_pf *pf,
772 const struct rte_eth_fdir_input *fdir_input,
773 unsigned char *raw_pkt)
775 unsigned char *payload, *ptr;
778 struct sctp_hdr *sctp;
779 uint8_t size, dst = 0;
780 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
782 /* fill the ethernet and IP head */
783 i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
785 /* fill the L4 head */
786 switch (fdir_input->flow_type) {
787 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
788 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
789 sizeof(struct ipv4_hdr));
790 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
792 * The source and destination fields in the transmitted packet
793 * need to be presented in a reversed order with respect
794 * to the expected received packets.
796 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
797 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
798 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
801 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
802 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
803 sizeof(struct ipv4_hdr));
804 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
806 * The source and destination fields in the transmitted packet
807 * need to be presented in a reversed order with respect
808 * to the expected received packets.
810 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
811 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
812 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
815 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
816 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
817 sizeof(struct ipv4_hdr));
818 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
819 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
822 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
823 case RTE_ETH_FLOW_FRAG_IPV4:
824 payload = raw_pkt + sizeof(struct ether_hdr) +
825 sizeof(struct ipv4_hdr);
826 set_idx = I40E_FLXPLD_L3_IDX;
829 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
830 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
831 sizeof(struct ipv6_hdr));
832 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
834 * The source and destination fields in the transmitted packet
835 * need to be presented in a reversed order with respect
836 * to the expected received packets.
838 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
839 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
840 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
843 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
844 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
845 sizeof(struct ipv6_hdr));
846 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
848 * The source and destination fields in the transmitted packet
849 * need to be presented in a reversed order with respect
850 * to the expected received packets.
852 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
853 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
854 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
857 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
858 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
859 sizeof(struct ipv6_hdr));
860 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
861 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
864 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
865 case RTE_ETH_FLOW_FRAG_IPV6:
866 payload = raw_pkt + sizeof(struct ether_hdr) +
867 sizeof(struct ipv6_hdr);
868 set_idx = I40E_FLXPLD_L3_IDX;
871 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
875 /* fill the flexbytes to payload */
876 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
877 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
878 size = pf->fdir.flex_set[pit_idx].size;
881 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
883 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
884 (void)rte_memcpy(ptr,
885 &fdir_input->flow_ext.flexbytes[dst],
886 size * sizeof(uint16_t));
892 /* Construct the tx flags */
893 static inline uint64_t
894 i40e_build_ctob(uint32_t td_cmd,
899 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
900 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
901 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
902 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
903 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
907 * check the programming status descriptor in rx queue.
908 * done after Programming Flow Director is programmed on
912 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
914 volatile union i40e_rx_desc *rxdp;
921 rxdp = &rxq->rx_ring[rxq->rx_tail];
922 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
923 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
924 >> I40E_RXD_QW1_STATUS_SHIFT;
926 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
927 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
928 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
929 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
931 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
932 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
934 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
935 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
937 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
938 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
939 " (FD_ID %u): programming status"
941 rxdp->wb.qword0.hi_dword.fd_id);
943 } else if (error == (0x1 <<
944 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
945 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
946 " (FD_ID %u): programming status"
948 rxdp->wb.qword0.hi_dword.fd_id);
951 PMD_DRV_LOG(ERR, "invalid programming status"
952 " reported, error = %u.", error);
954 PMD_DRV_LOG(ERR, "unknown programming status"
955 " reported, len = %d, id = %u.", len, id);
956 rxdp->wb.qword1.status_error_len = 0;
958 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
965 * i40e_add_del_fdir_filter - add or remove a flow director filter.
966 * @pf: board private structure
967 * @filter: fdir filter entry
968 * @add: 0 - delete, 1 - add
971 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
972 const struct rte_eth_fdir_filter *filter,
975 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
976 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
977 enum i40e_filter_pctype pctype;
980 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
981 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
982 " check the mode in fdir_conf.");
986 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
987 PMD_DRV_LOG(ERR, "invalid flow_type input.");
990 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
991 PMD_DRV_LOG(ERR, "Invalid queue ID");
995 memset(pkt, 0, I40E_FDIR_PKT_LEN);
997 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
999 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1002 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1003 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1005 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1013 * i40e_fdir_filter_programming - Program a flow director filter rule.
1014 * Is done by Flow Director Programming Descriptor followed by packet
1015 * structure that contains the filter fields need to match.
1016 * @pf: board private structure
1018 * @filter: fdir filter entry
1019 * @add: 0 - delelet, 1 - add
1022 i40e_fdir_filter_programming(struct i40e_pf *pf,
1023 enum i40e_filter_pctype pctype,
1024 const struct rte_eth_fdir_filter *filter,
1027 struct i40e_tx_queue *txq = pf->fdir.txq;
1028 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1029 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1030 volatile struct i40e_tx_desc *txdp;
1031 volatile struct i40e_filter_program_desc *fdirdp;
1036 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1037 fdirdp = (volatile struct i40e_filter_program_desc *)
1038 (&(txq->tx_ring[txq->tx_tail]));
1040 fdirdp->qindex_flex_ptype_vsi =
1041 rte_cpu_to_le_32((fdir_action->rx_queue <<
1042 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1043 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1045 fdirdp->qindex_flex_ptype_vsi |=
1046 rte_cpu_to_le_32((fdir_action->flex_off <<
1047 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1048 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1050 fdirdp->qindex_flex_ptype_vsi |=
1051 rte_cpu_to_le_32((pctype <<
1052 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1053 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1055 /* Use LAN VSI Id by default */
1056 fdirdp->qindex_flex_ptype_vsi |=
1057 rte_cpu_to_le_32((pf->main_vsi->vsi_id <<
1058 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1059 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1061 fdirdp->dtype_cmd_cntindex =
1062 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1065 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1066 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1067 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1069 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1070 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1071 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1073 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1074 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1076 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1077 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1078 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1079 I40E_TXD_FLTR_QW1_DEST_MASK);
1081 fdirdp->dtype_cmd_cntindex |=
1082 rte_cpu_to_le_32((fdir_action->report_status<<
1083 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1084 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1086 fdirdp->dtype_cmd_cntindex |=
1087 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1088 fdirdp->dtype_cmd_cntindex |=
1089 rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1090 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1091 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1093 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1095 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1096 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1097 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1098 td_cmd = I40E_TX_DESC_CMD_EOP |
1099 I40E_TX_DESC_CMD_RS |
1100 I40E_TX_DESC_CMD_DUMMY;
1102 txdp->cmd_type_offset_bsz =
1103 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1105 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1106 if (txq->tx_tail >= txq->nb_tx_desc)
1108 /* Update the tx tail register */
1110 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1112 for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1113 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1114 if (txdp->cmd_type_offset_bsz &
1115 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1118 if (i >= I40E_FDIR_WAIT_COUNT) {
1119 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1120 " time out to get DD on tx queue.");
1123 /* totally delay 10 ms to check programming status*/
1124 rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1125 if (i40e_check_fdir_programming_status(rxq) < 0) {
1126 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1127 " programming status reported.");
1135 * i40e_fdir_flush - clear all filters of Flow Director table
1136 * @pf: board private structure
1139 i40e_fdir_flush(struct rte_eth_dev *dev)
1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1144 uint16_t guarant_cnt, best_cnt;
1147 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1148 I40E_WRITE_FLUSH(hw);
1150 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1151 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1152 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1153 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1156 if (i >= I40E_FDIR_FLUSH_RETRY) {
1157 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1160 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1161 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1162 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1163 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1164 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1165 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1166 if (guarant_cnt != 0 || best_cnt != 0) {
1167 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1170 PMD_DRV_LOG(INFO, "FD table Flush success.");
1175 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1176 struct rte_eth_flex_payload_cfg *flex_set,
1179 struct i40e_fdir_flex_pit *flex_pit;
1180 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1181 uint16_t src, dst, size, j, k;
1182 uint8_t i, layer_idx;
1184 for (layer_idx = I40E_FLXPLD_L2_IDX;
1185 layer_idx <= I40E_FLXPLD_L4_IDX;
1187 if (layer_idx == I40E_FLXPLD_L2_IDX)
1188 ptr->type = RTE_ETH_L2_PAYLOAD;
1189 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1190 ptr->type = RTE_ETH_L3_PAYLOAD;
1191 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1192 ptr->type = RTE_ETH_L4_PAYLOAD;
1194 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1195 flex_pit = &pf->fdir.flex_set[layer_idx *
1196 I40E_MAX_FLXPLD_FIED + i];
1197 if (flex_pit->size == 0)
1199 src = flex_pit->src_offset * sizeof(uint16_t);
1200 dst = flex_pit->dst_offset * sizeof(uint16_t);
1201 size = flex_pit->size * sizeof(uint16_t);
1202 for (j = src, k = dst; j < src + size; j++, k++)
1203 ptr->src_offset[k] = j;
1211 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1212 struct rte_eth_fdir_flex_mask *flex_mask,
1215 struct i40e_fdir_flex_mask *mask;
1216 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1219 uint16_t off_bytes, mask_tmp;
1221 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1222 i <= I40E_FILTER_PCTYPE_FRAG_IPV6;
1224 mask = &pf->fdir.flex_mask[i];
1225 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1227 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1228 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1229 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1230 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1231 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1233 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1234 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1237 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1238 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1239 mask_tmp = ~mask->bitmask[j].mask;
1240 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1241 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1243 ptr->flow_type = flow_type;
1250 * i40e_fdir_info_get - get information of Flow Director
1251 * @pf: ethernet device to get info from
1252 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1253 * the flow director information.
1256 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1258 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1259 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1260 uint16_t num_flex_set = 0;
1261 uint16_t num_flex_mask = 0;
1263 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1264 fdir->mode = RTE_FDIR_MODE_PERFECT;
1266 fdir->mode = RTE_FDIR_MODE_NONE;
1269 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1271 (uint32_t)hw->func_caps.fd_filters_best_effort;
1272 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1273 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1274 fdir->flex_payload_unit = sizeof(uint16_t);
1275 fdir->flex_bitmask_unit = sizeof(uint16_t);
1276 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1277 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1278 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1280 i40e_fdir_info_get_flex_set(pf,
1281 fdir->flex_conf.flex_set,
1283 i40e_fdir_info_get_flex_mask(pf,
1284 fdir->flex_conf.flex_mask,
1287 fdir->flex_conf.nb_payloads = num_flex_set;
1288 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1292 * i40e_fdir_stat_get - get statistics of Flow Director
1293 * @pf: ethernet device to get info from
1294 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1295 * the flow director statistics.
1298 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1301 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1304 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1306 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1307 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1309 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1310 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1314 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1315 * @pf: board private structure
1316 * @filter_op:operation will be taken.
1317 * @arg: a pointer to specific structure corresponding to the filter_op
1320 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1321 enum rte_filter_op filter_op,
1324 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1327 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1330 if (filter_op == RTE_ETH_FILTER_NOP)
1333 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1336 switch (filter_op) {
1337 case RTE_ETH_FILTER_ADD:
1338 ret = i40e_add_del_fdir_filter(dev,
1339 (struct rte_eth_fdir_filter *)arg,
1342 case RTE_ETH_FILTER_DELETE:
1343 ret = i40e_add_del_fdir_filter(dev,
1344 (struct rte_eth_fdir_filter *)arg,
1347 case RTE_ETH_FILTER_FLUSH:
1348 ret = i40e_fdir_flush(dev);
1350 case RTE_ETH_FILTER_INFO:
1351 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1353 case RTE_ETH_FILTER_STATS:
1354 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1357 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);